PIC10F220T-I/OTVAO [MICROCHIP]
RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDSO6;
| 型号： | PIC10F220T-I/OTVAO |
| 厂家： | 
MICROCHIP |
| 描述： | RISC Microcontroller, 8-Bit, FLASH, 8MHz, CMOS, PDSO6 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总88页 (文件大小：1367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC10F220/222
Data Sheet
High-Performance Microcontrollers
with 8-Bit A/D
2005-2013 Microchip Technology Inc.
DS40001270F
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2005-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620775912
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
DS40001270F-page 2
2005-2013 Microchip Technology Inc.
PIC10F220/222
6-Pin, 8-Bit Flash Microcontrollers
Device Included In This Data Sheet:
Low-Power Features/CMOS Technology:
• PIC10F220
• PIC10F222
• Operating Current:
- < 175 A @ 2V, 4 MHz
• Standby Current:
High-Performance RISC CPU:
- 100 nA @ 2V, typical
• Low-Power, High-Speed Flash Technology:
- 100,000 Flash endurance
- > 40-year retention
• Only 33 Single-Word Instructions to Learn
• All Single-Cycle Instructions Except for Program
Branches which are Two-Cycle
• Fully Static Design
• 12-bit Wide Instructions
• Wide Operating Voltage Range: 2.0V to 5.5V
• Wide Temperature Range:
- Industrial: -40C to +85C
- Extended: -40C to +125C
• 2-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
for Data and Instructions
• 8-bit Wide Data Path
• 8 Special Function Hardware Registers
• Operating Speed:
Peripheral Features:
- 500 ns instruction cycle with 8 MHz internal
clock
• 4 I/O Pins:
- 3 I/O pins with individual direction control
- 1 input only pin
- 1 s instruction cycle with 4 MHz internal
clock
- High current sink/source for direct LED drive
- Wake-on-change
Special Microcontroller Features:
- Weak pull-ups
• 4 or 8 MHz Precision Internal Oscillator:
- Factory calibrated to ±1%
• 8-bit Real-Time Clock/Counter (TMR0) with 8-bit
Programmable Prescaler
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Debugging (ICD) Support
• Power-On Reset (POR)
• Analog-to-Digital (A/D) Converter:
- 8-bit resolution
- 2 external input channels
- 1 internal input channel dedicated
• Short Device Reset Timer, DRT (1.125 ms typical)
• Watchdog Timer (WDT) with Dedicated On-Chip
RC Oscillator for Reliable Operation
• Programmable Code Protection
• Multiplexed MCLR Input Pin
• Internal Weak Pull-Ups on I/O Pins
• Power-Saving Sleep mode
• Wake-up from Sleep on Pin Change
Program Memory
Flash (words)
Data Memory
Timers
8-bit
Device
I/O
8-Bit A/D (ch)
SRAM (bytes)
PIC10F220
PIC10F222
256
512
16
23
4
4
1
1
2
2
2005-2013 Microchip Technology Inc.
DS40001270F-page 1
PIC10F220/222
6-Lead SOT-23 Pin Diagram
1
2
6
5
GP0/AN0/ICSPDAT
GP3/MCLR/VPP
VDD
VSS
3
4
GP1/AN1/ICSPCLK
GP2/T0CKI/FOSC4
8-Lead DIP Pin Diagram
GP3/MCLR/VPP
VSS
1
N/C
VDD
8
7
6
5
2
3
4
N/C
GP2/T0CKI/FOSC4
GP1/AN1/ICSPCLK
GP0/AN0/ICSPDAT
8-Lead DFN Pin Diagram
N/C
VDD
8
1
GP3/MCLR/VPP
VSS
7
6
5
2
3
4
GP2/T0CKI/FOSC4
GP1/AN1/ICSPCLK
N/C
GP0/AN0/ICSPDAT
DS40001270F-page 2
2005-2013 Microchip Technology Inc.
PIC10F220/222
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 Device Varieties .......................................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 13
5.0 I/O Port....................................................................................................................................................................................... 21
6.0 TMR0 Module and TMR0 Register............................................................................................................................................. 25
7.0 Analog-to-Digital (A/D) converter ............................................................................................................................................... 29
8.0 Special Features Of The CPU.................................................................................................................................................... 33
9.0 Instruction Set Summary............................................................................................................................................................ 43
10.0 Electrical Characteristics............................................................................................................................................................ 51
11.0 Development Support................................................................................................................................................................. 61
12.0 DC and AC Characteristics Graphs and Charts......................................................................................................................... 69
13.0 Packaging Information................................................................................................................................................................ 73
Index .................................................................................................................................................................................................... 81
The Microchip Web Site....................................................................................................................................................................... 83
Customer Change Notification Service ................................................................................................................................................ 83
Customer Support................................................................................................................................................................................ 83
Product Identification System .............................................................................................................................................................. 85
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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2005-2013 Microchip Technology Inc.
DS40001270F-page 3
PIC10F220/222
NOTES:
DS40001270F-page 4
2005-2013 Microchip Technology Inc.
PIC10F220/222
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC10F220/222 devices fit in applications ranging
from personal care appliances and security systems to
low-power remote transmitters/receivers. The Flash
technology makes customizing application programs
(transmitter codes, appliance settings, receiver fre-
quencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make these microcontrollers well suited for
applications with space limitations. Low-cost, low-
power, high-performance, ease-of-use and I/O flexibil-
ity make the PIC10F220/222 devices very versatile,
even in areas where no microcontroller use has been
considered before (e.g., timer functions, logic and
PLDs in larger systems and coprocessor applications).
The PIC10F220/222 devices from Microchip
Technology are low-cost, high-performance, 8-bit, fully-
static Flash-based CMOS microcontrollers. They
employ a RISC architecture with only 33 single-word/
single-cycle instructions. All instructions are single-
cycle (1 s) except for program branches, which take
two cycles. The PIC10F220/222 devices deliver perfor-
mance in an order of magnitude higher than their com-
petitors in the same price category. The 12-bit wide
instructions are highly symmetrical, resulting in a
typical 2:1 code compression over other 8-bit
microcontrollers in its class. The easy-to-use and easy
to remember instruction set reduces development time
significantly.
The PIC10F220/222 products are equipped with spe-
cial features that reduce system cost and power
requirements. The Power-on Reset (POR) and Device
Reset Timer (DRT) eliminates the need for the external
Reset circuitry. INTOSC Internal Oscillator mode is pro-
vided, thereby, preserving the limited number of I/O
available. Power-Saving Sleep mode, Watchdog Timer
and code protection features improve system cost,
power and reliability.
The PIC10F220/222 devices are available in cost-
effective Flash, which is suitable for production in any
volume. The customer can take full advantage of
Microchip’s price leadership in Flash programmable
microcontrollers while benefiting from the Flash
programmable flexibility.
The PIC10F220/222 products are supported by a full-
featured macro assembler, a software simulator, an in-
circuit debugger,
a
‘C’ compiler,
a
low-cost
development programmer and a full featured program-
mer. All the tools are supported on IBM® PC and
compatible machines.
TABLE 1-1:
PIC10F220/222 DEVICES(1), (2)
PIC10F220
PIC10F222
Clock
Maximum Frequency of Operation (MHz)
Flash Program Memory
Data Memory (bytes)
Timer Module(s)
8
256
16
8
512
23
Memory
Peripherals
Features
TMR0
Yes
2
TMR0
Yes
2
Wake-up from Sleep on pin change
Analog inputs
I/O Pins
3
3
Input Only Pins
1
1
Internal Pull-ups
Yes
Yes
33
Yes
Yes
33
In-Circuit Serial Programming™
Number of instructions
Packages
6-pin SOT-23,
8-pin DIP, DFN
6-pin SOT-23,
8-pin DIP, DFN
Note 1: The PIC10F220/222 devices have Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O
current capability and precision internal oscillator.
2: The PIC10F220/222 devices use serial programming with data pin GP0 and clock pin GP1.
2005-2013 Microchip Technology Inc.
DS40001270F-page 5
PIC10F220/222
NOTES:
DS40001270F-page 6
2005-2013 Microchip Technology Inc.
PIC10F220/222
2.0
DEVICE VARIETIES
A variety of packaging options are available. Depend-
ing on application and production requirements, the
proper device option can be selected using the
information in this section. When placing orders, please
use the PIC10F220/222 Product Identification System
at the back of this data sheet to specify the correct part
number.
2.1
Quick Turn Programming (QTP)
Devices
Microchip offers a QTP programming service for
factory production orders. This service is made
available for users who choose not to program
medium-to-high quantity units and whose code
patterns have stabilized. The devices are identical to
the Flash devices but with all Flash locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please
contact your local Microchip Technology sales office for
more details.
2.2
Serialized Quick Turn
ProgrammingSM (SQTPSM) Devices
Microchip offers a unique programming service, where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
2005-2013 Microchip Technology Inc.
DS40001270F-page 7
PIC10F220/222
NOTES:
DS40001270F-page 8
2005-2013 Microchip Technology Inc.
PIC10F220/222
The PIC10F220/222 devices contain an 8-bit ALU and
working register. The ALU is a general purpose arith-
metic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC10F220/222 devices
can be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC10F220/222 devices use a Harvard archi-
tecture in which program and data are accessed on
separate buses. This improves bandwidth over tradi-
tional von Neumann architectures where program and
data are fetched on the same bus. Separating program
and data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12 bits wide, making it possible to have all
single-word instructions. A 12-bit wide program mem-
ory access bus fetches a 12-bit instruction in a single
cycle. A two-stage pipeline overlaps fetch and execu-
tion of instructions. Consequently, all instructions (33)
execute in a single cycle (1 s @ 4 MHz or 500 ns @
8 MHz) except for program branches.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two’s comple-
ment in nature. In two-operand instructions, one oper-
and is typically the W (working) register. The other
operand is either a file register or an immediate
constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC) and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
The table below lists program memory (Flash) and data
memory (RAM) for the PIC10F220/222 devices.
Memory
Device
A simplified block diagram is shown in Figure 3-1 with
the corresponding device pins described in Table 3-1.
Program
Data
PIC10F220
PIC10F222
256 x 12
512 x 12
16 x 8
23 x 8
The PIC10F220/222 devices can directly or indirectly
address its register files and data memory. All Special
Function Registers (SFR), including the PC, are
mapped in the data memory. The PIC10F220/222
devices have a highly orthogonal (symmetrical) instruc-
tion set that makes it possible to carry out any opera-
tion, on any register, using any addressing mode. This
symmetrical nature and lack of “special optimal situa-
tions” make programming with the PIC10F220/222
devices simple, yet efficient. In addition, the learning
curve is reduced significantly.
2005-2013 Microchip Technology Inc.
DS40001270F-page 9
PIC10F220/222
FIGURE 3-1:
BLOCK DIAGRAM
9-10
8
GPIO
Data Bus
Program Counter
Flash
512 x 12 or
256 x 12
Program
Memory
GP0/AN0/ICSPDAT
GP1/AN1/ICSPCLK
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
RAM
23 or 16
bytes
STACK1
STACK2
File
Registers
Program
Bus
12
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
5
Direct Addr
5-7
FSR Reg
STATUS Reg
8
3
MUX
Device Reset
Timer
Instruction
Decode &
Control
Power-on
Reset
ALU
AN0
AN1
8
Watchdog
Timer
ADC
Timing
Generation
W Reg
Internal RC
Clock
Timer0
Absolute
Voltage
MCLR
VDD, VSS
Reference
TABLE 3-1:
PINOUT DESCRIPTION
Input
Function
Output
Type
Name
Description
Type
GP0/AN0/ICSPDAT
GP0
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
AN0
ICSPDAT
GP1
AN
ST
—
Analog Input
CMOS In-Circuit programming data
GP1/AN1/ICSPCLK
TTL
CMOS Bidirectional I/O pin. Can be software programmed for internal weak
pull-up and wake-up from Sleep on pin change.
AN1
ICSPCLK
GP2
AN
ST
—
—
Analog Input
In-Circuit programming clock
GP2/T0CKI/FOSC4
GP3/MCLR/VPP
TTL
ST
CMOS Bidirectional I/O pin
Clock input to TMR0
CMOS Oscillator/4 output
T0CKI
FOSC4
GP3
—
—
TTL
—
Input pin. Can be software programmed for internal weak pull-up and
wake-up from Sleep on pin change.
MCLR
ST
—
Master Clear (Reset). When configured as MCLR, this pin is an
active-low Reset to the device. Voltage on MCLR/VPP must not
exceed VDD during normal device operation or the device will enter
Programming mode.
VPP
VDD
VSS
HV
P
—
—
—
Programming voltage input
VDD
VSS
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
P
Legend:
I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input,
ST = Schmitt Trigger input, AN = Analog Input
DS40001270F-page 10
2005-2013 Microchip Technology Inc.
PIC10F220/222
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the PC to change (e.g., GOTO) then two cycles
are required to complete the instruction (Example 3-1).
The clock is internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. Internally, the PC is incremented every Q1,
and the instruction is fetched from program memory
and latched into the Instruction Register (IR) in Q4. It is
decoded and executed during Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
A fetch cycle begins with the PC incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC + 1
PC + 2
Fetch INST (PC)
Execute INST (PC - 1)
Fetch INST (PC + 1)
Execute INST (PC)
Fetch INST (PC + 2)
Execute INST (PC + 1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
2. MOVWF GPIO
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
GPIO, BIT1
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
2005-2013 Microchip Technology Inc.
DS40001270F-page 11
PIC10F220/222
NOTES:
DS40001270F-page 12
2005-2013 Microchip Technology Inc.
PIC10F220/222
4.2
Program Memory Organization for
the PIC10F222
4.0
MEMORY ORGANIZATION
The PIC10F220/222 memories are organized into pro-
gram memory and data memory. Data memory banks
are accessed using the File Select Register (FSR).
The PIC10F222 devices have a 10-bit Program
Counter (PC) capable of addressing a 1024 x 12
program memory space.
4.1
Program Memory Organization for
the PIC10F220
Only the first 512 x 12 (0000h-01FFh) for the Mem-
High are physically implemented (see Figure 4-2).
Accessing a location above these boundaries will
cause a wrap-around within the first 512 x 12 space
(PIC10F222). The effective Reset vector is at 0000h,
(see Figure 4-2). Location 01FFh (PIC10F222) con-
tains the internal clock oscillator calibration value.
This value should never be overwritten.
The PIC10F220 devices have a 9-bit Program Counter
(PC) capable of addressing a 512 x 12 program
memory space.
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F220 are physically implemented (see
Figure 4-1). Accessing
a location above these
boundaries will cause a wrap-around within the first
256 x 12 space (PIC10F220). The effective Reset
vector is at 0000h, (see Figure 4-1). Location 00FFh
(PIC10F220) contains the internal clock oscillator
calibration value. This value should never be
overwritten.
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F222
<9:0>
PC<8:0>
10
CALL, RETLW
Stack Level 1
Stack Level 2
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC10F220
(1)
Reset Vector
0000h
<8:0>
PC<7:0>
9
CALL, RETLW
On-chip Program
Memory
Stack Level 1
Stack Level 2
(1)
Reset Vector
0000h
On-chip Program
Memory
512 Words
01FFh
0200h
02FFh
256 Word
00FFh
0100h
Note 1: Address 0000h becomes the effective
Reset vector. Location 01FFh contains the
MOVLW XXinternal oscillator calibration
value.
01FFh
Note 1: Address 0000h becomes the
effective Reset vector. Location 00FFh
contains the MOVLW XXinternal oscillator
calibration value.
2005-2013 Microchip Technology Inc.
DS40001270F-page 13
PIC10F220/222
FIGURE 4-4:
PIC10F222 REGISTER
FILE MAP
4.3
Data Memory Organization
Data memory is composed of registers or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers (SFR)
and General Purpose Registers (GPR).
File Address
(1)
INDF
00h
01h
02h
03h
04h
05h
06h
07h
TMR0
PCL
The Special Function Registers include the TMR0 reg-
ister, the Program Counter (PCL), the STATUS register,
the I/O register (GPIO) and the File Select Register
(FSR). In addition, Special Function Registers are used
to control the I/O port configuration and prescaler
options.
STATUS
FSR
OSCCAL
GPIO
ADCON0
ADRES
The General Purpose Registers are used for data and
control information under command of the instructions.
08h
09h
For the PIC10F220, the register file is composed of 9
Special Function Registers and 16 General Purpose
Registers (Figure 4-3, Figure 4-4).
General
Purpose
Registers
For the PIC10F222, the register file is composed of 9
Special Function Registers and 23 General Purpose
Registers (Figure 4-4).
1Fh
4.3.1
GENERAL PURPOSE REGISTER
FILE
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing; INDF and
FSR Registers”.
The General Purpose Register file is accessed, either
directly or indirectly, through the File Select Register
(FSR). See Section 4.9 “Indirect Data Addressing;
INDF and FSR Registers”.
4.3.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control the
operation of the device (Table 4-1).
FIGURE 4-3:
PIC10F220 REGISTER
FILE MAP
File Address
The Special Function Registers can be classified into
two sets. The Special Function Registers associated
with the “core” functions are described in this section.
Those related to the operation of the peripheral
features are described in the section for each
peripheral feature.
(1)
INDF
00h
01h
02h
03h
04h
05h
06h
07h
TMR0
PCL
STATUS
FSR
OSCCAL
GPIO
ADCON0
ADRES
08h
09h
(2)
Unimplemented
0Fh
10h
General
Purpose
Registers
1Fh
Note 1: Not a physical register. See Section 4.9
“Indirect Data Addressing; INDF and
FSR Registers”.
2: Unimplemented, read as 00h.
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TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Power-On
Reset
Page #
(2)
00h
01h
02h
INDF
Uses contents of FSR to address data memory (not a physical register)
8-Bit Real-Time Clock/Counter
xxxx xxxx
xxxx xxxx
1111 1111
20
25
19
TMR0
(1)
PCL
Low Order 8 Bits of PC
(3)
03h
04h
05h
06h
STATUS
FSR
GPWUF
—
—
TO
PD
Z
DC
C
0--1 1xxx
111x xxxx
1111 1110
---- xxxx
15
20
18
21
Indirect Data Memory Address Pointer
OSCCAL
GPIO
CAL6
—
CAL5
—
CAL4
—
CAL3
—
CAL2
GP3
CAL1
GP2
CAL0
GP1
FOSC4
GP0
07h
08h
N/A
ADCON0
ADRES
ANS1
ANS0
—
—
CHS1
CHS0 GO/DONE ADON
11-- 1100
xxxx xxxx
---- 1111
30
31
23
Result of Analog-to-Digital Conversion
TRISGPIO
OPTION
—
—
—
—
I/O Control Register
PSA PS2
N/A
GPWU GPPU
T0CS
T0SE
PS1
PS0
1111 1111
17
Legend:
– = unimplemented, read as ‘0’, x= unknown, u= unchanged, q= value depends on condition.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.7 “Program Counter” for an
explanation of how to access these bits.
2: Other (non Power-up) Resets include external Reset through MCLR, Watchdog Timer and wake-up on pin change
Reset.
3: See Table 8-1 for other Reset specific values.
4.4
STATUS Register
This register contains the arithmetic status of the ALU,
the Reset status and the page preselect bit.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
Therefore, it is recommended that only BCF, BSF and
MOVWFinstructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, DC or C bits
from the STATUS register. For other instructions, which
do affect Status bits, see Instruction Set Summary.
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REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h)
R/W-0
GPWUF
bit 7
R/W-0
—
R/W-0
—
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GPWUF: GPIO Reset bit
1= Reset due to wake-up from Sleep on pin change
0= After power-up or other Reset
bit 6
bit 5
bit 4
Reserved: Do not use. Use of this bit may affect upward compatibility with future products.
Reserved: Do not use. Use of this bit may affect upward compatibility with future products.
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF:
1= A carry to the 4th low-order bit of the result occurred
0= A carry to the 4th low-order bit of the result did not occur
SUBWF:
1= A borrow from the 4th low-order bit of the result did not occur
0= A borrow from the 4th low-order bit of the result occurred
bit 0
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF:
SUBWF:
RRFor RLF:
1= A carry occurred
1= A borrow did not occur Load bit with LSb or MSb, respectively
0= A carry did not occur 0= A borrow occurred
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4.5
OPTION Register
Note:
Note:
If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin (i.e., note that TRIS overrides
Option control of GPPU and GPWU).
The OPTION register is a 8-bit wide, write-only register,
which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
The OPTION register is not memory mapped and is
therefore only addressable by executing the OPTION
instruction, the contents of the W register will be trans-
ferred to the OPTION register. A Reset sets the
OPTION<7:0> bits.
If the T0CS bit is set to ‘1’, it will override
the TRIS function on the T0CKI pin.
REGISTER 4-2:
OPTION REGISTER
W-1
GPWU
bit 7
W-1
GPPU
W-1
W-1
W-1
PSA
W-1
PS2
W-1
PS1
W-1
PS0
T0CS
T0SE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPWU: Enable Wake-up On Pin Change bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
GPPU: Enable Weak Pull-ups bit (GP0, GP1, GP3)
1= Disabled
0= Enabled
T0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin (overrides TRIS on the T0CKI pin)
0= Transition on internal instruction cycle clock, FOSC/4
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on the T0CKI pin
0= Increment on low-to-high transition on the T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
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4.6
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal precision 4/8 MHz oscillator. It
contains seven bits for calibration.
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
After you move in the calibration constant, do not
change the value. See Section 8.2.2 “Internal 4/8 MHz
Oscillator”.
REGISTER 4-3:
OSCCAL – OSCILLATOR CALIBRATION REGISTER (ADDRESS: 05h)
R/W-1
CAL6
R/W-1
CAL5
R/W-1
CAL4
R/W-1
CAL3
R/W-1
CAL2
R/W-1
CAL1
R/W-1
CAL0
R/W-0
FOSC4
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-1
CAL<6:0>: Oscillator Calibration bits
0111111= Maximum frequency
•
•
•
0000001
0000000= Center frequency
1111111
•
•
•
1000000= Minimum frequency
bit 0
FOSC4: INTOSC/4 Output Enable bit(1)
1= INTOSC/4 output onto GP2
0= GP2/T0CKI applied to GP2
Note 1: Overrides GP2/T0CKI control registers when enabled.
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4.7.1
EFFECTS OF RESET
4.7
Program Counter
The PC is set upon a Reset, which means that the PC
addresses the last location in program memory (i.e.,
the oscillator calibration instruction). After executing
MOVLW XX, the PC will roll over to location 0000h and
begin executing user code.
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>.
4.8
Stack
The PIC10F220 device has a 2-deep, 8-bit wide
hardware PUSH/POP stack.
For a CALLinstruction or any instruction where the PCL
is the destination, bits 7:0 of the PC again are provided
by the instruction word. However, PC<8> does not
come from the instruction word, but is always cleared
(Figure 4-5).
The PIC10F222 device has a 2-deep, 9-bit wide
hardware PUSH/POP stack.
A CALLinstruction will PUSH the current value of stack
1 into stack 2 and then PUSH the current PC value,
incremented by one, into stack level 1. If more than two
sequential CALL’s are executed, only the most recent
two return addresses are stored.
Instructions where the PCL is the destination or Modify
PCL instructions, include MOVWF PC, ADDWF PCand
BSF PC, 5.
Note:
Because PC<8> is cleared in the CALL
instruction or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any
program memory page (512 words long).
A RETLWinstruction will POP the contents of stack level
1 into the PC and then copy stack level 2 contents into
level 1. If more than two sequential RETLW’s are exe-
cuted, the stack will be filled with the address
previously stored in level 2.
Note 1: The W register will be loaded with the lit-
eral value specified in the instruction. This
is particularly useful for the implementa-
tion of data look-up tables within the
program memory.
FIGURE 4-5:
LOADING OF PC
BRANCH INSTRUCTIONS
GOTOInstruction
8 7
0
2: There are no Status bits to indicate stack
PC
PCL
overflows or stack underflow conditions.
3: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLWinstructions.
Instruction Word
CALLor Modify PCLInstruction
8 7
0
PC
PCL
Instruction Word
Reset to ‘0’
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EXAMPLE 4-1:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
4.9
Indirect Data Addressing; INDF
and FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
MOVLW
MOVWF
0x10
;initialize pointer
;to RAM
FSR
NEXT
CLRF
INDF
;clear INDF
;register
INCF
BTFSC
GOTO
FSR,F
FSR,4
NEXT
;inc pointer
;all done?
;NO, clear next
4.9.1
INDIRECT ADDRESSING
• Register file 09 contains the value 10h
• Register file 0A contains the value 0Ah
• Load the value 09 into the FSR register
CONTINUE
:
:
;YES, continue
• A read of the INDF register will return the value
of 10h
The FSR is a 5-bit wide register. It is used in conjunc-
tion with the INDF register to indirectly address the data
memory area.
• Increment the value of the FSR register by one
(FSR = 0A)
• A read of the INDR register now will return the
value of 0Ah.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although Status bits may be affected).
Note:
Do not use banking. FSR <7:5> are
unimplemented and read as ‘1’s.
A simple program to clear RAM locations 10h-1Fh
using Indirect addressing is shown in Example 4-1.
FIGURE 4-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
4
(opcode)
0
(FSR)
0
4
Location Select
Location Select
00h
Data
Memory
0Fh
10h
(1)
1Fh
Bank 0
Note 1: For register map detail, see Section 4.3 “Data Memory Organization”.
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The TRIS registers are “write-only” and are set (output
drivers disabled) upon Reset.
5.0
I/O PORT
As with any other register, the I/O register(s) can be
written and read under program control. However, read
instructions (e.g., MOVF GPIO, W) always read the I/O
pins independent of the pin’s Input/Output modes. On
Reset, all I/O ports are defined as input (inputs are at
high-impedance) since the I/O control registers are all
set.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except GP3, which is input
only, may be used for both input and output operations.
For input operations, these ports are non-latching. Any
input must be present until read by an input instruction
(e.g., MOVF GPIO, W). The outputs are latched and
remain unchanged until the output latch is rewritten. To
use a port pin as output, the corresponding direction
control bit in TRIS must be cleared (= 0). For use as an
input, the corresponding TRIS bit must be set. Any I/O
pin (except GP3) can be programmed individually as
input or output.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low-order 4 bits
are used (GP<3:0>). Bits 7 through 4 are unimple-
mented and read as ‘0’s. Please note that GP3 is an
input only pin. Pins GP0, GP1 and GP3 can be config-
ured with weak pull-ups and also for wake-up on
change. The wake-up on change and weak pull-up
functions are not individually pin selectable. If GP3/
MCLR is configured as MCLR, a weak pull-up can be
enabled via the Configuration Word. Configuring GP3
as MCLR disables the wake-up on change function for
this pin.
FIGURE 5-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
VDD
P
VDD
(1)
WR
Port
Latch
5.2
TRIS Registers
CK
The Output Driver Control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A ‘1’ from a TRIS register bit puts the corre-
sponding output driver in a High-Impedance mode. A
‘0’ puts the contents of the output data latch on the
selected pins, enabling the output buffer. The excep-
tions are GP3, which is input only, and the GP2/T0CKI/
FOSC4 pin, which may be controlled by various
registers. See Table 5-1.
N
I/O
pin
W
Reg
D
Q
Q
TRIS
Latch
VSS VSS
TRIS ‘f’
CK
Reset
(2)
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and
VSS.
2: See Table 3-1 for buffer type.
TABLE 5-1:
ORDER OF PRECEDENCE FOR PIN FUNCTIONS
Priority
GP0
GP1
GP2
GP3
1
2
3
AN0
TRIS GPIO
—
AN1
TRIS GPIO
—
FOSC4
T0CKI
MCLR
—
TRIS GPIO
—
TABLE 5-2:
REQUIREMENTS TO MAKE PINS AVAILABLE IN DIGITAL MODE
Bit
GP0
GP1
GP2
GP3
FOSC4
T0CS
—
—
—
0
—
—
0
0
0
—
—
—
—
0
ANS1
—
—
—
ANS0
—
—
MCLRE
—
Legend:
— = Condition of bit will have no effect on the setting of the pin to Digital mode.
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FIGURE 5-2:
BLOCK DIAGRAM OF GP0
FIGURE 5-3:
BLOCK DIAGRAM OF GP2
AND GP1
(1)
Data
Bus
D
I/O Pin
Q
Q
GPPU
Data
Latch
WR
Port
FOSC4
CK
OSCCAL<0>
Data
W
Reg
Bus
D
Q
Q
D
Q
Q
Data
Latch
TRIS
Latch
(1)
I/O Pin
WR
Port
TRIS ‘f’
CK
CK
W
Reg
Reset
T0CS
D
Q
Q
TRIS
Latch
TRIS ‘f’
CK
RD Port
Reset
T0CKI
Analog Enable
Note 1: I/O pins have protection diodes to VDD and
VSS.
RD Port
FIGURE 5-4:
BLOCK DIAGRAM OF GP3
Q
D
GPPU
CK
MCLRE
Reset
Mis-Match
(1)
ADC
I/O Pin
Note 1: I/O pins have protection diodes to VDD and
VSS.
Data Bus
RD Port
Q
D
CK
Mis-match
Note 1: GP3/MCLR pin has a protection diode to VSS
only.
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TABLE 5-3:
SUMMARY OF PORT REGISTERS
Value on
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Power-On
Reset
All Other Resets
N/A
TRISGPIO
—
—
—
—
I/O Control Registers
---- 1111
---- 1111
1111 1111
N/A
OPTION
STATUS
GPIO
GPWU
GPWUF
—
GPPU T0CS T0SE PSA
PS2
Z
PS1 PS0 1111 1111
(1)
03h
—
—
—
—
TO
—
PD
DC
C
0001 1xxx
q00q quuu
06h
GP3
GP2 GP1 GP0 ---- xxxx
---- uuuu
Legend:
Shaded cells not used by PORT registers, read as ‘0’, – = unimplemented, read as ‘0’, x= unknown, u= unchanged,
q= depends on condition.
Note 1: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.
EXAMPLE 5-1:
I/O PORT READ-MODIFY-
WRITE INSTRUCTIONS
5.4
I/O Programming Considerations
5.4.1
BIDIRECTIONAL I/O PORTS
;Initial GPIO Settings
;GPIO<3:2> Inputs
;GPIO<1:0> Outputs
;
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit 2 of GPIO will cause
all eight bits of GPIO to be read into the CPU, bit 2 to
be set and the GPIO value to be written to the output
latches. If another bit of GPIO is used as a bidirectional
I/O pin (say bit 0) and it is defined as an input at this
time, the input signal present on the pin itself would be
read into the CPU and rewritten to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
;
;
GPIO latch
GPIO pins
----------
---- pp11
---- pp11
----------
GPIO, 1 ;---- pp01
GPIO, 0 ;---- pp10
BCF
BCF
MOVLW 007h;
TRIS
GPIO
;---- pp10
---- pp11
;
Note:
The user may have expected the pin values to
be ---- pp00. The second BCFcaused GP1
to be latched as the pin value (High).
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-5).
Therefore, care must be exercised if a write followed by
a read operation is carried out on the same I/O port. The
sequence of instructions should allow the pin voltage to
stabilize (load dependent) before the next instruction
causes that file to be read into the CPU. Otherwise, the
previous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to separate
these instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
Read-Modify-Write instructions (e.g., BCF, BSF, etc.)
on an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-5:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC + 3
PC
PC + 1
PC + 2
This example shows a write to GPIO followed
by a read from GPIO.
Instruction
Fetched
MOVWFGPIO
MOVFGPIO, W
NOP
NOP
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle
TPD = propagation delay
GP<2:0>
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
Executed
MOVWF GPIO
(Write to GPIO)
MOVF GPIO,W
(Read GPIO)
NOP
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Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge. Restric-
tions on the external clock input are discussed in detail
in Section 6.1 “Using Timer0 With An External
Clock”.
6.0
TMR0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select:
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit will
assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, 1:256
are selectable. Section 6.2 “Prescaler” details the
operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
Data Bus
GP2/T0CKI
Pin
FOSC/4
0
1
PSOUT
8
1
0
Sync with
Internal
Clocks
TMR0 Reg
Programmable
PSOUT
Sync
(2)
Prescaler
(2 TCY delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
FIGURE 6-2:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
Instruction
Fetch
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
NT0 + 1
T0
T0 + 1
T0 + 2
NT0
NT0 + 2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
2005-2013 Microchip Technology Inc.
DS40001270F-page 25
PIC10F220/222
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Instruction
Fetch
T0
T0 + 1
NT0
NT0 + 1
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-On
Reset
Value on
All Other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 – 8-Bit Real-Time Clock/Counter
GPWU GPPU T0CS T0SE PSA
xxxx xxxx
1111 1111
---- 1111
uuuu uuuu
1111 1111
---- 1111
N/A
OPTION
TRISGPIO
PS2
PS1
PS0
(1)
N/A
—
—
I/O Control Register
—
—
Legend:
Shaded cells not used by Timer0, – = unimplemented, x = unknown, u= unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
6.1
Using Timer0 With An External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 2Tt0H) and low
for at least 2TOSC (and a small RC delay of 2Tt0H).
Refer to the electrical specification of the desired
device.
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4TOSC (and a small RC delay of 4Tt0H) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
DS40001270F-page 26
2005-2013 Microchip Technology Inc.
PIC10F220/222
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 6-4 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 6-4:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler Output(2)
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
6.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (see Section 8.6 “Watch-
dog Timer (WDT)”). For simplicity, this counter is
being referred to as “prescaler” throughout this data
sheet.
Note:
The prescaler may be used by either the
Timer0 module or the WDT, but not both.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the WDT and vice-versa.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDTinstruction will clear
the prescaler along with the WDT. The prescaler is
neither readable nor writable. On a Reset, the
prescaler contains all ‘0’s.
2005-2013 Microchip Technology Inc.
DS40001270F-page 27
PIC10F220/222
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT instruction should be executed before
switching the prescaler.
6.2.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during pro-
gram execution). To avoid an unintended device Reset,
the following instruction sequence (Example 6-1) must
be executed when changing the prescaler assignment
from Timer0 to the WDT.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
;Clear WDT and
;prescaler
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 WDT)
;Clear WDT
;Clear TMR0 & Prescaler
MOVLW ‘xxxx0xxx’ ;Select TMR0, new
;prescale value and
;clock source
CLRWDT
CLRF
TMR0
OPTION
MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)
OPTION
;are required only if
;desired
CLRWDT
;PS<2:0> are 000 or 001
MOVLW ‘00xx1xxx’b;Set Postscaler to
OPTION
;desired WDT rate
FIGURE 6-5:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY (= FOSC/4)
Data Bus
8
0
1
GP2/T0CKI(2)
Pin
M
U
X
1
0
M
U
X
Sync
2
Cycles
TMR0 Reg
T0SE(1)
T0CS(1)
PSA(1)
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
PS<2:0>(1)
8-to-1 MUX
PSA(1)
1
0
WDT Enable bit
MUX
PSA(1)
WDT
Time-Out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2: T0CKI is shared with pin GP2 on the PIC10F220/222.
DS40001270F-page 28
2005-2013 Microchip Technology Inc.
PIC10F220/222
7.0
ANALOG-TO-DIGITAL (A/D)
CONVERTER
Note:
The A/D Converter module consumes
power when the ADON bit is set even
when no channels are selected as analog
inputs. For low-power applications, it is
recommended that the ADON bit be
cleared when the A/D Converter is not in
use.
The A/D converter allows conversion of an analog
signal into an 8-bit digital signal.
7.1
Clock Divisors
The A/D Converter has a single clock source setting,
INTOSC/4. The A/D Converter requires 13 TAD periods
to complete a conversion. The divisor values do not
affect the number of TAD periods required to perform a
conversion. The divisor values determine the length of
the TAD period.
7.5
The GO/DONE bit
The GO/DONE bit is used to determine the status of a
conversion, to start a conversion and to manually halt a
conversion in process. Setting the GO/DONE bit starts
a conversion. When the conversion is complete, the A/
D Converter module clears the GO/DONE bit. A con-
version can be terminated by manually clearing the
GO/DONE bit while a conversion is in process. Manual
termination of a conversion may result in a partially
converted result in ADRES.
Note:
Due to the fixed clock divisor, a conversion
will complete in 13 CPU instruction cycles.
7.2
Voltage Reference
Due to the nature of the design, there is no external
voltage reference allowed for the A/D Converter.
The A/D Converter reference voltage will always be
VDD.
The GO/DONE bit is cleared when the device enters
Sleep, stopping the current conversion. The A/D Con-
verter does not have a dedicated oscillator, it runs off of
the system clock.
7.3
Analog Mode Selection
The GO/DONE bit cannot be set when ADON is clear.
The ANS<1:0> bits are used to configure pins for ana-
log input. Upon any Reset ANS<1:0> defaults to 11.
This configures pins AN0 and AN1 as analog inputs.
Pins configured as analog inputs are not available for
digital output. Users should not change the ANS bits
while a conversion is in process. ANS bits are active
regardless of the condition of ADON.
7.6
Sleep
This A/D Converter does not have a dedicated A/D
Converter clock and therefore no conversion in Sleep
is possible. If a conversion is underway and a Sleep
command is executed, the GO/DONE and ADON bit
will be cleared. This will stop any conversion in process
and power-down the A/D Converter module to con-
serve power. Due to the nature of the conversion pro-
cess, the ADRES may contain a partial conversion. At
least 1 bit must have been converted prior to Sleep to
have partial conversion data in ADRES. The CHS bits
are reset to their default condition and CHS<1:0> = 11.
7.4
A/D Converter Channel Selection
The CHS bits are used to select the analog channel to
be sampled by the A/D Converter. The CHS bits
should not be changed during a conversion. To
acquire an analog signal, the CHS selection must
match one of the pin(s) selected by the ANS bits. The
Internal Absolute Voltage Reference can be selected
regardless of the condition of the ANS bits. All channel
selection information will be lost when the device
enters Sleep.
For accurate conversions, TAD must meet the following:
• 500 ns < TAD < 50 s
• TAD = 1/(FOSC/divisor)
TABLE 7-1:
EFFECTS OF SLEEP AND WAKE ON ADCON0
ANS1
ANS0
CHS1
CHS0
GO/DONE
ADON
Prior to Sleep
Prior to Sleep
Entering Sleep
Wake
x
x
x
x
1
1
x
x
1
1
0
1
0
0
0
1
0
0
x
Unchanged
1
x
Unchanged
1
2005-2013 Microchip Technology Inc.
DS40001270F-page 29
PIC10F220/222
7.7
Analog Conversion Result
Register
7.8
Internal Absolute Voltage
Reference
The ADRES register contains the results of the last
conversion. These results are present during the sam-
pling period of the next analog conversion process.
After the sampling period is over, ADRES is cleared (=
0). A ‘leading one’ is then right shifted into the ADRES
to serve as an internal conversion complete bit. As
each bit weight, starting with the MSb, is converted, the
leading one is shifted right and the converted bit is
stuffed into ADRES. After a total of 9 right shifts of the
‘leading one’ have taken place, the conversion is com-
plete; the ‘leading one’ has been shifted out and the
GO/DONE bit is cleared.
The function of the Internal Absolute Voltage Refer-
ence is to provide a constant voltage for conversion
across the devices VDD supply range. The A/D Con-
verter is ratiometric with the conversion reference
voltage being VDD. Converting a constant voltage of
0.6V (typical) will result in a result based on the voltage
applied to VDD of the device. The result of conversion
of this reference across the VDD range can be
approximated by: Conversion Result = 0.6V/(VDD/256)
Note:
The actual value of the Absolute Voltage
Reference varies with temperature and
part-to-part variation. The conversion is
also susceptible to analog noise on the
VDD pin and noise generated by the sink-
ing or sourcing of current on the I/O pins.
If the GO/DONE bit is cleared in software during a con-
version, the conversion stops. The data in ADRES is
the partial conversion result. This data is valid for the bit
weights that have been converted. The position of the
‘leading one’ determines the number of bits that have
been converted. The bits that were not converted
before the GO/DONE was cleared are unrecoverable.
REGISTER 7-1:
ADCON0: A/D CONVERTER 0 REGISTER
R/W-1
ANS1
R/W-1
ANS0
U-0
—
U-0
—
R/W-1
CHS1
R/W-1
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ANS1: ADC Analog Input Pin Select bit
1= GP1/AN1 configured for analog input
0= GP1/AN1 configured as digital I/O
(1), (2)
ANS0: ADC Analog Input Pin Select bit
1= GP0/AN0 configured as an analog input
0= GP0/AN0 configured as digital I/O
bit 5-4
bit 3-2
Unimplemented: Read as ‘0’
(3)
CHS<1:0>: ADC Channel Select bits
00= Channel 00 (GP0/AN0)
01= Channel 01 (GP1/AN1)
1X= 0.6V absolute Voltage reference
(4)
bit 1
bit 0
GO/DONE: ADC Conversion Status bit
1= ADC conversion in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared
by hardware when the ADC is done converting.
0= ADC conversion completed/not in progress. Manually clearing this bit while a conversion is in process
terminates the current conversion.
ADON: ADC Enable bit
1= ADC module is operating
0= ADC module is shut-off and consumes no power
Note 1: When the ANS bits are set, the channel(s) selected are automatically forced into analog mode regardless of the pin
function previously defined.
2:
The ANS<1:0> bits are active regardless of the condition of ADON
3: CHS<1:0> bits default to 11after any Reset.
4: If the ADON bit is clear, the GO/DONE bit cannot be set.
DS40001270F-page 30
2005-2013 Microchip Technology Inc.
PIC10F220/222
REGISTER 7-2:
ADRES: ANALOG CONVERSION RESULT REGISTER
R-X
ADRES7
bit 7
R-X
R-X
R-X
R-X
R-X
R-X
R-X
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ADRES<7:0>
2005-2013 Microchip Technology Inc.
DS40001270F-page 31
PIC10F220/222
After the analog input channel is selected (or changed),
an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
time, Equation 7-1 may be used. This equation
assumes that 1/2 LSb error is used (256 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
7.9
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 7-1. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 7-1.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
EQUATION 7-1:
ACQUISITION TIME EXAMPLE
Assumptions:
Temperature = 50°C and external impedance of 10 k 5.0V VDD
Tacq
=
=
=
Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
TAMP + TC + TCOFF
2 s + TC + [(Temperature - 25°C)(0.05 s/°C)]
Solving for Tc:
Therefore:
Tc
=
=
=
CHOLD (RIC + RSS + RS) In(1/512)
-25pF (l k + 7 k + 10 k ) In(0.00196)
2.81 s
Tacq
=
=
2 s + 2.81 s + [(50°C-25°C)(0.0 5s/°C)]
6.06 s
Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion.
2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
FIGURE 7-1:
ANALOG INPUT MODULE
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC 1k
Rss
Rs
CPIN
5 pF
VA
I LEAKAGE
± 500 nA
CHOLD = 25 pF
VSS/VREF-
VT = 0.6V
6V
5V
RSS
Legend:
CPIN
VT
ILEAKAGE
= Input Capacitance
= Threshold Voltage
= Leakage current at the pin due
to various junctions
VDD 4V
3V
2V
RIC
SS
CHOLD
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
5 6 7 8 9 1011
Sampling Switch
(k)
DS40001270F-page 32
2005-2013 Microchip Technology Inc.
PIC10F220/222
The PIC10F220/222 devices have a Watchdog Timer,
which can be shut off only through Configuration bit
WDTE. It runs off of its own RC oscillator for added reli-
ability. When using DRT, there is an 1.125 ms (typical)
delay only on VDD power-up. With this timer on-chip,
most applications need no external Reset circuitry.
8.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of real-
time applications. The PIC10F220/222 microcontrol-
lers have a host of such features intended to maximize
system reliability, minimize cost through elimination of
external components, provide power-saving operating
modes and offer code protection. These features are:
The Sleep mode is designed to offer a very low current
Power-Down mode. The user can wake-up from Sleep
through a change on input pins or through a Watchdog
Timer time-out.
• Reset:
8.1
Configuration Bits
- Power-on Reset (POR)
- Device Reset Timer (DRT)
- Watchdog Timer (WDT)
- Wake-up from Sleep on pin change
• Sleep
The PIC10F220/222 Configuration Words consist of 12
bits. Configuration bits can be programmed to select
various device configurations. One bit is the Watchdog
Timer enable bit, one bit is the MCLR enable bit and
one bit is for code protection (see Register 8-1).
• Code Protection
• ID Locations
• In-Circuit Serial Programming™
• Clock Out
REGISTER 8-1:
CONFIG: CONFIGURATION WORD(1)
—
—
—
—
—
—
—
MCLRE
CP
WDTE MCPU IOSCFS
bit 0
bit 11
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 11-5 Unimplemented: Read as ‘0’
bit 4
bit 3
bit 2
bit 1
MCLRE: GP3/MCLR Pin Function Select bit
1= GP3/MCLR pin function is MCLR
0= GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
CP: Code Protection bit
1= Code protection off
0= Code protection on
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
MCPU: Master Clear Pull-up Enable bit(2)
1= Pull-up disabled
0= Pull-up enabled
bit 0
IOSCFS: Internal Oscillator Frequency Select bit
1= 8 MHz
0= 4 MHz
Note 1: Refer to the “PIC10F220/222 Memory Programming Specification” (DS41266), to determine how to
access the Configuration Word. The Configuration Word is not user addressable during device operation.
2: MCLRE must be a ‘1’ to enable this selection.
2005-2013 Microchip Technology Inc.
DS40001270F-page 33
PIC10F220/222
8.2
Oscillator Configurations
8.3
Reset
The device differentiates between various kinds of
Reset:
8.2.1
OSCILLATOR TYPES
The PIC10F220/222 devices are offered with internal
oscillator mode only.
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during Sleep
• INTOSC: Internal 4/8 MHz Oscillator
• WDT Time-out Reset during normal operation
• WDT Time-out Reset during Sleep
• Wake-up from Sleep on pin change
8.2.2
INTERNAL 4/8 MHz OSCILLATOR
The internal oscillator provides a 4/8 MHz (nominal)
system clock (see Section 10.0 “Electrical Charac-
teristics” for information on variation over voltage and
temperature).
Some registers are not reset in any way, they are
unknown on POR and unchanged in any other Reset.
Most other registers are reset to “Reset state” on
Power-on Reset (POR), MCLR, WDT or Wake-up on
pin change Reset during normal operation. They are
not affected by a WDT Reset during Sleep or MCLR
Reset during Sleep, since these Resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD and GPWUF bits. They are set or cleared
differently in different Reset situations. These bits are
used in software to determine the nature of Reset. See
Table 8-1 for a full description of Reset states of all
registers.
In addition, a calibration instruction is programmed into
the last address of memory, which contains the calibra-
tion value for the internal oscillator. This location is
always uncode protected, regardless of the code-pro-
tect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value and is
placed at the Reset vector. This will load the W register
with the calibration value upon Reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency.
Note:
Erasing the device will also erase the pre-
programmed internal calibration value for
the internal oscillator. The calibration
value must be read prior to erasing the
part so it can be reprogrammed correctly
later.
TABLE 8-1:
RESET CONDITIONS FOR REGISTERS – PIC10F220/222
Register
Address
Power-on Reset
MCLR Reset, WDT Time-out, Wake-up On Pin Change,
(1)
(1)
W
—
qqqq qqqu
qqqq qqqu
INDF
TMR0
PC
00h
01h
02h
xxxx xxxx
xxxx xxxx
1111 1111
uuuu uuuu
uuuu uuuu
1111 1111
STATUS
FSR
03h
04h
05h
06h
07h
08h
—
0--1 1xxx
111x xxxx
1111 1110
---- xxxx
11-- 1100
xxxx xxxx
1111 1111
---- 1111
q00q quuu
111u uuuu
uuuu uuuu
---- uuuu
11-- 1100
uuuu uuuu
1111 1111
---- 1111
OSCCAL
GPIO
ADCON0
ADRES
OPTION
TRIS
—
Legend:
u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: Bits <7:2> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
DS40001270F-page 34
2005-2013 Microchip Technology Inc.
PIC10F220/222
TABLE 8-2:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
1111 1111
1111 1111
Power-on Reset
0--1 1xxx
MCLR Reset during normal operation
0--u uuuu
MCLR Reset during Sleep
0--1 0uuu
0--0 0uuu
0--0 uuuu
1--1 0uuu
1111 1111
1111 1111
1111 1111
1111 1111
WDT Reset during Sleep
WDT Reset normal operation
Wake-up from Sleep on pin change
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’.
The Power-on Reset circuit and the Device Reset
Timer (see Section 8.5 “Device Reset Timer (DRT)”)
circuit are closely related. On power-up, the Reset latch
is set and the DRT is reset. The DRT timer begins
counting once it detects MCLR to be high. After the
time-out period, which is typically 1.125 ms, it will reset
the Reset latch and thus end the on-chip Reset signal.
8.3.1
MCLR ENABLE
This Configuration bit, when unprogrammed (left in the
‘1’ state), enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD and the pin is assigned to be a I/O. See Figure 8-1.
FIGURE 8-1:
MCLR SELECT
A power-up example where MCLR is held low is shown
in Figure 8-3. VDD is allowed to rise and stabilize before
bringing MCLR high. The chip will actually come out of
Reset TDRT msec after MCLR goes high.
GPWU
Weak Pull-up
In Figure 8-4, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together or the pin
is programmed to be GP3). The VDD is stable before
the Start-up timer times out and there is no problem in
getting a proper Reset. However, Figure 8-5 depicts a
problem situation where VDD rises too slowly. The time
between when the DRT senses that MCLR is high and
when MCLR and VDD actually reach their full value, is
too long. In this situation, when the start-up timer times
out, VDD has not reached the VDD (min) value and the
chip may not function correctly. For such situations, we
recommend that external RC circuits be used to
achieve longer POR delay times (Figure 8-4).
GP3/MCLR/VPP
Internal MCLR
MCLRE
8.4
Power-on Reset (POR)
The PIC10F220/222 devices incorporate an on-chip
Power-on Reset (POR) circuitry, which provides an
internal chip Reset for most power-up situations.
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the internal POR, program
the GP3/MCLR/VPP pin as MCLR and tie through a
resistor to VDD, or program the pin as GP3. An internal
weak pull-up resistor is implemented using a transistor
(refer to Table 10-1 for the pull-up resistor ranges). This
will eliminate external RC components usually needed
to create a Power-on Reset.
Note:
When the devices start normal operation
(exit the Reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
proper operation. If these conditions are
not met, the device must be held in Reset
until the operating conditions are met.
When the devices start normal operation (exit the
Reset condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the devices
must be held in Reset until the operating parameters
are met.
For additional information on design considerations
related to the use of PIC10F220/222 devices with their
short device Reset timer, refer to Application Notes
AN522, “Power-Up Considerations” (DS00522) and
AN607, “Power-up Trouble Shooting” (DS00607).
A simplified block diagram of the on-chip Power-on
Reset circuit is shown in Figure 8-2.
2005-2013 Microchip Technology Inc.
DS40001270F-page 35
PIC10F220/222
FIGURE 8-2:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
VDD
Power-up
Detect
POR (Power-on
Reset)
GP3/MCLR/VPP
MCLR Reset
S
R
Q
Q
MCLRE
WDT Reset
WDT Time-out
Start-up Timer
1.125 ms
CHIP Reset
Pin Change
Sleep
Wake-up on pin Change Reset
FIGURE 8-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
FIGURE 8-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
DS40001270F-page 36
2005-2013 Microchip Technology Inc.
PIC10F220/222
FIGURE 8-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
Internal POR
TDRT
DRT Time-out
Internal Reset
Note:
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final
value. In this example, the chip will reset properly if, and only if, V1 VDD min.
2005-2013 Microchip Technology Inc.
DS40001270F-page 37
PIC10F220/222
8.6.1
WDT PERIOD
8.5
Device Reset Timer (DRT)
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, a time-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
On the PIC10F220/222 devices, the DRT runs any time
the device is powered up.
The DRT operates on an internal oscillator. The pro-
cessor is kept in Reset as long as the DRT is active.
The DRT delay allows VDD to rise above VDD min. and
for the oscillator to stabilize.
The on-chip DRT keeps the devices in a Reset condi-
tion for approximately 1.125 ms after MCLR has
reached a logic high (VIH MCLR) level. Programming
GP3/MCLR/VPP as MCLR and using an external RC
network connected to the MCLR input is not required in
most cases. This allows savings in cost-sensitive and/
or space restricted applications, as well as allowing the
use of the GP3/MCLR/VPP pin as a general purpose
input.
Under worst-case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
8.6.2
WDT PROGRAMMING
CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The Device Reset Time delays will vary from chip-to-
chip due to VDD, temperature and process variation.
See AC parameters for details.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum Sleep time before a WDT wake-up Reset.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 8.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
TABLE 8-3:
DRT (DEVICE RESET TIMER
PERIOD)
POR Reset
Subsequent Resets
1.125 ms (typical)
10 s (typical)
8.6
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
internal 4/8 MHz oscillator. This means that the WDT
will run even if the main processor clock has been
stopped, for example, by execution of a SLEEPinstruc-
tion. During normal operation or Sleep, a WDT Reset or
wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration WDTE as a ‘0’ (see Section 8.1
“Configuration Bits”). Refer to the PIC10F220/222
Programming Specification to determine how to access
the Configuration Word.
DS40001270F-page 38
2005-2013 Microchip Technology Inc.
PIC10F220/222
FIGURE 8-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M
U
X
Postscaler
8-to-1 MUX
1
Watchdog
Timer
3
PS<2:0>
PSA
WDT Enable
Configuration
(Figure 6-4)
To Timer0
PSA
Bit
0
1
MUX
WDT Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
TABLE 8-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Value on
All Other
Resets
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On
Reset
N/A
OPTION
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u= unchanged.
8.7
Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO/PD/GPWUF/CWUF)
The TO, PD and GPWUF bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a Power-up condition, a MCLR,
Watchdog Timer (WDT) Reset or wake-up on pin
change.
TABLE 8-5:
GPWUF
TO/PD/GPWUF STATUS AFTER RESET
TO
PD
Reset Caused By
WDT wake-up from Sleep
0
0
0
0
0
u
WDT time-out (not from Sleep)
0
0
1
1
0
1
MCLR wake-up from Sleep
Power-up
0
1
u
1
u
0
MCLR not during Sleep
Wake-up from Sleep on pin change
Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.
Note 1: The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR
input does not change the TO, PD or GPWUF Status bits.
2005-2013 Microchip Technology Inc.
DS40001270F-page 39
PIC10F220/222
FIGURE 8-9:
BROWN-OUT
8.8
Reset on Brown-out
PROTECTION CIRCUIT 3
A Brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
Brown-out.
VDD
MCP809
VDD
Bypass
Capacitor
VSS
VDD
To reset PIC10F220/222 devices when a Brown-out
occurs, external Brown-out protection circuits may be
built, as shown in Figure 8-7 and Figure 8-8.
RST
(2)
MCLR
PIC10F22X
FIGURE 8-7:
BROWN-OUT
PROTECTION CIRCUIT 1
Note 1: This Brown-out Protection circuit employs
Microchip Technology’s MCP809 micro-
controller supervisor. There are 7 different
trip point selections to accommodate 5V to
3V systems.
VDD
VDD
33k
2: Pin must be configured as MCLR.
PIC10F22X
Q1
(2)
MCLR
10k
(1)
8.9
Power-down Mode (Sleep)
40k
A device may be powered down (Sleep) and later
powered up (wake-up from Sleep).
Note 1: This circuit will activate Reset when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
2: Pin must be configured as MCLR.
8.9.1
SLEEP
The Power-Down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low or high-impedance).
FIGURE 8-8:
BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
R2
Note:
A Reset generated by a WDT time-out
does not drive the MCLR pin low.
PIC10F22X
Q1
(2)
MCLR
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the GP3/
MCLR/VPP pin must be at a logic high level if MCLR is
enabled.
(1)
40k
Note 1: This brown-out circuit is less expensive,
although less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
R1
= 0.7V
VDD •
R1 + R2
2: Pin must be configured as MCLR.
DS40001270F-page 40
2005-2013 Microchip Technology Inc.
PIC10F220/222
8.9.2
WAKE-UP FROM SLEEP
8.12 In-Circuit Serial Programming™
The device can wake-up from Sleep through one of the
following events:
The PIC10F220/222 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom
firmware, to be programmed.
1. An external Reset input on GP3/MCLR/VPP pin,
when configured as MCLR.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
3. A change on input pin GP0, GP1 or GP3 when
wake-up on change is enabled.
These events cause a device Reset. The TO, PD
GPWUF bits can be used to determine the cause of a
device Reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The GPWUF bit indicates a change in state while in
Sleep at pins GP0, GP1 or GP3 (since the last file or bit
operation on GP port).
The devices are placed into a Program/Verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 becomes the programming clock
and GP0 becomes the programming data. Both GP1
and GP0 are Schmitt Trigger inputs in this mode.
After Reset, a 6-bit command is then supplied to the
device. Depending on the command, 16 bits of program
data are then supplied to or from the device, depending
if the command was a Load or a Read. For complete
details of serial programming, please refer to the
PIC10F220/222 Programming Specifications.
Caution: Right before entering Sleep, read the
input pins. When in Sleep, wake up
occurs when the values at the pins
change from the state they were in at the
last reading. If a wake-up on change
occurs and the pins are not read before
re-entering Sleep, a wake-up will occur
immediately even if no pins change
while in Sleep mode.
A typical In-Circuit Serial Programming connection is
shown in Figure 8-10.
FIGURE 8-10:
TYPICAL IN-CIRCUIT
SERIAL
PROGRAMMING™
CONNECTION
Note:
The WDT is cleared when the device
wakes from Sleep, regardless of the wake-
up source.
To Normal
Connections
External
Connector
Signals
PIC10F22X
8.10 Program Verification/Code
Protection
+5V
0V
VDD
If the Code Protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
VSS
VPP
MCLR/VPP
GP1
GP0
CLK
The first 64 locations and the last location (Reset
Vector) can be read, regardless of the code protection
bit setting.
Data I/O
VDD
8.11 ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code
identification numbers. These locations are not
accessible during normal execution, but are readable
and writable during program/verify.
To Normal
Connections
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ‘1’s.
2005-2013 Microchip Technology Inc.
DS40001270F-page 41
PIC10F220/222
NOTES:
DS40001270F-page 42
2005-2013 Microchip Technology Inc.
PIC10F220/222
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true or the program counter is changed as a result of an
instruction, the instruction execution time is 2 s.
9.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Each PIC16 instruction is a 12-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands which further specify the operation
of the instruction. The formats for each of the catego-
ries is presented in Figure 9-1, while the various
opcode fields are summarized in Table 9-1.
Figure 9-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
‘0xhhh’
For byte-oriented instructions, ‘f’ represents a file reg-
ister designator and ‘d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
where ‘h’ signifies a hexadecimal digit.
FIGURE 9-1:
GENERAL FORMAT FOR
INSTRUCTIONS
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’, the result is placed
in the file register specified in the instruction.
Byte-oriented file register operations
11
6
5
d
4
0
OPCODE
f (FILE #)
For bit-oriented instructions, ‘b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ‘f’ represents the number of the
file in which the bit is located.
d = 0for destination W
d = 1for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
For literal and control operations, ‘k’ represents an
8 or 9-bit constant or literal value.
5
4
0
OPCODE
f (FILE #)
b = 3-bit address
f = 5-bit file register address
TABLE 9-1:
OPCODE FIELD
DESCRIPTIONS
Literal and control operations (except GOTO)
11
Field
Description
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
8
7
0
OPCODE
k (literal)
Bit address within an 8-bit file register
Literal field, constant data or label
k = 8-bit immediate value
k
x
Don’t care location (= 0or 1)
Literal and control operations – GOTOinstruction
11
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
9
8
0
OPCODE
k (literal)
d
Destination select;
d= 0(store result in W)
d= 1(store result in file register ‘f’)
Default is d= 1
k = 9-bit immediate value
label
TOS
PC
Label name
Top-of-Stack
Program Counter
Watchdog Timer counter
Time-out bit
WDT
TO
PD
Power-down bit
dest
Destination, either the W register or the specified
register file location
[
(
]
)
Options
Contents
Assigned to
< >
Register bit field
In the set of
italics
User defined term (font is courier)
2005-2013 Microchip Technology Inc.
DS40001270F-page 43
PIC10F220/222
TABLE 9-2:
INSTRUCTION SET SUMMARY
Description
12-Bit Opcode
MSb LSb
Mnemonic,
Operands
Status
Affected
Cycles
Notes
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
1
1
1
1
1
0001 11df ffff C,DC,Z
1,2,4
2,4
4
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
0010 11df ffff
0010 10df ffff
0011 11df ffff
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1
2,4
2,4
2,4
2,4
2,4
2,4
1,4
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
Z
None
None
C
–
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
2,4
2,4
1,2,4
2,4
C
0000 10df ffff C,DC,Z
0011 10df ffff
0001 10df ffff
None
Z
Exclusive OR W with f
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
0100 bbbf ffff
None
None
None
None
2,4
2,4
0101 bbbf ffff
0110 bbbf ffff
0111 bbbf ffff
1(2)
1(2)
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
–
k
–
f
AND literal with W
Call subroutine
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100 TO, PD
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
Z
None
1
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
None
Z
None
None
None
0000 0000 0011 TO, PD
0000 0000 0fff
1111 kkkk kkkk
None
Z
3
XORLW
k
Exclusive OR Literal to W
Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for
GOTO. See Section 4.7 “Program Counter”.
2: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and
is driven low by an external device, the data will be written back with a ‘0’.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tri-state
latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS40001270F-page 44
2005-2013 Microchip Technology Inc.
PIC10F220/222
9.1
Instruction Description
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF f,d
Syntax:
[ label ] BCF f,b
Operands:
0 f 31
d
Operands:
0 f 31
0 b 7
Operation:
(W) + (f) (destination)
Operation:
0 (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description:
Add the contents of the W register
Description:
Bit ‘b’ in register ‘f’ is cleared.
and register ‘f’. If ‘d’ is ‘0’, the result
is stored in the W register. If ‘d’ is
‘1’, the result is stored back in
register ‘f’.
ANDLW
AND literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
0 k 255
k
Syntax:
[ label ] BSF f,b
Operands:
Operation:
Operands:
0 f 31
0 b 7
(W).AND. (k) (W)
Operation:
1 (f<b>)
Status Affected: Z
Status Affected: None
Description:
The contents of the W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description: Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test f, Skip if Clear
ANDWF
AND W with f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDWF f,d
Operands:
0 f 31
0 b 7
Operands:
0 f 31
d [0,1]
Operation:
skip if (f<b>) = 0
Operation:
(W) AND (f) (destination)
Status Affected: None
Status Affected: Z
Description: If bit ‘b’ in register ‘f’ is ‘0’, then the
Description: The contents of the W register are
next instruction is skipped.
AND’ed with register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
If bit ‘b’ is ‘0’, then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a two-cycle instruction.
2005-2013 Microchip Technology Inc.
DS40001270F-page 45
PIC10F220/222
CLRW
Clear W
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] CLRW
None
Syntax:
[ label ] BTFSS f,b
Operands:
Operation:
Operands:
0 f 31
0 b < 7
00h (W);
1 Z
Operation:
skip if (f<b>) = 1
Status Affected:
Description:
Z
Status Affected: None
The W register is cleared. Zero bit
(Z) is set.
Description:
If bit ‘b’ in register ‘f’ is ‘1’, then the
next instruction is skipped.
If bit ‘b’ is ‘1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a two-cycle instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT k
None
CALL
Subroutine Call
[ label ] CALL k
0 k 255
Syntax:
Operands:
Operation:
Operands:
Operation:
00h WDT;
0 WDT prescaler (if assigned);
(PC) + 1 Top of Stack;
k PC<7:0>;
1 TO;
1 PD
(Status<6:5>) PC<10:9>;
0 PC<8>
Status Affected: TO, PD
Status Affected: None
Description:
The CLRWDTinstruction resets the
Description:
Subroutine call. First, return
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
address (PC + 1) is pushed onto
the stack. The eight-bit immediate
address is loaded into PC bits
<7:0>. The upper bits PC<10:9>
are loaded from STATUS<6:5>,
PC<8> is cleared. CALLis a two-
cycle instruction.
CLRF
Clear f
COMF
Complement f
Syntax:
[ label ] CLRF
0 f 31
f
Syntax:
Operands:
[ label ] COMF f,d
Operands:
Operation:
0 f 31
d [0,1]
00h (f);
1 Z
Operation:
(f) (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
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PIC10F220/222
DECF
Decrement f
INCF
Increment f
Syntax:
Operands:
[ label ] DECF f,d
Syntax:
Operands:
[ label ] INCF f,d
0 f 31
d [0,1]
0 f 31
d [0,1]
Operation:
(f) – 1 (dest)
Operation:
(f) + 1 (dest)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
INCFSZ
Syntax:
Increment f, Skip if 0
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] INCFSZ f,d
[ label ] DECFSZ f,d
Operands:
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
(f) + 1 (dest), skip if result = 0
Operation:
(f) – 1 d; skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are dec-
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
remented. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
If the result is ‘0’, then the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead making it a two-
cycle instruction.
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead making it a two-cycle
instruction.
IORLW
Inclusive OR literal with W
[ label ] IORLW k
0 k 255
GOTO
Unconditional Branch
[ label ] GOTO k
0 k 511
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. (k) (W)
Z
k PC<8:0>;
STATUS<6:5> PC<10:9>
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description: GOTOis an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTOis a two-
cycle instruction.
2005-2013 Microchip Technology Inc.
DS40001270F-page 47
PIC10F220/222
IORWF
Inclusive OR W with f
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 f 31
Syntax:
[ label ] IORWF f,d
f
Operands:
0 f 31
d [0,1]
Operands:
Operation:
(W) (f)
Operation:
(W).OR. (f) (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
Move data from the W register to
register ‘f’.
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is ‘1’,
the result is placed back in register
‘f’.
MOVF
Move f
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
[ label ] MOVF f,d
Syntax:
0 f 31
d [0,1]
Operands:
Operation:
No operation
Operation:
(f) (dest)
Status Affected: None
Status Affected:
Description:
Z
Description:
No operation.
The contents of register ‘f’ are
moved to destination ‘d’. If ‘d’ is ‘0’,
destination is the W register. If ‘d’
is ‘1’, the destination is file register
‘f’. ‘d’ = 1is useful as a test of a file
register, since status flag Z is
affected.
MOVLW
Syntax:
Move Literal to W
[ label ] MOVLW k
0 k 255
OPTION
Syntax:
Load OPTION Register
[ label ] OPTION
None
Operands:
Operation:
Operands:
Operation:
(W) OPTION
k (W)
Status Affected: None
Status Affected: None
Description: The content of the W register is
Description: The eight-bit literal ‘k’ is loaded
loaded into the OPTION register.
into the W register. The “don’t
cares” will assembled as ‘0’s.
DS40001270F-page 48
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PIC10F220/222
RETLW
Return with Literal in W
[ label ] RETLW k
0 k 255
SLEEP
Enter SLEEP Mode
Syntax:
Syntax:
[label]
SLEEP
Operands:
Operation:
Operands:
Operation:
None
k (W);
TOS PC
00h WDT;
0 WDT prescaler;
1 TO;
Status Affected: None
0 PD
Description:
The W register is loaded with the
Status Affected: TO, PD, RBWUF
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
Description:
Time-out Status bit (TO) is set. The
Power-down Status bit (PD) is
cleared.
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
The processor is put into Sleep
mode with the oscillator stopped.
See section on Sleep for more
details.
RLF
Rotate Left f through Carry
SUBWF
Subtract W from f
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[label] SUBWF f,d
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
See description below
C
Operation:
(f) – (W) dest)
Status Affected:
Description:
Status Affected: C, DC, Z
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register. If
‘d’ is ‘1’, the result is stored back in
register ‘f’.
Description:
Subtract (2’s complement method)
the W register from register ‘f’. If ‘d’
is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
register ‘f’
C
RRF
Rotate Right f through Carry
SWAPF
Syntax:
Swap Nibbles in f
Syntax:
Operands:
[ label ] RRF f,d
[label] SWAPF f,d
0 f 31
d [0,1]
Operands:
0 f 31
d [0,1]
Operation:
See description below
C
Operation:
(f<3:0>) (dest<7:4>);
(f<7:4>) (dest<3:0>)
Status Affected:
Description:
Status Affected: None
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ is ‘0’, the
result is placed in the W register. If
‘d’ is ‘1’, the result is placed back
in register ‘f’.
Description: The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
register ‘f’
C
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PIC10F220/222
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
f
Operands:
Operation:
f = 6
(W) TRIS register f
Status Affected: None
Description:
TRIS register ‘f’ (f = 6 or 7) is
loaded with the contents of the W
register
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW k
0 k 255
Operands:
Operation:
(W) .XOR. k W)
Z
Status Affected:
Description:
The contents of the W register are
XOR’ed with the eight-bit literal ‘k’.
The result is placed in the W
register.
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
Operands:
0 f 31
d [0,1]
Operation:
(W) .XOR. (f) dest)
Status Affected:
Description:
Z
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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10.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature ...............................................................................................................................-65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +6.5V
Voltage on MCLR with respect to VSS.............................................................................................................0 to +13.5V
Voltage on all other pins with respect to VSS .................................................................................. -0.3V to (VDD + 0.3V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin .....................................................................................................................................80 mA
Max. current into VDD pin........................................................................................................................................80 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin............................................................................................................25 mA
Max. output current sourced by I/O port .................................................................................................................75 mA
Max. output current sunk by I/O port ......................................................................................................................75 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} .. + (VOL x
IOL)
†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
2005-2013 Microchip Technology Inc.
DS40001270F-page 51
PIC10F220/222
FIGURE 10-1:
6.0
VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
8
0
4
10
20
25
Frequency (MHz)
DS40001270F-page 52
2005-2013 Microchip Technology Inc.
PIC10F220/222
10.1 DC Characteristics: PIC10F220/222 (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40×C TA +85C (industrial)
DC CHARACTERISTICS
Param
Sym
No.
(1)
Characteristic
Min Typ
Max Units
Conditions
D001
D002
D003
VDD Supply Voltage
2.0
5.5
—
V
V
V
See Figure 10-1
(2)
VDR RAM Data Retention Voltage
1.5*
—
—
Device in Sleep mode
VPOR VDD Start Voltage
Vss
—
to ensure Power-on Reset
D004
D010
SVDD VDD Rise Rate
to ensure Power-on Reset
(3)
0.05*
—
—
V/ms
IDD
IPD
Supply Current
—
—
—
—
175
0.625
250
275
1.1
400
1.5
A
mA
A
VDD = 2.0V, Fosc = 4 MHz
VDD = 5.0V, Fosc = 4 MHz
VDD = 2.0V, Fosc = 8 MHz
VDD = 5.0V, Fosc = 8 MHz
0.800
mA
(4)
Power-down Current
D020
D022
—
—
0.1
1
1.2
2.4
A
A
VDD = 2.0V
VDD = 5.0V
(4)
IWDT WDT Current
—
—
1.0
7
3
16
A
A
VDD = 2.0V
VDD = 5.0V
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only
and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus
rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.
4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD
or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is
enabled.
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DS40001270F-page 53
PIC10F220/222
10.2 DC Characteristics: PIC10F220/222 (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40×C £ TA £ +125×C (extended)
DC CHARACTERISTICS
Param
Sym
No.
(1)
Characteristic
Supply Voltage
Min
Typ
Max
Units
Conditions
D001
D002
D003
VDD
VDR
2.0
1.5*
—
5.5
—
V
V
V
See Figure 10-1
(2)
RAM Data Retention Voltage
Device in Sleep mode
VPOR
VDD Start Voltage
Vss
—
to ensure Power-on Reset
(3)
IDD
Supply Current
D010
—
—
—
—
175
0.625
250
275
1.1
400
1.5
A
mA
A
VDD = 2.0V, Fosc = 4 MHz
VDD = 5.0V, Fosc = 4 MHz
VDD = 2.0V, Fosc = 8 MHz
VDD = 5.0V, Fosc = 8 MHz
0.800
mA
(4)
IPD
Power-down Current
D020
D022
—
—
0.1
1
9
15
A
A
VDD = 2.0V
VDD = 5.0V
(4)
IWDT
WDT Current
—
—
1.0
7
18
22
A
A
VDD = 2.0V
VDD = 5.0V
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25C. This data is for design guidance only
and is not tested.
2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading, bus
rate, internal code execution pattern and temperature also have an impact on the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
All I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in Sleep mode.
4: Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD
or VSS. The peripheral current is the sum of the base IPD and the additional current consumed when the peripheral is
enabled.
DS40001270F-page 54
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PIC10F220/222
10.3 DC Characteristics: PIC10F220/222 (Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
-40°C TA +85°C (industrial)
-40°C TA +125°C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC specification
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
VIL Input Low Voltage
I/O ports:
D030
D030A
D031
with TTL buffer
Vss
Vss
Vss
—
—
—
0.8
V
V
V
For all 4.5 VDD 5.5V
0.15 VDD
0.2 VDD
Otherwise
with Schmitt Trigger
buffer
D032
MCLR, T0CKI
Vss
—
0.2 VDD
V
VIH Input High Voltage
I/O ports:
—
—
—
—
D040
D040A
D041
with TTL buffer
2.0
VDD
VDD
VDD
V
V
V
4.5 VDD 5.5V
Otherwise
0.25 VDD + 0.8
0.8VDD
with Schmitt Trigger
For entire VDD range
buffer
D042
D070
MCLR, T0CKI
0.8VDD
50
—
VDD
400
V
IPUR GPIO weak pull-up current
250
A VDD = 5V, VPIN = VSS
(1)
IIL
Input Leakage Current
D060
D061
I/O ports
—
—
±0.1
±0.7
± 1
± 5
A Vss VPIN VDD, Pin at high-imped-
ance
(2)
GP3/MCLR
A Vss VPIN VDD
Output Low Voltage
D080
I/O ports
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V, -40C to
+85C
D080A
IOL = 7.0 mA, VDD = 4.5V, -40C to
+125C
Output High Voltage
(2)
D090
I/O ports
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V, -40C to
+85C
D090A
IOH = -2.5 mA, VDD = 4.5V, -40C to
+125C
Capacitive Loading Specs on Output Pins
All I/O pins
D101
—
—
50*
pF
†
*
Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
These parameters are for design guidance only and are not tested.
Note 1: Negative current is defined as coming out of the pin.
2: This specification applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the
MCLR circuit is higher than the standard I/O logic.
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PIC10F220/222
TABLE 10-1: PULL-UP RESISTOR RANGES
VDD (Volts)
GP0/GP1
Temperature (C)
Min
Typ
Max
Units
2.0
5.5
-40
25
73K
73K
82K
86K
15K
15K
19K
23K
105K
113K
123K
132k
21K
186K
187K
190K
190K
33K
85
125
-40
25
22K
34K
85
26k
35K
125
29K
35K
GP3
2.0
-40
25
63K
77K
82K
86K
16K
16K
24K
26K
81K
93K
96k
96K
116K
116K
119K
22K
85
125
-40
25
100K
20k
5.5
21K
25k
23K
85
28K
125
27K
29K
DS40001270F-page 56
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PIC10F220/222
10.4 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T Time
Lowercase subscripts (pp) and their meanings:
pp
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
Cycle time
Device Reset Timer
I/O port
Oscillator
OSC1
t0
T0CKI
wdt
Watchdog Timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (high-impedance)
Low
Valid
L
High-impedance
FIGURE 10-2:
LOAD CONDITIONS
Legend:
CL
CL = 50 pF for all pins
pin
VSS
TABLE 10-2: CALIBRATED INTERNAL RC FREQUENCIES – PIC10F220/222
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
-40C TA +85C (industrial),
-40C TA +125C (extended)
AC CHARACTERISTICS
Operating Voltage VDD range is described in
Section 10.1 “DC Characteristics: PIC10F220/222 (Industrial)”.
Param
Freq.
Tolerance
Sym
Characteristic
Min Typ†
Max Units
Conditions
No.
F10
FOSC
Internal Calibrated
INTOSC
1%
2%
3.96 4.00
3.92 4.00
4.04 MHz VDD=3.5V @ 25C
4.08 MHz 2.5V VDD 5.5V
0C TA +85C (industrial)
4.20 MHz 2.0V VDD 5.5V
-40C TA +85C (industrial)
-40C TA +125C (extended)
Frequency(1, 2, 3)
5%
3.80 4.00
†
Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: Under stable VDD conditions.
3: Frequency values in this table are doubled when the 8 MHz INTOSC option is selected.
2005-2013 Microchip Technology Inc.
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PIC10F220/222
FIGURE 10-3:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
30
Internal
POR
32
32
32
DRT
(2)
Timeout
Internal
Reset
Watchdog
Timer
Reset
31
34
34
(1)
I/O pin
Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.
2: Runs on POR Reset only.
TABLE 10-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC10F220/222
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
AC CHARACTERISTICS
-40C TA +125C (extended)
Operating Voltage VDD range is described in Section 10.1 “DC
Characteristics: PIC10F220/222 (Industrial)”
Param
Sym
No.
Characteristic
MCLR Pulse Width (low)
Min Typ(1) Max Units
Conditions
30
31
32
TMC
2*
5*
—
—
—
—
s
s
VDD = 5V, -40°C to +85°C
VDD = 5.0V
L
TWDT Watchdog Timer Time-out Period
(no prescaler)
10
10
18
18
29
31
ms VDD = 5.0V (Industrial)
ms VDD = 5.0V (Extended)
TDRT* Device Reset Timer Period
(standard)
0.600 1.125 1.85
0.600 1.125 1.95
ms VDD = 5.0V (Industrial)
ms VDD = 5.0V (Extended)
34
TIOZ
I/O High-impedance from MCLR
low
—
—
2*
s
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS40001270F-page 58
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PIC10F220/222
FIGURE 10-4:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
TABLE 10-4: TIMER0 CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40C TA +85C (industrial)
-40C TA +125C (extended)
AC CHARACTERISTICS
Param
Sym
No.
Characteristic
No Prescaler
Min
Typ(1) Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Width
With Prescaler
No Prescaler
With Prescaler
Tt0L T0CKI Low Pulse
Width
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40* N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2005-2013 Microchip Technology Inc.
DS40001270F-page 59
PIC10F220/222
TABLE 10-5: A/D CONVERTER CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
Sym
Characteristic Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
—
8 bits
±1.5
bit
A03
A04
A05
A06
A07
A10
A25
A30
EIL
Integral Error
Differential Error
Full-scale Range
—
LSb
EDL
EFS
—
—
-1 < EDL + 1.5 LSb
2.0*
—
—
5.5*
±1.5
±1.5
—
V
LSb
LSb
—
EOFF Offset Error
—
EGN
—
Gain Error
—
—
Monotonicity
—
guaranteed(1)
VSS VAIN VDD
VAIN
ZAIN
Analog Input Voltage
VSS
—
—
—
VDD
10
V
Recommended
k
Impedence of Analog
Voltage Source
A31*
IAD A/D Conversion Current(2)
—
—
120
200
150
250
A
A
2.0V
5.0V
*
These parameters are characterized but not tested.
†
Data in the “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only are not tested.
Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
2: This is the additional current consumed by the A/D module when it is enabled; this current adds to base
IDD.
TABLE 10-6: A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
AD131 TCNV Conversion Time
(not including
—
13
—
TCY Set GO/DONE bit to new data in A/D
Result register
Acquisition Time)
AD132* TACQ Acquisition Time(1)
—
3.5
5
—
s VDD = 5V
s VDD = 2.5V
*
These parameters are characterized but not tested.
†
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The Section 7.9 “A/D Acquisition Requirements” for information on how to compute minimum
acquisition times based on operating conditions.
DS40001270F-page 60
2005-2013 Microchip Technology Inc.
PIC10F220/222
11.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “Maximum” or “minimum” represents (mean + 3) or (mean -
3) respectively, where s is a standard deviation, over each temperature range.
FIGURE 11-1:
IDD vs. VDD OVER FOSC (4 MHZ)
XT Mode
1,400
1,200
1,000
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
Maximum
4 MHz
4 MHz
Typical
600
400
200
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2005-2013 Microchip Technology Inc.
DS40001270F-page 61
PIC10F220/222
FIGURE 11-2:
IDD vs. VDD OVER FOSC (8 MHZ)
1,800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
Maximum
1,600
1,400
1,200
1,000
800
8 MHz
8 MHz
Typical
600
400
200
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 11-3:
TYPICAL IPD vs. VDD (SLETEyPpicMaOl DE, ALL PERIPHERALS DISABLED)
1.10
Typical: Statistical Mean @25°C
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001270F-page 62
2005-2013 Microchip Technology Inc.
PIC10F220/222
FIGURE 11-4:
MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
18.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
16.0
14.0
12.0
10.0
8.0
Max. 125°C
6.0
4.0
Max. 85°C
3.5
2.0
0.0
2.0
2.5
3.0
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 11-5:
TYPICAL WDT IPD vs. VDD
9
Typical: Statistical Mean @25°C
8
7
6
5
4
3
2
1
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2005-2013 Microchip Technology Inc.
DS40001270F-page 63
PIC10F220/222
FIGURE 11-6:
MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE
Maximum
25.0
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
20.0
15.0
10.0
5.0
Max. 125°C
Max. 85°C
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 11-7:
WDT TIME-OUT vs. VDD OVER TEMPERATURE (NO PRESCALER)
50
45
40
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
Max. 85°C
35
30
25
20
15
10
5
Typical. 25°C
Min. -40°C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS40001270F-page 64
2005-2013 Microchip Technology Inc.
PIC10F220/222
FIGURE 11-8:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
(VDD = 3V, -40×C TO 125×C)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
Max. 85°C
Typical 25°C
Min. -40°C
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 11-9:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
Max. 125°C
Max. 85°C
Typ. 25°C
Min. -40°C
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
2005-2013 Microchip Technology Inc.
DS40001270F-page 65
PIC10F220/222
FIGURE 11-10:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
2.5
2.0
1.5
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
FIGURE 11-11:
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.5
5.0
4.5
4.0
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
3.5
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
DS40001270F-page 66
2005-2013 Microchip Technology Inc.
PIC10F220/222
FIGURE 11-12:
TTL INPUT THRESHOLD VIN vs. VDD
1.7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
1.5
1.3
1.1
0.9
0.7
0.5
Max. -40°C
Typ. 25°C
Min. 125°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 11-13:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD
(ST Input, -40×C TO 125×C)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VIH Max. 125°C
VIH Min. -40°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst Case Temp) + 3
(-40°C to 125°C)
VIL Max. -40°C
VIL Min. 125°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2005-2013 Microchip Technology Inc.
DS40001270F-page 67
PIC10F220/222
NOTES:
DS40001270F-page 68
2005-2013 Microchip Technology Inc.
PIC10F220/222
12.1 MPLAB X Integrated Development
Environment Software
12.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
- MPLAB PM3 Device Programmer
• Smart code completion makes suggestions and
provides hints as you type
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Automatic code formatting based on user-defined
rules
• Third-party development tools
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2005-2013 Microchip Technology Inc.
DS40001270F-page 69
PIC10F220/222
12.2 MPLAB XC Compilers
12.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
12.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
12.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS40001270F-page 70
2005-2013 Microchip Technology Inc.
PIC10F220/222
12.6 MPLAB X SIM Software Simulator
12.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
12.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
12.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
12.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2005-2013 Microchip Technology Inc.
DS40001270F-page 71
PIC10F220/222
12.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
12.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
®
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS40001270F-page 72
2005-2013 Microchip Technology Inc.
PIC10F220/222
13.0 PACKAGING INFORMATION
13.1 Package Marking Information
6-Lead SOT-23*
Example
XXNN
20JR
8-Lead PDIP
Example
PIC10F220
I/P 07Q
0520
XXXXXXXX
XXXXXNNN
YYWW
e
3
8-Lead DFN*
Example
XXX
YWW
NN
BJ0
625
3Q
Legend: XX...X Product-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2005-2013 Microchip Technology Inc.
DS40001270F-page 73
PIC10F220/222
TABLE 13-1: 8-LEAD 2x3 DFN (MC) TOP
MARKING
TABLE 13-2: 6-LEAD SOT-23 (OT)
PACKAGE TOP MARKING
Part Number
Marking
Part Number
Marking
PIC10F220-I/MC
PIC10F220-E/MC
PIC10F222-I/MC
PIC10F222-E/MC
BJ0
BK0
BL0
BM0
PIC10F220-I/OT
PIC10F220-E/OT
PIC10F222-I/OT
PIC10F222-E/OT
20NN
A0NN
22NN
A2NN
Note:
NN
represents
the
alphanumeric
traceability code.
DS40001270F-page 74
2005-2013 Microchip Technology Inc.
PIC10F220/222
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2005-2013 Microchip Technology Inc.
DS40001270F-page 75
PIC10F220/222
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001270F-page 76
2005-2013 Microchip Technology Inc.
PIC10F220/222
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2005-2013 Microchip Technology Inc.
DS40001270F-page 77
PIC10F220/222
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DS40001270F-page 78
2005-2013 Microchip Technology Inc.
PIC10F220/222
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2005-2013 Microchip Technology Inc.
DS40001270F-page 79
PIC10F220/222
APPENDIX A: REVISION HISTORY
Revision A
Original release of document.
Revision B (03/2006)
Table 3-1, GP1; Section 4.7, Program Counter; Table 5-
2; Figure 8-5; Section 9.1, ANDWF, SLEEP, SUBWF,
SWAPF, XORLW.
Revision C (08/2006)
Added 8-Lead DFN pinout diagram, updated Table 1-1
with DFN package, updated Table 10-3 in Section 10.0,
added 8-Lead DFN package marking information to
section 13.0, updated the Product Identification
System section to include DFN package identification.
Added note to package drawings.
Revision D (02/2007)
Replaced Dev. Tool Section; Replaced Package
Drawings.
Revision E (06/2007)
Updated and added Characterization Data; Revised
Operating Current; Revised Section 8.4 and Note;
Revised Section 10.0, Total Power Dissipation, 10.1,
10.2, 10.3 DC Characteristics; Revised Tables 10-2,
10-3, 10-5, 10-6; Section 11.0; Revised Product ID
System.
Revision F (10/2013)
Revised Packaging Legend.
DS40001270F-page 80
2005-2013 Microchip Technology Inc.
PIC10F220/222
INDEX
A
M
A/D
Memory Organization ......................................................... 13
Data Memory.............................................................. 14
Program Memory (PIC10F220) .................................. 13
Program Memory (PIC10F222) .................................. 13
Microchip Internet Web Site................................................ 75
MPLAB ASM30 Assembler, Linker, Librarian..................... 62
MPLAB ICD 2 In-Circuit Debugger..................................... 63
MPLAB ICE 2000 High-Performance Universal
Specifications.............................................................. 60
ADC
Internal Sampling Switch (RSS) IMPEDANCE ................ 32
Source Impedance...................................................... 32
ALU ....................................................................................... 9
Assembler
MPASM Assembler..................................................... 62
In-Circuit Emulator...................................................... 63
MPLAB Integrated Development Environment Software.... 61
MPLAB PM3 Device Programmer ...................................... 63
MPLAB REAL ICE In-Circuit Emulator System .................. 63
MPLINK Object Linker/MPLIB Object Librarian.................. 62
B
Block Diagram
On-Chip Reset Circuit................................................. 36
Timer0......................................................................... 25
TMR0/WDT Prescaler................................................. 28
Watchdog Timer.......................................................... 39
Block Diagrams
O
OPTION Register................................................................ 17
OSCCAL Register............................................................... 18
Oscillator Configurations..................................................... 34
Oscillator Types
Analog Input Model..................................................... 32
Brown-Out Protection Circuit .............................................. 40
C
HS............................................................................... 34
LP ............................................................................... 34
C Compilers
MPLAB C18 ................................................................ 62
MPLAB C30 ................................................................ 62
Carry ..................................................................................... 9
Clocking Scheme ................................................................ 11
Code Protection ............................................................ 33, 41
Configuration Bits................................................................ 33
Customer Change Notification Service ............................... 75
Customer Notification Service............................................. 75
Customer Support............................................................... 75
P
PIC10F220/222 Device Varieties.......................................... 7
PICSTART Plus Development Programmer....................... 64
POR
Device Reset Timer (DRT) ................................... 33, 38
PD............................................................................... 39
Power-on Reset (POR)............................................... 33
TO............................................................................... 39
Power-down Mode.............................................................. 40
Prescaler ............................................................................ 27
Program Counter................................................................ 19
D
DC and AC Characteristics................................................. 65
Development Support ......................................................... 61
Digit Carry............................................................................. 9
Q
Q cycles.............................................................................. 11
E
R
Errata .................................................................................... 3
Reader Response............................................................... 76
Read-Modify-Write.............................................................. 23
Register File Map
F
Family of Devices
PIC10F22X ................................................................... 5
FSR..................................................................................... 20
PIC10F220 ................................................................. 14
PIC10F222 ................................................................. 14
Registers
Special Function......................................................... 14
Reset .................................................................................. 33
Reset on Brown-Out ........................................................... 40
G
GPIO................................................................................... 21
I
S
I/O Interfacing ..................................................................... 21
I/O Ports.............................................................................. 21
I/O Programming Considerations........................................ 23
ID Locations.................................................................. 33, 41
INDF.................................................................................... 20
Indirect Data Addressing..................................................... 20
Instruction Cycle ................................................................. 11
Instruction Flow/Pipelining .................................................. 11
Instruction Set Summary..................................................... 44
Internal Sampling Switch (RSS) IMPEDANCE ........................ 32
Internet Address.................................................................. 75
Sleep ............................................................................ 33, 40
Software Simulator (MPLAB SIM) ...................................... 62
Special Features of the CPU .............................................. 33
Special Function Registers................................................. 14
Stack................................................................................... 19
STATUS Register ..................................................... 9, 15, 29
T
Timer0
Timer0 ........................................................................ 25
Timer0 (TMR0) Module .............................................. 25
TMR0 with External Clock .......................................... 26
Timing Parameter Symbology and Load Conditions .......... 57
TRIS Registers ................................................................... 21
L
Loading of PC ..................................................................... 19
2005-2013 Microchip Technology Inc.
DS40001270F-page 81
PIC10F220/222
W
Wake-up from Sleep ...........................................................41
Watchdog Timer (WDT) ................................................ 33, 38
Period..........................................................................38
Programming Considerations .....................................38
WWW Address....................................................................75
WWW, On-Line Support........................................................3
Z
Zero bit..................................................................................9
DS40001270F-page 82
2005-2013 Microchip Technology Inc.
PIC10F220/222
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2005-2013 Microchip Technology Inc.
DS40001270F-page 83
PIC10F220/222
NOTES:
DS40001270F-page 84
2005-2013 Microchip Technology Inc.
PIC10F220/222
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
PIC10F220-I/P = Industrial temp., PDIP
package (Pb-free)
PIC10F222T-E/OT = Extended temp., SOT-23
package (Pb-free), Tape and Reel
c)
PIC10F222-E/MC = Extended temp., DFN
package (Pb-free)
Device:
PIC10F220
PIC10F222
PIC10F220T (Tape & Reel)
PIC10F222T (Tape & Reel)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
Pattern:
P
=
=
=
300 mil PDIP (Pb-free)
SOT-23, 6-LD (Pb-free)
DFN, 8-LD 2x3 (Pb-free)
OT
MC
Special Requirements
2005-2013 Microchip Technology Inc.
DS40001270F-page 85
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-3019-1500
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Seoul
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
Los Angeles
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Taiwan - Taipei
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/20/13
DS40001270F-page 86
2005-2013 Microchip Technology Inc.
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