PIC10F322-E/OTVAO [MICROCHIP]
RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO6;
| 型号： | PIC10F322-E/OTVAO |
| 厂家： | 
MICROCHIP |
| 描述： | RISC Microcontroller, 8-Bit, FLASH, 20MHz, CMOS, PDSO6 微控制器 光电二极管 |
| 文件： | 总193页 (文件大小：1494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC10(L)F320/322
6/8-Pin Flash-Based, 8-Bit Microcontrollers
High-Performance RISC CPU
eXtreme Low-Power (XLP) Features
(PIC10LF320/322)
• Only 35 Instructions to Learn:
- All single-cycle instructions, except branches
• Operating Speed:
• Sleep Current:
- 20 nA @ 1.8V, typical
• Operating Current:
- DC – 16 MHz clock input
- DC – 250 ns instruction cycle
• Eight-level Deep Hardware Stack
• Interrupt Capability
- 25 A @ 1 MHz, 1.8V, typical
• Watchdog Timer Current:
- 500 nA @ 1.8V, typical
• Processor Self-Write/Read access to Program
Memory
• Pinout Compatible to other 6-Pin PIC10FXXX
Microcontrollers
Peripheral Features
• Four I/O Pins:
- One input-only pin
- High current sink/source for LED drivers
- Individually selectable weak pull-ups
- Interrupt-on-Change
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two PWM modules:
Memory
• Up to 512 Words of Flash Program Memory
• 64 Bytes Data Memory
• High-Endurance Flash Data Memory (HEF)
- 128B of nonvolatile data storage
- 100K erase/write cycles
- 10-bit PWM, max. frequency 16 kHz
- Combined to single 2-phase output
• A/D Converter:
- 8-bit resolution with 3 channels
• Configurable Logic Cell (CLC):
- 8 selectable input source signals
- Two inputs per module
Special Microcontroller Features
• Low-Power 16 MHz Internal Oscillator:
- Software selectable frequency range from
16 MHz to 31 kHz
- Factory calibrated to 1%, typical
• Wide Operating Range:
- 1.8V to 3.6V (PIC10LF320/322)
- 2.3V to 5.5V (PIC10F320/322)
• Power-On Reset (POR)
- Software selectable logic functions including:
AND/OR/XOR/D Flop/D Latch/SR/JK
- External or internal inputs/outputs
- Operation while in Sleep
• Power-up Timer (PWRT)
• Brown-Out Reset (BOR)
• Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
- 16-bit increment
- Linear frequency control
- High-speed clock input
• Ultra Low-Power Sleep Regulator
• Extended Watchdog Timer (WDT)
• Programmable Code Protection
• Power-Saving Sleep mode
• Selectable Oscillator Options (EC mode or
Internal Oscillator)
- Selectable Output modes
- Fixed Duty Cycle (FDC)
• In-Circuit Serial Programming™ (ICSP™) (via
Two Pins)
• In-Circuit Debugger Support
• Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V (‘F’ variant only) Output
Levels
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- Selectable falling and rising edge dead-band
control
- Polarity control
- Two auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO
• Integrated Temperature Indicator
• 40-year Flash Data Retention
2011-2015 Microchip Technology Inc.
DS40001585D-page 1
PIC10(L)F320/322
PIC10(L)F320/322 Family Types
Device
PIC10(L)F320 (1) 256
PIC10(L)F322 (1) 512
64
64
128
128
4
4
3
3
2
2
2
2
1
1
1
1
1
1
1
1
H
H
Y
Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;
E - Emulation, Available using Emulation Header.
2: One pin is input-only.
Data Sheet Index:
1: DS40001585
PIC10(L)F320/322 Data Sheet, 6/8 Pin High Performance, Flash Microcontrollers.
Note:
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001585D-page 2
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 1:
SOT-23
6-PIN DIAGRAM, PIC10(L)F320/322
ICSPDAT/RA0
1
RA3/MCLR/VPP
VDD
6
5
4
PIC10(L)F320
PIC10(L)F322
V
SS
2
3
ICSPCLK/RA1
RA2
FIGURE 2:
8-PIN DIAGRAM, PIC10(L)F320/322
PDIP, DFN
N/C
VDD
1
2
RA3/MCLR/VPP
VSS
8
7
6
5
3
4
RA2
N/C
ICSPCLK/RA1
RA0/ICSPDAT
TABLE 1:
6 AND 8-PIN ALLOCATION TABLE, PIC10(L)F320/322
I/O 6-Pin 8-Pin Analog Timer PWM Interrupts Pull-ups
CWG
NCO
CLC
Basic
ICSP
RA0
RA1
RA2
RA3
N/C
N/C
VDD
VSS
1
3
5
4
3
8
1
6
2
7
AN0
AN1
AN2
—
—
—
PWM1
PWM2
—
IOC0
IOC1
INT/IOC2
IOC3
—
Y
Y
CWG1A
—
CLC1IN0
CLC1
—
ICSPDAT
CWG1B
NCO1CLK
CLKIN ICSPCLK
4
T0CKI
—
Y
CWG1FLT
NCO1
—
CLC1IN1 CLKR
6
—
Y
—
—
—
—
—
—
—
—
—
—
MCLR
—
VPP
—
—
—
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
—
2
—
—
—
—
—
—
2011-2015 Microchip Technology Inc.
DS40001585D-page 3
PIC10(L)F320/322
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 6
2.0 Memory Organization................................................................................................................................................................... 9
3.0 Device Configuration .................................................................................................................................................................. 19
4.0 Oscillator Module........................................................................................................................................................................ 24
5.0 Resets ........................................................................................................................................................................................ 28
6.0 Interrupts .................................................................................................................................................................................... 35
7.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 44
8.0 Watchdog Timer......................................................................................................................................................................... 46
9.0 Flash Program Memory Control ................................................................................................................................................. 50
10.0 I/O Port....................................................................................................................................................................................... 67
11.0 Interrupt-On-Change .................................................................................................................................................................. 73
12.0 Fixed Voltage Reference (FVR) ................................................................................................................................................. 77
13.0 Internal Voltage Regulator (IVR) ................................................................................................................................................ 79
14.0 Temperature Indicator Module ................................................................................................................................................... 81
15.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 83
16.0 Timer0 Module ........................................................................................................................................................................... 93
17.0 Timer2 Module ........................................................................................................................................................................... 96
18.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................... 98
19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 104
20.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 119
21.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 129
22.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 144
23.0 Instruction Set Summary.......................................................................................................................................................... 147
24.0 Electrical Specifications............................................................................................................................................................ 156
25.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 176
26.0 Development Support............................................................................................................................................................... 177
27.0 Packaging Information.............................................................................................................................................................. 181
Appendix A: Data Sheet Revision History.......................................................................................................................................... 189
DS40001585D-page 4
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
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2011-2015 Microchip Technology Inc.
DS40001585D-page 5
PIC10(L)F320/322
1.0
DEVICE OVERVIEW
The PIC10(L)F320/322 are described within this data
sheet. They are available in 6/8-pin packages. Figure 1-1
shows a block diagram of the PIC10(L)F320/322
devices. Table 1-2 shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
Analog-to-Digital Converter (ADC)
Configurable Logic Cell (CLC)
Complementary Wave Generator (CWG)
Fixed Voltage Reference (FVR)
Numerically Controlled Oscillator (NCO)
Temperature Indicator
PWM Modules
●
●
●
●
●
●
●
●
●
●
●
●
PWM1
●
●
●
●
PWM2
Timers
Timer0
●
●
●
●
Timer2
DS40001585D-page 6
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 1-1:
PIC10(L)F320/322 BLOCK DIAGRAM
Program
Flash Memory
RAM
PORTA
CLKR
CLKIN
Timing
Generation
CPU
INTRC
Oscillator
Figure 2-1
MCLR
Timer0
Timer2
Temp.
Indicator
ADC
8-Bit
FVR
PWM1
CLC
CWG
PWM2
NCO
Note 1:
See applicable chapters for more information on peripherals.
2011-2015 Microchip Technology Inc.
DS40001585D-page 7
PIC10(L)F320/322
TABLE 1-2:
PIC10(L)F320/322 PINOUT DESCRIPTION
Input Output
Name
Function
Description
Type
Type
RA0/PWM1/CLC1IN0/CWG1A/
AN0/ICSPDAT
RA0
PWM1
CLC1IN0
CWG1A
AN0
TTL
—
CMOS General purpose I/O with IOC and WPU.
CMOS PWM output.
ST
—
CLC input.
CMOS CWG primary output.
A/D Channel input.
—
AN
ST
TTL
—
—
ICSPDAT
RA1
CMOS ICSP™ Data I/O.
RA1/PWM2/CLC1/CWG1B/AN1/
CLKIN/ICSPCLK/NCO1CLK
CMOS General purpose I/O with IOC and WPU.
CMOS PWM output.
PWM2
CLC1
CLC output.
—
CMOS
CWG1B
AN1
—
CMOS CWG complementary output.
AN
ST
ST
ST
TTL
ST
ST
—
—
—
—
—
A/D Channel input.
CLKIN
ICSPCLK
NCO1CLK
RA2
External Clock input (EC mode).
ICSP™ Programming Clock.
Numerical Controlled Oscillator external clock input.
RA2/INT/T0CKI/NCO1/CLC1IN1/
CLKR/AN2/CWG1FLT
CMOS General purpose I/O with IOC and WPU.
INT
—
—
External interrupt.
Timer0 clock input.
T0CKI
NCO1
CLC1IN1
CLKR
AN2
CMOS Numerically Controlled Oscillator output.
CLC input.
CMOS Clock Reference output.
ST
—
—
AN
ST
—
—
—
—
—
—
—
A/D Channel input.
Complementary Waveform Generator Fault 1 source input.
General purpose input.
CWG1FLT
RA3
RA3/MCLR/VPP
TTL
ST
MCLR
VPP
Master Clear with internal pull-up.
Programming voltage.
HV
VDD
VSS
VDD
Power
Power
Positive supply.
VSS
Ground reference.
Legend: AN = Analog input or output
TTL = CMOS input with TTL levels
HV = High Voltage
CMOS = CMOS compatible input or output
ST = CMOS input with Schmitt Trigger levels
DS40001585D-page 8
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
2.1
Program Memory Organization
2.0
MEMORY ORGANIZATION
The mid-range core has a 13-bit program counter
capable of addressing 8K x 14 program memory space.
This device family only implements up to 512 words of
the 8K program memory space. Table 2-1 shows the
memory sizes implemented for the PIC10(L)F320/322
family. Accessing a location above these boundaries will
cause a wrap-around within the implemented memory
space. The Reset vector is at 0000h and the interrupt
vector is at 0004h (see Figures 2-1, and 2-2).
These devices contain the following types of memory:
• Program Memory
- Configuration Word
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
TABLE 2-1:
Device
DEVICE SIZES AND ADDRESSES
Program Memory
Space (Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range (1)
PIC10(L)F320
PIC10(L)F322
256
512
00FFh
01FFh
0080h-00FFh
0180h-01FFh
Note 1: High-endurance Flash applies to low byte of each address in the range.
2011-2015 Microchip Technology Inc.
DS40001585D-page 9
PIC10(L)F320/322
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC10(L)F320
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC10(L)F322
PC<12:0>
13
PC<12:0>
13
CALL
RETURN, RETLW
CALL,
RETURN, RETLW
RETFIE
RETFIE
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 8
Reset Vector
Stack Level 8
Reset Vector
0000h
0000h
Interrupt Vector
Page 0
Interrupt Vector
Page 0
0004h
0005h
0004h
0005h
On-chip
Program
Memory
On-chip
Program
Memory
00FFh
0100h
Rollover to Page 0
01FFh
0200h
Rollover to Page 0
Rollover to Page 0
Rollover to Page 0
FFFh
FFFh
DS40001585D-page 10
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
2.2.1
GENERAL PURPOSE REGISTER
FILE
2.2
Data Memory Organization
The data memory is in one bank, which contains the
General Purpose Registers (GPR) and the Special
Function Registers (SFR). The RP<1:0> bits of the
STATUS register are the bank select bits.
The register file is organized as 64 x 8 in the
PIC10(L)F320/322. Each register is accessed, either
directly or indirectly, through the File Select Register
(FSR) (see Section 2.4 “Indirect Addressing, INDF
and FSR Registers”).
RP1 RP0
0
0
Bank 0 is selected
2.2.2
SPECIAL FUNCTION REGISTERS
The bank extends up to 7Fh (128 bytes). The lower
locations of the bank are reserved for the Special Func-
tion Registers. Above the Special Function Registers
are the General Purpose Registers, implemented as
Static RAM.
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-3). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
2011-2015 Microchip Technology Inc.
DS40001585D-page 11
PIC10(L)F320/322
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’(where u= unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affect-
ing any Status bits (see Section 23.0 “Instruction Set
Summary”).
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC10(L)F320 and
should be maintained as clear. Use of
these bits is not recommended, since this
may affect upward compatibility with
future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction.
DS40001585D-page 12
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 2-1:
STATUS: STATUS REGISTER
R/W-0/0
IRP
R/W-0/0
RP1
R/W-0/0
RP0
R-1/q
TO
R-1/q
PD
R/W-x/u
Z
R/W-x/u
DC
R/W-x/u
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
IRP: Reserved(2)
RP<1:0>: Reserved(2)
TO: Time-out bit
bit 6-5
bit 4
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-Down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of
the source register.
2: Maintain as ‘0’.
2011-2015 Microchip Technology Inc.
DS40001585D-page 13
PIC10(L)F320/322
2.2.3
DEVICE MEMORY MAPS
The memory maps for PIC10(L)F320/322 are as shown
in Table 2-2.
TABLE 2-2:
PIC10(L)F320/322 MEMORY MAP (BANK 0)
(*)
PMADRL
PMADRH
PMDATL
INDF
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
3Dh
3Eh
3Fh
40h
60h
TMR0
PCL
STATUS
FSR
PMDATH
PMCON1
PMCON2
CLKRCON
NCO1ACCL
NCO1ACCH
PORTA
TRISA
LATA
ANSELA
WPUA
PCLATH
INTCON
PIR1
NCO1ACCU
NCO1INCL
NCO1INCH
Reserved
PIE1
NCO1CON
NCO1CLK
Reserved
General
Purpose
Registers
General
Purpose
Registers
OPTION_REG 0Eh
PCON
OSCCON
TMR2
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
WDTCON
32 Bytes
32 Bytes
CLC1CON
CLC1SEL1
CLC1SEL2
CLC1POL
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CWG1CON0
CWG1CON1
CWG1CON2
CWG1DBR
CWG1DBF
VREGCON
BORCON
PR2
T2CON
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
IOCAP
IOCAN
IOCAF
FVRCON
ADRES
ADCON
5Fh
7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
*
= Not a physical register.
DS40001585D-page 14
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 2-3:
SPECIAL FUNCTION REGISTER SUMMARY (BANK 0)
Value on
POR, BOR other resets
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
xxxx xxxx xxxx xxxx
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
---- xxxx ---- uuuu
---- 1111 ---- 1111
---- -xxx ---- -uuu
---- -111 ---- -111
---- 1111 ---- 1111
---- ---0 ---- ---0
0000 0000 0000 000u
-0-0 0-0- -0-0 0-0-
-0-0 0-0- -0-0 0-0-
1111 1111 uuuu uuuu
---- --qq ---- --uu
-110 0-00 -110 0-00
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
xx-- ---- uu-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
xx-- ---- uu-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
---- 0000 ---- 0000
---- 0000 ---- 0000
---- 0000 ---- 0000
0x00 --00 0x00 --00
xxxx xxxx uuuu uuuu
TMR0
PCL
Program Counter (PC) Least Significant Byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PORTA
TRISA
LATA
—
—
—
—
—
—
—
RA3
RA2
TRISA2
LATA2
ANSA2
WPUA2
—
RA1
TRISA1
LATA1
ANSA1
WPUA1
—
RA0
TRISA0
LATA0
ANSA0
WPUA0
PCLH0
IOCIF
—
(1)
—
—
—
—
—
—
—
—
ANSELA
WPUA
PCLATH
INTCON
PIR1
—
—
—
—
—
—
—
—
—
WPUA3
—
—
—
—
GIE
—
PEIE
ADIF
ADIE
INTEDG
—
TMR0IE
—
INTE
NCO1IF
NCO1IE
T0SE
—
IOCIE
CLC1IF
CLC1IE
PSA
TMR0IF
—
INTF
TMR2IF
TMR2IE
PS<2:0>
POR
PIE1
—
—
—
—
OPTION_REG WPUEN
T0CS
—
PCON
—
—
—
—
—
BOR
OSCCON
TMR2
IRCF<2:0>
HFIOFR
LFIOFR
HFIOFS
Timer2 Module Register
Timer2 Period Register
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PR2
T2CON
—
TOUTPS<3:0>
TMR2ON
—
T2CKPS<1:0>
PWM1DCL
PWM1DCH
PWM1CON
PWM2DCL
PWM2DCH
PWM2CON
IOCAP
PWM1DCL<1:0>
—
—
—
—
—
PWM1DCH<7:0>
PWM1EN PWM1OE PWM1OUT PWM1POL
PWM2DCL<1:0>
—
—
—
—
—
—
—
—
—
—
PWM2DCH<7:0>
PWM2EN PWM2OE PWM2OUT PWM2POL
—
—
—
—
—
—
—
—
—
—
—
—
IOCAP3
IOCAN3
IOCAF3
—
IOCAP2
IOCAN2
IOCAF2
—
IOCAP1
IOCAN1
IOCAF1
IOCAP0
IOCAN0
IOCAF0
IOCAN
IOCAF
—
—
—
—
FVRCON
ADRES
FVREN
FVRRDY
TSEN
TSRNG
ADFVR<1:0>
A/D Result Register
CHS<2:0>
GO/
DONE
1Fh
ADCON
ADCS<2:0>
ADON
0000 0000 0000 0000
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
Unimplemented, read as ‘1’.
2011-2015 Microchip Technology Inc.
DS40001585D-page 15
PIC10(L)F320/322
TABLE 2-3:
SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED)
Value on
POR, BOR other resets
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0 (Continued)
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
PMADRL
PMADRH
PMDATL
PMADR<7:0>
—
0000 0000 0000 0000
—
—
—
—
—
—
PMADR8 ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
PMDAT<7:0>
PMDATH
PMCON1
PMCON2
CLKRCON
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
—
—
—
—
PMDAT<13:8>
WRERR WREN
--xx xxxx --uu uuuu
CFGS
LWLO
FREE
WR
RD
—
1000 0000 1000 q000
0000 0000 0000 0000
-0-- ---- -0-- ----
0000 0000 0000 0000
0000 0000 0000 0000
---- 0000 ---- 0000
0000 0001 0000 0001
0000 0000 0000 0000
Program Memory Control Register 2 (not a physical register)
—
CLKROE
—
—
—
—
—
NCO1 Accumulator <7:0>
NCO1 Accumulator <15:8>
—
NCO1 Accumulator <19..16>
NCO1 Increment <7:0>
NCO1 Increment <15:8>
Unimplemented
—
—
NCO1CON
NCO1CLK
Reserved
WDTCON
N1EN
N1OE
N1PWS<2:0>
N1OUT
N1POL
—
—
—
—
—
—
N1PFM
0000 ---0 00x0 ---0
000- --00 000- --00
xxxx xxxx uuuu uuuu
N1CKS<1:0>
Reserved
—
—
WDTPS<4:0>
SWDTEN --01 0110 --01 0110
LC1EN
LC1OE
LC1OUT LC1INTP
LC1D2S<2:0>
LC1INTN
LC1MODE<2:0>
LC1D1S<2:0>
LC1D3S<2:0>
00x0 -000 00x0 -000
CLC1CON
CLC1SEL0
CLC1SEL1
CLC1POL
CLC1GLS0
CLC1GLS1
CLC1GLS2
32h
33h
34h
35h
36h
37h
38h
39h
—
—
—
—
-xxx -xxx -uuu -uuu
-xxx -xxx -uuu -uuu
LC1D4S<2:0>
LC1POL
—
—
—
LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0--0 0000 0--0
xxxx --xx uuuu --uu
CLC1GLS3
G1EN
G1OEB
G1OEA
G1POLB
G1POLA
CWG1CON0
—
—
G1CS0
G1IS<1:0>
G1ASDLB<1:0>
G1ASDLA<1:0>
3Ah
3Bh
3Ch
3Dh
CWG1CON1
CWG1CON2
CWG1DBR
CWG1DBF
—
—
—
—
G1ASE G1ARSEN
—
—
G1ASDCLC1 G1ASDFLT xx-- --xx uu-- --uu
--xx xxxx --uu uuuu
—
—
—
—
CWG1DBR<5:0>
CWG1DBF<5:0>
--xx xxxx --uu uuuu
3Eh
—
—
—
—
—
—
—
—
—
VREGPM1
—
Reserved ---- --01 ---- --01
BORRDY 10-- ---q uu-- ---u
VREGCON
BORCON
3Fh
SBOREN
BORFS
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
Unimplemented, read as ‘1’.
DS40001585D-page 16
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
2.3.2
STACK
2.3
PCL and PCLATH
All devices have an 8-level x 13-bit wide hardware
stack (see Figure 2-1). The stack space is not part of
either program or data space and the Stack Pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALLinstruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-3 shows the two
situations for the loading of the PC. The upper example
in Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> PCH). The lower example in
Figure 2-3 shows how the PC is loaded during a CALLor
GOTOinstruction (PCLATH<4:3> PCH).
of a RETURN,
RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Instruction with
Note 1: There are no Status bits to indicate Stack
12
8
7
0
PCL as
Overflow or Stack Underflow conditions.
Destination
PC
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
8
PCLATH<4:0>
PCLATH
5
ALU Result
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
2.4
Indirect Addressing, INDF and
FSR Registers
PCLATH<4:3>
PCLATH
11
2
OPCODE <10:0>
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-4.
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
INDIRECT ADDRESSING
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower eight bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
MOVLW
MOVWF
0x40
FSR
;initialize pointer
;to RAM
NEXT
CLRF
INCF
BTFSS
GOTO
INDF
FSR
;clear INDF register
;inc pointer
FSR,7
NEXT
;all done?
;no clear next
;yes continue
CONTINUE
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2011-2015 Microchip Technology Inc.
DS40001585D-page 17
PIC10(L)F320/322
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322
Direct Addressing
From Opcode
Indirect Addressing
7
6
0
0
File Select Register
Location Select
Location Select
00h
Data
Memory
7Fh
Bank 0
For memory map detail, see Figure 2-2.
DS40001585D-page 18
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
3.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Word
and Device ID.
3.1
Configuration Word
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word at
2007h.
2011-2015 Microchip Technology Inc.
DS40001585D-page 19
PIC10(L)F320/322
3.2
Register Definitions: Configuration Word
REGISTER 3-1:
CONFIG: CONFIGURATION WORD
R/P-1/1
LVP
U-1
—
R/P-1/1
R/P-1/1
R/P-1/1
BORV
R/P-1/1
LPBOR
WRT<1:0>
bit 13
bit 8
R/P-1/1
FOSC
R/P-1/1
CP
R/P-1/1
MCLRE
R/P-1/1
PWRTE
R/P-1/1
R/P-1/1
R/P-1/1
R/P-1/1
WDTE<1:0>
BOREN<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
bit 13
Unimplemented: Read as ‘1’
bit 12-11
WRT<1:0>: Flash Memory Self-Write Protection bits
256 W Flash memory: PIC10(L)F320:
11=Write protection off
10=000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control
01=000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control
00=000h to 0FFh write-protected, no addresses may be modified by PMCON control
512 W Flash memory: PIC10(L)F322:
11=Write protection off
10=000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control
01=000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control
00=000h to 1FFh write-protected, no addresses may be modified by PMCON control
bit 10
bit 9
bit 8
bit 7
bit 6
BORV: Brown-out Reset Voltage Selection bit
1= Brown-out Reset voltage (VBOR), low trip point selected.
0= Brown-out Reset voltage (VBOR), high trip point selected.
LPBOR: Low-Power Brown-out Reset Enable bit
1= Low-power Brown-out Reset is enabled
0= Low-power Brown-out Reset is disabled
LVP: Low-Voltage Programming Enable bit
1= Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR.
0= High Voltage on MCLR/VPP must be used for programming
CP: Code Protection bit(2)
1= Program memory code protection is disabled
0= Program memory code protection is enabled
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUA3 bit.
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Once enabled, code-protect can only be disabled by bulk erasing the device.
3: See VBOR parameter for specific trip point voltages.
DS40001585D-page 20
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 3-1:
CONFIG: CONFIGURATION WORD (CONTINUED)
bit 5
PWRTE: Power-up Timer Enable bit(1)
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
bit 2-1
bit 0
BOREN<1:0>: Brown-out Reset Enable bits
11= Brown-out Reset enabled; SBOREN bit is ignored
10= Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored
01= Brown-out Reset controlled by the SBOREN bit in the BORCON register
00= Brown-out Reset disabled; SBOREN bit is ignored
FOSC: Oscillator Selection bit
1= EC on CLKIN pin
0= INTOSC oscillator I/O function available on CLKIN pin
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Once enabled, code-protect can only be disabled by bulk erasing the device.
3: See VBOR parameter for specific trip point voltages.
2011-2015 Microchip Technology Inc.
DS40001585D-page 21
PIC10(L)F320/322
3.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory protection are controlled independently.
Internal access to the program memory and data
memory are unaffected by any code protection setting.
3.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 3.4
“Write
Protection” for more information.
3.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Word define the
size of the program memory block that is protected.
3.5
User ID
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 3.6 “Device ID and Revision ID” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC10(L)F320/322 Flash Memory Programming
Specification” (DS41572).
DS40001585D-page 22
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
3.6
Device ID and Revision ID
The memory location 2006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 9.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
3.7
Register Definitions: Device and Revision
REGISTER 3-2:
DEVID: DEVICE ID REGISTER(1)
R
R
R
R
R
R
R
R
R
R
DEV<8:3>
bit 13
bit 8
bit 0
R
R
R
R
DEV<2:0>
REV<4:0>
bit 7
Legend:
R = Readable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 13-5
DEV<8:0>: Device ID bits
DEVID<13:0> Values
Device
DEV<8:0>
REV<4:0>
PIC10F320
PIC10LF320
PIC10F322
PIC10LF322
10 1001 101
10 1001 111
10 1001 100
10 1001 110
x xxxx
x xxxx
x xxxx
x xxxx
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision.
Note 1: This location cannot be written.
2011-2015 Microchip Technology Inc.
DS40001585D-page 23
PIC10(L)F320/322
The system can be configured to use an internal
calibrated high-frequency oscillator as clock source, with
a choice of selectable speeds via software.
4.0
4.1
OSCILLATOR MODULE
Overview
Clock source modes are configured by the FOSC bit in
Configuration Word (CONFIG).
The oscillator module has a variety of clock sources and
selection features that allow it to be used in a range of
applications while maximizing performance and
minimizing power consumption. Figure 4-1 illustrates a
block diagram of the oscillator module.
1. EC oscillator from CLKIN.
2. INTOSC oscillator, CLKIN not enabled.
FIGURE 4-1:
PIC10(L)F320/322 CLOCK SOURCE BLOCK DIAGRAM
IRCF<2:0>
3
HFINTOSC
16 MHz
HFIOFR(1)
HFIOFS(1)
111
110
101
100
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
INTOSC
011
010
001
250 kHz
31 kHz
FOSC
000
(Configuration
LFINTOSC
31 kHz
Word)
LFIOFR(1)
0
System Clock
(CPU and
EC
Peripherals)
1
CLKIN
CLKR
CLKROE
Note 1: HFIOFR, HFIOFS and LFIOFR are Status bits in the OSCCON register.
DS40001585D-page 24
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
4.3.2
FREQUENCY SELECT BITS (IRCF)
4.2
Clock Source Modes
The output of the 16 MHz HFINTOSC is connected to
a divider and multiplexer (see Figure 4-1). The Internal
Oscillator Frequency Select bits (IRCF) of the
OSCCON register select the frequency output of the
internal oscillator:
Clock source modes can be classified as external or
internal.
• Internal clock source (INTOSC) is contained
within the oscillator module, which has eight
selectable output frequencies, with a maximum
internal frequency of 16 MHz.
• HFINTOSC
- 16 MHz
• The External Clock mode (EC) relies on an
external signal for the clock source.
- 8 MHz (default after Reset)
- 4 MHz
The system clock can be selected between external or
internal clock sources via the FOSC bit of the
Configuration Word.
- 2 MHz
- 1 MHz
- 500 kHz
4.3
Internal Clock Modes
- 250 kHz
• LFINTOSC
- 31 kHz
The internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators that are used to generate all internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC) and the 31 kHz
(LFINTOSC).
Note:
Following any Reset, the IRCF<2:0> bits
of the OSCCON register are set to ‘110’
and the frequency selection is set to
8 MHz. The user can modify the IRCF bits
to select a different frequency.
The HFINTOSC consists of a primary and secondary
clock. The secondary clock starts first with rapid start-
up time, but low accuracy. The secondary clock ready
signal is indicated with the HFIOFR bit of the OSCCON
register. The primary clock follows with slower start-up
time and higher accuracy. The primary clock is stable
when the HFIOFS bit of the OSCCON register bit goes
high.
There is no delay when switching between HFINTOSC
frequencies with the IRCF bits. This is because the
switch involves only a change to the frequency output
divider.
Start-up delay specifications are located in
Section 24.0 “Electrical Specifications”.
4.3.1
INTOSC MODE
When the FOSC bit of the Configuration Word is
cleared, the INTOSC mode is selected. When INTOSC
is selected, CLKIN pin is available for general purpose
I/O. See Section 3.0 “Device Configuration” for
more information.
2011-2015 Microchip Technology Inc.
DS40001585D-page 25
PIC10(L)F320/322
4.4
Register Definitions: Reference Clock Control
REGISTER 4-1:
CLKRCON – REFERENCE CLOCK CONTROL REGISTER
U-0
—
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
CLKROE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
q = Value depends on condition
bit 7
bit 6
Unimplemented: Read as ‘0’
CLKROE: Reference Clock Output Enable bit
1= Reference Clock output (CLKR), regardless of TRIS
0= Reference Clock output disabled
bit 5-0
Unimplemented: Read as ‘0’
4.5
Register Definitions: Oscillator Control
REGISTER 4-2:
OSCCON: OSCILLATOR CONTROL REGISTER
U-0
—
R/W-1/1
R/W-1/1
R/W-0/0
R-0/0
U-0
—
R-0/0
R-0/0
IRCF<2:0>
HFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF<2:0>: INTOSC (FOSC) Frequency Select bits
111= 16 MHz
110= 8 MHz (default value)
101= 4 MHz
100= 2 MHz
011= 1 MHz
010= 500 kHz
001= 250 kHz
000= 31 kHz (LFINTOSC)
bit 3
HFIOFR: High-Frequency Internal Oscillator Ready bit
1= 16 MHz Internal Oscillator (HFINTOSC) is ready
0= 16 MHz Internal Oscillator (HFINTOSC) is not ready
bit 2
bit 1
Unimplemented: Read as ‘0’
LFIOFR: Low-Frequency Internal Oscillator Ready bit
1= 31 kHz Internal Oscillator (LFINTOSC) is ready
0= 31 kHz Internal Oscillator (LFINTOSC) is not ready
bit 0
HFIOFS: High-Frequency Internal Oscillator Stable bit
1= 16 MHz Internal Oscillator (HFINTOSC) is stable
0= 16 MHz Internal Oscillator (HFINTOSC) is not stable
DS40001585D-page 26
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
4.6
External Clock Mode
4.6.1
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the CLKIN input.
TABLE 4-1:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLKRCON
OSCCON
—
—
CLKROE
—
—
—
—
—
—
26
26
IRCF<2:0>
HFIOFR
LFIOFR
HFIOFS
—
Legend:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by ECWG.
TABLE 4-2:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
—
—
—
WRT<1:0>
WDTE<1:0>
BORV
LPBOR
13:8
7:0
LVP
CONFIG
20
CP
MCLRE
PWRTE
BOREN<1:0>
FOSC
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
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5.0
RESETS
There are multiple ways to reset this device:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
• Low-Power Brown-Out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP™ Programming Mode Exit
MCLRE
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
PWRT
R
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1: See Table 5-1 for BOR active conditions.
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5.1
Power-On Reset (POR)
5.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Word. The four operating modes are:
• BOR is always on
5.1.1
POWER-UP TIMER (PWRT)
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
The Power-up Timer provides a nominal 64 ms time-
out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word.
Refer to Table 5-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Register 3-1.
A VDD noise rejection filter prevents the BOR from trig-
gering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 5-2 for more information.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 5-1:
BOREN<1:0>
11
BOR OPERATING MODES
Device Operation upon:
Release of POR/Wake- up from Sleep
SBOREN
Device Mode
BOR Mode
X
X
X
Awake
Sleep
X
Active
Active
Waits for BOR ready(1) (BORRDY = 1)
10
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready(1) (BORRDY = 1)
Begins immediately (BORRDY = x)
Disabled
Active
1
0
X
01
00
X
Disabled
Disabled
X
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
5.2.1
BOR IS ALWAYS ON
5.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
When the BOREN bits of Configuration Word are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device start-
up is not delayed by the BOR ready condition or the
VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
5.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Word are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
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FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
5.3
Register Definition: BOR Control
REGISTER 5-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
R/W-0/u
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R-q/u
(1)
BORFS
—
BORRDY
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Word 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Word = 01:
1= BOR enabled
0= BOR disabled
(1)
BORFS: Brown-out Reset Fast Start bit
If BOREN<1:0> = 11(Always on) or BOREN<1:0> = 00(Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10(Disabled in Sleep) or BOREN<1:0> = 01(Under software control):
1= Band gap is forced on always (covers Sleep/wake-up/operating cases)
0= Band gap operates normally, and may turn off
bit 5-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Word.
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5.4
Low-Power Brown-out Reset
(LPBOR)
5.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 8.0
“Watchdog Timer” for more information.
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.7
Programming Mode ICSP Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.8
Power-Up Timer
5.4.1
ENABLING LPBOR
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
The LPBOR is controlled by the LPBOR bit of
Configuration Word. When the device is erased, the
LPBOR module defaults to enabled.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word.
5.4.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal which goes to
the PCON register and to the power control block.
5.9
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. MCLR must be released (if enabled).
5.5
MCLR
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 4.0 “Oscillator Module” for more informa-
tion.
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE and the LVP bit of Configuration Word (Table 5-
2).
The Power-up Timer runs independently of MCLR Reset.
If MCLR is kept low long enough, the Power-up Timer will
expire. Upon bringing MCLR high, the device will begin
execution after 10 FOSC cycles (see Figure 5-3). This is
useful for testing purposes or to synchronize more than
one device operating in parallel.
TABLE 5-2:
MCLRE
MCLR CONFIGURATION
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
5.5.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
A Reset does not drive the MCLR pin low.
5.5.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control.
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FIGURE 5-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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5.10 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 5-3 and Table 5-4 show the Reset
conditions of these registers.
TABLE 5-3:
POR
RESET STATUS BITS AND THEIR SIGNIFICANCE
BOR
TO
PD
Condition
0
u
u
u
u
u
x
0
u
u
u
u
1
1
0
0
u
1
1
1
u
0
u
0
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
TABLE 5-4:
RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
0001 1000
000u uuuu
---- --0x
---- --uu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
0001 0uuu
0000 uuuu
0000 0uuu
0001 1uuu
0001 0uuu
---- --uu
---- --uu
---- --uu
---- --u0
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
PC + 1(1)
Interrupt Wake-up from Sleep
---- --uu
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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5.11 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
The PCON register bits are shown in Register 5-2.
5.12 Register Definition: Power Control
REGISTER 5-2:
PCON: POWER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W/HC-q/u R/W/HC-q/u
POR BOR
bit 0
bit 7
Legend:
HC = Bit is cleared by hardware
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-2
bit 1
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
TABLE 5-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
BORCON SBOREN BORFS
—
—
—
—
—
—
—
Z
—
POR
DC
BORRDY
BOR
30
34
13
48
PCON
—
IRP
—
—
RP1
—
—
PD
STATUS
WDTCON
RP0
TO
C
WDTPS<4:0>
SWDTEN
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
TABLE 5-6: SUMMARY OF CONFIGURATION WORD WITH RESETS
Register
on Page
Name
Bits Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
WRT<1:0>
WDTE<1:0>
BORV
LPBOR
LVP
CONFIG
20
CP
MCLRE PWRTE
BOREN<1:0>
FOSC
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Reset.
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6.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Context Saving during Interrupts
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 6-1.
FIGURE 6-1:
INTERRUPT LOGIC
Rev. 10-000010A
1/13/2014
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
IOCIF
IOCIE
Interrupt
to CPU
PEIE
GIE
PIRn<7>
PIEn<7>
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6.1
Operation
6.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 6-2 and Section 6.3 “Interrupts
During Sleep” for more details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 register)
The INTCON and PIR1 registers record individual inter-
rupts via interrupt flag bits. Interrupt flag bits will be set,
regardless of the status of the GIE, PEIE and individual
interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 6-2:
INTERRUPT LATENCY
INTOSC
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC-1
PC
PC+1
0004h
0005h
PC
1 Cycle Instruction at PC
Execute
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC+1/FSR
ADDR
New PC/
PC+1
PC-1
PC
0004h
0005h
PC
Execute
2 Cycle Instruction at PC
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
NOP
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
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FIGURE 6-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTOSC
CLKR
(3)
INT pin
INTF
(1)
(1)
(2)
(4)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Forced NOP
Forced NOP
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 24.0 “Electrical Specifications”.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.
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6.3
Interrupts During Sleep
6.5
Context Saving During Interrupts
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
holding
registers
W_TEMP
and
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 7.0 “Power-
Down Mode (Sleep)” for more details.
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Table 1-2). This makes context save and
restore operations simpler. The code shown in
Example 6-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
6.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
Note:
These devices do not require saving the
PCLATH. However, if computed GOTOs
are used in both the ISR and the main
code, the PCLATH must be saved and
restored in the ISR.
EXAMPLE 6-1:
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
W_TEMP
STATUS,W
;Copy W to TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Save status to bank zero STATUS_TEMP register
MOVWF
:
STATUS_TEMP
:(ISR)
:
;Insert user code here
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
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6.6
Interrupt Control Registers
REGISTER 6-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF
R/W-0/0
INTF
R-0/0
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the INT external interrupt
0= Disables the INT external interrupt
IOCIE: Interrupt-on-Change Interrupt Enable bit
1= Enables the interrupt-on-change interrupt
0= Disables the interrupt-on-change interrupt
TMR0IF: Timer0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1= When at least one of the interrupt-on-change pins changed state
0= None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register
have been cleared by software.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
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REGISTER 6-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
—
R/W-0/0
ADIE
U-0
—
R/W-0/0
NCO1IE
R/W-0/0
CLC1IE
U-0
—
R/W-0/0
TMR2IE
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
bit 5
bit 4
Unimplemented: Read as ‘0’
NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit
1= Enables the NCO overflow interrupt
0= Disables the NCO overflow interrupt
bit 3
CLC1IE: Configurable Logic Block Interrupt Enable bit
1= Enables the CLC interrupt
0= Disables the CLC interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 Match interrupt
0= Disables the TMR2 to PR2 Match interrupt
bit 0
Unimplemented: Read as ‘0’
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
2011-2015 Microchip Technology Inc.
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PIC10(L)F320/322
REGISTER 6-3:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
—
R/W-0/0
ADIF
U-0
—
R/W-0/0
NCO1IF
R/W-0/0
CLC1IF
U-0
—
R/W-0/0
TMR2IF
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Converter Interrupt Flag bit
1= The A/D conversion completed
0= The A/D conversion is not complete
bit 5
bit 4
Unimplemented: Read as ‘0’
NCO1IF: Numerically Controlled Oscillator Interrupt Flag bit
1= NCO1 overflow occurred (must be cleared in software)
0= No NCO1 overflow
bit 3
CLC1IF: Configurable Logic Block Rising Edge Interrupt Flag bit
1= CLC interrupt occurred (must be cleared in software)
0= No CLC Interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match
Note: The match must occur the number of times specified by the TMR2 postscaler (Register 17-1).
bit 0
Unimplemented: Read as ‘0’
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
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TABLE 6-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCAF
IOCAN
IOCAP
GIE
—
PEIE
—
TMR0IE
—
INTE
—
IOCIE
TMR0IF
INTF
IOCIF
40
76
75
75
95
41
42
IOCAF3 IOCAF2 IOCAF1 IOCAF0
IOCAN3 IOCAN2 IOCAN1 IOCAN0
IOCAP3 IOCAP2 IOCAP1 IOCAP0
—
—
—
—
—
—
—
—
OPTION_REG WPUEN INTEDG
T0CS
—
T0SE
PSA
PS<2:0>
TMR2IE
TMR2IF
—
—
—
PIE1
PIR1
ADIE
ADIF
NCO1IE CLC1IE
NCO1IF CLC1IF
—
—
—
—
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
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PIC10(L)F320/322
7.1
Wake-up from Sleep
7.0
POWER-DOWN MODE (SLEEP)
The device can wake-up from Sleep through one of the
following events:
The Power-Down mode is entered by executing a
SLEEPinstruction.
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
Upon entering Sleep mode, the following conditions
exist:
3. POR Reset
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
4. Watchdog Timer, if enabled
5. Any external interrupt
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
6. Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 5.10
“Determining the Cause of a Reset”.
6. ADC is unaffected, if the dedicated FRC clock is
selected.
7. I/O ports maintain the status they had before
SLEEPwas executed (driving high, low or high-
impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEPinstruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
8. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following condi-
tions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The Complementary Waveform Generator (CWG) and
the Numerically Controlled Oscillator (NCO) modules
can utilize the HFINTOSC oscillator as their respective
clock source. Under certain conditions, when the
HFINTOSC is selected for use with the CWG or NCO
modules, the HFINTOSC will remain active during
Sleep. This will have a direct effect on the Sleep mode
current. Please refer to 21.0 “Complementary Wave-
form Generator (CWG) Module” and 20.0 “Numeri-
cally Controlled Oscillator (NCO) Module” for more
information.
• CWG and NCO modules using HFINTOSC
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 12.0
“Fixed Voltage Reference (FVR)” for more informa-
tion on these modules.
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• If the interrupt occurs during or after the
execution of a SLEEPinstruction
7.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
- SLEEPinstruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
• If the interrupt occurs before the execution of a
SLEEPinstruction
- SLEEPinstruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
- PD bit of the STATUS register will not be
cleared.
FIGURE 7-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
(3)
CLKOUT(2)
TOST
Interrupt Latency(4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Forced NOP
Forced NOP
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
TOST= 1024 TOSC; This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4 “Low-
Power Brown-out Reset (LPBOR)”.).
2:
3:
4:
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STATUS
IRP
—
RP1
—
RP0
TO
PD
Z
DC
C
13
48
WDTCON
WDTPS<4:0>
SWDTEN
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
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8.0
WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 8-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
Prescaler WDT
WDTE<1:0> = 11
LFINTOSC
WDT Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
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8.1
Independent Clock Source
8.3
Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 24.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the time-
out period from 1 ms to 256 seconds (nominal). After a
Reset, the default time-out period is 2 seconds.
8.4
Clearing the WDT
The WDT is cleared when any of the following
conditions occur:
8.2
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word. See Table 8-1.
• Any Reset
• CLRWDTinstruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail
8.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Word are set to
‘11’, the WDT is always on.
• WDT is disabled
WDT protection is active during Sleep.
See Table 8-2 for more information.
8.2.2
WDT IS OFF IN SLEEP
8.5
Operation During Sleep
When the WDTE bits of Configuration Word are set to
‘10’, the WDT is on, except in Sleep.
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
WDT protection is not active during Sleep.
When the device exits Sleep, the WDT is cleared
again.
8.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See Section 2.0 “Memory Organization” and
Register 2-1 for more information.
WDT protection is unchanged by Sleep. See Table 8-1
for more details.
TABLE 8-1:
WDTE<1:0>
WDT OPERATING MODES
Device
Mode
WDT
Mode
SWDTEN
11
10
X
X
X
Active
Active
Awake
Sleep Disabled
1
0
X
Active
X
01
Disabled
00
X
Disabled
TABLE 8-2:
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Cleared
Exit Sleep
Change INTOSC divider (IRCF bits)
Unaffected
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8.6
Watchdog Control Register
REGISTER 8-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS<4:0>
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010 = 1:8388608 (223) (Interval 256s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01100 = 1:131072 (217) (Interval 4s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01010 = 1:32768 (Interval 1s nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00000 = 1:32 (Interval 1 ms nominal)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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TABLE 8-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
STATUS
—
IRP
—
IRCF<2:0>
RP0
HFIOFR
PD
—
Z
LFIOFR HFIOFS
26
13
48
RP1
—
TO
DC
C
WDTCON
WDTPS<4:0>
SWDTEN
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.
TABLE 8-4:
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page
Name
Bits Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
WRT<1:0>
WDTE<1:0>
BORV
LPBOR
LVP
CONFIG
20
CP
MCLRE PWRTE
BOREN<1:0>
FOSC
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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PIC10(L)F320/322
9.1.1
PMCON1 AND PMCON2
REGISTERS
9.0
FLASH PROGRAM MEMORY
CONTROL
PMCON1 is the control register for Flash program
memory accesses.
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
• PMCON1
• PMCON2
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 9-bit address of the program memory
location being read.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the
device.
9.2
Flash Program Memory Overview
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Word)
and write protection (WRT<1:0> bits in Configuration
Word).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. How-
ever, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Word.
9.1
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 512 words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
See Table 9-1 for Erase Row size and the number of
write latches for Flash program memory.
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PIC10(L)F320/322
FIGURE 9-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
TABLE 9-1:
Device
FLASH MEMORY
ORGANIZATION BY DEVICE
Write
Row Erase
Latches
(words)
(words)
Start
Read Operation
PIC10(L)F320
PIC10(L)F322
16
16
Select
Program or Configuration Memory
(CFGS)
9.2.1
READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1. Write the desired address to the
PMADRH:PMADRL register pair.
2. Clear the CFGS bit of the PMCON1 register.
Select
Word Address
(PMADRH:PMADRL)
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
Initiate Read operation
(RD = 1)
Instruction Fetched ignored
NOPexecution forced
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Instruction Fetched ignored
NOP execution forced
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
Data read now in
PMDATH:PMDATL
End
Read Operation
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FIGURE 9-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
PMADRH,PMADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
PMDATH,PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC + 1)
INSTR(PC + 2)
instruction ignored instruction ignored
BSF PMCON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
Forced NOP
Forced NOP
executed here
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 9-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; not required on devices with 1 Bank of SFRs
MOVLW
MOVWF
MOVLW
MOVWF
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
; Do not select Configuration Space
; Initiate read
; Ignored (Figure 9-2)
; Ignored (Figure 9-2)
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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9.2.2
Note:
FLASH MEMORY UNLOCK
SEQUENCE
FIGURE 9-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
A delay of at least 100 s is required after
Power-On Reset (POR) before executing
a Flash memory unlock sequence.
Start
Unlock Sequence
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
Write 055h to
PMCON2
• Row Erase
• Load program memory write latches
Write 0AAh to
PMCON2
• Write of program memory write latches to
program memory
• Write of program memory write latches to User
IDs
Initiate
Write or Erase operation
(WR = 1)
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOPinstruction
Instruction Fetched ignored
NOP execution forced
5. NOPinstruction
Instruction Fetched ignored
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
NOP execution forced
End
Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
2011-2015 Microchip Technology Inc.
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9.2.3
ERASING FLASH PROGRAM
MEMORY
FIGURE 9-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Start
Erase Operation
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register.
Disable Interrupts
(GIE = 0)
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
Select
Program or Configuration Memory
(CFGS)
See Example 9-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
Select Row Address
(PMADRH:PMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 9-3
CPU stalls while
ERASE operation completes
(2ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
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EXAMPLE 9-2:
ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
; Disable ints so required sequences will execute properly
; not required on devices with 1 Bank of SFRs
; Load lower 8 bits of erase address boundary
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
; Load upper 6 bits of erase address boundary
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
; Not configuration space
; Specify an erase operation
; Enable writes
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
NOP
NOP
; NOP instructions are forced as processor starts
; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
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The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
9.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1. Load the address in PMADRH:PMADRL of the
row to be programmed.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
1. Set the WREN bit of the PMCON1 register.
2. Clear the CFGS bit of the PMCON1 register.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 9-5 (row writes to program memory with 16 write
latches) for more details.
3. Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower five bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 9.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 9.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 9-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
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FIGURE 9-5:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
7
1 0 7
4 3
0
7
5
0
7
0
-
-
PMADRH
PMADRL
PMDATH
6
PMDATL
8
-
-
-
-
-
-
-
r4 r3 r2 r1 r0 c3 c2 c1 c0
14
Program Memory Write Latches
4
14
14
14
14
Write Latch #0
00h
Write Latch #1
01h
Write Latch #14 Write Latch #15
0Eh 0Fh
PMADRL<3:0>
14
14
14
14
5
PMADRH<0>:
PMADRL<7:4>
Row
000h
001h
002h
Addr
0000h
0010h
0020h
Addr
0001h
0011h
0021h
Addr
Addr
000Eh
001Eh
002Eh
000Fh
001Fh
002Fh
CFGS = 0
01Eh
01Fh
01E0h
01F0h
01E1h
01F1h
01EEh
01FEh
01EFh
01FFh
Row
Address
Decode
Flash Program Memory
000h
2000h - 2003h
USER ID 0 - 3
2004h - 2005h
reserved
2006h
2007h
2008h
reserved
DEVICEID
REVID
Configuration
Word
CFGS = 1
Configuration Memory
PIC10(L)F320/322
FIGURE 9-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
(word_cnt)
Update the word counter
(word_cnt--)
Write Latches to Flash
Disable Interrupts
(LWLO = 0)
(GIE = 0)
Unlock Sequence
Figure 9-3
Select
Program or Config. Memory
(CFGS)
Yes
Last word to
write ?
CPU stalls while Write
operation completes
(2ms typical)
No
Select Row Address
(PMADRH:PMADRL)
Unlock Sequence
Figure 9-3
Select Write Operation
(FREE = 0)
Disable
Write/Erase Operation
(WREN = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Write Operation
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EXAMPLE 9-3:
WRITING TO FLASH PROGRAM MEMORY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
;
A valid starting address (the least significant bits = '00')
is loaded in ADDRH:ADDRL
;
ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVF
MOVWF
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
DATAADDR,W
FSR
;Load initial address
;
;
;
;Load initial data address
;
LOOP MOVF INDF,W
;Load first data byte into lower
MOVWF
INCF
PMDATL
FSR,F
;
;Next byte
MOVF
MOVWF
INCF
INDF,W
PMDATH
FSR,F
;Load second data byte into upper
;
;
BANKSEL PMCON1
BSF
PMCON1,WREN ;Enable writes
BCF
BTFSC
GOTO
INTCON,GIE
INTCON,GIE
$-2
;Disable interrupts (if using)
;See AN576
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;Start of required write sequence:
;Write 55h
;
;Write 0AAh
;Set WR bit to begin write
;Required to transfer data to the buffer
;registers
NOP
NOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
BSF
PMCON1,WREN ;Disable writes
INTCON,GIE ;Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF
PMADRL, W
INCF
ANDLW
SUBLW
PMADRL,F
0x03
0x03
;Increment address
;Indicates when sixteen words have been programmed
;Change value for different size write blocks
;0x0F = 16 words
;0x0B = 12 words
;0x07 = 8 words
;0x03 = 4 words
BTFSS
GOTO
STATUS,Z
LOOP
;Exit on a match,
;Continue if more data needs to be written
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FIGURE 9-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
9.3
Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Start
Modify Operation
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
Figure 9-2
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
An image of the entire row read
must be stored in RAM
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
Figure 9-4
Write Operation
use RAM image
Figure 9-5
End
Modify Operation
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9.4
User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Word can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<13> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 9-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 9-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 9-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
2000h-2003h
2006h
User IDs
Yes
Yes
Yes
Yes
No
No
Device ID/Revision ID
Configuration Word
2007h
EXAMPLE 9-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; not required on devices with 1 Bank of SFRs
MOVLW
MOVWF
CLRF
PROG_ADDR_LO
PMADRL
PMADRH
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
; Select Configuration Space
; Disable interrupts
; Initiate read
; Executed (See Figure 9-2)
; Ignored (See Figure 9-2)
; Restore interrupts
INTCON,GIE
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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9.5
Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 9-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
Figure 9-2
PMDAT =
RAM image
?
No
Fail
Verify Operation
Yes
No
Last
Word ?
Yes
End
Verify Operation
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9.6
Flash Program Memory Control Registers
REGISTER 9-1:
PMDATL: PROGRAM MEMORY DATA LOW
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
PMDAT<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PMDAT<7:0>: The value of the program memory word pointed to by PMADRH and PMADRL after a
Program Memory Read command.
REGISTER 9-2:
PMDATH: PROGRAM MEMORY DATA HIGH
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
PMDAT<13:8>: The value of the program memory word pointed to by PMADRH and PMADRL after a
Program Memory Read command.
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REGISTER 9-3:
PMADRL: PROGRAM MEMORY ADDRESS LOW
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PMADR<7:0>: Program Memory Read Address low bits
REGISTER 9-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
PMADR8
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-1
bit 0
Unimplemented: Read as ‘0’
PMADR8: Program Memory Read Address High bit
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REGISTER 9-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
—
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0 R/W/HC-0/q(2)
FREE WRERR
R/W-0/0
WREN
R/S/HC-0/0 R/S/HC-0/0
WR RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
Unimplemented: Read as ‘1’
CFGS: Configuration Select bit
1= Access Configuration, User ID and Device ID Registers
0= Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1= Only the addressed program memory write latch is loaded/updated on the next WR command
0= The addressed program memory write latch is loaded/updated and a write of all program memory
write latches will be initiated on the next WR command
bit 4
bit 3
FREE: Program Flash Erase Enable bit
1= Performs an erase operation on the next WR command (hardware cleared upon completion)
0= Performs an write operation on the next WR command
WRERR: Program/Erase Error Flag bit
1= Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0= The program or erase operation completed normally.
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash
WR: Write Control bit
1= Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit
1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0= Does not initiate a program Flash read.
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started
(WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).
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REGISTER 9-6:
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0 W-0/0 W-0/0 W-0/0 W-0/0
Program Memory Control Register 2
W-0/0
W-0/0
W-0/0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 9-3:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
INTCON
PMCON1
PMCON2
PMADRL
GIE
—
PEIE
TMR0IE
LWLO
INTE
IOCIE
TMR0IF
WREN
INTF
WR
IOCIF
RD
40
65
66
64
64
63
63
CFGS
FREE
WRERR
Program Memory Control Register 2
PMADR<7:0>
PMADRH
PMDATL
—
—
—
—
—
—
—
—
—
PMADR8
PMDAT<7:0>
PMDAT<13:8>
PMDATH
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
TABLE 9-4:
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
WRT<1:0>
WDTE<1:0>
BORV
LPBOR
LVP
13:8
7:0
—
—
—
CONFIG
20
CP
MCLR
PWRTE
BOREN<1:0>
FOSC
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
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FIGURE 10-1:
I/O PORT OPERATION
10.0 I/O PORT
Depending on which peripherals are enabled, some or
all of the pins may not be available as general purpose
I/O. In general, when a peripheral is enabled on a port
pin, that pin cannot be used as a general purpose
output. However, the pin can still be read.
Read LATA
TRISA
D
Q
PORTA has three standard registers for its operation.
These registers are:
Write LATA
Write PORTA
CK
Data Register
VDD
• TRISA register (data direction)
• PORTA register (reads the levels on the pins of
the device)
Data Bus
• LATA register (output latch)
I/O pin
Read PORTA
To peripherals
Some ports may have one or more of the following
additional registers. These registers are:
VSS
• ANSELA (analog select)
• WPUA (weak pull-up)
ANSELA
The Data Latch (LATA register) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads of the values held in
the I/O PORT latches, while a read of the PORTA
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELA register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
EXAMPLE 10-1:
INITIALIZING PORTA
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
BANKSEL
CLRF
PORTA
PORTA
;not required on devices with 1 Bank of SFRs
;Init PORTA
BANKSEL
CLRF
LATA
LATA
;not required on devices with 1 Bank of SFRs
;
BANKSEL
CLRF
BANKSEL
MOVLW
ANSELA
ANSELA
TRISA
B'00000011'
TRISA
;not required on devices with 1 Bank of SFRs
;digital I/O
;not required on devices with 1 Bank of SFRs
;Set RA<1:0> as inputs
MOVWF
;and set RA<2:3> as
;outputs
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10.1.3
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
10.1 PORTA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 10-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 10-1 shows how to
initialize PORTA.
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 10-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Digital output functions may control the pin when it is in
Analog mode with the priority shown in Table 10-1.
Reading the PORTA register (Register 10-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
TABLE 10-1: PORTA OUTPUT PRIORITY
Pin Name
Function Priority(1)
RA0
ICSPDAT
CWG1A
PWM1
RA0
The TRISA register (Register 10-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RA1
CWG1B
PWM2
CLC1
RA1
RA2
RA3
NCO1
CLKR
RA2
10.1.1
WEAK PULL-UPS
Each of the PORTA pins has an individually configu-
rable internal weak pull-up. Control bits WPUA<3:0>
enable or disable each pull-up (see Register 10-5).
Each weak pull-up is automatically turned off when the
port pin is configured as an output. All pull-ups are dis-
abled on a Power-on Reset by the WPUEN bit of the
OPTION_REG register.
None
Note 1: Priority listed from highest to lowest.
10.1.2
ANSELA REGISTER
The ANSELA register (Register 10-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
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10.2 Register Definitions: PORTA
REGISTER 10-1: PORTA: PORTA REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-x/x
RA3
R/W-x/x
RA2
R/W-x/x
RA1
R/W-x/x
RA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
RA<3:0>: PORTA I/O Value bits (RA3 is read-only)
Note 1: Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register
return actual I/O pin values.
REGISTER 10-2: TRISA: PORTA TRI-STATE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-1
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
(1)
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’.
Unimplemented: Read as ‘1’.
bit 2-0
TRISA<2:0>: RA<2:0> Port I/O Tri-State Control bits
1= Port output driver is disabled
0= Port output driver is enabled
Note 1: Unimplemented, read as ‘1’.
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REGISTER 10-3: LATA: PORTA DATA LATCH REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’.
LATA<2:0>: RA<2:0> Output Latch Value bits
Note 1: Writes to PORTx are actually written to the corresponding LATx register. Reads from LATx register return
register values, not I/O pin values.
REGISTER 10-4: ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’.
ANSA<2:0>: Analog Select between Analog or Digital Function on Pins RA<2:0>, respectively
1= Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
0= Digital I/O. Pin is assigned to port or Digital special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if
available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to
allow external control of the voltage on the pin.
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PIC10(L)F320/322
REGISTER 10-5: WPUA: WEAK PULL-UP PORTA REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
R/W-1/1
WPUA2
R/W-1/1
WPUA1
R/W-1/1
WPUA0
WPUA3
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’.
WPUA<3:0>: Weak Pull-up PORTA Control bits
1= Weak Pull-up enabled(1)
0= Weak Pull-up disabled.
Note 1: Enabling weak pull-ups also requires that the WPUEN bit of the OPTION_REG register be cleared
(Register 16-1).
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TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
IOCAF
IOCAN
IOCAP
LATA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSA2
ANSA1
ANSA0
70
76
75
75
70
69
69
71
IOCAF3 IOCAF2 IOCAF1 IOCAF0
IOCAN3 IOCAN2 IOCAN1 IOCAN0
IOCAP3 IOCAP2 IOCAP1 IOCAP0
—
LATA2
RA2
LATA1
RA1
LATA0
RA0
PORTA
TRISA
WPUA
RA3
(1)
—
TRISA2 TRISA1 TRISA0
WPUA3 WPUA2 WPUA1 WPUA0
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note 1: Unimplemented, read as ‘1’.
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11.3 Interrupt Flags
11.0 INTERRUPT-ON-CHANGE
The IOCAFx bits located in the IOCAF register are
status flags that correspond to the interrupt-on-change
pins of PORTA. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx bits.
The PORTA pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTA pin, or
combination of PORTA pins, can be configured to
generate an interrupt. The Interrupt-on-change module
has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
11.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags
The individual status flags, (IOCAFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 11-1 is a block diagram of the IOC module.
11.1 Enabling the Module
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
To allow individual PORTA pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
EXAMPLE 11-1:
CLEARING INTERRUPT
FLAGS
11.2 Individual Pin Configuration
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
For each PORTA pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCAPx bit of the IOCAP
register is set. To enable a pin to detect a falling edge,
the associated IOCANx bit of the IOCAN register is set.
11.5 Operation in Sleep
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCAPx bit
and the IOCANx bit of the IOCAP and IOCAN registers,
respectively.
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCAF
register will be updated prior to the first instruction
executed out of Sleep.
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FIGURE 11-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
Q4Q1
IOCANx
D
Q
CK
Edge
Detect
R
RAx
Data Bus =
0 or 1
S
To Data Bus
IOCAFx
IOCAPx
D
Q
D
Q
CK
CK
IOCIE
R
Write IOCAFx
R
Q2
From all other
IOCAFx individual
pin detectors
IOC Interrupt
to CPU Core
Q1
Q1
Q1
Q2
Q2
Q2
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11.6 Interrupt-On-Change Registers
REGISTER 11-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
IOCAP3
R/W-0/0
IOCAP2
R/W-0/0
IOCAP1
R/W-0/0
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’.
IOCAP<3:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.( 1)
0= Interrupt-on-Change disabled for the associated pin.
Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
REGISTER 11-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
IOCAN3
R/W-0/0
IOCAN2
R/W-0/0
IOCAN1
R/W-0/0
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’.
IOCAN<3:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.( 1)
0= Interrupt-on-Change disabled for the associated pin.
Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
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REGISTER 11-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
IOCAF3
R/W-0/0
IOCAF2
R/W-0/0
IOCAF1
R/W-0/0
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’.
IOCAF<3:0>: Interrupt-on-Change PORTA Flag bits
1= An enable change was detected on the associated pin.
Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling
edge was detected on RAx.( 1)
0= No change was detected, or the user cleared the detected change.
Note 1: Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
TABLE 11-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCAF
IOCAN
IOCAP
TRISA
GIE
—
PEIE
—
TMR0IE
INTE
—
IOCIE
TMR0IF
INTF
IOCIF
40
76
75
75
69
—
—
—
—
IOCAF3 IOCAF2 IOCAF1 IOCAF0
IOCAN3 IOCAN2 IOCAN1 IOCAN0
—
—
—
—
—
—
IOCAP3 IOCAP2 IOCAP1 IOCAP0
(1)
—
—
—
—
TRISA2 TRISA1 TRISA0
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
Note 1: Unimplemented, read as ‘1’.
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12.1 Independent Gain Amplifiers
12.0 FIXED VOLTAGE REFERENCE
(FVR)
The output of the FVR supplied to the ADC is routed
through an independent programmable gain amplifier.
The amplifier can be configured to amplify the
reference voltage by 1x, 2x or 4x, to produce the three
possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
To minimize current consumption when the FVR is
disabled, the FVR buffers should be turned off by
clearing the ADFVR<1:0> bits.
12.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 24.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 12-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
x2
x4
FVR
(To ADC Module)
1.024V Fixed
Reference
+
-
FVREN
FVRRDY
Any peripheral requiring
the Fixed Reference
(See Table 12-1)
TABLE 12-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
Conditions
Description
HFINTOSC
FOSC = 1
EC on CLKIN pin.
BOREN<1:0> = 11
BOR always enabled.
BOR
IVR
BOREN<1:0> = 10and BORFS = 1
BOREN<1:0> = 01and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOR under software control, BOR Fast Start enabled.
All PIC10F320/322 devices, when
VREGPM1 = 1and not in Sleep
The device runs off of the Power-Save mode regulator when
in Sleep mode.
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12.3 FVR Control Registers
REGISTER 12-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
TSEN(3)
R/W-0/0
TSRNG(3)
U-0
—
U-0
—
R/W-0/0
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
FVREN: Fixed Voltage Reference Enable bit
1= Fixed Voltage Reference is enabled
0= Fixed Voltage Reference is disabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1= Fixed Voltage Reference output is ready for use
0= Fixed Voltage Reference output is not ready or not enabled
TSEN: Temperature Indicator Enable bit(3)
1= Temperature Indicator is enabled
0= Temperature Indicator is disabled
TSRNG: Temperature Indicator Range Selection bit(3)
1= VOUT = VDD - 4VT (High Range)
0= VOUT = VDD - 2VT (Low Range)
bit 3-2
bit 1-0
Unimplemented: Read as ‘0‘
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00= ADC Fixed Voltage Reference Peripheral output is off.
Note 1: FVRRDY indicates the true state of the FVR.
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 14.0 “Temperature Indicator Module” for additional information.
TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN FVRRDY
TSEN
TSRNG
—
—
ADFVR<1:0>
78
Legend: Shaded cells are not used with the Fixed Voltage Reference.
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PIC10(L)F320/322
13.0 INTERNAL VOLTAGE
REGULATOR (IVR)
The Internal Voltage Regulator (IVR), which provides
operation above 3.6V is available on:
• PIC10F320
• PIC10F322
This circuit regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. When VDD approaches the
regulated voltage, the IVR output automatically tracks
the input voltage.
The IVR operates in one of three power modes based
on user configuration and peripheral selection. The
operating power modes are:
- High
- Low
- Power-Save Sleep mode
Power modes are selected automatically depending on
the device operation, as shown in Table 13-1. Tracking
mode is selected automatically when VDD drops below
the safe operating voltage of the core.
Note:
IVR is disabled in Tracking mode, but will
consume power. See Section 24.0
“Electrical Specifications” for more
information.
TABLE 13-1: IVR POWER MODES - REGULATED
VREGPM1 Bit
Sleep Mode
Memory Bias Power Mode
IVR Power Mode
EC Mode or INTOSC = 16 MHz (HP Bias)
INTOSC = 1 to 8 MHz (MP Bias)
INTOSC = 31 kHz to 500 kHz (LP Bias)
Don’t Care
High
x
No
Low
Low
0
Yes
Yes
No HFINTOSC
1
Power Save(1)
No Peripherals
Note 1: Forced to Low-Power mode by any of the following conditions:
•
•
•
•
BOR is enabled
HFINTOSC is an active peripheral source
Self-write is active
ADC is in an active conversion
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REGISTER 13-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
VREGPM1
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
Unimplemented: Read as ‘0’.
VREGPM1: Voltage Regulator Power Mode Selection bit
1 = Power-Save Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up.
0 = Low-Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up.
Reserved: Maintain this bit set.
bit 0
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FIGURE 14-1:
TEMPERATURE CIRCUIT
DIAGRAM
14.0 TEMPERATURE INDICATOR
MODULE
Rev. 10-000069A
7/31/2013
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between of -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
TSRNG
VOUT
To ADC
Temp. Indicator
14.1 Circuit Operation
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
14.2 Minimum Operating VDD vs.
Minimum Sensing Temperature
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
Equation 14-1 describes the output characteristics of
the temperature indicator.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
EQUATION 14-1: VOUT RANGES
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
Table 14-1 shows the recommended minimum VDD vs.
range setting.
TABLE 14-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 12.0 “Fixed Voltage Reference (FVR)” for
more information.
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
14.3 Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
14.4 ADC Acquisition Time
The low range is selected by clearing the TSRNG bit of
the FVRCON0 register. The low range generates a
lower voltage drop and thus, a lower bias voltage is
needed to operate the circuit. The low range is provided
for low voltage operation.
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
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TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
FVRCON
ADCON
FVREN FVRRDY
ADCS<2:0>
TSEN
TSRNG
—
—
ADFVR<1:0>
78
88
GO/
CHS<2:0>
ADON
DONE
ADRES
A/D Result Register
89
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the temperature indicator module.
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15.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) converts an
analog input signal to an 8-bit binary representation of
that signal. This device uses three analog input
channels, which are multiplexed into a single sample
and hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates an 8-bit binary result via successive
approximation and stores the conversion result into the
ADC result register (ADRES). Figure 15-1 shows the
block diagram of the ADC.
The ADC voltage reference is software selectable to be
internally generated.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 15-1:
ADC SIMPLIFIED BLOCK DIAGRAM
VREF- = Vss
VREF+ = VDD
AN0
AN1
AN2
000
001
010
011
100
101
110
111
Reserved
Reserved
Reserved
ADC
8
GO/DONE
Temp Indicator
FVR
ADRES
ADON(1)
VSS
CHS<2:0>(2)
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See ADCON register (Register 15-1) for detailed analog channel selection per device.
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15.1.4
CONVERSION CLOCK
15.1 ADC Configuration
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON register
(Register 15-1). There are seven possible clock
options:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• FOSC/2
• ADC conversion clock source
• Interrupt control
• FOSC/4
• FOSC/8
• FOSC/16
15.1.1
PORT CONFIGURATION
• FOSC/32
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 10.0 “I/O Port” for more information.
• FOSC/64
• FRC (dedicated internal RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 9.5 TAD periods
as shown in Figure 15-2.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
For correct conversion, the appropriate TAD specifica-
tion must be met. Refer to the A/D conversion require-
ments in Section 24.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of
appropriate ADC clock selections.
15.1.2
CHANNEL SELECTION
There are up to five channel selections available:
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
• AN<2:0> pins
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Refer to Section 12.0 “Fixed Voltage Reference
(FVR)” and Section 14.0 “Temperature Indicator
Module” for more information on these channel selec-
tions.
The CHS bits of the ADCON register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
There is no external voltage reference connections to
the ADC. Only VDD can be used as a reference source.
The FVR is only available as an input channel and not
a VREF+ input to the ADC.
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TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0>
000
16 MHz
8 MHz
4 MHz
1 MHz
Clock Source
FOSC/2
125 ns(1)
250 ns(1)
0.5 s(1)
1.0 s
250 ns(1)
500 ns(1)
1.0 s
500 ns(1)
1.0 s
2.0 s
4.0 s
8.0 s(2)
16.0 s(2)
32.0 s(2)
64.0 s(2)
1.0-6.0 s(1,3)
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
100
001
101
010
110
x11
2.0 s
2.0 s
4.0 s
2.0 s
4.0 s
8.0 s(2)
1.0-6.0 s(1,3)
8.0 s(2)
16.0 s(2)
1.0-6.0 s(1,3)
4.0 s
1.0-6.0 s(1,3)
Legend:
Note 1: These values violate the minimum required TAD time.
2: For faster conversion times, the selection of another clock source is recommended.
Shaded cells are outside of recommended range.
3: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD7 TAD8 TAD9
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6
b5
b4
b2
b7
b6
b3
b1
b0
Conversion starts
Holding capacitor is disconnected from analog input
(typically 100 ns)
Set GO bit
On the following cycle:
ADRES is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is
connected to analog input.
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15.1.5
INTERRUPTS
15.2 ADC Operation
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
15.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.5 “A/D Conver-
sion Procedure”.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEPinstruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
15.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRES register with new conversion
result
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially com-
plete Analog-to-Digital conversion sample. Incomplete
bits will match the last bit converted.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
15.2.4
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEPinstruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
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15.2.5
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
• Disable weak pull-ups either globally (Refer
to the OPTION_REG register) or individually
(Refer to the appropriate WPUX register)
2. Configure the ADC module:
• Select ADC conversion clock
• Select ADC input channel
• Turn on ADC module
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
.
5. Start conversion by setting the GO/DONE bit.
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.4 “A/D Acquisition
Requirements”.
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15.3 ADC Register Definitions
The following registers are used to control the
operation of the ADC.
REGISTER 15-1: ADCON: A/D CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
ADCS<2:0>
CHS<2:0>
GO/DONE
bit 7
Legend:
bit 0
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4-2
bit 1
ADCS<2:0>: A/D Conversion Clock Select bits
111= FRC
110= FOSC/64
101= FOSC/16
100= FOSC/4
011= FRC
010= FOSC/32
001= FOSC/8
000= FOSC/2
CHS<2:0>: Analog Channel Select bits
111= FVR (Fixed Voltage Reference) Buffer Output(2)
110= Temperature Indicator(1)
101= Reserved. No channel connected.
100= Reserved. No channel connected.
011= Reserved. No channel connected.
010= AN2
001= AN1
000= AN0
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (Setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is complete.)
If this bit is cleared while a conversion is in progress, the conversion will stop and the results of the
conversion up to this point will be transferred to the result registers, but the ADIF interrupt flag bit will
not be set.
If ADON = 0:
0= A/D conversion not in progress
bit 0
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Temperature Indicator Module” for more information.
2: See Section 12.0 “Fixed Voltage Reference (FVR)” for more information.
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REGISTER 15-2: ADRES: ADC RESULT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
8-bit result
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source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(511 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
15.4 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-3. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/511)
= –10pF1k + 7k + 10k ln(0.001957)
= 1.12µs
Therefore:
TACQ = 2µs + 1.12µs + 50°C- 25°C0.05µs/°C
= 4.37µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
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FIGURE 15-3:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
VT 0.6V
SS
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VSS/VREF-
VT 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Note 1: Refer to Section 24.0 “Electrical Specifications”.
FIGURE 15-4:
ADC TRANSFER FUNCTION
Full-Scale Range
FFh
FEh
FDh
FCh
FBh
03h
02h
01h
00h
Analog Input Voltage
1.5 LSB
0.5 LSB
Zero-Scale
Transition
VREF-
Full-Scale
Transition
VREF+
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TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
88
ADCON
ADCS<2:0>
CHS<2:0>
GO/DONE
ADON
ADRES
ANSELA
FVRCON
INTCON
PIE1
ADRES<7:0>
89
70
78
40
41
42
69
—
FVREN
GIE
—
—
FVRRDY
PEIE
ADIE
ADIF
—
—
TSEN
TMR0IE
—
—
—
—
ANSA2
—
ANSA1
ANSA0
TSRNG
INTE
ADFVR<1:0>
IOCIE
CLC1IE
CLC1IF
—
TMR0IF
—
INTF
IOCIF
—
NCO1IE
NCO1IF
—
TMR2IE
TMR2IF
TRISA1
PIR1
—
—
—
—
TRISA
—
—
TRISA2
TRISA0
Legend:
x= unknown, u= unchanged, — = unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for ADC module.
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When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
16.0 TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
16.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
Figure 16-1 is a block diagram of the Timer0 module.
8-Bit Counter mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION_REG register to ‘1’.
16.1 Timer0 Operation
The rising or falling transition of the incrementing edge
for the external input source is determined by the T0SE
bit in the OPTION_REG register.
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
16.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION_REG
register.
FIGURE 16-1:
BLOCK DIAGRAM OF THE TIMER0 PRESCALER
FOSC/4
Data Bus
0
1
8
T0CKI
1
SYNC
TMR0
2 TCY
0
T0CS
T0SE
Set Flag bit TMR0IF
8-bit
Prescaler
on Overflow
PSA
8
PS<2:0>
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16.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
16.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
A single software programmable prescaler is available
for use with Timer0. The prescaler assignment is
controlled by the PSA bit of the OPTION_REG register.
To assign the prescaler to Timer0, the PSA bit must be
cleared to a ‘0’.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS<2:0> bits of the
OPTION_REG register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
16.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 24.0 “Electrical
Specifications”.
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REGISTER 16-1: OPTION_REG: OPTION REGISTER
R/W-1/u
WPUEN(1)
R/W-1/u
INTEDG
R/W-1/u
T0CS
R/W-1/u
T0SE
R/W-1/u
PSA
R/W-1/u
R/W-1/u
PS<2:0>
R/W-1/u
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit(1)
1= Weak pull-ups are disabled
0= Weak pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is inactive and has no effect on the Timer 0 module
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Note 1: WPUEN does not disable the pull-up for the MCLR input when MCLR = 1.
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
T0CS
INTE
T0SE
IOCIE
PSA
TMR0IF
INTF
IOCIF
40
95
40
69
OPTION_REG WPUEN INTEDG
TMR0
PS<2:0>
Timer0 module Register
TRISA
—
—
—
—
—
TRISA2 TRISA1 TRISA0
Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the
Timer0 module.
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The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
17.0 TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
• Interrupt on TMR2 match with PR2
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• Software programmable prescaler (1:1, 1:4, 1:16,
1:64)
• Software programmable postscaler (1:1 to 1:16)
See Figure 17-1 for a block diagram of Timer2.
• A write to TMR2 occurs.
• A write to T2CON occurs.
17.1 Timer2 Operation
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:64. The output of the prescaler is then used to
increment the TMR2 register.
Note:
TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented.
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 17-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
Output
TMR2
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS<1:0>
4
TOUTPS<3:0>
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REGISTER 17-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TOUTPS<3:0>
TMR2ON
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer2 Output Postscaler Select bits
1111= 1:16 Postscaler
1110= 1:15 Postscaler
1101= 1:14 Postscaler
1100= 1:13 Postscaler
1011= 1:12 Postscaler
1010= 1:11 Postscaler
1001= 1:10 Postscaler
1000= 1:9 Postscaler
0111= 1:8 Postscaler
0110= 1:7 Postscaler
0101= 1:6 Postscaler
0100= 1:5 Postscaler
0011= 1:4 Postscaler
0010= 1:3 Postscaler
0001= 1:2 Postscaler
0000= 1:1 Postscaler
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
11= Prescaler is 64
10= Prescaler is 16
01= Prescaler is 4
00= Prescaler is 1
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
—
PEIE
ADIE
ADIF
TMR0IE
INTE
IOCIE
CLC1IE
CLC1IF
TMR0IF
INTF
IOCIF
—
40
41
42
96
96
97
—
—
NCO1IE
NCO1IF
—
—
TMR2IE
TMR2IF
PIR1
—
—
PR2
Timer2 module Period Register
Timer2 module Register
TMR2
T2CON
Legend:
—
TOUTPS<3:0>
TMR2ON
T2CKPS<1:0>
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
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Figure 18-1 shows a simplified block diagram of PWM
operation.
18.0 PULSE-WIDTH MODULATION
(PWM) MODULE
Figure 18-2 shows a typical waveform of the PWM
signal.
The PWM module generates a Pulse-Width Modulated
signal determined by the duty cycle, period, and
resolution that are configured by the following registers:
• PR2
• T2CON
• PWMxDCH
• PWMxDCL
• PWMxCON
FIGURE 18-1:
SIMPLIFIED PWM BLOCK DIAGRAM
PWMxDCL<7:6>
Duty Cycle registers
PWMxDCH
PWMxOUT
to other peripherals: CLC and CWG
Latched
(Not visible to user)
Output Enable (PWMxOE)
TRIS Control
0
1
Q
Q
Comparator
R
S
PWMx
TMR2 Module
(1)
Output Polarity (PWMxPOL)
TMR2
Comparator
PR2
Clear Timer,
PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2
prescaler to create a 10-bit time base.
For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section 18.1.9
“Setup for PWM Operation using PWMx Pins”.
FIGURE 18-2:
PWM OUTPUT
Period
Pulse Width
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0
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When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
18.1 PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
• TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
Note:
Clearing the PWMxOE bit will relinquish
control of the PWMx pin.
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
18.1.1 FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note:
The Timer2 postscaler has no effect on the
PWM operation.
18.1.4
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to the PWMxDCH and PWMxDCL register pair. The
PWMxDCH register contains the eight MSbs and the
PWMxDCL<7:6>, the two LSbs. The PWMxDCH and
PWMxDCL registers can be written to at any time.
Note: The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than the
PWM output.
Equation 18-2 is used to calculate the PWM pulse
width.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb)
registers. When the value is greater than or equal to
PR2, the PWM output is never cleared (100% duty
cycle).
Equation 18-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 18-2: PULSE WIDTH
Pulse Width = PWMxDCH:PWMxDCL<7:6>
Note: The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are updated
when Timer2 matches PR2. Care should be
taken to update both registers before the
timer match occurs.
TOSC
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC
EQUATION 18-3: DUTY CYCLE RATIO
18.1.2 PWM OUTPUT POLARITY
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = -----------------------------------------------------------------------------------
4PR2 + 1
18.1.3
PWM PERIOD
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 18-1.
EQUATION 18-1: PWM PERIOD
PWM Period = PR2 + 1 4 TOSC
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
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18.1.5
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 18-4.
EQUATION 18-4: PWM RESOLUTION
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
Note:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 18-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 64)
PR2 Value
64
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 18-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 64)
PR2 Value
64
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
18.1.6
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
18.1.7
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 4.0 “Oscillator Module” for
additional details.
18.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
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18.1.9
SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx pins:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the PR2 register with the PWM period value.
4. Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
5. Configure and start Timer2:
•
•
•
Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note below.
Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See Note below.
7. Enable the PWMx pin output driver(s) by clear-
ing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.
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18.2 PWM Register Definitions
REGISTER 18-1: PWMxCON: PWM CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
PWMxEN
PWMxOE
PWMxOUT PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
PWMxEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
PWMxOE: PWM Module Output Enable bit
1= Output to PWMx pin is enabled
0= Output to PWMx pin is disabled
bit 5
bit 4
PWMxOUT: PWM Module Output Value bit
PWMxPOL: PWMx Output Polarity Select bit
1= PWM output is active-low.
0= PWM output is active-high.
bit 3-0
Unimplemented: Read as ‘0’
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REGISTER 18-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
PWMxDCH<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register.
REGISTER 18-3: PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
R/W-x/u
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PWMxDCL<7:6>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register.
Unimplemented: Read as ‘0’
TABLE 18-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
LATA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSA2
LATA2
RA2
ANSA1
LATA1
RA1
ANSA0
LATA0
RA0
70
70
PORTA
RA3
69
PR2
Timer2 module Period Register
PWM1EN PWM1OE PWM1OUT PWM1POL
PWM1DCH<7:0>
96
PWM1CON
PWM1DCH
PWM1DCL
PWM2CON
PWM2DCH
PWM2DCL
T2CON
—
—
—
—
102
103
103
102
103
103
97
PWM1DCL<7:6>
—
—
—
—
—
—
—
—
—
—
PWM2EN PWM2OE PWM2OUT PWM2POL
PWM2DCH<7:0>
PWM2DCL<7:6>
—
—
—
—
—
—
—
TOUTPS<3:0>
Timer2 module Register
TMR2ON
T2CKPS<1:0>
TMR2
96
TRISA
—
—
—
—
—
TRISA2
TRISA1
TRISA0
69
Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.
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Refer to Figure 19-1 for a simplified diagram showing
signal flow through the CLCx.
19.0 CONFIGURABLE LOGIC CELL
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLCx) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell selects any combi-
nation of the eight input signals and through the use of
configurable gates reduces the selected inputs to four
logic lines that drive one of eight selectable single-out-
put logic functions.
•
Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
Input sources are a combination of the following:
- OR-XNOR
• Two I/O pins
• Internal clocks
• Peripherals
• Register bits
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
The output can be directed internally to peripherals and
to an output pin.
FIGURE 19-1:
CLCx SIMPLIFIED BLOCK DIAGRAM
D
Q
LCxOUT
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
Q1
LE
See Figure 19-3
LCxOE
LCxEN
lcxq
lcxg1
TRIS Control
CLCx
lcxg2
lcxg3
lcxg4
Logic
lcx_out
Function
LCxPOL
Interrupt
det
LCxINTP
LCxINTN
Interrupt
det
LCxMODE<2:0>
sets
CLCxIF
flag
See Figure 19-2
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19.1.2
DATA GATING
19.1 CLCx Setup
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
Programming the CLCx module is performed by
configuring the four stages in the logic signal flow. The
four stages are:
• Data selection
Note:
Data gating is undefined at power-up.
• Data gating
• Logic function selection
• Output polarity
The gate stage is more than just signal direction. The gate
can be configured to direct each input signal as inverted
or non-inverted data. Directed signals are ANDed
together in each gate. The output of each gate can be
inverted before going on to the logic function stage.
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
The gating is in essence a 1-to-4 input AND/NAND/OR/
NOR gate. When every input is inverted and the output
is inverted, the gate is an OR of all enabled data inputs.
When the inputs and output are not inverted, the gate
is an AND or all enabled inputs.
19.1.1
DATA SELECTION
There are eight signals available as inputs to the
configurable logic. Four 8-input multiplexers are used
to select the inputs to pass on to the next stage.
Table 19-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If no
inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 19-3 and Register 19-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 19-2. Data inputs in the figure
are identified by a generic numbered input name.
TABLE 19-2: DATA GATING LOGIC
Table 19-1 correlates the generic input name to the
actual signal for each CLC module. The columns
labeled lcxd1 through lcxd4 indicate the MUX output for
the selected data input. D1S through D4S are
abbreviations for the MUX select input codes:
LCxD1S<2:0> through LCxD4S<2:0>, respectively.
Selecting a data input in a column excludes all other
inputs in that column.
CLCxGLS0
LCxGyPOL
Gate Logic
0x55
0x55
0xAA
0xAA
0x00
0x00
1
0
1
0
0
1
AND
NAND
NOR
OR
Logic 0
Logic 1
Note:
Data selections are undefined at power-up.
TABLE 19-1: CLCx DATA INPUT
SELECTION
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses). If
the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
lcxd1 lcxd2 lcxd3 lcxd4
Data Input
CLC 1
D1S
D2S
D3S
D4S
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000 CLCx
001 CLCxIN1
010 CLCxIN2
011 PWM1
100 PWM2
101 NCOx
110 FOSC
Data gating is configured with the logic gate select
registers as follows:
• Gate 1: CLCxGLS0 (Register 19-5)
• Gate 2: CLCxGLS1 (Register 19-6)
• Gate 3: CLCxGLS2 (Register 19-7)
• Gate 4: CLCxGLS3 (Register 19-8)
111 LFINTOSC
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 19-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that gate.
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19.1.3
LOGIC FUNCTION
19.1.5
CLCX SETUP STEPS
There are eight available logic functions including:
• AND-OR
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• OR-XOR
• Select desired inputs using CLCxSEL0 and
CLCxSEL1 registers (See Table 19-1).
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the
LCxPOLy bits of the CLCxPOL register.
• Select the desired logic function with the
LCxMODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate
output polarity step).
• AND
• S-R Latch
• D Flip-Flop with Set and Reset
• D Flip-Flop with Reset
• J-K Flip-Flop with Reset
• Transparent Latch with Set and Reset
Logic functions are shown in Figure 19-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage. The
output is fed to the inversion stage and from there to other
peripherals, an output pin, and back to the CLCx itself.
19.1.4
OUTPUT POLARITY
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON reg-
ister inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
• If driving the CLCx pin, set the LCxOE bit of the
CLCxCON register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
- Set the LCxINTN bit in the CLCxCON
register or falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
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19.2 CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR registers will be
set when either edge detector is triggered and its asso-
ciated enable bit is set. The LCxINTP enables rising
edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON
register.
To fully enable the interrupt, set the following bits:
• LCxON bit of the CLCxCON register
• CLCxIE bit of the associated PIE registers
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the associated PIR registers must be
cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
19.3 Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
19.4 Operation During Sleep
The selection, gating, and logic functions are not
affected by Sleep. Operation will continue provided that
the source signals are also not affected by Sleep.
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FIGURE 19-2:
INPUT DATA SELECTION AND GATING
Data Selection
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
000
Data GATE 1
lcxd1T
lcxd1N
LCxD1G1T
LCxD1G1N
LCxD2G1T
LCxD2G1N
LCxD3G1T
LCxD3G1N
LCxD4G1T
LCxD4G1N
111
000
LCxD1S<2:0>
lcxg1
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
LCxG1POL
lcxd2T
lcxd2N
111
000
LCxD2S<2:0>
LCxD3S<2:0>
LCxD4S<2:0>
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
Data GATE 2
lcxg2
lcxd3T
lcxd3N
(Same as Data GATE 1)
Data GATE 3
111
000
lcxg3
lcxg4
(Same as Data GATE 1)
Data GATE 4
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
(Same as Data GATE 1)
lcxd4T
lcxd4N
111
Note:
All controls are undefined at power-up.
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FIGURE 19-3:
PROGRAMMABLE LOGIC FUNCTIONS
AND - OR
OR - XOR
lcxg1
lcxg2
lcxg3
lcxg4
lcxg1
lcxg2
lcxg3
lcxg4
lcxq
lcxq
LCxMODE<2:0>= 000
LCxMODE<2:0>= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxg2
lcxg3
lcxg4
lcxq
S
R
Q
lcxg2
lcxg3
lcxg4
lcxq
LCxMODE<2:0>= 010
LCxMODE<2:0>= 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg4
lcxg2
S
lcxq
D
Q
lcxg2
lcxq
D
Q
lcxg1
lcxg3
lcxg1
lcxg3
R
R
LCxMODE<2:0>= 100
LCxMODE<2:0>= 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
lcxg2
lcxg1
lcxg4
lcxq
J
Q
S
lcxg2
lcxq
D
Q
K
R
LE
lcxg1
lcxg3
R
lcxg3
LCxMODE<2:0>= 110
LCxMODE<2:0>= 111
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19.5 CLC Control Registers
REGISTER 19-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
LCxEN
R/W-0/0
LCxOE
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
LCxOUT
LCxINTP
LCxINTN
LCxMODE<2:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
LCxEN: Configurable Logic Cell Enable bit
1= Configurable Logic Cell is enabled and mixing input signals
0= Configurable Logic Cell is disabled and has logic zero output
LCxOE: Configurable Logic Cell Output Enable bit
1= Configurable Logic Cell port pin output enabled
0= Configurable Logic Cell port pin output disabled
bit 5
bit 4
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1= CLCxIF will be set when a rising edge occurs on lcx_out
0= CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1= CLCxIF will be set when a falling edge occurs on lcx_out
0= CLCxIF will not be set
bit 2-0
LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111= Cell is 1-input transparent latch with S and R
110= Cell is J-K Flip-Flop with R
101= Cell is 2-input D Flip-Flop with R
100= Cell is 1-input D Flip-Flop with S and R
011= Cell is S-R latch
010= Cell is 4-input AND
001= Cell is OR-XOR
000= Cell is AND-OR
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REGISTER 19-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-x/u
LCxPOL
U-0
—
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4POL LCxG3POL
LCxG2POL LCxG1POL
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
bit 7
LCxPOL: LCOUT Polarity Control bit
1= The output of the logic cell is inverted
0= The output of the logic cell is not inverted
bit 6-4
bit 3
Unimplemented: Read as ‘0’
LCxG4POL: Gate 4 Output Polarity Control bit
1= The output of gate 4 is inverted when applied to the logic cell
0= The output of gate 4 is not inverted
bit 2
bit 1
bit 0
LCxG3POL: Gate 3 Output Polarity Control bit
1= The output of gate 3 is inverted when applied to the logic cell
0= The output of gate 3 is not inverted
LCxG2POL: Gate 2 Output Polarity Control bit
1= The output of gate 2 is inverted when applied to the logic cell
0= The output of gate 2 is not inverted
LCxG1POL: Gate 1 Output Polarity Control bit
1= The output of gate 1 is inverted when applied to the logic cell
0= The output of gate 1 is not inverted
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REGISTER 19-3: CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER
U-0
—
R/W-x/u
R/W-x/u
LCxD2S<2:0>(1)
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
LCxD1S<2:0>(1)
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD2S<2:0>: Input Data 2 Selection Control bits(1)
111= CLCxIN[7] is selected for lcxd2.
110= CLCxIN[6] is selected for lcxd2.
101= CLCxIN[5] is selected for lcxd2.
100= CLCxIN[4] is selected for lcxd2.
011= CLCxIN[3] is selected for lcxd2.
010= CLCxIN[2] is selected for lcxd2.
001= CLCxIN[1] is selected for lcxd2.
000= CLCxIN[0] is selected for lcxd2.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD1S<2:0>: Input Data 1 Selection Control bits(1)
111= CLCxIN[7] is selected for lcxd1.
110= CLCxIN[6] is selected for lcxd1.
101= CLCxIN[5] is selected for lcxd1.
100= CLCxIN[4] is selected for lcxd1.
011= CLCxIN[3] is selected for lcxd1.
010= CLCxIN[2] is selected for lcxd1.
001= CLCxIN[1] is selected for lcxd1.
000= CLCxIN[0] is selected for lcxd1.
Note 1: See Table 19-1 for signal names associated with inputs.
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REGISTER 19-4: CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER
U-0
—
R/W-x/u
R/W-x/u
LCxD4S<2:0>(1)
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
LCxD3S<2:0>(1)
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD4S<2:0>: Input Data 4 Selection Control bits(1)
111= CLCxIN[7] is selected for lcxd4.
110= CLCxIN[6] is selected for lcxd4.
101= CLCxIN[5] is selected for lcxd4
100= CLCxIN[4] is selected for lcxd4.
011= CLCxIN[3] is selected for lcxd4.
010= CLCxIN[2] is selected for lcxd4.
001= CLCxIN[1] is selected for lcxd4.
000= CLCxIN[0] is selected for lcxd4.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD3S<2:0>: Input Data 3 Selection Control bits(1)
111= CLCxIN[7] is selected for lcxd3.
110= CLCxIN[6] is selected for lcxd3.
101= CLCxIN[5] is selected for lcxd3.
100= CLCxIN[4] is selected for lcxd3.
011= CLCxIN[3] is selected for lcxd3.
010= CLCxIN[2] is selected for lcxd3.
001= CLCxIN[1] is selected for lcxd3.
000= CLCxIN[0] is selected for lcxd3.
Note 1: See Table 19-1 for signal names associated with inputs.
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REGISTER 19-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T
LCxG1D2N
LCxG1D1T LCxG1D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg1
0= lcxd4T is not gated into lcxg1
LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg1
0= lcxd4N is not gated into lcxg1
LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg1
0= lcxd3T is not gated into lcxg1
LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg1
0= lcxd3N is not gated into lcxg1
LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg1
0= lcxd2T is not gated into lcxg1
LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg1
0= lcxd2N is not gated into lcxg1
LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg1
0= lcxd1T is not gated into lcxg1
LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg1
0= lcxd1N is not gated into lcxg1
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REGISTER 19-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T
LCxG2D2N
LCxG2D1T LCxG2D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg2
0= lcxd4T is not gated into lcxg2
LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg2
0= lcxd4N is not gated into lcxg2
LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg2
0= lcxd3T is not gated into lcxg2
LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg2
0= lcxd3N is not gated into lcxg2
LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg2
0= lcxd2T is not gated into lcxg2
LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg2
0= lcxd2N is not gated into lcxg2
LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg2
0= lcxd1T is not gated into lcxg2
LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg2
0= lcxd1N is not gated into lcxg2
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REGISTER 19-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T
LCxG3D2N
LCxG3D1T LCxG3D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg3
0= lcxd4T is not gated into lcxg3
LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg3
0= lcxd4N is not gated into lcxg3
LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg3
0= lcxd3T is not gated into lcxg3
LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg3
0= lcxd3N is not gated into lcxg3
LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg3
0= lcxd2T is not gated into lcxg3
LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg3
0= lcxd2N is not gated into lcxg3
LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg3
0= lcxd1T is not gated into lcxg3
LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg3
0= lcxd1N is not gated into lcxg3
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REGISTER 19-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T
LCxG4D2N
LCxG4D1T LCxG4D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg4
0= lcxd4T is not gated into lcxg4
LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg4
0= lcxd4N is not gated into lcxg4
LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg4
0= lcxd3T is not gated into lcxg4
LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg4
0= lcxd3N is not gated into lcxg4
LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg4
0= lcxd2T is not gated into lcxg4
LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg4
0= lcxd2N is not gated into lcxg4
LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg4
0= lcxd1T is not gated into lcxg4
LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg4
0= lcxd1N is not gated into lcxg4
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TABLE 19-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Register
on Page
Name
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
CLC1CON
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC1POL
CLC1SEL0
CLC1SEL1
LC1EN
LC1OE
LC1OUT
LC1INTP
LC1INTN
LC1MODE<2:0>
110
114
115
116
117
111
112
113
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N
LC1POL
—
—
—
LC1G4POL LC1G3POL LC1G2POL LC1G1POL
—
—
LC1D2S<2:0>
LC1D4S<2:0>
—
—
LC1D1S<2:0>
LC1D3S<2:0>
INTCON
PIE1
GIE
—
PEIE
ADIE
ADIF
—
TMR0IE
INTE
NCO1IE
NCO1IF
—
IOCIE
CLC1IE
CLC1IF
—
TMR0IF
—
INTF
IOCIF
—
40
41
42
69
—
—
—
TMR2IE
TMR2IF
TRISA1
PIR1
—
—
—
TRISA
Legend:
—
TRISA2
TRISA0
— = unimplemented read as ‘0’. Shaded cells are not used for CLC module.
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20.0 NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCOx) module
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the resolution of division does not
vary with the divider value. The NCOx is most useful for
applications that requires frequency accuracy and fine
resolution at a fixed duty cycle.
Features of the NCOx include:
• 16-bit increment function
• Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode
• Output pulse width control
• Multiple clock input sources
• Output polarity control
• Interrupt capability
Figure 20-1 is a simplified block diagram of the NCOx
module.
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DS40001585D-page 119
FIGURE 20-1:
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM
NCOxINCH NCOxINCL
16
Rev. 10-000028A
7/30/2013
(1)
INCBUFH INCBUFL
16
20
NCO_overflow
Adder
20
HFINTOSC
FOSC
00
01
10
NCOx_clk
NCOxACCU NCOxACCH NCOxACCL
20
LCx_out
NCO1CLK
11
NCO_interrupt
set bit
NxCKS<1:0>
2
NCOxIF
Fixed Duty
Cycle Mode
Circuitry
NxOE
D
Q
D
Q
0
1
TRIS bit
NCOx
_
Q
NxPFM
NxPOL
NCOx_out
To Peripherals
NxOUT
S
Q
EN
D
Q
_
Ripple
Counter
R
Q
Q1
Pulse
R
Frequency
3
Mode Circuitry
NxPWS<2:0>
Note 1:
The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
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PIC10(L)F320/322
20.1.3
ADDER
20.1 NCOx OPERATION
The NCOx Adder is a full adder, which operates
asynchronously to the clock source selected. The
addition of the previous result and the increment value
replaces the accumulator value on the rising edge of
each input clock.
The NCOx operates by repeatedly adding a fixed value
to an accumulator. Additions occur at the input clock
rate. The accumulator will overflow with a carry
periodically, which is the raw NCOx output. This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 20-1.
20.1.4
INCREMENT REGISTERS
The Increment value is stored in two 8-bit registers
making up a 16-bit increment. In order of LSB to MSB
they are:
The NCOx output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCOx
output is then distributed internally to other peripherals
and optionally output to a pin. The accumulator overflow
also generates an interrupt.
• NCOxINCL
• NCOxINCH
The NCOx output creates an instantaneous frequency,
which may cause uncertainty. This output depends on
the ability of the receiving circuit (i.e., CWG or external
resonant converter circuitry) to average the
instantaneous frequency to reduce uncertainty.
Both of the registers are readable and writable. The
Increment registers are double-buffered to allow for
value changes to be made without first disabling the
NCOx module.
The buffer loads are immediate when the module is
disabled. Writing to the MS register first is necessary
because then the buffer is loaded synchronously with
the NCOx operation after the write is executed on the
lower increment register.
20.1.1
NCOx CLOCK SOURCES
Clock sources available to the NCOx include:
• HFINTOSC
• FOSC
• LC1OUT
• NCO1CLK pin
Note: The increment buffer registers are not user-
accessible.
The NCOx clock source is selected by configuring the
NxCKS<1:0> bits in the NCOxCLK register.
20.1.2
ACCUMULATOR
The Accumulator is a 20-bit register. Read and write
access to the Accumulator is available through three
registers:
• NCOxACCL
• NCOxACCH
• NCOxACCU
EQUATION 20-1:
NCO Clock Frequency Increment Value
FOVERFLOW= --------------------------------------------------------------------------------------------------------------
2n
n = Accumulator width in bits
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20.2 FIXED DUTY CYCLE (FDC) MODE
In Fixed Duty Cycle (FDC) mode, every time the
Accumulator overflows, the output is toggled. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure 20-2.
The FDC mode is selected by clearing the NxPFM bit
in the NCOxCON register.
20.3 PULSE FREQUENCY (PF) MODE
In Pulse Frequency (PF) mode, every time the Accu-
mulator overflows, the output becomes active for one
or more clock periods. See Section 20.3.1 “OUTPUT
PULSE WIDTH CONTROL” for more information.
Once the clock period expires, the output returns to an
inactive state. This provides a pulsed output.
The output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see Figure 20-2.
The value of the active and inactive states depends on
the Polarity bit, NxPOL in the NCOxCON register.
The PF mode is selected by setting the NxPFM bit in
the NCOxCON register.
20.3.1
OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the active state of the out-
put can vary in width by multiple clock periods. Various
pulse widths are selected with the NxPWS<2:0> bits in
the NCOxCLK register.
When the selected pulse width is greater than the
Accumulator overflow time frame, then NCOx
operation is undefined.
20.4 OUTPUT POLARITY CONTROL
The last stage in the NCOx module is the output polar-
ity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the inter-
rupts are enabled will cause an interrupt for the result-
ing output transition.
The NCOx output can be used internally by source
code or other peripherals. This is done by reading the
NxOUT (read-only) bit of the NCOxCON register.
DS40001585D-page 122
2011-2015 Microchip Technology Inc.
FIGURE 20-2:
NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment
Value
4000h
4000h
4000h
NCOx
Accumulator
Value
00000h 04000h 08000h
FC000h 00000h 04000h 08000h
FC000h 00000h 04000h 08000h
NCO_overflow
NCO_interrupt
NCOx Output
FDC Mode
NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
PIC10(L)F320/322
20.5 Interrupts
When the Accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIR1 register is set. To enable
this interrupt event, the following bits must be set:
• NxEN bit of the NCOxCON register
• NCOxIE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
20.6 Effects of a Reset
All of the NCOx registers are cleared to zero as the
result of a Reset.
20.7 Operation In Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
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20.8 NCOx Control Registers
REGISTER 20-1: NCOxCON: NCOx CONTROL REGISTER
R/W-0/0
NxEN
R/W-0/0
NxOE
R-0/0
R/W-0/0
NxPOL
U-0
—
U-0
—
U-0
—
R/W-0/0
NxPFM
NxOUT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
NxEN: NCOx Enable bit
1= NCOx module is enabled
0= NCOx module is disabled
NxOE: NCOx Output Enable bit
1= NCOx output pin is enabled
0= NCOx output pin is disabled
NxOUT: NCOx Output bit
1= NCOx output is high
0= NCOx output is low
NxPOL: NCOx Polarity bit
1= NCOx output signal is active-low (inverted)
0= NCOx output signal is active-high (non-inverted)
bit 3-1
bit 0
Unimplemented: Read as ‘0’.
NxPFM: NCOx Pulse Frequency mode bit
1= NCOx operates in Pulse Frequency mode
0= NCOx operates in Fixed Duty Cycle mode
REGISTER 20-2: NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
(1,2)
NxPWS<2:0>
NxCKS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2)
111= 128 NCOx clock periods
110= 64 NCOx clock periods
101= 32 NCOx clock periods
100= 16 NCOx clock periods
011= 8 NCOx clock periods
010= 4 NCOx clock periods
001= 2 NCOx clock periods
000= 1 NCOx clock periods
bit 4-2
bit 1-0
Unimplemented: Read as ‘0’
NxCKS<1:0>: NCOx Clock Source Select bits
11= LC1OUT
10= HFINTOSC (16 MHz)
01= FOSC
00= NCO1CLK pin
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined.
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REGISTER 20-3: NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
NCOxACC<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxACC<7:0>: NCOx Accumulator, low byte
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined.
REGISTER 20-4: NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
NCOxACC<15:8>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxACC<15:8>: NCOx Accumulator, high byte
REGISTER 20-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC<19:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NCOxACC<19:16>: NCOx Accumulator, upper byte
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REGISTER 20-6: NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCOxINC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxINC<7:0>: NCOx Increment, low byte
REGISTER 20-7: NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxINC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxINC<15:8>: NCOx Increment, high byte
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TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCOx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CLC1SEL0
CLC1SEL1
CWG1CON1
INTCON
—
—
LC1D2S2 LC1D2S1 LC1D2S0
LC1D4S2 LC1D4S1 LC1D4S0
—
—
LC1D1S2 LC1D1S1 LC1D1S0
LC1D3S2 LC1D3S1 LC1D3S0
112
113
140
40
G1ASDLB<1:0>
G1ASDLA<1:0>
TMR0IE INTE
—
—
G1IS<1:0>
GIE
PEIE
IOCIE
TMR0IF
INTF
IOCIF
NCO1ACCH
NCO1ACCL
NCO1ACCU
NCO1CLK
NCO1CON
NCO1INCH
NCO1INCL
PIE1
NCO1ACCH<15:8>
NCO1ACCL<7:0>
126
126
126
125
125
127
127
41
—
NCO1ACCU<19:16
N1PWS<2:0>
N1OE
—
—
—
—
—
N1CKS<1:0>
N1EN
N1OUT
N1POL
—
N1PFM
NCO1INCH<15:8>
NCO1INCL<7:0>
—
—
—
ADIE
ADIF
—
—
—
—
NCO1IE
NCO1IF
—
CLC1IE
CLC1IF
—
—
—
TMR2IE
TMR2IF
TRISA1
—
—
PIR1
42
TRISA
TRISA2
TRISA0
69
Legend:
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for NCO module.
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21.0 COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG)
produces a complementary waveform with dead-band
delay from a selection of input sources.
The CWG module has the following features:
• Selectable dead-band clock source control
• Selectable input sources
• Output enable control
• Output polarity control
• Dead-band control with Independent 6-bit rising
and falling edge dead-band counters
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
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FIGURE 21-1:
CWG BLOCK DIAGRAM
2
GxASDLA
00
10
11
2
GxCS
FOSC
‘0’
‘1’
GxASDLA = 01
1
cwg_clock
GxOEA
CWGxDBR
6
HFINTOSC
1
2
EN
R
=
=
GxIS
0
TRISx
TRISx
CWGxA
PWM1OUT
PWM2OUT
N1OUT
S
R
Q
Q
GxPOLA
Input Source
LC1OUT
CWGxDBF
6
GxOEB
EN
R
0
1
GxPOLB
CWGxB
GxASDLB = 01
00
10
11
‘0’
‘1’
CWG1FLT (INT pin)
GxASDFLT
GxASE
shutdown
GxASDLB
Auto-Shutdown
Source
2
S
S
R
Q
Q
D
Q
LC1OUT
GxASDCLC1
GxASE Data Bit
WRITE
GxARSEN
set dominate
x = CWG module number
PIC10(L)F320/322
FIGURE 21-2:
TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)
cwg_clock
PWM1
CWGxA
Rising Edge
Dead Band
Rising Edge Dead Band
Falling Edge Dead Band
Rising Edge D
Falling Edge Dead Band
CWGxB
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21.4.2
POLARITY CONTROL
21.1 Fundamental Operation
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active-high. Clearing the output
polarity bit configures the corresponding output as
active-low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.
The CWG generates a two output complementary
waveform from one of four selectable input sources.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 21.5 “Dead-Band Control”. A typical
operating waveform, with dead band, generated from a
single input signal is shown in Figure 21-2.
21.5 Dead-Band Control
Dead-band control provides for non-overlapping output
signals to prevent shoot-through current in power
switches. The CWG contains two 6-bit dead-band
counters. One dead-band counter is used for the rising
edge of the input source control. The other is used for
the falling edge of the input source control.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in
Section 21.9 “Auto-shutdown Control”.
Dead band is timed by counting CWG clock periods
from zero up to the value in the rising or falling dead-
band counter registers. See CWGxDBR and
CWGxDBF registers (Register 21-4 and Register 21-5,
respectively).
21.2 Clock Source
The CWG module allows the following clock sources
to be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
21.6 Rising Edge Dead Band
The clock sources are selected using the G1CS0 bit of
the CWGxCON0 register (Register 21-1).
The rising edge dead band delays the turn-on of the
CWGxA output from when the CWGxB output is turned
off. The rising edge dead-band time starts when the
rising edge of the input source signal goes true. When
this happens, the CWGxB output is immediately turned
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
21.3 Selectable Input Sources
The CWG can generate the complementary waveform
for the following input sources:
• PWM1
• PWM2
• N1OUT
• LC1OUT
The CWGxDBR register sets the duration of the dead-
band interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
The input sources are selected using the GxIS<1:0>
bits in the CWGxCON1 register (Register 21-2).
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
21.4 Output Control
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
Immediately after the CWG module is enabled, the
complementary drive is configured with both CWGxA
and CWGxB drives cleared.
21.4.1
OUTPUT ENABLES
Each CWG output pin has individual output enable
control. Output enables are selected with the GxOEA
and GxOEB bits of the CWGxCON0 register. When an
output enable control is cleared, the module asserts no
control over the pin. When an output enable is set, the
override value or active PWM waveform is applied to
the pin per the port priority selection. The output pin
enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
and CWG drive levels have no effect.
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21.7 Falling Edge Dead Band
The falling edge dead band delays the turn-on of the
CWGxB output from when the CWGxA output is turned
off. The falling edge dead-band time starts when the
falling edge of the input source goes true. When this
happens, the CWGxA output is immediately turned off
and the falling edge dead-band delay time starts. When
the falling edge dead-band delay time is reached, the
CWGxB output is turned on.
The CWGxDBF register sets the duration of the dead-
band interval on the falling edge of the input source
signal. This duration is from 0 to 64 counts of dead
band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
Refer to Figure 21-3 and Figure 21-4 for examples.
21.8 Dead-Band Uncertainty
When the rising and falling edges of the input source
triggers the dead-band counters, the input may be
asynchronous. This will create some uncertainty in the
dead-band time delay. The maximum uncertainty is
equal to one CWG clock period. Refer to Equation 21-1
for more detail.
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FIGURE 21-3:
DEAD-BAND OPERATION, CWGxDBR = 01H, CWGxDBF = 02H
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 21-4:
DEAD-BAND OPERATION, CWGxDBR = 03H, CWGxDBF = 04H, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
CWGxA
CWGxB
source shorter than dead band
PIC10(L)F320/322
EQUATION 21-1: DEAD-BAND DELAY TIME
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------
Fcwg_clock
EXAMPLE 21-1:
DEAD-BAND DELAY TIME
UNCERTAINTY
Fcwg_clock = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------
Fcwg_clock
1
= ------------------
16 MHz
= 625ns
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21.9 Auto-shutdown Control
21.10 Operation During Sleep
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can be
either cleared automatically or held until cleared by
software.
The CWG module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep, provided
that the CWG module is enabled, the input source is
active, and the HFINTOSC is selected as the clock
source, regardless of the system clock source
selected.
21.9.1
SHUTDOWN
The Shutdown state can be entered by either of the
following two methods:
• Software generated
• External Input
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input source
is active, the CPU will go idle during Sleep, but the
CWG will continue to operate and the HFINTOSC will
remain active.
21.9.1.1
Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will
force the CWG into the shutdown state.
This will have a direct effect on the Sleep mode current.
When auto-restart is disabled, the shutdown state will
persist as long as the GxASE bit is set.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
edge event. See Figure 21-6.
21.9.1.2
External Input Source
External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes high, the CWG outputs will immediately go to the
selected override levels without software delay. Any
combination of two input sources can be selected to
cause a shutdown condition. The two sources are:
• LC1OUT
• CWG1FLT
Shutdown inputs are selected using the GxASDS0 and
GxASDS1 bits of the CWGxCON2 register.
(Register 21-3).
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.
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21.11.2.1 Software controlled restart
21.11 Configuring the CWG
When the GxARSEN bit of the CWGxCON2 register is
cleared, the CWG must be restarted after an auto-shut-
down event by software.
The following steps illustrate how to properly configure
the CWG to ensure a synchronous start:
1. Ensure that the TRIS control bits corresponding
to CWGxA and CWGxB are set so that both are
configured as inputs.
The CWG will resume operation on the first rising edge
event after the GxASE bit is cleared. Clearing the shut-
down state requires all selected shutdown inputs to be
low, otherwise the GxASE bit will remain set.
2. Clear the GxEN bit, if not already cleared.
3. Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
21.11.2.2 Auto-Restart
4. Setup the following controls in CWGxCON2
auto-shutdown register:
When the GxARSEN bit of the CWGxCON2 register is
set, the CWG will restart from the auto-shutdown state
automatically.
• Select desired shutdown source.
• Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
After the shutdown event clears, the GxASE bit will
clear automatically and the CWG will resume operation
on the first rising edge event.
• Set the GxASE bit and clear the GxARSEN
bit.
5. Select the desired input source using the
CWGxCON1 register.
6. Configure the following controls in CWGxCON0
register:
• Select desired clock source.
• Select the desired output polarities.
• Set the output enables for the outputs to be
used.
7. Set the GxEN bit.
8. Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
9. If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automati-
cally. Otherwise, clear the GxASE bit to start the
CWG.
21.11.1 PIN OVERRIDE LEVELS
The levels driven to the output pins, while the shutdown
input is true, are controlled by the GxASDLA and
GxASDLB bits of the CWGxCON1 register
(Register 21-2). GxASDLA controls the CWG1A
override level and GxASDLB controls the CWG1B
override level. The control bit logic level corresponds to
the output logic drive level while in the shutdown state.
The polarity control does not apply to the override level.
21.11.2 AUTO-SHUTDOWN RESTART
After an auto-shutdown event has occurred, there are
two ways to have resume operation:
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 21-5 and Figure 21-6.
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FIGURE 21-5: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (GxARSEN = 0)
GxASE Cleared by Software
Shutdown Event Ceases
CWG Input
Source
Shutdown Source
GxASE
Tri-State (No Pulse)
Tri-State (No Pulse)
CWG1A
CWG1B
No Shutdown
Output Resumes
Shutdown
FIGURE 21-6:
SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (GxARSEN = 1)
Shutdown Event Ceases
GxASE auto-cleared by hardware
CWG Input
Source
Shutdown Source
GxASE
CWG1A
Tri-State (No Pulse)
CWG1B
Tri-State (No Pulse)
Shutdown
No Shutdown
Output Resumes
PIC10(L)F320/322
21.12 CWG Control Registers
REGISTER 21-1: CWGxCON0: CWG CONTROL REGISTER 0
R/W-0/0
GxEN
R/W-0/0
GxOEB
R/W-0/0
GxOEA
R/W-0/0
GxPOLB
R/W-0/0
GxPOLA
U-0
—
U-0
—
R/W-0/0
GxCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3
GxEN: CWGx Enable bit
1= Module is enabled
0= Module is disabled
GxOEB: CWGxB Output Enable bit
1= CWGxB is available on appropriate I/O pin
0= CWGxB is not available on appropriate I/O pin
GxOEA: CWGxA Output Enable bit
1= CWGxA is available on appropriate I/O pin
0= CWGxA is not available on appropriate I/O pin
GxPOLB: CWGxB Output Polarity bit
1= Output is inverted polarity
0= Output is normal polarity
GxPOLA: CWGxA Output Polarity bit
1= Output is inverted polarity
0= Output is normal polarity
bit 2-1
bit 0
Unimplemented: Read as ‘0’
GxCS0: CWGx Clock Source Select bit
1= HFINTOSC
0= FOSC
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PIC10(L)F320/322
REGISTER 21-2: CWGxCON1: CWG CONTROL REGISTER 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
—
U-0
—
R/W-0/0
R/W-0/0
GxASDLB<1:0>
GxASDLA<1:0>
GxIS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
GxASDLB<1:0>: CWGx Shutdown State for CWGxB
When an auto shutdown event is present (GxASE = 1):
11= CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.
10= CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.
01= CWGxB pin is tri-stated
00= CWGxB pin is driven to its inactive state after the selected dead-band interval. GxPOLB still will
control the polarity of the output.
bit 5-4
GxASDLA<1:0>: CWGx Shutdown State for CWGxA
When an auto shutdown event is present (GxASE = 1):
00= CWGxA pin is driven to its inactive state after the selected dead-band interval. GxPOLA still will
control the polarity of the output.
01= CWGxA pin is tri-stated
10= CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.
11= CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
GxIS<1:0>: CWGx Dead-band Source Select bits
11= LC1OUT
10= N1OUT
01= PWM2OUT
00= PWM1OUT
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PIC10(L)F320/322
REGISTER 21-3: CWGxCON2: CWG CONTROL REGISTER 2
R/W/HC/HS-0/0
GxASE
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
GxARSEN
GxASDCLC1 GxASDFLT
bit 0
bit 7
Legend:
HC = Bit is cleared by hardware
R = Readable bit
HS = Bit is set by hardware
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
GxASE: Auto-Shutdown Event Status bit
1= An Auto-Shutdown event has occurred. GxOEB/GxOEA Output Controls overridden, Outputs
disabled.
0= No Auto-Shutdown event has occurred, or an Auto-restart has occurred. GxOEB/GxOEA
Output Controls enabled.
GxARSEN: Auto-Restart Enable bit
1= Auto-restart is enabled
0= Auto-restart is disabled
bit 5-2
bit 1
Unimplemented: Read as ‘0’
GxASDCLC1: CWG Auto-shutdown Source Enable bit 1
1= Shutdown when LC1OUT is high
0= LC1OUT has no effect on shutdown
bit 0
GxASDFLT: CWG Auto-shutdown Source Enable bit 0
1= Shutdown when CWG1FLT input is low
0= CWG1FLT input has no effect on shutdown
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PIC10(L)F320/322
REGISTER 21-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING
DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising Counts bits
11 1111= 63-64 counts of dead band
11 1110= 62-63 counts of dead band
00 0010= 2-3 counts of dead band
00 0001= 1-2 counts of dead band
00 0000= 0 counts of dead band
REGISTER 21-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING
DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling Counts bits
11 1111= 63-64 counts of dead band
11 1110= 62-63 counts of dead band
00 0010= 2-3 counts of dead band
00 0001= 1-2 counts of dead band
00 0000= 0 counts of dead band. Dead-band generation is bypassed.
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PIC10(L)F320/322
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
—
—
G1POLA
—
ANSA2
—
ANSA1
—
ANSA0
G1CS0
70
CWG1CON0
CWG1CON1
CWG1CON2
CWG1DBF
CWG1DBR
G1EN
G1OEB
G1OEA
G1POLB
139
140
141
142
142
G1ASDLB<1:0>
G1ASDLA<1:0>
G1IS<1:0>
G1ASDCLC1 G1ASDFLT
—
G1ASE
G1ARSEN
—
—
—
—
CWG1DBF<5:0>
CWG1DBR<5:0>
—
—
—
—
—
—
—
—
LATA
—
—
—
—
—
LATA2
LATA1
LATA0
70
69
TRISA
Legend:
—
TRISA2
TRISA1
TRISA0
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
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PIC10(L)F320/322
22.3 Common Programming Interfaces
22.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin, 6
connector) configuration. See Figure 22-1.
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
FIGURE 22-1:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
NC
2 4 6
VDD
In Program/Verify mode the Program Memory, User
IDs and the Configuration Words are programmed
through serial communications. The ICSPDAT pin is a
bidirectional I/O used for transferring the serial data
and the ICSPCLK pin is the clock input. For more
information on ICSP™ refer to the “PIC10(L)F320/322
Flash Memory Programming Specification" (DS41572).
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
VPP/MCLR
VSS
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
22.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
5 = ICSPCLK
6 = No Connect
22.2 Low-Voltage Programming Entry
Mode
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 22-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Word is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 5.4 “Low-Power
Brown-out Reset (LPBOR)” for more information.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
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PIC10(L)F320/322
FIGURE 22-2:
PICkit™ STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
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PIC10(L)F320/322
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 22-3 for more
information.
FIGURE 22-3:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
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PIC10(L)F320/322
TABLE 23-1: OPCODE FIELD
DESCRIPTIONS
23.0 INSTRUCTION SET SUMMARY
The PIC10(L)F320/322 instruction set is highly orthog-
onal and is comprised of three basic categories:
Field
Description
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
Bit address within an 8-bit file register
Literal field, constant data or label
k
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 23-1, while the various opcode
fields are summarized in Table 23-1.
x
Don’t care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
Table 23-2 lists the instructions recognized by the
MPASMTM assembler.
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
PD
Power-down bit
FIGURE 23-1:
GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
Literal and control operations
General
13
8
7
0
0
23.1 Read-Modify-Write Operations
OPCODE
k (literal)
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
For example, a CLRF PORTA instruction will read
PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the
IOCIF flag.
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PIC10(L)F320/322
TABLE 23-2: INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
1, 2
1, 2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
–
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1, 2
1, 2
1, 2
1, 2
1, 2
00 0010 dfff ffff C, DC, Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1, 2
1, 2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C, DC, Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO, PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO, PD
11 110x kkkk kkkk C, DC, Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
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PIC10(L)F320/322
23.2 Instruction Descriptions
BCF
Bit Clear f
ADDLW
Add literal and W
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
0 b 7
Operands:
Operation:
Status Affected:
Description:
(W) + k (W)
C, DC, Z
Operation:
0 (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the 8-bit literal ‘k’
and the result is placed in the
W register.
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[ label ] BSF f,b
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
0 b 7
Operands:
0 f 127
d 0,1
Operation:
1 (f<b>)
Operation:
(W) + (f) (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit ‘b’ in register ‘f’ is set.
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
BTFSC
Bit Test f, Skip if Clear
ANDLW
AND literal with W
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
0 f 127
0 b 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
skip if (f<b>) = 0
Z
Status Affected: None
The contents of W register are
AND’ed with the 8-bit literal ‘k’.
The result is placed in the W
register.
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
2-cycle instruction.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF f,d
Operands:
0 f 127
d 0,1
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
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PIC10(L)F320/322
CLRWDT
Clear Watchdog Timer
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] BTFSS f,b
Operands:
Operation:
None
Operands:
0 f 127
0 b < 7
00h WDT
0 WDT prescaler,
1 TO
Operation:
skip if (f<b>) = 1
Status Affected: None
1 PD
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
Status Affected: TO, PD
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
2-cycle instruction.
Status bits TO and PD are set.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
0 k 2047
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
(f) (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The 11-bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a 2-cycle instruction.
CLRF
Clear f
DECF
Decrement f
Syntax:
[ label ] CLRF
0 f 127
f
Syntax:
[ label ] DECF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
DS40001585D-page 150
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOPis
executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOPis executed
instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO k
0 k 2047
Syntax:
[ label ] IORLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
(W) .OR. k (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the 8-bit literal ‘k’. The
result is placed in the
Description:
GOTOis an unconditional branch.
The 11-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a
2-cycle instruction.
W register.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(W) .OR. (f) (destination)
Operation:
(f) + 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
2011-2015 Microchip Technology Inc.
DS40001585D-page 151
PIC10(L)F320/322
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
MOVF
Move f
Syntax:
f
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
Status Affected:
Description:
0 f 127
d [0,1]
Operation:
(f) (dest)
None
Status Affected:
Description:
Z
Move data from W register to
register ‘f’.
The contents of register ‘f’ is
moved to a destination dependent
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1is useful to test a file
register since Status flag Z is
affected.
Words:
1
1
Cycles:
Example:
MOVW
F
OPTION_REG
Before Instruction
OPTION_REG = 0xFF
Words:
1
1
W
=
0x4F
After Instruction
Cycles:
Example:
OPTION_REG = 0x4F
MOVF
FSR, 0
W
=
0x4F
After Instruction
W
=
value in FSR
register
Z
=
1
MOVLW
Syntax:
Move literal to W
NOP
No Operation
[ label ] MOVLW k
0 k 255
Syntax:
[ label ] NOP
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
Words:
None
k (W)
No operation
Status Affected: None
None
Description:
The 8-bit literal ‘k’ is loaded into W
register. The “don’t cares” will
assemble as ‘0’s.
No operation.
1
Cycles:
1
Words:
1
1
NOP
Example:
Cycles:
Example:
MOVLW
0x5A
After Instruction
W
=
0x5A
DS40001585D-page 152
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return with literal in W
Syntax:
Syntax:
[ label ] RETLW k
Operands:
Operation:
Operands:
Operation:
0 k 255
TOS PC,
1 GIE
k (W);
TOS PC
Status Affected:
Description:
None
Status Affected:
Description:
None
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE (INT-
CON<7>). This is a 2-cycle
instruction.
The W register is loaded with the
8-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a 2-cycle instruction.
Words:
1
2
Cycles:
Example:
Words:
1
CALL TABLE;W contains
Cycles:
Example:
2
;table offset
;value
RETFIE
GOTO DONE
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
After Interrupt
PC = TOS
TABLE
GIE =
1
RETLW k2
;
•
•
•
RETLW kn ;End of table
DONE
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a 2-cycle instruc-
tion.
2011-2015 Microchip Technology Inc.
DS40001585D-page 153
PIC10(L)F320/322
RLF
Rotate Left f through Carry
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
See description below
C
Status Affected:
Description:
0 PD
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
C
Register f
Words:
1
1
Cycles:
Example:
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW k
0 k 255
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
k - (W) W)
Operation:
See description below
C
Status Affected: C, DC, Z
Status Affected:
Description:
Description: The W register is subtracted (2’s
complement method) from the 8-bit
literal ‘k’. The result is placed in the
W register.
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Result
Condition
C = 0
W k
C
Register f
C = 1
W k
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
DS40001585D-page 154
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
SUBWF
Subtract W from f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] XORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - (W) destination)
Operation:
(W) .XOR. (f) destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
Subtract (2’s complement method)
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
C = 0
W f
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW
Exclusive OR literal with W
Syntax:
[ label ] XORLW k
0 k 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
The contents of the W register
are XOR’ed with the 8-bit
literal ‘k’. The result is placed in
the W register.
2011-2015 Microchip Technology Inc.
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PIC10(L)F320/322
24.0 ELECTRICAL SPECIFICATIONS
(†)
24.1 Absolute Maximum Ratings
Ambient temperature under bias...................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on pins with respect to VSS
on VDD pin
PIC10F320/322 ......................................................................................................... -0.3V to +6.5V
PIC10LF320/322 ....................................................................................................... -0.3V to +4.0V
on MCLR pin ........................................................................................................................... -0.3V to +9.0V
on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)
Maximum current
on VSS pin(1)
-40°C TA +85°C .............................................................................................................. 250 mA
+85°C TA +125°C ............................................................................................................. 85 mA
on VDD pin(1)
-40°C TA +85°C .............................................................................................................. 250 mA
+85°C TA +125°C ............................................................................................................. 85 mA
Sunk by any I/O pin .............................................................................................................................. 50 mA
Sourced by any I/O pin ......................................................................................................................... 50 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA
Total power dissipation(2) ...............................................................................................................................800 mW
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Section 24.4 “Thermal
Considerations” to calculate device specifications.
2: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001585D-page 156
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PIC10(L)F320/322
24.2 Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage(1)
PIC10LF320/322
VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V
VDDMIN (16 MHz < Fosc 20 MHz)......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +3.6V
PIC10F320/322
VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V
VDDMIN (16 MHz < Fosc 20 MHz)......................................................................................... +2.5V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................... +85°C
Extended Temperature
TA_MIN...................................................................................................................................... -40°C
TA_MAX.................................................................................................................................. +125°C
Note 1: See Parameter D001, DC Characteristics: Supply Voltage.
2011-2015 Microchip Technology Inc.
DS40001585D-page 157
PIC10(L)F320/322
FIGURE 24-1:
PIC10F320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
5.5
2.5
2.3
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 24-6 for each Oscillator mode’s supported frequencies.
FIGURE 24-2:
PIC10LF320/322 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
3.6
2.5
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 24-6 for each Oscillator mode’s supported frequencies.
DS40001585D-page 158
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
24.3
DC Characteristics
TABLE 24-1: SUPPLY VOLTAGE
PIC10LF320/322
Standard Operating Conditions (unless otherwise stated)
PIC10F320/322
Param.
No.
Sym.
Characteristic
Supply Voltage
Min.
Typ†
Max.
Units
Conditions
D001
VDD
1.8
2.5
—
—
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 20 MHz
D001
2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 20 MHz
D002*
VDR
RAM Data Retention Voltage(1)
1.5
1.7
—
—
—
—
—
—
—
—
V
V
V
V
V
Device in Sleep mode
Device in Sleep mode
D002*
VPOR*
Power-on Reset Release Voltage
Power-on Reset Rearm Voltage
1.6
0.8
1.7
VPORR*
—
Device in Sleep mode
Device in Sleep mode
—
D003
VFVR
Fixed Voltage Reference Voltage
1x gain (1.024V nominal)
2x gain (2.048V nominal)
4x gain (4.096V nominal)
VDD 2.5V, -40°C TA +85°C
VDD 2.5V, -40°C TA +85°C
VDD 4.75V, -40°C TA +85°C
-8
—
—
+6
—
%
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
V/ms See Section 5.1 “Power-On Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2011-2015 Microchip Technology Inc.
DS40001585D-page 159
PIC10(L)F320/322
FIGURE 24-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
(2)
(3)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
DS40001585D-page 160
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 24-2: SUPPLY VOLTAGE (IDD)(1,2)
PIC10LF320/322
Standard Operating Conditions (unless otherwise stated)
PIC10F320/322
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
D013
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
34
60
45
105
101
148
211
290
500
430
600
775
1.3
1.8
1.4
1.8
4.1
6.5
44
A
A
A
A
A
A
A
A
A
A
mA
mA
mA
mA
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.6
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
FOSC = 500 kHz
EC mode
D013
76
FOSC = 500 kHz
EC mode
110
153
190
350
290
395
480
0.8
1.1
0.8
1.1
2.2
3.9
31
D014
D014
FOSC = 8 MHz
EC mode
FOSC = 8 MHz
EC mode
D015
D015
D016
D016
FOSC = 20 MHz
EC mode
FOSC = 20 MHz
EC mode
FOSC = 32 kHz
LFINTOSC mode, 85°C
FOSC = 32 kHz
LFINTOSC mode, 85°C
40
57
71
117
4.5
7.0
44
D016A
D016A
3.2
4.8
31
FOSC = 32 kHz
LFINTOSC mode, 125°C
FOSC = 32 kHz
LFINTOSC mode,125°C
40
57
71
117
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
2011-2015 Microchip Technology Inc.
DS40001585D-page 161
PIC10(L)F320/322
TABLE 24-2: SUPPLY VOLTAGE (IDD)(1,2) (CONTINUED)
PIC10LF320/322
Standard Operating Conditions (unless otherwise stated)
PIC10F320/322
Conditions
Note
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
D017
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
213
264
290
360
368
422
515
0.50
0.70
1.0
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
FOSC = 500 kHz
HFINTOSC mode
D017
272
A
FOSC = 500 kHz
HFINTOSC mode
310
A
372
A
D018
D018
0.33
0.43
0.45
0.56
0.64
0.46
0.73
0.60
0.76
0.85
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
1.1
1.2
D019
D019
1.1
FOSC = 16 MHz
HFINTOSC mode
1.2
1.1
FOSC = 16 MHz
HFINTOSC mode
1.2
1.3
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
DS40001585D-page 162
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 24-3: POWER-DOWN CURRENTS (IPD)(1,2)
PIC10LF320/322
Standard Operating Conditions (unless otherwise stated)
PIC10F320/322
Conditions
Units
Param
No.
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
VDD
Note
D023
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.06
0.08
0.20
0.30
0.40
0.5
0.8
4.0
4.2
4.3
30
1.1
1.3
1.1
1.4
2.4
9
2
2
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.0
5.0
3.0
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
WDT, BOR, and FVR disabled,
all Peripherals Inactive
D023
2
WDT, BOR, and FVR disabled,
all Peripherals Inactive
2
2.4
11
13
12
14
16
120
123
120
133
170
18
20
20.2
15
15
20
5
D024
D024
WDT Current (Note 1)
WDT Current (Note 1)
11
10
12
14
96
106
96
106
136
16
18
20
10
10
15
4
D025
D025
FVR current
FVR current
39
32
39
70
D026
D026
7.5
8
BOR Current (Note 1)
BOR Current (Note 1)
9
D026A
D026A
2.7
3.0
3.2
0.1
0.1
3.4
3.6
3.8
250
250
280
280
280
LPBOR Current
LPBOR Current
D028
D028
A/D Current (Note 1, Note 3), no
conversion in progress
5
6
6
7
A/D Current (Note 1, Note 3), no
conversion in progress
7
8
8
9
D029
D029
—
—
—
—
—
—
—
—
—
—
A/D Current (Note 1, Note 3),
conversion in progress
A/D Current (Note 1, Note 3),
conversion in progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
2011-2015 Microchip Technology Inc.
DS40001585D-page 163
PIC10(L)F320/322
TABLE 24-4: I/O PORTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
VIL
Characteristic
Min.
Typ†
Max.
Units
Conditions
Input Low Voltage
I/O PORT:
D032
D032A
D033
D034
with TTL buffer
—
—
—
—
—
—
—
—
0.8
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.2 VDD
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
MCLR
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
2.0
—
—
—
—
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
D040A
0.25 VDD +
0.8
D041
D042
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
—
—
—
—
V
V
2.0V VDD 5.5V
(2)
IIL
Input Leakage Current
D060
I/O ports
—
—
± 5
± 125
nA
VSS VPIN VDD, Pin at
high-impedance @ 85°C
± 5
± 1000
± 200
nA 125°C
D061
MCLR
± 50
nA
A
V
VSS VPIN VDD @ 85°C
IPUR
VOL
Weak Pull-up Current
D070*
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
Output Low Voltage
D080
I/O ports
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
—
0.6
—
VOH
Output High Voltage
D090
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
VDD - 0.7
V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
DS40001585D-page 164
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 24-5: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
No.
Program Memory Programming
Specifications
D110
D111
D112
VIHH
IDDP
Voltage on MCLR/VPP pin
Supply Current during Programming
VDD for Bulk Erase
8.0
—
—
—
—
9.0
10
V
mA
V
(Note 2)
2.7
VDD
max.
D113
VPEW
VDD for Write or Row Erase
VDD
min.
—
—
VDD
max.
V
D114
D115
IPPPGM Current on MCLR/VPP during
Erase/Write
—
1.0
5.0
—
mA
mA
IDDPGM Current on VDD during Erase/Write
—
Program Flash Memory
D121
D122
EP
Cell Endurance
VDD for Read
10K
—
—
E/W -40C to +85C (Note 1)
VPR
VDD
min.
VDD
max.
V
D123
D124
TIW
Self-timed Write Cycle Time
—
2
2.5
—
ms
TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
D125
EHEFC High-Endurance Flash Cell
100K
—
—
E/W 0°C TA 60, lower byte last
128 addresses
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
2011-2015 Microchip Technology Inc.
DS40001585D-page 165
PIC10(L)F320/322
24.4 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
Characteristic
Typ.
Units
Conditions
6-pin SOT-23 package
TH01
JA
Thermal Resistance Junction to Ambient
60
80
C/W
C/W
C/W
C/W
C/W
C/W
C
8-pin PDIP package
8-pin DFN package
6-pin SOT-23 package
8-pin PDIP package
8-pin DFN package
90
TH02
JC
Thermal Resistance Junction to Case
31.4
24
24
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
150
—
W
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD
(1)
PINTERNAL Internal Power Dissipation
—
W
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/JA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature
3: TJ = Junction Temperature
DS40001585D-page 166
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
24.5 AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKR
CS
osc
rd
CLKIN
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 24-4:
LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
2011-2015 Microchip Technology Inc.
DS40001585D-page 167
PIC10(L)F320/322
FIGURE 24-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS02
OS03
CLKR
(CLKROE = 1)
TABLE 24-6: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max.
Units
MHz EC mode
Conditions
No.
OS01
OS02
OS03
FOSC
External CLKIN Frequency(1)
External CLKIN Period(1)
Instruction Cycle Time(1)
DC
31.25
200
—
—
20
TOSC
TCY
ns
ns
EC Oscillator mode
TCY = 4/FOSC
TCY
DC
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 24-7: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Freq.
Tolerance
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency(1)
±3%
-8 to +4%
—
—
16.0
16.0
—
—
MHz 0°C TA +85°C, VDD 2.3V
MHz -40°C TA 125°C
OS09
LFOSC
Internal LFINTOSC Frequency
±25%
—
—
—
31
5
—
8
kHz
OS10* TWARM
HFINTOSC
s
Wake-up from Sleep Start-up Time
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS40001585D-page 168
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 24-6:
HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE
Rev. 10-000135D
2/11/2014
125
85
-ꢁ% to +ꢂ%
60
ꢀ%
25
0
-ꢁ% to +ꢂ%
-40
1.8
2.3
5.5
VDD (V)
2011-2015 Microchip Technology Inc.
DS40001585D-page 169
PIC10(L)F320/322
FIGURE 24-7:
CLKR AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKR
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 24-8: CLKR AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
(1)
OS11
OS12
OS13
TosH2ckL
TosH2ckH
TckL2ioV
FOSC to CLKOUT
—
—
—
—
—
—
70
72
20
ns
ns
ns
3.3V VDD 5.0V
3.3V VDD 5.0V
(1)
FOSC to CLKOUT
CLKOUT to Port out valid(1)
(1)
OS14
OS15
OS16
TioV2ckH
TosH2ioV
TosH2ioI
Port input valid before CLKOUT
TOSC + 200 ns
—
50
—
—
70*
—
ns
ns
ns
Fosc (Q1 cycle) to Port out valid
—
3.3V VDD 5.0V
3.3V VDD 5.0V
Fosc (Q2 cycle) to Port input invalid
50
(I/O in setup time)
OS17
TioV2osH
Port input valid to Fosc(Q2 cycle)
(I/O in setup time)
20
—
—
ns
ns
ns
OS18* TioR
OS19* TioF
Port output rise time
Port output fall time
—
—
40
15
72
32
VDD = 1.8V
3.3V VDD 5.0V
—
—
28
15
55
30
VDD = 1.8V
3.3V VDD 5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC.
DS40001585D-page 170
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 24-8:
RESET, WATCHDOG TIMER, AND POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 24-9:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33
(due to BOR)
2011-2015 Microchip Technology Inc.
DS40001585D-page 171
PIC10(L)F320/322
TABLE 24-9: RESET, WATCHDOG TIMER, POWER-UP TIMER AND BROWN-OUT RESET
PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
No.
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 3.3-5V, -40°C to +85°C
s VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
10
16
27
ms VDD = 3.3V-5V
1:16 Prescaler used
33*
34*
TPWRT
TIOZ
Power-up Timer Period, PWRTE = 0
40
—
64
—
140
2.0
ms
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
s
(1)
35
VBOR
Brown-out Reset Voltage
2.55
2.70
2.85
V
BORV = 0
2.30 2.40
2.55
2.05
V
V
BORV = 1 (PIC10F320/322)
BORV = 1(PIC10LF320/322)
1.80
1.90
36*
37*
38
VHYST
Brown-out Reset Hysteresis
0
25
50
5
mV -40°C to +85°C
TBORDC Brown-out Reset DC Response Time
1
3
s
VDD VBOR
LPBOR = 1
VLPBOR Low-Power Brown-Out Reset Voltage 1.8
These parameters are characterized but not tested.
2.1
2.5
V
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 24-10:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
TMR0
TABLE 24-10: TIMER0 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
No.
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
Typ†
Max.
Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40001585D-page 172
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 24-11:
CLC PROPAGATION TIMING
Rev. 10-000031A
7/30/2013
LCx_in[n](1)
CLC
CLC
CLC
CLCx
CLCxINn
CLCxINn
LCx_out(1)
Input time
Module
Output time
CLC
CLC
Module
CLC
CLCx
LCx_in[n](1)
LCx_out(1)
Input time
Output time
CLC01
CLC02
CLC03
Note 1: See FIGURE 19-1: CLCx Simplified Block Diagram, to identify specific CLC signals.
TABLE 24-11: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min. Typ† Max. Units
Conditions
CLC01* TCLCIN
CLC02* TCLC
CLC input time
CLC module input to output propagation time
—
7
—
ns
—
—
24
12
—
—
ns VDD = 1.8V
ns VDD > 3.6V
CLC03* TCLCOUT CLC output time
Rise Time
Fall Time
—
—
—
OS18
OS19
45
—
—
—
—
—
(Note 1)
(Note 1)
CLC04* FCLCMAX CLC maximum switching frequency
MHz
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:See Table 24-8 for OS18 and OS19 rise and fall times.
2011-2015 Microchip Technology Inc.
DS40001585D-page 173
PIC10(L)F320/322
TABLE 24-12: A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
No.
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
—
—
8
bit
Integral Error
±1.7
±1
LSb VREF = 3.0V
Differential Error
LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error
—
—
—
—
—
—
—
±2.5
±2.0
VDD
VREF
10
LSb VREF = 3.0V
LSb VREF = 3.0V
AD05 EGN Gain Error
AD06 VREF Reference Voltage
AD07 VAIN Full-Scale Range
1.8
VSS
—
V
V
VREF = (VREF+ minus VREF-)
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
Can go higher if external 0.01F capacitor is
present on input pin.
k
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
TABLE 24-13: A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
No.
AD130* TAD
A/D Clock Period
1.0
—
6.0
6.0
s
s
TOSC-based
ADCS<1:0> = 11(ADRC mode)
A/D Internal FRC Oscillator Period 1.0
1.6
AD131 TCNV Conversion Time (not including
Acquisition Time)(1)
—
—
9.5
—
TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time
5.0
—
—
—
s
AD133* THCD Holding Capacitor Disconnect Time
—
—
1/2 TAD
FOSC-based
1/2 TAD + 1TCY
ADCS<2:0> = x11 (ADC FRC mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
DS40001585D-page 174
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 24-12:
A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON, GO
1 Tcy
AD134
Q4
(TOSC/2(1)
)
AD131
AD130
A/D CLK
7
6
5
4
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 Tcy
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
FIGURE 24-13:
A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON, GO
AD134
Q4
(1)
1 Tcy
(TOSC/2 + TCY
)
AD131
AD130
A/D CLK
A/D Data
7
6
5
3
2
1
0
4
NEW_DATA
1 Tcy
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
2011-2015 Microchip Technology Inc.
DS40001585D-page 175
PIC10(L)F320/322
25.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
DS40001585D-page 176
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
26.1 MPLAB X Integrated Development
Environment Software
26.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
- MPLAB PM3 Device Programmer
• Smart code completion makes suggestions and
provides hints as you type
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Automatic code formatting based on user-defined
rules
• Third-party development tools
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2011-2015 Microchip Technology Inc.
DS40001585D-page 177
PIC10(L)F320/322
26.2 MPLAB XC Compilers
26.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16, and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
26.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
26.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
DS40001585D-page 178
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
26.6 MPLAB X SIM Software Simulator
26.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the MPLAB
IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
26.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the tar-
get via a Microchip debug (RJ-11) connector (compati-
ble with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
26.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
26.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2011-2015 Microchip Technology Inc.
DS40001585D-page 179
PIC10(L)F320/322
26.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
26.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
®
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS40001585D-page 180
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
27.0 PACKAGING INFORMATION
27.1 Package Marking Information
6-Lead SOT-23
Example
LA11
XXNN
8-Lead PDIP (300 mil)
Example
XXXXXXXX
XXXXXNNN
10F320
I/P 07Q
1110
e
3
YYWW
8-Lead DFN (2x3x0.9 mm)
Example
BAA
110
20
Legend: XX...X Product-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011-2015 Microchip Technology Inc.
DS40001585D-page 181
PIC10(L)F320/322
TABLE 27-1: 8-LEAD 2x3 DFN (MC) TOP
MARKING
TABLE 27-2: 6-LEAD SOT-23 (OT)
PACKAGE TOP MARKING
Part Number
Marking
Part Number
Marking
PIC10F322(T)-I/MC
PIC10F322(T)-E/MC
PIC10F320(T)-I/MC
PIC10F320(T)-E/MC
PIC10LF322(T)-I/MC
PIC10LF322(T)-E/MC
PIC10LF320(T)-I/MC
PIC10LF320(T)-E/MC
BAA
BAB
BAC
BAD
BAF
BAG
BAH
BAJ
PIC10F322(T)-I/OT
PIC10F322(T)-E/OT
PIC10F320(T)-I/OT
PIC10F320(T)-E/OT
PIC10LF322(T)-I/OT
PIC10LF322(T)-E/OT
PIC10LF320(T)-I/OT
PIC10LF320(T)-E/OT
LA/LJ
LB/LK
LC
LD
LE
LF
LG
LH
DS40001585D-page 182
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
27.2 Package Details
The following sections give the technical details of the packages.
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2011-2015 Microchip Technology Inc.
DS40001585D-page 183
PIC10(L)F320/322
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001585D-page 184
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2011-2015 Microchip Technology Inc.
DS40001585D-page 185
PIC10(L)F320/322
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS40001585D-page 186
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
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2011-2015 Microchip Technology Inc.
DS40001585D-page 187
PIC10(L)F320/322
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001585D-page 188
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A (07/2011)
Original release.
Revision B (02/2014)
Electrical Specifications update and new formats;
Minor edits.
Revision C (05/2015)
Updated Figures 7-1 and 11-1. Update Sections 5.4.1,
24.1, and 24.3. Updated Tables 24-2 and 24-9.
Revision D (11/2015)
Updated the “eXtreme Low-Power (XLP) Features”
section; added “Memory” section. Updated “Family
Types” table; Updated Table 2-1, 24-5, 24-7, 24-9,
24-12 and 24-13; Updated Figure 7-1, 24-6 and section
15.2.5; Other minor corrections.
2011-2015 Microchip Technology Inc.
DS40001585D-page 189
PIC10(L)F320/322
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://www.microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
DS40001585D-page 190
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
PART NO.
X
/XX
XXX
-
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
Pattern
a)
PIC10LF320T - I/OT
Tape and Reel,
Industrial temperature,
SOT-23 package
b)
c)
PIC10F322 - I/P
Industrial temperature
PDIP package
Device:
PIC10F320, PIC10LF320, PIC10F322, PIC10LF322
Blank = Standard packaging (tube or tray)
PIC10F322 - E/MC
Extended temperature,
DFN package
Tape and Reel
Option:
T
= Tape and Reel(1)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
Pattern:
OT
P
= SOT-23
= PDIP
= DFN
MC
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2011-2015 Microchip Technology Inc.
DS40001585D-page 191
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2011-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0020-2
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
DS40001585D-page 192
2011-2015 Microchip Technology Inc.
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
Hong Kong
Tel: 852-2943-5100
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Germany - Dusseldorf
Tel: 49-2129-3766400
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Germany - Karlsruhe
Tel: 49-721-625370
India - Pune
Tel: 91-20-3019-1500
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Austin, TX
Tel: 512-257-3370
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Boston
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Dongguan
Tel: 86-769-8702-9880
Italy - Venice
Tel: 39-049-7625286
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
Cleveland
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Poland - Warsaw
Tel: 48-22-3325737
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Sweden - Stockholm
Tel: 46-8-5090-4654
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Detroit
Novi, MI
UK - Wokingham
Tel: 44-118-921-5800
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Tel: 248-848-4000
Fax: 44-118-921-5820
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
New York, NY
Tel: 631-435-6000
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
San Jose, CA
Tel: 408-735-9110
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
07/14/15
2011-2015 Microchip Technology Inc.
DS40001585D-page 193
相关型号：
PIC10F322T-E/MC
8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO8, 2 X 3 MM, 0.90 MM HEIGHT, PLASTIC, DFN-8
MICROCHIP
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