PIC12C671 [MICROCHIP]
EPROM Memory Programming Specification; EPROM存储器编程规范
| 型号： | PIC12C671 |
| 厂家： | 
MICROCHIP |
| 描述： | EPROM Memory Programming Specification |
| 文件： | 总14页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12C67X AND PIC12CE67X
EPROM Memory Programming Specification
This document includes the programming
specifications for the following devices:
Pin Diagram:
PDIP
• PIC12C671
• PIC12C672
• PIC12CE673
• PIC12CE674
VSS
VDD
1
2
3
4
8
7
6
5
GP0/AN0
GP1/AN1/VREF
GP5/OSC1/CLKIN
GP4/OSC2/AN3/
CLKOUT
GP3/MCLR/VPP
GP2/T0CKI/
AN2/INT
1.0
PROGRAMMING THE
PIC12C67X AND PIC12CE67X
The PIC12C67X and PIC12CE67X can be pro-
grammed using a serial method. In serial mode the
PIC12C67X and PIC12CE67X can be programmed
while in the users system. This allows for increased
design flexibility.
1.1
Hardware Requirements
The PIC12C67X and PIC12CE67X requires two pro-
grammable power supplies, one for VDD (2.0V to 6.0V
recommended) and one for VPP (12V to 14V). Both
supplies should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC12C67X and
PIC12CE67X allows programming of user program
memory, special locations used for ID, and the configu-
ration word for the PIC12C67X and PIC12CE67X.
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12C671/672 and PIC12CE673/674
During Programming
Pin Name
Pin Name
CLOCK
DATA
VPP
Pin Type
Pin Description
GP1
GP0
I
I/O
P
Clock input
Data input/output
Programming Power
Power Supply
Ground
GP3/MCLR/VPP
VDD
VDD
P
VSS
VSS
P
Legend: I = Input, O = Output, P = Power
1998 Microchip Technology Inc.
DS40175A-page 1
PIC12C67X and PIC12CE67X
In the configuration memory space, 0x2000-0x20FF
are utilized. When in configuration memory, as in the
user memory, the 0x2000-0x2XFF segment is repeat-
edly accessed as the PC exceeds 0x2XFF (see
Figure 2-1).
2.0
PROGRAM MODE ENTRY
2.1
User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC12C67X family.
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
0x2003].
TABLE 2-1:
IMPLEMENTATION OF
PROGRAM MEMORY IN THE
PIC12C67X
Note 1: All other locations in PIC configuration
memory are reserved and should not be
programmed.
Device
Program Memory Size
Note 2: Due to the secure nature of the on-board
PIC12C671/
PIC12CE673
0x000 - 0x3FF (1K)
EEPROM
memory
in
the
PIC12CE673/674, it can be accessed only
by the user program.
PIC12C672/
PIC12CE674
0x000 - 0x7FF (2K)
When the PC reaches the last location of the imple-
mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
In programming mode the program memory space
extends from 0x0000 to 0x3FFF, with the first half
(0x0000-0x1FFF) being user program memory and the
second half (0x2000-0x3FFF) being configuration
memory. The PC will increment from 0x0000 to
0x1FFF and wrap to 0x000 or 0x2000 to 0x3FFF and
wrap around to 0x2000 (not to 0x0000). Once in con-
figuration memory, the highest bit of the PC stays a '1',
thus always pointing to the configuration memory. The
only way to point to user program memory is to reset
the part and reenter program/verify mode, as described
in Section 2.2.
The last location of the program memory space holds
the factory programmed oscillator calibration value.
This location should not be programmed except when
blank (a non-blank value should not cause the device
to fail a blank check). If blank, the programmer should
program it to a RETLW XX statement where "XX" is the
calibration value.
DS40175A-page 2
1998 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 2-1: PROGRAM MEMORY MAPPING
1KW
2KW
0
1FF
3FF
ID Location
ID Location
ID Location
ID Location
Reserved
2000
2001
2002
2003
2004
2005
2006
2007
Implemented
Implemented
400
7FF
800
Implemented
BFF
C00
FFF
1000
Reserved
Reserved
Reserved
Reserved
Configuration Word
1FFF
2000
2008
Reserved
Reserved
Reserved
Reserved
2100
3FFF
1998 Microchip Technology Inc.
DS40175A-page 3
PIC12C67X and PIC12CE67X
have a minimum setup and hold time (see AC/DC
specs) with respect to the falling edge of the clock.
Commands that have data associated with them (read
and load) are specified to have a minimum delay of 1µs
between the command and the data. After this delay
the clock pin is cycled 16 times with the first cycle being
a start bit and the last cycle being a stop bit. Data is
also input and output LSB first. Therefore, during a
read operation the LSB will be transmitted onto pin
GP0 on the rising edge of the second cycle, and during
a load operation the LSB will be latched on the falling
edge of the second cycle. A minimum 1µs delay is also
specified between consecutive commands.
2.2
Program/Verify Mode
The program/verify mode is entered by holding pins
GP1 and GP0 low while raising MCLR pin from VIL to
VIHH (high voltage). VDD is then raised from VIL to
VIH.Once in this mode the user program memory and
the configuration memory can be accessed and pro-
grammed in serial fashion. The mode of operation is
serial, and the memory that is accessed is the user pro-
gram memory. GP1 is a Schmitt Trigger input in this
mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at VIL). This means
that all I/O are in the reset state (High impedance
inputs).
All commands are transmitted LSB first. Data words
are also transmitted LSB first. The data is transmitted
on the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1µs is required between a command and a data word
(or another command).
Note 1: The MCLR pin must be raised from VIL to
VIHH before VDD is applied. This is to
ensure that the device does not have the
PC incremented while in valid operation
range.
The commands that are available are listed
in Table 1-1.
Note 2: Do not power GP2, GP4 or GP5 before
VDD is applied.
1.0.1.1
LOAD CONFIGURATION
1.0.1
PROGRAM/VERIFY OPERATION
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
The GP1 pin is used as a clock input pin, and the GP0
pin is used for entering command bits and data
input/output during serial operation. To input a com-
mand, the clock pin (GP1) is cycled six times. Each
command bit is latched on the falling edge of the clock
with the least significant bit (LSB) of the command
being input first. The data on pin GP0 is required to
operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user pro-
gram memory is to exit the program/verify test mode by taking MCLR low (VIL).
TABLE 1-1:
COMMAND MAPPING
Command
Mapping (MSB ... LSB)
Data
0, data(14), 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
Load Configuration
Load Data
0, data(14), 0
0, data(14), 0
Read Data
Increment Address
Begin programming
End Programming
DS40175A-page 4
1998 Microchip Technology Inc.
EPROM Memory Programming Specification
FIGURE 1-1: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X PROGRAM MEMORY
Start
Set V = V
PP
IHH1
•
Set V = V
DD
DDP
N = 0
No
Yes
Report Programming
Failure
N > 25
Program Cycle
Read Data
Command
N = N + 1
N = # of Program Cycles
No
Increment Address
Command
Data Correct?
Yes
Program Cycle
Apply 3N Additional
Program Cycles
Load Data
Command
No
All Locations Done?
Begin Programming
Command
Yes
Verify all Locations
@ V
DD MIN.•
Wait 100 µs
V
= V
PP
IHH2
No
Report Verify
DD MIN.
Data Correct?
@ V
Error
End Programming
Command
Yes
Verify all Locations
@ V
DD MAX.
V
= V
PP
IHH2
No
Report Verify
@ V Error
Data Correct?
Yes
DD MAX
Done
• VDDP = VDD range for programming (typically 4.75V - 5.25V).
V
DD MIN. = Minimum V
DD MAX. = Maximum V
for device operation.
for device operation.
DD
V
DD
1998 Microchip Technology Inc.
DS40175A-page 5
PIC12C67X and PIC12CE67X
FIGURE 1-2: PROGRAM FLOW CHART - PIC12C67X AND PIC12CE67X CONFIGURATION WORD
& ID LOCATIONS
Start
Set V = V
PP
IHH1
Load Configuration
Command
N = 0
No
Yes
Read Data
Command
Program ID Loc?
Program Cycle
N = N + 1
Increment Address
No
Command
Data Correct?
Yes
N = # of Program
Cycles
No
Address = 2004
Yes
No
N > 25
Yes
Increment Address
Command
ID/Configuration
Error
Apply 3N
Program Cycles
Increment Address
Command
Program Cycle
100 Cycles
Read Data
Command
Increment Address
Command
No
Data Correct?
Yes
Set V = V min
No
DD
DD
Report Program
ID/Config. Error
Data Correct?
Yes
Read Data Command
Set V = V
PP
IHH2
No
Yes
Set V = V max
DD
DD
Data Correct?
Done
Read Data Command
Set V = V
PP
IHH2
DS40175A-page 6
1998 Microchip Technology Inc.
EPROM Memory Programming Specification
1.0.1.2
LOAD DATA
1.1
Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 4-1.
The PIC12C67X and PIC12CE67X uses an intelligent
algorithm. The algorithm calls for program verification
at VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
VDDmax guarantees good “program margin”.
1.0.1.3
READ DATA
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input.The GP0
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped-
ance) after the 16th rising edge. A timing diagram of
this command is shown in Figure 4-2.
The actual programming must be done with VDD in the
VDDP range (4.75 - 5.25V).
VDDP
= VCC range required during programming.
VDD min. = minimum operating VDD spec for the part.
VDD max.= maximum operating VDD spec for the part.
Programmers must verify the PIC12C67X and
PIC12CE67X at its specified VDDmax and VDDmin lev-
els. Since Microchip may introduce future versions of
the PIC12C67X and PIC12CE67X with a broader VDD
range, it is best that these levels are user selectable
(defaults are ok).
1.0.1.4
INCREMENT ADDRESS
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 4-3.
Note:
Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.
1.0.1.5
BEGIN PROGRAMMING
A load command (load configuration or load data)
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.
1.0.1.6
END PROGRAMMING
After receiving this command, the chip stops program-
ming the memory (configuration program memory or
user program memory) that it was programming at the
time.
1998 Microchip Technology Inc.
DS40175A-page 7
PIC12C67X and PIC12CE67X
2.0
CONFIGURATION WORD
The PIC12C67X and PIC12CE67X family members
have several configuration bits. These bits can be pro-
grammed (reads '0') or left unprogrammed (reads '1') to
select various device configurations. Figure 2-1 pro-
vides an overview of configuration bits.
FIGURE 2-1: CONFIGURATION WORD
Bit Number:
13
11 10
9
8
12
7
6
5
4
2
3
1
0
Register: CONFIG
Address 2007h
CP0 PWRTE
FOSC1 FOSC0
WDTE FOSC2
CP1 CP0 CP1 CP0 CP1 CP0
MCLRE CP1
bit 13-8, 6-5: CP1:CP0: Code Protection bits (1) (2)
11 = Code protection off
10 = 0400h-07FFh code protected;
01 = 0200h-07FFh code protected;
00 = 0000h-07FFh code protected;
bit 7:
MCLRE: GP3/MCLR pin function select
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to Vdd
bit 4:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 3:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0:
FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin
110 = EXTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin
101 = INTRC oscillator / CLKOUT function on GP4/OSC2/CLKOUT pin
100 = INTRC oscillator / GP4 function on GP4/OSC2/CLKOUT pin
011 = invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 3: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
4: 07FFh is always uncodeprotected on the 12C672 and 03FFh is always uncodeprotected on the 12C671. This location
contains the RETLW xx calibration instruction for the INTRC.
DS40175A-page 8
1998 Microchip Technology Inc.
EPROM Memory Programming Specification
For PIC12C67X and PIC12CE67X devices, once code
protection is enabled, all protected segments read '0's
(or “garbage values”) and are prevented from further
programming. All unprotected segments, including ID
and configuration word locations , and calibration word
location read normally and can be programmed.
3.0
CODE PROTECTION
The program code written into the EPROM can be pro-
tected by writing to the CP0 & CP1 bits of the configu-
ration word.
3.1
Embedding Configuration Word and ID Information in the Hex File
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.
TABLE 3-1:
CONFIGURATION WORD
PIC12C671, PIC12CE673
To code protect:
• Protect all memory
• Protect 0200h-07FFh
• No code protection
00 0000 X00X XXXX
01 0101 X01X XXXX
11 1111 X11X XXXX
Program Memory Segment
R/W in Protected Mode
R/W in Unprotected Mode
Configuration Word (0x2007)
Unprotected memory segment
Protected memory segment
ID Locations (0x2000 : 0x2003)
INTRC Calibration Word (0X3FF)
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read All 0’s, Write Disabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
PIC12C672, PIC12CE674
To code protect:
• Protect all memory
• Protect 0200h-07FFh
• Protect 0400h-07FFh
• No code protection
00 0000 X00X XXXX
01 0101 X01X XXXX
10 1010 X10X XXXX
11 1111 X11X XXXX
Program Memory Segment
R/W in Protected Mode
R/W in Unprotected Mode
Configuration Word (0x2007)
Unprotected memory segment
Protected memory segment
ID Locations (0x2000 : 0x2003)
INTRC Calibration Word (0X7FF)
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read All 0’s, Write Disabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
Read Unscrambled, Write Enabled
1998 Microchip Technology Inc.
DS40175A-page 9
PIC12C67X and PIC12CE67X
The least significant 16 bits of this sum is the check-
sum.
3.2
Checksum
3.2.1
CHECKSUM CALCULATIONS
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
ently depending on the code protect setting, the table
describes how to manipulate the actual program mem-
ory values to simulate the values that would be read
from a protected device. When calculating a checksum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
Checksum is calculated by reading the contents of the
PIC12C67X and PIC12CE67X memory locations and
adding the opcodes up to the maximum user address-
able location, excluding the oscillator calibration loca-
tion in the last address, e.g., 0x3FE for the
PIC12C671/CE673. Any carry bits exceeding 16-bits
are neglected. Finally, the configuration word (appropri-
ately masked) is added to the checksum. Checksum
computation for each member of the PIC12C67X and
PIC12CE67X devices is shown in Table 3-2.
Note that some older devices have an additional value
added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
TABLE 3-2:
Device
CHECKSUM COMPUTATION
Ox25E6 at
Blank
Value
Code
Protect
Checksum*
SUM[0x000:0x3FE] + CFGW & 0x3FFF
SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID
CFGW & 0x3FFF + SUM_ID
0 and max
address
PIC12C671
PIC12CE673
OFF
1/2
3B3F
4E5E
3B4E
070D
0013
071C
ALL
PIC12C672
PIC12CE674
OFF
1/2
3/4
SUM[0x000:0x7FE] + CFGW & 0x3FFF
SUM[0x000:0x3FF] + CFGW & 0x3FFF + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3FFF + SUM_ID
CFGW & 0x3FFF + SUM_ID
373F
5D6E
4A5E
374E
030D
0F23
FC13
031C
ALL
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble.
For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
DS40175A-page 10
1998 Microchip Technology Inc.
EPROM Memory Programming Specification
4.0
PROGRAM/VERIFY MODE ELECTRICAL CHARACTERISTICS
TABLE 4-1:
AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (25°C is recommended)
Operating Voltage:
4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.
Parameter
Sym.
Characteristic
Min.
Typ. Max.
Units
Conditions
No.
General
PD1
VDDP Supply voltage during programming
4.75
5.0
5.25
20
V
PD2
IDDP Supply current (from VDD)
during programming
mA
PD3
PD4
VDDV Supply voltage during verify
VDDmin
12.75
VDDmax
13.25
V
V
Note 1
VIHH1 Voltage on MCLR/VPP during
programming
Note 2
PD5
PD6
VIHH2 Voltage on MCLR/VPP during verify
VDD + 4.0
13.5
50
IPP
Programming supply current (from
VPP)
mA
PD9
PD8
VIH1 (GP0, GP1) input high level
VIL1 (GP0, GP1) input low level
0.8 VDD
0.2 VDD
V
V
Schmitt Trigger input
Schmitt Trigger input
Serial Program Verify
P1
TR
MCLR/VPP rise time (VSS to VIHH)
for test mode entry
8.0
8.0
µs
P2
P3
P4
P5
Tf
MCLR Fall time
µs
ns
ns
µs
Tset1 Data in setup time before clock ↓
Thld1 Data in hold time after clock ↓
100
100
1.0
Tdly1 Data input not driven to next clock
input (delay required between com-
mand/data or command/command)
P6
P7
Tdly2 Delay between clock ↓ to clock ↑ of
1.0
µs
next command or data
Tdly3 Clock ↑ to data out valid
200
ns
(during read data)
P8
P9
Thld0 Hold time after VDD↑
TPPDP Hold time after VPP↑
2
5
µs
µs
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
Note 2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
1998 Microchip Technology Inc.
DS40175A-page 11
EPROM Memory Programming Specification
FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VDD
P9
VIHH
MCLR/VPP
100ns
2
P6
P8
1
3
4
5
6
1
2
3
4
5
15
1µs min.
GP1
(CLOCK)
100ns
0
GP0
(DATA)
0
0
0
0
1
0
0
P5
P3
P4
P4
1µs min.
P3
100ns
min.
100ns
min.
Program/Verify Mode
Reset
FIGURE 4-2: READ DATA COMMAND (PROGRAM/VERIFY)
VDD
P9
VIHH
MCLR/VPP
100ns
2
P6
P8
1
3
4
5
6
1
2
3
4
5
15
1µs min.
GP1
(CLOCK)
100ns
1
P7
GP0
(DATA)
0
0
0
0
0
P5
P4
1µs min.
P3
100ns
min.
RB7
input
RB7 = output
Program/Verify Mode
Reset
FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VDD
P9
VIHH
MCLR/VPP
P6
Next Command
2
1µs min.
1
1
2
3
4
5
6
GP1
(CLOCK)
GP0
(DATA)
0
0
0
0
1
0
0
1
P5
P3
P4
1µs min.
100ns
min
Program/Verify Mode
Reset
1998 Microchip Technology Inc.
DS40175A-page 12
EPROM Memory Programming Specification
NOTES:
1998 Microchip Technology Inc.
DS40175A-page 13
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United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222 Japan
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Tel: 630-285-0071 Fax: 630-285-0075
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Tel: 86-21-6275-5700
Fax: 86 21-6275-5060
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Singapore
Microchip Technology Taiwan
Singapore Branch
200 Middle Road
#07-02 Prime Centre
1/13/98
Tel: 714-263-1888 Fax: 714-263-1338
NewYork
Microchip Technology Inc.
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Organization (ISO).
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 2/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS40175A-page 14
1998 Microchip Technology Inc.
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