PIC12F1501T-OMSSQTP [MICROCHIP]
8-Pin Flash, 8-Bit Microcontrollers; 8引脚闪存8位微控制器
| 型号： | PIC12F1501T-OMSSQTP |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Pin Flash, 8-Bit Microcontrollers |
| 文件： | 总278页 (文件大小：3299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12(L)F1501
Data Sheet
8-Pin Flash, 8-Bit Microcontrollers
*8-bit, 8-pin devices protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2011 Microchip Technology Inc.
Preliminary
DS41615A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-765-2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41615A-page 2
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
8-Pin Flash, 8-Bit Microcontrollers
High-Performance RISC CPU:
Low-Power Features (PIC12LF1501):
• C Compiler Optimized Architecture
• Only 49 Instructions
• 1K Words Linear Program Memory Addressing
• 64 bytes Linear Data Memory Addressing
• Operating Speed:
• Standby Current:
- 20 nA @ 1.8V, typical
• Watchdog Timer Current:
- 200 nA @ 1.8V, typical
• Operating Current:
- DC – 20 MHz clock input
- 30 A/MHz @ 1.8V, typical
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
Peripheral Features:
•
Analog-to-Digital Converter (ADC):
- 10-bit resolution
- 4 external channels
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
- 2 internal channels:
- Fixed Voltage Reference and DAC channels
- Temperature Indicator channel
- Auto acquisition capability
- Conversion available during Sleep
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Factory calibrated to ±1%, typical
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• Three External Clock modes up to 20 MHz
• 1 Comparator:
- Rail-to-rail inputs
- Power mode control
- Software controllable hysteresis
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
- 1 rail-to-rail resistive 5-bit DAC with positive
reference selection
• 6 I/O Pins (1 Input-only Pin):
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable interrupt-on-change
(IOC) pins
Special Microcontroller Features:
• Operating Voltage Range:
- 1.8V to 3.6V (PIC12LF1501)
- 2.3V to 5.5V (PIC12F1501)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-Out Reset
(LPBOR)
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Extended Watchdog Timer (WDT):
- Programmable period from 1 ms to 256s
• Programmable Code Protection
• In-Circuit Serial Programming™ (ICSP™) via Two
Pins
• Enhanced Low-Voltage Programming (LVP)
• Power-Saving Sleep mode:
- Low-Power Sleep mode
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Four 10-bit PWM modules
• 2 Configurable Logic Cell (CLC) modules:
- 16 selectable input source signals
- Four inputs per module
- Low-Power BOR (LPBOR)
• Integrated Temperature Indicator
• 128 Bytes High-Endurance Flash:
- 100,000 write Flash endurance (minimum)
- Software control of combinational/sequential
logic/state/clock functions
- AND/OR/XOR/D Flop/D Latch/SR/JK
- External or internal inputs/outputs
- Operation while in Sleep
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 3
PIC12(L)F1501
Peripheral Features (Continued):
• Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
- 16-bit increment
- True linear frequency control
- High-speed clock input
- Selectable Output modes:
- Fixed Duty Cycle (FDC) mode
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- 8 selectable signal sources
- Selectable falling and rising edge dead-band
control
- Polarity control
- 4 auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO
PIC12(L)F1501/PIC16(L)F150X Family Types
Device
PIC12(L)F1501 (1) 1024 64
6
4
8
1
2
1
1
2/1
2/1
2/1
2/1
2/1
4
4
4
4
4
—
—
—
1
—
1
1
1
1
1
1
2
2
2
4
4
1
1
1
1
1
H
H
—
—
—
Y
PIC16(L)F1503 (2) 2048 128 12
PIC16(L)F1507 (3) 2048 128 18 12
PIC16(L)F1508 (4) 4096 256 18 12
PIC16(L)F1509 (4) 8192 512 18 12
—
2
—
1
—
1
H
I/H
I/H
2
1
1
1
Y
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Requires Debug Header.
2: One pin is input-only.
Data Sheet Index: (Unshaded devices are described in this document.)
1: Future Product
2: DS41607
3: DS41586
4: DS41609
PIC12(L)F1501 Data Sheet, 8-Pin Flash, 8-bit Microcontrollers.
PIC16(L)F1503 Data Sheet, 14-Pin Flash, 8-bit Microcontrollers.
PIC16(L)F1507 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
PIC16(L)F1508/1509 Data Sheet, 20-Pin Flash, 8-bit Microcontrollers.
DS41615A-page 4
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 1:
8-PIN PDIP, SOIC, MSOP, DFN DIAGRAM FOR PIC12(L)F1501
PDIP, SOIC, MSOP, DFN
VDD
RA5
1
2
VSS
8
7
6
5
RA0/ICSPDAT
RA4
RA1/ICSPCLK
RA2
3
4
MCLR/VPP/RA3
Note: See Table 1 for location of all peripheral functions.
TABLE 1:
8-PIN ALLOCATION TABLE (PIC12(L)F1501)
(1)
RA0
RA1
RA2
7
6
5
AN0
AN1
AN2
DACOUT1
VREF+
C1IN+
C1IN0-
C1OUT
—
—
CWG1B
—
—
CLC2IN1 PWM2 IOC
Y
Y
Y
ICSPDAT
ICSPCLK
—
(1)
NCO1
—
CLC2IN0
—
IOC
(1)
(1)
DACOUT2
T0CKI CWG1A
CLC1
PWM1 INT
IOC
CWG1FLT
(2)
(1)
RA3
4
—
—
—
T1G
T1G
—
—
CLC1IN0
—
IOC
Y
MCLR
VPP
(2)
(2)
RA4
RA5
3
2
AN3
—
—
—
C1IN1-
—
CWG1B
CLC1
PWM3 IOC
Y
Y
CLKOUT
CLKIN
(2)
(2)
T1CKI CWG1A
NCO1
NCO1CLK
CLC1IN1 PWM4 IOC
CLC2
VDD
VSS
1
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
VSS
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 5
PIC12(L)F1501
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 39
5.0 Oscillator Module........................................................................................................................................................................ 45
6.0 Resets ........................................................................................................................................................................................ 53
7.0 Interrupts .................................................................................................................................................................................... 61
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 75
9.0 Watchdog Timer......................................................................................................................................................................... 79
10.0 Flash Program Memory Control ................................................................................................................................................. 83
11.0 I/O Ports ..................................................................................................................................................................................... 99
12.0 Interrupt-On-Change ................................................................................................................................................................ 105
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 109
14.0 Temperature Indicator Module ................................................................................................................................................. 111
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 113
16.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 127
17.0 Comparator Module.................................................................................................................................................................. 131
18.0 Timer0 Module ......................................................................................................................................................................... 141
19.0 Timer1 Module with Gate Control............................................................................................................................................. 145
20.0 Timer2 Module ......................................................................................................................................................................... 157
21.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................. 161
22.0 Configurable Logic Cell (CLC).................................................................................................................................................. 167
23.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 183
24.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 193
25.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 209
26.0 Instruction Set Summary.......................................................................................................................................................... 211
27.0 Electrical Specifications............................................................................................................................................................ 225
28.0 DC and AC Characteristics Graphs and Charts....................................................................................................................... 247
29.0 Development Support............................................................................................................................................................... 249
30.0 Packaging Information.............................................................................................................................................................. 253
Appendix A: Data Sheet Revision History.......................................................................................................................................... 267
Index .................................................................................................................................................................................................. 269
The Microchip Web Site..................................................................................................................................................................... 275
Customer Change Notification Service .............................................................................................................................................. 275
Customer Support.............................................................................................................................................................................. 275
Reader Response .............................................................................................................................................................................. 276
Product Identification System............................................................................................................................................................. 277
DS41615A-page 6
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We
welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2011 Microchip Technology Inc.
Preliminary
DS41615A-page 7
PIC12(L)F1501
NOTES:
DS41615A-page 8
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
1.0
DEVICE OVERVIEW
The PIC12(L)F1501 are described within this data sheet.
They are available in 14-pin packages. Figure 1-1 shows
a block diagram of the PIC12(L)F1501 devices. Table 1-2
shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
Analog-to-Digital Converter (ADC)
●
●
●
●
●
●
●
●
●
●
●
●
Complementary Wave Generator (CWG)
Digital-to-Analog Converter (DAC)
Fixed Voltage Reference (FVR)
Numerically Controlled Oscillator (NCO)
Temperature Indicator
Comparators
C1
●
●
Configurable Logic Cell (CLC)
CLC1
●
●
●
●
CLC2
PWM Modules
PWM1
●
●
●
●
●
●
●
●
PWM2
PWM3
PWM4
Timers
Timer0
●
●
●
●
●
●
Timer1
Timer2
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 9
PIC12(L)F1501
FIGURE 1-1:
PIC12(L)F1501 BLOCK DIAGRAM
Program
Flash Memory
RAM
Timing
Generation
CLKOUT
PORTA
CPU
CLKIN
INTRC
Oscillator
(Figure 2-1)
MCLR
NCO1
Timer0
Timer1
Timer2
CLC1
CLC2
C1
CWG1
Temp.
Indicator
ADC
10-Bit
FVR
PWM4
DAC
PWM1
PWM2
PWM3
Note 1:
2:
See applicable chapters for more information on peripherals.
See Table 1-1 for peripherals available on specific devices.
DS41615A-page 10
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 1-2:
PIC12(L)F1501 PINOUT DESCRIPTION
Input Output
Function
Name
Description
Type
Type
RA0/AN0/C1IN+/DACOUT1/
CWG1B /CLC2IN1/PWM2/
ICSPDAT
RA0
AN0
TTL
AN
AN
—
CMOS General purpose I/O.
(1)
—
—
A/D Channel input.
C1IN+
DACOUT1
CWG1B
CLC2IN1
PWM2
ICSPDAT
RA1
Comparator positive input.
AN
Digital-to-Analog Converter output.
—
CMOS CWG complementary output.
Configurable Logic Cell source input.
ST
—
—
CMOS Pulse Width Module source output.
CMOS ICSP™ Data I/O.
ST
TTL
AN
AN
AN
—
RA1/AN1/VREF+/C1IN0-/
CMOS General purpose I/O.
(1)
NCO1 /CLC2IN0/ICSPCLK
AN1
—
—
—
A/D Channel input.
VREF+
C1IN0-
NCO1
CLC2IN0
ICSPCLK
RA2
A/D Positive Voltage Reference input.
Comparator negative input.
CMOS Numerically Controlled Oscillator output.
ST
ST
ST
AN
—
—
—
Configurable Logic Cell source input.
ICSP™ Programming Clock.
RA2/AN2/C1OUT/DACOUT2/
CMOS General purpose I/O.
A/D Channel input.
CMOS Comparator output.
(1)
T0CKI/INT/PWM1/CLC1
CWG1A /CWG1FLT
/
AN2
—
(1)
C1OUT
DACOUT2
T0CKI
INT
—
AN
—
Digital-to-Analog Converter output.
ST
ST
—
Timer0 clock input.
External interrupt.
—
PWM1
CLC1
CMOS Pulse Width Module source output.
CMOS Configurable Logic Cell source output.
CMOS CWG complementary output.
—
CWG1A
CWG1FLT
RA3
—
ST
TTL
ST
HV
ST
ST
TTL
AN
AN
—
—
—
—
—
—
—
Complementary Waveform Generator Fault input.
General purpose input.
(2)
RA3/CLC1IN0/VPP/T1G /MCLR
CLC1IN0
VPP
Configurable Logic Cell source input.
Programming voltage.
T1G
Timer1 Gate input.
MCLR
RA4
Master Clear with internal pull-up.
(2)
RA4/AN3/C1IN1-/CWG1B
/
CMOS General purpose I/O.
(2)
(1)
CLC1 /PWM3/CLKOUT/T1G
AN3
—
—
A/D Channel input.
C1IN1-
CWG1B
CLC1
Comparator negative input.
CMOS CWG complementary output.
CMOS Configurable Logic Cell source output.
CMOS Pulse Width Module source output.
CMOS FOSC/4 output.
—
PWM3
CLKOUT
T1G
—
—
ST
—
Timer1 Gate input.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 11
PIC12(L)F1501
TABLE 1-2:
PIC12(L)F1501 PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(2)
RA5/CLKIN/T1CKI/CWG1A
/
RA5
CLKIN
T1CKI
CWG1A
NCO1
NCO1CLK
CLC1IN1
CLC2
TTL
CMOS
ST
CMOS General purpose I/O.
(2)
NCO1 /NCO1CLK/CLC1IN1/
CLC2/PWM4
—
—
External clock input (EC mode).
Timer1 clock input.
—
CMOS CWG complementary output.
ST
—
—
—
Numerically Controlled Oscillator output.
Numerically Controlled Oscillator Clock source input.
Configurable Logic Cell source input.
ST
ST
—
CMOS Configurable Logic Cell source output.
CMOS Pulse Width Module source output.
PWM4
VDD
—
VDD
VSS
Power
Power
—
—
Positive supply.
VSS
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Default location for peripheral pin function. Alternate location can be selected using the APFCON register.
2: Alternate location for peripheral pin function selected by the APFCON register.
DS41615A-page 12
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register and, if enabled, will cause a soft-
ware Reset. See section Section 3.4 “Stack” for more
details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is one additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 26.0 “Instruction Set Summary” for more
details.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 13
PIC12(L)F1501
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
8
15
Data Bus
RAM
Program Counter
Flash
Program
Memory
16-LevelStack
(15-bit)
Program
Bus
14
RAM Addr
Program Memory
Read (PMR)
12
Addr MUX
InstructionReg
Indirect
Addr
7
Direct Addr
12
12
5
BSR Reg
15
FSR0 Reg
FSR1 Reg
15
STATUSReg
8
3
MUX
Power-up
Timer
Instruction
Decodeand
Control
ALU
Power-on
Reset
CLKIN
8
Watchdog
Timer
Timing
Generation
W Reg
CLKOUT
Brown-out
Reset
Internal
Oscillator
Block
VDD
VSS
DS41615A-page 14
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
The following features are associated with access and
control of program memory and data memory:
3.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• PCL and PCLATH
• Stack
• Program Memory
- Configuration Words
- Device ID
• Indirect Addressing
- User ID
3.1
Program Memory Organization
- Flash Program Memory
• Data Memory
The enhanced mid-range core has a 15-bit program
counter capable of addressing 32K x 14 program
memory space. Table 3-1 shows the memory sizes
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
implemented. Accessing
a location above these
boundaries will cause a wrap-around within the
implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 3-1).
TABLE 3-1:
Device
DEVICE SIZES AND ADDRESSES
Program Memory Size
(Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range(1)
PIC12F1501
PIC12LF1501
1,024
03FFh
0380h-03FFh
Note 1: High-Endurance Flash applies to the low byte of each address in the range.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 15
PIC12(L)F1501
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC12(L)F1501
3.1.1
READING PROGRAM MEMORY AS
DATA
There are two methods of accessing constants in pro-
gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
3.1.1.1
RETLWInstruction
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
EXAMPLE 3-1:
constants
BRW
RETLW INSTRUCTION
0000h
;Add Index in W to
;program counter to
;select data
Interrupt Vector
Page 0
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;Index0 data
;Index1 data
0004h
0005h
On-chip
Program
Memory
03FFh
0400h
Rollover to Page 0
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRWinstruction makes this type of table very sim-
ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRWinstruction is not available so the older table read
method must be used.
Rollover to Page 0
7FFFh
DS41615A-page 16
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
3.1.1.2
Indirect Read with FSR
3.2.1
CORE REGISTERS
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIWinstruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-4.
TABLE 3-2:
CORE REGISTERS
The HIGH directive will set bit<7> if a label points to a
location in program memory.
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
my_function
;Index0 data
;Index1 data
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW
LOW constants
FSR1L
HIGH constants
FSR1H
0[FSR1]
WREG
PCLATH
INTCON
x0Ah or x8Ah
x0Bh or x8Bh
;THE PROGRAM MEMORY IS IN W
3.2
Data Memory Organization
The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 3-2):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Data memory uses a 12-bit address. The upper 7 bits
of the address define the Bank address and the lower
5 bits select the registers/RAM in that bank.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 17
PIC12(L)F1501
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 26.0
“Instruction Set Summary”).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-0/u
Z
R/W-0/u
DC(1)
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-Out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-Down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41615A-page 18
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
3.2.2
SPECIAL FUNCTION REGISTER
FIGURE 3-2:
BANKED MEMORY
PARTITIONING
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the appro-
priate peripheral chapter of this data sheet.
Memory Region
7-bit Bank Offset
00h
Core Registers
(12 bytes)
0Bh
0Ch
3.2.3
GENERAL PURPOSE RAM
Special Function Registers
(20 bytes maximum)
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
1Fh
20h
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
General Purpose RAM
(80 bytes maximum)
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5
DEVICE MEMORY MAPS
The memory maps for PIC12(L)F1501 are as shown in
Table 3-3.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 19
PIC12(L)F1501
DS41615A-page 20
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 21
PIC12(L)F1501
DS41615A-page 22
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 3-3:
PIC12(L)F1501 MEMORY MAP (CONTINUED)
Bank 30
Bank 31
—
F0Ch
F8Ch
—
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
—
Unimplemented
Read as ‘0’
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
Unimplemented
Read as ‘0’
F6Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 23
PIC12(L)F1501
3.2.6
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-4 can be
addressed from any Bank.
TABLE 3-4:
CORE FUNCTION REGISTERS SUMMARY
Value on
POR, BOR other Resets
Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0-31
x00h or
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
INDF0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
x01h or
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
INDF1
PCL
x02h or
x82h
Program Counter (PC) Least Significant Byte
x03h or
x83h
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x04h or
x84h
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x05h or
x85h
x06h or
x86h
x07h or
x87h
x08h or
x88h
—
—
—
BSR<4:0>
x09h or
x89h
WREG
PCLATH
INTCON
Working Register
x0Ahor
x8Ah
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x0Bhor
x8Bh
GIE
INTF
IOCIF
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
DS41615A-page 24
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00Ch
00Dh
00Eh
00Fh
010h
011h
PORTA
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--xx xxxx --xx xxxx
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TMR1GIF
—
—
—
—
—
—
—
—
—
—
—
PIR1
PIR2
PIR3
—
ADIF
—
—
C1IF
—
—
—
—
—
—
—
—
NCO1IF
—
TMR2IF
—
TMR1IF
—
00-- --00 00-- --00
--0- -0-- --0- -0--
---- --00 ---- --00
012h
013h
014h
015h
016h
017h
018h
019h
—
—
—
CLC2IF
CLC1IF
Unimplemented
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
Holding Register for the 8-bit Timer0 Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 -0-0 uuuu -u-u
0000 0x00 uuuu uxuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
TMR1CS<1:0>
TMR1GE T1GPOL
T1CKPS<1:0>
T1GTM T1GSPM
—
T1SYNC
T1GVAL
—
TMR1ON
T1GGO/
DONE
T1GSS<1:0>
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
Bank 1
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
TMR2
PR2
T2CON
—
Timer2 Module Register
Timer2 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
T2OUTPS<3:0>
TMR2ON
TRISA2
T2CKPS<1:0>
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
(2)
TRISA
—
—
—
TRISA5
TRISA4
—
TRISA1
TRISA0
--11 1111 --11 1111
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TMR1GIE
—
—
—
—
—
—
—
—
—
—
—
PIE1
ADIE
—
—
C1IE
—
—
—
—
—
—
—
—
NCO1IE
—
TMR2IE
—
TMR1IE
—
00-- --00 00-- --00
--0- -0-- -00- -0--
---- --00 ---- --00
PIE2
—
PIE3
—
—
CLC2IE
CLC1IE
—
Unimplemented
—
—
OPTION_REG
PCON
WDTCON
—
WPUEN
STKOVF
—
INTEDG
STKUNF
—
TMR0CS
—
TMR0SE
RWDT
PSA
PS<2:0>
POR
1111 1111 1111 1111
00-1 11qq qq-q qquu
--01 0110 --01 0110
RMCLR
RI
BOR
WDTPS<4:0>
SWDTEN
Unimplemented
—
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
ADCON2
—
—
IRCF<3:0>
—
—
SCS<1:0>
-011 1-00 -011 1-00
---0 --00 ---q --qq
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
-000 0000 -000 0000
0000 --00 0000 --00
0000 ---- 0000 ----
—
—
HFIOFR
—
LFIOFR
HFIOFS
A/D Result Register Low
A/D Result Register High
—
CHS<4:0>
GO/DONE
ADON
—
ADFM
ADCS<2:0>
—
—
—
—
ADPREF<1:0>
TRIGSEL<3:0>
—
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 25
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
10Ch
10Dh
10Eh
10Fh
110h
111h
LATA
—
—
LATA5
LATA4
—
LATA2
LATA1
LATA0
--xx -xxx --uu -uuu
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
C1ON
—
—
—
—
—
—
—
—
—
—
—
CM1CON0
CM1CON1
—
C1OUT
C1INTN
C1OE
C1POL
—
—
C1SP
C1HYS
C1SYNC
0000 -100 0000 -100
0000 -000 0000 -000
112h
113h
114h
115h
116h
117h
118h
119h
C1INTP
C1PCH<1:0>
C1NCH<2:0>
Unimplemented
Unimplemented
—
—
—
—
—
—
CMOUT
BORCON
FVRCON
DACCON0
DACCON1
—
—
—
—
—
—
—
—
—
—
—
MC1OUT
BORRDY
---- ---0 ---- ---0
10-- ---q uu-- ---u
0q00 0000 0q00 0000
0-00 -0-- 0-00 -0--
---0 0000 ---0 0000
SBOREN
BORFS
FVREN
DACEN
—
FVRRDY
—
TSEN
DACOE1
—
TSRNG
DACOE2
CDAFVR<1:0>
ADFVR<1:0>
—
DACPSS
—
—
DACR<4:0>
11Ah
to
—
Unimplemented
—
—
11Ch
11Dh
11Eh
11Fh
Bank 3
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
APFCON
CWG1BSEL CWG1ASEL
Unimplemented
—
—
—
T1GSEL
—
CLC1SEL
ANSA1
NCO1SEL
ANSA0
00-- 0-00 00-- 0-00
—
—
—
—
—
—
Unimplemented
ANSELA
—
—
—
ANSA4
—
ANSA2
---1 -111 ---1 -111
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON(1)
Flash Program Memory Address Register Low Byte
Flash Program Memory Address Register High Byte
Flash Program Memory Read Data Register Low Byte
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
0000 x000 0000 q000
0000 0000 0000 0000
---- --01 ---- --01
—
—
—
Flash Program Memory Read Data Register High Byte
(2)
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
Flash Program Memory Control Register 2
—
—
—
—
—
—
VREGPM
Reserved
198h
to
—
Unimplemented
—
—
19Fh
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
DS41615A-page 26
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
20Ch
WPUA
—
—
—
WPUA5
WPUA4
WPUA3
WPUA2
WPUA1
WPUA0
--11 1111 --11 1111
20Dh
to
21Fh
Unimplemented
—
—
—
—
—
—
—
—
Bank 5
28Ch
to
29Fh
—
—
—
Unimplemented
Unimplemented
Unimplemented
Bank 6
30Ch
to
31Fh
Bank 7
38Ch
to
390h
391h
392h
393h
IOCAP
IOCAN
IOCAF
—
—
—
—
—
—
IOCAP5
IOCAN5
IOCAF5
IOCAP4
IOCAN4
IOCAF4
IOCAP3
IOCAN3
IOCAF3
IOCAP2
IOCAN2
IOCAF2
IOCAP1
IOCAN1
IOCAF1
IOCAP0
IOCAN0
IOCAF0
--00 0000 --00 0000
--00 0000 --00 0000
--00 0000 --00 0000
394h
to
39Fh
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
Bank 8
40Ch
to
41Fh
Bank 9
48Ch
to
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
NCO1ACCL
NCO1ACCH
NCO1ACCU
NCO1INCL
NCO1INCH
—
NCO1ACC<7:0>
NCO1ACC<15:8>
NCO1ACC<19:16>
NCO1INC<7:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
NCO1INC<15:8>
Unimplemented
N1EN
—
—
NCO1CON
NCO1CLK
N1OE
N1OUT
N1POL
—
—
—
—
—
—
N1PFM
0000 ---0 0000 ---0
0000 --00 0000 --00
N1PWS<2:0>
N1CKS<1:0>
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 27
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 10
50Ch
to
51Fh
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
Bank 11
58Ch
to
59Fh
—
Bank 12
60Ch
to
—
610h
611h
PWM1DCL
PWM1DCH
PWM1CON0
PWM2DCL
PWM2DCH
PWM2CON0
PWM3DCL
PWM3DCH
PWM3CON0
PWM4DCL
PWM4DCH
PWM4CON0
PWM1DCL<7:6>
—
—
—
—
—
—
00-- ---- 00-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
00-- ---- 00-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
00-- ---- 00-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
00-- ---- 00-- ----
xxxx xxxx uuuu uuuu
0000 ---- 0000 ----
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
PWM1DCH<7:0>
PWM1EN
PWM1OE PWM1OUT PWM1POL
—
—
—
—
—
—
—
—
PWM2DCL<7:6>
—
—
PWM2DCH<7:0>
PWM2EN
PWM2OE PWM2OUT PWM2POL
—
—
—
—
—
—
—
—
PWM3DCL<7:6>
—
—
PWM3DCH<7:0>
PWM3EN
PWM3OE PWM3OUT PWM3POL
—
—
—
—
—
—
—
—
PWM4DCL<7:6>
—
—
PWM4DCH<7:0>
PWM4OE PWM4OUT PWM4POL
PWM4EN
—
—
—
—
61Dh
to
—
Unimplemented
—
—
61Fh
Bank 13
68Ch
to
—
Unimplemented
—
—
690h
691h
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1CON2
—
—
—
—
CWG1DBR<5:0>
CWG1DBF<5:0>
--00 0000 --00 0000
--xx xxxx --xx xxxx
0000 0--0 0000 0--0
0000 -000 0000 -000
692h
693h
694h
695h
G1EN
G1OEB
G1OEA
G1POLB
—
G1POLA
—
—
G1CS0
G1ASDLB<1:0>
G1ASDLA<1:0>
—
—
G1IS<2:0>
G1ASE
G1ARSEN
G1ASDC1 G1ASDFLT G1ASDCLC2 00-- -000 00-- -000
—
696h
to
—
Unimplemented
—
—
69Fh
Bank 14-29
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
DS41615A-page 28
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Banks 14-29
x0Ch/
x8Ch
—
x1Fh/
x9Fh
—
Unimplemented
—
—
—
Bank 30
F0Ch
to
—
Unimplemented
—
F0Eh
F0Fh
CLCDATA
CLC1CON
CLC1POL
CLC1SEL0
CLC1SEL1
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC2CON
CLC2POL
CLC2SEL0
CLC2SEL1
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
—
LC1EN
LC1POL
—
—
LC1OE
—
—
—
LC1INTP
—
—
—
MLC1OUT
MLC2OUT ---- --00 ---- --00
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
LC1OUT
—
LC1INTN
LC1MODE<2:0>
0000 0000 0000 0000
LC1G4POL LC1G3POL LC1G2POL LC1G1POL 0--- xxxx 0--- uuuu
LC1D2S<2:0>
LC1D4S<2:0>
—
—
LC1D1S<2:0>
LC1D3S<2:0>
-xxx -xxx -uuu -uuu
-xxx -xxx -uuu -uuu
—
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T
LC1G1D1N xxxx xxxx uuuu uuuu
LC1G2D1N xxxx xxxx uuuu uuuu
LC1G3D1N xxxx xxxx uuuu uuuu
LC1G4D1N xxxx xxxx uuuu uuuu
LC2MODE<2:0> 0000 0000 0000 0000
LC2EN
LC2POL
—
LC2OE
—
LC2OUT
—
LC2INTP
—
LC2INTN
LC2G4POL LC2G3POL LC2G2POL LC2G1POL 0--- xxxx 0--- uuuu
LC2D2S<2:0>
LC2D4S<2:0>
—
—
LC2D1S<2:0>
LC2D3S<2:0>
-xxx -xxx -uuu -uuu
-xxx -xxx -uuu -uuu
—
LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T
LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T
LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T
LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T
LC2G1D1N xxxx xxxx uuuu uuuu
LC2G2D1N xxxx xxxx uuuu uuuu
LC2G3D1N xxxx xxxx uuuu uuuu
LC2G4D1N xxxx xxxx uuuu uuuu
F20h
to
—
Unimplemented
—
—
F6Fh
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 29
PIC12(L)F1501
TABLE 3-5:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F8Ch
—
FE3h
—
Unimplemented
—
—
—
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
STATUS_
SHAD
—
—
—
—
—
Z_SHAD
DC_SHAD
C_SHAD
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
WREG_
SHAD
Working Register Shadow
BSR_
SHAD
—
—
—
Bank Select Register Shadow
PCLATH_
SHAD
Program Counter Latch High Register Shadow
FSR0L_
SHAD
Indirect Data Memory Address 0 Low Pointer Shadow
Indirect Data Memory Address 0 High Pointer Shadow
Indirect Data Memory Address 1 Low Pointer Shadow
Indirect Data Memory Address 1 High Pointer Shadow
Unimplemented
FSR0H_
SHAD
FSR1L_
SHAD
FSR1H_
SHAD
—
FECh
FEDh
FEEh
FEFh
—
—
—
—
—
Current Stack Pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
Top-of-Stack Low byte
Top-of-Stack High byte
—
TOSH
Legend:
Note 1:
2:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, r= reserved. Shaded locations are unimplemented, read as ‘0’.
PIC12F1501 only.
Unimplemented, read as ‘1’.
DS41615A-page 30
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
3.3.2
COMPUTED GOTO
3.3
PCL and PCLATH
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application
Note AN556, “Implementing a Table Read” (DS00556).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-3 shows the five
situations for the loading of the PC.
3.3.3
COMPUTED FUNCTION CALLS
FIGURE 3-3:
LOADING OF PC IN
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
DIFFERENT SITUATIONS
Instruction with
14
0
PCH
7
PCL
PCL as
PC
Destination
8
6
0
PCLATH
ALU Result
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
14
0
PCH
PCL
GOTO, CALL
PC
The CALLWinstruction enables computed calls by com-
bining PCLATH and W to form the destination address.
A computed CALLWis accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
11
4
6
0
PCLATH
OPCODE <10:0>
14
0
0
0
PCH
7
PCL
CALLW
PC
8
6
0
3.3.4
BRANCHING
PCLATH
W
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
14
PCH
PCL
PC
BRW
BRA
15
PC + W
14
PCH
PCL
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
PC
15
PC + OPCODE <8:0>
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRAinstruction.
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun-
ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con-
tained in the PCLATH register and those being written
to the PCL register.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 31
PIC12(L)F1501
3.4.1
ACCESSING THE STACK
3.4
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-4 through 3-7). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLWor a RETFIEinstruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Words). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over-
flow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLWand
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIEwill decrement STKPTR. At any
time, STKPTR can be inspected to see how much
stack is left. The STKPTR always points at the currently
used place on the stack. Therefore, a CALLor CALLW
will increment the STKPTR and then write the PC, and
a return will unload the PC and then decrement the
STKPTR.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
Reference Figure 3-4 through Figure 3-7 for examples
of accessing the stack.
FIGURE 3-4:
ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled
STKPTR = 0x1F
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
(STVREN = 0)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
DS41615A-page 32
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
This figure shows the stack configuration
after the first CALLor a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
0x00
Return Address
STKPTR = 0x00
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURNinstructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 33
PIC12(L)F1501
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 4
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALLor
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
TOSH:TOSL
STKPTR = 0x10
3.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Words is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
DS41615A-page 34
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 3-8:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
0x1FFF
0x2000
Reserved
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
FSR
Address
Range
0x7FFF
0x8000
Program
Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 35
PIC12(L)F1501
3.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-9:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
00000 00001 00010
11111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
DS41615A-page 36
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
3.5.2
LINEAR DATA MEMORY
3.5.3
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-11:
PROGRAM FLASH
MEMORY MAP
FIGURE 3-10:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 37
PIC12(L)F1501
NOTES:
DS41615A-page 38
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
4.0
DEVICE CONFIGURATION
Device Configuration consists of Configuration Words,
Code Protection and Device ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 39
PIC12(L)F1501
REGISTER 4-1:
CONFIG1: CONFIGURATION WORD 1
U-1
—
U-1
—
R/P-1
R/P-1
R/P-1
R/P-1
U-1
—
CLKOUTEN
BOREN<1:0>
bit 13
bit 8
R/P-1
CP
R/P-1
R/P-1
R/P-1
R/P-1
U-1
—
R/P-1
FOSC<1:0>
MCLRE
PWRTE
WDTE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
-n = Value when blank or after Bulk Erase
‘0’ = Bit is cleared
bit 13-12
bit 11
Unimplemented: Read as ‘1’
CLKOUTEN: Clock Out Enable bit
1= CLKOUT function is disabled. I/O function on the CLKOUT pin
0= CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits(1)
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
01= BOR controlled by SBOREN bit of the BORCON register
00= BOR disabled
bit 8
bit 7
Unimplemented: Read as ‘1’
CP: Code Protection bit(2)
1= Program memory code protection is disabled
0= Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1=MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0=MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-Up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bits
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
bit 2
Unimplemented: Read as ‘1’
bit 1-0
FOSC<1:0>: Oscillator Selection bits
11= ECH: External Clock, High-Power mode: on CLKIN pin
10= ECM: External Clock, Medium-Power mode: on CLKIN pin
01= ECL: External Clock, Low-Power mode: on CLKIN pin
00= INTOSC oscillator: I/O function on CLKIN pin
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: Once enabled, code-protect can only be disabled by bulk erasing the device.
DS41615A-page 40
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 4-2:
CONFIG2: CONFIGURATION WORD 2
R/P-1
LVP
U-1
—
R/P-1
R/P-1
R/P-1
U-1
—
LPBOR
BORV
STVREN
bit 13
bit 8
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
U-1
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
-n = Value when blank or after Bulk Erase
bit 13
LVP: Low-Voltage Programming Enable bit(1)
1= Low-voltage programming enabled
0= High-voltage on MCLR must be used for programming
bit 12
bit 11
Unimplemented: Read as ‘1’
LPBOR: Low-Power BOR Enable bit
1= Low-Power Brown-out Reset is disabled
0= Low-Power Brown-out Reset is enabled
bit 10
bit 9
BORV: Brown-out Reset Voltage Selection bit(2)
1= Brown-out Reset voltage (Vbor), low trip point selected
0= Brown-out Reset voltage (Vbor), high trip point selected
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Stack Overflow or Underflow will cause a Reset
0= Stack Overflow or Underflow will not cause a Reset
bit 8-2
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
1 kW Flash memory:
11= Write protection off
10= 000h to 0FFh write-protected, 100h to 3FFh may be modified
01= 000h to 1FFh write-protected, 200h to 3FFh may be modified
00= 000h to 3FFh write-protected, no addresses may be modified
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
2: See Vbor parameter for specific trip point voltages.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 41
PIC12(L)F1501
4.2
Code Protection
Code protection allows the device to be protected from
unauthorized access. Internal access to the program
memory is unaffected by any code protection setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.3
“Write
Protection” for more information.
4.3
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC12(L)F1501/PIC16(L)F150X
Memory Programming Specification” (DS41573).
DS41615A-page 42
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2011 Microchip Technology Inc.
PIC12(L)F1501
4.5
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 10.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
REGISTER 4-3:
DEVICEID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
R
R
DEV<8:3>
bit 13
bit 8
bit 0
R
R
R
R
DEV<2:0>
REV<4:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘1’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
bit 13-5
DEV<8:0>: Device ID bits
DEVICEID<13:0> Values
Device
DEV<8:0>
REV<4:0>
PIC12F1501
PIC12LF1501
10 1100 110
10 1101 100
x xxxx
x xxxx
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 43
PIC12(L)F1501
NOTES:
DS41615A-page 44
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
The oscillator module can be configured in one of the
following clock modes.
5.0
5.1
OSCILLATOR MODULE
Overview
1. ECL – External Clock Low-Power mode
(0 MHz to 0.5 MHz)
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
2. ECM – External Clock Medium-Power mode
(0.5 MHz to 4 MHz)
3. ECH – External Clock High-Power mode
(4 MHz to 20 MHz)
4. INTOSC – Internal oscillator (31 kHz to 16 MHz)
Clock Source modes are selected by the FOSC<1:0>
bits in the Configuration Words. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
The EC clock mode relies on an external logic level
signal as the device clock source.
The INTOSC internal oscillator block produces low and
high-frequency clock sources, designated LFINTOSC
and HFINTOSC. (see Internal Oscillator Block,
Figure 5-1).
A
wide selection of device clock
frequencies may be derived from these clock sources.
FIGURE 5-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
CLKIN EC
EC
Sleep
CLKIN
CPU and
Peripherals
IRCF<3:0>
16 MHz
Internal Oscillator
8 MHz
4 MHz
2 MHz
Internal
Oscillator
Block
Clock
1 MHz
16 MHz
Source
Control
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
16 MHz
(HFINTOSC)
FOSC<1:0> SCS<1:0>
31 kHz
Source
31 kHz
31 kHz (LFINTOSC)
WDT, PWRT and other modules
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Preliminary
DS41615A-page 45
PIC12(L)F1501
5.2.1.1
EC Mode
5.2
Clock Source Types
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the CLKIN input. CLKOUT is
available for general purpose I/O or CLKOUT.
Figure 5-2 shows the pin connections for EC mode.
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator mod-
ules (EC mode).
Internal clock sources are contained within the
oscillator module. The oscillator block has two internal
oscillators that are used to generate two system clock
sources: the 16 MHz High-Frequency Internal
Oscillator (HFINTOSC) and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
EC mode has 3 power modes to select from through
Configuration Words:
• High power, 4-20 MHz (FOSC = 11)
• Medium power, 0.5-4 MHz (FOSC = 10)
• Low power, 0-0.5 MHz (FOSC = 01)
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
When EC mode is selected, there is no delay in opera-
tion after a Power-on Reset (POR) or wake-up from
Sleep. Because the PIC® MCU design is fully static,
stopping the external clock input will have the effect of
halting the device while leaving all data intact. Upon
restarting the external clock, the device will resume
operation as if no time had elapsed.
5.2.1
EXTERNAL CLOCK SOURCES
An external clock source can be used as the device
system clock by performing one of the following
actions:
FIGURE 5-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
• Program the FOSC<1:0> bits in the Configuration
Words to select an external clock source that will
be used as the default system clock upon a
device Reset.
CLKIN
Clock from
• Clear the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
Ext. System
PIC® MCU
CLKOUT
- An external clock source determined by the
value of the FOSC bits.
(1)
FOSC/4 or
I/O
See Section 5.3 “Clock Switching”for more informa-
tion.
Note 1: Output depends upon CLKOUTEN bit of the
Configuration Words.
DS41615A-page 46
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
5.2.2
INTERNAL CLOCK SOURCES
5.2.2.2
LFINTOSC
The device may be configured to use the internal oscil-
lator block as the system clock by performing one of the
following actions:
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a multiplexer
(see Figure 5-1). Select 31 kHz, via software, using the
IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information. The LFINTOSC is also
the frequency for the Power-up Timer (PWRT) and
Watchdog Timer (WDT).
• Program the FOSC<1:0> bits in Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
“Clock Switching”for more information.
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000x) as
the system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT is available for general purpose
I/O or CLKOUT.
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
The function of the CLKOUT pin is determined by the
CLKOUTEN bit in Configuration Words.
• FOSC<1:0> = 00, or
The internal oscillator block has two independent
oscillators clock sources.
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz.
Peripherals that use the LFINTOSC are:
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running.
5.2.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
The outputs of the HFINTOSC connects to a prescaler
and multiplexer (see Figure 5-1). One of multiple
frequencies derived from the HFINTOSC can be
selected via software using the IRCF<3:0> bits of the
OSCCON register. See Section 5.2.2.4 “Internal
Oscillator Clock Switch Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<1:0> = 00, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
A fast start-up oscillator allows internal circuits to
power-up and stabilize before switching to HFINTOSC.
The High-Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running.
The High-Frequency Internal Oscillator Stable bit
(HFIOFS) of the OSCSTAT register indicates when the
HFINTOSC is running within 0.5% of its final value.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 47
PIC12(L)F1501
5.2.2.3
Internal Oscillator Frequency
Selection
5.2.2.4
Internal Oscillator Clock Switch
Timing
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-3). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
The outputs of the 16 MHz HFINTOSC postscaler and
the LFINTOSC connect to
a
multiplexer (see
Figure 5-1). The Internal Oscillator Frequency Select
bits IRCF<3:0> of the OSCCON register select the
frequency output of the internal oscillators. One of the
following frequencies can be selected via software:
1. IRCF<3:0> bits of the OSCCON register are
modified.
• HFINTOSC
- 16 MHz
2. If the new clock is shut down, a clock start-up
delay is started.
- 8 MHz
- 4 MHz
3. Clock switch circuitry waits for a falling edge of
the current clock.
- 2 MHz
- 1 MHz
4. Clock switch is complete.
See Figure 5-3 for more details.
- 500 kHz (default after Reset)
- 250 kHz
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected.
- 125 kHz
- 62.5 kHz
- 31.25 kHz
• LFINTOSC
- 31 kHz
Start-up delay specifications are located in the
oscillator tables of Section 27.0 “Electrical
Specifications”.
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
DS41615A-page 48
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 5-3:
HFINTOSC
INTERNAL OSCILLATOR SWITCH TIMING
LFINTOSC (WDT disabled)
HFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
0
IRCF <3:0>
System Clock
HFINTOSC
LFINTOSC (WDT enabled)
HFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT is enabled
LFINTOSC
Start-up Time 2-cycle Sync
Running
HFINTOSC
= 0
0
IRCF <3:0>
System Clock
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 49
PIC12(L)F1501
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
5.3
Clock Switching
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<1:0> bits in the Configuration Words.
• Default system oscillator determined by FOSC
bits in Configuration Words
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
• Internal Oscillator Block (INTOSC)
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-2.
TABLE 5-1:
Switch From
OSCILLATOR SWITCHING DELAYS
Switch To
Frequency
Oscillator Delay
LFINTOSC
HFINTOSC
31 kHz
31.25 kHz-16 MHz
DC – 20 MHz
DC – 20 MHz
31.25 kHz-16 MHz
31 kHz
Sleep/POR
2 cycles
EC
LFINTOSC
EC
1 cycle of each
2 s (approx.)
1 cycle of each
Any clock source
Any clock source
HFINTOSC
LFINTOSC
DS41615A-page 50
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
5.4
Oscillator Control Registers
REGISTER 5-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1
IRCF<3:0>
U-0
—
U-0
—
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
1111= 16 MHz
1110= 8 MHz
1101= 4 MHz
1100= 2 MHz
1011= 1 MHz
1010= 500 kHz(1)
1001= 250 kHz(1)
1000= 125 kHz(1)
0111= 500 kHz (default upon Reset)
0110= 250 kHz
0101= 125 kHz
0100= 62.5 kHz
001x= 31.25 kHz
000x= 31 kHz (LFINTOSC)
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Reserved
00= Clock determined by FOSC<1:0> in Configuration Words
Note 1: Duplicate frequency derived from HFINTOSC.
2011 Microchip Technology Inc.
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PIC12(L)F1501
REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-0/q
U-0
—
U-0
—
R-0/q
R-0/q
HFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Conditional
bit 7-5
bit 4
Unimplemented: Read as ‘0’
HFIOFR: High-Frequency Internal Oscillator Ready bit
1= 16 MHz Internal Oscillator (HFINTOSC) is ready
0= 16 MHz Internal Oscillator (HFINTOSC) is not ready
bit 3-2
bit 1
Unimplemented: Read as ‘0’
LFIOFR: Low-Frequency Internal Oscillator Ready bit
1= 31 kHz Internal Oscillator (LFINTOSC) is ready
0= 31 kHz Internal Oscillator (LFINTOSC) is not ready
bit 0
HFIOFS: High-Frequency Internal Oscillator Stable bit
1= 16 MHz Internal Oscillator (HFINTOSC) is stable
0= 16 MHz Internal Oscillator (HFINTOSC) is not yet stable
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
OSCCON
OSCSTAT
IRCF<3:0>
—
—
SCS<1:0>
51
52
—
—
HFIOFR
—
LFIOFR
HFIOFS
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
CLKOUTEN
BOREN<1:0>
—
CONFIG1
40
CP
MCLRE
PWRTE
WDTE<1:0>
FOSC<1:0>
—
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
DS41615A-page 52
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
6.0
RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESETinstruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-chip Reset Circuit
is shown in Figure 6-1.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
ICSP™ Programming Mode Exit
RESETInstruction
Stack
Pointer
MCLRE
Sleep
MCLR
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
PWRT
R
Done
LPBOR
Reset
PWRTE
LFINTOSC
BOR
Active(1)
Note 1: See Table 6-1 for BOR active conditions.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 53
PIC12(L)F1501
6.1
Power-on Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Words. The four operating modes are:
• BOR is always on
6.1.1
POWER-UP TIMER (PWRT)
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
The Power-up Timer provides a nominal 64 ms
time-out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Words.
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Words.
A VDD noise rejection filter prevents the BOR from trig-
gering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
BOREN<1:0>
11
BOR OPERATING MODES
Instruction Execution upon:
Release of POR or Wake-up from Sleep
SBOREN
Device Mode
BOR Mode
X
X
X
Awake
Sleep
X
Active
Active
Waits for BOR ready(1) (BORRDY = 1)
10
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready(1) (BORRDY = 1)
Begins immediately (BORRDY = x)
Disabled
Active
1
0
X
01
00
X
Disabled
Disabled
X
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
6.2.1
BOR IS ALWAYS ON
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Words are pro-
grammed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
When the BOREN bits of Configuration Words are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device
start-up is not delayed by the BOR ready condition or
the VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
6.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Words are pro-
grammed to ‘10’, the BOR is on, except in Sleep. The
device start-up will be delayed until the BOR is ready
and VDD is higher than the BOR threshold.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
DS41615A-page 54
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
R/W-0/u
BORFS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-q/u
BORRDY
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
SBOREN: Software Brown-out Reset Enable bit
If BOREN <1:0> in Configuration Words 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> in Configuration Words = 01:
1= BOR Enabled
0= BOR Disabled
(1)
BORFS: Brown-out Reset Fast Start bit
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1= Band gap is forced on always (covers sleep/wake-up/operating cases)
0= Band gap operates normally, and may turn off
bit 5-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Words.
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Preliminary
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PIC12(L)F1501
6.3
Low-Power Brown-out Reset
(LPBOR)
6.5
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 9.0
“Watchdog Timer” for more information.
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.6
RESET Instruction
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.3.1
ENABLING LPBOR
6.7
Stack Overflow/Underflow Reset
The LPBOR is controlled by the LPBOR bit of
Configuration Words. When the device is erased, the
LPBOR module defaults to disabled.
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Words. See Section 3.4.2 “Overflow/Underflow
Reset” for more information.
6.3.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR mod-
ule to provide the generic BOR signal which goes to
the PCON register and to the power control block.
6.8
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.4
MCLR
6.9
Power-Up Timer
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Words and the LVP bit of
Configuration Words (Table 6-2).
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
TABLE 6-2:
MCLRE
MCLR CONFIGURATION
The Power-up Timer is controlled by the PWRTE bit of
Configuration Words.
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
6.10 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. MCLR must be released (if enabled).
6.4.1
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module” for more informa-
tion.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
The Power-up Timer runs independently of MCLR
Reset. If MCLR is kept low long enough, the Power-up
Timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Note:
A Reset does not drive the MCLR pin low.
6.4.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 11.2 “PORTA Regis-
ters” for more information.
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PIC12(L)F1501
FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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PIC12(L)F1501
6.11 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 6-3 and Table 6-4 show the Reset
conditions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
u
0
u
u
u
u
u
u
u
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
u
u
u
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-- 110x
uu-- 0uuu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
PC + 1(1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit (GIE) is set, the return address
is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
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PIC12(L)F1501
6.12 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q
U-0
—
R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF
bit 7
STKUNF
RWDT
RMCLR
RI
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred
0= A Stack Overflow has not occurred or cleared by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred
0= A Stack Underflow has not occurred or cleared by firmware
bit 5
bit 4
Unimplemented: Read as ‘0’
RWDT: Watchdog Timer Reset Flag bit
1= A Watchdog Timer Reset has not occurred or set by firmware
0= A Watchdog Timer Reset has occurred (cleared by hardware)
bit 3
bit 2
bit 1
bit 0
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set by firmware
0= A MCLR Reset has occurred (cleared by hardware)
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set by firmware
0= A RESETinstruction has been executed (cleared by hardware)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
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PIC12(L)F1501
TABLE 6-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BORCON SBOREN BORFS
—
—
—
—
RWDT
TO
—
RMCLR
PD
—
RI
Z
—
POR
DC
BORRDY
BOR
55
59
18
81
PCON
STKOVF STKUNF
STATUS
WDTCON
—
—
—
—
C
WDTPS<4:0>
SWDTEN
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TABLE 6-6:
SUMMARY OF CONFIGURATION WORD WITH RESETS
Register
on Page
Name
Bits Bit -/7
Bit -/6 Bit 13/5 Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
CP
—
—
—
—
CLKOUTEN
BOREN<1:0>
—
CONFIG1
CONFIG2
40
41
MCLRE PWRTE
WDTE<1:0>
—
FOSC<1:0>
13:8
7:0
—
—
LVP
—
—
—
LPBOR
—
BORV STVREN
—
—
—
WRT<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
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7.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
(TMR1IF) PIR1<0>
IOCIF
IOCIE
Interrupt
to CPU
(TMR1IF) PIR1<0>
PEIE
GIE
PIRn<7>
PIEn<7>
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7.1
Operation
7.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-2
and Figure 7.3 for more details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1, PIE2 and PIE3 registers)
The INTCON, PIR1, PIR2 and PIR3 registers record
individual interrupts via interrupt flag bits. Interrupt flag
bits will be set, regardless of the status of the GIE, PEIE
and individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See “Section 7.5 “Automatic
Context Saving”.”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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PIC12(L)F1501
FIGURE 7-2:
INTERRUPT LATENCY
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC-1
PC
PC+1
0004h
0005h
PC
1 Cycle Instruction at PC
Execute
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC+1/FSR
ADDR
New PC/
PC+1
PC-1
PC
0004h
0005h
PC
Execute
2 Cycle Instruction at PC
Inst(PC)
NOP
NOP
Inst(0004h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
PC+2
0004h
0005h
PC
NOP
Execute
3 Cycle Instruction at PC
NOP
NOP
NOP
Inst(0004h)
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PIC12(L)F1501
FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
FOSC
CLKOUT
(3)
INT pin
INTF
(1)
(1)
(2)
(4)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Forced NOP
Forced NOP
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: For minimum width of INT pulse, refer to AC specifications in Section 27.0 “Electrical Specifications””.
4: INTF is enabled to be set any time during the Q4-Q1 cycles.
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PIC12(L)F1501
7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to Section 8.0
“Power-Down Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s appli-
cation, other registers may also need to be saved.
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PIC12(L)F1501
7.6
Interrupt Control Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
7.6.1
INTCON REGISTER
The INTCON register is a readable and writable
register, that contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF
R/W-0/0
INTF
R-0/0
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the INT external interrupt
0= Disables the INT external interrupt
IOCIE: Interrupt-on-Change Enable bit
1= Enables the interrupt-on-change
0= Disables the interrupt-on-change
TMR0IF: Timer0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1= When at least one of the interrupt-on-change pins changed state
0= None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCBF register
have been cleared by software.
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7.6.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 Gate Acquisition interrupt
0= Disables the Timer1 Gate Acquisition interrupt
ADIE: A/D Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
bit 5-2
bit 1
Unimplemented: Read as ‘0’
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
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PIC12(L)F1501
7.6.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0
—
U-0
—
R/W-0/0
C1IE
U-0
—
U-0
—
R/W-0/0
NCO1IE
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
C1IE: Comparator C1 Interrupt Enable bit
1= Enables the Comparator C1 interrupt
0= Disables the Comparator C1 interrupt
bit 4-3
bit 2
Unimplemented: Read as ‘0’
NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit
1= Enables the NCO interrupt
0= Disables the NCO interrupt
bit 1-0
Unimplemented: Read as ‘0’
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7.6.4
PIE3 REGISTER
The PIE3 register contains the interrupt enable bits, as
shown in Register 7-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-4:
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
CLC2IE
R/W-0/0
CLC1IE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
CLC2IE: Configurable Logic Block 2 Interrupt Enable bit
1= Enables the CLC 2 interrupt
0= Disables the CLC 2 interrupt
bit 0
CLC1IE: Configurable Logic Block 1 Interrupt Enable bit
1= Enables the CLC 1 interrupt
0= Disables the CLC 1 interrupt
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PIC12(L)F1501
7.6.5
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
ADIF: A/D Converter Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 5-2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
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2011 Microchip Technology Inc.
PIC12(L)F1501
7.6.6
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-6.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-6:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
U-0
—
U-0
—
R/W-0/0
C1IF
U-0
—
U-0
—
R/W-0/0
NCO1IF
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5
Unimplemented: Read as ‘0’
C1IF: Numerically Controlled Oscillator Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 4-3
bit 2
Unimplemented: Read as ‘0’
NCO1IF: Numerically Controlled Oscillator Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 1-0
Unimplemented: Read as ‘0’
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PIC12(L)F1501
7.6.7
PIR3 REGISTER
The PIR3 register contains the interrupt flag bits, as
shown in Register 7-7.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-7:
PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
CLC2IF
R/W-0/0
CLC1IF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
CLC2IF: Configurable Logic Block 2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 0
CLC1IF: Configurable Logic Block 1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
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PIC12(L)F1501
TABLE 7-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
PSA
—
TMR0IF
INTF
IOCIF
66
143
67
68
69
70
71
72
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PS<2:0>
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
TMR1GIE
ADIE
—
—
—
—
—
—
—
—
—
NCO1IE
—
TMR2IE TMR1IE
C1IE
—
—
—
—
—
TMR1GIF
—
—
—
—
—
CLC2IE CLC1IE
TMR2IF TMR1IF
—
ADIF
—
—
C1IF
NCO1IF
—
—
—
—
—
—
—
—
CLC2IF CLC1IF
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
2011 Microchip Technology Inc.
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PIC12(L)F1501
NOTES:
DS41615A-page 74
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2011 Microchip Technology Inc.
PIC12(L)F1501
8.1
Wake-up from Sleep
8.0
POWER-DOWN MODE (SLEEP)
The device can wake-up from Sleep through one of the
following events:
The Power-Down mode is entered by executing a
SLEEPinstruction.
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
Upon entering Sleep mode, the following conditions exist:
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
3. POR Reset
4. Watchdog Timer, if enabled
5. Any external interrupt
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
6. Interrupts by peripherals capable of running dur-
ing Sleep (see individual peripheral for more
information)
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.11
“Determining the Cause of a Reset”.
6. ADC is unaffected, if the dedicated FRC clock is
selected.
7. I/O ports maintain the status they had before
SLEEP was executed (driving high, low or
high-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEPinstruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
8. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following
conditions should be considered:
• I/O pins should not be floating
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
• CWG, NCO and CLC modules using HFINTOSC
8.1.1
WAKE-UP USING INTERRUPTS
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 13.0
“Fixed Voltage Reference (FVR)” for more
information on this module.
• If the interrupt occurs before the execution of a
SLEEPinstruction:
- SLEEPinstruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction:
- SLEEPinstruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
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PIC12(L)F1501
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
FIGURE 8-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2)
Interrupt Latency(3)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Forced NOP
Forced NOP
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
2:
3:
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PIC12(L)F1501
8.2.2
PERIPHERAL USAGE IN SLEEP
8.2
Low-Power Sleep Mode
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the Normal Power
mode when those peripherals are enabled. The
Low-Power Sleep mode is intended for use with these
peripherals:
The PIC12F1501 device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC12F1501 allows the user to optimize the operating
current in Sleep, depending on the application
requirements.
• Brown-Out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/Interrupt-on-change pins
• Timer1 (with external clock source)
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
The Complementary Waveform Generator (CWG), the
Numerically Controlled Oscillator (NCO) and the Con-
figurable Logic Cell (CLC) modules can utilize the
HFINTOSC oscillator as either a clock source or as an
input source. Under certain conditions, when the
HFINTOSC is selected for use with the CWG, NCO or
CLC modules, the HFINTOSC will remain active during
Sleep. This will have a direct effect on the Sleep mode
current.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con-
figuration and stabilize.
Please refer to sections 22.5 “Operation During
Sleep”, 23.7 “Operation In Sleep” and 24.10 “Oper-
ation During Sleep” for more information.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The Normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
Note:
The PIC12LF1501 does not have a con-
figurable Low-Power Sleep mode.
PIC12LF1501 is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD and I/O voltage than the
PIC12F1501. See Section 25.0 “Electri-
cal Specifications” for more information.
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PIC12(L)F1501
REGISTER 8-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1= Low-Power Sleep mode enabled in Sleep
Draws lowest current in Sleep, slower wake-up
0= Normal Power mode enabled in Sleep
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC12F1501 only.
TABLE 8-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register on
Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCAF
GIE
—
PEIE
—
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
66
107
107
107
67
IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0
IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0
IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0
IOCAN
IOCAP
—
—
—
—
PIE1
TMR1GIE
ADIE
—
—
—
—
—
—
—
—
TO
—
—
NCO1IE
—
TMR2IE TMR1IE
C1IE
PIE2
—
—
—
—
68
PIE3
—
—
—
—
—
CLC2IE CLC1IE
TMR2IF TMR1IF
69
—
PIR1
TMR1GIF
ADIF
—
—
70
C1IF
NCO1IF
PIR2
—
—
—
—
—
—
CLC2IF
DC
—
CLC1IF
C
71
PIR3
—
—
—
—
PD
—
Z
72
STATUS
WDTCON
—
18
—
WDTPS<4:0>
SWDTEN
81
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
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2011 Microchip Technology Inc.
PIC12(L)F1501
9.0
WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 9-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
WDTE<1:0> = 11
LFINTOSC
WDT Time-out
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
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PIC12(L)F1501
9.1
Independent Clock Source
9.3
Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1 ms. See
Section 27.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the
time-out period from 1 ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
9.4
Clearing the WDT
The WDT is cleared when any of the following condi-
tions occur:
9.2
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Words. See Table 9-1.
• Any Reset
• CLRWDTinstruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail
9.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Words are set to
‘11’, the WDT is always on.
• WDT is disabled
WDT protection is active during Sleep.
See Table 9-2 for more information.
9.2.2
WDT IS OFF IN SLEEP
9.5
Operation During Sleep
When the WDTE bits of Configuration Words are set to
‘10’, the WDT is on, except in Sleep.
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting. When the device exits Sleep, the WDT is
cleared again.
WDT protection is not active during Sleep.
9.2.3
WDT CONTROLLED BY SOFTWARE
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON register can also be
used. See Section 3.0 “Memory Organization” for
more information.
When the WDTE bits of Configuration Words are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 9-1
for more details.
TABLE 9-1:
WDTE<1:0>
WDT OPERATING MODES
Device
Mode
WDT
Mode
SWDTEN
11
10
X
X
X
Active
Active
Awake
Sleep Disabled
1
0
X
Active
X
01
Disabled
00
X
Disabled
TABLE 9-2:
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = INTOSC, EXTCLK
Change INTOSC divider (IRCF bits)
Unaffected
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PIC12(L)F1501
9.6
Watchdog Control Register
REGISTER 9-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS<4:0>
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (217) (Interval 4s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10010 = 1:8388608 (223) (Interval 256s nominal)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
2011 Microchip Technology Inc.
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PIC12(L)F1501
TABLE 9-3:
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
PCON
—
STKOVF
—
IRCF<3:0>
—
RI
Z
SCS<1:0>
51
59
18
81
STKUNF
—
—
RWDT
TO
RMCLR
PD
POR
DC
BOR
C
STATUS
WDTCON
—
—
—
WDTPS<4:0>
SWDTEN
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 9-4:
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
CLKOUTEN
BOREN<1:0>
—
CONFIG1
40
CP
MCLRE
PWRTE
WDTE<1:0>
—
FOSC<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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PIC12(L)F1501
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
10.0 FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
• PMCON1
• PMCON2
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
10.2 Flash Program Memory Overview
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge
pump.
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Words)
and write protection (WRT<1:0> bits in Configuration
Words).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. How-
ever, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Words.
10.1 PMADRL and PMADRH Registers
See Table 10-1 for Erase Row size and the number of
write latches for Flash program memory.
The PMADRH:PMADRL register pair can address up
to a maximum of 16K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
TABLE 10-1: FLASH MEMORY
ORGANIZATION BY DEVICE
Write
Latches
(words)
Row Erase
(words)
Device
10.1.1
PMCON1 AND PMCON2
REGISTERS
PIC12F1501
PIC12LF1501
PMCON1 is the control register for Flash program
memory accesses.
16
16
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10.2.1
READING THE FLASH PROGRAM
MEMORY
To read a program memory location, the user must:
1. Write the desired address to the
PMADRH:PMADRL register pair.
2. Clear the CFGS bit of the PMCON1 register.
FIGURE 10-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
Read Operation
3. Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
Select
Program or Configuration Memory
(CFGS)
Select
Word Address
(PMADRH:PMADRL)
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
Initiate Read operation
(RD = 1)
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOPexecution forced
Data read now in
PMDATH:PMDATL
End
Read Operation
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FIGURE 10-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
PMADRH,PMADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
PMDATH,PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC + 1)
INSTR(PC + 2)
instruction ignored instruction ignored
BSF PMCON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
Forced NOP
Forced NOP
executed here
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; Select Bank for PMCON registers
MOVLW
MOVWF
MOVLW
MOVWF
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
; Do not select Configuration Space
; Initiate read
; Ignored (Figure 10-2)
; Ignored (Figure 10-2)
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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10.2.2
FLASH MEMORY UNLOCK
SEQUENCE
FIGURE 10-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
Start
Unlock Sequence
• Row Erase
• Load program memory write latches
Write 055h to
PMCON2
• Write of program memory write latches to pro-
gram memory
• Write of program memory write latches to User
IDs
Write 0AAh to
PMCON2
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
Initiate
Write or Erase operation
(WR = 1)
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOPinstruction
5. NOPinstruction
Instruction Fetched ignored
NOPexecution forced
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Instruction Fetched ignored
NOPexecution forced
End
Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
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10.2.3
ERASING FLASH PROGRAM
MEMORY
FIGURE 10-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Start
Erase Operation
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register.
Disable Interrupts
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
(GIE = 0)
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
Select
Program or Configuration Memory
(CFGS)
See Example 10-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
Select Row Address
(PMADRH:PMADRL)
Select Erase Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 10-3
CPU stalls while
Erase operation completes
(2ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
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EXAMPLE 10-2:
ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
; Not configuration space
; Specify an erase operation
; Enable writes
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
NOP
NOP
; NOP instructions are forced as processor starts
; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
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The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
10.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1. Load the address in PMADRH:PMADRL of the
row to be programmed.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 10-5 (row writes to program memory with 16
write latches) for more details.
1. Set the WREN bit of the PMCON1 register.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
The write latches are aligned to the Flash row address
boundary defined by the upper 11-bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:4>)
with the lower 4-bits of PMADRL, (PMADRL<3:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 10.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 10-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
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FIGURE 10-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
Write Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
(word_cnt)
Update the word counter
(word_cnt--)
Write Latches to Flash
Disable Interrupts
(LWLO = 0)
(GIE = 0)
Unlock Sequence
Figure 10-3
Select
Program or Config. Memory
(CFGS)
Yes
Last word to
write ?
CPU stalls while Write
operation completes
(2ms typical)
No
Select Row Address
(PMADRH:PMADRL)
Unlock Sequence
Figure 10-3
Select Write Operation
(FREE = 0)
Disable
Write/Erase Operation
(WREN = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
Write Operation
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EXAMPLE 10-3:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 32 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
; Disable ints so required sequences will execute properly
; Bank 3
; Load initial address
;
;
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
LOW DATA_ADDR ; Load initial data address
FSR0L
HIGH DATA_ADDR ; Load initial data address
;
FSR0H
;
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
; Not configuration space
; Enable writes
; Only Load Write Latches
BSF
BSF
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
PMADRL,W
0x0F
0x0F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 16 addresses
;
; Exit if last of 16 words,
;
XORLW
ANDLW
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor
; loads program memory write latches
;
NOP
NOP
INCF
GOTO
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
START_WRITE
BCF
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
MOVLW
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required write sequence:
; Write 55h
;
MOVWF
MOVLW
MOVWF
BSF
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
; to program memory.
NOP
NOP
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
; Disable writes
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Enable interrupts
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FIGURE 10-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
10.3 Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Start
Modify Operation
1. Load the starting address of the row to be
modified.
2. Read the existing data from the row into a RAM
image.
Read Operation
Figure 10-2
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
An image of the entire row read
must be stored in RAM
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
Figure 10-4
Write Operation
use RAM image
Figure 10-5
End
Modify Operation
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10.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 10-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 10-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
8000h-8003h
Function
Read Access
Write Access
User IDs
Yes
Yes
Yes
Yes
No
No
8006h
Device ID/Revision ID
8007h-8008h
Configuration Words 1 and 2
EXAMPLE 10-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
MOVLW
MOVWF
CLRF
PROG_ADDR_LO
PMADRL
PMADRH
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
; Select Configuration Space
; Disable interrupts
; Initiate read
; Executed (See Figure 10-2)
; Ignored (See Figure 10-2)
; Restore interrupts
INTCON,GIE
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
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10.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
Read Operation
Figure 10-2
PMDAT =
RAM image
?
No
Fail
Verify Operation
Yes
No
Last
Word ?
Yes
End
Verify Operation
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10.6 Flash Program Memory Control Registers
REGISTER 10-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-1
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘1’
PMADR<14:8>: Specifies the Most Significant bits for program memory address
bit 6-0
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REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
—
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0 R/W/HC-x/q(2)
FREE WRERR
R/W-0/0
WREN
R/S/HC-0/0
WR
R/S/HC-0/0
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
Unimplemented: Read as ‘1’
CFGS: Configuration Select bit
1= Access Configuration, User ID and Device ID Registers
0= Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1= Only the addressed program memory write latch is loaded/updated on the next WR command
0= The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4
bit 3
FREE: Program Flash Erase Enable bit
1= Performs an erase operation on the next WR command (hardware cleared upon completion)
0= Performs an write operation on the next WR command
WRERR: Program/Erase Error Flag bit
1= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0= The program or erase operation completed normally
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash
WR: Write Control bit
1= Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash is complete and inactive
bit 0
RD: Read Control bit
1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0= Does not initiate a program Flash read
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1).
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).
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REGISTER 10-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Program Memory Control Register 2
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMCON1
PMCON2
PMADRL
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
—
97
98
96
96
96
96
66
Program Memory Control Register 2
PMADRL<7:0>
PMADRH
PMDATL
—
PMADRH<6:0>
PMDATL<7:0>
PMDATH
INTCON
Legend:
—
—
PMDATH<5:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
CP
—
—
MCLRE
—
—
PWRTE
LVP
—
CLKOUTEN
BOREN<1:0>
—
CONFIG1
40
41
WDTE<1:0>
—
BORV
—
FOSC<1:0>
13:8
7:0
—
—
LPBOR
—
STVREN
WRT<1:0>
—
CONFIG2
—
—
—
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
DS41615A-page 98
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 11-1:
GENERIC I/O PORT
OPERATION
11.0 I/O PORTS
Each port has three standard registers for its operation.
These registers are:
• TRISx registers (data direction)
Read LATx
TRISx
• PORTx registers (reads the levels on the pins of
the device)
D
Q
• LATx registers (output latch)
Write LATx
Write PORTx
Some ports may have one or more of the following
additional registers. These registers are:
CK
Data Register
VDD
• ANSELx (analog select)
• WPUx (weak pull-up)
Data Bus
Read PORTx
In general, when a peripheral is enabled on a port pin,
that pin cannot be used as a general purpose output.
However, the pin can still be read.
I/O pin
To peripherals
VSS
ANSELx
TABLE 11-1: PORT AVAILABILITY PER
DEVICE
EXAMPLE 11-1:
INITIALIZING PORTA
Device
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
PIC12(L)F1501
●
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
BANKSEL PORTA
CLRF PORTA
BANKSEL LATA
CLRF LATA
BANKSEL ANSELA
CLRF ANSELA
BANKSEL TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
MOVLW
MOVWF
B'00111000' ;Set RA<5:3> as inputs
TRISA
;and set RA<2:0> as
;outputs
Ports that support analog inputs have an associated
ANSELx register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 11-1.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 99
PIC12(L)F1501
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
11.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. The APFCON register
is shown in Register 11-1. For this device family, the
following functions can be moved between different
pins.
• SDO
• SS
• T1G
• CLC1
• NCO1
REGISTER 11-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
T1GSEL
U-0
—
R/W-0/0
R/W-0/0
CWG1BSEL CWG1ASEL
bit 7
CLC1SEL
NCO1SEL
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
CWG1BSEL: Pin Selection bit
1= CWG1B function is on RA4
0= CWG1B function is on RA0
CWG1ASEL: Pin Selection bit
1= CWG1A function is on RA5
0= CWG1A function is on RA2
bit 5-4
bit 3
Unimplemented: Read as ‘0’
T1GSEL: Pin Selection bit
1= T1G function is on RA3
0= T1G function is on RA4
bit 2
bit 1
Unimplemented: Read as ‘0’
CLC1SEL: Pin Selection bit
1= CLC1 function is on RA4
0= CLC1 function is on RA2
bit 0
NCO1SEL: Pin Selection bit
1= NCO1 function is on RA5
0= NCO1 function is on RA1
DS41615A-page 100
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
11.2.2
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
11.2 PORTA Registers
PORTA is a 6-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 11-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). The exception is RA3, which is
input only and its TRIS bit will always read as ‘1’.
Example 11-1 shows how to initialize an I/O port.
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 11-2.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC and comparator
inputs, are not shown in the priority lists. These inputs
are active when the I/O pin is set for Analog mode using
the ANSELx registers. Digital output functions may
control the pin when it is in Analog mode with the
priority shown in Table 11-2.
Reading the PORTA register (Register 11-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
TABLE 11-2: PORTA OUTPUT PRIORITY
(1)
Pin Name
Function Priority
The TRISA register (Register 11-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RA0
ICSPDAT
DACOUT1
CWG1B(2)
PWM2
RA0
NCO1(2)
RA1
RA1
RA2
11.2.1
ANSELA REGISTER
DACOUT2
CWG1A(2)
CWG1FLT
CLC1(2)
C1OUT
PWM1
The ANSELA register (Register 11-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
RA2
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
RA3
RA4
None
CLKOUT
CWG1B(3)
CLC1(3)
PWM3
RA4
RA5
CWG1A(3)
CLC2
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
NCO1(3)
PWM4
RA5
Note 1: Priority listed from highest to lowest.
2: Default pin (see APFCON register).
3: Alternate pin (see APFCON register).
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 101
PIC12(L)F1501
REGISTER 11-2: PORTA: PORTA REGISTER
U-0
—
U-0
—
R/W-x/x
RA5
R/W-x/x
RA4
R-x/x
RA3
R/W-x/x
RA2
R/W-x/x
RA1
R/W-x/x
RA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
RA<5:0>: PORTA I/O Value bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-3: TRISA: PORTA TRI-STATE REGISTER
U-0
—
U-0
—
R/W-1/1
TRISA5
R/W-1/1
TRISA4
U-1
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
(1)
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
TRISA<5:4>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
bit 3
Unimplemented: Read as ‘1’
bit 2-0
TRISA<2:0>: PORTA Tri-State Control bit
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
Note 1: Unimplemented, read as ‘1’.
DS41615A-page 102
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 11-4: LATA: PORTA DATA LATCH REGISTER
U-0
—
U-0
—
R/W-x/u
LATA5
R/W-x/u
LATA4
U-0
—
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
bit 3
Unimplemented: Read as ‘0’
LATA<5:4>: RA<5:4> Output Latch Value bits(1)
Unimplemented: Read as ‘0’
bit 2-0
LATA<2:0>: RA<2:0> Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return
of actual I/O pin values.
REGISTER 11-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
U-0
—
R/W-1/1
ANSA4
U-0
—
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-5
bit 4
Unimplemented: Read as ‘0’
ANSA4: Analog Select between Analog or Digital Function on pins RA4, respectively
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
0= Digital I/O. Pin is assigned to port or digital special function.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 103
PIC12(L)F1501
REGISTER 11-6: WPUA: WEAK PULL-UP PORTA REGISTER
U-0
—
U-0
—
R/W-1/1
WPUA5
R/W-1/1
WPUA4
R/W-1/1
WPUA3
R/W-1/1
WPUA2
R/W-1/1
WPUA1
R/W-1/1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits(3)
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
3: For the WPUA3 bit, when MCLRE = 1, weak pull-up is internally enabled, but not reported here.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
—
ANSA4
—
—
ANSA2
—
ANSA1
ANSA0
103
100
103
143
102
102
104
CWG1BSEL CWG1ASEL
T1GSEL
APFCON
LATA
CLC1SEL NCO1SEL
—
WPUEN
—
—
INTEDG
—
LATA5
TMR0CS
RA5
LATA4
TMR0SE
RA4
—
LATA2
LATA1
PS<2:0>
RA1
LATA0
OPTION_REG
PORTA
PSA
RA3
RA2
RA0
(1)
—
TRISA
—
—
TRISA5
WPUA5
TRISA4
WPUA4
TRISA2
WPUA2
TRISA1
WPUA1
TRISA0
WPUA0
WPUA
—
—
WPUA3
Legend:
Note 1:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Unimplemented, read as ‘1’.
TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
—
—
—
—
CLKOUTEN
BOREN<1:0>
—
CONFIG1
40
CP
MCLRE
PWRTE
WDTE<1:0>
—
FOSC<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
DS41615A-page 104
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
12.3 Interrupt Flags
12.0 INTERRUPT-ON-CHANGE
The IOCAFx and IOCBFx bits located in the IOCAF and
IOCBF registers, respectively, are status flags that
correspond to the interrupt-on-change pins of the
associated port. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx and IOCBFx bits.
The PORTA and PORTB pins can be configured to
operate as Interrupt-On-Change (IOC) pins. An interrupt
can be generated by detecting a signal that has either a
rising edge or a falling edge. Any individual port pin, or
combination of port pins, can be configured to generate
an interrupt. The interrupt-on-change module has the
following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
12.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags
The individual status flags, (IOCAFx and IOCBFx bits),
can be cleared by resetting them to zero. If another edge
is detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 12-1 is a block diagram of the IOC module.
12.1 Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 12-1:
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
12.2 Individual Pin Configuration
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
MOVLW 0xff
XORWF IOCAF, W
ANDWF IOCAF, F
A pin can be configured to detect rising and falling
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
12.5 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 105
PIC12(L)F1501
FIGURE 12-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE)
Q4Q1
IOCANx
D
Q
CK
Edge
Detect
R
RAx
Data Bus =
0 or 1
S
To Data Bus
IOCAFx
IOCAPx
D
D
Q
Q
Write IOCAFx
CK
CK
IOCIE
R
Q2
From all other
IOCAFx individual
pin detectors
IOC interrupt
to CPU core
Q1
Q1
Q1
Q2
Q3
Q2
Q2
Q3
Q3
Q4
Q4
Q4Q1
Q4
Q4
Q4Q1
Q4Q1
Q4Q1
DS41615A-page 106
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
12.6 Interrupt-On-Change Registers
REGISTER 12-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
—
U-0
—
R/W-0/0
IOCAP5
R/W-0/0
IOCAP4
R/W-0/0
IOCAP3
R/W-0/0
IOCAP2
R/W-0/0
IOCAP1
R/W-0/0
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 12-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
—
U-0
—
R/W-0/0
IOCAN5
R/W-0/0
IOCAN4
R/W-0/0
IOCAN3
R/W-0/0
IOCAN2
R/W-0/0
IOCAN1
R/W-0/0
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set
upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 12-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
—
U-0
—
R/W/HS-0/0
IOCAF5
R/W/HS-0/0
IOCAF4
R/W/HS-0/0
IOCAF3
R/W/HS-0/0
IOCAF2
R/W/HS-0/0
IOCAF1
R/W/HS-0/0
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling edge was
detected on RAx.
0= No change was detected, or the user cleared the detected change
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 107
PIC12(L)F1501
TABLE 12-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
GIE
—
—
PEIE
—
—
ANSA4
INTE
—
ANSA2
TMR0IF
IOCAF2
IOCAN2
IOCAP2
TRISA2
ANSA1
INTF
ANSA0
IOCIF
103
66
INTCON
IOCAF
IOCAN
IOCAP
TRISA
TMR0IE
IOCAF5
IOCAN5
IOCAP5
TRISA5
IOCIE
IOCAF4
IOCAN4
IOCAP4
TRISA4
IOCAF3
IOCAN3
IOCAF1
IOCAN1
IOCAP1
TRISA1
IOCAF0
IOCAN0
IOCAP0
TRISA0
107
107
107
102
—
—
—
—
IOCAP3
—(1)
—
—
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.
Note 1: Unimplemented, read as ‘1’.
DS41615A-page 108
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
13.0 FIXED VOLTAGE REFERENCE
(FVR)
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The CDAFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the comparator modules.
Reference Section 17.0 “Comparator Module” for
additional information.
• ADC input channel
• Comparator positive input
• Comparator negative input
13.2 FVR Stabilization Period
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 27.0 “Electrical Specifications” for the
minimum delay requirement.
13.1 Independent Gain Amplifier
The output of the FVR supplied to the ADC and
comparators is routed through a programmable gain
amplifier. Each amplifier can be programmed for a gain
of 1x, 2x or 4x, to produce the three possible voltage
levels.
FIGURE 13-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
X1
X2
X4
FVR BUFFER1
(To ADC Module)
CDAFVR<1:0>
2
X1
X2
X4
FVR BUFFER2
(To Comparators)
+
_
FVREN
FVRRDY
Any peripheral requiring the
Fixed Reference
(See Table 13-1)
TABLE 13-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
Conditions
Description
HFINTOSC
FOSC<1:0> = 00and
INTOSC is active and device is not in Sleep.
IRCF<3:0> = 000x
BOREN<1:0> = 11
BOR always enabled.
BOR
LDO
BOREN<1:0> = 10and BORFS = 1
BOREN<1:0> = 01and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOR under software control, BOR Fast Start enabled.
All PIC12F1501 devices, when
VREGPM = 1and not in Sleep
The device runs off of the Low-Power Regulator when in
Sleep mode.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 109
PIC12(L)F1501
13.3 FVR Control Registers
REGISTER 13-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
TSEN
R/W-0/0
TSRNG
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3-2
FVREN: Fixed Voltage Reference Enable bit
1= Fixed Voltage Reference is enabled
0= Fixed Voltage Reference is disabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1= Fixed Voltage Reference output is ready for use
0= Fixed Voltage Reference output is not ready or not enabled
TSEN: Temperature Indicator Enable bit(3)
1= Temperature Indicator is enabled
0= Temperature Indicator is disabled
TSRNG: Temperature Indicator Range Selection bit(3)
1= VOUT = VDD - 4VT (High Range)
0= VOUT = VDD - 2VT (Low Range)
CDAFVR<1:0>: Comparator Fixed Voltage Reference Selection bits
11= Comparator Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10= Comparator Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01= Comparator Fixed Voltage Reference Peripheral output is 1x (1.024V)
00= Comparator Fixed Voltage Reference Peripheral output is off
bit 1-0
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bit
11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00= ADC Fixed Voltage Reference Peripheral output is off
Note 1: FVRRDY is always ‘1’ for the PIC12F1501 devices.
2: Fixed Voltage Reference output cannot exceed VDD.
3: See Section 14.0 “Temperature Indicator Module” for additional information.
TABLE 13-2: SUMMARYOF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR>1:0>
ADFVR<1:0>
110
Legend:
Shaded cells are unused by the Fixed Voltage Reference module.
DS41615A-page 110
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 14-1:
TEMPERATURE CIRCUIT
DIAGRAM
14.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
VOUT
To ADC
14.1 Circuit Operation
14.2 Minimum Operating VDD
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is cor-
rectly biased.
Equation 14-1 describes the output characteristics of
the temperature indicator.
EQUATION 14-1: VOUT RANGES
Table 14-1 shows the recommended minimum VDD vs.
range setting.
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
TABLE 14-1: RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 13.0 “Fixed Voltage Reference (FVR)” for
more information.
3.6V
1.8V
14.3 Temperature Output
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
14.4 ADC Acquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 111
PIC12(L)F1501
TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
118
Legend:
Shaded cells are unused by the temperature indicator module.
DS41615A-page 112
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
15.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 15-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 15-1:
ADC BLOCK DIAGRAM
VDD
ADPREF = 00
VREF+
ADPREF = 10
VREF- = VSS
VREF+
AN0
00000
VREF+/AN1
AN2
00001
00010
AN3
00011
00100
ADC
Reserved
10
GO/DONE
11100
11101
11110
11111
Reserved
Temp Indicator
DAC
0= Left Justify
1= Right Justify
ADFM
ADON
16
FVR Buffer1
ADRESH ADRESL
VSS
CHS<4:0>
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 113
PIC12(L)F1501
15.1.4
CONVERSION CLOCK
15.1 ADC Configuration
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• FOSC/8
• FOSC/16
• FOSC/32
• Result formatting
• FOSC/64
15.1.1
PORT CONFIGURATION
• FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 11.0 “I/O Ports” for more information.
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD peri-
ods as shown in Figure 15-2.
For correct conversion, the appropriate TAD specifica-
tion must be met. Refer to the A/D conversion require-
ments in Section 27.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of appro-
priate ADC clock selections.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
15.1.2
CHANNEL SELECTION
There are 7 channel selections available:
• AN<3:0> pins
• Temperature Indicator
• DAC
• FVR (Fixed Voltage Reference) Output
Refer to Section 13.0 “Fixed Voltage Reference (FVR)”
and Section 14.0 “Temperature Indicator Module” for
more information on these channel selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
DS41615A-page 114
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 15-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0>
Clock Source
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
100
001
101
010
110
x11
100 ns(2)
200 ns(2)
400 ns(2)
800 ns
125 ns(2)
250 ns(2)
0.5 s(2)
1.0 s
250 ns(2)
500 ns(2)
1.0 s
500 ns(2)
1.0 s
2.0 s
4.0 s
8.0 s(3)
16.0 s(3)
32.0 s(3)
64.0 s(3)
1.0-6.0 s(1,4)
2.0 s
2.0 s
4.0 s
1.6 s
2.0 s
4.0 s
8.0 s(3)
1.0-6.0 s(1,4)
8.0 s(3)
16.0 s(3)
1.0-6.0 s(1,4)
3.2 s
1.0-6.0 s(1,4)
4.0 s
1.0-6.0 s(1,4)
Legend:
Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7
b4
b1
b0
b9
b8
b7
b6
b5
b3
b2
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
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Preliminary
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PIC12(L)F1501
15.1.5
INTERRUPTS
15.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEPinstruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 15-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
bit 7
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
DS41615A-page 116
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
15.2.4
ADC OPERATION DURING SLEEP
15.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
15.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.6 “A/D Conver-
sion Procedure”.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
15.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
15.2.5
AUTO-CONVERSION TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result
The auto-conversion trigger allows periodic ADC mea-
surements without software intervention. When a rising
edge of the selected source occurs, the GO/DONE bit
is set by hardware.
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
The auto-conversion trigger source is selected with the
TRIGSEL<3:0> bits of the ADCON2 register.
Using the auto-conversion trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Auto-conversion sources are:
• TMR0
• TMR1
• TMR2
• C1
• CLC1
• CLC2
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 117
PIC12(L)F1501
15.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 15-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
BANKSEL
MOVLW
ADCON1
;
B’11110000’ ;Right justify, Frc
;clock
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
MOVWF
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
ADCON1
TRISA
TRISA,0
ANSEL
ANSEL,0
ADCON0
;Vdd and Vss Vref+
;
;Set RA0 to input
;
;Set RA0 to analog
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
B’00000001’ ;Select channel AN0
ADCON0
SampleTime
;Turn ADC On
;Acquisiton delay
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
BSF
BTFSC
GOTO
BANKSEL
MOVF
MOVWF
BANKSEL
MOVF
ADCON0,ADGO ;Start conversion
ADCON0,ADGO ;Is conversion done?
$-1
ADRESH
;No, test again
;
.
5. Start conversion by setting the GO/DONE bit.
ADRESH,W
RESULTHI
ADRESL
;Read upper 2 bits
;store in GPR space
;
6. Wait for ADC conversion to complete by one of
the following:
ADRESL,W
RESULTLO
;Read lower 8 bits
;Store in GPR space
• Polling the GO/DONE bit
MOVWF
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.3 “A/D Acquisition
Requirements”.
DS41615A-page 118
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
15.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the
operation of the ADC.
REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
CHS<4:0>
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000= AN0
00001= AN1
00010= AN2
00011= AN3
00100= Reserved. No channel connected.
•
•
•
11100= Reserved. No channel connected.
11101= Temperature Indicator(1)
11110= DAC (Digital-to-Analog Converter)(2)
11111=FVR (Fixed Voltage Reference) Buffer 1 Output(3)
GO/DONE: A/D Conversion Status bit
bit 1
bit 0
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Temperature Indicator Module” for more information.
2: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information.
3: See Section 13.0 “Fixed Voltage Reference (FVR)” for more information.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 119
PIC12(L)F1501
REGISTER 15-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
ADCS<2:0>
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock supplied from a dedicated RC oscillator)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00= VREF+ is connected to VDD
01= Reserved
10= VREF+ is connected to external VREF+ pin(1)
11= Reserved
Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 27.0 “Electrical Specifications” for details.
DS41615A-page 120
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 15-3: ADCON2: A/D CONTROL REGISTER 2
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
TRIGSEL<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1)
0000= No auto-conversion trigger selected
0001= Reserved
0010= Reserved
0011= TMR0 Overflow(2)
0100= TMR1 Overflow(2)
0101= TMR2 Match to PR2(2)
0110= C1OUT
0111= Reserved
1000= CLC1
1001= CLC2
1010= Reserved
1011= Reserved
1100= Reserved
1101= Reserved
1110= Reserved
1111= Reserved
bit 3-0
Unimplemented: Read as ‘0’
Note 1: This is a rising edge sensitive input for all sources.
2: Signal also sets its corresponding interrupt flag.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 121
PIC12(L)F1501
REGISTER 15-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<9:2>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 15-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
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Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 15-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 15-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
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PIC12(L)F1501
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
15.3 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –12.5pF1k + 7k + 10k ln(0.0004885)
= 1.12µs
Therefore:
TACQ = 5µs + 1.12µs + 50°C- 25°C0.05µs/°C
= 7.37µs
Note 1: The reference voltage (VREF+) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41615A-page 124
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 15-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
SS
VT 0.6V
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VREF-
VT 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Note 1: Refer to Section 27.0 “Electrical Specifications”.
FIGURE 15-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
1.5 LSB
0.5 LSB
Zero-Scale
Transition
VREF-
Full-Scale
Transition
VREF+
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PIC12(L)F1501
TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
119
120
ADCON0
ADCON1
ADCON2
ADRESH
—
CHS<4:0>
GO/DONE
ADON
ADFM
ADCS<2:0>
—
—
—
—
ADPREF<1:0>
TRIGSEL<3:0>
—
—
121
A/D Result Register High
A/D Result Register Low
122, 123
122, 123
103
ADRESL
ANSELA
INTCON
—
—
—
ANSA4
INTE
—
IOCIE
—
ANSA2
TMR0IF
ANSA1
INTF
ANSA0
IOCIF
GIE
PEIE
TMR0IE
66
PIE1
TMR1GIE
TMR1GIF
—
ADIE
ADIF
—
—
—
—
—
TMR2IE
TMR2IF
TRISA1
TMR1IE
TMR1IF
TRISA0
67
PIR1
—
—
—(1)
70
TRISA
FVRCON
Legend:
—
TRISA5
TSEN
TRISA4
TSRNG
TRISA2
102
FVREN
FVRRDY
CDAFVR<1:0>
ADFVR<1:0>
110
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for ADC module.
Note 1: Unimplemented, read as ‘1’.
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Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
16.1 Output Voltage Selection
16.0 DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
The DAC has 32 voltage level ranges. The 32 levels
are set with the DACR<4:0> bits of the DACCON1
register.
The Digital-to-Analog Converter supplies a variable
voltage reference, ratiometric with the input source,
with 32 selectable output levels.
The DAC output voltage is determined by the following
equations:
The input of the DAC can be connected to:
• External VREF+ pin
• VDD supply voltage
The output of the DAC can be configured to supply a
reference voltage to the following:
• Comparator positive input
• ADC input channel
• DACOUT1 pin
• DACOUT2 pin
The Digital-to-Analog Converter (DAC) can be enabled
by setting the DACEN bit of the DACCON0 register.
EQUATION 16-1: DAC OUTPUT VOLTAGE
IF DACEN = 1
DACR4:0
VOUT = VSOURCE+ – VSOURCE- ----------------------------- + VSOURCE-
25
IF DACEN = 0 and DACLPS = 1 and DACR[4:0] = 11111
VOUT = VSOURCE +
IF DACEN = 0 and DACLPS = 0 and DACR[4:0] = 00000
VOUT = VSOURCE –
VSOURCE+ = VDD, VREF, or FVR BUFFER 2
VSOURCE- = VSS
16.2 Ratiometric Output Level
16.3 DAC Voltage Reference Output
The DAC output value is derived using a resistor ladder
with each end of the ladder tied to a positive and
negative voltage reference input source. If the voltage
of either input source fluctuates, a similar fluctuation will
result in the DAC output value.
The DAC voltage can be output to the DACOUT1 and
DACOUT2 pins by setting the respective DACOE1 and
DACOE2 pins of the DACCON0 register. Selecting the
DAC reference voltage for output on either DACOUTx
pin automatically overrides the digital output buffer and
digital input threshold detector functions of that pin.
Reading the DACOUTx pin when it has been config-
ured for DAC reference voltage output will always
return a ‘0’.
The value of the individual resistors within the ladder
can be found in Section 27.0 “Electrical
Specifications”.
Due to the limited current drive capability, a buffer must
be used on the DAC voltage reference output for
external connections to either DACOUTx pin.
Figure 16-2 shows an example buffering technique.
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
FIGURE 16-1:
DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM
Digital-to-Analog Converter (DAC)
VSOURCE+
VDD
DACR<4:0>
5
VREF+
R
R
DACPSS
DACEN
R
R
R
32
Steps
DAC
(To Comparator and
ADC Module)
R
R
R
DACOUT1
DACOE1
VSOURCE-
DACOUT2
DACOE2
FIGURE 16-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
PIC® MCU
DAC
Module
R
+
–
Buffered DAC Output
DACOUTX
Voltage
Reference
Output
Impedance
DS41615A-page 128
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
16.4 Operation During Sleep
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
16.5 Effects of a Reset
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
DACOUT pin.
• The DACR<4:0> range select bits are cleared.
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
16.6 DAC Control Registers
REGISTER 16-1: DACCON0: VOLTAGE REFERENCE CONTROL REGISTER 0
R/W-0/0
DACEN
U-0
—
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
U-0
—
U-0
—
DACOE1
DACOE2
DACPSS
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
DACEN: DAC Enable bit
1= DAC is enabled
0= DAC is disabled
bit 6
bit 5
Unimplemented: Read as ‘0’
DACOE1: DAC Voltage Output Enable bit
1= DAC voltage level is also an output on the DACOUT1 pin
0= DAC voltage level is disconnected from the DACOUT1 pin
bit 4
DACOE2: DAC Voltage Output Enable bit
1= DAC voltage level is also an output on the DACOUT2 pin
0= DAC voltage level is disconnected from the DACOUT2 pin
bit 3
bit 2
Unimplemented: Read as ‘0’
DACPSS: DAC Positive Source Select bit
1=
0=
VREF+ pin
VDD
bit 1-0
Unimplemented: Read as ‘0’
REGISTER 16-2: DACCON1: VOLTAGE REFERENCE CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
DACR<4:0>: DAC Voltage Output Select bits
TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC MODULE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CDAFVR<1:0>
FVRCON
DACCON0
DACCON1
Legend:
FVREN
DACEN
—
FVRRDY
TSEN
TSRNG
ADFVR1
—
ADFVR0
—
161
130
130
—
—
DACOE1 DACOE2
—
—
DACPSS
DACR<4:0>
— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.
DS41615A-page 130
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 17-1:
SINGLE COMPARATOR
17.0 COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
Comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of program execution. The analog
comparator module includes the following features:
VIN+
VIN-
+
Output
–
VIN-
VIN+
• Independent comparator control
• Programmable input selection
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
Output
• Wake-up from Sleep
• Programmable Speed/Power optimization
• PWM shutdown
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
• Programmable and fixed voltage reference
17.1
Comparator Overview
A single comparator is shown in Figure 17-1 along with
the relationship between the analog input levels and
the digital output. When the analog voltage at VIN+ is
less than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparators available for this device are located in
Table 17-1.
TABLE 17-1: COMPARATORAVAILABILITY
PER DEVICE
Device
C1
PIC12F1501
PIC12LF1501
●
●
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Preliminary
DS41615A-page 131
PIC12(L)F1501
FIGURE 17-2:
COMPARATOR MODULES SIMPLIFIED BLOCK DIAGRAM
CxNCH<2:0>
CxON(1)
3
CxINTP
Interrupt
det
0
C12IN0-
C12IN1-
C12IN2-
C12IN3-
Set CxIF
1
CxINTN
Interrupt
det
MUX
(2)
2
3
4
CXPOL
CxVN
CxVP
-
CXOUT
FVR Buffer2
To Data Bus
D
Q
Cx
MCXOUT
+
Q1
EN
0
CXIN+
CxHYS
MUX
1
DAC
(2)
CxSP
async_CxOUT
To CWG
CXOE
FVR Buffer2
2
3
CXSYNC
CxON
TRIS bit
CXOUT
CXPCH<1:0>
0
1
2
D
Q
(from Timer1)
T1CLK
SYNC_CXOUT
To Timer1,
CLCx, ADC
Note 1:
2:
When CxON = 0, the comparator will produce a ‘0’ at the output.
When CxON = 0, all multiplexer inputs are disconnected.
DS41615A-page 132
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
17.2.3
COMPARATOR OUTPUT POLARITY
17.2 Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Each comparator has 2 control registers: CMxCON0 and
CMxCON1.
The CMxCON0 registers (see Register 17-1) contain
Control and Status bits for the following:
• Enable
Table 17-2 shows the output state versus input
conditions, including polarity control.
• Output selection
• Output polarity
TABLE 17-2: COMPARATOR OUTPUT
STATE VS. INPUT
• Speed/Power selection
• Hysteresis enable
• Output synchronization
CONDITIONS
Input Condition
CxPOL
CxOUT
The CMxCON1 registers (see Register 17-2) contain
Control bits for the following:
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
0
0
1
1
0
1
1
0
• Interrupt enable
• Interrupt edge polarity
• Positive input channel selection
• Negative input channel selection
17.2.4
COMPARATOR SPEED/POWER
SELECTION
17.2.1
COMPARATOR ENABLE
The trade-off between speed or power can be opti-
mized during program execution with the CxSP control
bit. The default state for this bit is ‘1’ which selects the
normal speed mode. Device power consumption can
be optimized at the cost of slower comparator propaga-
tion delay by clearing the CxSP bit to ‘0’.
Setting the CxON bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxON bit
disables the comparator resulting in minimum current
consumption.
17.2.2
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register. In order to
make the output available for an external connection,
the following conditions must be true:
• CxOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CxON bit of the CMxCON0 register must be set
Note 1: The CxOE bit of the CMxCON0 register
overrides the PORT data latch. Setting
the CxON bit of the CMxCON0 register
has no impact on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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Preliminary
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PIC12(L)F1501
17.3 Comparator Hysteresis
17.5 Comparator Interrupt
A selectable amount of separation voltage can be
added to the input pins of each comparator to provide a
hysteresis function to the overall operation. Hysteresis
is enabled by setting the CxHYS bit of the CMxCON0
register.
An interrupt can be generated upon a change in the
output value of the comparator for each comparator, a
rising edge detector and a falling edge detector are
present.
When either edge detector is triggered and its associ-
ated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the Corresponding Interrupt
Flag bit (CxIF bit of the PIR2 register) will be set.
See Section 27.0 “Electrical Specifications” for
more information.
17.4 Timer1 Gate Operation
To enable the interrupt, you must set the following bits:
• CxON, CxPOL and CxSP bits of the CMxCON0
register
The output resulting from a comparator operation can
be used as a source for gate control of Timer1. See
Section 19.5 “Timer1 Gate” for more information.
This feature is useful for timing the duration or interval
of an analog event.
• CxIE bit of the PIE2 register
• CxINTP bit of the CMxCON1 register (for a rising
edge detection)
It is recommended that the comparator output be syn-
chronized to Timer1. This ensures that Timer1 does not
increment while a change in the comparator is occur-
ring.
• CxINTN bit of the CMxCON1 register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
17.4.1
COMPARATOR OUTPUT
SYNCHRONIZATION
The output from a comparator can be synchronized
with Timer1 by setting the CxSYNC bit of the
CMxCON0 register.
Note:
Although a comparator is disabled, an
interrupt can be generated by changing
the output polarity with the CxPOL bit of
the CMxCON0 register, or by switching
the comparator on or off with the CxON bit
of the CMxCON0 register.
Once enabled, the comparator output is latched on the
falling edge of the Timer1 source clock. If a prescaler is
used with Timer1, the comparator output is latched after
the prescaling function. To prevent a race condition, the
comparator output is latched on the falling edge of the
Timer1 clock source and Timer1 increments on the
rising edge of its clock source. See the Comparator
Block Diagram (Figure 17-2) and the Timer1 Block
Diagram (Figure 19-1) for more information.
17.6 Comparator Positive Input
Selection
Configuring the CxPCH<1:0> bits of the CMxCON1
register directs an internal voltage reference or an
analog pin to the non-inverting input of the comparator:
• CxIN+ analog pin
• DAC
• FVR (Fixed Voltage Reference)
• VSS (Ground)
See Section 13.0 “Fixed Voltage Reference (FVR)”
for more information on the Fixed Voltage Reference
module.
See Section 16.0 “Digital-to-Analog Converter
(DAC) Module” for more information on the DAC input
signal.
Any time the comparator is disabled (CxON = 0), all
comparator inputs are disabled.
DS41615A-page 134
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
17.7 Comparator Negative Input
Selection
17.9 Analog Input Connection
Considerations
The CxNCH<1:0> bits of the CMxCON0 register direct
one of the input sources to the comparator inverting
input.
A simplified circuit for an analog input is shown in
Figure 17-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is for-
ward biased and a latch-up may occur.
Note:
To use CxIN+ and CxINx- pins as analog
input, the appropriate bits must be set in
the ANSEL register and the correspond-
ing TRIS bits must also be set to disable
the output drivers.
A maximum source impedance of 10 k is recommended
for the analog sources. Also, any external component
connected to an analog input pin, such as a capacitor or
a Zener diode, should have very little leakage current to
minimize inaccuracies introduced.
17.8 Comparator Response Time
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the comparator
differs from the settling time of the voltage reference.
Therefore, both of these times must be considered when
determining the total response time to a comparator
input change. See the Comparator and Voltage Refer-
ence Specifications in Section 27.0 “Electrical Specifi-
cations” for more details.
Note 1: When reading a PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 135
PIC12(L)F1501
FIGURE 17-3:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
VT 0.6V
RIC
Rs < 10K
To Comparator
(1)
ILEAKAGE
CPIN
5 pF
VA
VT 0.6V
Vss
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
Note 1: See Section 27.0 “Electrical Specifications”.
DS41615A-page 136
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 17-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0
R/W-0/0
CxON
R-0/0
R/W-0/0
CxOE
R/W-0/0
CxPOL
U-0
—
R/W-1/1
CxSP
R/W-0/0
CxHYS
R/W-0/0
CxSYNC
CxOUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
CxON: Comparator Enable bit
1= Comparator is enabled and consumes no active power
0= Comparator is disabled
CxOUT: Comparator Output bit
If CxPOL = 1 (inverted polarity):
1= CxVP < CxVN
0= CxVP > CxVN
If CxPOL = 0 (non-inverted polarity):
1= CxVP > CxVN
0= CxVP < CxVN
bit 5
bit 4
CxOE: Comparator Output Enable bit
1= CxOUT is present on the CxOUT pin. Requires that the associated TRIS bit be cleared to actually
drive the pin. Not affected by CxON.
0= CxOUT is internal only
CxPOL: Comparator Output Polarity Select bit
1= Comparator output is inverted
0= Comparator output is not inverted
bit 3
bit 2
Unimplemented: Read as ‘0’
CxSP: Comparator Speed/Power Select bit
1= Comparator operates in normal power, higher speed mode
0= Comparator operates in low-power, low-speed mode
bit 1
bit 0
CxHYS: Comparator Hysteresis Enable bit
1= Comparator hysteresis enabled
0= Comparator hysteresis disabled
CxSYNC: Comparator Output Synchronous Mode bit
1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.
Output updated on the falling edge of Timer1 clock source.
0= Comparator output to Timer1 and I/O pin is asynchronous.
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
REGISTER 17-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1
R/W-0/0
CxINTP
R/W-0/0
CxINTN
R/W-0/0
R/W-0/0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
CxPCH<1:0>
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
CxINTP: Comparator Interrupt on Positive Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit
0= No interrupt flag will be set on a positive going edge of the CxOUT bit
bit 6
CxINTN: Comparator Interrupt on Negative Going Edge Enable bits
1= The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit
0= No interrupt flag will be set on a negative going edge of the CxOUT bit
bit 5-4
CxPCH<1:0>: Comparator Positive Input Channel Select bits
11= CxVP connects to VSS
10= CxVP connects to FVR Voltage Reference
01= CxVP connects to DAC Voltage Reference
00= CxVP connects to CxIN+ pin
bit 3
Unimplemented: Read as ‘0’
bit 2-0
CxNCH<2:0>: Comparator Negative Input Channel Select bits
111= Reserved
110= Reserved
101= Reserved
100= CxVN connects to FVR Voltage reference
011= CxVN connects to C12IN3- pin
010= CxVN connects to C12IN2- pin
001= CxVN connects to C12IN1- pin
000= CxVN connects to C12IN0- pin
REGISTER 17-3: CMOUT: COMPARATOR OUTPUT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0/0
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-1
bit 0
Unimplemented: Read as ‘0’
MC1OUT: Mirror Copy of C1OUT bit
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PIC12(L)F1501
TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
CM1CON0
CM1CON1
CMOUT
DACCON0
DACCON1
FVRCON
INTCON
PIE2
—
C1ON
C1NTP
—
—
C1OUT
C1INTN
—
—
ANSA4
C1POL
—
—
—
—
—
ANSA2
C1SP
ANSA1
C1HYS
C1NCH<2:0>
—
ANSA0
103
137
138
138
130
130
110
66
C1OE
C1SYNC
C1PCH<1:0>
—
DACOE1
—
—
—
MC1OUT
—
DACEN
—
—
DACOE2
DACPSS
DACR<4:0>
—
—
FVREN
GIE
—
FVRRDY
PEIE
—
TSEN
TMR0IE
C1IE
TSRNG
INTE
—
CDAFVR<1:0>
ADFVR<1:0>
IOCIE
—
TMR0IF
NCO1IE
NCO1IF
RA2
INTF
—
IOCIF
—
68
—
C1IF
—
PIR2
—
—
—
—
71
PORTA
RA5
RA4
RA3
RA1
RA0
102
103
102
—
—
—
—
LATA
—
LATA5
TRISA5
LATA4
TRISA4
—
LATA2
LATA1
TRISA1
LATA0
TRISA0
(1)
TRISA
—
TRISA2
—
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.
Note 1: Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 139
PIC12(L)F1501
NOTES:
DS41615A-page 140
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
18.1.2
8-BIT COUNTER MODE
18.0 TIMER0 MODULE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
The Timer0 module is an 8-bit timer/counter with the
following features:
8-Bit Counter mode using the T0CKI pin is selected by
setting the TMR0CS bit in the OPTION_REG register to
‘1’.
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
The rising or falling transition of the incrementing edge
for either input source is determined by the TMR0SE bit
in the OPTION_REG register.
• TMR0 can be used to gate Timer1
Figure 18-1 is a block diagram of the Timer0 module.
18.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
18.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 18-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
1
8
T0CKI
1
Sync
TMR0
2 TCY
0
Set Flag bit TMR0IF
on Overflow
PSA
TMR0SE
TMR0CS
8-bit
Prescaler
Overflow to Timer1
8
PS<2:0>
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 141
PIC12(L)F1501
18.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by set-
ting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
18.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
18.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 27.0 “Electrical
Specifications”.
18.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
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PIC12(L)F1501
18.2 Option and Timer0 Control Register
REGISTER 18-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
R/W-1/1
INTEDG
R/W-1/1
R/W-1/1
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
TMR0CS
TMR0SE
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-Up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is not assigned to the Timer0 module
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
ADCON2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRIGSEL<3:0>
PEIE TMR0IE
—
—
—
INTF
—
121
66
INTCON
OPTION_REG
TMR0
GIE
INTE
IOCIE
PSA
TMR0IF
IOCIF
WPUEN
INTEDG TMR0CS TMR0SE
PS<2:0>
143
141*
102
Holding Register for the 8-bit Timer0 Count
TRISA5 TRISA4
(1)
TRISA
—
—
—
TRISA2
TRISA1
TRISA0
Legend:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
*
Page provides register information.
Note 1: Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 143
PIC12(L)F1501
NOTES:
DS41615A-page 144
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
• Gate Single-Pulse mode
19.0 TIMER1 MODULE WITH GATE
CONTROL
• Gate Value Status
• Gate Event Interrupt
The Timer1 module is a 16-bit timer/counter with the
following features:
Figure 19-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Special Event Trigger
• Selectable Gate Source Polarity
• Gate Toggle mode
FIGURE 19-1:
TIMER1 BLOCK DIAGRAM
T1GSS<1:0>
00
T1G
T1GSPM
From Timer0
Overflow
01
0
t1g_in
Data Bus
T1GVAL
0
D
Q
10
11
sync_C1OUT
Reserved
Single Pulse
Acq. Control
RD
1
T1GCON
Q1 EN
1
D
Q
Q
Interrupt
Set
TMR1GIF
T1GGO/DONE
CK
TMR1ON
T1GTM
det
R
T1GPOL
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
EN
D
Synchronized
Clock Input
0
To ADC Auto-Conversion
T1CLK
TMR1H
TMR1L
Q
1
TMR1CS<1:0>
LFINTOSC
T1SYNC
11
10
Synchronize(3)
det
Prescaler
1, 2, 4, 8
(1)
T1CKI
2
T1CKPS<1:0>
FOSC
Internal
Clock
01
00
FOSC/2
Internal
Clock
Sleep input
FOSC/4
Internal
Clock
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
19.1 Timer1 Operation
19.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> bits of the T1CON register are used
to select the clock source for Timer1. Table 19-2
displays the clock source selections.
19.2.1
INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 19-1 displays the Timer1 enable
selections.
TABLE 19-1: TIMER1 ENABLE
SELECTIONS
The following asynchronous sources may be used:
• Asynchronous event on the T1G pin to Timer1
gate
Timer1
Operation
TMR1ON
TMR1GE
19.2.2
EXTERNAL CLOCK SOURCE
0
0
1
1
0
1
0
1
Off
Off
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
Always On
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. The
external clock source can be synchronized to the
microcontroller system clock or it can run
asynchronously.
Count Enabled
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 19-2: CLOCK SOURCE SELECTIONS
TMR1CS<1:0>
T1OSCEN
Clock Source
11
10
01
00
x
0
x
x
LFINTOSC
External Clocking on T1CKI Pin
System Clock (FOSC)
Instruction Clock (FOSC/4)
DS41615A-page 146
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2011 Microchip Technology Inc.
PIC12(L)F1501
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 19-3 for timing details.
19.3 Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
TABLE 19-3: TIMER1 GATE ENABLE
SELECTIONS
19.4 Timer1 Operation in
T1CLK T1GPOL
T1G
Timer1 Operation
Asynchronous Counter Mode
0
0
1
1
0
1
0
1
Counts
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 19.4.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Holds Count
Holds Count
Counts
19.5.2
TIMER1 GATE SOURCE
SELECTION
Timer1 gate source selections are shown in Table 19-4.
Source selection is controlled by the T1GSS<1:0> bits
of the T1GCON register. The polarity for each available
source is also selectable. Polarity selection is controlled
by the T1GPOL bit of the T1GCON register.
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 19-4: TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
00
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
19.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
10
11
Comparator 1 Output sync_C1OUT
(optionally synchronized comparator output)
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
Reserved
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
19.5 Timer1 Gate
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 gate can also be driven by multiple selectable
sources.
19.5.1
TIMER1 GATE ENABLE
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 147
PIC12(L)F1501
19.5.2.1
T1G Pin Gate Operation
19.5.5
TIMER1 GATE VALUE STATUS
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
gate circuitry.
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
19.5.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
a
19.5.6
TIMER1 GATE EVENT INTERRUPT
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
19.5.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the sig-
nal. See Figure 19-4 for timing details.
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
19.5.4
TIMER1 GATE SINGLE-PULSE
MODE
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 19-5 for timing details.
If the Single Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1 gate
source to be measured. See Figure 19-6 for timing
details.
DS41615A-page 148
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2011 Microchip Technology Inc.
PIC12(L)F1501
19.7.1
ALTERNATE PIN LOCATIONS
19.6 Timer1 Interrupt
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
19.7 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
• TMR1CS bits of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
Timer1 oscillator will continue to operate in Sleep
regardless of the T1SYNC bit setting.
FIGURE 19-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 149
PIC12(L)F1501
FIGURE 19-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
N + 3
N + 4
FIGURE 19-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
DS41615A-page 150
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 19-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
2011 Microchip Technology Inc.
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PIC12(L)F1501
FIGURE 19-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
DS41615A-page 152
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
19.8 Timer1 Control Registers
REGISTER 19-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
U-0
—
R/W-0/u
T1SYNC
U-0
—
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
TMR1CS<1:0>: Timer1 Clock Source Select bits
11=Timer1 clock source is LFINTOSC
10=Timer1 clock source is T1CKI pin (on rising edge)
01=Timer1 clock source is system clock (FOSC)
00=Timer1 clock source is instruction clock (FOSC/4)
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
Unimplemented: Read as ‘0’
T1SYNC: Timer1 Synchronization Control bit
1= Do not synchronize asynchronous clock input
0= Synchronize asynchronous clock input with system clock (FOSC)
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1 and clears Timer1 gate flip-flop
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 153
PIC12(L)F1501
REGISTER 19-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
T1GPOL
R/W-0/u
T1GTM
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
R/W-0/u
TMR1GE
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 counting is controlled by the Timer1 gate function
0= Timer1 counts regardless of Timer1 gate function
bit 6
bit 5
T1GPOL: Timer1 Gate Polarity bit
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
T1GTM: Timer1 Gate Toggle Mode bit
1= Timer1 Gate Toggle mode is enabled
0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
bit 3
bit 2
bit 0
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1= Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate
0= Timer1 Gate Single-Pulse mode is disabled
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0= Timer1 gate single-pulse acquisition has completed or has not been started
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
T1GSS<1:0>: Timer1 Gate Source Select bits
11= Reserved
10= Comparator 1 optionally synchronized output (sync_C1OUT)
01= Timer0 overflow output
00= Timer1 gate pin
DS41615A-page 154
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
19.8.1
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
TABLE 19-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
APFCON
—
—
—
—
ANSA4
—
—
ANSA2
—
ANSA1
ANSA0
103
100
T1GSEL
CLC1SEL NCO1SEL
CWG1BSEL CWG1ASEL
INTCON
PIE1
GIE
PEIE
ADIE
ADIF
TMR0IE
—
INTE
—
IOCIE
—
TMR0IF
INTF
IOCIF
TMR1IE
TMR1IF
66
67
TMR1GIE
TMR1GIF
—
—
TMR2IE
TMR2IF
PIR1
—
—
—
70
TMR1H
TMR1L
TRISA
T1CON
T1GCON
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
149*
149*
102
153
154
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
(1)
—
—
TRISA5
TRISA4
—
TRISA2
T1SYNC
T1GVAL
TRISA1
—
TRISA0
TMR1CS<1:0>
T1CKPS<1:0>
—
TMR1ON
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GSS<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
*
Note 1:
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 155
PIC12(L)F1501
NOTES:
DS41615A-page 156
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
20.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
See Figure 20-1 for a block diagram of Timer2.
FIGURE 20-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
TMR2
Output
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS<1:0>
4
T2OUTPS<3:0>
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 157
PIC12(L)F1501
20.1 Timer2 Operation
20.3 Timer2 Output
The clock input to the Timer2 module is the system
instruction clock (FOSC/4).
The unscaled output of TMR2 is available primarily to
the PWMx module, where it is used as a time base for
operation.
TMR2 increments from 00h on each clock edge.
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
20.4 Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
counter/postscaler
(see
Section 20.2
“Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMR2 is not cleared when T2CON is
written.
20.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
DS41615A-page 158
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 20-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000= 1:1 Postscaler
0001= 1:2 Postscaler
0010= 1:3 Postscaler
0011= 1:4 Postscaler
0100= 1:5 Postscaler
0101= 1:6 Postscaler
0110= 1:7 Postscaler
0111= 1:8 Postscaler
1000= 1:9 Postscaler
1001= 1:10 Postscaler
1010= 1:11 Postscaler
1011= 1:12 Postscaler
1100= 1:13 Postscaler
1101= 1:14 Postscaler
1110= 1:15 Postscaler
1111= 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
10= Prescaler is 16
11= Prescaler is 64
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 159
PIC12(L)F1501
TABLE 20-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
PEIE
ADIE
ADIF
TMR0IE
INTE
—
IOCIE
—
TMR0IF
INTF
IOCIF
66
67
TMR1GIE
TMR1GIF
—
—
—
—
TMR2IE
TMR2IF
TMR1IE
TMR1IF
PIR1
—
—
70
PR2
Timer2 Module Period Register
157*
165
165
165
165
159
157*
PWM1CON PWM1EN PWM1OE PWM1OUT PWM1POL
PWM2CON PWM2EN PWM2OE PWM2OUT PWM2POL
PWM3CON PWM3EN PWM3OE PWM3OUT PWM3POL
PWM4CON PWM4EN PWM4OE PWM4OUT PWM4POL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T2CON
TMR2
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
Holding Register for the 8-bit TMR2 Count
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
*
Page provides register information.
DS41615A-page 160
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section 21.1.9
“Setup for PWM Operation using PWMx Pins”.
21.0 PULSE-WIDTH MODULATION
(PWM) MODULE
The PWM module generates a Pulse-Width Modulated
signal determined by the duty cycle, period, and reso-
lution that are configured by the following registers:
FIGURE 21-1:
PWM OUTPUT
Period
• PR2
• T2CON
Pulse Width
TMR2 = PR2
• PWMxDCH
• PWMxDCL
• PWMxCON
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0
Figure 21-2 shows a simplified block diagram of PWM
operation.
Figure 21-1 shows a typical waveform of the PWM
signal.
FIGURE 21-2:
SIMPLIFIED PWM BLOCK DIAGRAM
PWMxDCL<7:6>
Duty Cycle registers
PWMxDCH
PWMxOUT
to other peripherals: CLC and CWG
Latched
(Not visible to user)
Output Enable (PWMxOE)
TRIS Control
PWMx
0
1
Q
Q
Comparator
R
S
TMR2 Module
(1)
Output Polarity (PWMxPOL)
TMR2
Comparator
PR2
Clear Timer,
PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by
the Timer2 prescaler to create a 10-bit time base.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 161
PIC12(L)F1501
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
21.1 PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
• TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
Note:
Clearing the PWMxOE bit will relinquish
control of the PWMx pin.
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
21.1.1
FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note:
The Timer2 postscaler has no effect on
the PWM operation.
21.1.4
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to the PWMxDCH and PWMxDCL register pair.
The PWMxDCH register contains the eight MSbs and
the PWMxDCL<7:6>, the two LSbs. The PWMxDCH
and PWMxDCL registers can be written to at any time.
Note:
The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than
the PWM output.
Equation 21-2 is used to calculate the PWM pulse
width.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) reg-
isters. When the value is greater than or equal to PR2,
the PWM output is never cleared (100% duty cycle).
Equation 21-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 21-2: PULSE WIDTH
Note:
The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are
updated when Timer2 matches PR2. Care
should be taken to update both registers
before the timer match occurs.
Pulse Width = PWMxDCH:PWMxDCL<7:6>
TOSC
(TMR2 Prescale Value)
Note: TOSC = 1/FOSC
21.1.2
PWM OUTPUT POLARITY
EQUATION 21-3: DUTY CYCLE RATIO
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = -----------------------------------------------------------------------------------
4PR2 + 1
21.1.3
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 21-1.
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to
1:1.
EQUATION 21-1: PWM PERIOD
PWM Period = PR2 + 1 4 TOSC
(TMR2 Prescale Value)
Note:
TOSC = 1/FOSC
DS41615A-page 162
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
21.1.5
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolu-
tion will result in 1024 discrete duty cycles, whereas an
8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 21-4.
EQUATION 21-4: PWM RESOLUTION
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 21-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 64)
PR2 Value
64
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 21-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 64)
PR2 Value
64
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
21.1.6
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
21.1.7
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock fre-
quency will result in changes to the PWM frequency.
Refer to Section 5.0 “Oscillator Module” for addi-
tional details.
21.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 163
PIC12(L)F1501
21.1.9
SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps should be taken when configuring
the module for PWM operation using the PWMx pins:
1. Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the PR2 register with the PWM period
value.
4. Clear the PWMxDCH register and bits <7:6> of
the PWMxDCL register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register. See Note below.
• Configure the T2CKPS bits of the T2CON register
with the Timer2 prescale value.
• Enable Timer2 by setting the TMR2ON bit of the
T2CON register.
6. Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See Note below.
7. Enable the PWMx pin output driver(s) by clear-
ing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
8. Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: In order to send a complete duty cycle
and period on the first PWM output, the
above steps must be followed in the order
given. If it is not critical to start with a
complete PWM signal, then move Step 8
to replace Step 4.
2: For operation with other peripherals only,
disable PWMx pin outputs.
DS41615A-page 164
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
21.2 PWM Register Definitions
REGISTER 21-1: PWMxCON: PWM CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
U-0
—
PWMxEN
PWMxOE
PWMxOUT PWMxPOL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
PWMxEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
PWMxOE: PWM Module Output Enable bit
1= Output to PWMx pin is enabled
0= Output to PWMx pin is disabled
bit 5
bit 4
PWMxOUT: PWM Module Output Value bit
PWMxPOL: PWMx Output Polarity Select bit
1= PWM output is active-low
0= PWM output is active-high
bit 3-0
Unimplemented: Read as ‘0’
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 165
PIC12(L)F1501
REGISTER 21-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
PWMxDCH<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL register.
REGISTER 21-3: PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
R/W-x/u
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
PWMxDCL<7:6>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH register.
Unimplemented: Read as ‘0’
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PR2
Timer2 module Period Register
157*
165
166
166
166
166
166
165
166
166
165
166
166
159
157*
PWM1CON
PWM1DCH
PWM1DCL
PWM2CON
PWM2DCH
PWM2DCL
PWM3CON
PWM3DCH
PWM3DCL
PWM4CON
PWM4DCH
PWM4DCL
T2CON
PWM1EN
PWM1OE
PWM1OUT
PWM1POL
—
—
—
—
PWM1DCH<7:0>
PWM1DCL<7:6>
—
—
—
—
—
—
—
—
—
—
PWM2EN
PWM2OE
PWM2OUT
PWM2POL
PWM2DCH<7:0>
PWM2DCL<7:6>
—
—
—
—
—
—
—
—
—
—
PWM3EN
PWM3OE
PWM4OE
PWM3OUT
PWM3POL
PWM3DCH<7:0>
PWM3DCL<7:6>
—
—
—
—
—
—
—
—
—
—
PWM4EN
PWM4OUT
PWM4POL
PWM4DCH<7:0>
PWM4DCL<7:6>
—
—
—
—
—
—
—
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
TMR2
Timer2 module Register
—(1)
TRISA
—
—
TRISA5
TRISA4
TRISA2
TRISA1
TRISA0
102
Legend:
-= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.
*
Page provides register information.
Note 1:
Unimplemented, read as ‘1’.
DS41615A-page 166
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Refer to Figure 22-1 for a simplified diagram showing
signal flow through the CLCx.
22.0 CONFIGURABLE LOGIC CELL
(CLC)
Possible configurations include:
The Configurable Logic Cell (CLC) provides program-
mable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 16
input signals and through the use of configurable gates
reduces the 16 inputs to four logic lines that drive one
of eight selectable single-output logic functions.
•
Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
Input sources are a combination of the following:
• I/O pins
- OR-XNOR
• Internal clocks
• Peripherals
• Register bits
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
The output can be directed internally to peripherals and
to an output pin.
FIGURE 22-1:
CLCx SIMPLIFIED BLOCK DIAGRAM
D
Q
LCxOUT
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
MLCxOUT
Q1
LE
LCxOE
LCxEN
lcxq
lcxg1
lcxg2
lcxg3
lcxg4
TRIS Control
CLCx
Logic
lcx_out
Function
LCxPOL
Interrupt
det
LCxINTP
LCxINTN
Interrupt
det
LCxMODE<2:0>
sets
CLCxIF
flag
Note: See Figure 22-2.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 167
PIC12(L)F1501
22.1.1
DATA SELECTION
22.1 CLCx Setup
There are 16 signals available as inputs to the configu-
rable logic. Four 8-input multiplexers are used to select
the inputs to pass on to the next stage. The 16 inputs to
the multiplexers are arranged in groups of four. Each
group is available to two of the four multiplexers, in
each case, paired with a different group. This arrange-
ment makes possible selection of up to two from a
group without precluding a selection from another
group.
Programming the CLCx module is performed by config-
uring the 4 stages in the logic signal flow. The 4 stages
are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is setup at run time by writing to the corre-
sponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 22-3 and Register 22-4,
respectively).
Data inputs are selected with CLCxSEL0 and
CLCxSEL1 registers (Register 22-3 and Register 22-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 22-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 22-1 correlates the generic input name to the
actual signal for each CLC module. The columns labeled
lcxd1 through lcxd4 indicate the MUX output for the
selected data input. D1S through D4S are abbreviations
for the MUX select input codes: LCxD1S<2:0> through
LCxD4S<2:0>, respectively. Selecting a data input in a
column excludes all other inputs in that column.
Note:
Data selections are undefined at power-up.
TABLE 22-1: CLCx DATA INPUT SELECTION
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
Data Input
CLC 1
CLC1IN0
CLC 2
CLC2IN0
CLCxIN[0]
000
001
010
011
100
101
110
111
—
—
—
—
—
100
101
110
111
—
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
CLC1IN1
sync_C1OUT
Reserved
FOSC
CLC2IN1
sync_C1OUT
Reserved
FOSC
—
—
—
—
000
001
010
011
100
101
110
111
—
—
—
—
TMR0IF
TMR0IF
—
—
TMR1IF
TMR1IF
—
—
TMR2 = PR2
lc1_out
TMR2 = PR2
lc1_out
000
001
010
011
100
101
110
111
—
—
—
lc2_out
lc2_out
—
—
Reserved
Reserved
NCO1OUT
HFINTOSC
PWM3OUT
PWM4OUT
Reserved
Reserved
LFINTOSC
ADFRC
—
—
—
000
001
010
011
—
—
—
—
PWM1OUT
PWM2OUT
—
—
DS41615A-page 168
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Data gating is indicated in the right side of Figure 22-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that
gate.
22.1.2
DATA GATING
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
22.1.3
LOGIC FUNCTION
Note:
Data gating is undefined at power-up.
There are 8 available logic functions including:
The gate stage is more than just signal direction. The
gate can be configured to direct each input signal as
inverted or non-inverted data. Directed signals are
ANDed together in each gate. The output of each gate
can be inverted before going on to the logic function
stage.
• AND-OR
• OR-XOR
• AND
• S-R Latch
• D Flip-Flop with Set and Reset
• D Flip-Flop with Reset
• J-K Flip-Flop with Reset
• Transparent Latch with Set and Reset
The gating is in essence
a
1-to-4 input
AND/NAND/OR/NOR gate. When every input is
inverted and the output is inverted, the gate is an OR of
all enabled data inputs. When the inputs and output are
not inverted, the gate is an AND or all enabled inputs.
Logic functions are shown in Figure 22-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage.
The output is fed to the inversion stage and from there
to other peripherals, an output pin, and back to the
CLCx itself.
Table 22-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If
no inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
22.1.4
OUTPUT POLARITY
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON reg-
ister inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
TABLE 22-2: DATA GATING LOGIC
CLCxGLS0
LCxG1POL
Gate Logic
0x55
0x55
0xAA
0xAA
0x00
0x00
1
0
1
0
0
1
AND
NAND
NOR
OR
Logic 0
Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses).
If the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select reg-
isters as follows:
• Gate 1: CLCxGLS0 (Register 22-5)
• Gate 2: CLCxGLS1 (Register 22-6)
• Gate 3: CLCxGLS2 (Register 22-7)
• Gate 4: CLCxGLS3 (Register 22-8)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 169
PIC12(L)F1501
The CLCxIF bit of the associated PIR registers, must
be cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
22.1.5
CLCx SETUP STEPS
The following steps should be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 and
CLCxSEL1 registers (See Table 22-1).
• Clear any associated ANSEL bits.
22.3 Output Mirror Copies
Mirror copies of all LCxCON output bits are contained
in the CLCxDATA register. Reading this register reads
the outputs of all CLCs simultaneously. This prevents
any reading skew introduced by testing or reading the
CLCxOUT bits in the individual CLCxCON registers.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the
LCxPOLy bits of the CLCxPOL register.
22.4 Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
• Select the desired logic function with the
LCxMODE<2:0> bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate out-
put polarity step).
22.5 Operation During Sleep
The CLC module operates independently from the
system clock and will continue to run during Sleep,
provided that the input sources selected remain active.
• If driving the CLCx pin, set the LCxOE bit of the
CLCxCON register and also clear the TRIS bit
corresponding to that output.
The HFINTOSC remains active during Sleep when the
CLC module is enabled and the HFINTOSC is
selected as an input source, regardless of the system
clock source selected.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and as a CLC input
source, when the CLC is enabled, the CPU will go idle
during Sleep, but the CLC will continue to operate and
the HFINTOSC will remain active.
- Set the LCxINTN bit in the CLCxCON
register or falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
This will have a direct effect on the Sleep mode current.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
22.6 Alternate Pin Locations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
22.2 CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR registers will be set
when either edge detector is triggered and its associated
enable bit is set. The LCxINTP enables rising edge inter-
rupts and the LCxINTN bit enables falling edge inter-
rupts. Both are located in the CLCxCON register.
To fully enable the interrupt, set the following bits:
• LCxON bit of the CLCxCON register
• CLCxIE bit of the associated PIE registers
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a fall-
ing edge detection)
• PEIE and GIE bits of the INTCON register
DS41615A-page 170
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 22-2:
INPUT DATA SELECTION AND GATING
Data Selection
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
000
Data GATE 1
lcxd1T
lcxd1N
LCxD1G1T
LCxD1G1N
LCxD2G1T
LCxD2G1N
LCxD3G1T
LCxD3G1N
LCxD4G1T
LCxD4G1N
111
000
LCxD1S<2:0>
lcxg1
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
CLCxIN[8]
CLCxIN[9]
CLCxIN[10]
CLCxIN[11]
LCxG1POL
lcxd2T
lcxd2N
111
000
LCxD2S<2:0>
LCxD3S<2:0>
LCxD4S<2:0>
CLCxIN[8]
CLCxIN[9]
Data GATE 2
lcxg2
CLCxIN[10]
CLCxIN[11]
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
lcxd3T
lcxd3N
(Same as Data GATE 1)
Data GATE 3
111
000
lcxg3
lcxg4
(Same as Data GATE 1)
Data GATE 4
CLCxIN[12]
CLCxIN[13]
CLCxIN[14]
CLCxIN[15]
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
(Same as Data GATE 1)
lcxd4T
lcxd4N
111
Note:
All controls are undefined at power-up.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 171
PIC12(L)F1501
FIGURE 22-3:
PROGRAMMABLE LOGIC FUNCTIONS
AND - OR
OR - XOR
lcxg1
lcxg2
lcxg3
lcxg4
lcxg1
lcxg2
lcxg3
lcxg4
lcxq
lcxq
LCxMODE<2:0>= 000
LCxMODE<2:0>= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxq
S
R
Q
lcxg2
lcxg3
lcxg4
lcxg2
lcxg3
lcxg4
lcxq
LCxMODE<2:0>= 010
LCxMODE<2:0>= 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg4
lcxg2
S
lcxq
D
Q
lcxg2
lcxq
D
Q
lcxg1
lcxg3
lcxg1
lcxg3
R
R
LCxMODE<2:0>= 100
LCxMODE<2:0>= 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
lcxg2
lcxg1
lcxg4
lcxq
J
Q
S
lcxg2
lcxq
D
Q
K
R
LE
lcxg1
lcxg3
R
lcxg3
LCxMODE<2:0>= 110
LCxMODE<2:0>= 111
DS41615A-page 172
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
22.7 CLCx Control Registers
REGISTER 22-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
LCxEN
R/W-0/0
LCxOE
R-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
LCxOUT
LCxINTP
LCxINTN
LCxMODE<2:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
LCxEN: Configurable Logic Cell Enable bit
1= Configurable logic cell is enabled and mixing input signals
0= Configurable logic cell is disabled and has logic zero output
LCxOE: Configurable Logic Cell Output Enable bit
1= Configurable logic cell port pin output enabled
0= Configurable logic cell port pin output disabled
bit 5
bit 4
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1= CLCxIF will be set when a rising edge occurs on lcx_out
0= CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1= CLCxIF will be set when a falling edge occurs on lcx_out
0= CLCxIF will not be set
bit 2-0
LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits
111= Cell is 1-input transparent latch with S and R
110= Cell is J-K flip-flop with R
101= Cell is 2-input D flip-flop with R
100= Cell is 1-input D flip-flop with S and R
011= Cell is S-R latch
010= Cell is 4-input AND
001= Cell is OR-XOR
000= Cell is AND-OR
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 173
PIC12(L)F1501
REGISTER 22-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-0/0
LCxPOL
U-0
—
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4POL LCxG3POL
LCxG2POL LCxG1POL
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
LCxPOL: LCOUT Polarity Control bit
1= The output of the logic cell is inverted
0= The output of the logic cell is not inverted
bit 6-4
bit 3
Unimplemented: Read as ‘0’
LCxG4POL: Gate 4 Output Polarity Control bit
1= The output of gate 4 is inverted when applied to the logic cell
0= The output of gate 4 is not inverted
bit 2
bit 1
bit 0
LCxG3POL: Gate 3 Output Polarity Control bit
1= The output of gate 3 is inverted when applied to the logic cell
0= The output of gate 3 is not inverted
LCxG2POL: Gate 2 Output Polarity Control bit
1= The output of gate 2 is inverted when applied to the logic cell
0= The output of gate 2 is not inverted
LCxG1POL: Gate 1 Output Polarity Control bit
1= The output of gate 1 is inverted when applied to the logic cell
0= The output of gate 1 is not inverted
DS41615A-page 174
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 22-3: CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
LCxD2S<2:0>
LCxD1S<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD2S<2:0>: Input Data 2 Selection Control bits(1)
111= CLCxIN[11] is selected for lcxd2
110= CLCxIN[10] is selected for lcxd2
101= CLCxIN[9] is selected for lcxd2
100= CLCxIN[8] is selected for lcxd2
011= CLCxIN[7] is selected for lcxd2
010= CLCxIN[6] is selected for lcxd2
001= CLCxIN[5] is selected for lcxd2
000= CLCxIN[4] is selected for lcxd2
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD1S<2:0>: Input Data 1 Selection Control bits(1)
111= CLCxIN[7] is selected for lcxd1
110= CLCxIN[6] is selected for lcxd1
101= CLCxIN[5] is selected for lcxd1
100= CLCxIN[4] is selected for lcxd1
011= CLCxIN[3] is selected for lcxd1
010= CLCxIN[2] is selected for lcxd1
001= CLCxIN[1] is selected for lcxd1
000= CLCxIN[0] is selected for lcxd1
Note 1: See Table 22-1 for signal names associated with inputs.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 175
PIC12(L)F1501
REGISTER 22-4: CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
LCxD4S<2:0>
LCxD3S<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD4S<2:0>: Input Data 4 Selection Control bits(1)
111= CLCxIN[3] is selected for lcxd4
110= CLCxIN[2] is selected for lcxd4
101= CLCxIN[1] is selected for lcxd4
100= CLCxIN[0] is selected for lcxd4
011= CLCxIN[15] is selected for lcxd4
010= CLCxIN[14] is selected for lcxd4
001= CLCxIN[13] is selected for lcxd4
000= CLCxIN[12] is selected for lcxd4
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD3S<2:0>: Input Data 3 Selection Control bits(1)
111= CLCxIN[15] is selected for lcxd3
110= CLCxIN[14] is selected for lcxd3
101= CLCxIN[13] is selected for lcxd3
100= CLCxIN[12] is selected for lcxd3
011= CLCxIN[11] is selected for lcxd3
010= CLCxIN[10] is selected for lcxd3
001= CLCxIN[9] is selected for lcxd3
000= CLCxIN[8] is selected for lcxd3
Note 1: See Table 22-1 for signal names associated with inputs.
DS41615A-page 176
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 22-5: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T
LCxG1D2N
LCxG1D1T LCxG1D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg1
0= lcxd4T is not gated into lcxg1
LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg1
0= lcxd4N is not gated into lcxg1
LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg1
0= lcxd3T is not gated into lcxg1
LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg1
0= lcxd3N is not gated into lcxg1
LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg1
0= lcxd2T is not gated into lcxg1
LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg1
0= lcxd2N is not gated into lcxg1
LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg1
0= lcxd1T is not gated into lcxg1
LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg1
0= lcxd1N is not gated into lcxg1
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 177
PIC12(L)F1501
REGISTER 22-6: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T
LCxG2D2N
LCxG2D1T LCxG2D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg2
0= lcxd4T is not gated into lcxg2
LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg2
0= lcxd4N is not gated into lcxg2
LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg2
0= lcxd3T is not gated into lcxg2
LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg2
0= lcxd3N is not gated into lcxg2
LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg2
0= lcxd2T is not gated into lcxg2
LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg2
0= lcxd2N is not gated into lcxg2
LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg2
0= lcxd1T is not gated into lcxg2
LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg2
0= lcxd1N is not gated into lcxg2
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Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 22-7: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T
LCxG3D2N
LCxG3D1T LCxG3D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg3
0= lcxd4T is not gated into lcxg3
LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg3
0= lcxd4N is not gated into lcxg3
LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg3
0= lcxd3T is not gated into lcxg3
LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg3
0= lcxd3N is not gated into lcxg3
LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg3
0= lcxd2T is not gated into lcxg3
LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg3
0= lcxd2N is not gated into lcxg3
LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg3
0= lcxd1T is not gated into lcxg3
LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg3
0= lcxd1N is not gated into lcxg3
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 179
PIC12(L)F1501
REGISTER 22-8: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T
LCxG4D2N
LCxG4D1T LCxG4D1N
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit
1= lcxd4T is gated into lcxg4
0= lcxd4T is not gated into lcxg4
LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1= lcxd4N is gated into lcxg4
0= lcxd4N is not gated into lcxg4
LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit
1= lcxd3T is gated into lcxg4
0= lcxd3T is not gated into lcxg4
LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1= lcxd3N is gated into lcxg4
0= lcxd3N is not gated into lcxg4
LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit
1= lcxd2T is gated into lcxg4
0= lcxd2T is not gated into lcxg4
LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1= lcxd2N is gated into lcxg4
0= lcxd2N is not gated into lcxg4
LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit
1= lcxd1T is gated into lcxg4
0= lcxd1T is not gated into lcxg4
LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1= lcxd1N is gated into lcxg4
0= lcxd1N is not gated into lcxg4
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Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 22-9: CLCDATA: CLC DATA OUTPUT
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
MLC2OUT
MLC1OUT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
MLC2OUT: Mirror copy of LC2OUT bit
MLC1OUT: Mirror copy of LC1OUT bit
bit 0
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 181
PIC12(L)F1501
TABLE 22-3: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Register
on Page
Name
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
T1GSEL
LC1INTN
LC2INTN
—
APFCON
CLC1CON
CLC2CON
CLCDATA
CLC1GLS0
CLC1GLS1
CLC1GLS2
CLC1GLS3
CLC1POL
CLC1SEL0
CLC1SEL1
CLC2GLS0
CLC2GLS1
CLC2GLS2
CLC2GLS3
CLC2POL
CLC2SEL0
CLC2SEL1
INTCON
CWG1BSEL CWG1ASEL
—
—
—
CLC1SEL
NCO1SEL
100
173
173
177
177
178
179
180
174
175
176
177
178
179
180
174
175
176
66
LC1EN
LC2EN
—
LC1OE
LC2OE
—
LC1OUT
LC2OUT
—
LC1INTP
LC2INTP
—
LC1MODE<2:0>
LC2MODE<2:0>
—
MLC2OUT MLC1OUT
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N
LC1POL
—
—
—
LC1G4POL LC1G3POL LC1G2POL LC1G1POL
—
—
LC1D2S<2:0>
LC1D4S<2:0>
—
—
LC1D1S<2:0>
LC1D3S<2:0>
LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N
LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N
LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N
LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N
LC2POL
—
—
—
LC2D2S<2:0>
LC2D4S<2:0>
TMR0IE
—
—
LC2G4POL LC2G3POL LC2G2POL LC2G1POL
—
—
LC2D1S<2:0>
LC2D3S<2:0>
INTF
—
GIE
—
PEIE
—
INTE
—
IOCIE
—
TMR0IF
—
IOCIF
PIE3
CLC2IE
CLC1IE
CLC1IF
TRISA0
69
PIR3
—
—
—
—
—
—
CLC2IF
72
(1)
TRISA
—
—
TRISA5
TRISA4
—
TRISA2
TRISA1
102
Legend:
Note 1:
— = unimplemented read as ‘0’,. Shaded cells are not used for CLC module.
Unimplemented, read as ‘1’.
DS41615A-page 182
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
23.0 NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCOx) module
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the resolution of division does not
vary with the divider value. The NCOx is most useful for
applications that require frequency accuracy and fine
resolution at a fixed duty cycle.
Features of the NCOx include:
• 16-bit increment function
• Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode
• Output pulse width control
• Multiple clock input sources
• Output polarity control
• Interrupt capability
Figure 23-1 is a simplified block diagram of the NCOx
module.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 183
PIC12(L)F1501
DS41615A-page 184
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
23.1.3
ADDER
23.1 NCOx OPERATION
The NCOx Adder is a full adder, which operates
independently from the system clock. The addition of
the previous result and the increment value replaces
the accumulator value on the rising edge of each input
clock.
The NCOx operates by repeatedly adding a fixed value
to an accumulator. Additions occur at the input clock
rate. The accumulator will overflow with a carry
periodically, which is the raw NCOx output. This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 23-1.
23.1.4
INCREMENT REGISTERS
The increment value is stored in two 8-bit registers
making up a 16-bit increment. In order of LSB to MSB
they are:
The NCOx output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCOx
output is then distributed internally to other peripherals
and optionally output to a pin. The accumulator overflow
also generates an interrupt.
• NCOxINCL
• NCOxINCH
The NCOx period changes in discrete steps to create an
average frequency. This output depends on the ability of
the receiving circuit (i.e., CWG or external resonant
converter circuitry) to average the NCOx output to
reduce uncertainty.
Both of the registers are readable and writeable. The
increment registers are double-buffered to allow for
value changes to be made without first disabling the
NCOx module.
The buffer loads are immediate when the module is dis-
abled. Writing to the NCOxINCH register first is neces-
sary because then the buffer is loaded synchronously
with the NCOx operation after the write is executed on
the NCOxINCL register.
23.1.1
NCOx CLOCK SOURCES
Clock sources available to the NCOx include:
• HFINTOSC
• FOSC
• LCxOUT
• CLKIN pin
Note: The increment buffer registers are not
user-accessible.
The NCOx clock source is selected by configuring the
NxCKS<2:0> bits in the NCOxCLK register.
23.1.2
ACCUMULATOR
The accumulator is a 20-bit register. Read and write
access to the accumulator is available through three
registers:
• NCOxACCL
• NCOxACCH
• NCOxACCU
EQUATION 23-1:
NCO Clock Frequency Increment Value
FOVERFLOW= ---------------------------------------------------------------------------------------------------------------
2n
n = Accumulator width in bits
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Preliminary
DS41615A-page 185
PIC12(L)F1501
23.2 FIXED DUTY CYCLE (FDC) MODE
In Fixed Duty Cycle (FDC) mode, every time the
accumulator overflows, the output is toggled. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure 23-2.
The FDC mode is selected by clearing the NxPFM bit
in the NCOxCON register.
23.3 PULSE FREQUENCY (PF) MODE
In Pulse Frequency (PF) mode, every time the accumu-
lator overflows, the output becomes active for one or
more clock periods. Once the clock period expires, the
output returns to an inactive state. This provides a
pulsed output.
The output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see Figure 23-2.
The value of the active and inactive states depends on
the polarity bit, NxPOL in the NCOxCON register.
The PF mode is selected by setting the NxPFM bit in
the NCOxCON register.
23.3.1
OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the active state of the out-
put can vary in width by multiple clock periods. Various
pulse widths are selected with the NxPWS<2:0> bits in
the NCOxCLK register.
When the selected pulse width is greater than the
accumulator overflow time frame, the output of the
NCOx operation is indeterminate.
23.4 OUTPUT POLARITY CONTROL
The last stage in the NCOx module is the output polar-
ity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the inter-
rupts are enabled will cause an interrupt for the result-
ing output transition.
The NCOx output can be used internally by source
code or other peripherals. Accomplish this by reading
the NxOUT (read-only) bit of the NCOxCON register.
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PIC12(L)F1501
DS41615A-page 187
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2011 Microchip Technology Inc.
PIC12(L)F1501
23.5 Interrupts
When the accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIRx register is set. To enable
the interrupt event, the following bits must be set:
• NxEN bit of the NCOxCON register
• NCOxIE bit of the PIEx register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
23.6 Effects of a Reset
All of the NCOx registers are cleared to zero as the
result of a Reset.
23.7 Operation In Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains
active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
23.8 Alternate Pin Locations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
DS41615A-page 188
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
23.9 NCOx Control Registers
REGISTER 23-1: NCOxCON: NCOx CONTROL REGISTER
R/W-0/0
NxEN
R/W-0/0
NxOE
R-0/0
R/W-0/0
NxPOL
U-0
—
U-0
—
U-0
—
R/W-0/0
NxPFM
NxOUT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
NxEN: NCOx Enable bit
1= NCOx module is enabled
0= NCOx module is disabled
NxOE: NCOx Output Enable bit
1= NCOx output pin is enabled
0= NCOx output pin is disabled
NxOUT: NCOx Output bit
1= NCOx output is high
0= NCOx output is low
NxPOL: NCOx Polarity bit
1= NCOx output signal is active-high
0= NCOx output signal is active-low
bit 3-1
bit 0
Unimplemented: Read as ‘0’.
NxPFM: NCOx Pulse Frequency Mode bit
1= NCOx operates in Pulse Frequency mode
0= NCOx operates in Fixed Duty Cycle mode
REGISTER 23-2: NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
NxPWS<2:0>
NxCKS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-5
NxPWS<2:0>: NCOx Output Pulse Width Select bits(1, 2)
111= 128 NCOx clock periods
110= 64 NCOx clock periods
101= 32 NCOx clock periods
100= 16 NCOx clock periods
011= 8 NCOx clock periods
010= 4 NCOx clock periods
001= 2 NCOx clock periods
000= 1 NCOx clock periods
bit 4-2
bit 1-0
Unimplemented: Read as ‘0’
NxCKS<1:0>: NCOx Clock Source Select bits
11= NCO1CLK
10= LC1OUT
01= FOSC
00= HFINTOSC (16 MHz)
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undeterminate.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 189
PIC12(L)F1501
REGISTER 23-3: NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
NCOxACC<7:0>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxACC<7:0>: NCOx Accumulator, low byte
REGISTER 23-4: NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
bit 7
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
bit 0
NCOxACC<15:8>
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxACC<15:8>: NCOx Accumulator, high byte
REGISTER 23-5: NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC<19:16>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NCOxACC<19:16>: NCOx Accumulator, upper byte
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Preliminary
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PIC12(L)F1501
REGISTER 23-6: NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCOxINC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxINC<7:0>: NCOx Increment, low byte
REGISTER 23-7: NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxINC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
NCOxINC<15:8>: NCOx Increment, high byte
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Preliminary
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PIC12(L)F1501
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCOx
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T1GSEL
IOCIE
APFCON
INTCON
CWG1BSEL CWG1ASEL
—
—
—
CLC1SEL NCO1SEL
100
66
GIE
PEIE
TMR0IE
INTE
TMR0IF
INTF
IOCIF
NCO1ACCH
NCO1ACCL
NCO1ACCU
NCO1CLK
NCO1CON
NCO1INCH
NCO1INCL
PIE2
NCO1ACC<15:8>
NCO1ACC<7:0>
190
190
190
189
189
191
191
68
—
NCO1ACC<19:16>
N1PWS<2:0>
N1OE
—
—
—
—
—
N1CKS<1:0>
N1EN
N1OUT
N1POL
—
N1PFM
NCO1INC<15:8>
NCO1INC<7:0>
—
—
—
—
—
—
C1IE
C1IF
—
—
—
—
NCO1IE
NCO1IF
TRISA2
—
—
—
—
PIR2
71
(1)
TRISA
TRISA5
TRISA4
—
TRISA1
TRISA0
102
Legend:
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends on condition. Shaded cells are not
used for ADC module.
Note 1: Unimplemented, read as ‘1’.
DS41615A-page 192
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
24.0 COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
The Complementary Waveform Generator (CWG) pro-
duces a complementary waveform with dead-band
delay from a selection of input sources.
The CWG module has the following features:
• Selectable dead-band clock source control
• Selectable input sources
• Output enable control
• Output polarity control
• Dead-band control with independent 6-bit rising
and falling edge dead-band counters
• Auto-shutdown control with:
- Selectable shutdown sources
- Auto-restart enable
- Auto-shutdown pin override control
2011 Microchip Technology Inc.
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PIC12(L)F1501
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 194
PIC12(L)F1501
FIGURE 24-2:
TYPICAL CWG OPERATION WITH PWM1 (NO AUTO-SHUTDOWN)
cwg_clock
PWM1
CWGxA
Rising Edge
Dead Band
Rising Edge Dead Band
Falling Edge Dead Band
Rising Edge D
Falling Edge Dead Band
CWGxB
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PIC12(L)F1501
24.4.2
POLARITY CONTROL
24.1 Fundamental Operation
The polarity of each CWG output can be selected
independently. When the output polarity bit is set, the
corresponding output is active high. Clearing the output
polarity bit configures the corresponding output as
active low. However, polarity does not affect the
override levels. Output polarity is selected with the
GxPOLA and GxPOLB bits of the CWGxCON0 register.
The CWG generates a two output complementary
waveform from one of four selectable input sources.
The off-to-on transition of each output can be delayed
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 24.5 “Dead-Band Control”. A typical
operating waveform, with dead band, generated from a
single input signal is shown in Figure 24-2.
24.5 Dead-Band Control
Dead-band control provides for non-overlapping output
signals to prevent shoot-through current in power
switches. The CWG contains two 6-bit dead-band
counters. One dead-band counter is used for the rising
edge of the input source control. The other is used for
the falling edge of the input source control.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in
Section 24.9 “Auto-shutdown Control”.
Dead band is timed by counting CWG clock periods
from zero up to the value in the rising or falling dead-
band counter registers. See CWGxDBR and
CWGxDBF registers (Register 24-4 and Register 24-5,
respectively).
24.2 Clock Source
The CWG module allows the following clock sources
to be selected:
• Fosc (system clock)
• HFINTOSC (16 MHz only)
24.6 Rising Edge Dead Band
The clock sources are selected using the G1CS0 bit of
the CWGxCON0 register (Register 24-1).
The rising edge dead band delays the turn-on of the
CWGxA output from when the CWGxB output is turned
off. The rising edge dead-band time starts when the
rising edge of the input source signal goes true. When
this happens, the CWGxB output is immediately turned
off and the rising edge dead-band delay time starts.
When the rising edge dead-band delay time is reached,
the CWGxA output is turned on.
24.3 Selectable Input Sources
The CWG can generate the complementary waveform
for the following input sources:
• async_C1OUT
• PWM1
• PWM2
• PWM3
• PWM4
The CWGxDBR register sets the duration of the dead-
band interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
• N1OUT
• LC1OUT
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero) indicates that no
dead band is present.
The input sources are selected using the GxIS<2:0>
bits in the CWGxCON1 register (Register 24-2).
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
24.4 Output Control
Immediately after the CWG module is enabled, the
complementary drive is configured with both CWGxA
and CWGxB drives cleared.
24.4.1
OUTPUT ENABLES
Each CWG output pin has individual output enable
control. Output enables are selected with the GxOEA
and GxOEB bits of the CWGxCON0 register. When an
output enable control is cleared, the module asserts no
control over the pin. When an output enable is set, the
override value or active PWM waveform is applied to
the pin per the port priority selection. The output pin
enables are dependent on the module enable bit,
GxEN. When GxEN is cleared, CWG output enables
and CWG drive levels have no effect.
DS41615A-page 196
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PIC12(L)F1501
24.7 Falling Edge Dead Band
The falling edge dead band delays the turn-on of the
CWGxB output from when the CWGxA output is turned
off. The falling edge dead-band time starts when the
falling edge of the input source goes true. When this
happens, the CWGxA output is immediately turned off
and the falling edge dead-band delay time starts. When
the falling edge dead-band delay time is reached, the
CWGxB output is turned on.
The CWGxDBF register sets the duration of the dead-
band interval on the falling edge of the input source sig-
nal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero) indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
Refer to Figure 24-3 and Figure 24-4 for examples.
24.8 Dead-Band Uncertainty
When the rising and falling edges of the input source
triggers the dead-band counters, the input may be asyn-
chronous. This will create some uncertainty in the dead-
band time delay. The maximum uncertainty is equal to
one CWG clock period. Refer to Equation 24-1 for more
detail.
2011 Microchip Technology Inc.
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PIC12(L)F1501
2011 Microchip Technology Inc.
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PIC12(L)F1501
EQUATION 24-1: DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------
Fcwg_clock
Example:
Fcwg_clock = 16 MHz
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------
Fcwg_clock
1
= ------------------
16 MHz
= 625ns
2011 Microchip Technology Inc.
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PIC12(L)F1501
24.9 Auto-shutdown Control
24.10 Operation During Sleep
Auto-shutdown is a method to immediately override the
CWG output levels with specific overrides that allow for
safe shutdown of the circuit. The shutdown state can be
either cleared automatically or held until cleared by
software.
The CWG module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock and input sources selected
remain active.
The HFINTOSC remains active during Sleep, provided
that the CWG module is enabled, the input source is
active, and the HFINTOSC is selected as the clock
source, regardless of the system clock source
selected.
24.9.1
SHUTDOWN
The shutdown state can be entered by either of the fol-
lowing two methods:
• Software generated
• External Input
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the CWG clock
source, when the CWG is enabled and the input
source is active, the CPU will go idle during Sleep, but
the CWG will continue to operate and the HFINTOSC
will remain active.
24.9.1.1
Software Generated Shutdown
Setting the GxASE bit of the CWGxCON2 register will
force the CWG into the shutdown state.
When auto-restart is disabled, the shutdown state will
persist as long as the GxASE bit is set.
This will have a direct effect on the Sleep mode current.
When auto-restart is enabled, the GxASE bit will clear
automatically and resume operation on the next rising
edge event. See Figure 24-6.
24.11 Alternate Pin Locations
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
24.9.1.2
External Input Source
External shutdown inputs provide the fastest way to
safely suspend CWG operation in the event of a Fault
condition. When any of the selected shutdown inputs
goes active, the CWG outputs will immediately go to
the selected override levels without software delay. Any
combination of two input sources can be selected to
cause a shutdown condition. The sources are:
• async_C1OUT
• LC2OUT
• CWG1FLT
Shutdown inputs are selected using the GxASDS0 and
GxASDS1 bits of the CWGxCON2 register.
(Register 24-3).
Note:
Shutdown inputs are level sensitive, not
edge sensitive. The shutdown state can-
not be cleared, except by disabling auto-
shutdown, as long as the shutdown input
level persists.
DS41615A-page 200
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2011 Microchip Technology Inc.
PIC12(L)F1501
24.12.1 PIN OVERRIDE LEVELS
24.12 Configuring the CWG
The levels driven to the output pins, while the shutdown
input is true, are controlled by the GxASDLA and
GxASDLB bits of the CWGxCON2 register
(Register 24-3). GxASDLA controls the CWG1A
override level and GxASDLB controls the CWG1B
override level. The control bit logic level corresponds to
the output logic drive level while in the shutdown state.
The polarity control does not apply to the override level.
The following steps illustrate how to properly configure
the CWG to ensure a synchronous start:
1. Ensure that the TRIS control bits corresponding
to CWGxA and CWGxB are set so that both are
configured as inputs.
2. Clear the GxEN bit, if not already cleared.
3. Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
24.12.2 AUTO-SHUTDOWN RESTART
4. Setup the following controls in CWGxCON2
auto-shutdown register:
After an auto-shutdown event has occurred, there are
two ways to have resume operation:
• Select desired shutdown source.
• Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
• Software controlled
• Auto-restart
The restart method is selected with the GxARSEN bit
of the CWGxCON2 register. Waveforms of software
controlled and automatic restarts are shown in
Figure 24-5 and Figure 24-6.
• Set the GxASE bit and clear the GxARSEN
bit.
5. Select the desired input source using the
CWGxCON1 register.
24.12.2.1 Software Controlled Restart
6. Configure the following controls in CWGxCON0
register:
When the GxARSEN bit of the CWGxCON2 register is
cleared, the CWG must be restarted after an auto-shut-
down event by software.
• Select desired clock source.
• Select the desired output polarities.
Clearing the shutdown state requires all selected shut-
down inputs to be low, otherwise the GxASE bit will
remain set. The overrides will remain in effect until the
first rising edge event after the GxASE bit is cleared.
The CWG will then resume operation.
• Set the output enables for the outputs to be
used.
7. Set the GxEN bit.
8. Clear TRIS control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
24.12.2.2 Auto-Restart
When the GxARSEN bit of the CWGxCON2 register is
set, the CWG will restart from the auto-shutdown state
automatically.
9. If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automati-
cally. Otherwise, clear the GxASE bit to start the
CWG.
The GxASE bit will clear automatically when all shut-
down sources go low. The overrides will remain in
effect until the first rising edge event after the GxASE
bit is cleared. The CWG will then resume operation.
2011 Microchip Technology Inc.
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DS41615A-page 201
PIC12(L)F1501
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 202
PIC12(L)F1501
24.13 CWG Control Registers
REGISTER 24-1: CWGxCON0: CWG CONTROL REGISTER 0
R/W-0/0
GxEN
R/W-0/0
GxOEB
R/W-0/0
GxOEA
R/W-0/0
GxPOLB
R/W-0/0
GxPOLA
U-0
—
U-0
—
R/W-0/0
GxCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
bit 3
GxEN: CWGx Enable bit
1= Module is enabled
0= Module is disabled
GxOEB: CWGxB Output Enable bit
1= CWGxB is available on appropriate I/O pin
0= CWGxB is not available on appropriate I/O pin
GxOEA: CWGxA Output Enable bit
1= CWGxA is available on appropriate I/O pin
0= CWGxA is not available on appropriate I/O pin
GxPOLB: CWGxB Output Polarity bit
1= Output is inverted polarity
0= Output is normal polarity
GxPOLA: CWGxA Output Polarity bit
1= Output is inverted polarity
0= Output is normal polarity
bit 2-1
bit 0
Unimplemented: Read as ‘0’
GxCS0: CWGx Clock Source bit
1= HFINTOSC
0= FOSC
2011 Microchip Technology Inc.
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DS41615A-page 203
PIC12(L)F1501
REGISTER 24-2: CWGxCON1: CWG CONTROL REGISTER 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
GxASDLB<1:0>
GxASDLA<1:0>
GxIS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
GxASDLB<1:0>: CWGx Shutdown State for CWGxB
When an auto shutdown event is present (GxASE = 1):
11= CWGxB pin is driven to ‘1’, regardless of the setting of the GxPOLB bit.
10= CWGxB pin is driven to ‘0’, regardless of the setting of the GxPOLB bit.
01= CWGxB pin is tri-stated
00= CWGxB pin is driven to it’s inactive state after the selected dead-band interval. GxPOLB still will
control the polarity of the output.
bit 5-4
GxASDLA<1:0>: CWGx Shutdown State for CWGxA
When an auto shutdown event is present (GxASE = 1):
11= CWGxA pin is driven to ‘1’, regardless of the setting of the GxPOLA bit.
10= CWGxA pin is driven to ‘0’, regardless of the setting of the GxPOLA bit.
01= CWGxA pin is tri-stated
00= CWGxA pin is driven to it’s inactive state after the selected dead-band interval. GxPOLA still will
control the polarity of the output.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
GxIS<2:0>: CWGx Input Source Select bits
111= LC1OUT
110= N1OUT
101= PWM4OUT
100= PWM3OUT
011= PWM2OUT
010= PWM1OUT
001= async_C1OUT
000= Reserved
DS41615A-page 204
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
REGISTER 24-3: CWGxCON2: CWG CONTROL REGISTER 2
R/W-0/0
G1ASE
R/W-0/0
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
G1ARSEN
G1ASDC1
G1ASDFLT G1ASDCLC2
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
G1ASE: Auto-Shutdown Event Status bit
1= An auto-shutdown event has occurred
0= No auto-shutdown event has occurred
G1ARSEN: Auto-Restart Enable bit
1= Auto-restart is enabled
0= Auto-restart is disabled
bit 5-3
bit 2
Unimplemented: Read as ‘0’
G1ASDC1: CWG Auto-shutdown on Comparator 1 Enable bit
1= Shutdown when Comparator 1 output is high
0= Comparator 1 output has no effect on shutdown
bit 1
bit 0
G1ASDFLT: CWG Auto-shutdown on FLT Enable bit
1= Shutdown when CWG1FLT in put is low
0= CWG1FLT input has no effect on shutdown
G1ASDCLC2: CWG Auto-shutdown on CLC2 Enable bit
1= Shutdown when LC2OUT is high
0= LC2OUT has no effect on shutdown
2011 Microchip Technology Inc.
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DS41615A-page 205
PIC12(L)F1501
REGISTER 24-4: CWGxDBR: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) RISING
DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
CWGxDBR<5:0>: Complementary Waveform Generator (CWGx) Rising counts
11 1111= 63-64 counts of dead band
11 1110= 62-63 counts of dead band
00 0010= 2-3 counts of dead band
00 0001= 1-2 counts of dead band
00 0000= 0 counts of dead band
REGISTER 24-5: CWGxDBF: COMPLEMENTARY WAVEFORM GENERATOR (CWGx) FALLING
DEAD-BAND COUNT REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
CWGxDBF<5:0>: Complementary Waveform Generator (CWGx) Falling counts
11 1111= 63-64 counts of dead band
11 1110= 62-63 counts of dead band
00 0010= 2-3 counts of dead band
00 0001= 1-2 counts of dead band
00 0000= 0 counts of dead band. Dead-band generation is bypassed.
DS41615A-page 206
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
24.13.1 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 11.1 “Alternate Pin Function” for
more information.
TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH CWG
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
—
ANSA4
—
—
ANSA2
ANSA1
CLC1SEL
—
ANSA0
NCO1SEL
G1CS0
103
100
203
204
205
206
206
102
T1GSEL
APFCON
CWG1BSEL CWG1ASEL
—
—
CWG1CON0
CWG1CON1
CWG1CON2
CWG1DBF
CWG1DBR
TRISA
G1EN
G1OEB
G1OEA G1POLB G1POLA
G1ASDLB<1:0>
G1ASDLA<1:0>
G1IS<1:0>
—
—
—
G1ASE
G1ARSEN
G1ASDC1
CWG1DBF<5:0>
CWG1DBR<5:0>
TRISA2
G1ASDFLT
G1ASDCLC2
—
—
—
—
—
—
—
—
(1)
TRISA5 TRISA4
TRISA1
TRISA0
—
Legend:
Note 1:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by CWG.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 207
PIC12(L)F1501
NOTES:
DS41615A-page 208
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
25.3 Common Programming Interfaces
25.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6 pin, 6
connector) configuration. See Figure 25-1.
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process, allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
FIGURE 25-1:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
ICSPDAT
• VSS
NC
2 4 6
VDD
In Program/Verify mode the program memory, user IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirec-
tional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC16193X/PIC16LF193X Memory
Programming Specification” (DS41360).
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
VPP/MCLR
VSS
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
25.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
5 = ICSPCLK
6 = No Connect
25.2 Low-Voltage Programming Entry
Mode
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 25-2.
The Low-Voltage Programming Entry mode allows the
PIC® Flash MCUs to be programmed using VDD only,
without high voltage. When the LVP bit of Configuration
Words is set to ‘1’, the low-voltage ICSP programming
entry is enabled. To disable the Low-Voltage ICSP
mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
1. MCLR is brought to VIL.
2.
A
32-bit key sequence is presented on
ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section MCLR for more infor-
mation.
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
2011 Microchip Technology Inc.
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DS41615A-page 209
PIC12(L)F1501
FIGURE 25-2:
PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 25-3 for more
information.
FIGURE 25-3:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
DS41615A-page 210
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
26.1 Read-Modify-Write Operations
26.0 INSTRUCTION SET SUMMARY
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
Each instruction is a 14-bit word containing the opera-
tion code (opcode) and all required operands. The op
codes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
TABLE 26-1: OPCODE FIELD
DESCRIPTIONS
Table 26-3 lists the instructions recognized by the
MPASMTM assembler.
Field
Description
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
k
x
Don’t care location (= 0or 1).
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 26-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
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Preliminary
DS41615A-page 211
PIC12(L)F1501
FIGURE 26-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
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PIC12(L)F1501
TABLE 26-3: PIC12(L)F1501 ENHANCED INSTRUCTION SET
14-Bit Opcode
Status
Mnemonic,
Operands
Description
Cycles
Notes
Affected
MSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
00 0111 dfff ffff C, DC, Z
LSb
ADDWF
f, d
Add W and f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
ADDWFC f, d
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff
ANDWF
ASRF
LSLF
f, d
f, d
f, d
f, d
f
Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
Clear W
Complement f
Decrement f
Increment f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
C
C
RRF
SUBWF
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
SUBWFB f, d
SWAPF
XORWF
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
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PIC12(L)F1501
TABLE 26-3: PIC12(L)F1501 ENHANCED INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
kkkk
MOVIW
n mm
Z
Z
2, 3
k[n]
n mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
1
1
11 1111 0nkk 1nmm
00 0000 0001 kkkk
2
2, 3
MOVWI
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
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PIC12(L)F1501
26.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
-32 k 31
n [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range
0000h-FFFFh. Moving beyond these
bounds will cause the FSR to
wrap-around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
d 0,1
Operands:
Operation:
Status Affected:
Description:
Operation:
(W) .AND. (f) (destination)
(W) + k (W)
C, DC, Z
Status Affected:
Description:
Z
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d 0,1
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Operation:
(W) + (f) (destination)
Status Affected:
Description:
C, DC, Z
Status Affected:
Description:
C, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
C
register f
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) + (C) dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
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PIC12(L)F1501
BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
skip if (f<b>) = 0
Operation:
0 (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
0 f 127
0 b < 7
Operands:
-256 label - PC + 1 255
-256 k 255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
1 (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
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PIC12(L)F1501
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 k 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
(PC) +1 TOS,
(W) PC<7:0>,
Operation:
(f) (destination)
(PCLATH<6:0>) PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a two-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
The contents of register ‘f’ are cleared
and the Z bit is set.
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
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PIC12(L)F1501
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 k 2047
k
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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PIC12(L)F1501
LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
Operation:
(f) (dest)
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,destination is W
register. If d = 1, the destination is file
register f itself. d = 1is useful to test a
file register since status flag Z is
affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
=
value in FSR register
1
Syntax:
[ label ] LSRF f {,d}
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
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DS41615A-page 219
PIC12(L)F1501
MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP
0 k 127
k PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
INDFn W
Effective address is determined by
MOVLW
Move literal to W
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Operands:
Operation:
Status Affected:
Description:
After the Move, the FSR value will be
either:
None
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
Status Affected:
Z
Words:
1
1
Cycles:
Example:
Mode
Syntax
mm
00
01
10
11
MOVLW
0x5A
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
After Instruction
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
Syntax:
f
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
Status Affected:
Description:
None
Move data from W register to register
‘f’.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Words:
1
1
Cycles:
Example:
MOVWF
Before Instruction
OPTION_REG = 0xFF
OPTION_REG
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap-around.
W
= 0x4F
After Instruction
OPTION_REG = 0x4F
= 0x4F
W
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 k 15
k BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
DS41615A-page 220
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
NOP
No Operation
MOVWI
Move W to INDFn
Syntax:
[ label ] NOP
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
Description:
Words:
None
No operation
None
No operation
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
1
Cycles:
1
W INDFn
Effective address is determined by
Example:
NOP
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
with W
OPTION
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Syntax:
[ label ] OPTION
None
Unchanged
Operands:
Operation:
Status Affected:
Description:
Status Affected:
None
(W) OPTION_REG
None
Mode
Syntax
mm
00
01
10
11
Move data from W register to
OPTION_REG register.
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
RESET
Software Reset
Syntax:
[ label ] RESET
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
None
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
Description:
None
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
This instruction provides a way to
execute a hardware Reset by soft-
ware.
FSRn is limited to the range
0000h-FFFFh.
Incrementing/decrementing it beyond
these bounds will cause it to
wrap-around.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 221
PIC12(L)F1501
RETURN
Return from Subroutine
RETFIE
Syntax:
Return from Interrupt
Syntax:
[ label ] RETURN
None
[ label ] RETFIE
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
None
TOS PC
None
TOS PC,
1 GIE
Status Affected:
Description:
None
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
RETLW
Syntax:
Return with literal in W
RLF
Rotate Left f through Carry
[ label ] RETLW
0 k 255
k
Syntax:
Operands:
[ label ]
RLF f,d
Operands:
Operation:
0 f 127
d [0,1]
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Description:
None
Status Affected:
Description:
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Words:
1
2
C
Register f
Cycles:
Example:
CALL TABLE;W contains table
;offset value
Words:
1
1
Cycles:
Example:
•
•
•
;W now has table value
TABLE
RLF
REG1,0
Before Instruction
ADDWF PC ;W = offset
RETLW k1 ;Begin table
REG1
C
=
=
1110 0110
0
RETLW k2
;
After Instruction
•
•
•
REG1
W
C
=
=
=
1110 0110
1100 1100
1
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS41615A-page 222
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW
0 k 255
k
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
d [0,1]
k - (W) W)
C, DC, Z
Operation:
See description below
C
The W register is subtracted (2’s com-
plement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
Status Affected:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C = 0
W k
C = 1
W k
C
Register f
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
SUBWF
Subtract W from f
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
[ label ] SUBWF f,d
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
(f) - (W) destination)
Status Affected:
Description:
C, DC, Z
0 PD
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’ is
‘1’, the result is stored back in register
‘f.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
C = 0
W f
The processor is put into Sleep mode
with the oscillator stopped.
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(f) – (W) – (B) dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 223
PIC12(L)F1501
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
Description:
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register with W
Syntax:
[ label ] XORWF f,d
Syntax:
[ label ] TRIS f
5 f 7
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) TRIS register ‘f’
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
DS41615A-page 224
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC12F1501 ............................................................................. -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC12LF1501 ........................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin, -40°C TA +85°C for industrial............................................................... 210 mA
Maximum current out of VSS pin, -40°C TA +125°C for extended .............................................................. 95 mA
Maximum current into VDD pin, -40°C TA +85°C for industrial.................................................................. 150 mA
Maximum current into VDD pin, -40°C TA +125°C for extended................................................................. 70 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 225
PIC12(L)F1501
FIGURE 27-1:
PIC12F1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
5.5
2.5
2.3
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.
FIGURE 27-2:
PIC12LF1501 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
3.6
2.5
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 27-1 for each Oscillator mode’s supported frequencies.
DS41615A-page 226
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.1 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No.
Sym.
Characteristic
Supply Voltage
Min. Typ† Max.
Units
Conditions
D001
VDD
PIC12LF1501 1.8
—
—
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 20 MHz
2.5
D001
PIC12F1501 2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 20 MHz
D002*
VDR
RAM Data Retention Voltage(1)
PIC12LF1501 1.5
PIC12F1501 1.65
Power-on Reset Release Voltage
PIC12LF1501
PIC12F1501
Power-on Reset Rearm Voltage
—
—
—
—
V
V
Device in Sleep mode
Device in Sleep mode
D002*
D002A* VPOR*
—
—
1.6
1.7
—
—
V
V
D002A*
D002B* VPORR*
PIC12LF1501
PIC12F1501
—
—
0.8
1.7
—
—
V
V
D002B*
D003
VADFVR
Fixed Voltage Reference Voltage for
ADC, Initial Accuracy
—
—
—
—
—
—
1
1
1
1
1
1
—
—
—
—
—
—
%
1.024V, VDD 2.5V, 85°C (NOTE 2)
1.024V, VDD 2.5V, 125°C (NOTE 2)
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
D003C* TCVFVR
Temperature Coefficient, Fixed
Voltage Reference
—
-130
0.270
—
—
—
—
ppm/°C
%/V
D003D* VFVR/
VIN
Line Regulation, Fixed Voltage
Reference
—
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
V/ms See Section 6.1 “Power-on Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting the
FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or
greater.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 227
PIC12(L)F1501
FIGURE 27-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
(3)
(2)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
DS41615A-page 228
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
D013
D013
—
—
—
—
—
—
—
25
45
140
230
180
240
320
250
430
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
FOSC = 1 MHz
EC Oscillator mode, Medium-power mode
60
FOSC = 1 MHz
EC Oscillator mode
Medium-power mode
80
100
100
180
D014
D014
FOSC = 4 MHz
EC Oscillator mode,
Medium-power mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
160
210
260
2.5
4.0
14
275
450
650
18
A
A
A
A
A
A
A
A
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
A
A
A
A
A
A
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
3.0
5.0
1.8
3.0
FOSC = 4 MHz
EC Oscillator mode
Medium-power mode
D015
D015
FOSC = 31 kHz
LFINTOSC mode
20
58
FOSC = 31 kHz
LFINTOSC mode
15
65
16
70
D017*
D017*
0.40
0.60
0.50
0.60
0.70
0.60
1.0
0.74
0.96
1.03
6
0.70
1.10
0.75
1.15
1.35
1.2
1.75
1.2
1.8
2.0
17
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
D018
D018
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
D019A
D019A
D019B
*
FOSC = 32 kHz
ECL mode
8
20
14
25
FOSC = 32 kHz
ECL mode
15
30
15
165
190
FOSC = 500 kHz
ECM mode
20
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 229
PIC12(L)F1501
27.2 DC Characteristics: PIC12(L)F1501-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
D019B
—
—
—
34
37
210
270
—
A
A
mA
3.0
5.0
3.0
FOSC = 500 kHz
ECM mode
D019C
D019C
0.65
FOSC = 20 MHz
ECH mode
—
—
0.75
0.87
—
—
mA
mA
3.0
5.0
FOSC = 20 MHz
ECH mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: CLKIN = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
DS41615A-page 230
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
Units
VDD
Note
(2)
Power-down Base Current (IPD)
D022
D022
—
.02
.03
10
1.0
1.1
35
42
45
1.5
2.0
38
43
48
22
24
62
72
115
14
47
55
5
2.4
3.0
40
48
61
2.4
3.0
44
48
65
25
27
65
75
120
16
50
66
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.0
5.0
3.0
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
WDT, BOR, FVR, and T1OSC
disabled, all Peripherals Inactive
11
12
D023
D023
0.2
0.5
11
LPWDT Current (Note 1)
LPWDT Current (Note 1)
12
13
D023A
D023A
13
FVR current (Note 1)
FVR current (Note 1)
22
23
30
34
D024
D024
7
BOR Current (Note 1)
BOR Current (Note 1)
15
17
D024A
D024A
0.2
10
LPBOR Current
LPBOR Current
25
30
3.5
4.0
39
43
46
1.5
2.0
38
43
46
40
50
4.0
4.5
45
49
65
3.0
3.5
45
49
65
12
D026
D026
0.03
0.04
10
A/D Current (Note 1, Note 3), no
conversion in progress
A/D Current (Note 1, Note 3), no
conversion in progress
11
12
D026A*
D026A*
250
250
280
280
280
A/D Current (Note 1, Note 3),
conversion in progress
A/D Current (Note 1, Note 3),
conversion in progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 231
PIC12(L)F1501
27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
Units
VDD
Note
(2)
Power-down Base Current (IPD)
D027*
D027*
—
20
21
30
31
32
7
43
45
53
57
61
20
25
30
37
40
44
46
54
58
62
21
26
31
38
41
55
60
65
70
75
35
40
45
55
60
56
61
66
71
76
36
41
46
56
61
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1 Comparator Enabled
(HP Mode)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1 Comparator Enabled
(HP Mode)
D027A*
D027A*
1 Comparator Enabled
(LP Mode)
80
17
18
19
21
22
31
32
33
8
1 Comparator Enabled
(LP Mode)
D028*
D028*
2 Comparators Enabled
(HP Mode)
2 Comparators Enabled
(HP Mode)
D028A*
D028A*
2 Comparators Enabled
(LP Mode)
81
18
19
20
2 Comparators Enabled
(LP Mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
DS41615A-page 232
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.3 DC Characteristics: PIC12(L)F1501-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC12LF1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC12F1501
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Note
Param
No.
Max.
+85°C +125°C
Max.
Device Characteristics
Min.
Typ†
Units
VDD
(2)
Power-down Base Current (IPD) in Low-Power Sleep mode
D029A
D029B
—
—
0.1
0.2
1.5
1.7
1.9
40
45
47
20
24
13
14
15
40
42
43
2.0
2.3
2.5
45
50
52
25
30
18
19
20
45
47
48
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.3
3.0
5.0
2.3
3.0
5.0
3.0
5.0
2.3
3.0
5.0
2.3
3.0
5.0
Base
0.3
18
FVR Enabled
BOR Enabled
18.5
19
D029C
D029D
—
—
8.0
9.5
3.2
Comparator Enabled
(LP mode)
3.5
3.6
D029E
—
17.0
17.5
18.0
Comparator Enabled
(HP mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Legend:
TBD = To Be Determined
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 233
PIC12(L)F1501
27.4 DC Characteristics: PIC12(L)F1501-I/E
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D030
D030A
D031
D032
with TTL buffer
—
—
—
—
—
—
—
—
0.8
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.2 VDD
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
MCLR
VIH
Input High Voltage
I/O ports:
—
—
—
—
—
—
D040
with TTL buffer
2.0
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
D040A
0.25 VDD +
0.8
D041
D042
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
—
—
—
—
V
V
2.0V VDD 5.5V
(1)
IIL
Input Leakage Current
D060
I/O ports
—
—
± 5
± 125
nA
VSS VPIN VDD, Pin at high-
impedance at 85°C
± 5
± 1000
± 200
nA 125°C
D061
MCLR(2)
± 50
nA
A
V
VSS VPIN VDD at 85°C
IPUR
VOL
Weak Pull-up Current
D070*
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
(3)
Output Low Voltage
D080
D090
I/O ports
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
0.6
(3)
VOH
Output High Voltage
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
VDD - 0.7
—
—
—
V
Capacitive Loading Specs on Output Pins
All I/O pins
These parameters are characterized but not tested.
D101A* CIO
—
50
pF
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Negative current is defined as current sourced by the pin.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Including OSC2 in CLKOUT mode.
DS41615A-page 234
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
DC CHARACTERISTICS
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
Program Memory Programming
Specifications
D110
D111
D112
D113
VIHH
IDDP
VBE
Voltage on MCLR/VPP pin
Supply Current during Programming
VDD for Bulk Erase
8.0
—
—
—
—
—
9.0
V
mA
V
(Note 2)
10
2.7
VDD max.
VDD max.
VPEW
VDD for Write or Row Erase
VDD min.
V
D114
IPPPGM Current on MCLR/VPP during Erase/
Write
—
1.0
—
mA
D115
IDDPGM Current on VDD during Erase/Write
Program Flash Memory
—
5.0
—
mA
D121
D122
D123
D124
EP
Cell Endurance
10K
VDD min.
—
—
—
2
—
VDD max.
2.5
E/W -40C to +85C (Note 1)
VPR
TIW
VDD for Read
V
Self-timed Write Cycle Time
ms
TRETD Characteristic Retention
—
40
—
Year Provided no other
specifications are violated
D125
EHEFC High-Endurance Flash Cell
100K
—
—
E/W 0C to +60C,
Lower byte,
Last 128 Addresses in Flash
Memory
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 235
PIC12(L)F1501
27.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Typ.
Units
Conditions
8-pin PDIP package
TH01
JA
Thermal Resistance Junction to Ambient
89.3
149.5
211
C/W
C/W
C/W
C/W
C/W
C/W
8-pin SOIC package
8-pin MSOP package
56.7
68
8-pin DFN 3X3mm package
8-pin DFN 2X3mm package
TH02
JC
Thermal Resistance Junction to Case
43.1
8-pin PDIP package
39.9
39
C/W
C/W
C/W
C/W
C
8-pin SOIC package
8-pin MSOP package
8-pin DFN 3X3mm package
8-pin DFN 2X3mm package
9
12.7
150
—
TH03
TH04
TH05
TH06
TH07
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
W
PD = PINTERNAL + PI/O
(1)
PINTERNAL Internal Power Dissipation
—
W
PINTERNAL = IDD x VDD
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/JA
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: TJ = Junction Temperature.
DS41615A-page 236
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
27.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
CLKIN
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCKx
SS
SDIx
do
dt
SDO
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 27-4:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 237
PIC12(L)F1501
27.8 AC Characteristics: PIC12(L)F1501-I/E
FIGURE 27-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS12
OS03
OS11
OS02
CLKOUT
(CLKOUT Mode)
Note 1:
See Table 27-3.
TABLE 27-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
OS01
FOSC
External CLKIN Frequency(1)
DC
DC
DC
50
—
—
—
—
—
0.5
4
MHz EC Oscillator mode (low)
MHz EC Oscillator mode (medium)
MHz EC Oscillator mode (high)
20
OS02
OS03
TOSC
TCY
External CLKIN Period(1)
Instruction Cycle Time(1)
ns
ns
EC mode
200
DC
TCY = FOSC/4
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
TABLE 27-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
Sym.
No.
Freq.
Tolerance
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency(1)
10%
—
16.0
—
MHz 0°C TA +85°C
OS09
LFOSC
Internal LFINTOSC Frequency
—
—
—
—
31
5
—
8
kHz -40°C TA +125°C
s
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
These parameters are characterized but not tested.
*
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41615A-page 238
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
FIGURE 27-6:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS18
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 27-3: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
OS11 TosH2ckL FOSC to CLKOUT (1)
OS12 TosH2ckH FOSC to CLKOUT (1)
OS13 TckL2ioV CLKOUT to Port out valid(1)
—
—
—
—
—
—
70
72
20
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
ns
OS14 TioV2ckH Port input valid before CLKOUT(1)
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid
TOSC + 200 ns
—
50
—
—
70*
—
ns
—
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
OS16 TosH2ioI
Fosc (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
20
—
—
ns
(I/O in setup time)
OS18* TioR
OS19* TioF
Port output rise time(2)
—
—
15
40
32
72
ns
ns
VDD = 2.0V
VDD = 5.0V
Port output fall time(2)
—
—
28
15
55
30
VDD = 2.0V
VDD = 5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level
time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in EC mode where CLKOUT output is 4 x TOSC.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 239
PIC12(L)F1501
FIGURE 27-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
FIGURE 27-8:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Words is programmed to ‘0’.
2 ms delay if PWRTE = 0and VREGEN = 1.
DS41615A-page 240
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 27-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 3.3-5V, -40°C to +85°C
s VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
10
16
27
ms VDD = 3.3V-5V,
1:16 Prescaler used
33*
34*
TPWRT Power-up Timer Period, PWRTE = 0 40
65
—
140
2.0
ms
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
s
35
VBOR
Brown-out Reset Voltage: BORV = 0 2.55 2.70 2.85
V
PIC12(L)F1501
BORV = 1 2.30 2.40 2.55
V
V
PIC12F1501
PIC12LF1501
1.80 1.90 2.05
36*
37*
VHYST
Brown-out Reset Hysteresis
0
1
25
3
50
5
mV -40°C to +85°C
TBORDC Brown-out Reset DC Response
Time
s VDD VBOR
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
FIGURE 27-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 241
PIC12(L)F1501
TABLE 27-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
Typ†
Max.
Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
TT1H
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
46*
47*
TT1L
TT1P
T1CKI Low Synchronous, No Prescaler
0.5 TCY + 20
Time
Synchronous, with Prescaler
Asynchronous
15
30
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
—
ns
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting
the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V
or greater.
TABLE 27-6: PIC12(L)F1501 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature Tested at 25°C
Param
No.
Sym.
Characteristic
Resolution
Min.
Typ†
Max. Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
—
—
—
—
—
—
10
±1.7
±1
bit
Integral Error
LSb VREF = 3.0V
Differential Error
LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error
—
—
—
—
—
—
—
±2.5
±2.0
VDD
VREF
10
LSb VREF = 3.0V
LSb VREF = 3.0V
AD05 EGN Gain Error
AD06 VREF Reference Voltage(3)
1.8
VSS
—
V
V
VREF = (VREF+ minus VREF-) (NOTE 5)
AD07 VAIN Full-Scale Range
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
k Can go higher if external 0.01F capacitor is
present on input pin.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF+ pin, VDD pin, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
5: FVR voltage selected must be 2.048V or 4.096V.
DS41615A-page 242
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 27-7: PIC12(L)F1501 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD130* TAD
A/D Clock Period
1.0
1.0
—
9.0
6.0
s
s
TOSC-based
A/D Internal FRC Oscillator
Period
1.6
ADCS<1:0> = 11(ADFRC mode)
AD131 TCNV Conversion Time (not including
Acquisition Time)(1)
—
—
11
—
—
TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time
5.0
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
FIGURE 27-10:
PIC12(L)F1501 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
AD134
Q4
(TOSC/2(1)
)
AD131
AD130
A/D CLK
9
8
7
6
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 243
PIC12(L)F1501
FIGURE 27-11:
PIC12(L)F1501 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
(1)
(TOSC/2 + TCY
1 TCY
)
AD131
AD130
A/D CLK
A/D Data
9
8
7
3
2
1
0
6
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as FRC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
DS41615A-page 244
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 27-8: COMPARATOR SPECIFICATIONS
Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
Sym.
Characteristics
Min.
Typ.
Max. Units
Comments
No.
CM01
Vioff
Input Offset Voltage
—
±7.5
±60
mV High Power Mode,
Vicm = VDD/2
CM02
Vicm
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time Rising Edge
Response Time Falling Edge
Response Time Rising Edge
Response Time Falling Edge
0
—
50
VDD
—
V
CM03*
CM04A
CM04B
CM04C
CM04D
CM05*
CMRR
—
—
—
—
—
—
dB
400
200
1200
550
—
800
400
—
ns High Power Mode
ns High Power Mode
Tresp
ns Low Power Mode
—
ns
Tmc2ov Comparator Mode Change to
Output Valid
10
s
CM06
Chyster Comparator Hysteresis
—
65
—
mV Hysteresis ON
*
These parameters are characterized but not tested.
TABLE 27-9: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS
Operating Conditions: 2.5V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated).
Param
No.
Sym.
Characteristics
Step Size
Min.
Typ.
Max.
Units
Comments
DAC01*
DAC02*
DAC03*
DAC04*
*
CLSB
—
—
—
—
VDD/32
—
—
1/2
—
V
LSb
CACC
CR
Absolute Accuracy
Unit Resistor Value (R)
Settling Time(1)
5000
—
CST
10
s
These parameters are characterized but not tested.
Note 1: Settling time measured while DACR<4:0> transitions from ‘0000’ to ‘1111’.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 245
PIC12(L)F1501
NOTES:
DS41615A-page 246
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
28.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 247
PIC12(L)F1501
NOTES:
DS41615A-page 248
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
29.1 MPLAB Integrated Development
Environment Software
29.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- HI-TECH C® for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 249
PIC12(L)F1501
29.2 MPLAB C Compilers for Various
Device Families
29.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
29.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
29.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41615A-page 250
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
29.7 MPLAB SIM Software Simulator
29.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
29.10 PICkit 3 In-Circuit Debugger/
Programmer and
29.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 251
PIC12(L)F1501
29.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
29.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
29.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41615A-page 252
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
30.0 PACKAGING INFORMATION
30.1 Package Marking Information
8-Lead PDIP (300 mil)
Example
12F1501
XXXXXXXX
XXXXXNNN
e
3
I/P
017
YYWW
1110
8-Lead SOIC (3.90 mm)
Example
12F1501
I/SN1110
017
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
*
Standard PICmicro® device marking consists of Microchip part number, year code, week code and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 253
PIC12(L)F1501
Package Marking Information (Continued)
8-Lead MSOP (3x3 mm)
Example
F1501I
110017
8-Lead DFN (2x3x0.9 mm)
Example
BAK
110
10
8-Lead DFN (3x3x0.9 mm)
Example
MFB1
1110
017
XXXX
YYWW
NNN
PIN 1
PIN 1
DS41615A-page 254
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
TABLE 30-1: 8-LEAD 2x3 DFN (MC) TOP
MARKING
Part Number
Marking
PIC12F1501-E/MC
PIC12F1501-I/MC
PIC12LF1501-E/MC
PIC12LF1501-I/MC
BAK
BAL
BAM
BAP
TABLE 30-2: 8-LEAD 3x3 QFN (MF) TOP
MARKING
Part Number
Marking
PIC12F1501-E/MF
PIC12F1501-I/MF
PIC12LF1501-E/MF
PIC12LF1501-I/MF
MFA1
MFB1
MFC1
MFD1
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 255
PIC12(L)F1501
30.2 Package Details
The following sections give the technical details of the packages.
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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꢤꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪꢅꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢣꢀꢶꢩ
DS41615A-page 256
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 257
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41615A-page 258
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 259
PIC12(L)F1501
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢦꢋꢌꢠꢘꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦꢞꢒꢆꢚꢦꢞꢟꢇꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
D
N
E
E1
NOTE 1
2
b
1
e
c
φ
A2
A
L
L1
A1
ꢯꢄꢃꢏꢇ
ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢱ
ꢌ
ꢶ
ꢣꢁꢺꢨꢅꢩꢛꢝ
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ
ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢹꢃꢋꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ
ꢬꢕꢕꢏꢅꢳꢌꢄꢜꢏꢘ
ꢦ
ꢷ
ꢣꢁꢻꢨ
ꢣꢁꢣꢣ
ꢷ
ꢣꢁꢶꢨ
ꢀꢁꢀꢣ
ꢣꢁꢸꢨ
ꢣꢁꢀꢨ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢷ
ꢥꢁꢸꢣꢅꢩꢛꢝ
ꢞꢁꢣꢣꢅꢩꢛꢝ
ꢞꢁꢣꢣꢅꢩꢛꢝ
ꢣꢁꢺꢣ
ꢳ
ꢣꢁꢥꢣ
ꢣꢁꢶꢣ
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ
ꢳꢀ
ꢀ
ꢣꢁꢸꢨꢅꢼꢠꢬ
ꢷ
ꢣꢾ
ꢶꢾ
ꢳꢌꢉꢋꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢳꢌꢉꢋꢅꢹꢃꢋꢏꢘ
ꢖ
ꢔ
ꢣꢁꢣꢶ
ꢣꢁꢙꢙ
ꢷ
ꢷ
ꢣꢁꢙꢞ
ꢣꢁꢥꢣ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢀꢨꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢀꢀꢀꢩ
DS41615A-page 260
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 261
PIC12(L)F1501
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢩꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦꢥꢒꢆꢓꢆꢪꢫꢔꢫꢕꢣꢤꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢩꢜꢛ
ꢜꢘꢊꢃꢝ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢪꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
e
D
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
NOTE 1
2
1
1
2
D2
BOTTOM VIEW
TOP VIEW
A
NOTE 2
A3
A1
ꢯꢄꢃꢏꢇ
ꢢꢰꢳꢳꢰꢢꢠꢫꢠꢼꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢳꢃꢑꢃꢏꢇ
ꢢꢰꢱ
ꢱꢴꢢ
ꢶ
ꢣꢁꢨꢣꢅꢩꢛꢝ
ꢣꢁꢸꢣ
ꢢꢦꢵ
ꢱꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢲꢌꢃꢜꢘꢏ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ
ꢝꢕꢄꢏꢉꢖꢏꢅꢫꢘꢃꢖꢭꢄꢌꢇꢇ
ꢴꢆꢌꢐꢉꢊꢊꢅꢳꢌꢄꢜꢏꢘ
ꢴꢆꢌꢐꢉꢊꢊꢅꢹꢃꢋꢏꢘ
ꢱ
ꢌ
ꢦ
ꢦꢀ
ꢦꢞ
ꢟ
ꢣꢁꢶꢣ
ꢣꢁꢣꢣ
ꢀꢁꢣꢣ
ꢣꢁꢣꢨ
ꢣꢁꢣꢙ
ꢣꢁꢙꢣꢅꢼꢠꢬ
ꢙꢁꢣꢣꢅꢩꢛꢝ
ꢞꢁꢣꢣꢅꢩꢛꢝ
ꢷ
ꢷ
ꢣꢁꢙꢨ
ꢠ
ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢳꢌꢄꢜꢏꢘ
ꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋꢅꢹꢃꢋꢏꢘ
ꢝꢕꢄꢏꢉꢖꢏꢅꢹꢃꢋꢏꢘ
ꢝꢕꢄꢏꢉꢖꢏꢅꢳꢌꢄꢜꢏꢘ
ꢝꢕꢄꢏꢉꢖꢏꢽꢏꢕꢽꢠꢍꢡꢕꢇꢌꢋꢅꢂꢉꢋ
ꢟꢙ
ꢠꢙ
ꢔ
ꢳ
U
ꢀꢁꢞꢣ
ꢀꢁꢨꢣ
ꢣꢁꢙꢣ
ꢣꢁꢞꢣ
ꢣꢁꢙꢣ
ꢀꢁꢨꢨ
ꢀꢁꢻꢨ
ꢣꢁꢞꢣ
ꢣꢁꢨꢣ
ꢷ
ꢣꢁꢥꢣ
ꢷ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢂꢉꢖꢭꢉꢜꢌꢅꢑꢉꢒꢅꢘꢉꢆꢌꢅꢕꢄꢌꢅꢕꢐꢅꢑꢕꢐꢌꢅꢌꢍꢡꢕꢇꢌꢋꢅꢏꢃꢌꢅꢔꢉꢐꢇꢅꢉꢏꢅꢌꢄꢋꢇꢁ
ꢞꢁ ꢂꢉꢖꢭꢉꢜꢌꢅꢃꢇꢅꢇꢉꢗꢅꢇꢃꢄꢜꢈꢊꢉꢏꢌꢋꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢨꢢꢁ
ꢩꢛꢝꢪ ꢩꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢫꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢼꢠꢬꢪ ꢼꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢫꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢽꢀꢙꢞꢝ
DS41615A-page 262
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 263
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41615A-page 264
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 265
PIC12(L)F1501
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41615A-page 266
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
Original release (11/2011).
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
NOTES:
DS41615A-page 268
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
INDEX
Comparator............................................................... 132
Digital-to-Analog Converter (DAC) ........................... 128
Generic I/O Port.......................................................... 99
Interrupt Logic............................................................. 61
NCO.......................................................................... 184
On-Chip Reset Circuit................................................. 53
PIC12(L)F1501....................................................... 5, 10
PWM......................................................................... 161
Timer0 ...................................................................... 141
Timer1 ...................................................................... 145
Timer1 Gate.............................................. 150, 151, 152
Timer2 ...................................................................... 157
Voltage Reference.................................................... 109
Voltage Reference Output Buffer Example .............. 128
BORCON Register.............................................................. 55
BRA .................................................................................. 216
Brown-out Reset (BOR)...................................................... 55
Specifications ........................................................... 241
Timing and Characteristics....................................... 240
A
A/D
Specifications.................................................... 242, 243
Absolute Maximum Ratings .............................................. 225
AC Characteristics
Industrial and Extended ............................................ 238
Load Conditions........................................................ 237
ADC .................................................................................. 113
Acquisition Requirements ......................................... 124
Associated registers.................................................. 126
Block Diagram........................................................... 113
Calculating Acquisition Time..................................... 124
Channel Selection..................................................... 114
Configuration............................................................. 114
Configuring Interrupt ................................................. 118
Conversion Clock...................................................... 114
Conversion Procedure .............................................. 118
Internal Sampling Switch (RSS) Impedance.............. 124
Interrupts................................................................... 116
Operation .................................................................. 117
Operation During Sleep ............................................ 117
Port Configuration..................................................... 114
Reference Voltage (VREF)......................................... 114
Source Impedance.................................................... 124
Starting an A/D Conversion ...................................... 116
ADCON0 Register....................................................... 25, 119
ADCON1 Register....................................................... 25, 120
ADCON2 Register............................................................. 121
ADDFSR ........................................................................... 215
ADDWFC .......................................................................... 215
ADRESH Register............................................................... 25
ADRESH Register (ADFM = 0)......................................... 122
ADRESH Register (ADFM = 1)......................................... 123
ADRESL Register (ADFM = 0).......................................... 122
ADRESL Register (ADFM = 1).......................................... 123
Alternate Pin Function....................................................... 100
Analog-to-Digital Converter. See ADC
C
C Compilers
MPLAB C18.............................................................. 250
CALL................................................................................. 217
CALLW ............................................................................. 217
CLCDATA Register........................................................... 181
CLCxCON Register .......................................................... 173
CLCxGLS0 Register ......................................................... 177
CLCxGLS1 Register ......................................................... 178
CLCxGLS2 Register ......................................................... 179
CLCxGLS3 Register ......................................................... 180
CLCxPOL Register ........................................................... 174
CLCxSEL0 Register.......................................................... 175
Clock Sources
External Modes........................................................... 46
EC ...................................................................... 46
Internal Modes............................................................ 47
HFINTOSC ......................................................... 47
Internal Oscillator Clock Switch Timing.............. 48
LFINTOSC.......................................................... 47
Clock Switching .................................................................. 50
CMOUT Register.............................................................. 138
CMxCON0 Register.......................................................... 137
CMxCON1 Register.......................................................... 138
Code Examples
ANSELA Register ............................................................. 103
APFCON Register............................................................. 100
Assembler
MPASM Assembler................................................... 250
Automatic Context Saving................................................... 65
B
Bank 10............................................................................... 28
Bank 11............................................................................... 28
Bank 12............................................................................... 28
Bank 13............................................................................... 28
Bank 14-29.......................................................................... 28
Bank 2................................................................................. 26
Bank 3................................................................................. 26
Bank 30............................................................................... 29
Bank 4................................................................................. 27
Bank 5................................................................................. 27
Bank 6................................................................................. 27
Bank 7................................................................................. 27
Bank 8................................................................................. 27
Bank 9................................................................................. 27
Block Diagrams
A/D Conversion ........................................................ 118
Initializing PORTA ...................................................... 99
Writing to Flash Program Memory.............................. 92
Comparator
Associated Registers................................................ 139
Operation.................................................................. 131
Comparator Module.......................................................... 131
Cx Output State Versus Input Conditions................. 133
Comparator Specifications................................................ 245
Comparators
C2OUT as T1 Gate................................................... 147
Complementary Waveform Generator (CWG).......... 193, 194
CONFIG1 Register ............................................................. 40
CONFIG2 Register ............................................................. 41
Core Function Register....................................................... 24
Customer Change Notification Service............................. 275
Customer Notification Service .......................................... 275
Customer Support............................................................. 275
CWG
ADC .......................................................................... 113
ADC Transfer Function ............................................. 125
Analog Input Model........................................... 125, 136
Clock Source............................................................... 45
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Auto-shutdown Control .............................................200
Clock Source.............................................................196
Output Control...........................................................196
Selectable Input Sources..........................................196
CWGxCON0 Register .......................................................203
CWGxCON1 Register .......................................................204
CWGxCON2 Register .......................................................205
CWGxDBF Register..........................................................206
CWGxDBR Register..........................................................206
BRA .......................................................................... 216
CALL......................................................................... 217
CALLW ..................................................................... 217
LSLF ......................................................................... 219
LSRF ........................................................................ 219
MOVF ....................................................................... 219
MOVIW ..................................................................... 220
MOVLB..................................................................... 220
MOVWI..................................................................... 221
OPTION.................................................................... 221
RESET...................................................................... 221
SUBWFB .................................................................. 223
TRIS ......................................................................... 224
BCF .......................................................................... 216
BSF........................................................................... 216
BTFSC...................................................................... 216
BTFSS ...................................................................... 216
CALL......................................................................... 217
CLRF ........................................................................ 217
CLRW ....................................................................... 217
CLRWDT .................................................................. 217
COMF ....................................................................... 217
DECF........................................................................ 217
DECFSZ ................................................................... 218
GOTO ....................................................................... 218
INCF ......................................................................... 218
INCFSZ..................................................................... 218
IORLW...................................................................... 218
IORWF...................................................................... 218
MOVLW .................................................................... 220
MOVWF.................................................................... 220
NOP.......................................................................... 221
RETFIE..................................................................... 222
RETLW ..................................................................... 222
RETURN................................................................... 222
RLF........................................................................... 222
RRF .......................................................................... 223
SLEEP ...................................................................... 223
SUBLW..................................................................... 223
SUBWF..................................................................... 223
SWAPF..................................................................... 224
XORLW .................................................................... 224
XORWF .................................................................... 224
INTCON Register................................................................ 66
Internal Oscillator Block
D
DACCON0 (Digital-to-Analog Converter Control 0)
Register.....................................................................130
DACCON1 (Digital-to-Analog Converter Control 1)
Register.....................................................................130
Data Memory.......................................................................17
DC and AC Characteristics ...............................................247
DC Characteristics
Extended and Industrial ............................................234
Industrial and Extended ............................................227
Development Support .......................................................249
Device Configuration...........................................................39
Code Protection ..........................................................42
Configuration Word.....................................................39
User ID..................................................................42, 43
Device ID Register ..............................................................43
Device Overview .............................................................9, 79
Digital-to-Analog Converter (DAC)....................................127
Associated Registers ................................................130
Effects of a Reset......................................................128
Specifications............................................................245
E
Effects of Reset
PWM mode ...............................................................163
Electrical Specifications ....................................................225
Enhanced Mid-Range CPU.................................................13
Errata ....................................................................................7
Extended Instruction Set
ADDFSR ...................................................................215
F
Firmware Instructions........................................................211
Fixed Voltage Reference (FVR)........................................109
Associated Registers ................................................110
Flash Program Memory.......................................................83
Associated Registers ..................................................98
Configuration Word w/ Flash Program Memory..........98
Erasing........................................................................87
Modifying.....................................................................93
Write Verify .................................................................95
Writing.........................................................................89
Flash Program Memory Control..........................................83
FSR Register.......................................................................24
FVRCON (Fixed Voltage Reference Control) Register.....110
INTOSC
Specifications ................................................... 238
Internal Sampling Switch (RSS) Impedance...................... 124
Internet Address ............................................................... 275
Interrupt-On-Change......................................................... 105
Associated Registers................................................ 108
Interrupts............................................................................. 61
ADC .......................................................................... 118
Associated registers w/ Interrupts............................... 73
TMR1........................................................................ 149
INTOSC Specifications..................................................... 238
IOCAF Register ................................................................ 107
IOCAN Register................................................................ 107
IOCAP Register ................................................................ 107
I
INDF Register .....................................................................24
Indirect Addressing .............................................................34
Instruction Format .............................................................212
Instruction Set ...................................................................211
ADDLW .....................................................................215
ADDWF.....................................................................215
ADDWFC ..................................................................215
ANDLW .....................................................................215
ANDWF.....................................................................215
L
LATA Register .................................................................. 103
Load Conditions................................................................ 237
LSLF ................................................................................. 219
LSRF................................................................................. 219
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PIC12(L)F1501
PMCON1 Register........................................................ 83, 97
PMCON2 Register........................................................ 83, 98
PMDATH Register.............................................................. 96
PMDATL Register............................................................... 96
PMDRH Register................................................................ 96
PORTA ............................................................................. 101
ANSELA Register..................................................... 101
Associated Registers................................................ 104
LATA Register ............................................................ 26
PORTA Register......................................................... 25
Specifications ........................................................... 239
PORTA Register............................................................... 102
Power-Down Mode (Sleep)................................................. 75
Associated Registers.................................................. 78
Power-on Reset.................................................................. 54
Power-up Time-out Sequence............................................ 56
Power-up Timer (PWRT).................................................... 54
Specifications ........................................................... 241
PR2 Register ...................................................................... 25
Program Memory................................................................ 15
Map and Stack (PIC12(L)F1501................................. 16
Programming, Device Instructions.................................... 211
Pulse Width Modulation (PWM)........................................ 161
Associated registers w/ PWM................................... 166
PWM Mode
M
MCLR.................................................................................. 56
Internal........................................................................ 56
Memory Organization.......................................................... 15
Data ............................................................................ 17
Program ...................................................................... 15
Microchip Internet Web Site.............................................. 275
MOVIW ............................................................................. 220
MOVLB ............................................................................. 220
MOVWI ............................................................................. 221
MPLAB ASM30 Assembler, Linker, Librarian ................... 250
MPLAB Integrated Development Environment Software.. 249
MPLAB PM3 Device Programmer .................................... 252
MPLAB REAL ICE In-Circuit Emulator System................. 251
MPLINK Object Linker/MPLIB Object Librarian ................ 250
N
NCO
Associated registers.................................................. 192
NCOxACCH Register........................................................ 190
NCOxACCL Register ........................................................ 190
NCOxACCU Register........................................................ 190
NCOxCLK Register........................................................... 189
NCOxCON Register.......................................................... 189
NCOxINCH Register ......................................................... 191
NCOxINCL Register.......................................................... 191
Numerically Controlled Oscillator (NCO)........................... 183
Duty Cycle........................................................ 162
Effects of Reset................................................ 163
Example PWM Frequencies and
O
Resolutions, 20 MHZ................................ 163
Example PWM Frequencies and
OPCODE Field Descriptions............................................. 211
OPTION ............................................................................ 221
OPTION Register.............................................................. 143
OSCCON Register.............................................................. 51
Oscillator
Associated Registers .................................................. 52
Associated registers.................................................. 207
Oscillator Module ................................................................ 45
ECH ............................................................................ 45
ECL............................................................................. 45
ECM............................................................................ 45
INTOSC ...................................................................... 45
Oscillator Parameters ....................................................... 238
Oscillator Specifications.................................................... 238
Oscillator Start-up Timer (OST)
Resolutions, 8 MHz .................................. 163
Operation in Sleep Mode.................................. 163
Setup for Operation using PWMx pins ............. 164
System Clock Frequency Changes .................. 163
PWM Period ............................................................. 162
Setup for PWM Operation using PWMx Pins ........... 164
PWMxCON Register......................................................... 165
PWMxDCH Register......................................................... 166
PWMxDCL Register.......................................................... 166
R
Reader Response............................................................. 276
Read-Modify-Write Operations ......................................... 211
Registers
ADCON0 (ADC Control 0)........................................ 119
ADCON1 (ADC Control 1)........................................ 120
ADCON2 (ADC Control 2)........................................ 121
ADRESH (ADC Result High) with ADFM = 0) .......... 122
ADRESH (ADC Result High) with ADFM = 1) .......... 123
ADRESL (ADC Result Low) with ADFM = 0)............ 122
ADRESL (ADC Result Low) with ADFM = 1)............ 123
ANSELA (PORTA Analog Select) ............................ 103
APFCON (Alternate Pin Function Control) ............... 100
BORCON Brown-out Reset Control) .......................... 55
CLCDATA (Data Output).......................................... 181
CLCxCON (CLCx Control)........................................ 173
CLCxGLS0 (Gate 1 Logic Select)............................. 177
CLCxGLS1 (Gate 2 Logic Select)............................. 178
CLCxGLS2 (Gate 3 Logic Select)............................. 179
CLCxGLS3 (Gate 4 Logic Select)............................. 180
CLCxPOL (Signal Polarity Control) .......................... 174
CLCxSEL0 (Multiplexer Data 1 and 2 Select) .......... 175
CMOUT (Comparator Output) .................................. 138
CMxCON0 (Cx Control)............................................ 137
CMxCON1 (Cx Control 1)......................................... 138
Configuration Word 1.................................................. 40
Specifications............................................................ 241
OSCSTAT Register............................................................. 52
P
Packaging ......................................................................... 253
Marking ............................................................. 253, 254
PDIP Details.............................................................. 255
PCL and PCLATH............................................................... 14
PCL Register....................................................................... 24
PCLATH Register ............................................................... 24
PCON Register ............................................................. 25, 59
PIE1 Register................................................................ 25, 67
PIE2 Register................................................................ 25, 68
PIE3 Register................................................................ 25, 69
PIR1 Register................................................................ 25, 70
PIR2 Register................................................................ 25, 71
PIR3 Register................................................................ 25, 72
PMADR Registers............................................................... 83
PMADRH Registers ............................................................ 83
PMADRL Register............................................................... 96
PMADRL Registers............................................................. 83
2011 Microchip Technology Inc.
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PIC12(L)F1501
Configuration Word 2..................................................41
Core Function, Summary............................................24
CWGxCON0 (CWG Control 0)..................................203
CWGxCON1 (CWG Control 1)..................................204
CWGxCON2 (CWG Control 1)..................................205
CWGxDBF (CWGx Dead Band Falling Count) .........206
CWGxDBR (CWGx Dead Band Rising Count) .........206
DACCON0 ................................................................130
DACCON1 ................................................................130
Device ID ....................................................................43
FVRCON...................................................................110
INTCON (Interrupt Control).........................................66
IOCAF (Interrupt-on-Change PORTA Flag)..............107
IOCAN (Interrupt-on-Change PORTA
Accessing ................................................................... 32
Reset .......................................................................... 34
Stack Overflow/Underflow .................................................. 56
STATUS Register ............................................................... 18
SUBWFB .......................................................................... 223
T
T1CON Register ......................................................... 25, 153
T1GCON Register ............................................................ 154
T2CON (Timer2) Register................................................. 159
T2CON Register ................................................................. 25
Temperature Indicator
Associated Registers................................................ 112
Temperature Indicator Module.......................................... 111
Thermal Considerations.................................................... 236
Timer0............................................................................... 141
Associated Registers................................................ 143
Operation.................................................................. 141
Specifications ........................................................... 242
Timer1............................................................................... 145
Associated registers ......................................... 155, 207
Asynchronous Counter Mode................................... 147
Reading and Writing......................................... 147
Clock Source Selection............................................. 146
Interrupt .................................................................... 149
Operation.................................................................. 146
Operation During Sleep............................................ 149
Prescaler .................................................................. 147
Specifications ........................................................... 242
Timer1 Gate
Negative Edge) .................................................107
IOCAP (Interrupt-on-Change PORTA
Positive Edge)...................................................107
LATA (Data Latch PORTA).......................................103
NCOxACCH (NCOx Accumulator High Byte) ...........190
NCOxACCL (NCOx Accumulator Low Byte).............190
NCOxACCU (NCOx Accumulator Upper Byte).........190
NCOxCLK (NCOx Clock Control) .............................189
NCOxCON (NCOx Control) ......................................189
NCOxINCH (NCOx Increment High Byte).................191
NCOxINCL (NCOx Increment Low Byte) ..................191
OPTION_REG (OPTION) .........................................143
OSCCON (Oscillator Control) .....................................51
OSCSTAT (Oscillator Status) .....................................52
PCON (Power Control Register).................................59
PCON (Power Control) ...............................................59
PIE1 (Peripheral Interrupt Enable 1)...........................67
PIE2 (Peripheral Interrupt Enable 2)...........................68
PIE3 (Peripheral Interrupt Enable 3)...........................69
PIR1 (Peripheral Interrupt Register 1) ........................70
PIR2 (Peripheral Interrupt Request 2) ........................71
PIR3 (Peripheral Interrupt Request 3) ........................72
PMADRL (Program Memory Address)........................96
PMCON1 (Program Memory Control 1)......................97
PMCON2 (Program Memory Control 2)......................98
PMDATH (Program Memory Data).............................96
PMDATL (Program Memory Data)..............................96
PMDRH (Program Memory Address)..........................96
PORTA......................................................................102
PWMxCON (PWM Control).......................................165
PWMxDCH (PWM Control).......................................166
PWMxDCL (PWM Control) .......................................166
Special Function, Summary........................................25
STATUS......................................................................18
T1CON (Timer1 Control)...........................................153
T1GCON (Timer1 Gate Control)...............................154
T2CON......................................................................159
TRISA (Tri-State PORTA).........................................102
VREGCON (Voltage Regulator Control).....................78
WDTCON (Watchdog Timer Control)..........................81
WPUA (Weak Pull-up PORTA).................................104
RESET ..............................................................................221
Reset...................................................................................53
Reset Instruction .................................................................56
Resets.................................................................................53
Associated Registers ..................................................60
Revision History ................................................................267
Selecting Source .............................................. 147
TMR1H Register....................................................... 145
TMR1L Register........................................................ 145
Timer2............................................................................... 157
Associated registers ................................................. 160
Timers
Timer1
T1CON ............................................................. 153
T1GCON........................................................... 154
Timer2
T2CON ............................................................. 159
Timing Diagrams
A/D Conversion......................................................... 243
A/D Conversion (Sleep Mode).................................. 244
Brown-out Reset (BOR)............................................ 240
Brown-out Reset Situations ........................................ 55
CLKOUT and I/O ...................................................... 239
Clock Timing............................................................. 238
Comparator Output................................................... 131
INT Pin Interrupt ......................................................... 64
Internal Oscillator Switch Timing ................................ 49
Reset Start-up Sequence ........................................... 57
Reset, WDT, OST and Power-up Timer................... 240
Timer0 and Timer1 External Clock ........................... 241
Timer1 Incrementing Edge ....................................... 149
Wake-up from Interrupt............................................... 76
Timing Parameter Symbology .......................................... 237
TMR0 Register.................................................................... 25
TMR1H Register................................................................. 25
TMR1L Register.................................................................. 25
TMR2 Register.................................................................... 25
TRIS.................................................................................. 224
TRISA Register........................................................... 25, 102
S
Software Simulator (MPLAB SIM).....................................251
Special Function Registers (SFRs).....................................25
Stack ...................................................................................32
DS41615A-page 272
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
V
VREF. SEE ADC Reference Voltage
VREGCON Register ........................................................... 78
W
Wake-up Using Interrupts ................................................... 75
Watchdog Timer (WDT)...................................................... 56
Associated Registers .................................................. 82
Modes ......................................................................... 80
Specifications............................................................ 241
WDTCON Register ............................................................. 81
WPUA Register................................................................. 104
Write Protection .................................................................. 42
WWW Address.................................................................. 275
WWW, On-Line Support ....................................................... 7
2011 Microchip Technology Inc.
Preliminary
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PIC12(L)F1501
NOTES:
DS41615A-page 274
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011 Microchip Technology Inc.
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PIC12(L)F1501
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
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Please list the following information, and use this outline to provide us with your comments about this document.
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Device: PIC12(L)F1501
Questions:
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7. How would you improve this document?
DS41615A-page 276
Preliminary
2011 Microchip Technology Inc.
PIC12(L)F1501
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
PART NO.
X
/XX
XXX
-
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
Pattern
a)
PIC12LF1501T - I/SN
Tape and Reel,
Industrial temperature,
SOIC package
b)
c)
PIC12F1501 - I/P
Industrial temperature
PDIP package
Device:
PIC12F1501, PIC12LF1501
PIC12F1501 - E/MF
Extended temperature,
DFN package
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Package:
MC
MF
MS
P
=
=
=
=
=
Micro Lead Frame (DFN) 2x3
Micro Lead Frame (DFN) 3x3
MSOP
Plastic DIP
SOIC
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
SN
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Pattern:
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2011 Microchip Technology Inc.
Preliminary
DS41615A-page 277
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
08/02/11
DS41615A-page 278
Preliminary
2011 Microchip Technology Inc.
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