PIC12F519T-I/MC_技术文档

PIC12F519

Data Sheet

8-Pin, 8-Bit Flash Microcontroller

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

Preliminary

DS41319A

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The

Embedded Control Solutions Company are registered

trademarks of Microchip Technology Incorporated in the

U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select

Mode, Smart Serial, SmartTel, Total Endurance, UNI/O,

WiperLock and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41319A-page ii

Preliminary

PIC12F519

8-Pin, 8-Bit Flash Microcontroller

High-Performance RISC CPU:

Low-Power Features/CMOS Technology:

• Only 33 Single-Word Instructions

• Standby Current:

- 100 nA @ 2.0V, typical

• Operating Current:

• All Single-Cycle Instructions except for Program

Branches which are Two-Cycle

- 15 μA @ 32 kHz, 2.0V, typical

- 170 μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

- 1 μA @ 2.0V, typical

- 7 μA @ 5.0V, typical

• Two-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

for Data and Instructions

• Operating Speed:

- DC – 8 MHz Oscillator

- DC – 500 ns instruction cycle

• High Endurance Program and Flash Data Memory

Cells

- 100,000 write Program Memory endurance

- 1,000,000 write Flash Data Memory endurance

- Program and Flash Data retention: >40 years

• Fully Static Design

• Wide Operating Voltage Range: 2.0V to 5.5V

- Wide temperature range

• On-chip Flash Program Memory

- 1024 x 12

• General Purpose Registers (SRAM)

- 41 x 8

• Flash Data Memory

- 64 x 8

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

Special Microcontroller Features:

• 8 MHz Precision Internal Oscillator

- Factory calibrated to ±1%

Peripheral Features:

• 6 I/O Pins

- 5 I/O pins with individual direction control

- 1 input-only pin

- High current sink/source for direct LED drive

• 8-bit Real-Time Clock/Counter (TMR0) with 8-bit

Programmable Prescaler.

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Debugging (ICD) Support

• Power-on Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with Dedicated On-Chip

RC Oscillator for Reliable Operation

• Programmable Code Protection

• Multiplexed MCLR Input Pin

• Internal Weak Pull-ups on I/O Pins

• Power-Saving Sleep mode

• Wake-up from Sleep on Pin Change

• Selectable Oscillator Options:

- INTRC: 4 MHz or 8 MHz precision Internal

RC oscillator

- EXTRC: External low-cost RC oscillator

- XT:

- LP:

Standard crystal/resonator

Power-saving, low-frequency crystal

Preliminary

DS41319A-page 1

PIC12F519

FIGURE 1:

PIC12F519 8-PIN PDIP, SOIC, MSOP, 2X3 DFN DIAGRAM

PDIP, SOIC, MSOP

VSS

VDD

RB5/OSC1/CLKIN

RB4/OSC2

1

2

3

4

8

7

RB0/ICSPDAT

RB1/ICSPCLK

RB2/T0CKI

6

5

RB3/MCLR/VPP

DFN

VDD

1

8

7

6

5

VSS

RB5/OSC1/CLKIN

RB4/OSC2

2

3

4

RB0/ICSPDAT

RB1/ICSPCLK

RB2/T0CKI

RB3/MCLR/VPP

Program

Memory

Data Memory

8-bit A/D

Channels

Device

I/O

Comparators Timers 8-bit

Flash

(bytes)

Flash (words) SRAM (bytes)

1024 41

PIC12F519

64

6

0

1

0

DS41319A-page 2

Preliminary

PIC12F519

Table of Contents

General Description .............................................................................................................................................................................. 5

PIC12F519 Device Varieties ................................................................................................................................................................ 7

Architectural Overview .......................................................................................................................................................................... 9

Memory Organization .......................................................................................................................................................................... 13

Flash Data Memory ............................................................................................................................................................................. 21

I/O Port ................................................................................................................................................................................................ 25

Timer0 Module and TMR0 Register .................................................................................................................................................... 29

Special Features Of The CPU ............................................................................................................................................................ 35

Instruction Set Summary ..................................................................................................................................................................... 49

Development Support ......................................................................................................................................................................... 57

Electrical Characteristics ..................................................................................................................................................................... 61

DC and AC Characteristics Graphs and Charts .................................................................................................................................. 73

Packaging Information ........................................................................................................................................................................ 75

Index ................................................................................................................................................................................................... 81

The Microchip Web Site ...................................................................................................................................................................... 83

Customer Change Notification Service ............................................................................................................................................... 83

Customer Support ............................................................................................................................................................................... 83

Reader Response ............................................................................................................................................................................... 84

Product Identification System ............................................................................................................................................................. 85

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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To determine if an errata sheet exists for a particular device, please check with one of the following:

•

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Preliminary

DS41319A-page 3

PIC12F519

NOTES:

DS41319A-page 4

Preliminary

PIC12F519

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC12F519 device fits in applications ranging from

personal care appliances and security systems to low-

power remote transmitters/receivers. The Flash

technology makes customizing application programs

(transmitter codes, appliance settings, receiver

frequencies, etc.) extremely fast and convenient. The

small footprint packages, for through hole or surface

mounting, make these microcontrollers perfect for

applications with space limitations. Low cost, low

power, high performance, ease of use and I/O flexibility

make the PIC12F519 device very versatile even in

areas where no microcontroller use has been

considered before (e.g., timer functions, logic and

PLDs in larger systems and coprocessor applications).

The PIC12F519 device from Microchip Technology is

low-cost, high-performance, 8-bit, fully-static, Flash-

based CMOS microcontrollers. They employ a RISC

architecture with only 33 single-word/single-cycle

instructions. All instructions are single cycle except for

program branches, which take two cycles. The

PIC12F519 device delivers performance an order of

magnitude higher than their competitors in the same

price category. The 12-bit wide instructions are highly

symmetrical, resulting in

a

typical 2:1 code

compression over other 8-bit microcontrollers in its

class. The easy-to-use and easy to remember

instruction set reduces development time significantly.

The PIC12F519 product is equipped with special

features that reduce system cost and power

requirements. The Power-on Reset (POR) and Device

Reset Timer (DRT) eliminate the need for external

Reset circuitry. There are four oscillator configurations

to choose from including INTRC Internal Oscillator

mode and the power-saving LP (Low-power) Oscillator

mode. Power-Saving Sleep mode, Watchdog Timer

and code protection features improve system cost,

power and reliability.

The PIC12F519 device is available in the cost-effective

Flash programmable version, which is suitable for

production in any volume. The customer can take full

advantage of Microchip’s price leadership in Flash

programmable microcontrollers, while benefiting from

the Flash programmable flexibility.

The PIC12F519 product is supported by a full-featured

macro assembler, a software simulator, an in-circuit

emulator, a low-cost development programmer and a

full featured programmer. All the tools are supported on

PC and compatible machines.

TABLE 1-1:

FEATURES AND MEMORY OF PIC12F519

PIC12F519

Clock

Maximum Frequency of Operation (MHz)

Flash Program Memory

SRAM Data Memory (bytes)

Flash Data Memory

8

Memory

1024

41

64

Peripherals

Features

Timer Module(s)

TMR0

Wake-up from Sleep on Pin Change

I/O Pins

Yes

5

Input Pins

1

Internal Pull-ups

Yes

In-Circuit Serial Programming™

Number of Instructions

Packages

Yes

33

8-pin PDIP, SOIC, MSOP, 2X3 DFN

The PIC12F519 device has Power-on Reset, selectable Watchdog Timer, selectable code-protect, high I/O current capability and

precision internal oscillator.

The PIC12F519 device uses serial programming with data pin RB0 and clock pin RB1.

Preliminary

DS41319A-page 5

PIC12F519

NOTES:

DS41319A-page 6

Preliminary

PIC12F519

2.2

Serialized Quick Turn

Programming^SM(SQTP^SM) Devices

2.0

PIC12F519 DEVICE VARIETIES

A variety of packaging options are available. Depending

on application and production requirements, the proper

device option can be selected using the information in

this section. When placing orders, please use the

PIC12F519 Product Identification System at the back of

this data sheet to specify the correct part number.

Microchip offers a unique programming service, where a

few user-defined locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a

unique number, which can serve as an entry code,

password or ID number.

2.1

Quick Turn Programming (QTP)

Devices

Microchip offers a QTP programming service for factory

production orders. This service is made available for

users who choose not to program medium-to-high

quantity units and whose code patterns have stabilized.

The devices are identical to the Flash devices but with

all Flash locations and fuse options already

programmed by the factory. Certain code and prototype

verification procedures do apply before production

shipments are available. Please contact your local

Microchip Technology sales office for more details.

Preliminary

DS41319A-page 7

PIC12F519

NOTES:

DS41319A-page 8

Preliminary

PIC12F519

The ALU is 8 bits wide and capable of addition,

subtraction, shift and logical operations. Unless other-

wise mentioned, arithmetic operations are two’s

complement in nature. In two-operand instructions, one

operand is typically the W (working) register. The other

operand is either a file register or an immediate

constant. In single operand instructions, the operand is

either the W register or a file register.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC12F519 device can

be attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC12F519 device uses a Harvard architec-

ture in which program and data are accessed on sep-

arate buses. This improves bandwidth over traditional

von Neumann architectures where program and data

are fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12 bits wide, making it possible to have

all single-word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

execution of instructions. Consequently, all instruc-

tions (33) execute in a single cycle (500 ns @ 8 MHz,

1 μs @ 4 MHz) except for program branches.

The W register is an 8-bit working register used for ALU

operations. It is not an addressable register.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC) and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a borrow and digit borrow out bit, respec-

tively, in subtraction. See the SUBWF and ADDWF

instructions for examples.

A simplified block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-2.

Table 3-1 below lists memory supported by the

PIC12F519 device.

TABLE 3-1:

PIC12F519 MEMORY

Program

Data Memory

Memory

Device

Flash

Data

(bytes)

Flash

(words)

SRAM

(bytes)

PIC12F519

1024

41

64

The PIC12F519 device can directly or indirectly

address its register files and data memory. All Special

Function Registers (SFR), including the PC, are

mapped in the data memory. The PIC12F519 device

has a highly orthogonal (symmetrical) instruction set

that makes it possible to carry out any operation, on

any register, using any addressing mode. This symmet-

rical nature and lack of “special optimal situations”

make programming with the PIC12F519 device simple,

yet efficient. In addition, the learning curve is reduced

significantly.

The PIC12F519 device contains an 8-bit ALU and

working register. The ALU is a general purpose arith-

metic unit. It performs arithmetic and Boolean functions

between data in the working register and any register

file.

Preliminary

DS41319A-page 9

PIC12F519

FIGURE 3-1:

PIC12F519 ARCHITECTURAL BLOCK DIAGRAM

11

8

PORTB

Data Bus

RAM

Flash Program

Memory

Program Counter

RB0/ISCPDAT

RB1/ISCPCLK

RB2/T0CKI

RB3/MCLR/VPP

RB4/OSC2

1K x 12

Flash Data

Memory

64x8

Stack 1

Stack 2

File

RB55/OSC1/CLKIN

Registers

Program

Bus

12

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

5

Direct Addr

5-7

FSR Reg

STATUS Reg

8

3

MUX

Device Reset

Timer

Instruction

Decode &

Control

ALU

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

OSC1/CLKIN

OSC2

W Reg

Internal RC

OSC

Timer0

MCLR

VDD, VSS

DS41319A-page 10

Preliminary

PIC12F519

TABLE 3-2:

PIC12F519 PINOUT DESCRIPTION

Output

Type

Name

Function

Type

Input Type

Description

RB0/ICSPDAT

RB0

I/O

TTL

ST

CMOS

—

Bidirectional I/O port with weak pull-up

ICSPDAT

RB1

I/O

ICSP™ mode Schmitt Trigger

Bidirectional I/O port with weak pull-up

ICSP™ mode Schmitt Trigger

Bidirectional I/O port

RB1/ICSPCLK

RB2/T0CKI

I/O

TTL

ST

ICSPCLK

RB2

I

I/O

TTL

ST

CMOS

—

T0CKI

I

Timer0 clock input

RB3/MCLR/VPP RB3

MCLR

TTL

ST

—

Standard TTL input with weak pull-up

—

MCLR input – Weak pull-up always enabled in

this mode

VPP

I

I/O

O

I/O

I

High Voltage

—

CMOS

XTAL

CMOS

—

Test mode high voltage pin

Bidirectional I/O port

RB4/OSC2

RB4

OSC2

TTL

—

XTAL oscillator output pin

Bidirectional I/O port

RB5/OSC1/CLKINRB5

OSC1

TTL

XTAL

ST

XTAL oscillator input pin

CLKIN

VDD

I

—

EXTRC Schmitt Trigger input

Positive supply for logic and I/O pins

Ground reference for logic and I/O pins

VDD

P

—

VSS

P

—

Legend:

I = Input, O = Output, I/O = Input/Output, P = Power, — = Not Used, TTL = TTL input,

ST = Schmitt Trigger input, AN = Analog Voltage

Preliminary

DS41319A-page 11

PIC12F519

3.1

Clocking Scheme/Instruction

Cycle

3.2

Instruction Flow/Pipelining

An instruction cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the PC to change (e.g., GOTO), then two cycles

are required to complete the instruction (Example 3-1).

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the PC

is incremented every Q1 and the instruction is fetched

from program memory and latched into the instruction

register in Q4. It is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow is shown in Figure 3-2 and Example 3-1.

A fetch cycle begins with the PC incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the Instruction Register (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2:

CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

PC

Internal

Phase

Clock

PC

PC+1

PC+2

Fetch INST (PC)

Execute INST (PC – 1)

Fetch INST (PC + 1)

Execute INST (PC)

Fetch INST (PC + 2)

Execute INST (PC + 1)

EXAMPLE 3-1:

INSTRUCTION PIPELINE FLOW

1. MOVLW 03H

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTB, BIT1

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

DS41319A-page 12

Preliminary

PIC12F519

FIGURE 4-1:

MEMORY MAP

4.0

MEMORY ORGANIZATION

The PIC12F519 memories are organized into program

memory and data memory (SRAM).The self-writable

portion of the program memory called Flash data mem-

ory is located at addresses at 400h-43Fh. All program

mode commands that work on the normal Flash mem-

ory work on the Flash data memory. This includes bulk

erase, row/column/cycling toggles, Load and Read

data commands (Refer to Chapter 6 for more details).

For devices with more than 512 bytes of program mem-

ory, a paging scheme is used. Program memory pages

are accessed using one STATUS register bit. For the

PIC12F519, with data memory register files of more

than 32 registers, a banking scheme is used. Data

memory banks are accessed using the File Select

Register (FSR).

000h

On-chip User

Program

Memory (Page 0)

1FFh

200h

On-chip User

Program

Memory (Page 1)

3FEh

3FFh

400h

Reset Vector

Flash Data Memory

User ID Locations

43Fh

440h

443h

444h

447h

Backup OSCCAL

Locations

448h

4.1

Program Memory Organization for

the PIC12F519

Reserved

The PIC12F519 device has an 11-bit Program Counter

(PC) capable of addressing a 2K x 12 program memory

space. Program memory is partitioned into user memory,

data memory and configuration memory spaces.

49Fh

4A0h

Unimplemented

7FEh

7FFh

The user memory space is the on-chip user program

memory. As shown in Figure 4-1, It extends from 0x000

to 0x3FF and partitions into pages, including Reset

vector at address 0x3FF. Note that the PC will

increment from (0x000-0x3FF) then to 0x400, (not to

0x000).

Configuration Word

The data memory space is the Flash data memory

block and is located at addresses PC = 400h-43Fh. All

program mode commands that work on the normal

Flash memory work on the Flash data memory block.

This includes bulk erase, Load and Read data

commands.

The configuration memory space extends from 0x440

to 0x7FF. Locations from 0x448 through 0x49F are

reserved. The User ID locations extend from 0x440

through 0x443. The backup OSCCAL locations extend

from 0x444 through 0x447. The Configuration Word is

physically located at 0x7FF.

Refer to “PIC12F519 Memory Programming

Specification”, DS41316, for more detail.

Preliminary

DS41319A-page 13

PIC12F519

4.2.2

SPECIAL FUNCTION REGISTERS

4.2

Data Memory (SRAM and FSRs)

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions to control the

operation of the device (Table 4-1).

Data memory is composed of registers or bytes of

SRAM. Therefore, data memory for a device is speci-

fied by its register file. The register file is divided into

two functional groups: Special Function Registers

(SFR) and General Purpose Registers (GPR).

The Special Function Registers can be classified into

two sets. The Special Function Registers associated

with the “core” functions are described in this section.

Those related to the operation of the peripheral

features are described in the section for each

peripheral feature.

The Special Function Registers include the TMR0 reg-

ister, the Program Counter (PCL), the STATUS register,

the I/O register (port) and the File Select Register

(FSR). In addition, the EECON, EEDATA and EEADR

registers provide for interface with the Flash data

memory.

The PIC12F519 register file is composed of 10 Special

Function Registers and 41 General Purpose Registers.

4.2.1

GENERAL PURPOSE REGISTER

FILE

The General Purpose Register file is accessed, either

directly or indirectly, through the File Select Register

(FSR). See Section 4.8 “Indirect Data Addressing:

INDF and FSR Registers”.

FIGURE 4-2:

REGISTER FILE MAP

FSR<5>

File Address

00h

0

1

INDF⁽¹⁾

TMR0

PCL

INDF⁽¹⁾

EECON

PCL

20h

01h

02h

03h

04h

05h

06h

STATUS

FSR

STATUS

FSR

OSCCAL

PORTB

EEDATA

EEADR

07h

08h

General

Purpose

Registers

Address map

back to

addresses

in Bank 0

09h

0Ah

2Fh

30h

0Fh

10h

General

Purpose

Registers

General

Purpose

Registers

1Fh

3Fh

Bank 0

Bank 1

Note 1: Not a physical register.

DS41319A-page 14

Preliminary

PIC12F519

TABLE 4-1:

SPECIAL FUNCTION REGISTER SUMMARY

Value on

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Power-on

Reset

N/A

00h

01h

TRIS

—

TRIS5

TRIS4

TRIS3

TRIS2

TRIS1

TRIS0

--11 1111

1111 1111

xxxx xxxx

1111 1111

0001 1xxx

110x xxxx

1111 111-

--xx xxxx

XXX0 0000

OPTION

INDF

Contains Control Bits to Configure Timer0 and Timer0/WDT Prescaler

Uses Contents of FSR to Address Data Memory (not a physical register)

Timer0 Module Register

TMR0

(1)

02h

PCL

Low Order 8 bits of PC

03h

04h

05h

06h

21h

25h

26h

STATUS

FSR

RBWUF

—

PA0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

OSCCAL

PORTB

EECON

EEDATA

EEADR

CAL6

—

CAL5

—

CAL4

RB5

—

CAL3

RB4

CAL2

RB3

CAL1

RB2

CAL0

RB1

WR

—

RB0

RD

—

FREE

WRERR

WREN

EEDATA7 EEDATA6 EEDATA5 EEDATA4 EEDATA3 EEDATA2 EEDATA1 EEDATA0 xxxx xxxx

EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 --xx xxxx

—

Legend:

x = unknown, u = unchanged, – = unimplemented, read as ‘0’ (if applicable). Shaded cells = unimplemented or unused

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.6 “Program Counter” for an

explanation of how to access these bits.

Preliminary

DS41319A-page 15

PIC12F519

For example, CLRF STATUS, will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u= unchanged).

4.3

STATUS register

This register contains the arithmetic status of the ALU,

the Reset status and the page preselect bit.

Therefore, it is recommended that only BCF, BSF and

MOVWFinstructions be used to alter the STATUS regis-

ter. These instructions do not affect the Z, DC or C bits

from the STATUS register. For other instructions which

do affect Status bits, see Section 9.0 “Instruction Set

Summary”.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

REGISTER 4-1:

STATUS: STATUS REGISTER

R/W-0

RBWUF

bit 7

U-0

—

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

RBWUF: Wake-up From Sleep on Pin Change bit

1= Reset due to wake-up from Sleep on pin change

0= After power-up or other Reset

bit 6

bit 5

Unimplemented: Do not use

PA0: Program Page Preselect bit

1= Page 1 (000h-1FFh)

0= Page 0 (200h-3FFh)

bit 4

bit 3

bit 2

bit 1

TO: Time-out bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF:

1= A carry from the 4th low-order bit of the result occurred

0= A carry from the 4th low-order bit of the result did not occur

SUBWF:

1= A borrow from the 4th low-order bit of the result did not occur

0= A borrow from the 4th low-order bit of the result occurred

bit 0

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF:

1= A carry occurred

SUBWF:

1= A borrow did not occur

RRF or RLF:

Load bit with LSb or MSb, respectively

0= A carry did not occur 0= A borrow occurred

DS41319A-page 16

Preliminary

PIC12F519

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION regis-

ter. A Reset sets the OPTION<7:0> bits.

4.4

OPTION Register

The OPTION register is a 8-bit wide, write-only register,

which contains various control bits to configure the

Timer0/WDT prescaler and Timer0.

Note:

If the T0SC bit is set to ‘1’, it will override

the TRIS function on the T0CKI pin.

REGISTER 4-2:

OPTION: OPTION REGISTER

W-1

PS2

W-1

PS1

W-1

PS0

RBWU

bit 7

RBPU

T0CS

T0SE

PSA

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBWU: Enable Wake-up On Pin Change bit

1= Disabled

0= Enabled

RBPU: Enable Weak Pull-ups bit

1= Disabled

0= Enabled

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (CLKOUT)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler assigned to the WDT

0= Prescaler assigned to Timer0

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Preliminary

DS41319A-page 17

PIC12F519

4.5

OSCCAL Register

The Oscillator Calibration (OSCCAL) register is used

to calibrate the 8 MHz internal oscillator macro. It

contains 7 bits of calibration that uses a two’s

complement scheme for controlling the oscillator speed.

See Register 4-3 for details.

REGISTER 4-3:

OSCCAL: OSCILLATOR CALIBRATION REGISTER

R/W-1

CAL6

R/W-1

CAL5

R/W-1

CAL4

R/W-1

CAL3

R/W-1

CAL2

R/W-1

CAL1

R/W-1

CAL0

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-1

CAL<6:0>: Oscillator Calibration bits

0111111= Maximum frequency

•

0000001

0000000= Center frequency

1111111

•

1000000=Minimum frequency

bit 0

Unimplemented: Read as ‘0’

DS41319A-page 18

Preliminary

PIC12F519

4.6.1

EFFECTS OF RESET

4.6

Program Counter

The PC is set upon a Reset, which means that the PC

addresses the last location in the last page (i.e., the

oscillator calibration instruction). After executing

MOVLW XX, the PC will roll over to location 00h and

begin executing user code.

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

The STATUS register page preselect bits are cleared

upon a Reset, which means that page 0 is pre-selected.

For a GOTO instruction, bits <8:0> of the PC are pro-

vided by the GOTO instruction word. The Program

Counter (PCL) is mapped to PC<7:0>. Bit 5 of the STA-

TUS register provides page information to bit 9 of the

PC (Figure 4-3).

Therefore, upon a Reset, a GOTO instruction will

automatically cause the program to jump to page 0 until

the value of the page bits is altered.

For a CALL instruction, or any instruction where the

PCL is the destination, bits <7:0> of the PC again are

provided by the instruction word. However, PC<8>

does not come from the instruction word, but is always

cleared (Figure 4-3).

4.7

Stack

The PIC12F519 device has a two-deep, 12-bit wide

hardware PUSH/POP stack.

A CALLinstruction will PUSH the current value of Stack

1 into Stack 2 and then PUSH the current PC value,

incremented by one, into Stack Level 1. If more than two

sequential CALLs are executed, only the most recent two

return addresses are stored.

Instructions where the PCL is the destination, or modify

PCL instructions, include MOVWF PC, ADDWF PCand

BSF PC,5.

Note:

Because PC<8> is cleared in the CALL

instruction or any modify PCL instruction,

all subroutine calls or computed jumps are

limited to the first 256 locations of any

program memory page (512 words long).

A RETLW instruction will POP the contents of Stack

Level 1 into the PC and then copy Stack Level 2

contents into Stack Level 1. If more than two sequential

RETLWs are executed, the stack will be filled with the

address previously stored in Stack Level 2. Note that

the W register will be loaded with the literal value

specified in the instruction. This is particularly useful for

the implementation of data look-up tables within the

program memory.

FIGURE 4-3:

LOADING OF PC

BRANCH INSTRUCTIONS

GOTOInstruction

10 9 8 7

0

Note 1: There are no Status bits to indicate stack

PC

PCL

overflows or stack underflow conditions.

2: There are no instruction mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL

and RETLWinstructions.

Instruction Word

0

PA0

7

Status

CALLor Modify PCL Instruction

10 9 8 7

0

PCL

PC

Instruction Word

Reset to ‘0’

PA0

7

0

Status

Preliminary

DS41319A-page 19

PIC12F519

EXAMPLE 4-1:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

4.8

Indirect Data Addressing: INDF

and FSR Registers

The INDF register is not

a physical register.

MOVLW 0x10

MOVWF FSR

CLRF INDF

;initialize pointer

;to RAM

;clear INDF

;register

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

00h. Writing to the INDF Register indirectly results in a

no-operation (although Status bits may be affected).

INCF

BTFSC FSR,4

GOTO

FSR,F

;inc pointer

;all done?

;NO, clear next

The FSR is an 8-bit wide register. It is used in conjunc-

tion with the INDF Register to indirectly address the

data memory area.

:

;YES, continue

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

FSR<5> is used to select between banks (0= Bank 0,

1= Bank 1).

FSR<7:6> are unimplemented and read as ‘11’.

FIGURE 4-4:

DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR) 0

(FSR)

4

(opcode)

0

5

4

5

Location Select

Bank Select

Location Select

Bank

0

1

00h

Data

Memory

0Fh

10h

1Fh

Bank 0

3Fh

Bank 1

DS41319A-page 20

Preliminary

PIC12F519

Only the lower 8 bits of each word is readable or

writable in User mode.

5.0

FLASH DATA MEMORY

The Flash data memory resides at locations

0x400-0x43F. It is physically attached to the Flash pro-

gram memory block. The Flash memory consists of 8

rows and has self-write capability of up to 64 bytes.

This memory block is not directly mapped in the regis-

ter file space. Instead, it is indirectly addressed through

the Special Function Registers. There are three SFRs

used to read and write this memory:

The Flash data memory allows byte read and write. A

byte write automatically erases the row in which the

target byte is located and writes the new data (erase

before write). During the operation of read/write, the

CPU stalls.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device.

• EEDATA (Register 5-1)

• EEADR (Register 5-2)

• EECON (Register 5-3)

When the device is code-protected, the CPU may

continue to read and write the Flash data memory and

read the program memory. When code-protected, the

device programmer can no longer access data or

program memory.

EEDATA holds the 8-bit data for read/write, and

EEADR holds the address of the EEDATA location

being accessed. The effective program counter

address is EEADR + 400h.

• EEADR (00h), PC (400h)

• EEADR (01h), PC (401h)

REGISTER 5-1:

EEDATA: FLASH DATA REGISTER

R/W-x

EEDATA7

bit 7

R/W-x

EEDATA6

EEDATA5

EEDATA4

EEDATA3

EEDATA2

EEDATA1

EEDATA0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n = Value at POR

bit 7-0

EEDATA<7:0>: 8-bits of data to be read from/written to data Flash

Preliminary

DS41319A-page 21

PIC12F519

REGISTER 5-2:

EEADR: FLASH ADDRESS REGISTER

U-0

—

U-0

—

R/W-x

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Do not use

EEADR<5:0>: 6-bits of address to be read from/written to data Flash

REGISTER 5-3:

EECON: FLASH CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

FREE

R/W-0

WREN

R/W-0

WR

R/W-0

RD

WRERR

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-5

bit 4

Unimplemented: Do not use

FREE: Flash Data Memory Row Erase Enable Bit

1= Program memory row being pointed to by EEADR will be erased on the next write cycle. No write

will be performed. This bit is cleared at the completion of the erase operation.

0= Perform write only

bit 3

bit 2

bit 1

bit 0

WRERR: Write Error Flag bit

1= A write operation terminated prematurely (by device Reset)

0= Write operation completed successfully

WREN: Write Enable bit

1= Allows write cycle to Flash data memory

0= Inhibits write cycle to Flash data memory

WR: Write Control bit

1= Initiate a erase or write cycle

0= Write/Erase cycle is complete

RD: Read Control bit

1= Initiate a read of Flash data memory

0= Do not read Flash data memory

DS41319A-page 22

Preliminary

PIC12F519

EXAMPLE 5-2:

ERASE DATA MEMORY

ROW

5.1

Reading Data Memory

To read a memory location, the user must write the

address to be read into the EEADR register and then

set the RD bit in the EECON register. The data will be

available in the next instruction cycle. The CPU will

stall during read operation.

BSF

FSR,5

;SWITCH TO BANK 1

MOVLW EE_ADR_ERASE ;LOAD ADDRESS TO ERASE

MOVWF EEADR

;LOAD ADDRESS TO SFR

; SELECT ERASE

; ENABL FLASH PROG’ING

; INITITATE ERASE

BSF

EECON,FREE

EECON,WREN

EECON,WR

EXAMPLE 5-1:

FLASH DATA MEMORY

READ

xxx

;NEXT INSTRUCTION

BSF

FSR,5

;SWITCH TO BANK 1

MOVLW

BSF

INSTRUCTION

EE_ADR_READ;LOAD ADDRESS TO READ

EECON,RD

;INITITATE THE READ

Note 1: The FREE bit may be set by any com-

mand normally used by the core. How-

ever, the WREN and WR bits can only be

set using a series of BSF commands, as

documented in Example 5-2. No other

sequence of commands will work, no

exceptions.

NOP

MOVF

;INSTRUCTION IGNORED

;GET NEW DATA

EEDATA,W

Note: Only a BSF command will work to enable the

Flash data memory read documented in

Example 5-1. No other sequence of com-

mands will work, no exceptions.

2: The upper 3 bits of the EEADR register

indicates which row is to be erased.

5.3

Writing a Data Memory Word

5.2

Erasing a Data Memory Row

To write a memory location, the user must write the

address to be written to into the EEADR register. He

must then load the data to be written into the EEDATA

register. Once the data and address have been

loaded, a specific sequence must be executed to

initiate the write to the program memory. The

sequence is as follows:

In order to write new data to the Flash data memory,

the program memory row that is being addressed by

EEADR<5:0> must be erased.

To prevent a spurious row erasure, a specific

sequence must be executed to initiate the erase to the

program memory. The sequence is as follows:

• Set the WREN bit (enable writes to the Flash data

memory array)

- Set the FREE bit (enable Flash data memory

row erase)

• Set the WR bit (initiates the write to the Flash data

memory array)

- Set the WREN bit (enable writes to the Flash

data memory array)

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in hard-

ware.

- set the WR bit (initiates the row erase of the

Flash data memory array)

If the WREN bit is not set in the instruction cycle after

the FREE bit is set, the FREE bit will be cleared in

hardware.

This sequence is to prevent an accidental write to the

Flash memory.

If the WR bit is not set in the instruction cycle after the

WREN bit is set, the WREN bit will be cleared in

hardware.

Preliminary

DS41319A-page 23

PIC12F519

EXAMPLE 5-3:

DATA MEMORY WRITE

5.4

DATA MEMORY OPERATION

DURING CODE-PROTECT

BSF

FSR,5

;SWITCH TO BANK 1

;LOAD ADDRESS TO

;WRITE

;INTO EEADR

;REGISTER

MOVLW EE_ADR_WRITE

Data memory can be code-protected by programming

the CPDF bit in the Configuration Word (Register 8-1)

to ‘0’.

MOVWF EEADR

MOVLW EE_DATA_TO_WRITE;LOAD DATA TO

MOVWF EEDATA

;INTO EEDATA

;REGISTER

BSF

EECON,WREN

EECON,WR

;ENABLE WRITES

;START WRITE

;SEQUENCE

NOP

;WAIT AS READ

;INSTRUCTION

;IS DECODED

;INSTRUCTION

IGNORED

Note 1: Only a series of BSF commands will work

to enable the memory write sequence

documented in Example 5-3. No other

sequence of commands will work, no

exceptions.

2: For reads, erases and writes to the Flash

data memory, there is no need to insert a

NOP into the user code as is done on

mid-range devices. The instruction imme-

diately

following

the

“BSF

EECON,WR/RD” will be fetched and

executed properly.

DS41319A-page 24

Preliminary

PIC12F519

6.2

TRIS Registers

6.0

I/O PORT

The Output Driver Control registers are loaded with

the contents of the W Register by executing the TRIS

f instruction. A ‘1’ from a TRIS Register bit puts the

corresponding output driver in a high-impedance

(Input) mode. A ‘0’ puts the contents of the output data

latch on the selected pins, enabling the output buffer.

As with any other register, the I/O register(s) can be

written and read under program control. However, read

instructions (e.g., MOVF PORTB,W) always read the I/O

pins independent of the pin’s Input/Output modes. On

Reset, all I/O ports are defined as input (inputs are at

high-impedance) since the I/O control registers are all

set.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon Reset.

6.1

PORTB

Note:

If the T0CS bit is set to ‘1’, it will override

PORTB is an 8-bit I/O register. Only the low-order 6 bits

are used (RB<5:0>). Bits 7 and 6 are unimplemented

and read as ‘0’s. Please note that RB3 is an input-only

pin. The Configuration Word can set several I/O’s to

alternate functions. When acting as alternate functions,

the pins will read as ‘0’ during a port read. Pins RB0,

RB1, and RB3 can be configured with weak pull-ups

and also for wake-up on change. The wake-up on

change and weak pull-up functions are not pin select-

able. If RB3/MCLR is configured as MCLR, weak pull-

up is always on and wake-up on change for this pin is

not enabled.

the TRIS function on the T0CKI pin.

TABLE 6-1:

Device

PIC12F519

Note 1: When MCLREN = 1, the weak pull-up on RB3/MCLR is always enabled.

WEAK PULL-UP ENABLED PINS

RB0 Weak Pull-up RB1 Weak Pull-up RB3 Weak Pull-up⁽¹⁾RB4 Weak Pull-up

Yes

No

Preliminary

DS41319A-page 25

PIC12F519

REGISTER 6-1:

PORTB: PORTB REGISTER

U-0

—

R/W-x

RB5

R/W-x

RB4

R/W-x

RB3

R/W-x

RB2

R/W-x

RB1

R/W-x

RB0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘1’

RB<5:0>: PORTB I/O Pin bits

1= Port pin is >VIH min.

0= Port pin is <VIL max.

REGISTER 6-2:

TRIS: TRI-STATE PORTB REGISTER

U-0

—

W-1

—

TRIS5

TRIS4

TRIS3

TRIS2

TRIS1

TRIS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘1’

TRIS<5:0>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

DS41319A-page 26

Preliminary

PIC12F519

FIGURE 6-1:

PIC12F519 EQUIVALENT

CIRCUIT FOR A

6.3

I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 6-1. All port pins, except RB3 which is input only,

may be used for both input and output operations. For

input operations, these ports are non-latching. Any

input must be present until read by an input instruction

(e.g., MOVF PORTB, W). The outputs are latched and

remain unchanged until the output latch is rewritten. To

use a port pin as output, the corresponding direction

control bit in TRIS must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin (except RB3) can be programmed individually as

input or output.

SINGLE I/O PIN

Data

Bus

D

Q

Data

Latch

VDD

P

VDD

WR

Port

CK

N

I/O

W

Reg

D

Q

TRIS

Latch

VSS VSS

TRIS ‘f’

CK

Reset

(1)

RD Port

Note 1: See Table 3-2 for buffer type.

TABLE 6-2:

SUMMARY OF PORT REGISTERS

Value on

POR, BOR other Resets

Value on all

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

TRIS

—

RB5

RB4

RB3

RB2

RB1

RB0

--xx xxxx

--11 1111

--uu uuuu

--11 1111

TRIS5

TRIS4

TRIS3

TRIS2

TRIS1

TRIS0

Legend:

x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’

Preliminary

DS41319A-page 27

PIC12F519

EXAMPLE 6-1:

READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

6.4

I/O Programming Considerations

6.4.1

BIDIRECTIONAL I/O PORTS

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute the

bit operation and re-write the result. Caution must be

used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit 5 of PORTB will cause

all eight bits of PORTB to be read into the CPU, bit 5 to

be set and the PORTB value to be written to the output

latches. If another bit of PORTB is used as a bidirec-

tional I/O pin (say bit 0) and it is defined as an input at

this time, the input signal present on the pin itself would

be read into the CPU and rewritten to the data latch of

this particular pin, overwriting the previous content. As

long as the pin stays in the Input mode, no problem

occurs. However, if bit 0 is switched into Output mode

later on, the content of the data latch may now be

unknown.

;Initial PORTB Settings

;PORTB<5:3> Inputs

;PORTB<2:0> Outputs

;

PORTB latch PORTB pins

----------

PORTB, 5 ;--01 -ppp

PORTB, 4 ;--10 -ppp

----------

--11 pppp

BCF

MOVLW 007h;

TRIS PORTB

;--10 -ppp

--11 pppp

;

Note 1: The user may have expected the pin values to

be ‘--00 pppp’. The 2nd BCFcaused RB5 to

be latched as the pin value (High).

6.4.2

SUCCESSIVE OPERATIONS ON

I/O PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle (Figure 6-2).

Therefore, care must be exercised if a write followed by

a read operation is carried out on the same I/O port. The

sequence of instructions should allow the pin voltage to

stabilize (load dependent) before the next instruction

causes that file to be read into the CPU. Otherwise, the

previous state of that pin may be read into the CPU rather

than the new state. When in doubt, it is better to separate

these instructions with a NOP or another instruction not

accessing this I/O port.

Example 6-1 shows the effect of two sequential

Read-Modify-Write instructions (e.g., BCF, BSF, etc.)

on an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired OR”, “wired

AND”). The resulting high output currents may damage

the chip.

FIGURE 6-2:

SUCCESSIVE I/O OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC + 3

PC

PC + 1

PC + 2

This example shows a write to PORTB

followed by a read from PORTB.

Instruction

Fetched

MOVWFPORTB

MOVFPORTB, W

NOP

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

RB<5:0>

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Port pin

written here

Port pin

sampled here

Instruction

Executed

MOVWF PORTB

(Write to PORTB)

MOVF PORTB,W

(Read PORTB)

NOP

DS41319A-page 28

Preliminary

PIC12F519

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

T0SE bit (OPTION<4>) determines the source edge.

Clearing the T0SE bit selects the rising edge. Restric-

tions on the external clock input are discussed in detail

in Section 7.1 “Using Timer0 with an External

Clock”.

7.0

TIMER0 MODULE AND TMR0

REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select:

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit, PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is not

readable or writable. When the prescaler is assigned to

the Timer0 module, prescale values of 1:2, 1:4,...,

1:256 are selectable. Section 7.2 “Prescaler” details

the operation of the prescaler.

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In Timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 7-2 and Figure 7-3).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 7-1.

The Timer0 contained in the CPU core follows the

standard baseline definition.

FIGURE 7-1:

TIMER0 BLOCK DIAGRAM

Data Bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

Clocks

TMR0 Reg

Programmable

Prescaler

T0CKI

PSout

Sync

(2)

(1)

(2 cycle delay)

T0SE

3

(1)

PSA

(1)

PS2, PS1, PS0

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer.

FIGURE 7-2:

TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

Instruction

Fetch

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

NT0 + 1

T0

T0 + 1

T0 + 2

NT0

NT0 + 2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

Preliminary

DS41319A-page 29

PIC12F519

FIGURE 7-3:

TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

PC

(Program

Counter)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC – 1 PC PC + 1 PC + 2 PC + 3 PC + 4 PC + 5 PC + 6

MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Instruction

Fetch

T0

T0 + 1

NT0

NT0 + 1

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

TABLE 7-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

All Other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

OPTION

TRIS

Timer0 – 8-bit Real-Time Clock/Counter

xxxx xxxx

1111 1111

uuuu uuuu

1111 1111

--11 1111

N/A

RBWU

—

RBPU

—

T0CS T0SE

PSA

PS2

PS1

PS0

N/A

TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111

Legend:

x = unknown, u = unchanged, – = unimplemented, read as ‘0’, Shaded cells = unimplemented, read as ‘0’

DS41319A-page 30

Preliminary

PIC12F519

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler, so that the prescaler output is symmetrical.

For the external clock to meet the sampling require-

ment, the ripple counter must be taken into account.

Therefore, it is necessary for T0CKI to have a period of

at least 4 TOSC (and a small RC delay of 4 Tt0H) divided

by the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the

minimum pulse width requirement of Tt0H. Refer to

parameters 40, 41 and 42 in the electrical specification

of the desired device.

7.1

Using Timer0 with an External

Clock

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock require-

ment is due to internal phase clock (TOSC) synchroniza-

tion. Also, there is a delay in the actual incrementing of

Timer0 after synchronization.

7.1.1

EXTERNAL CLOCK

SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks (Figure 7-4).

Therefore, it is necessary for T0CKI to be high for at

least 2 TOSC (and a small RC delay of 2 Tt0H) and low

for at least 2 TOSC (and a small RC delay of 2 Tt0H).

Refer to the electrical specification of the desired

device.

7.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 7-4 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 7-4:

TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

misses sampling

External Clock Input or

(2)

Prescaler Output

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4 TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

Preliminary

DS41319A-page 31

PIC12F519

EXAMPLE 7-1:

CHANGING PRESCALER

(TIMER0 → WDT)

;Clear WDT

;Clear TMR0 and Prescaler

7.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module or as a postscaler for the Watchdog

Timer (WDT), respectively (see Section 8.6 “Watch-

dog Timer (WDT)”). For simplicity, this counter is

being referred to as “prescaler” throughout this data

sheet.

CLRWDT

CLRF

TMR0

MOVLW ‘00xx1111’b;These 3 lines (5, 6, 7)

OPTION

;are required only if

;desired

;PS<2:0> are 000 or 001

CLRWDT

MOVLW ‘00xx1xxx’b;Set Postscaler to

OPTION ;desired WDT rate

Note:

The prescaler may be used by either the

Timer0 module or the WDT, but not both.

Thus, a prescaler assignment for the

Timer0 module means that there is no

prescaler for the WDT and vice versa.

To change the prescaler from the WDT to the Timer0

module, use the sequence shown in Example 7-2. This

sequence must be used even if the WDT is disabled. A

CLRWDT instruction should be executed before

switching the prescaler.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x, etc.) will clear the prescaler. When assigned

to WDT, a CLRWDT instruction will clear the prescaler

along with the WDT. The prescaler is neither readable

nor writable. On a Reset, the prescaler contains all ‘0’s.

EXAMPLE 7-2:

CHANGING PRESCALER

(WDT → TIMER0)

;Clear WDT and

;prescaler

CLRWDT

MOVLW ‘xxxx0xxx’ ;Select TMR0, new

;prescale value and

;clock source

7.2.1

SWITCHING PRESCALER

ASSIGNMENT

OPTION

The prescaler assignment is fully under software

control (i.e., it can be changed “on-the-fly” during pro-

gram execution). To avoid an unintended device Reset,

the following instruction sequence (Example 7-1) must

be executed when changing the prescaler assignment

from Timer0 to the WDT.

DS41319A-page 32

Preliminary

PIC12F519

FIGURE 7-5:

BLOCK DIAGRAM OF THE TIMER0/ WDT PRESCALER⁽¹⁾

TCY (= FOSC/4)

Data Bus

8

0

1

M

U

X

1

0

M

U

X

T0CKI

Sync

2

Cycles

TMR0 Reg

T0SE

T0CS

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

8-to-1 MUX

PS<2:0>

PSA

1

0

WDT Enable bit

MUX

PSA

WDT

Time-Out

Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

Preliminary

DS41319A-page 33

PIC12F519

NOTES:

DS41319A-page 34

Preliminary

PIC12F519

The Sleep mode is designed to offer a very low current

Power-Down mode. The user can wake-up from Sleep

through a change on input pins or through a Watchdog

Timer time-out. Several oscillator options are also

made available to allow the part to fit the application,

including an internal 4 MHz or 8 MHz oscillator. The

EXTRC oscillator option saves system cost while the

LP crystal option saves power. A set of Configuration

bits are used to select various options.

8.0

SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits that deal with the needs of

real-time applications. The PIC12F519 microcontroller

has a host of such features intended to maximize

system reliability, minimize cost through elimination of

external components, provide power-saving operating

modes and offer code protection. These features are:

8.1

Configuration Bits

• Oscillator Selection

• Reset:

The PIC12F519 Configuration Words consist of 12 bits.

Configuration bits can be programmed to select various

device configurations. Two bits are for the selection of

the oscillator type; one bit is the Watchdog Timer enable

bit, one bit is the MCLR enable bit and one bit is for code

protection (Register 8-1).

- Power-on Reset (POR)

- Device Reset Timer (DRT)

- Wake-up from Sleep on Pin Change

• Watchdog Timer (WDT)

• Sleep

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

The PIC12F519 device has a Watchdog Timer, which

can be shut off only through Configuration bit WDTE. It

runs off of its own RC oscillator for added reliability. If

using XT or LP selectable oscillator options, there is

always an 18 ms (nominal) delay provided by the

Device Reset Timer (DRT), intended to keep the chip in

Reset until the crystal oscillator is stable. If using

INTRC or EXTRC, the DRT provides a 1 ms (nominal)

delay.

Preliminary

DS41319A-page 35

PIC12F519

REGISTER 8-1:

CONFIG: CONFIGURATION WORD REGISTER⁽¹⁾

—

CPDF

IOSCFS

MCLRE

CP

WDTE

FOSC1

FOSC0

bit 0

bit 7

bit 6

Unimplemented: Read as ‘1’

CPDF: Code Protection bit - Flash Data Memory

1= Code protection off

0= Code protection on

bit 5

bit 4

bit 3

bit 2

bit 1-0

IOSCFS: Internal Oscillator Frequency Select bit

1= 8 MHz INTOSC speed

0= 4 MHz INTOSC speed

MCLRE: Master Clear Enable bit

1= RB3/MCLR pin functions as MCLR

0= RB3/MCLR pin functions as RB3, MCLR internally tied to VDD

CP: Code Protection bit - User Program Memory

1= Code protection off

0= Code protection on

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

FOSC<1:0>: Oscillator Selection bits

00= LP oscillator with 18 ms DRT⁽²⁾

01= XT oscillator with 18 ms DRT⁽²⁾

10= INTOSC with 1 ms DRT⁽²⁾

11= EXTRC with 1 ms DRT⁽²⁾

Note 1: Refer to the “PIC12F519 Memory Programming Specification”, DS41316 to determine how to access the

Configuration Word.

2: DRT length (18 ms or 1 ms) is a function of clock mode selection. It is the responsibility of the application

designer to ensure the use of either 18 ms (nominal) DRT or the 1 ms (nominal) DRT will result in

acceptable operation. Refer to Section 11.1 “DC Characteristics: PIC12F519 (Industrial)” and

Section 11.2 “DC Characteristics: PIC12F519 (Extended)” for VDD rise time and stability requirements

for this mode of operation.

DS41319A-page 36

Preliminary

PIC12F519

FIGURE 8-2:

EXTERNAL CLOCK INPUT

OPERATION (XT OR LP

OSC CONFIGURATION)

8.2

Oscillator Configurations

8.2.1

OSCILLATOR TYPES

The PIC12F519 device can be operated in up to four

different oscillator modes. The user can program using

the Configuration bits (FOSC<1:0>), to select one of

these modes:

OSC1

Clock from

ext. system

PIC12F519

OSC2

Open

• LP:

• XT:

Low-Power Crystal

Crystal/Resonator

• INTRC: Internal 4 MHz or 8 MHz Oscillator

• EXTRC: External Resistor/Capacitor

TABLE 8-1:

CAPACITOR SELECTION FOR

CERAMIC RESONATORS

8.2.2

CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

Osc

Resonator Cap. Range Cap. Range

Type

Freq.

C1

C2

In XT or LP modes, a crystal or ceramic resonator is

connected to the (RB5)/OSC1/(CLKIN) and (RB4)/OSC2

pins to establish oscillation (Figure 8-1). The PIC12F519

oscillator designs require the use of a parallel cut crystal.

Use of a series cut crystal may give a frequency out of the

crystal manufacturers specifications. When in XT or LP

modes, the device can have an external clock source

drive the (RB5)/OSC1/CLKIN pin (Figure 8-2). When the

part is used in this fashion, the output drive levels on the

OSC2 pin are very weak. This pin should be left open and

unloaded. Also when using this mode, the external clock

should observe the frequency limits for the clock mode

chosen (XT or LP).

XT

4.0 MHz

30 pF

Note:

Component values shown are for design

guidance only. Since each resonator has

its own characteristics, the user should

consult the resonator manufacturer for

appropriate values of external compo-

nents.

TABLE 8-2:

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR –

PIC12F519⁽²⁾

Osc

Resonator Cap.Range Cap. Range

Note 1: The user should verify that the device

oscillator starts and performs as

expected. Adjusting the loading capacitor

values and/or the Oscillator mode may

be required.

Type

Freq.

C1

C2

LP

XT

32 kHz⁽¹⁾

15 pF

200 kHz

1 MHz

4 MHz

47-68 pF

15 pF

47-68 pF

15 pF

FIGURE 8-1:

CRYSTAL OPERATION

(OR CERAMIC

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

RESONATOR)

(XT OR LP OSC

CONFIGURATION)

2: Component values shown are for design

guidance only. Rs may be required to

avoid overdriving crystals with low drive

level specification. Since each crystal has

its own characteristics, the user should

consult the crystal manufacturer for

appropriate values of external compo-

nents.

(1)

C1

PIC12F519

OSC1

OSC2

Sleep

XTAL

(3)

RF

To internal

logic

(2)

RS

(1)

C2

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF approx. value = 10 MΩ.

Preliminary

DS41319A-page 37

PIC12F519

8.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

8.2.4

EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC circuit option

offers additional cost savings. The RC oscillator fre-

quency is a function of the supply voltage, the resistor

(REXT) and capacitor (CEXT) values, and the operating

temperature. In addition to this, the oscillator frequency

will vary from unit-to-unit due to normal process param-

eter variation. Furthermore, the difference in lead frame

capacitance between package types will also affect the

oscillation frequency, especially for low CEXT values.

The user also needs to take into account variation due

to tolerance of external R and C components used.

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external crystal

oscillator circuit. Prepackaged oscillators provide a wide

operating range and better stability. A well-designed

crystal oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used: one with parallel resonance, or one with series

resonance.

Figure 8-3 shows implementation of a parallel resonant

oscillator circuit. The circuit is designed to use the fun-

damental frequency of the crystal. The 74AS04 inverter

performs the 180-degree phase shift that a parallel

oscillator requires. The 4.7 kΩ resistor provides the

negative feedback for stability. The 10 kΩ potentiome-

ters bias the 74AS04 in the linear region. This circuit

could be used for external oscillator designs.

Figure 8-5 shows how the R/C combination is con-

nected to the PIC12F519 device. For REXT values

below 3.0 kΩ, the oscillator operation may become

unstable, or stop completely. For very high REXT values

(e.g., 1 MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. It is recommended keeping

REXT between 5.0 kΩ and 100 kΩ.

FIGURE 8-3:

EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Although the oscillator will operate with no external

capacitor (CEXT = 0pF), it is recommended using

values above 20 pF for noise and stability reasons.

With no or small external capacitance, the oscillation

frequency can vary dramatically due to changes in

external capacitances, such as PCB trace capacitance

or package lead frame capacitance.

+5V

To Other

Devices

10k

74AS04

4.7k

Section 11.0 “Electrical Characteristics”, shows RC

frequency variation from part-to-part due to normal

process variation. The variation is larger for larger val-

ues of R (since leakage current variation will affect RC

frequency more for large R) and for smaller values of C

(since variation of input capacitance will affect RC

frequency more).

CLKIN

74AS04

PIC12F519

10k

XTAL

10k

Also, see the Electrical Specifications section for

variation of oscillator frequency due to VDD for given

REXT/CEXT values, as well as frequency variation due

to operating temperature for given R, C and VDD

values.

20 pF

Figure 8-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 8-5:

EXTERNAL RC

OSCILLATOR MODE

VDD

FIGURE 8-4:

EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

REXT

Internal

clock

OSC1

N

To Other

Devices

330

74AS04

CEXT

VSS

PIC16F519

74AS04

CLKIN

0.1 mF

PIC12F519

XTAL

DS41319A-page 38

Preliminary

PIC12F519

8.2.5

INTERNAL 4/8 MHz RC

OSCILLATOR

8.3

Reset

The device differentiates between various kinds of

Reset:

The internal RC oscillator provides a fixed 4/8 MHz

(nominal) system clock at VDD = 5V and 25°C, (see

Section 11.0 “Electrical Characteristics” for

information on variation over voltage and temperature).

• Power-on Reset (POR)

• MCLR Reset during normal operation

• MCLR Reset during Sleep

In addition, a calibration instruction is programmed into

the last address of memory, which contains the calibra-

tion value for the internal RC oscillator. This location is

always non-code protected, regardless of the

code-protect settings. This value is programmed as a

MOVLW XXinstruction where XXis the calibration value,

and is placed at the Reset vector. This will load the W

register with the calibration value upon Reset and the

PC will then roll over to the users program at address

0x000. The user then has the option of writing the value

to the OSCCAL Register (05h) or ignoring it.

• WDT Time-out Reset during normal operation

• WDT Time-out Reset during Sleep

• Wake-up from Sleep on pin change

Some registers are not reset in any way, and they are

unknown on Power-on Reset (POR) and unchanged in

any other Reset. Most other registers are reset to

“Reset state” on Power-on Reset (POR), MCLR, WDT

or Wake-up on pin change Reset during normal opera-

tion. They are not affected by a WDT Reset during

Sleep or MCLR Reset during Sleep, since these

Resets are viewed as resumption of normal operation.

The exceptions to this are TO, PD and RBWUF bits.

They are set or cleared differently in different Reset sit-

uations. These bits are used in software to determine

the nature of Reset. See Table 8-3 for a full description

of Reset states of all registers.

OSCCAL, when written to with the calibration value, will

“trim” the internal oscillator to remove process variation

from the oscillator frequency.

Note:

Erasing the device will also erase the

pre-programmed internal calibration value

for the internal oscillator. The calibration

value must be read prior to erasing the

part so it can be reprogrammed correctly

later.

For the PIC12F519 device, only bits <7:1> of OSCCAL

are used for calibration. See Register 4-3 for more

information.

Note:

The bit 0 of the OSCCAL register is

unimplemented and should be written as

‘0’ when modifying OSCCAL for

compatibility with future devices.

Preliminary

DS41319A-page 39

PIC12F519

TABLE 8-3:

Register

RESET CONDITIONS FOR REGISTERS

MCLR Reset, WDT Time-out,

Wake-up On Pin Change

Address

Power-on Reset

W

—

qqqq qqqu⁽¹⁾

xxxx xxxx

1111 1111

qqqq qqqu⁽¹⁾

uuuu uuuu

1111 1111

INDF

TMR0

PCL

00h

01h

02h

STATUS

FSR

03h

04h

05h

06h

—

0001 1xxx

110x xxxx

1111 111-

--xx xxxx

1111 1111

--11 1111

xxx0 0000

xxxx xxxx

--xx xxxx

q00q quuu^{(2), (3)}

11uu uuuu

uuuu uuu-

--uu uuuu

1111 1111

--11 1111

OSCCAL

PORTB

OPTION

TRIS

—

EECON

EEDATA

EEADR

21h

25h

26h

Legend: u= unchanged, x= unknown, – = unimplemented bit, read as ‘0’, q= value depends on condition.

Note 1: Bits <7:1> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.

2: See Table 8-7 for Reset value for specific conditions.

3: If Reset was due to wake-up on pin change, then bit 7 = 1. All other Resets will cause bit 7 = 0.

TABLE 8-4:

RESET CONDITION FOR SPECIAL REGISTERS

STATUS Addr: 03h

PCL Addr: 02h

Power-on Reset

0001 1xxx

1111 1111

MCLR Reset during normal operation

MCLR Reset during Sleep

000u uuuu

0001 0uuu

0000 0uuu

0000 uuuu

1001 0uuu

WDT Reset during Sleep

WDT Reset normal operation

Wake-up from Sleep on pin change

Legend: u= unchanged, x= unknown

DS41319A-page 40

Preliminary

PIC12F519

The Power-on Reset circuit and the Device Reset

Timer (see Section 8.5 “Device Reset Timer (DRT)”)

circuit are closely related. On power-up, the Reset latch

is set and the DRT is reset. The DRT timer begins

counting once it detects MCLR to be high. After the

time-out period, which is typically 18 ms or 1 ms, it will

reset the Reset latch and thus end the on-chip Reset

signal.

8.3.1

MCLR ENABLE

This Configuration bit, when unprogrammed (left in the

‘1’ state), enables the external MCLR function. When

programmed, the MCLR function is tied to the internal

VDD and the pin is assigned to be a I/O. See Figure 8-6.

FIGURE 8-6:

MCLR SELECT

A power-up example where MCLR is held low is shown

in Figure 8-8. VDD is allowed to rise and stabilize before

bringing MCLR high. The chip will actually come out of

Reset TDRT after MCLR goes high.

RBWU

RB3/MCLR/VPP

Internal MCLR

In Figure 8-9, the on-chip Power-on Reset feature is

being used (MCLR and VDD are tied together or the pin

is programmed to be RB3). The VDD is stable before

the Start-up timer times out and there is no problem in

getting a proper Reset. However, Figure 8-10 depicts a

problem situation where VDD rises too slowly. The time

between when the DRT senses that MCLR is high and

when MCLR and VDD actually reach their full value, is

too long. In this situation, when the start-up timer times

out, VDD has not reached the VDD (min) value and the

chip may not function correctly. For such situations, we

recommend that external RC circuits be used to

achieve longer POR delay times (Figure 8-9).

MCLRE

8.4

Power-on Reset (POR)

The PIC12F519 device incorporates an on-chip

Power-on Reset (POR) circuitry, which provides an

internal chip Reset for most power-up situations.

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper oper-

ation. To take advantage of the internal POR, program

the RB3/MCLR/VPP pin as MCLR and tie through a

resistor to VDD, or program the pin as RB3, in which

case, an internal weak pull-up resistor is implemented

using a transistor (refer to Table 11-2 for the pull-up

resistor ranges). This will eliminate external RC compo-

nents usually needed to create a Power-on Reset. A

maximum rise time for VDD is specified. See

Section 11.0 “Electrical Characteristics” for details.

Note:

When the devices start normal operation

(exit the Reset condition), device operat-

ing parameters (voltage, frequency, tem-

perature, etc.) must be met to ensure

operation. If these conditions are not met,

the device must be held in Reset until the

operating conditions are met.

When the devices start normal operation (exit the

Reset condition), device operating parameters (volt-

age, frequency, temperature,...) must be met to ensure

operation. If these conditions are not met, the devices

must be held in Reset until the operating parameters

are met.

A simplified block diagram of the on-chip Power-on

Reset circuit is shown in Figure 8-7.

Preliminary

DS41319A-page 41

PIC12F519

FIGURE 8-7:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

VDD

Power-up

Detect

POR (Power-on Reset)

MCLR Reset

RB3/MCLR/VPP

S

R

Q

MCLRE

Start-up Timer

WDT Reset

WDT Time-out

(10 μs, 1 ms

CHIP Reset

or 18 ms)

Pin Change

Sleep

Wake-up on pin Change Reset

FIGURE 8-8:

TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

FIGURE 8-9:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE

TIME

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

DS41319A-page 42

Preliminary

PIC12F519

FIGURE 8-10:

TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE

TIME

V1

VDD

MCLR

Internal POR

TDRT

DRT Time-out

Internal Reset

Note:

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final

value. In this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

Preliminary

DS41319A-page 43

PIC12F519

8.5

Device Reset Timer (DRT)

8.6

Watchdog Timer (WDT)

On the PIC12F519 device, the DRT runs any time the

device is powered up. DRT runs from Reset and varies

based on oscillator selection and Reset type (see

Table 8-5).

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator, which does not require any external

components. This RC oscillator is separate from the

external RC oscillator of the (RB5)/OSC1/CLKIN pin

and the internal 4 or 8 MHz oscillator. This means that

the WDT will run even if the main processor clock has

been stopped, for example, by execution of a SLEEP

instruction. During normal operation or Sleep, a WDT

Reset or wake-up Reset, generates a device Reset.

The DRT operates on an internal RC oscillator. The

processor is kept in Reset as long as the DRT is active.

The DRT delay allows VDD to rise above VDD min. and

for the oscillator to stabilize.

Oscillator circuits based on crystals or ceramic resona-

tors require a certain time after power-up to establish a

stable oscillation. The on-chip DRT keeps the devices in

a Reset condition after MCLR has reached a logic high

(VIH MCLR) level. Programming RB3/MCLR/VPP as

MCLR and using an external RC network connected to

the MCLR input is not required in most cases. This

allows savings in cost-sensitive and/or space restricted

applications, as well as allowing the use of the

RB3/MCLR/VPP pin as a general purpose input.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer Reset.

The WDT can be permanently disabled by program-

ming the configuration WDTE as a ‘0’ (see Section 8.1

“Configuration Bits”). Refer to the PIC12F519 Pro-

gramming Specifications to determine how to access

the Configuration Word.

8.6.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT (under software control) by

writing to the OPTION register. Thus, a time-out period

of a nominal 2.3 seconds can be realized. These peri-

ods vary with temperature, VDD and part-to-part pro-

cess variations (see DC specs).

The Device Reset Time delays will vary from

chip-to-chip due to VDD, temperature and process vari-

ation. See AC parameters for details.

The DRT will also be triggered upon a Watchdog Timer

time-out from Sleep. This is particularly important for

applications using the WDT to wake from Sleep mode

automatically.

Reset sources are POR, MCLR, WDT time-out and

wake-up on pin change. See Section 8.8.2 “Wake-up

from Sleep”, Notes 1, 2 and 3.

Under worst-case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

TABLE 8-5:

DRT (DEVICE RESET TIMER

PERIOD)

8.6.2

WDT PROGRAMMING

CONSIDERATIONS

Oscillator

Configuration

Subsequent

POR Reset

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from

timing out and generating a device Reset.

Resets

INTOSC, EXTRC

LP, XT

1 ms (typical)

10 μs (typical)

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum Sleep time before a WDT wake-up Reset.

18 ms (typical) 18 ms (typical)

DS41319A-page 44

Preliminary

PIC12F519

FIGURE 8-11:

WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 7-1)

0

M

U

X

Postscaler

1

Watchdog

Time

8-to-1 MUX

PS<2:0>

PSA

WDT Enable

Configuration

(Figure 7-3)

To Timer0

PSA

Bit

0

1

MUX

WDT Time-out

Note 1: PSA, PS<2:0> are bits in the OPTION register.

TABLE 8-6:

SUMMARY OF REGISTER ASSOCIATED WITH THE WATCHDOG TIMER

Value on

POR, BOR other Resets

Value on all

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OPTION

RBWU

RBPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

Legend:

Shaded boxes = Not used by Watchdog Timer.

Preliminary

DS41319A-page 45

PIC12F519

8.8.2

WAKE-UP FROM SLEEP

8.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO, PD, RBWUF)

The device can wake-up from Sleep through one of

the following events:

1. An external Reset input on RB3/MCLR/VPP pin,

when configured as MCLR.

The TO, PD and (RBWUF) bits in the STATUS register

can be tested to determine if a Reset condition has

been caused by a power-up condition, a MCLR or

Watchdog Timer (WDT) Reset.

2. A Watchdog Timer Time-out Reset (if WDT was

enabled).

3. A change on input pin RB0, RB1 and RB3 when

wake-up on change is enabled.

TABLE 8-7:

TO/PD/(RBWUF) STATUS

AFTER RESET

These events cause a device Reset. The TO, PD and

RBWUF bits can be used to determine the cause of

device Reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEP is invoked.

The RBWUF bit indicates a change in state while in

Sleep at pins RB0, RB1 and RB3 (since the last file or

bit operation on RB port).

RBWUF TO PD

Reset Caused By

0

u

WDT wake-up from Sleep

WDT time-out (not from

Sleep)

0

1

u

1

0

1

u

0

MCLR wake-up from Sleep

Power-up

Note:

Caution: Right before entering Sleep,

read the input pins. When in Sleep, wake

up occurs when the values at the pins

change from the state they were in at the

last reading. If a wake-up on change

occurs and the pins are not read before

re-entering Sleep, a wake-up will occur

immediately even if no pins change while

in Sleep mode.

MCLR not during Sleep

Wake-up from Sleep on pin

change

Legend: u= unchanged

Note 1: The TO, PD and RBWUF bits maintain

their status (u) until a Reset occurs. A

low-pulse on the MCLR input does not

change the TO, PD and RBWUF Status

bits.

The WDT is cleared when the device wakes from

Sleep, regardless of the wake-up source.

8.8

Power-down Mode (Sleep)

A device may be powered down (Sleep) and later

powered up (wake-up from Sleep).

8.8.1

SLEEP

The Power-down mode is entered by executing a

SLEEPinstruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low or high-impedance).

Note:

A Reset generated by a WDT time-out

does not drive the MCLR pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

RB3/MCLR/VPP pin must be at a logic high level if

MCLR is enabled.

DS41319A-page 46

Preliminary

PIC12F519

FIGURE 8-12:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

8.9

Program Verification/Code

Protection

If the code protection bit has not been programmed, the

on-chip program memory can be read out for

verification purposes.

To Normal

Connections

PIC12F519

External

Connector

Signals

The first 64 locations and the last location (OSCCAL)

can be read, regardless of the code protection bit

setting.

+5V

0V

VDD

The last memory location can be read regardless of the

code protection bit setting on the PIC12F519 device.

VSS

VPP

MCLR/VPP

8.10 ID Locations

RB1

RB0

CLK

Four memory locations are designated as ID locations

where users can store checksum or other code

identification numbers. These locations are not

accessible during normal execution, but are readable

and writable during program/verify.

Data I/O

VDD

To Normal

Connections

Use only the lower 4 bits of the ID locations and always

program the upper 8 bits as ‘0’s.

8.11 In-Circuit Serial Programming™

The PIC12F519 device can be serially programmed

while in the end application circuit. This is simply done

with two lines for clock and data, and three other lines for

power, ground and the programming voltage. This

allows users to manufacture boards with unprogrammed

PIC12F519 device and then program the PIC12F519

device just before shipping the product. This also allows

the most recent firmware, or a custom firmware, to be

programmed.

The PIC12F519 device is placed into a Program/Verify

mode by holding the RB1 and RB0 pins low while rais-

ing the MCLR (VPP) pin from VIL to VIHH (see program-

ming specification). The RB1 pin becomes the

programming clock, and the RB0 pin becomes the

programming data. Both RB1 and RB0 pins are Schmitt

Trigger inputs in this mode.

After Reset, a 6-bit command is then supplied to the

device. Depending on the command, 14 bits of program

data are then supplied to or from the device, depending

if the command was a Load or a Read. For complete

details of serial programming, please refer to the

“PIC12F519 Memory Programming Specification,”

(DS41316).

A typical In-Circuit Serial Programming connection is

shown in Figure 8-12.

Preliminary

DS41319A-page 47

PIC12F519

NOTES:

DS41319A-page 48

Preliminary

PIC12F519

All instructions are executed within a single instruction

cycle, unless a conditional test is true or the program

counter is changed as a result of an instruction. In this

case, the execution takes two instruction cycles. One

instruction cycle consists of four oscillator periods.

Thus, for an oscillator frequency of 4 MHz, the normal

instruction execution time is 1 μs. If a conditional test is

true or the program counter is changed as a result of an

instruction, the instruction execution time is 2 μs.

9.0

INSTRUCTION SET SUMMARY

The PIC12F519 instruction set is highly orthogonal and

is comprised of three basic categories.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC12F519 instruction is a 12-bit word divided

into an opcode, which specifies the instruction type,

and one or more operands which further specify the

operation of the instruction. The formats for each of the

categories is presented in Figure 9-1, while the various

opcode fields are summarized in Table 9-1.

Figure 9-1 shows the three general formats that the

instructions can have. All examples in the figure use

the following format to represent a hexadecimal

number:

0xhhh

For byte-oriented instructions, ‘f’ represents a file reg-

ister designator and ‘d’ represents a destination desig-

nator. The file register designator specifies which file

register is to be used by the instruction.

where ‘h’ signifies a hexadecimal digit.

FIGURE 9-1:

GENERAL FORMAT FOR

INSTRUCTIONS

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’, the result is placed

in the file register specified in the instruction.

Byte-oriented file register operations

11

6

5

d

4

0

OPCODE

f (FILE #)

For bit-oriented instructions, ‘b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ‘f’ represents the number of the

file in which the bit is located.

d = 0for destination W

d = 1for destination f

f = 5-bit file register address

Bit-oriented file register operations

11 8 7

b (BIT #)

For literal and control operations, ‘k’ represents an

8 or 9-bit constant or literal value.

5

4

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 5-bit file register address

TABLE 9-1:

OPCODE FIELD

DESCRIPTIONS

Literal and control operations (except GOTO)

11

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

8

7

0

OPCODE

k (literal)

Bit address within an 8-bit file register

Literal field, constant data or label

k = 8-bit immediate value

k

x

Don’t care location (= 0or 1)

Literal and control operations – GOTOinstruction

11

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

9

8

0

OPCODE

k (literal)

d

Destination select;

d= 0(store result in W)

d= 1(store result in file register ‘f’)

Default is d = 1

k = 9-bit immediate value

label

TOS

PC

Label name

Top-of-Stack

Program Counter

Watchdog Timer counter

Time-out bit

WDT

TO

PD

Power-down bit

dest

Destination, either the W register or the specified

register file location

[

(

]

)

Options

Contents

→

Assigned to

Register bit field

In the set of

< >

∈

italics User defined term (font is courier)

Preliminary

DS41319A-page 49

PIC12F519

TABLE 9-2:

INSTRUCTION SET SUMMARY

Description

12-Bit Opcode

MSb LSb

Mnemonic,

Operands

Status

Affected

Cycles

Notes

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

1

0001 11df ffff C, DC, Z 1, 2, 4

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

0010 11df ffff

0010 10df ffff

0011 11df ffff

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

Z

None

Z

None

Z

2, 4

4

–

f, d

f

1

2, 4

1, 4

1⁽²⁾

1

1⁽²⁾

1

Z

None

C

–

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

2, 4

C

0000 10df ffff C, DC, Z 1, 2, 4

0011 10df ffff

0001 10df ffff

None

Z

2, 4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

0100 bbbf ffff

None

2, 4

0101 bbbf ffff

0110 bbbf ffff

0111 bbbf ffff

1⁽²⁾

LITERAL AND CONTROL OPERATIONS

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

–

k

–

k

–

f

AND literal with W

Call Subroutine

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100 TO, PD

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

Z

None

1

3

Clear Watchdog Timer

Unconditional branch

Inclusive OR literal with W

Move literal to W

Load OPTION register

Return, place literal in W

Go into Standby mode

Load TRIS register

None

Z

None

0000 0000 0011 TO, PD

0000 0000 0fff

1111 kkkk kkkk

None

Z

XORLW

k

Exclusive OR literal to W

Note 1: The 9th bit of the program counter will be forced to a ‘0’ by any instruction that writes to the PC except for

GOTO. See Section 4.6 “Program Counter”.

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and

is driven low by an external device, the data will be written back with a ‘0’.

3: The instruction TRIS f, where f = 6, causes the contents of the W register to be written to the tri-state

latches of PORTB. A ‘1’ forces the pin to a high-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be

cleared (if assigned to TMR0).

DS41319A-page 50

Preliminary

PIC12F519

ADDWF

Add W and f

BCF

Bit Clear f

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] BCF f,b

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operation:

(W) + (f) → (dest)

Operation:

0 → (f<b>)

Status Affected: C, DC, Z

Status Affected: None

Description:

Add the contents of the W register

Description:

Bit ‘b’ in register ‘f’ is cleared.

and register ‘f’. If ‘d’ is’0’, the result

is stored in the W register. If ‘d’ is

‘1’, the result is stored back in

register ‘f’.

ANDLW

AND literal with W

BSF

Bit Set f

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] BSF f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

1 → (f<b>)

Status Affected: Z

Status Affected: None

Description:

The contents of the W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description: Bit ‘b’ in register ‘f’ is set.

BTFSC

Bit Test f, Skip if Clear

ANDWF

AND W with f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

skip if (f<b>) = 0

Operation:

(W) .AND. (f) → (dest)

Status Affected: None

Status Affected: Z

Description: If bit ‘b’ in register ‘f’ is ‘0’, then the

Description: The contents of the W register are

next instruction is skipped.

AND’ed with register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W register.

If ‘d’ is ‘1’, the result is stored back

in register ‘f’.

If bit ‘b’ is ‘0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOPis executed instead,

making this a two-cycle instruction.

Preliminary

DS41319A-page 51

PIC12F519

CLRW

Clear W

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRW

None

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

00h → (W);

1 → Z

Operation:

skip if (f<b>) = 1

Status Affected:

Description:

Z

Status Affected: None

The W register is cleared. Zero bit

(Z) is set.

Description:

If bit ‘b’ in register ‘f’ is ‘1’, then the

next instruction is skipped.

If bit ‘b’ is ‘1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOPis executed instead,

making this a two-cycle instruction.

CLRWDT

Syntax:

Clear Watchdog Timer

[ label ] CLRWDT

None

CALL

Subroutine Call

[ label ] CALL k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

00h → WDT;

0 → WDT prescaler (if assigned);

(PC) + 1→ Top-of-Stack;

k → PC<7:0>;

1 → TO;

1 → PD

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected: TO, PD

Status Affected: None

Description:

The CLRWDTinstruction resets the

Description:

Subroutine call. First, return

WDT. It also resets the prescaler, if

the prescaler is assigned to the

WDT and not Timer0. Status bits

TO and PD are set.

address (PC + 1) is pushed onto

the stack. The eight-bit immediate

address is loaded into PC

bits <7:0>. The upper bits

PC<10:9> are loaded from

STATUS<6:5>, PC<8> is cleared.

CALLis a two-cycle instruction.

CLRF

Clear f

COMF

Complement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 31

f

Syntax:

Operands:

[ label ] COMF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d ∈ [0,1]

00h → (f);

1 → Z

Operation:

(f) → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

DS41319A-page 52

Preliminary

PIC12F519

DECF

Decrement f

INCF

Increment f

Syntax:

Operands:

[ label ] DECF f,d

Syntax:

Operands:

[ label ] INCF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) – 1 → (dest)

Operation:

(f) + 1 → (dest)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

INCFSZ

Syntax:

Increment f, Skip if 0

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] INCFSZ f,d

[ label ] DECFSZ f,d

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

(f) + 1 → (dest), skip if result = 0

Operation:

(f) – 1 → d; skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘0’, then the next

instruction, which is already

fetched, is discarded and a NOPis

executed instead making it a

two-cycle instruction.

If the result is ‘0’, the next instruc-

tion, which is already fetched, is

discarded and a NOPis executed

instead making it a two-cycle

instruction.

IORLW

Inclusive OR literal with W

[ label ] IORLW k

0 ≤ k ≤ 255

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 511

Syntax:

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

(W) .OR. (k) → (W)

Z

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description: GOTOis an unconditional branch.

The 9-bit immediate value is

loaded into PC bits <8:0>. The

upper bits of PC are loaded from

STATUS<6:5>. GOTOis a two-

cycle instruction.

Preliminary

DS41319A-page 53

PIC12F519

IORWF

Inclusive OR W with f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

[ label ] IORWF f,d

f

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

(W) → (f)

Operation:

(W).OR. (f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

Move data from the W register to

register ‘f’.

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is ‘1’,

the result is placed back in register

‘f’.

MOVF

Move f

NOP

No Operation

[ label ] NOP

None

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

Operation:

No operation

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Description:

Z

Description:

No operation.

The contents of register ‘f’ are

moved to destination ‘d’. If ‘d’ is ‘0’,

destination is the W register. If ‘d’

is ‘1’, the destination is file

register ‘f’. ‘d’ = 1is useful as a

test of a file register, since status

flag Z is affected.

MOVLW

Syntax:

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load OPTION Register

[ label ] Option

None

Operands:

Operation:

Operands:

Operation:

(W) → Option

k → (W)

Status Affected: None

Description: The content of the W register is

Description:

The eight-bit literal ‘k’ is loaded

into the W register. The “don’t

loaded into the OPTION register.

cares” will assembled as ‘0’s.

DS41319A-page 54

Preliminary

PIC12F519

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

SLEEP

Enter SLEEP Mode

Syntax:

[label ]

SLEEP

Operands:

Operation:

Operands:

Operation:

None

k → (W);

TOS → PC

00h → WDT;

0 → WDT prescaler;

1 → TO;

Status Affected: None

0 → PD

Description:

The W register is loaded with the

Status Affected: TO, PD, RBWUF

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address). This

is a two-cycle instruction.

Description:

Time-out Status bit (TO) is set. The

Power-down Status bit (PD) is

cleared.

RBWUF is unaffected.

The WDT and its prescaler are

cleared.

The processor is put into Sleep

mode with the oscillator stopped.

See Section 8.8 “Power-down

Mode (Sleep)” on Sleep for more

details.

RLF

Rotate Left f through Carry

SUBWF

Subtract W from f

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

[label ] SUBWF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f) – (W) → (dest)

Status Affected:

Description:

Status Affected: C, DC, Z

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is stored back in reg-

ister ‘f’.

Description:

Subtract (two’s complement

method) the W register from regis-

ter ‘f’. If ‘d’ is ‘0’, the result is stored

in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

register ‘f’

C

RRF

Rotate Right f through Carry

SWAPF

Syntax:

Swap Nibbles in f

Syntax:

Operands:

[ label ] RRF f,d

[ label ] SWAPF f,d

0 ≤ f ≤ 31

d ∈ [0,1]

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Description:

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

Status Affected: None

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

register ‘f’

C

Preliminary

DS41319A-page 55

PIC12F519

TRIS

Load TRIS Register

XORWF

Syntax:

Exclusive OR W with f

Syntax:

[ label ] TRIS

f

[ label ] XORWF f,d

Operands:

Operation:

f = 6

Operands:

0 ≤ f ≤ 31

d ∈ [0,1]

(W) → TRIS register f

Status Affected: None

Operation:

(W) .XOR. (f) → (dest)

Description:

TRIS register ‘f’ (f = 6 or 7) is

loaded with the contents of the W

register.

Status Affected:

Description:

Z

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

XORLW

Exclusive OR literal with W

Syntax:

[label ] XORLW k

0 ≤ k ≤ 255

Operands:

Operation:

(W) .XOR. k → (W)

Z

Status Affected:

Description:

The contents of the W register are

XOR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

DS41319A-page 56

Preliminary

PIC12F519

10.1 MPLAB Integrated Development

Environment Software

10.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

Preliminary

DS41319A-page 57

PIC12F519

10.2 MPASM Assembler

10.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

10.6 MPLAB SIM Software Simulator

10.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

10.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41319A-page 58

Preliminary

PIC12F519

10.7 MPLAB ICE 2000

High-Performance

10.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

10.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

10.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

Preliminary

DS41319A-page 59

PIC12F519

10.11 PICSTART Plus Development

Programmer

10.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

10.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41319A-page 60

Preliminary

PIC12F519

11.0 ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40°C to +125°C

Storage temperature ............................................................................................................................-65°C to +150°C

Voltage on VDD with respect to VSS ...............................................................................................................0 to +6.5V

Voltage on MCLR with respect to VSS..........................................................................................................0 to +13.5V

Voltage on all other pins with respect to VSS ............................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾..................................................................................................................................700 mW

Max. current out of VSS pin ................................................................................................................................200 mA

Max. current into VDD pin...................................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ...........................................................................................................±20 mA

Max. output current sunk by any I/O pin ..............................................................................................................25 mA

Max. output current sourced by any I/O pin.........................................................................................................25 mA

Max. output current sourced by I/O port ..............................................................................................................75 mA

Max. output current sunk by I/O port ...................................................................................................................75 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

^†NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above

those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

Preliminary

DS41319A-page 61

PIC12F519

FIGURE 11-1:

PIC12F519 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

6.0

5.5

5.0

4.5

4.0

3.5

VDD

(Volts)

3.0

2.5

INTOSC ONLY

2.0

0

4

8

10

20

25

Frequency (MHz)

FIGURE 11-2:

MAXIMUM OSCILLATOR FREQUENCY TABLE

LP

XT

EXTRC

INTOSC

0

200 kHz

4 MHz

8 MHz

Frequency (MHz)

DS41319A-page 62

Preliminary

PIC12F519

11.1 DC CHARACTERISTICS: PIC12F519 (Industrial)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 40°C ≤ TA ≤ +85°C (industrial)

DC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min Typ⁽¹⁾Max Units

Conditions

D001

D002

VDD

VDR

Supply Voltage

RAM Data Retention Voltage⁽²⁾

2.0

—

5.5

—

V

See Figure 11-1

1.5*

Vss

Device in Sleep mode

D003 VPOR VDD Start Voltage to ensure

—

See Section 8.4 “Power-on

Reset (POR)” for details

Power-on Reset

D004

D010

SVDD VDD Rise Rate to ensure

0.05*

—

V/ms See Section 8.4 “Power-on

Reset (POR)” for details

(Note 6)

Power-on Reset

IDD

Supply Current^(3,4)

—

175

0.625 1.1

275

μA

FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

mA

—

250

1.0

450

1.5

μA

mA

FOSC = 8 MHz, VDD = 2.0V

FOSC = 8 MHz, VDD = 5.0V

—

11

38

15

52

μA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020

D022

IPD

Power-down Current⁽⁵⁾

—

0.1

0.35

1.2

2.2

μA

VDD = 2.0V

VDD = 5.0V

IWDT WDT Current⁽⁵⁾

—

1.0

7.0

3.0

16.0

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

6: This rise rate applies if the clock mode selected (LP, XT) allows DRT to hold the device in Reset within

18 ms (nominal delay) DRT. Otherwise, the user must ensure that VDD reaches VDDMIN before DRT

expires.

Preliminary

DS41319A-page 63

PIC12F519

11.2 DC CHARACTERISTICS: PIC12F519 (Extended)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature 40°C ≤ TA ≤ +125°C (extended)

DC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min Typ⁽¹⁾Max Units

Conditions

D001

D002

VDD

VDR

Supply Voltage

RAM Data Retention Voltage⁽²⁾

2.0

—

5.5

—

V

See Figure 11-1

1.5*

Vss

Device in Sleep mode

D003 VPOR VDD Start Voltage to ensure

—

See Section 8.4 “Power-on

Reset (POR)” for details

Power-on Reset

D004

D010

SVDD VDD Rise Rate to ensure

0.05*

—

V/ms See Section 8.4 “Power-on

Reset (POR)” for details

(Note 6)

Power-on Reset

IDD

Supply Current^(3,4)

—

175

0.625 1.1

275

μA

FOSC = 4 MHz, VDD = 2.0V

FOSC = 4 MHz, VDD = 5.0V

mA

—

250

1.0

450

1.5

μA

mA

FOSC = 8 MHz, VDD = 2.0V

FOSC = 8 MHz, VDD = 5.0V

—

11

38

16

54

μA

FOSC = 32 kHz, VDD = 2.0V

FOSC = 32 kHz, VDD = 5.0V

D020

D022

IPD

Power-down Current⁽⁵⁾

—

0.1

0.35 15.0

9.0

μA

VDD = 2.0V

VDD = 5.0V

IWDT WDT Current⁽⁵⁾

—

1.0

7.0

18

22

μA

VDD = 2.0V

VDD = 5.0V

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design

guidance only and is not tested.

2: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on

the current consumption.

4: The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VSS, T0CKI = VDD, MCLR =

VDD; WDT enabled/disabled as specified.

5: For standby current measurements, the conditions are the same as IDD, except that the device is in Sleep

mode. If a module current is listed, the current is for that specific module enabled and the device in Sleep.

6: This rise rate applies if the clock mode selected (LP, XT) allows DRT to hold the device in Reset within

18 ms (nominal delay) DRT. Otherwise, the user must ensure that VDD reaches VDDMIN before DRT

expires.

DS41319A-page 64

Preliminary

PIC12F519

TABLE 11-1: DC CHARACTERISTICS: PIC12F519 (Industrial, Extended)

Standard Operating Conditions (unless otherwise specified)

Operating temperature

-40°C ≤ TA ≤ +85°C (industrial)

DC CHARACTERISTICS

-40°C ≤ TA ≤ +125°C (extended)

Operating voltage VDD range as described in DC specification.

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

VIL

Input Low Voltage

I/O ports

D030

D030A

D031

D032

D033

D033A

with TTL buffer

Vss

—

0.8V

V

For all 4.5 ≤ VDD ≤ 5.5V

0.15 VDD

0.3

Otherwise

with Schmitt Trigger buffer

MCLR, T0CKI

OSC1 (EXTRC mode)

OSC1 (XT and LP modes)

Input High Voltage

I/O ports

(Note 1)

VIH

—

D040

with TTL buffer

2.0

VDD

V

4.5 ≤ VDD ≤ 5.5V

D040A

0.25 VDD

+ 0.8V

Otherwise

D041

D042

D042A

D043

D070

with Schmitt Trigger buffer

MCLR, T0CKI

0.85 VDD

1.6

—

VDD

400

V

For entire VDD range

(Note 1)

OSC1 (EXTRC mode)

OSC1 (XT and LP modes)

I/O PORT weak pull-up current⁽⁵⁾

Input Leakage Current^{(2), (3)}

I/O ports

—

V

—

V

IPUR

IIL

50

250

μA

VDD = 5V, VPIN = VSS

D060

D061

D063

—

±0.7

—

±1

±5

μA

Vss ≤ VPIN ≤ VDD, Pin at high-impedance

Vss ≤ VPIN ≤ VDD

RB3/MCLR⁽⁴⁾

OSC1

Vss ≤ VPIN ≤ VDD, XT and LP osc configuration

Output Low Voltage

I/O ports

D080

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V, –40°C to +85°C

IOL = 7.0 mA, VDD = 4.5V, –40°C to +125°C

D080A

Output High Voltage

D090

I/O ports⁽³⁾

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V, –40°C to +85°C

IOH = -2.5 mA, VDD = 4.5V, –40°C to +125°C

D090A

Capacitive Loading Specs on Output Pins

D101

All I/O pins

—

50

pF

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12F519 be driven

with external clock in RC mode.

Note 1:

2:

The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operat-

ing conditions. Higher leakage current may be measured at different input voltages.

3:

4:

5:

Negative current is defined as coming out of the pin.

This specification applies to RB3/MCLR configured as RB3 with internal pull-up disabled.

This specification applies to all weak pull-up devices, including the weak pull-up found on RB3/MCLR. The current value listed will be the

same whether or not the pin is configured as RB3 with pull-up enabled or MCLR.

Preliminary

DS41319A-page 65

PIC12F519

TABLE 11-2: PULL-UP RESISTOR RANGES

Temperature

VDD (Volts)

Min

Typ

Max

Units

(°C)

RB0/RB1

2.0

5.5

–40

25

73K

82K

86K

15K

19K

23K

105K

113K

123K

132K

21K

186K

187K

190K

33K

Ω

85

125

–40

25

22K

34K

85

26K

35K

125

29K

35K

RB3

2.0

–40

25

63K

77K

82K

86K

16K

24K

26K

81K

93K

96K

100K

20K

21K

25K

27K

96K

116K

119K

22K

Ω

85

125

–40

25

5.5

23K

85

28K

125

29K

DS41319A-page 66

Preliminary

PIC12F519

11.3 Timing Parameter Symbology and Load Conditions – PIC12F519

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

T Time

Lowercase subscripts (pp) and their meanings:

pp

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

Cycle time

Device Reset Timer

I/O port

Oscillator

OSC1

t0

T0CKI

wdt

Watchdog Timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (high-impedance)

Low

Valid

L

High-impedance

FIGURE 11-3:

LOAD CONDITIONS – PIC12F519

Legend:

CL

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT or LP modes

when external clock is used

to drive OSC1

VSS

FIGURE 11-4:

EXTERNAL CLOCK TIMING – PIC12F519

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

Preliminary

DS41319A-page 67

PIC12F519

TABLE 11-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

AC CHARACTERISTICS

Operating Voltage VDD range is described in Section 11.0 “Electri-

cal Characteristics”

Param

Sym

Characteristic

Min Typ⁽¹⁾

Max Units

Conditions

No.

1A

FOSC External CLKIN Frequency⁽²⁾DC

DC

—

4

200

4

MHz XT Oscillator mode

kHz LP Oscillator mode

Oscillator Frequency⁽²⁾

DC

0.1

DC

250

5

MHz EXTRC Oscillator mode

MHz XT Oscillator mode

kHz LP Oscillator mode

ns XT Oscillator mode

μs LP Oscillator mode

ns EXTRC Oscillator mode

4

200

—

1

TOSC

External CLKIN Period⁽²⁾

Oscillator Period⁽²⁾

250

5

10,000 ns XT Oscillator mode

—

DC

—

μs LP Oscillator mode

ns

2

3

TCY

Instruction Cycle Time

200 4/FOSC

TosL, Clock in (OSC1) Low or High 50*

TosH Time

—

ns XT Oscillator

μs LP Oscillator

ns XT Oscillator

ns LP Oscillator

2*

—

4

TosR, Clock in (OSC1) Rise or Fall

TosF Time

—

25*

50*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: All specified values are based on characterization data for that particular oscillator type under standard

operating conditions with the device executing code. Exceeding these specified limits may result in an

unstable oscillator operation and/or higher than expected current consumption. When an external clock

input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

TABLE 11-2: CALIBRATED INTERNAL RC FREQUENCIES

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

-40°C ≤ TA ≤ +85°C (industrial),

-40°C ≤ TA ≤ +125°C (extended)

AC CHARACTERISTICS

Operating Voltage VDD range is described in Section 10.1

Param

Freq.

Tolerance

Sym

Characteristic

Min Typ†

Max Units

Conditions

No.

F10

FOSC

Internal Calibrated

±1%

±2%

7.92 8.00

7.84 8.00

8.08 MHz 3.5V, 25C

INTOSC Frequency⁽¹⁾

8.16 MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

±5%

7.60 8.00

8.40 MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

*

These parameters are characterized but not tested.

†

Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

DS41319A-page 68

Preliminary

PIC12F519

FIGURE 11-5:

I/O TIMING

Q1

Q2

Q3

Q4

OSC1

I/O Pin

(input)

17

18

19

I/O Pin

(output)

New Value

Old Value

20, 21

Note:

All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 11-3: TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

AC CHARACTERISTICS

Operating Voltage VDD range is described in

Param

Sym

No.

Characteristic

Min

Typ⁽¹⁾Max Units

17

18

TOSH2IOV

TOSH2IOI

OSC1↑ (Q1 cycle) to Port Out Valid^{(2), (3)}

—

100*

—

ns

OSC1↑ (Q2 cycle) to Port Input Invalid (I/O in hold

TBD

time)⁽²⁾

19

20

21

TIOV2OSH

TIOR

Port Input Valid to OSC1↑ (I/O in setup time)

Port Output Rise Time⁽³⁾

Port Output Fall Time⁽³⁾

TBD

—

10

—

ns

50**

TIOF

—

TBD = To be determined.

These parameters are characterized but not tested.

** These parameters are design targets and are not tested.

*

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

2: Measurements are taken in EXTRC mode.

3: See Figure 11-3 for loading conditions.

Preliminary

DS41319A-page 69

PIC12F519

FIGURE 11-6:

RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING

VDD

MCLR

30

Internal

POR

32

DRT

(2)

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

(1)

I/O pin

Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.

2: Runs in MCLR or WDT Reset only in XT and LP.

TABLE 11-3: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER – PIC12F519

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section TABLE 11-1: “DC CHARACTERISTICS: PIC12F519

(Industrial, Extended)”

AC CHARACTERISTICS

Param

Sym

No.

Characteristic

Min Typ⁽¹⁾Max Units

Conditions

30

31

TMCL MCLR Pulse Width (low)

2000*

—

ns

VDD = 5.0V

TWDT Watchdog Timer Time-out Period

(no prescaler)

9*

18*

30*

40*

ms

VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

32

34

TDRT

Device Reset Timer Period

Standard

9*

18*

30*

40*

ms

VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

Short

0.5* 1.125*

0.5* 1.125* 2.5*

2*

ms

VDD = 5.0V (Industrial)

VDD = 5.0V (Extended)

TIOZ

I/O High-impedance from MCLR

low

—

2000*

ns

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS41319A-page 70

Preliminary

PIC12F519

TABLE 11-4: DRT (DEVICE RESET TIMER PERIOD)

Oscillator Configuration

POR Reset

Subsequent Resets

IntRC and ExtRC

1 ms (typical)

18 ms (typical)

10 μs (typical)

XT and LP

18 ms (typical)

FIGURE 11-7:

TIMER0 CLOCK TIMINGS

T0CKI

40

41

42

TABLE 11-4: TIMER0 CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)

-40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in

Section TABLE 11-1: “DC CHARACTERISTICS: PIC12F519 (Industrial,

Extended)”

AC CHARACTERISTICS

Param

Sym

No.

Characteristic

No Prescaler

Min

Typ⁽¹⁾Max Units

Conditions

40

41

42

Tt0H T0CKI High Pulse

0.5 TCY + 20*

10*

—

ns

Width

With Prescaler

No Prescaler

With Prescaler

Tt0L T0CKI Low Pulse

Width

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40* N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Preliminary

DS41319A-page 71

PIC12F519

NOTES:

DS41319A-page 72

Preliminary

PIC12F519

12.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

Preliminary

DS41319A-page 73

PIC12F519

NOTES:

DS41319A-page 74

Preliminary

PIC12F519

13.0 PACKAGING INFORMATION

13.1 Package Marking Information

8-Lead PDIP

Example

12F519-I

XXXXXXXX

XXXXXNNN

YYWW

/P017

0610

8-Lead SOIC (3.90 mm)

Example

XXXXXXXX

12F519-I

/SN0610

017

XXXXYYWW

NNN

8-Lead MSOP

Example

XXXXXX

YWWNNN

519/MS

610017

8-Lead 2x3 DFN*

Example

X X X

Y W W

N N

B E 0

6 1 0

1 7

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PIC^®device marking consists of Microchip part number, year code, week code, and traceability

code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

Preliminary

DS41319A-page 75

PIC12F519

8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS41319A-page 76

Preliminary

PIC12F519

8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff

A2

A1

E

1.25

0.10

–

§

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

4.90 BSC

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057B

Preliminary

DS41319A-page 77

PIC12F519

8-Lead Plastic Micro Small Outline Package (MS) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

b

1

e

c

φ

A2

A

L

L1

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

0.65 BSC

Overall Height

A

–

1.10

0.95

0.15

Molded Package Thickness

Standoff

A2

A1

E

0.75

0.00

0.85

–

4.90 BSC

3.00 BSC

0.60

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

L

0.40

0.80

Footprint

L1

φ

0.95 REF

–

Foot Angle

0°

8°

Lead Thickness

Lead Width

c

0.08

0.22

–

0.23

0.40

b

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-111B

DS41319A-page 78

Preliminary

PIC12F519

8-Lead Plastic Dual Flat, No Lead Package (MC) – 2x3x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

b

N

L

K

E2

E

EXPOSED PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

NOTE 2

A3

A1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

0.50 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

D

0.02

Contact Thickness

Overall Length

Overall Width

0.20 REF

2.00 BSC

3.00 BSC

–

E

Exposed Pad Length

Exposed Pad Width

Contact Width

Contact Length

Contact-to-Exposed Pad

D2

E2

b

1.30

1.50

0.18

0.30

0.20

1.75

1.90

0.30

0.50

–

0.25

L

0.40

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-123B

Preliminary

DS41319A-page 79

PIC12F519

APPENDIX A: REVISION HISTORY

Revision A (May 2007)

Original release of this document.

DS41319A-page 80

Preliminary

PIC12F519

INDEX

MPLAB ICD 2 In-Circuit Debugger..................................... 59

MPLAB ICE 2000 High-Performance Universal

A

ALU ....................................................................................... 9

Assembler

In-Circuit Emulator...................................................... 59

MPLAB Integrated Development Environment Software.... 57

MPLAB PM3 Device Programmer ...................................... 59

MPLAB REAL ICE In-Circuit Emulator System .................. 59

MPLINK Object Linker/MPLIB Object Librarian.................. 58

MPASM Assembler..................................................... 58

B

Block Diagram

On-Chip Reset Circuit................................................. 42

Timer0......................................................................... 29

TMR0/WDT Prescaler................................................. 33

Watchdog Timer.......................................................... 45

O

OPTION Register................................................................ 17

OSC selection..................................................................... 35

OSCCAL Register............................................................... 18

Oscillator Configurations..................................................... 37

Oscillator Types

C

C Compilers

HS............................................................................... 37

LP ............................................................................... 37

RC .............................................................................. 37

XT............................................................................... 37

MPLAB C18 ................................................................ 58

MPLAB C30 ................................................................ 58

Carry ..................................................................................... 9

Clocking Scheme ................................................................ 12

Code Protection ............................................................ 35, 47

CONFIG1 Register.............................................................. 36

Configuration Bits................................................................ 35

Customer Change Notification Service ............................... 83

Customer Notification Service............................................. 83

Customer Support............................................................... 83

P

PIC12F519 Device Varieties................................................. 7

PICSTART Plus Development Programmer....................... 60

POR

Device Reset Timer (DRT) ................................... 35, 44

PD............................................................................... 46

TO............................................................................... 46

PORTB ............................................................................... 25

Power-down Mode.............................................................. 46

Prescaler ............................................................................ 32

Program Counter................................................................ 19

D

Data EEPROM Memory

Code Protection .......................................................... 24

DC and AC Characteristics................................................. 73

Development Support ......................................................... 57

Digit Carry............................................................................. 9

Q

Q cycles.............................................................................. 12

E

Errata .................................................................................... 3

R

RC Oscillator....................................................................... 38

Reader Response............................................................... 84

Read-Modify-Write.............................................................. 28

Register File Map

PIC16C57/CR57......................................................... 14

Registers

F

FSR..................................................................................... 20

FSR Register ...................................................................... 20

Fuses. See Configuration Bits

I

CONFIG1 (Configuration Word Register 1)................ 36

Special Function......................................................... 14

Reset .................................................................................. 35

I/O Interfacing ..................................................................... 27

I/O Ports.............................................................................. 25

I/O Programming Considerations........................................ 28

ID Locations.................................................................. 35, 47

INDF.................................................................................... 20

INDF Register ..................................................................... 20

Indirect Data Addressing..................................................... 20

Instruction Cycle ................................................................. 12

Instruction Flow/Pipelining .................................................. 12

Instruction Set Summary..................................................... 50

Internet Address.................................................................. 83

S

Sleep ............................................................................ 35, 46

Software Simulator (MPLAB SIM) ...................................... 58

Special Features of the CPU .............................................. 35

Special Function Registers................................................. 14

Stack................................................................................... 19

STATUS Register ........................................................... 9, 16

T

L

Timer0

Loading of PC ..................................................................... 19

Timer0 (TMR0) Module .............................................. 29

TMR0 with External Clock .......................................... 31

Timing Diagrams and Specifications .................................. 67

Timing Parameter Symbology and Load Conditions .......... 67

TRIS Registers ................................................................... 25

M

Memory Map

PIC12F519.................................................................. 13

Memory Organization.......................................................... 13

Data EEPROM Memory.............................................. 21

Program Memory (PIC12F519)................................... 13

Microchip Internet Web Site................................................ 83

MPLAB ASM30 Assembler, Linker, Librarian ..................... 58

Preliminary

DS41319A-page 81

PIC12F519

W

Wake-up from Sleep ...........................................................46

Watchdog Timer (WDT) ................................................ 35, 44

Period..........................................................................44

Programming Considerations .....................................44

WWW Address....................................................................83

WWW, On-Line Support........................................................3

Z

Zero bit..................................................................................9

DS41319A-page 82

Preliminary

PIC12F519

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS41319A-page 83

PIC12F519

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC12F519

DS41319A

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41319A-page 84

Preliminary

PIC12F519

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC12F519-I/P

package (Pb-free)

PIC12F519T-I/SL = Industrial temp., SOIC

=

Industrial temp., PDIP

b)

Device:

PIC12F519

PIC12F519T (Tape and Reel)

Temperature

Range:

I

E

=

-40°C to +85°C (Industrial)

-40°C to +125°C (Extended)

Package:

MC

MS

P

=

8L DFN 2x3 (DUAL Flatpack No-Leads)

MSOP (Pb-free)

=

300 mil PDIP (Pb-free)

SN

3.90 mm SOIC, 8-LD (Pb-free)

Pattern:

Note:

Special Requirements

Tape and Reel available for only the following packages: SOIC, MC and

MSOP.

Preliminary

DS41319A-page 85

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS41319A-page 86

Preliminary


型号：	PIC12F519T-I/MC
厂家：	MICROCHIP
描述：	8-Pin, 8-Bit Flash Microcontroller 8引脚， 8位闪存微控制器闪存微控制器和处理器外围集成电路光电二极管时钟
文件：	总88页 (文件大小：1268K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC12F519T-I/MC [MICROCHIP]

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