PIC12F615T-I/MF [MICROCHIP]
8-Pin, Flash-Based 8-Bit CMOS Microcontrollers; 8引脚，基于闪存的8位CMOS微控制器
| 型号： | PIC12F615T-I/MF |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Pin, Flash-Based 8-Bit CMOS Microcontrollers |
| 文件： | 总212页 (文件大小：1724K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12F609/615/617
PIC12HV609/615
Data Sheet
8-Pin, Flash-Based 8-Bit
CMOS Microcontrollers
*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U.S. Patent No. 5,847,450. Additional U.S. and
foreign patents and applications may be issued or pending.
2010 Microchip Technology Inc.
DS41302D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
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suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41302D-page 2
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Flash-Based, 8-Bit CMOS Microcontrollers
High-Performance RISC CPU:
Peripheral Features:
• Only 35 Instructions to Learn:
- All single-cycle instructions except branches
• Operating Speed:
• Shunt Voltage Regulator (PIC12HV609/615 only):
- 5 volt regulation
- 4 mA to 50 mA shunt range
• 5 I/O Pins and 1 Input Only
- DC – 20 MHz oscillator/clock input
- DC – 200 ns instruction cycle
• High Current Source/Sink for Direct LED Drive
• Interrupt Capability
- Interrupt-on-pin change or pins
- Individually programmable weak pull-ups
• 8-Level Deep Hardware Stack
• Direct, Indirect and Relative Addressing modes
• Analog Comparator module with:
- One analog comparator
- Programmable on-chip voltage reference
(CVREF) module (% of VDD)
- Comparator inputs and output externally
accessible
Special Microcontroller Features:
• Precision Internal Oscillator:
- Factory calibrated to ±1%, typical
- Software selectable frequency: 4 MHz or
8 MHz
- Built-In Hysteresis (software selectable)
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Power-Saving Sleep mode
• Voltage Range:
• Enhanced Timer1:
- PIC12F609/615/617: 2.0V to 5.5V
- 16-bit timer/counter with prescaler
- External Timer1 Gate (count enable)
- Option to use OSC1 and OSC2 in LP mode
as Timer1 oscillator if INTOSC mode
selected
- Option to use system clock as Timer1
• In-Circuit Serial ProgrammingTM (ICSPTM) via Two
- PIC12HV609/615: 2.0V to user defined
maximum (see note)
• Industrial and Extended Temperature Range
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
Pins
• Brown-out Reset (BOR)
PIC12F615/617/HV615 ONLY:
• Watchdog Timer (WDT) with independent
Oscillator for Reliable Operation
• Enhanced Capture, Compare, PWM module:
• Multiplexed Master Clear with Pull-up/Input Pin
• Programmable Code Protection
• High Endurance Flash:
- 16-bit Capture, max. resolution 12.5 ns
- Compare, max. resolution 200 ns
- 10-bit PWM with 1 or 2 output channels, 1
output channel programmable “dead time,”
max. frequency 20 kHz, auto-shutdown
- 100,000 write Flash endurance
- Flash retention: > 40 years
• A/D Converter:
• Self Read/ Write Program Memory (PIC12F617
only)
- 10-bit resolution and 4 channels, samples
internal voltage references
Low-Power Features:
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Standby Current:
- 50 nA @ 2.0V, typical
• Operating Current:
- 11 A @ 32 kHz, 2.0V, typical
- 260 A @ 4 MHz, 2.0V, typical
• Watchdog Timer Current:
- 1 A @ 2.0V, typical
Note:
Voltage across the shunt regulator should
not exceed 5V.
2010 Microchip Technology Inc.
DS41302D-page 3
PIC12F609/615/617/12HV609/615
Program
Memory
Data Memory
Self Read/
Self Write
10-bit A/D
(ch)
Timers
8/16-bit
Device
I/O
Comparators ECCP
Voltage Range
Flash
(words)
SRAM (bytes)
PIC12F609
PIC12HV609
PIC12F615
PIC12HV615
PIC12F617
1024
1024
1024
1024
2048
64
64
5
5
5
5
5
0
0
4
4
4
1
1
1
1
1
1/1
1/1
2/1
2/1
2/1
2.0V-5.5V
2.0V-user defined
2.0V-5.5V
—
—
—
—
64
YES
YES
YES
—
64
2.0V-user defined
2.0V-5.5V
—
128
YES
8-Pin Diagram, PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/CIN1-/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
VSS
8
7
6
5
1
2
GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT
PIC12F609/
HV609
3
4
TABLE 1:
I/O
PIC12F609/HV609 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
Pin
Comparators
Timer
Interrupts
Pull-ups
Basic
GP0
GP1
GP2
GP3(1)
GP4
GP5
—
7
6
5
4
3
2
1
8
CIN+
CIN0-
COUT
—
—
—
IOC
IOC
INT/IOC
IOC
IOC
IOC
—
Y
Y
ICSPDAT
ICSPCLK
—
T0CKI
—
Y
Y(2)
MCLR/VPP
OSC2/CLKOUT
OSC1/CLKIN
VDD
CIN1-
—
T1G
T1CKI
—
Y
Y
—
—
—
—
—
—
—
VSS
Note 1: Input only.
2: Only when pin is configured for external MCLR.
DS41302D-page 4
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
8-Pin Diagram, PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN)
VDD
GP5/T1CKI/P1A*/OSC1/CLKIN
VSS
8
7
6
5
1
2
GP0/AN0/CIN+/P1B/ICSPDAT
GP1/AN1/CIN0-/VREF/ICSPCLK
GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
PIC12F615/
617/HV615
GP4/AN3/CIN1-/T1G/P1B*/OSC2/CLKOUT
GP3/T1G*/MCLR/VPP
3
4
*
Alternate pin function.
TABLE 2:
PIC12F615/617/HV615 PIN SUMMARY (PDIP, SOIC, MSOP, DFN)
Comparator
I/O
Pin
Analog
Timer
CCP
Interrupts Pull-ups
Basic
s
GP0
GP1
GP2
GP3(1)
GP4
GP5
—
7
6
5
4
3
2
1
8
AN0
AN1
AN2
—
CIN+
CIN0-
COUT
—
—
—
P1B
—
IOC
IOC
INT/IOC
IOC
IOC
IOC
—
Y
Y
ICSPDAT
ICSPCLK/VREF
—
T0CKI
T1G*
T1G
T1CKI
—
CCP1/P1A
—
Y
Y(2)
MCLR/VPP
OSC2/CLKOUT
OSC1/CLKIN
VDD
AN3
—
CIN1-
—
P1B*
P1A*
—
Y
Y
—
—
—
—
—
—
—
—
—
—
VSS
*
Alternate pin function.
Note 1: Input only.
2: Only when pin is configured for external MCLR.
2010 Microchip Technology Inc.
DS41302D-page 5
PIC12F609/615/617/12HV609/615
Table of Contents
1.0 Device Overview ......................................................................................................................................................................... 7
2.0 Memory Organization................................................................................................................................................................ 11
3.0 Flash Program Memory Self Read/Self Write Control (PIC12F617 only).................................................................................. 27
4.0 Oscillator Module ....................................................................................................................................................................... 37
5.0 I/O Port ...................................................................................................................................................................................... 43
6.0 Timer0 Module .......................................................................................................................................................................... 53
7.0 Timer1 Module with Gate Control .............................................................................................................................................. 57
8.0 Timer2 Module (PIC12F615/617/HV615 only) .......................................................................................................................... 65
9.0 Comparator Module ................................................................................................................................................................... 67
10.0 Analog-to-Digital Converter (ADC) Module (PIC12F615/617/HV615 only) ............................................................................... 79
11.0 Enhanced Capture/Compare/PWM (With Auto-Shutdown and Dead Band) Module (PIC12F615/617/HV615 only) ............... 89
12.0 Special Features of the CPU ................................................................................................................................................... 107
13.0 Voltage Regulator .................................................................................................................................................................... 127
14.0 Instruction Set Summary ........................................................................................................................................................ 129
15.0 Development Support ............................................................................................................................................................. 139
16.0 Electrical Specifications ........................................................................................................................................................... 143
17.0 DC and AC Characteristics Graphs and Tables ...................................................................................................................... 171
18.0 Packaging Information ............................................................................................................................................................ 195
Appendix A: Data Sheet Revision History ......................................................................................................................................... 203
®
Appendix B: Migrating from other PIC Devices ............................................................................................................................... 203
Index ................................................................................................................................................................................................. 205
The Microchip Web Site .................................................................................................................................................................... 209
Customer Change Notification Service ............................................................................................................................................. 209
Customer Support ............................................................................................................................................................................. 209
Reader Response ............................................................................................................................................................................. 210
Product Identification System ............................................................................................................................................................ 211
Worldwide Sales and Service ........................................................................................................................................................... 212
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DS41302D-page 6
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
Block Diagrams and pinout descriptions of the devices
are as follows:
1.0
DEVICE OVERVIEW
The PIC12F609/615/617/12HV609/615 devices are
covered by this data sheet. They are available in 8-pin
PDIP, SOIC, MSOP and DFN packages.
• PIC12F609/HV609 (Figure 1-1, Table 1-1)
• PIC12F615/617/HV615 (Figure 1-2, Table 1-2)
FIGURE 1-1:
PIC12F609/HV609 BLOCK DIAGRAM
INT
Configuration
13
8
GPIO
Data Bus
Program Counter
GP0
Flash
GP1
GP2
GP3
GP4
GP5
1K X 14
Program
Memory
RAM
64 Bytes
File
Registers
8-Level Stack
(13-Bit)
Program
Bus
14
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
7
Direct Addr
8
FSR Reg
STATUS Reg
8
3
Power-up
Timer
MUX
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Watchdog
Timer
OSC1/CLKIN
Timing
Generation
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Block
Shunt Regulator
(PIC12HV609 only)
VDD
VSS
MCLR
T1G
T1CKI
T0CKI
Timer0
Timer1
Comparator Voltage Reference
Absolute Voltage Reference
Analog Comparator
and Reference
2010 Microchip Technology Inc.
DS41302D-page 7
PIC12F609/615/617/12HV609/615
FIGURE 1-2:
PIC12F615/617/HV615 BLOCK DIAGRAM
INT
Configuration
13
8
GPIO
Data Bus
Program Counter
Flash
GP0
GP1
GP2
GP3
GP4
GP5
1K X 14
and
2K X 14**
Program
Memory
RAM
64 Bytes and
128 Bytes**
File
8-Level Stack
(13-Bit)
Registers
Program
Bus
14
RAM Addr
9
Addr MUX
Instruction Reg
Indirect
Addr
7
Direct Addr
8
FSR Reg
STATUS Reg
8
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Watchdog
Timer
OSC1/CLKIN
Timing
Generation
W Reg
Brown-out
Reset
OSC2/CLKOUT
Internal
Oscillator
Shunt Regulator
T1G*
Block
(PIC12HV615 only)
VDD
VSS
MCLR
T1G
T1CKI
T0CKI
Timer0
Timer1
Timer2
Comparator Voltage Reference
Absolute Voltage Reference
Analog Comparator
and Reference
Analog-To-Digital Converter
ECCP
*
Alternate pin function.
** For the PIC12F617 only.
DS41302D-page 8
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 1-1:
PIC12F609/HV609 PINOUT DESCRIPTION
Input
Type
Output
Type
Name
Function
Description
GP0/CIN+/ICSPDAT
GP1/CIN0-/ICSPCLK
GP2/T0CKI/INT/COUT
GP0
CIN+
TTL
AN
ST
CMOS General purpose I/O with prog. pull-up and interrupt-on-change
Comparator non-inverting input
—
ICSPDAT
GP1
CMOS Serial Programming Data I/O
TTL
AN
ST
CMOS General purpose I/O with prog. pull-up and interrupt-on-change
CIN0-
ICSPCLK
GP2
—
Comparator inverting input
Serial Programming Clock
—
ST
CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T0CKI
INT
ST
—
—
Timer0 clock input
External Interrupt
ST
COUT
GP3
—
CMOS Comparator output
GP3/MCLR/VPP
TTL
ST
—
—
—
General purpose input with interrupt-on-change
MCLR
VPP
Master Clear w/internal pull-up
Programming voltage
HV
TTL
AN
GP4/CIN1-/T1G/OSC2/
CLKOUT
GP4
CMOS General purpose I/O with prog. pull-up and interrupt-on-change
—
Comparator inverting input
Timer1 gate (count enable)
CIN1-
T1G
ST
—
—
OSC2
CLKOUT
GP5
XTAL Crystal/Resonator
—
CMOS FOSC/4 output
GP5/T1CKI/OSC1/CLKIN
TTL
ST
CMOS General purpose I/O with prog. pull-up and interrupt-on-change
T1CKI
OSC1
CLKIN
VDD
—
—
—
—
—
Timer1 clock input
XTAL
ST
Crystal/Resonator
External clock input/RC oscillator connection
Positive supply
VDD
VSS
Power
Power
VSS
Ground reference
Legend: AN=Analog input or output
ST=Schmitt Trigger input with CMOS levels
CMOS= CMOS compatible input or output HV= High Voltage
TTL = TTL compatible input XTAL=Crystal
2010 Microchip Technology Inc.
DS41302D-page 9
PIC12F609/615/617/12HV609/615
TABLE 1-2:
PIC12F615/617/HV615 PINOUT DESCRIPTION
Input
Type
Output
Type
Name
Function
Description
GP0/AN0/CIN+/P1B/ICSPDAT
GP0
TTL
CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN0
CIN+
AN
AN
—
—
—
A/D Channel 0 input
Comparator non-inverting input
P1B
CMOS PWM output
ICSPDAT
GP1
ST
TTL
CMOS Serial Programming Data I/O
GP1/AN1/CIN0-/VREF/ICSPCLK
CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN1
CIN0-
VREF
AN
AN
AN
ST
ST
—
—
—
—
A/D Channel 1 input
Comparator inverting input
External Voltage Reference for A/D
Serial Programming Clock
ICSPCLK
GP2
GP2/AN2/T0CKI/INT/COUT/CCP1/
P1A
CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN2
T0CKI
INT
AN
ST
ST
—
—
—
—
A/D Channel 2 input
Timer0 clock input
External Interrupt
COUT
CCP1
P1A
CMOS Comparator output
ST
—
CMOS Capture input/Compare input/PWM output
CMOS PWM output
GP3/T1G*/MCLR/VPP
GP3
TTL
ST
ST
HV
TTL
—
—
—
—
General purpose input with interrupt-on-change
Timer1 gate (count enable), alternate pin
Master Clear w/internal pull-up
T1G*
MCLR
VPP
Programming voltage
GP4/AN3/CIN1-/T1G/P1B*/OSC2/
CLKOUT
GP4
CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
AN3
CIN1-
T1G
AN
AN
—
A/D Channel 3 input
—
Comparator inverting input
ST
—
—
Timer1 gate (count enable)
P1B*
CMOS PWM output, alternate pin
XTAL Crystal/Resonator
CMOS FOSC/4 output
OSC2
CLKOUT
GP5
—
—
GP5/T1CKI/P1A*/OSC1/CLKIN
TTL
CMOS General purpose I/O with prog. pull-up and interrupt-on-
change
T1CKI
P1A*
OSC1
CLKIN
VDD
ST
—
—
Timer1 clock input
CMOS PWM output, alternate pin
XTAL
ST
—
—
—
—
Crystal/Resonator
External clock input/RC oscillator connection
Positive supply
VDD
VSS
Power
Power
VSS
Ground reference
*
Alternate pin function.
Legend: AN=Analog input or output
ST=Schmitt Trigger input with CMOS levels TTL = TTL compatible input
CMOS=CMOS compatible input or output HV= High Voltage
XTAL=Crystal
DS41302D-page 10
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F617
2.0
2.1
MEMORY ORGANIZATION
Program Memory Organization
The PIC12F609/615/617/12HV609/615 has a 13-bit
program counter capable of addressing an 8K x 14
program memory space. Only the first 1K x 14 (0000h-
03FFh) for the PIC12F609/615/12HV609/615 is
physically implemented. For the PIC12F617, the first
2K x 14 (0000h-07FFh) is physically implemented.
Accessing a location above these boundaries will
cause a wrap-around within the first 1K x 14 space for
PIC12F609/615/12HV609/615 devices, and within the
first 2K x 14 space for the PIC12F617 device. The
Reset vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
Interrupt Vector
Page 0
0004h
0005h
PIC12F609/615/12HV609/615
On-Chip
Program
Memory
07FFh
0800h
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Wraps to 0000h-07FFh
1FFFh
Stack Level 1
Stack Level 2
2.2
Data Memory Organization
The data memory (see Figure 2-3) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 40h-7Fh in
Bank 0 are General Purpose Registers, implemented as
static RAM. For the PIC12F617, the register locations
20h-7Fh in Bank 0 and A0h-EFh in Bank 1 are general
purpose registers implemented as Static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. The RP0 bit of the STATUS register is the
bank select bit.
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0400h
RP0
Wraps to 0000h-03FFh
0
1
Bank 0 is selected
Bank 1 is selected
1FFFh
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always be
maintained as ‘0’s.
2010 Microchip Technology Inc.
DS41302D-page 11
PIC12F609/615/617/12HV609/615
2.2.1
GENERAL PURPOSE REGISTER
FILE
FIGURE 2-3:
DATA MEMORY MAP OF
THE PIC12F609/HV609
The register file is organized as 64 x 8 in the
PIC12F609/615/12HV609/615, and as 128 x 8 in the
PIC12F617. Each register is accessed, either directly
or indirectly, through the File Select Register (FSR)
(see Section 2.4 “Indirect Addressing, INDF and
FSR Registers”).
File
Address
File
Address
Indirect Addr.(1)
Indirect Addr.(1)
OPTION_REG
PCL
00h
01h
02h
80h
81h
82h
TMR0
PCL
STATUS
FSR
STATUS
FSR
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
2.2.2
SPECIAL FUNCTION REGISTERS
GPIO
TRISIO
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
PCON
OSCTUNE
WPU
IOC
VRCON
CMCON0
CMCON1
ANSEL
9Fh
A0h
3Fh
40h
General
Purpose
Registers
64 Bytes
EFh
F0h
6Fh
70h
Accesses 70h-7Fh
Bank 1
Accesses 70h-7Fh
Bank 0
7Fh
FFh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
DS41302D-page 12
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 2-4:
DATA MEMORY MAP OF
THEPIC12F615/617/HV615
File
File
Address
Address
Indirect Addr.(1)
Indirect Addr.(1)
OPTION_REG
PCL
00h
01h
02h
80h
81h
82h
TMR0
PCL
STATUS
FSR
STATUS
FSR
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
GPIO
TRISIO
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
TMR1L
TMR1H
PCON
T1CON
OSCTUNE
TMR2
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
PWM1CON
ECCPAS
APFCON
WPU
IOC
PMCON1(2)
PMCON2(2)
PMADRL(2)
PMADRH(2)
PMDATL(2)
PMDATH(2)
ADRESL
VRCON
CMCON0
CMCON1
ADRESH
ADCON0
ANSEL
9Fh
A0h
General
Purpose
Registers
General
Purpose
Registers
96 Bytes from
20h-7Fh(2)
32 Bytes(2)
Unimplemented for
PIC12F615/HV615
Unimplemented for
PIC12F615/HV615
BFh
C0h
3Fh
40h
General
Purpose
Registers
64 Bytes
6Fh
70h
EFh
F0h
Accesses 70h-7Fh
Bank 0
Accesses 70h-7Fh
Bank 1
7Fh
FFh
Unimplemented data memory locations, read as ‘0’.
Note 1: Not a physical register.
2: Used for the PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 13
PIC12F609/615/617/12HV609/615
TABLE 2-1:
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
TMR0
PCL
STATUS
FSR
GPIO
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx 25, 115
xxxx xxxx 53, 115
0000 0000 25, 115
0001 1xxx 18, 115
xxxx xxxx 25, 115
--x0 x000 43, 115
Program Counter’s (PC) Least Significant Byte
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
—
GP5
GP4
GP3
GP2
GP1
GP0
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIR1
—
—
PEIE
—
—
T0IE
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 25, 115
0000 0000 20, 115
GIE
INTE
—
GPIE
CMIF
T0IF
—
INTF
—
GPIF
—
TMR1IF ---- 0--0 22, 115
Unimplemented
—
—
TMR1L
TMR1H
T1CON
—
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57, 115
xxxx xxxx 57, 115
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 62, 115
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
CMVREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
—
—
—
—
—
—
—
VRCON
CMCON0
—
—
VRR
FVREN
CMPOL
VR3
—
VR2
VR1
—
VR0
0-00 0000 76, 116
0000 -0-0 72, 116
CMON
COUT
CMOE
CMR
CMCH
—
—
—
—
CMCON1
—
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC ---0 0-10 73, 116
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
Read only register.
1:
2:
DS41302D-page 14
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 2-2:
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
xxxx xxxx 25, 116
xxxx xxxx 53, 116
0000 0000 25, 116
0001 1xxx 18, 116
xxxx xxxx 25, 116
--x0 x000 43, 116
TMR0
PCL
Program Counter’s (PC) Least Significant Byte
STATUS
FSR
IRP(1)
RP1(1)
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIR1
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 25, 116
0000 0000 20, 116
GIE
PEIE
ADIF
T0IE
INTE
—
GPIE
CMIF
T0IF
—
INTF
GPIF
—
CCP1IF
TMR2IF
TMR1IF -00- 0-00 22, 116
—
Unimplemented
—
—
TMR1L
TMR1H
T1CON
TMR2(3)
T2CON(3)
CCPR1L(3)
CCPR1H(3)
CCP1CON(3)
PWM1CON(3)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx 57, 116
xxxx xxxx 57, 116
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS TMR1ON 0000 0000 62, 116
Timer2 Module Register
0000 0000 65, 116
12h
13h
14h
15h
16h
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 66, 116
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 1 High Byte
XXXX XXXX 90, 116
XXXX XXXX 90, 116
P1M
—
DC1B1
PDC5
DC1B0
PDC4
CCP1M3
PDC3
CCP1M2
PDC2
CCP1M1
PDC1
CCP1M0 0-00 0000 89, 116
PRSEN
PDC6
PDC0
0000 0000
105,
116
17h
ECCPAS(3)
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1
Unimplemented
PSSAC0
PSSBD1
PSSBD0 0000 0000
102,
116
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
—
VRCON
CMCON0
—
—
—
CMVREN
CMON
—
VRR
FVREN
CMPOL
VR3
—
VR2
VR1
—
VR0
0-00 0000 76, 116
0000 -0-0 72, 116
COUT
CMOE
CMR
CMCH
—
—
—
—
CMCON1
—
—
—
T1ACS
CMHYS
—
T1GSS
CMSYNC ---0 0-10 73, 116
—
Unimplemented
—
—
ADRESH(2, 3) Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result
ADCON0(3)
ADFM VCFG CHS2 CHS1 CHS0 GO/DONE
xxxx xxxx 85, 116
00-0 0000 84, 116
—
ADON
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1:
IRP and RP1 bits are reserved, always maintain these bits clear.
2:
3:
Read only register.
PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 15
PIC12F609/615/617/12HV609/615
TABLE 2-3:
PIC12F609/HV609 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 25, 116
1111 1111 19, 116
81h
OPTION_RE
G
T0SE
PSA
PS2
PS1
PS0
GPPU
INTEDG
T0CS
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
PCL
STATUS
FSR
TRISIO
—
Program Counter’s (PC) Least Significant Byte
IRP(1) RP1(1)
RP0 TO
Indirect Data Memory Address Pointer
0000 0000 25, 116
0001 1xxx 18, 116
xxxx xxxx 25, 116
PD
Z
DC
C
—
—
TRISIO5
TRISIO4 TRISIO3(4) TRISIO2
TRISIO1
TRISIO0 --11 1111 44, 116
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
PEIE
—
—
T0IE
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 25, 116
0000 0000 20, 116
GIE
INTE
—
GPIE
CMIE
T0IF
—
INTF
—
GPIF(3)
—
TMR1IE ---- 0--0 21, 116
Unimplemented
—
—
—
PCON
—
—
—
—
—
—
—
—
POR
BOR
---- --qq 23, 116
Unimplemented
—
—
—
OSCTUNE
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000 41, 116
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
WPU(2)
IOC
—
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111 46, 116
--00 0000 46, 116
—
IOC3
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ANSEL
—
—
—
ANS3
—
ANS1
ANS0
---- 1-11 45, 117
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3:
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4:
TRISIO3 always reads as ‘1’ since it is an input only pin.
DS41302D-page 16
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 2-4:
PIC12F615/617/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx 25, 116
1111 1111 19, 116
0000 0000 25, 116
0001 1xxx 18, 116
xxxx xxxx 25, 116
OPTION_REG
PCL
GPPU
Program Counter’s (PC) Least Significant Byte
IRP(1) RP1(1)
RP0 TO
Indirect Data Memory Address Pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
STATUS
FSR
PD
Z
DC
C
TRISIO
—
—
—
TRISIO5
TRISIO4 TRISIO3(4) TRISIO2
TRISIO1
TRISIO0 --11 1111 44, 116
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 25, 116
0000 0000 20, 116
GIE
PEIE
ADIE
T0IE
INTE
—
GPIE
CMIE
T0IF
—
INTF
GPIF(3)
—
CCP1IE
TMR2IE
TMR1IE -00- 0-00 21, 116
—
Unimplemented
—
—
—
PCON
—
—
—
—
—
—
—
—
POR
BOR
---- --qq 23, 116
Unimplemented
—
—
—
OSCTUNE
—
TUN4
TUN3
TUN2
TUN1
TUN0
---0 0000 41, 116
Unimplemented
—
—
PR2
Timer2 Module Period Register
1111 1111 65, 116
P1ASEL ---0 --00 21, 116
APFCON
—
—
—
T1GSEL
—
—
P1BSEL
—
Unimplemented
—
—
WPU(2)
IOC
—
—
—
WPU5
IOC5
WPU4
IOC4
—
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
--11 -111 46, 116
--00 0000 46, 116
—
IOC3
—
Unimplemented
—
—
—
29
—
PMCON1(7)
PMCON2(7)
PMADRL(7)
PMADRH(7)
PMDATL(7)
PMDATH(7)
ADRESL(5, 6)
ANSEL
—
—
—
—
WREN
WR
RD
---- -000
---- ----
Program Memory Control Register 2 (not a physical register).
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000
PMADRH2 PMADRH1 PMADRH0 ---- -000
PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000
Program Memory Data Register High Byte. --00 0000
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
ADCS2 ADCS1 ADCS0 ANS3 ANS2
28
28
28
28
—
—
—
—
—
—
—
xxxx xxxx 85, 117
-000 1111 45, 117
—
ANS1
ANS0
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
3:
MCLR and WDT Reset does not affect the previous value data latch. The GPIF bit will clear upon Reset but will set again if the mismatch
exists.
4:
5:
6:
7:
TRISIO3 always reads as ‘1’ since it is an input only pin.
Read only register.
PIC12F615/617/HV615 only.
PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 17
PIC12F609/615/617/12HV609/615
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits, see the Section 14.0
“Instruction Set Summary”.
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (RAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC12F609/615/617/
12HV609/615 and should be maintained
as clear. Use of these bits is not recom-
mended, since this may affect upward
compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS,will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’(where u= unchanged).
REGISTER 2-1:
STATUS: STATUS REGISTER
Reserved
IRP
Reserved
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
bit 6
bit 5
IRP: This bit is reserved and should be maintained as ‘0’
RP1: This bit is reserved and should be maintained as ‘0’
RP0: Register Bank Select bit (used for direct addressing)
1= Bank 1 (80h – FFh)
0= Bank 0 (00h – 7Fh)
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions), For Borrow, the polarity is
reversed.
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS41302D-page 18
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.2
OPTION Register
Note:
To achieve a 1:1 prescaler assignment for
Timer0, assign the prescaler to the WDT
by setting PSA bit to ‘1’ of the OPTION
register. See Section 6.1.3 “Software
Programmable Prescaler”.
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
• Timer0/WDT prescaler
• External GP2/INT interrupt
• Timer0
• Weak pull-ups on GPIO
REGISTER 2-2:
OPTION_REG: OPTION REGISTER
R/W-1
GPPU
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPPU: GPIO Pull-up Enable bit
1= GPIO pull-ups are disabled
0= GPIO pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of GP2/INT pin
0= Interrupt on falling edge of GP2/INT pin
T0CS: Timer0 Clock Source Select bit
1= Transition on GP2/T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
T0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on GP2/T0CKI pin
0= Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
BIT VALUE TIMER0 RATE WDT RATE
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 1
1 : 2
1 : 8
1 : 4
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
2010 Microchip Technology Inc.
DS41302D-page 19
PIC12F609/615/617/12HV609/615
2.2.2.3
INTCON Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO change and external
GP2/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-0
GPIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: GP2/INT External Interrupt Enable bit
1= Enables the GP2/INT external interrupt
0= Disables the GP2/INT external interrupt
GPIE: GPIO Change Interrupt Enable bit(1)
1= Enables the GPIO change interrupt
0= Disables the GPIO change interrupt
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1= Timer0 register has overflowed (must be cleared in software)
0= Timer0 register did not overflow
INTF: GP2/INT External Interrupt Flag bit
1= The GP2/INT external interrupt occurred (must be cleared in software)
0= The GP2/INT external interrupt did not occur
GPIF: GPIO Change Interrupt Flag bit
1= When at least one of the GPIO <5:0> pins changed state (must be cleared in software)
0= None of the GPIO <5:0> pins have changed state
Note 1: IOC register must also be enabled.
2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
DS41302D-page 20
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.4
PIE1 Register
The PIE1 register contains the Peripheral Interrupt
Enable bits, as shown in Register 2-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
—
R/W-0
ADIE(1)
R/W-0
CCP1IE(1)
U-0
—
R/W-0
CMIE
U-0
—
R/W-0
TMR2IE(1)
R/W-0
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIE: A/D Converter (ADC) Interrupt Enable bit(1)
1= Enables the ADC interrupt
0= Disables the ADC interrupt
bit 5
CCP1IE: CCP1 Interrupt Enable bit(1)
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 4
bit 3
Unimplemented: Read as ‘0’
CMIE: Comparator Interrupt Enable bit
1= Enables the Comparator interrupt
0= Disables the Comparator interrupt
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IE: Timer2 to PR2 Match Interrupt Enable bit(1)
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
bit 0
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
2010 Microchip Technology Inc.
DS41302D-page 21
PIC12F609/615/617/12HV609/615
2.2.2.5
PIR1 Register
The PIR1 register contains the Peripheral Interrupt flag
bits, as shown in Register 2-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
—
R/W-0
ADIF(1)
R/W-0
CCP1IF(1)
U-0
—
R/W-0
CMIF
U-0
—
R/W-0
TMR2IF(1)
R/W-0
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Read as ‘0’
ADIF: A/D Interrupt Flag bit(1)
1= A/D conversion complete
0= A/D conversion has not completed or has not been started
CCP1IF: CCP1 Interrupt Flag bit(1)
bit 5
Capture mode:
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare mode:
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CMIF: Comparator Interrupt Flag bit
1= Comparator output has changed (must be cleared in software)
0= Comparator output has not changed
bit 2
bit 1
Unimplemented: Read as ‘0’
TMR2IF: Timer2 to PR2 Match Interrupt Flag bit(1)
1= Timer2 to PR2 match occurred (must be cleared in software)
0= Timer2 to PR2 match has not occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Timer1 register overflowed (must be cleared in software)
0= Timer1 has not overflowed
Note 1: PIC12F615/617/HV615 only. PIC12F609/HV609 unimplemented, read as ‘0’.
DS41302D-page 22
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.2.2.6
PCON Register
The Power Control (PCON) register (see Table 12-2)
contains flag bits to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-6.
REGISTER 2-6:
PCON: POWER CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-0(1)
BOR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1
Unimplemented: Read as ‘0’
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: Reads as ‘0’ if Brown-out Reset is disabled.
2010 Microchip Technology Inc.
DS41302D-page 23
PIC12F609/615/617/12HV609/615
2.2.2.7
APFCON Register
(PIC12F615/617/HV615 only)
The Alternate Pin Function Control (APFCON) register
is used to steer specific peripheral input and output
functions between different pins. For this device, the
P1A, P1B and Timer1 Gate functions can be moved
between different pins.
The APFCON register bits are shown in Register 2-7.
REGISTER 2-7:
APFCON:ALTERNATE PIN FUNCTION REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
T1GSEL
P1BSEL
P1ASEL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
T1GSEL: TMR1 Input Pin Select bit
1= T1G function is on GP3/T1G(2)/MCLR/VPP
0= T1G function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT
bit 3-2
bit 1
Unimplemented: Read as ‘0’
P1BSEL: P1B Output Pin Select bit
1= P1B function is on GP4/AN3/CIN1-/T1G/P1B(2)/OSC2/CLKOUT
0= P1B function is on GP0/AN0/CIN+/P1B/ICSPDAT
bit 0
P1ASEL: P1A Output Pin Select bit
1= P1A function is on GP5/T1CKI/P1A(2)/OSC1/CLKIN
0= P1A function is on GP2/AN2/T0CKI/INT/COUT/CCP1/P1A
Note 1: PIC12F615/617/HV615 only.
2: Alternate pin function.
DS41302D-page 24
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
2.3.2
STACK
2.3
PCL and PCLATH
The PIC12F609/615/617/12HV609/615 Family has an
8-level x 13-bit wide hardware stack (see Figure 2-1).
The stack space is not part of either program or data
space and the Stack Pointer is not readable or writable.
The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a branch.
The stack is POPed in the event of a RETURN, RETLW
or a RETFIE instruction execution. PCLATH is not
affected by a PUSH or POP operation.
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-5 shows the two
situations for the loading of the PC. The upper example
in Figure 2-5 shows how the PC is loaded on a write to
PCL (PCLATH<4:0> PCH). The lower example in
Figure 2-5 shows how the PC is loaded during a CALLor
GOTOinstruction (PCLATH<4:3> PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Instruction with
Note 1: There are no Status bits to indicate stack
12
8
7
0
PCL as
overflow or stack underflow conditions.
Destination
PC
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
8
PCLATH<4:0>
PCLATH
5
ALU Result
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
2.4
Indirect Addressing, INDF and
FSR Registers
PCLATH<4:3>
PCLATH
11
2
OPCODE <10:0>
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-6.
2.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC<12:8> bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper 5 bits to the PCLATH register.
When the lower 8 bits are written to the PCL register,
all 13 bits of the program counter will change to the
values contained in the PCLATH register and those
being written to the PCL register.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
INDIRECT ADDRESSING
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). Care should be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower 8 bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
MOVLW
MOVWF
0x40
FSR
;initialize pointer
;to RAM
NEXT
CLRF
INCF
BTFSS
GOTO
INDF
FSR
;clear INDF register
;inc pointer
FSR,7
NEXT
;all done?
;no clear next
;yes continue
CONTINUE
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2010 Microchip Technology Inc.
DS41302D-page 25
PIC12F609/615/617/12HV609/615
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING PIC12F609/615/617/12HV609/615
Direct Addressing
Indirect Addressing
(1)
(1)
From Opcode
7
RP1
RP0
6
0
0
IRP
File Select Register
Bank Select
180h
Location Select
Bank Select
Location Select
00h
00
01
10
11
(2)
Data
Memory
NOT USED
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail, see Figure 2-3.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
2: Accesses in this area are mirrored back into Bank 0 and Bank 1.
DS41302D-page 26
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
3.1
PMADRH and PMADRL Registers
3.0
FLASH PROGRAM MEMORY
SELF READ/SELF WRITE
CONTROL (FOR PIC12F617
ONLY)
The PMADRH and PMADRL registers can address up
to a maximum of 8K words of program memory.
When selecting a program address value, the Most
Significant Byte (MSB) of the address is written to the
PMADRH register and the Least Significant Byte
(LSB) is written to the PMADRL register.
The Flash program memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers (see Registers 3-1 to 3-5). There
are six SFRs used to read and write this memory:
3.2
PMCON1 and PMCON2 Registers
PMCON1 is the control register for the data program
memory accesses.
• PMCON1
• PMCON2
• PMDATL
• PMDATH
• PMADRL
• PMADRH
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental premature
termination of a write operation.
When interfacing the program memory block, the
PMDATL and PMDATH registers form a two-byte word
which holds the 14-bit data for read/write, and the
PMADRL and PMADRH registers form a two-byte
word which holds the 13-bit address of the Flash loca-
tion being accessed. These devices have 2K words of
program Flash with an address range from 0000h to
07FFh.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear.
PMCON2 is not a physical register. Reading PMCON2
will read all ‘0’s. The PMCON2 register is used
exclusively in the Flash memory write sequence.
The program memory allows single word read and a
by four word write. A four word write automatically
erases the row of the location and writes the new data
(erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range
of the device for byte or word operations.
When the device is code-protected, the CPU may
continue to read and write the Flash program memory.
Depending on the settings of the Flash Program
Memory Enable (WRT<1:0>) bits, the device may or
may not be able to write certain blocks of the program
memory, however, reads of the program memory are
allowed.
When the Flash program memory Code Protection
(CP) bit in the Configuration Word register is enabled,
the program memory is code-protected, and the
device programmer (ICSP™) cannot access data or
program memory.
2010 Microchip Technology Inc.
DS41302D-page 27
PIC12F609/615/617/12HV609/615
REGISTER 3-1:
R/W-0
PMDATL: PROGRAM MEMORY DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMDATL7
bit 7
PMDATL6
PMDATL5
PMDATL4
PMDATL3
PMDATL2
PMDATL1
PMDATL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PMDATL<7:0>: 8 Least Significant Address bits to Write or Read from Program Memory
REGISTER 3-2:
R/W-0
PMADRL: PROGRAM MEMORY ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMADRL7
bit 7
PMADRL6
PMADRL5
PMADRL4
PMADRL3
PMADRL2
PMADRL1
PMADRL0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
PMADRL<7:0>: 8 Least Significant Address bits for Program Memory Read/Write Operation
REGISTER 3-3:
PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMDATH5
PMDATH4
PMDATH3
PMDATH2
PMDATH1
PMDATH0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
PMDATH<5:0>: 6 Most Significant Data bits from Program Memory
REGISTER 3-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PMADRH2
PMADRH1
PMADRH0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 3
Unimplemented: Read as ‘0’
PMADRH<2:0>: Specifies the 3 Most Significant Address bits or high bits for program memory reads.
bit 2-0
DS41302D-page 28
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 3-5:
PMCON1 – PROGRAM MEMORY CONTROL REGISTER 1 (ADDRESS: 93h)
U-1
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
WREN
R/S-0
WR
R/S-0
RD
bit 7
bit 0
bit 7
Unimplemented: Read as ‘1’
Unimplemented: Read as ‘0’
bit 6-3
bit 2
WREN: Program Memory Write Enable bit
1= Allows write cycles
0= Inhibits write to the EEPROM
bit 1
bit 0
WR: Write Control bit
1= Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete. The
WR bit can only be set (not cleared) in software.)
0= Write cycle to the Flash memory is complete
RD: Read Control bit
1= Initiates a program memory read (The read takes one cycle. The RD is cleared in hardware; the RD bit
can only be set (not cleared) in software).
0= Does not initiate a Flash memory read
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc.
DS41302D-page 29
PIC12F609/615/617/12HV609/615
3.3
Reading the Flash Program
Memory
To read a program memory location, the user must
write two bytes of the address to the PMADRL and
PMADRH registers, and then set control bit RD
(PMCON1<0>). Once the read control bit is set, the
program memory Flash controller will use the second
instruction cycle after to read the data. This causes the
second instruction immediately following the “BSF
PMCON1,RD” instruction to be ignored. The data is
available in the very next cycle in the PMDATL and
PMDATH registers; it can be read as two bytes in the
following instructions. PMDATL and PMDATH regis-
ters will hold this value until another read or until it is
written to by the user (during a write operation).
EXAMPLE 3-1:
FLASH PROGRAM READ
BANKSELPM_ADR
; Change STATUS bits RP1:0 to select bank with PMADRL
MOVLW
MOVWF
MOVLW
MOVWF
MS_PROG_PM_ADDR
PMADRH
LS_PROG_PM_ADDR
PMADRL
;
; MS Byte of Program Address to read
;
; LS Byte of Program Address to read
; Bank to containing PMCON1
; PM Read
BANKSELPMCON1
BSF
NOP
NOP
PMCON1, RD
; First instruction after BSF PMCON1,RD executes normally
; Any instructions here are ignored as program
; memory is read in second cycle after BSF PMCON1,RD
;
BANKSELPMDATL
; Bank to containing PMADRL
MOVF
MOVF
PMDATL, W
PMDATH, W
; W = LS Byte of Program PMDATL
; W = MS Byte of Program PMDATL
DS41302D-page 30
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
FIGURE 3-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Flash ADDR
Flash DATA
PC
PC + 1
PMADRH,PMADRL
PC+3
PC + 4
PC + 5
INSTR (PC)
INSTR (PC + 1)
PMDATH,PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
BSF PMCON1,RD
Executed here
INSTR (PC - 1)
Executed here
INSTR (PC + 1)
Executed here
NOP
Executed here
INSTR (PC + 3)
Executed here
INSTR (PC + 4)
Executed here
RD bit
PMDATH
PMDATL
Register
PMRHLT
2010 Microchip Technology Inc.
DS41302D-page 31
PIC12F609/615/617/12HV609/615
which the erase takes place (i.e., the last word of the
sixteen-word block erase). This is not Sleep mode as
the clocks and peripherals will continue to run. After
the four-word write cycle, the processor will resume
operation with the third instruction after the PMCON1
write instruction. The above sequence must be
repeated for the higher 12 words.
3.4
Writing the Flash Program
Memory
A word of the Flash program memory may only be
written to if the word is in an unprotected segment of
memory.
Flash program memory must be written in four-word
blocks. See Figure 3-2 and Figure 3-3 for more details.
3.5
Protection Against Spurious Write
A
block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where PMADRL<1:0> = 00. All block writes to
program memory are done as 16-word erase by four-
word write operations. The write operation is edge-
aligned and cannot occur across boundaries.
There are conditions when the device should not write
to the program memory. To protect against spurious
writes, various mechanisms have been built in. On
power-up, WREN is cleared. Also, the Power-up Timer
(64 ms duration) prevents program memory writes.
To write program data, it must first be loaded into the
buffer registers (see Figure 3-2). This is accomplished
by first writing the destination address to PMADRL and
PMADRH and then writing the data to PMDATL and
PMDATH. After the address and data have been set
up, then the following sequence of events must be
executed:
The write initiate sequence and the WREN bit help
prevent an accidental write during brown-out, power
glitch or software malfunction.
3.6
Operation During Code-Protect
When the device is code-protected, the CPU is able to
read and write unscrambled data to the program
memory. The test mode access is disabled.
1. Write 55h, then AAh, to PMCON2 (Flash
programming sequence).
2. Set the WR control bit of the PMCON1 register.
3.7
Operation During Write Protect
All four buffer register locations should be written to
with correct data. If less than four words are being
written to in the block of four words, then a read from
the program memory location(s) not being written to
must be performed. This takes the data from the
program location(s) not being written and loads it into
the PMDATL and PMDATH registers. Then the
sequence of events to transfer data to the buffer
registers must be executed.
When the program memory is write-protected, the
CPU can read and execute from the program memory.
The portions of program memory that are write pro-
tected can be modified by the CPU using the PMCON
registers, but the protected program memory cannot
be modified using ICSP mode.
To transfer data from the buffer registers to the program
memory, the PMADRL and PMADRH must point to the
last location in the four-word block (PMADRL<1:0> =
11). Then the following sequence of events must be
executed:
1. Write 55h, then AAh, to PMCON2 (Flash pro-
gramming sequence).
2. Set control bit WR of the PMCON1 register to
begin the write operation.
The user must follow the same specific sequence to
initiate the write for each word in the program block,
writing each program word in sequence (000, 001,
010, 011). When the write is performed on the last
word (PMADRL<1:0> = 11), a block of sixteen words is
automatically erased and the content of the four-word
buffer registers are written into the program memory.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase/write operation.
The user must place two NOPinstructions after the WR
bit is set. Since data is being written to buffer registers,
the writing of the first three words of the block appears
to occur immediately. The processor will halt internal
operations for the typical 4 ms, only during the cycle in
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FIGURE 3-2:
BLOCK WRITES TO 2K FLASH PROGRAM MEMORY
7
5
0
0 7
If at a new row
sixteen words of
Flash are erased,
then four buffers
are transferred
to Flash
PMDATH
6
PMDATL
8
automatically
after this word
is written
First word of block
to be written
14
14
14
14
PMADRL<1:0> = 00
Buffer Register
PMADRL<1:0> = 01
Buffer Register
PMADRL<1:0> = 10
Buffer Register
PMADRL<1:0> = 11
Buffer Register
Program Memory
FIGURE 3-3:
FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PMADRH,PMADRL
PMDATH,PMDATL
PC + 1
PC + 2
PC + 3
PC + 4
Flash
ADDR
INSTR
(PC + 1)
ignored
read
INSTR
(PC)
Flash
DATA
INSTR (PC+3)
INSTR (PC+2)
(INSTR (PC + 2)
NOP
Executed here
Processor halted
PM Write Time
BSF PMCON1,WR
Executed here
INSTR (PC + 1)
Executed here
INSTR (PC + 3)
Executed here
NOP
Executed here
Flash
Memory
Location
WR bit
PMWHLT
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An example of the complete four-word write sequence
is shown in Example 3-2. The initial address is loaded
into the PMADRH and PMADRL register pair; the eight
words of data are loaded using indirect addressing.
EXAMPLE 3-2:
WRITING TO FLASH PROGRAM MEMORY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
;
;
;
A valid starting address (the least significant bits = '00')
is loaded in ADDRH:ADDRL
ADDRH, ADDRL and DATADDR are all located in data memory
BANKSEL PMADRH
MOVF
MOVWF
MOVF
MOVWF
MOVF
ADDRH,W
PMADRH
ADDRL,W
PMADRL
; Load initial address
;
;
;
DATAADDR,W ; Load initial data address
MOVWF
MOVF
MOVWF
INCF
MOVF
MOVWF
INCF
FSR
;
LOOP
INDF,W
PMDATL
FSR,F
INDF,W
PMDATH
FSR,F
; Load first data byte into lower
;
; Next byte
; Load second data byte into upper
;
;
BANKSEL PMCON1
BSF
PMCON1,WREN ; Enable writes
BCF
INTCON,GIE ; Disable interrupts (if using)
BTFSC
GOTO
INTCON,GIE ; See AN576
$-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
; Start of required write sequence:
; Write 55h
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
; Write 0AAh
; Set WR bit to begin write
; Required to transfer data to the buffer
; registers
NOP
NOP
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
BSF
PMCON1,WREN ; Disable writes
INTCON,GIE ; Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF
PMADRL, W
INCF
ANDLW
SUBLW
PMADRL,F
0x03
0x03
; Increment address
; Indicates when sixteen words have been programmed
;
;
;
;
0x0F = 16 words
0x0B = 12 words
0x07 = 8 words
0x03 = 4 words
BTFSS
GOTO
STATUS,Z
LOOP
; Exit on a match,
; Continue if more data needs to be written
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TABLE 3-1:
SUMMARY OF REGISTERS ASSOCIATED WITH PROGRAM MEMORY
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
PMCON1
—
—
—
—
WREN
WR
RD
---- -000
---- -000
—
PMCON2 Program Memory Control Register 2 (not a physical register)
---- ----
0000 0000
---- ----
0000 0000
---- -000
0000 0000
--00 0000
PMADRL
PMADRH
PMDATL
PMDATH
Legend:
PMADRL7 PMADRL6 PMADRL5 PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0
—
—
—
—
—
PMADRH2 PMADRH1 PMADRH0 ---- -000
PMDATL7 PMDATL6 PMDATL5
PMDATL4
PMDATL3 PMDATL2 PMDATL1 PMDATL0
0000 0000
--00 0000
—
—
PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0
x= unknown, u= unchanged, —= unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by Program Memory module.
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NOTES:
DS41302D-page 36
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The Oscillator module can be configured in one of eight
clock modes.
4.0
4.1
OSCILLATOR MODULE
3. EC – External clock with I/O on OSC2/CLKOUT.
4. LP – 32 kHz Low-Power Crystal mode.
Overview
The Oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 4-1
illustrates a block diagram of the Oscillator module.
5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode.
6. HS – High Gain Crystal or Ceramic Resonator
mode.
7. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
Clock sources can be configured from external
oscillators, quartz crystal resonators, ceramic resonators
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured with a choice of
two selectable speeds: internal or external system clock
source.
8. RCIO – External Resistor-Capacitor (RC) with
I/O on OSC2/CLKOUT.
9. INTOSC – Internal oscillator with FOSC/4 output
on OSC2 and I/O on OSC1/CLKIN.
10. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
Clock Source modes are configured by the FOSC<2:0>
bits in the Configuration Word register (CONFIG). The
Internal Oscillator module provides
a selectable
system clock mode of either 4 MHz (Postscaler) or
8 MHz (INTOSC).
FIGURE 4-1:
PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0>
IOSCFS<7>
(Configuration Word Register)
External Oscillator
OSC2
OSC1
Sleep
LP, XT, HS, RC, RCIO, EC
INTOSC
System Clock
(CPU and Peripherals)
Internal Oscillator
INTOSC
8 MHz
Postscaler
4 MHz
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4.2
Clock Source Modes
4.3
External Clock Modes
Clock Source modes can be classified as external or
internal.
4.3.1 OSCILLATOR START-UP TIMER
(OST)
• External Clock modes rely on external circuitry for
the clock source. Examples are: Oscillator mod-
ules (EC mode), quartz crystal resonators or
ceramic resonators (LP, XT and HS modes) and
Resistor-Capacitor (RC) mode circuits.
If the Oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the Oscillator
module. When switching between clock sources, a
delay is required to allow the new clock to stabilize.
These oscillator delays are shown in Table 4-1.
• Internal clock sources are contained internally
within the Oscillator module. The Oscillator
module has two selectable clock frequencies:
4 MHz and 8 MHz
The system clock can be selected between external or
internal clock sources via the FOSC<2:0> bits of the
Configuration Word register.
TABLE 4-1:
Switch From
OSCILLATOR DELAY EXAMPLES
Switch To
Frequency
125 kHz to 8 MHz
Oscillator Delay
Sleep/POR
Sleep/POR
Sleep/POR
INTOSC
EC, RC
Oscillator Warm-Up Delay (TWARM)
2 instruction cycles
DC – 20 MHz
LP, XT, HS
32 kHz to 20 MHz
1024 Clock Cycles (OST)
4.3.2
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the OSC1 input and the OSC2 is available
for general purpose I/O. Figure 4-2 shows the pin
connections for EC mode.
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
FIGURE 4-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
Clock from
Ext. System
PIC® MCU
(1)
I/O
OSC2/CLKOUT
Note 1: Alternate pin functions are listed in the
Section 1.0 “Device Overview”.
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4.3.3
LP, XT, HS MODES
Note 1: Quartz crystal characteristics vary according
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 4-3). The mode selects a low,
medium or high gain setting of the internal inverter-
amplifier to support various resonator types and speed.
to type, package and manufacturer. The
user should consult the manufacturer data
sheets for specifications and recommended
application.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
LP Oscillator mode selects the lowest gain setting of
the internal inverter-amplifier. LP mode current
consumption is the least of the three modes. This mode
is designed to drive only 32.768 kHz tuning-fork type
crystals (watch crystals).
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
HS Oscillator mode selects the highest gain setting of
the internal inverter-amplifier. HS mode current
consumption is the highest of the three modes. This
mode is best suited for resonators that require a high
drive setting.
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
FIGURE 4-4:
CERAMIC RESONATOR
OPERATION
Figure 4-3 and Figure 4-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
(XT OR HS MODE)
FIGURE 4-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC® MCU
OSC1/CLKIN
C1
PIC® MCU
To Internal
Logic
OSC1/CLKIN
(3)
(2)
RP
RF
Sleep
C1
To Internal
Logic
Quartz
Crystal
(2)
OSC2/CLKOUT
(1)
C2
RF
Sleep
RS
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
OSC2/CLKOUT
(1)
C2
RS
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
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4.3.4
EXTERNAL RC MODES
4.4
Internal Clock Modes
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO.
The Oscillator module provides a selectable system
clock source of either 4 MHz or 8 MHz. The selectable
frequency is configured through the IOSCFS bit of the
Configuration Word.
The frequency of the internal oscillator can be trimmed
with a calibration value in the OSCTUNE register.
In RC mode, the RC circuit connects to OSC1. OSC2/
CLKOUT outputs the RC oscillator frequency divided
by 4. This signal may be used to provide a clock for
external circuitry, synchronization, calibration, test or
other application requirements. Figure 4-5 shows the
external RC mode connections.
4.4.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
or the FOSC<2:0> bits in the Configuration Word
register (CONFIG). See Section 12.0 “Special
Features of the CPU” for more information.
FIGURE 4-5:
EXTERNAL RC MODES
VDD
PIC® MCU
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
signal may be used to provide a clock for external
circuitry, synchronization, calibration, test or other
application requirements.
REXT
OSC1/CLKIN
Internal
Clock
CEXT
VSS
In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
are available for general purpose I/O.
(1)
FOSC/4 or
I/O
OSC2/CLKOUT
(2)
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
2: Output depends upon RC or RCIO Clock
mode.
In RCIO mode, the RC circuit is connected to OSC1.
OSC2 becomes an additional general purpose I/O pin.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
The user also needs to take into account variation due
to tolerance of external RC components used.
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The default value of the OSCTUNE register is ‘0’. The
value is a 5-bit two’s complement number.
4.4.1.1
OSCTUNE Register
The oscillator is factory calibrated but can be adjusted
in software by writing to the OSCTUNE register
(Register 4-1).
When the OSCTUNE register is modified, the frequency
will begin shifting to the new frequency. Code execution
continues during this shift. There is no indication that the
shift has occurred.
REGISTER 4-1:
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
TUN<4:0>: Frequency Tuning bits
01111= Maximum frequency
01110=
•
•
•
00001=
00000= Oscillator module is running at the calibrated frequency.
11111=
•
•
•
10000= Minimum frequency
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(2)
CONFIG
IOSCFS
—
CP
—
MCLRE PWRTE
TUN4
WDTE
TUN3
FOSC2
TUN2
FOSC1
TUN1
FOSC0
TUN0
—
—
OSCTUNE
—
---0 0000 ---u uuuu
Legend:
x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (Register 12-1) for operation of all register bits.
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NOTES:
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Reading the GPIO register (Register 5-1) reads the
status of the pins, whereas writing to it will write to the
5.0
I/O PORT
There are as many as six general purpose I/O pins
available. Depending on which peripherals are enabled,
some or all of the pins may not be available as general
purpose I/O. In general, when a peripheral is enabled,
the associated pin may not be used as a general
purpose I/O pin.
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch. GP3 reads ‘0’ when
MCLRE = 1.
The TRISIO register controls the direction of the
GPIO pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
register are maintained set when using them as analog
inputs. I/O pins configured as analog input always read
‘0’.
5.1
GPIO and the TRISIO Registers
GPIO is a 6-bit wide port with 5 bidirectional and 1 input-
only pin. The corresponding data direction register is
TRISIO (Register 5-2). Setting a TRISIO bit (= 1) will
make the corresponding GPIO pin an input (i.e., disable
the output driver). Clearing a TRISIO bit (= 0) will make
the corresponding GPIO pin an output (i.e., enables
output driver and puts the contents of the output latch on
the selected pin). The exception is GP3, which is input
only and its TRIS bit will always read as ‘1’. Example 5-
1 shows how to initialize GPIO.
Note:
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
EXAMPLE 5-1:
INITIALIZING GPIO
BANKSEL GPIO
;
CLRF
GPIO
;Init GPIO
BANKSEL ANSEL
;
Note:
GPIO = PORTA
TRISIO = TRISA
CLRF
ANSEL
;digital I/O, ADC clock
;setting ‘don’t care’
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
MOVLW
MOVWF
0Ch
TRISIO
REGISTER 5-1:
GPIO: GPIO REGISTER
U-0
—
U-0
R/W-x
GP5
R/W-x
GP4
R-x
R/W-x
GP2
R/W-x
GP1
R/W-x
GP0
—
GP3
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
GP<5:0>: GPIO I/O Pin bit
1= GPIO pin is > VIH
0= GPIO pin is < VIL
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REGISTER 5-2:
TRISIO: GPIO TRI-STATE REGISTER
U-0
—
U-0
—
R/W-1
R/W-1
R-1
R/W-1
R/W-1
R/W-1
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
TRISIO<5:0>: GPIO Tri-State Control bit
1= GPIO pin configured as an input (tri-stated)
0= GPIO pin configured as an output
Note 1: TRISIO<3> always reads ‘1’.
2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR’d
together to set the GPIO Change Interrupt Flag bit
(GPIF) in the INTCON register (Register 2-3).
5.2
Additional Pin Functions
Every GPIO pin on the PIC12F609/615/617/12HV609/
615 has an interrupt-on-change option and a weak pull-
up option. The next three sections describe these
functions.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
5.2.1
ANSEL REGISTER
The ANSEL register is used to configure the Input
mode of an I/O pin to analog. Setting the appropriate
ANSEL bit high will cause all digital reads on the pin to
be read as ‘0’ and allow analog functions on the pin to
operate correctly.
a) Any read of GPIO AND Clear flag bit GPIF. This
will end the mismatch condition;
OR
b) Any write of GPIO AND Clear flag bit GPIF will
end the mismatch condition;
The state of the ANSEL bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these resets, the GPIF flag will continue to
be set if a mismatch is present.
5.2.2
WEAK PULL-UPS
Note:
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
Each of the GPIO pins, except GP3, has an individually
configurable internal weak pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 5-5.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit of the
OPTION register). A weak pull-up is automatically
enabled for GP3 when configured as MCLR and
disabled when GP3 is an I/O. There is no software
control of the MCLR pull-up.
5.2.3
INTERRUPT-ON-CHANGE
Each GPIO pin is individually configurable as an
interrupt-on-change pin. Control bits IOCx enable or
disable the interrupt function for each pin. Refer to
Register 5-6. The interrupt-on-change is disabled on a
Power-on Reset.
DS41302D-page 44
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 5-3:
ANSEL: ANALOG SELECT REGISTER (PIC12F609/HV609)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
ANS3
U-0
—
R/W-1
ANS1
R/W-1
ANS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3
Unimplemented: Read as ‘0’
ANS3: Analog Select Between Analog or Digital Function on Pin GP4
(1)
1= Analog input. Pin is assigned as analog input
.
0= Digital I/O. Pin is assigned to port or special function.
bit 2
bit 1
Unimplemented: Read as ‘0’
ANS1: Analog Select Between Analog or Digital Function on Pin GP1
(1)
1= Analog input. Pin is assigned as analog input.
0= Digital I/O. Pin is assigned to port or special function.
bit 0
ANS0: Analog Select Between Analog or Digital Function on Pin GP0
0= Digital I/O. Pin is assigned to port or special function.
1= Analog input. Pin is assigned as analog input.
(1)
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-
change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
REGISTER 5-4:
ANSEL: ANALOG SELECT REGISTER (PIC12F615/617/HV615)
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
ANS3
R/W-1
ANS2
R/W-1
ANS1
R/W-1
ANS0
ADCS2
ADCS1
ADCS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100= FOSC/4
101= FOSC/16
110= FOSC/64
bit 3-0
ANS<3:0>: Analog Select Between Analog or Digital Function on Pins GP4, GP2, GP1, GP0, respectively.
(1)
1= Analog input. Pin is assigned as analog input
.
0= Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-
change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of
the voltage on the pin.
2010 Microchip Technology Inc.
DS41302D-page 45
PIC12F609/615/617/12HV609/615
REGISTER 5-5:
WPU: WEAK PULL-UP GPIO REGISTER
U-0
—
U-0
—
R/W-1
WPU5
R/W-1
WPU4
U-0
—
R/W-1
WPU2
R/W-1
WPU1
R/W-1
WPU0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
WPU<5:4>: Weak Pull-up Control bits
1= Pull-up enabled
0= Pull-up disabled
bit 3
WPU<3>: Weak Pull-up Register bit(3)
bit 2-0
WPU<2:0>: Weak Pull-up Control bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
3: The GP3 pull-up is enabled when configured as MCLR in the Configuration Word, otherwise it is disabled
as an input and reads as ‘0’.
4: WPU<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
REGISTER 5-6:
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER
U-0
—
U-0
—
R/W-0
IOC5
R/W-0
IOC4
R/W-0
IOC3
R/W-0
IOC2
R/W-0
IOC1
R/W-0
IOC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-change GPIO Control bit
1= Interrupt-on-change enabled
0= Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOC<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
DS41302D-page 46
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4
PIN DESCRIPTIONS AND
DIAGRAMS
5.2.4.2
GP1/AN1(1)/CIN0-/VREF(1)/ICSPCLK
Figure 5-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the Comparator or the ADC, refer to the
appropriate section in this data sheet.
• a general purpose I/O
(1)
• an analog input for the ADC
• an analog inverting input to the comparator
(1)
• a voltage reference input for the ADC
5.2.4.1
GP0/AN0(1)/CIN+/P1B(1)/ICSPDAT
• In-Circuit Serial Programming clock
Figure 5-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
Note 1: PIC12F615/617/HV615 only.
• a general purpose I/O
(1)
• an analog input for the ADC
• an analog non-inverting input to the comparator
(1)
• a PWM output
• In-Circuit Serial Programming data
FIGURE 5-1:
BLOCK DIAGRAM OF GP<1:0>
Analog(1)
Input Mode
VDD
Data Bus
D
Q
Q
Weak
CK
WR
WPU
GPPU
VDD
RD
WPU
D
Q
Q
I/O Pin
WR
CK
GPIO
VSS
D
Q
Q
WR
TRISIO
CK
RD
TRISIO
Analog(1)
Input Mode
RD
GPIO
D
Q
Q
Q
Q
D
CK
WR
IOC
Q1
EN
RD
IOC
D
S(2)
R
EN
Q
Interrupt-on-
Change
From other
GP<5:0> pins (GP0)
GP<5:2, 0> pins (GP1)
RD GPIO
To Comparator
To A/D Converter(3)
Write ‘0’ to GBIF
Note 1: Comparator mode and ANSEL determines Analog Input mode.
2: Set has priority over Reset.
3: PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 47
PIC12F609/615/617/12HV609/615
5.2.4.3
GP2/AN2(1)/T0CKI/INT/COUT/
CCP1(1)/P1A(1)
Note 1: PIC12F615/617/HV615 only.
Figure 5-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
• a general purpose I/O
(1)
• an analog input for the ADC
• the clock input for TMR0
• an external edge triggered interrupt
• a digital output from Comparator
(1)
• a Capture input/Compare input/PWM output
(1)
• a PWM output
FIGURE 5-2:
BLOCK DIAGRAM OF GP2
Analog(1)
Input Mode
VDD
Data Bus
D
Q
Q
Weak
CK
WR
WPU
C1OE
Enable
GPPU
VDD
RD
WPU
C1OE
1
0
D
Q
Q
I/O Pin
WR
CK
VSS
GPIO
D
Q
Q
WR
TRISIO
CK
RD
TRISIO
Analog(1)
Input Mode
RD
GPIO
D
Q
Q
Q
D
D
CK
WR
IOC
Q1
EN
RD
IOC
Q
S(2)
R
EN
Q
Interrupt-on-
Change
From other
GP<5:3, 1:0> pins
RD GPIO
To Timer0
To INT
Write ‘0’ to GBIF
To A/D Converter(3)
Note 1: Comparator mode and ANSEL determines Analog Input mode.
2: Set has priority over Reset.
3: PIC12F615/617/HV615 only.
DS41302D-page 48
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4.4
GP3/T1G(1, 2)/MCLR/VPP
Figure 5-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose input
(1, 2)
• a Timer1 gate (count enable), alternate pin
• as Master Clear Reset with weak pull-up
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
FIGURE 5-3:
BLOCK DIAGRAM OF GP3
VDD
MCLRE
Weak
Data Bus
MCLRE
Reset
Input
Pin
RD
TRISIO
VSS
MCLRE
VSS
RD
GPIO
D
Q
Q
Q
Q
D
CK
WR
IOC
Q1
EN
RD
IOC
D
(1)
Q
S
EN
Interrupt-on-
Change
From other
GP<5:4, 2:0> pins
R
RD GPIO
Write ‘0’ to GBIF
Note 1: Set has priority over Reset
2010 Microchip Technology Inc.
DS41302D-page 49
PIC12F609/615/617/12HV609/615
(1, 2)
GP4/AN3(2)/CIN1-/T1G/
P1B(1, 2)/OSC2/CLKOUT
• PWM output, alternate pin
5.2.4.5
• a crystal/resonator connection
• a clock output
Figure 5-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
• a general purpose I/O
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
(2)
• an analog input for the ADC
• Comparator inverting input
• a Timer1 gate (count enable)
FIGURE 5-4:
BLOCK DIAGRAM OF GP4
(3)
Analog
Input Mode
(1)
CLK
Modes
Data Bus
D
Q
Q
VDD
WR
WPU
CK
Weak
GPPU
RD
WPU
Oscillator
Circuit
OSC1
VDD
CLKOUT
Enable
FOSC/4
1
0
D
Q
Q
I/O Pin
WR
CK
GPIO
CLKOUT
Enable
VSS
D
Q
Q
INTOSC/
(2)
RC/EC
WR
TRISIO
CK
CLKOUT
Enable
RD
TRISIO
Analog
Input Mode
RD
GPIO
D
Q
Q
Q
D
D
CK
WR
IOC
Q1
EN
RD
IOC
Q
(4)
EN
Q
S
Interrupt-on-
Change
From other
GP<5, 3:0> pins
R
RD GPIO
To T1G
To A/D Converter
Write ‘0’ to GBIF
(5)
Note 1: CLK modes are XT, HS, LP, TMR1 LP and CLKOUT Enable.
2: With CLKOUT option.
3: Analog Input mode comes from ANSEL.
4: Set has priority over Reset.
5: PIC12F615/617/HV615 only.
DS41302D-page 50
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
5.2.4.6
GP5/T1CKI/P1A(1, 2)/OSC1/CLKIN
Note 1: Alternate pin function.
2: PIC12F615/617/HV615 only.
Figure 5-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
(1, 2)
• PWM output, alternate pin
• a crystal/resonator connection
• a clock input
FIGURE 5-5:
BLOCK DIAGRAM OF GP5
INTOSC
Mode
(1)
TMR1LPEN
Data Bus
D
VDD
Q
Q
WR
CK
Weak
WPU
GPPU
RD
WPU
Oscillator
Circuit
OSC2
VDD
D
Q
Q
WR
GPIO
CK
I/O Pin
D
Q
Q
WR
TRISIO
CK
VSS
INTOSC
Mode
RD
TRISIO
RD
GPIO
D
Q
Q
Q
D
D
CK
WR
IOC
Q1
EN
RD
IOC
Q
(2)
EN
Q
S
Interrupt-on-
Change
From other
GP<4:0> pins
R
RD GPIO
Write ‘0’ to GBIF
To Timer1
Note 1: Timer1 LP Oscillator enabled.
2: Set has priority over Reset.
2010 Microchip Technology Inc.
DS41302D-page 51
PIC12F609/615/617/12HV609/615
TABLE 5-1:
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSEL
CMCON0
INTCON
IOC
—
CMON
GIE
ADCS2(1) ADCS1(1) ADCS0(1)
ANS3
—
ANS2(1)
CMR
ANS1
—
ANS0
CMCH
GPIF
-000 1111
0000 -0-0
0000 0000
--00 0000
-000 1111
0000 -0-0
0000 0000
--00 0000
COUT
PEIE
—
CMOE
T0IE
CMPOL
INTE
GPIE
IOC3
T0IF
INTF
IOC1
—
IOC5
IOC4
IOC2
IOC0
OPTION_REG
GPIO
GPPU
—
INTEDG
T0CS
GP5
T0SE
GP4
PSA
GP3
PS2
GP2
PS1
GP1
PS0
GP0
1111 1111
--xx xxxx
--11 1111
--11 1111
0000 0000
0-00 0000
---0 --00
1111 1111
--u0 u000
--11 1111
--11 -111
uuuu uuuu
0-00 0000
---0 --00
—
—
—
TRISIO
—
TRISIO5
WPU5
TRISIO4
WPU4
TRISIO3
WPU3
TRISIO2
WPU2
TRISIO1
WPU1
TRISIO0
WPU0
WPU
—
T1CON
T1GINV TMR1GE TICKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
CCP1CON(1)
APFCON(1)
P1M
—
—
—
DC1B1
—
DC1B0
CCP1M3
—
CCP1M2 CCP1M1 CCP1M0
P1BSEL P1ASEL
T1GSEL
—
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.
Note 1:
PIC12F615/617/HV615 only.
DS41302D-page 52
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
6.1
Timer0 Operation
6.0
TIMER0 MODULE
When used as a timer, the Timer0 module can be used
as either an 8-bit timer or an 8-bit counter.
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
6.1.1
8-BIT TIMER MODE
• 8-bit prescaler (shared with Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
When used as a timer, the Timer0 module will
increment every instruction cycle (without prescaler).
Timer mode is selected by clearing the T0CS bit of the
OPTION register to ‘0’.
Figure 6-1 is a block diagram of the Timer0 module.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.
6.1.2
8-BIT COUNTER MODE
When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the OPTION register. Counter mode is selected by
setting the T0CS bit of the OPTION register to ‘1’.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FOSC/4
Data Bus
0
1
8
1
Sync
TMR0
2 TCY
T0CKI
pin
0
0
1
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
8
PSA
1
PS<2:0>
WDT
Time-out
Watchdog
Timer
0
WDTE
PSA
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
2: WDTE bit is in the Configuration Word register.
2010 Microchip Technology Inc.
DS41302D-page 53
PIC12F609/615/617/12HV609/615
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 6-2).
6.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT TIMER0)
CLRWDT
;Clear WDT and
;prescaler
;
BANKSEL OPTION_REG
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
MOVLW
ANDWF
IORLW
MOVWF
b’11110000’ ;Mask TMR0 select and
OPTION_REG,W ;prescaler bits
b’00000011’ ;Set prescale to 1:16
OPTION_REG
;
6.1.4
TIMER0 INTERRUPT
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
6.1.3.1
Switching Prescaler Between
Timer0 and WDT Modules
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 6-1, must be executed.
6.1.5
USING TIMER0 WITH AN
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks.
Therefore, the high and low periods of the external
clock source must meet the timing requirements as
shown in Section 16.0 “Electrical Specifications”.
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0 WDT)
BANKSEL TMR0
CLRWDT
;
;Clear WDT
;Clear TMR0 and
;prescaler
CLRF
TMR0
BANKSEL OPTION_REG
;
BSF
OPTION_REG,PSA ;Select WDT
CLRWDT
;
;
MOVLW
ANDWF
IORLW
MOVWF
b’11111000’
OPTION_REG,W
b’00000101’
OPTION_REG
;Mask prescaler
;bits
;Set WDT prescaler
;to 1:32
DS41302D-page 54
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 6-1:
OPTION_REG: OPTION REGISTER
R/W-1
GPPU
bit 7
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPPU: GPIO Pull-up Enable bit
1= GPIO pull-ups are disabled
0= GPIO pull-ups are enabled by individual PORT latch values in WPU register
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
0000 000x 0000 000x
1111 1111 1111 1111
INTCON
OPTION_REG
TRISIO
GIE
PEIE
T0IE
INTE
T0SE
GPIE
PSA
T0IF
PS2
INTF
PS1
GPIF
PS0
GPPU INTEDG
T0CS
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend:
– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0
module.
2010 Microchip Technology Inc.
DS41302D-page 55
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 56
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
7.2
Clock Source Selection
7.0
TIMER1 MODULE WITH GATE
CONTROL
The TMR1CS bit of the T1CON register is used to select
the clock source. When TMR1CS = 0, the clock source
is FOSC/4. When TMR1CS = 1, the clock source is
supplied externally.
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
Clock Source
TMR1CS
T1ACS
• Optional LP oscillator
FOSC/4
FOSC
0
0
1
0
1
x
• Synchronous or asynchronous operation
• Timer1 gate (count enable) via comparator or
T1G pin
T1CKI pin
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with ECCP)
• Comparator output synchronization to Timer1
clock
Figure 7-1 is a block diagram of the Timer1 module.
7.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
When used with an internal clock source, the module is
a timer. When used with an external clock source, the
module can be used as either a timer or counter.
2010 Microchip Technology Inc.
DS41302D-page 57
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FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
TMR1GE
T1GINV
TMR1ON
Set flag bit
TMR1IF on
Overflow
To Comparator Module
Timer1 Clock
(2)
TMR1
TMR1H
Synchronized
clock input
0
EN
TMR1L
1
Oscillator
(1)
T1SYNC
OSC1/T1CKI
1
(3)
Synchronize
det
Prescaler
1, 2, 4, 8
0
OSC2/T1G
2
T1CKPS<1:0>
TMR1CS
0
1
INTOSC
Without CLKOUT
1
0
FOSC
1
0
T1OSCEN
FOSC/4
Internal
Clock
COUT
(2)
T1GSEL
T1GSS
T1ACS
(4, 5)
GP3/T1G
Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
4: Alternate pin function.
5: PIC12F615/617/HV615 only.
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7.2.1
INTERNAL CLOCK SOURCE
7.5
Timer1 Operation in
Asynchronous Counter Mode
When the internal clock source is selected, the
TMR1H:TMR1L register pair will increment on multiples
of TCY as determined by the Timer1 prescaler.
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
continues to increment asynchronous to the internal
phase clocks. The timer will continue to run during
Sleep and can generate an interrupt on overflow,
which will wake-up the processor. However, special
precautions in software are needed to read/write the
timer (see Section 7.5.1 “Reading and Writing
Timer1 in Asynchronous Counter Mode”).
7.2.2
EXTERNAL CLOCK SOURCE
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
When counting, Timer1 is incremented on the rising
edge of the external clock input T1CKI. In addition, the
Counter mode clock can be synchronized to the
microcontroller system clock or run asynchronously.
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce a single spurious
increment.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC without CLKOUT),
Timer1 can use the LP oscillator as a clock source.
In Counter mode, a falling edge must be registered by
the counter prior to the first incrementing rising edge
after one or more of the following conditions:
Note:
In asynchronous counter mode or when
using the internal oscillator and T1ACS=1,
Timer1 can not be used as a time base for
the capture or compare modes of the
ECCP module (for PIC12F615/617/
HV615 only).
• Timer1 is enabled after POR or BOR Reset
• A write to TMR1H or TMR1L
• T1CKI is high when Timer1 is disabled and when
Timer1 is re-enabled T1CKI is low. See Figure 7-2.
7.3
Timer1 Prescaler
7.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself poses certain problems, since the
timer may overflow between the reads.
7.4
Timer1 Oscillator
A low-power 32.768 kHz crystal oscillator is built-in
between pins OSC1 (input) and OSC2 (output). The
oscillator is enabled by setting the T1OSCEN control
bit of the T1CON register. The oscillator will continue to
run during Sleep.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TTMR1L register
pair.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the primary system clock is derived from the internal
oscillator or when in LP oscillator mode. The user must
provide a software time delay to ensure proper
oscillator start-up.
TRISIO5 and TRISIO4 bits are set when the Timer1
oscillator is enabled. GP5 and GP4 bits read as ‘0’ and
TRISIO5 and TRISIO4 bits read as ‘1’.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
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7.6
Timer1 Gate
7.9
ECCP Capture/Compare Time
Base (PIC12F615/617/HV615 only)
Timer1 gate source is software configurable to be the
T1G pin (or the alternate T1G pin) or the output of the
Comparator. This allows the device to directly time
external events using T1G or analog events using the
Comparator. See the CMCON1 Register (Register 9-2)
for selecting the Timer1 gate source. This feature can
simplify the software for a Delta-Sigma A/D converter
and many other applications. For more information on
Delta-Sigma A/D converters, see the Microchip web site
(www.microchip.com).
The ECCP module uses the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
Note:
TMR1GE bit of the T1CON register must
be set to use either T1G or COUT as the
Timer1 gate source. See Register 9-2 for
more information on selecting the Timer1
gate source.
For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM (With Auto-Shutdown and
Dead Band) Module (PIC12F615/617/HV615 only)”.
Timer1 gate can be inverted using the T1GINV bit of
the T1CON register, whether it originates from the T1G
pin or the Comparator output. This configures Timer1
to measure either the active-high or active-low time
between events.
7.7
Timer1 Interrupt
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
• Timer1 interrupt enable bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
Note:
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
7.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
The device will wake-up on an overflow and execute
the next instruction. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine (0004h).
DS41302D-page 60
2010 Microchip Technology Inc.
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For more information, see Section 11.0 “Enhanced
Capture/Compare/PWM (With Auto-Shutdown and
Dead Band) Module (PIC12F615/617/HV615 only)”.
7.10 ECCP Special Event Trigger
(PIC12F615/617/HV615 only)
If a ECCP is configured to trigger a special event, the
trigger will clear the TMR1H:TMR1L register pair. This
special event does not cause a Timer1 interrupt. The
ECCP module may still be configured to generate a
ECCP interrupt.
7.11 Comparator Synchronization
The same clock used to increment Timer1 can also be
used to synchronize the comparator output. This
feature is enabled in the Comparator module.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
When using the comparator for Timer1 gate, the
comparator output should be synchronized to Timer1.
This ensures Timer1 does not miss an increment if the
comparator changes.
Timer1 should be synchronized to the FOSC to utilize
the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be
missed.
For more information, see Section 9.0 “Comparator
Module”.
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the ECCP, the write
will take precedence.
FIGURE 7-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
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7.12 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 7-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 7-1:
T1CON: TIMER 1 CONTROL REGISTER
R/W-0
T1GINV(1)
R/W-0
TMR1GE(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
T1GINV: Timer1 Gate Invert bit(1)
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
TMR1GE: Timer1 Gate Enable bit(2)
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 is on if Timer1 gate is active
0= Timer1 is on
bit 5-4
bit 3
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale Value
10= 1:4 Prescale Value
01= 1:2 Prescale Value
00= 1:1 Prescale Value
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1= LP oscillator is enabled for Timer1 clock
0= LP oscillator is off
For all other system clock modes:
This bit is ignored. LP oscillator is disabled.
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from T1CKI pin (on the rising edge)
0= Internal clock (FOSC/4) or system clock (FOSC)(3)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.
2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1
register, as a Timer1 gate source.
3: See T1ACS bit in CMCON1 register.
DS41302D-page 62
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TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
APFCON(1)
—
—
—
CMOE
—
T1GSEL
CMPOL
T1ACS
INTE
—
—
—
—
CMR
—
P1BSEL
—
P1ASEL
CMCH
---0 --00
0000 -0-0
---0 0-10
0000 000x
-00- 0-00
-00- 0-00
xxxx xxxx
xxxx xxxx
---0 --00
0000 -0-0
---0 0-10
0000 000x
-00- 0-00
-00- 0-00
uuuu uuuu
uuuu uuuu
CMCON0
CMCON1
INTCON
PIE1
CMON
—
COUT
—
CMHYS
GPIE
CMIE
CMIF
T1GSS
INTF
TMR2IE(1)
TMR2IF(1)
CMSYNC
GPIF
GIE
—
PEIE
ADIE(1)
ADIF(1)
T0IE
T0IF
—
CCP1IE(1)
CCP1IF(1)
TMR1IE
TMR1IF
PIR1
—
—
—
TMR1H
TMR1L
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
T1CON
T1GINV
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
TMR1CS
TMR1ON
0000 0000
uuuu uuuu
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Note 1: PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
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NOTES:
DS41302D-page 64
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The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
8.0
TIMER2 MODULE
(PIC12F615/617/HV615 ONLY)
The Timer2 module is an 8-bit timer with the following
features:
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
• 8-bit timer register (TMR2)
• 8-bit period register (PR2)
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
• Interrupt on TMR2 match with PR2
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
See Figure 8-1 for a block diagram of Timer2.
• A write to TMR2 occurs.
• A write to T2CON occurs.
8.1
Timer2 Operation
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register.
Note:
TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
Output
TMR2
Prescaler
Reset
EQ
TMR2
FOSC/4
1:1, 1:4, 1:16
Postscaler
1:1 to 1:16
2
Comparator
PR2
T2CKPS<1:0>
4
TOUTPS<3:0>
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REGISTER 8-1:
T2CON: TIMER 2 CONTROL REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000=1:1 Postscaler
0001=1:2 Postscaler
0010=1:3 Postscaler
0011=1:4 Postscaler
0100=1:5 Postscaler
0101=1:6 Postscaler
0110=1:7 Postscaler
0111=1:8 Postscaler
1000=1:9 Postscaler
1001=1:10 Postscaler
1010=1:11 Postscaler
1011=1:12 Postscaler
1100=1:13 Postscaler
1101=1:14 Postscaler
1110=1:15 Postscaler
1111=1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00=Prescaler is 1
01=Prescaler is 4
1x=Prescaler is 16
TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
—
PEIE
T0IE
INTE
—
GPIE
CMIE
CMIF
T0IF
—
INTF
GPIF
0000 0000
-00- 0-00
-00- 0-00
1111 1111
0000 0000
-000 0000
0000 0000
-00- 0-00
-00- 0-00
1111 1111
0000 0000
-000 0000
ADIE(1)
ADIF(1)
CCP1IE(1)
CCP1IF(1)
TMR2IE(1)
TMR2IF(1)
TMR1IE
TMR1IF
PIR1
—
—
—
PR2(1)
TMR2(1)
T2CON(1)
Timer2 Module Period Register
Holding Register for the 8-bit TMR2 Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0
—
TMR2ON
T2CKPS1
T2CKPS0
Legend:
x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
Note 1:
For PIC12F615/617/HV615 only.
DS41302D-page 66
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
than the analog voltage at VIN-, the output of the
9.0
COMPARATOR MODULE
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
The comparator can be used to interface analog
circuits to a digital circuit by comparing two analog
voltages and providing a digital indication of their
relative magnitudes. The comparator is a very useful
mixed signal building block because it provides analog
functionality independent of the program execution.
The Analog Comparator module includes the following
features:
FIGURE 9-1:SINGLE COMPARATOR
VIN+
VIN-
+
–
Output
• Programmable input section
• Comparator output is available internally/externally
• Programmable output polarity
• Interrupt-on-change
VIN-
• Wake-up from Sleep
VIN+
• PWM shutdown
• Timer1 gate (count enable)
• Output synchronization to Timer1 clock input
• Programmable voltage reference
• User-enable Comparator Hysteresis
Output
9.1
Comparator Overview
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
The comparator is shown in Figure 9-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at VIN+ is less
FIGURE 9-2:
COMPARATOR SIMPLIFIED BLOCK DIAGRAM
CMPOL
To
D
Q
Data Bus
Q1
EN
RD_CMCON0
CMCH
Set CMIF
D
Q
Q3*RD_CMCON0
Reset
EN
CL
(1)
CMON
GP1/CIN0-
0
CMVIN-
CMVIN+
MUX
To PWM Auto-Shutdown
CMOE
GP4/CIN1-
1
CMSYNC
CMPOL
0
MUX
(4)
COUT
CMR
D
Q
1
GP0/CIN+
0
MUX
1
From Timer1
Clock
FixedRef
0
SYNCCMOUT
To Timer1 Gate
CMVREF
MUX
CVREF
1
CMVREN
Note 1: When CMON = 0, the comparator will produce a ‘0’ output to the XOR Gate.
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).
3: Q1 is held high during Sleep mode.
4: Output shown for reference only. See I/O port pin diagram for more details.
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9.2
Analog Input Connection
Considerations
Note 1: When reading a GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert as an analog input, according to
the input specification.
A simplified circuit for an analog input is shown in
Figure 9-3. Since the analog input pins share their
connection with a digital input, they have reverse
biased ESD protection diodes to VDD and VSS. The
analog input, therefore, must be between VSS and VDD.
If the input voltage deviates from this range by more
than 0.6V in either direction, one of the diodes is
forward biased and a latch-up may occur.
2: Analog levels on any pin defined as a
digital input, may cause the input buffer to
consume more current than is specified.
A
maximum source impedance of 10 k is
recommended for the analog sources. Also, any
external component connected to an analog input pin,
such as a capacitor or a Zener diode, should have very
little leakage current to minimize inaccuracies
introduced.
FIGURE 9-3:
ANALOG INPUT MODEL
VDD
VT 0.6V
RIC
RS < 10K
To Comparator
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT 0.6V
VSS
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
RIC
RS
VA
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VT
= Threshold Voltage
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9.3.5
COMPARATOR OUTPUT POLARITY
9.3
Comparator Control
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CMPOL bit of the CMCON0 register. Clear-
ing CMPOL results in a non-inverted output. A com-
plete table showing the output state versus input
conditions and the polarity bit is shown in Table 9-1.
The comparator has two control and Configuration
registers: CMCON0 and CMCON1. The CMCON1
register is used for controlling the interaction with
Timer1 and simultaneously reading the comparator
output.
The CMCON0 register (Register 9-1) contain the
control and Status bits for the following:
• Enable
TABLE 9-1:
OUTPUT STATE VS. INPUT
CONDITIONS
• Input selection
• Reference selection
• Output selection
• Output polarity
Input Conditions
CMPOL
COUT
CMVIN- > CMVIN+
CMVIN- < CMVIN+
CMVIN- > CMVIN+
CMVIN- < CMVIN+
0
0
1
1
0
1
1
0
9.3.1
COMPARATOR ENABLE
Setting the CMON bit of the CMCON0 register enables
the comparator for operation. Clearing the CMON bit
disables the comparator for minimum current
consumption.
Note:
COUT refers to both the register bit and
output pin.
9.4
Comparator Response Time
9.3.2
COMPARATOR INPUT SELECTION
The comparator output is indeterminate for a period of
time after the change of an input source or the selection
of a new reference voltage. This period is referred to as
the response time. The response time of the compara-
tor differs from the settling time of the voltage refer-
ence. Therefore, both of these times must be
considered when determining the total response time
to a comparator input change. See Section 16.0
“Electrical Specifications” for more details.
The CMCH bit of the CMCON0 register directs one of
four analog input pins to the comparator inverting input.
Note:
To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be set in
the ANSEL register and the corresponding
TRIS bits must also be set to disable the
output drivers.
9.3.3
COMPARATOR REFERENCE
SELECTION
Setting the CMR bit of the CMxCON0 register directs
an internal voltage reference or an analog input pin to
the non-inverting input of the comparator. See
Section 9.10 “Comparator Voltage Reference” for
more information on the internal voltage reference
module.
9.3.4
COMPARATOR OUTPUT
SELECTION
The output of the comparator can be monitored by
reading either the COUT bit of the CMCON0 register. In
order to make the output available for an external
connection, the following conditions must be true:
• CMOE bit of the CMxCON0 register must be set
• Corresponding TRIS bit must be cleared
• CMON bit of the CMCON0 register must be set.
Note 1: The CMOE bit overrides the PORT data
latch. Setting the CMON has no impact
on the port override.
2: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external
outputs are not latched.
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FIGURE 9-4:
COMPARATOR
9.5
Comparator Interrupt Operation
INTERRUPT TIMING W/O
CMCON0 READ
The comparator interrupt flag can be set whenever
there is a change in the output value of the comparator.
Changes are recognized by means of a mismatch
circuit which consists of two latches and an exclusive-
or gate (see Figure 9-4 and Figure 9-5). One latch is
updated with the comparator output level when the
CMCON0 register is read. This latch retains the value
until the next read of the CMCON0 register or the
occurrence of a Reset. The other latch of the mismatch
circuit is updated on every Q1 system clock. A
mismatch condition will occur when a comparator
output change is clocked through the second latch on
the Q1 clock cycle. At this point the two mismatch
latches have opposite output levels which is detected
by the exclusive-or gate and fed to the interrupt
circuitry. The mismatch condition persists until either
the CMCON0 register is read or the comparator output
returns to the previous state.
Q1
Q3
CIN+
TRT
COUT
Set CMIF (edge)
CMIF
reset by software
FIGURE 9-5:
COMPARATOR
INTERRUPT TIMING WITH
CMCON0 READ
Q1
Q3
CIN+
TRT
Note 1: A write operation to the CMCON0 register
COUT
will also clear the mismatch condition
Set CMIF (edge)
CMIF
because all writes include
a
read
operation at the beginning of the write
cycle.
cleared by CMCON0 read
reset by software
2: Comparator interrupts will operate
correctly regardless of the state of
CMOE.
Note 1: If a change in the CMCON0 register
(COUT) should occur when a read
operation is being executed (start of the
Q2 cycle), then the CMIF of the PIR1
register interrupt flag may not get set.
The comparator interrupt is set by the mismatch edge
and not the mismatch level. This means that the
interrupt flag can be reset without the additional step of
reading or writing the CMCON0 register to clear the
mismatch registers. When the mismatch registers are
cleared, an interrupt will occur upon the comparator’s
return to the previous state, otherwise no interrupt will
be generated.
2: When a comparator is first enabled, bias
circuitry in the comparator module may
cause an invalid output from the
comparator until the bias circuitry is
stable. Allow about 1 s for bias settling
then clear the mismatch condition and
Software will need to maintain information about the
status of the comparator output, as read from the
CMCON1 register, to determine the actual change that
has occurred.
interrupt
flags
before
enabling
comparator interrupts.
The CMIF bit of the PIR1 register is the Comparator
Interrupt flag. This bit must be reset in software by
clearing it to ‘0’. Since it is also possible to write a '1' to
this register, an interrupt can be generated.
The CMIE bit of the PIE1 register and the PEIE and GIE
bits of the INTCON register must all be set to enable
comparator interrupts. If any of these bits are cleared,
the interrupt is not enabled, although the CMIF bit of
the PIR1 register will still be set if an interrupt condition
occurs.
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9.6
Operation During Sleep
The comparator, if enabled before entering Sleep
mode, remains active during Sleep. The additional
current consumed by the comparator is shown
separately
in
the
Section 16.0
“Electrical
Specifications”. If the comparator is not used to wake
the device, power consumption can be minimized while
in Sleep mode by turning off the comparator. The
comparator is turned off by clearing the CMON bit of the
CMCON0 register.
A change to the comparator output can wake-up the
device from Sleep. To enable the comparator to wake
the device from Sleep, the CMIE bit of the PIE1 register
and the PEIE bit of the INTCON register must be set.
The instruction following the SLEEPinstruction always
executes following a wake from Sleep. If the GIE bit of
the INTCON register is also set, the device will then
execute the Interrupt Service Routine.
9.7
Effects of a Reset
A device Reset forces the CMCON1 register to its
Reset state. This sets the comparator and the voltage
reference to the OFF state.
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REGISTER 9-1:
CMCON0: COMPARATOR CONTROL REGISTER 0
R/W-0
CMON
bit 7
R-0
R/W-0
CMOE
R/W-0
U-0
—
R/W-0
CMR
U-0
—
R/W-0
CMCH
COUT
CMPOL
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
CMON: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled
COUT: Comparator Output bit
If C1POL = 1(inverted polarity):
COUT = 0when CMVIN+ > CMVIN-
COUT = 1when CMVIN+ < CMVIN-
If C1POL = 0(non-inverted polarity):
COUT = 1when CMVIN+ > CMVIN-
COUT = 0when CMVIN+ < CMVIN-
bit 5
bit 4
CMOE: Comparator Output Enable bit
1= COUT is present on the COUT pin(1)
0= COUT is internal only
CMPOL: Comparator Output Polarity Select bit
1= COUT logic is inverted
0= COUT logic is not inverted
bit 3
bit 2
Unimplemented: Read as ‘0’
CMR: Comparator Reference Select bit (non-inverting input)
1= CMVIN+ connects to CMVREF output
0= CMVIN+ connects to CIN+ pin
bit 1
bit 0
Unimplemented: Read as ‘0’
CMCH: Comparator C1 Channel Select bit
0= CMVIN- pin of the Comparator connects to CIN0-
1= CMVIN- pin of the Comparator connects to CIN1-
Note 1: Comparator output requires the following three conditions: CMOE = 1, CMON = 1and corresponding port
TRIS bit = 0.
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9.8
Comparator Gating Timer1
9.9
Synchronizing Comparator Output
to Timer1
This feature can be used to time the duration or interval
of analog events. Clearing the T1GSS bit of the
CMCON1 register will enable Timer1 to increment
based on the output of the comparator. This requires
that Timer1 is on and gating is enabled. See
Section 7.0 “Timer1 Module with Gate Control” for
details.
The comparator output can be synchronized with
Timer1 by setting the CMSYNC bit of the CMCON1
register. When enabled, the comparator output is
latched on the falling edge of the Timer1 clock source.
If a prescaler is used with Timer1, the comparator
output is latched after the prescaling function. To
prevent a race condition, the comparator output is
latched on the falling edge of the Timer1 clock source
and Timer1 increments on the rising edge of its clock
source. See the Comparator Block Diagram (Figure 9-
2) and the Timer1 Block Diagram (Figure 7-1) for more
information.
It is recommended to synchronize the comparator with
Timer1 by setting the CMSYNC bit when the
comparator is used as the Timer1 gate source. This
ensures Timer1 does not miss an increment if the
comparator changes during an increment.
REGISTER 9-2:
CMCON1: COMPARATOR CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
T1ACS
CMHYS
T1GSS
CMSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
Unimplemented: Read as ‘0’
T1ACS: Timer1 Alternate Clock Select bit
1= Timer 1 Clock Source is System Clock (FOSC)
0= Timer 1 Clock Source is Instruction Clock (FOSC\4)
bit 3
CMHYS: Comparator Hysteresis Select bit
1 = Comparator Hysteresis enabled
0 = Comparator Hysteresis disabled
bit 2
bit 1
Unimplemented: Read as ‘0’
T1GSS: Timer1 Gate Source Select bit(1)
1= Timer 1 Gate Source is T1G pin (pin should be configured as digital input)
0= Timer 1 Gate Source is comparator output
bit 0
CMSYNC: Comparator Output Synchronization bit(2)
1= Output is synchronized with falling edge of Timer1 clock
0= Output is asynchronous
Note 1: Refer to Section 7.6 “Timer1 Gate”.
2: Refer to Figure 9-2.
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9.10.3
OUTPUT CLAMPED TO VSS
9.10 Comparator Voltage Reference
The CVREF output voltage can be set to Vss with no
power consumption by configuring VRCON as follows:
The Comparator Voltage Reference module provides
an internally generated voltage reference for the
comparators. The following features are available:
• FVREN = 0
• Independent from Comparator operation
• 16-level voltage range
This allows the comparator to detect a zero-crossing
while not consuming additional CVREF module current.
• Output clamped to VSS
9.10.4
OUTPUT RATIOMETRIC TO VDD
• Ratiometric with VDD
The comparator voltage reference is VDD derived and
therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 16.0
“Electrical Specifications”.
• Fixed Reference (0.6)
The VRCON register (Register 9-3) controls the
Voltage Reference module shown in Register 9-6.
9.10.1
INDEPENDENT OPERATION
9.10.5
FIXED VOLTAGE REFERENCE
The comparator voltage reference is independent of
the comparator configuration. Setting the VREN bit of
the VRCON register will enable the voltage reference.
The fixed voltage reference is independent of VDD, with
a nominal output voltage of 0.6V. This reference can be
enabled by setting the FVREN bit of the VRCON
register to ‘1’. This reference is always enabled when
the HFINTOSC oscillator is active.
9.10.2
OUTPUT VOLTAGE SELECTION
The CVREF voltage reference has 2 ranges with 16
voltage levels in each range. Range selection is
controlled by the VRR bit of the VRCON register. The
16 levels are set with the VR<3:0> bits of the VRCON
register.
9.10.6
FIXED VOLTAGE REFERENCE
STABILIZATION PERIOD
When the Fixed Voltage Reference module is enabled,
it will require some time for the reference and its
amplifier circuits to stabilize. The user program must
include a small delay routine to allow the module to
settle. See Section 16.0 “Electrical Specifications”
for the minimum delay requirement.
The CVREF output voltage is determined by the
following equations:
EQUATION 9-1:
CVREF OUTPUT VOLTAGE
VRR = 1 (low range):
CVREF = (VR<3:0>/24) VDD
VRR = 0 (high range):
CVREF = (VDD/4) +
9.10.7
VOLTAGE REFERENCE
SELECTION
(VR<3:0> VDD/32)
Multiplexers on the output of the Voltage Reference
module enable selection of either the CVREF or fixed
voltage reference for use by the comparators.
The full range of VSS to VDD cannot be realized due to
the construction of the module. See Figure 9-6.
Setting the CMVREN bit of the VRCON register
enables current to flow in the CVREF voltage divider
and selects the CVREF voltage for use by the Compar-
ator. Clearing the CMVREN bit selects the fixed voltage
for use by the Comparator.
When the CMVREN bit is cleared, current flow in the
CVREF voltage divider is disabled minimizing the power
drain of the voltage reference peripheral.
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FIGURE 9-6:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
VRR
8R
Analog
MUX
CMVREN
15
0
(1)
CVREF
To Comparators
and ADC Module
(1)
VR<3:0>
4
FVREN
Sleep
HFINTOSC enable
EN
FixedRef
0.6V
Fixed Voltage
Reference
To Comparators
and ADC Module
Note 1: Care should be taken to ensure CVREF remains within the comparator common mode input range. See
Section 16.0 “Electrical Specifications” for more detail.
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REGISTER 9-3:
VRCON: VOLTAGE REFERENCE CONTROL REGISTER
R/W-0
CMVREN
bit 7
U-0
—
R/W-0
VRR
R/W-0
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
FVREN
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
CMVREN: Comparator Voltage Reference Enable bit(1, 2)
1= CVREF circuit powered on and routed to CVREF input of the Comparator
0= 0.6 Volt constant reference routed to CVREF input of the Comparator
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
FVREN: 0.6V Reference Enable bit(2)
1= Enabled
0= Disabled
bit 3-0
VR<3:0>: Comparator Voltage Reference CVREF Value Selection bits (0 VR<3:0> 15)
When VRR = 1: CVREF = (VR<3:0>/24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD
Note 1: When CMVREN is low, the CVREF circuit is powered down and does not contribute to IDD current.
2: When CMVREN is low and the FVREN bit is low, the CVREF signal should provide Vss to the comparator.
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Figure 9-7 shows the relationship between the analog
9.11 Comparator Hysteresis
input levels and digital output of a comparator with and
without hysteresis. The output of the comparator
changes from a low state to a high state only when the
analog voltage at VIN+ rises above the upper
hysteresis threshold (VH+). The output of the
comparator changes from a high state to a low state
only when the analog voltage at VIN+ falls below the
lower hysteresis threshold (VH-).
Each comparator has built-in hysteresis that is user
enabled by setting the CMHYS bit of the CMCON1
register. The hysteresis feature can help filter noise and
reduce multiple comparator output transitions when the
output is changing state.
FIGURE 9-7:
COMPARATOR HYSTERESIS
VIN+
VIN-
+
–
Output
V+
VH+
VIN-
VH-
VIN+
Output
(Without Hysteresis)
Output
(With Hysteresis)
Note:
The black areas of the comparator output represents the uncertainty due to input offsets and response time.
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TABLE 9-2:
SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND
VOLTAGE REFERENCE MODULES
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSEL
CMCON0
CMCON1
INTCON
PIE1
—
CMON
—
ADCS2(1) ADCS1(1) ADCS0(1)
ANS3
—
ANS2(1)
CMR
—
ANS1
—
ANS0
CMCH
CMSYNC
GPIF
-000 1111
0000 -000
0000 0000
0000 000x
-00- 0-00
-00- 0-00
--xx xxxx
--11 1111
0-00 0000
-000 1111
0000 -000
0000 0000
0000 000x
-00- 0-00
-00- 0-00
--uu uuuu
--11 1111
0-00 0000
COUT
—
CMOE
—
CMPOL
T1ACS
INTE
—
CMHYS
GPIE
CMIE
CMIF
GP3
T1GSS
GIE
—
PEIE
ADIE(1)
ADIF(1)
—
T0IE
T0IF
—
INTF
CCP1IE(1)
CCP1IF(1)
GP5
TMR2IE(1)
TMR2IF(1)
GP1
TMR1IE
TMR1IF
GP0
PIR1
—
—
—
GPIO
—
GP4
GP2
TRISIO
—
—
TRISIO5
VRR
TRISIO4 TRISIO3 TRISIO2
FVREN VR3 VR2
TRISIO1
VR1
TRISIO0
VR0
VRCON
CMVREN
—
Legend:
x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for comparator.
Note 1: For PIC12F615/617/HV615 only.
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10.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
(PIC12F615/617/HV615 ONLY)
Note:
The ADRESL and ADRESH registers are
Read Only.
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).
The ADC voltage reference is software selectable to
either VDD or a voltage applied to the external reference
pins.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 10-1 shows the block diagram of the ADC.
FIGURE 10-1:
ADC BLOCK DIAGRAM
VDD
VCFG = 0
VCFG = 1
VREF
000
001
010
011
100
101
110
GP0/AN0
GP1/AN1/VREF
GP2/AN2
GP4/AN3
A/D
CVREF
10
GO/DONE
ADON
0.6V Reference
1.2V Reference
0= Left Justify
ADFM
1= Right Justify
10
CHS
ADRESH ADRESL
VSS
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10.1.3
ADC VOLTAGE REFERENCE
10.1 ADC Configuration
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either VDD or an external voltage
source. The negative voltage reference is always
connected to the ground reference.
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
10.1.4
CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCS bits of the ANSEL register.
There are seven possible clock options:
• Results formatting
10.1.1
PORT CONFIGURATION
• FOSC/2
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding port
section for more information.
• FOSC/4
• FOSC/8
• FOSC/16
• FOSC/32
• FOSC/64
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
• FRC (dedicated internal oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 10-3.
10.1.2
CHANNEL SELECTION
For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
Section 16.0 “Electrical Specifications” for more
information. Table 10-1 gives examples of appropriate
ADC clock selections.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 10.2
“ADC Operation” for more information.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
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TABLE 10-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD)
ADC Clock Source ADCS<2:0>
Device Frequency (FOSC)
20 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC
000
100
001
101
010
110
x11
100 ns(2)
200 ns(2)
400 ns(2)
800 ns(2)
1.6 s
250 ns(2)
500 ns(2)
1.0 s(2)
2.0 s
500 ns(2)
1.0 s(2)
2.0 s
2.0 s
4.0 s
8.0 s(3)
16.0 s(3)
32.0 s(3)
64.0 s(3)
2-6 s(1,4)
4.0 s
4.0 s
8.0 s(3)
16.0 s(3)
2-6 s(1,4)
3.2 s
2-6 s(1,4)
8.0 s(3)
2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.
FIGURE 10-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY to TAD
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit
ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
10.1.5
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 10.1.5 “Interrupts” for more
information.
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10.1.6
RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 10-4 shows the two output formats.
FIGURE 10-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
(ADFM = 0)
MSB
bit 7
LSB
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
10.2.4
ADC OPERATION DURING SLEEP
10.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
10.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 10.2.6 “A/D Conver-
sion Procedure”.
When the ADC clock source is something other than
10.2.2
COMPLETION OF A CONVERSION
FRC,
a SLEEP instruction causes the present
When the conversion is complete, the ADC module will:
conversion to be aborted and the ADC module is
turned off, although the ADON bit remains set.
• Clear the GO/DONE bit
• Set the ADIF flag bit
10.2.5
SPECIAL EVENT TRIGGER
• Update the ADRESH:ADRESL registers with new
conversion result
The ECCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
this trigger occurs, the GO/DONE bit is set by hardware
and the Timer1 counter resets to zero.
10.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH:ADRESL registers will not be updated with
the partially complete Analog-to-Digital conversion
sample. Instead, the ADRESH:ADRESL register pair
will retain the value of the previous conversion. Addi-
tionally, a 2 TAD delay is required before another acqui-
sition can be initiated. Following this delay, an input
acquisition is automatically started on the selected
channel.
Using the Special Event Trigger does not assure
proper ADC timing. It is the user’s responsibility to
ensure that the ADC timing requirements are met.
See Section 11.0 “Enhanced Capture/Compare/
PWM (With Auto-Shutdown and Dead Band)
Module (PIC12F615/617/HV615 only)” for more
information.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
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PIC12F609/615/617/12HV609/615
10.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 10-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd reference, Frc clock
;and GP0 input.
;
1. Configure Port:
• Disable pin output driver (See TRIS register)
• Configure pin as analog
;Conversion start & polling for completion
; are included.
;
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Select result format
BANKSEL TRISIO
;
BSF
TRISIO,0
;Set GP0 to input
;
BANKSEL ANSEL
MOVLW
IORWF
BANKSEL ADCON0
B’01110001’ ;ADC Frc clock,
ANSEL
; and GP0 as analog
;
• Turn on ADC module
MOVLW
MOVWF
CALL
BSF
BTFSC
GOTO
BANKSEL ADRESH
MOVF
MOVWF
BANKSEL ADRESL
B’10000001’ ;Right justify,
ADCON0
;Vdd Vref, AN0, On
;Acquisiton delay
;Start conversion
;Is conversion done?
;No, test again
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
SampleTime
ADCON0,GO
ADCON0,GO
$-1
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
ADRESH,W
RESULTHI
;Read upper 2 bits
;Store in GPR space
;
.
5. Start conversion by setting the GO/DONE bit.
MOVF
MOVWF
ADRESL,W
RESULTLO
;Read lower 8 bits
;Store in GPR space
6. Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 10.3 “A/D Acquisition
Requirements”.
2010 Microchip Technology Inc.
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10.2.7
ADC REGISTER DEFINITIONS
The following registers are used to control the operation of the ADC.
REGISTER 10-1: ADCON0: A/D CONTROL REGISTER 0
R/W-0
ADFM
R/W-0
VCFG
U-0
—
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
R/W-0
ADON
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
ADFM: A/D Conversion Result Format Select bit
1= Right justified
0= Left justified
VCFG: Voltage Reference bit
1= VREF pin
0= VDD
bit 5
Unimplemented: Read as ‘0’
bit 4-2
CHS<2:0>: Analog Channel Select bits
000= Channel 00 (AN0)
001= Channel 01 (AN1)
010= Channel 02 (AN2)
011= Channel 03 (AN3)
100= CVREF
101= 0.6V Reference
110= 1.2V Reference
111= Reserved. Do not use.
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: When the CHS<2:0> bits change to select the 1.2V or 0.6V reference, the reference output voltage will
have a transient. If the Comparator module uses this 0.6V reference voltage, the comparator output may
momentarily change state due to the transient.
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REGISTER 10-2: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES9
ADRES8
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 10-3: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 (READ-ONLY)
R-x
R-x
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Unimplemented: Read as ‘0’
REGISTER 10-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 (READ-ONLY)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-x
R-x
ADRES9
ADRES8
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-2
bit 1-0
Unimplemented: Read as ‘0’
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 10-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 (READ-ONLY)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
ADRES7
ADRES6
ADRES5
ADRES4
ADRES3
ADRES2
ADRES1
ADRES0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
2010 Microchip Technology Inc.
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an A/D acquisition must be done before the conversion
10.3 A/D Acquisition Requirements
can be started. To calculate the minimum acquisition
time, Equation 10-1 may be used. This equation
assumes that 1/2 LSb error is used (1024 steps for the
ADC). The 1/2 LSb error is the maximum error allowed
for the ADC to meet its specified resolution.
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 10-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 10-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),
EQUATION 10-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
2047
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – ----------- = VCHOLD
–TC
---------
RC
;[2] VCHOLD charge response to VAPPLIED
VAPPLIED 1 – e
= VCHOLD
–Tc
--------
RC
1
;combining [1] and [2]
= VAPPLIED1 – -----------
2047
VAPPLIED 1 – e
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –10pF1k + 7k + 10k ln(0.0004885)
= 1.37µs
Therefore:
TACQ = 2µs + 1.37µs + 50°C- 25°C0.05µs/°C
= 4.67µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS41302D-page 86
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 10-4:
ANALOG INPUT MODEL
VDD
VT = 0.6V
Sampling
Switch
ANx
SS
RIC 1k
Rss
Rs
CPIN
5 pF
VA
I LEAKAGE
± 500 nA
CHOLD = 10 pF
VSS/VREF-
VT = 0.6V
6V
5V
RSS
VDD 4V
3V
Legend: CPIN
= Input Capacitance
= Threshold Voltage
VT
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
SS
CHOLD
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance
5 6 7 8 9 1011
Sampling Switch
(k)
FIGURE 10-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
1 LSB ideal
Full-Scale
Transition
004h
003h
002h
001h
000h
Analog Input Voltage
1 LSB ideal
Zero-Scale
Transition
VDD/VREF+
VSS/VREF-
2010 Microchip Technology Inc.
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TABLE 10-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADCON0(1)
ANSEL
ADRESH(1,2) A/D Result Register High Byte
ADRESL(1,2) A/D Result Register Low Byte
ADFM
—
VCFG
—
CHS2
CHS1
ANS3
CHS0
GO/DONE ADON 00-0 0000 00-0 0000
ADCS2(1) ADCS1(1) ADCS0(1)
ANS2
ANS1
ANS0
-000 1111 -000 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--x0 x000 --x0 x000
0000 0000 0000 0000
(1)
GPIO
—
GIE
—
—
GP5
T0IE
GP4
INTE
—
GP3
GPIE
CMIE
CMIF
GP2
T0IF
—
GP1
INTF
GP0
INTCON
PIE1
PEIE
GPIF
(1)
(1)
(1)
(1)
(1)
ADIE
ADIF
—
CCP1IE
CCP1IF
TMR2IE
TMR2IF
TMR1IE -00- 0-00 -00- 0-00
TMR1IF -00- 0-00 -00- 0-00
(1)
PIR1
—
—
—
TRISIO
Legend:
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used for ADC module.
Note 1: For PIC12F615/617/HV615 only.
2: Read Only Register.
DS41302D-page 88
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
event when a predetermined amount of time has
expired. The PWM mode can generate a Pulse-Width
Modulated signal of varying frequency and duty cycle.
11.0 ENHANCED CAPTURE/
COMPARE/PWM (WITH AUTO-
SHUTDOWN AND DEAD BAND)
MODULE (PIC12F615/617/
HV615 ONLY)
Table 11-1 shows the timer resources required by the
ECCP module.
TABLE 11-1: ECCP MODE – TIMER
RESOURCES REQUIRED
The Enhanced Capture/Compare/PWM module is a
peripheral which allows the user to time and control
different events. In Capture mode, the peripheral
allows the timing of the duration of an event.The
Compare mode allows the user to trigger an external
ECCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
REGISTER 11-1: CCP1CON: ENHANCED CCP1 CONTROL REGISTER
R/W-0
P1M
U-0
—
R/W-0
R/W-0
DC1B0
R/W-0
R/W-0
R/W-0
CCP1M1
R/W-0
DC1B1
CCP1M3
CCP1M2
CCP1M0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
P1M: PWM Output Configuration bits
If CCP1M<3:2> = 00, 01, 10:
x= P1A assigned as Capture/Compare input; P1B assigned as port pins
If CCP1M<3:2> = 11:
0= Single output; P1A modulated; P1B assigned as port pins
1= Half-Bridge output; P1A, P1B modulated with dead-band control
bit 6
Unimplemented: Read as ‘0’
bit 5-4
DC1B<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.
bit 3-0
CCP1M<3:0>: ECCP Mode Select bits
0000=Capture/Compare/PWM off (resets ECCP module)
0001=Unused (reserved)
0010=Compare mode, toggle output on match (CCP1IF bit is set)
0011=Unused (reserved)
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4th rising edge
0111=Capture mode, every 16th rising edge
1000=Compare mode, set output on match (CCP1IF bit is set)
1001=Compare mode, clear output on match (CCP1IF bit is set)
1010=Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected)
1011=Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 or TMR2 and starts
an A/D conversion, if the ADC module is enabled)
1100=PWM mode; P1A active-high; P1B active-high
1101=PWM mode; P1A active-high; P1B active-low
1110=PWM mode; P1A active-low; P1B active-high
1111=PWM mode; P1A active-low; P1B active-low
2010 Microchip Technology Inc.
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11.1.2
TIMER1 MODE SELECTION
11.1 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin CCP1. An event is defined as one of the
following and is configured by the CCP1M<3:0> bits of
the CCP1CON register:
11.1.3
SOFTWARE INTERRUPT
• Every falling edge
• Every rising edge
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP1IE interrupt enable bit of the PIE1 register clear to
avoid false interrupts. Additionally, the user should
clear the CCP1IF interrupt flag bit of the PIR1 register
following any change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCP1IF of the PIR1 register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPR1H, CCPR1L register pair
is read, the old captured value is overwritten by the new
captured value (see Figure 11-1).
11.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCP1M<3:0> bits of the CCP1CON register.
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. Any Reset will clear the prescaler counter.
11.1.1
CCP1 PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the associated TRIS control bit.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCP1CON register before changing the
prescaler (see Example 11-1).
Note:
If the CCP1 pin is configured as an output,
a write to the port can cause a capture
condition.
FIGURE 11-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
EXAMPLE 11-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSELCCP1CON
;Set Bank bits to point
;to CCP1CON
;Turn CCP module off
Set Flag bit CCP1IF
(PIR1 register)
Prescaler
1, 4, 16
CLRF
CCP1CON
MOVLW
NEW_CAPT_PS;Load the W reg with
; the new prescaler
CCP1
pin
CCPR1H
CCPR1L
; move value and CCP ON
Capture
Enable
MOVWF
CCP1CON
;Load CCP1CON with this
; value
and
Edge Detect
TMR1H
TMR1L
CCP1CON<3:0>
System Clock (FOSC)
DS41302D-page 90
2010 Microchip Technology Inc.
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TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCPR1L
P1M
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
INTCON
PIE1
GIE
—
PEIE
T0IE
INTE
—
GPIE
CMIE
CMIF
T0IF
—
INTF
GPIF
0000 0000 0000 0000
ADIE(1) CCP1IE(1)
ADIF(1) CCP1IF(1)
TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00
TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00
PIR1
—
—
—
T1CON
TMR1L
TMR1H
TRISIO
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
0000 0000 uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 91
PIC12F609/615/617/12HV609/615
11.2.2
TIMER1 MODE SELECTION
11.2 Compare Mode
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 module may:
• Toggle the CCP1 output.
• Set the CCP1 output.
11.2.3
SOFTWARE INTERRUPT MODE
• Clear the CCP1 output.
When Generate Software Interrupt mode is chosen
(CCP1M<3:0> = 1010), the CCP1 module does not
assert control of the CCP1 pin (see the CCP1CON
register).
• Generate a Special Event Trigger.
• Generate a Software Interrupt.
The action on the pin is based on the value of the
CCP1M<3:0> control bits of the CCP1CON register.
11.2.4
SPECIAL EVENT TRIGGER
All Compare modes can generate an interrupt.
When Special Event Trigger mode is chosen
(CCP1M<3:0> = 1011), the CCP1 module does the
following:
FIGURE 11-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
CCP1CON<3:0>
Mode Select
The CCP1 module does not assert control of the CCP1
pin in this mode (see the CCP1CON register).
Set CCP1IF Interrupt Flag
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPR1H, CCPR1L
register pair. The TMR1H, TMR1L register pair is not
reset until the next rising edge of the Timer1 clock. This
allows the CCPR1H, CCPR1L register pair to
effectively provide a 16-bit programmable period
register for Timer1.
(PIR1)
4
CCP1
Pin
CCPR1H CCPR1L
Comparator
Q
S
R
Output
Logic
Match
TMR1H TMR1L
TRIS
Output Enable
Special Event Trigger
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMRxIF of the PIR1 register.
Special Event Trigger will:
•
•
•
Clear TMR1H and TMR1L registers.
NOT set interrupt flag bit TMR1IF of the PIR1 register.
Set the GO/DONE bit to start the ADC conversion.
2: Removing the match condition by
changing the contents of the CCPR1H
and CCPR1L register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will preclude
the Reset from occurring.
11.2.1
CCP1 PIN CONFIGURATION
The user must configure the CCP1 pin as an output by
clearing the associated TRIS bit.
Note:
Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the PORT I/O
data latch.
DS41302D-page 92
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCPR1L
P1M
—
DC1B1
DC1B0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000
xxxx xxxx uuuu uuuu
Capture/Compare/PWM Register 1 Low Byte
CCPR1H Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
INTCON
PIE1
GIE
—
PEIE
T0IE
INTE
—
GPIE
CMIE
CMIF
T0IF
—
INTF
GPIF
0000 0000 0000 0000
ADIE(1) CCP1IE(1)
ADIF(1) CCP1IF(1)
TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00
TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00
PIR1
—
—
—
T1CON
TMR1L
TMR1H
TMR2
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module Register
0000 0000 uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Compare.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
DS41302D-page 93
PIC12F609/615/617/12HV609/615
The PWM output (Figure 11-4) has a time base
(period) and a time that the output stays high (duty
cycle).
11.3 PWM Mode
The PWM mode generates a Pulse-Width Modulated
signal on the CCP1 pin. The duty cycle, period and
resolution are determined by the following registers:
FIGURE 11-4:
CCP PWM OUTPUT
• PR2
Period
• T2CON
• CCPR1L
• CCP1CON
Pulse Width
TMR2 = PR2
TMR2 = CCPRxL:CCPxCON<5:4>
In Pulse-Width Modulation (PWM) mode, the CCP
module produces up to a 10-bit resolution PWM output
on the CCP1 pin. Since the CCP1 pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCP1 pin output driver.
TMR2 = 0
Note:
Clearing the CCP1CON register will
relinquish CCP1 control of the CCP1 pin.
Figure 11-3 shows a simplified block diagram of PWM
operation.
Figure 11-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 11.3.7
“Setup for PWM Operation”.
FIGURE 11-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
CCPR1H(2) (Slave)
Comparator
CCP1
R
S
Q
(1)
TMR2
TRIS
Comparator
PR2
Clear Timer2,
toggle CCP1 pin and
latch duty cycle
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
2: In PWM mode, CCPR1H is a read-only register.
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11.3.1
PWM PERIOD
EQUATION 11-2: PULSE WIDTH
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
Pulse Width = CCPR1L:CCP1CON<5:4>
TOSC (TMR2 Prescale Value)
EQUATION 11-1: PWM PERIOD
EQUATION 11-3: DUTY CYCLE RATIO
PWM Period = PR2 + 1 4 TOSC
(TMR2 Prescale Value)
CCPR1L:CCP1CON<5:4>
Duty Cycle Ratio = -----------------------------------------------------------------------
4PR2 + 1
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
• TMR2 is cleared
• The CCP1 pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H.
Note:
The Timer2 postscaler (see Section 8.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
When the 10-bit time base matches the CCPR1H and
2-bit latch, then the CCP1 pin is cleared (see Figure 11-
3).
11.3.2
PWM DUTY CYCLE
11.3.3
PWM RESOLUTION
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR1L register and
DC1B<1:0> bits of the CCP1CON register. The
CCPR1L contains the eight MSbs and the DC1B<1:0>
bits of the CCP1CON register contain the two LSbs.
CCPR1L and DC1B<1:0> bits of the CCP1CON
register can be written to at any time. The duty cycle
value is not latched into CCPR1H until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR1H
register is read-only.
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 11-4.
EQUATION 11-4: PWM RESOLUTION
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 11-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
2010 Microchip Technology Inc.
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11.3.4
OPERATION IN SLEEP MODE
11.3.7
SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCP1
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Disable the PWM pin (CCP1) output drivers by
setting the associated TRIS bit.
2. Set the PWM period by loading the PR2 register.
3. Configure the CCP module for the PWM mode
by loading the CCP1CON register with the
appropriate values.
11.3.5
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 4.0 “Oscillator Module” for additional
details.
4. Set the PWM duty cycle by loading the CCPR1L
register and DC1B bits of the CCP1CON register.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the PIR1
register.
11.3.6
EFFECTS OF RESET
• Set the Timer2 prescale value by loading the
T2CKPS bits of the T2CON register.
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output after a new PWM cycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of the
PIR1 register is set).
• Enable the CCP1 pin output driver by clearing
the associated TRIS bit.
DS41302D-page 96
2010 Microchip Technology Inc.
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The PWM outputs are multiplexed with I/O pins and are
11.4 PWM (Enhanced Mode)
designated P1A and P1B. The polarity of the PWM pins
is configurable and is selected by setting the CCP1M
bits in the CCP1CON register appropriately.
The Enhanced PWM Mode can generate a PWM signal
on up to four different output pins with up to 10-bits of
resolution. It can do this through four different PWM
output modes:
Table 11-6 shows the pin assignments for each
Enhanced PWM mode.
• Single PWM
Figure 11-5 shows an example of a simplified block
diagram of the Enhanced PWM module.
• Half-Bridge PWM
To select an Enhanced PWM mode, the P1M bits of the
CCP1CON register must be set appropriately.
Note:
To prevent the generation of an
incomplete waveform when the PWM is
first enabled, the ECCP module waits until
the start of a new PWM period before
generating a PWM signal.
FIGURE 11-5:
EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE
CCP1<1:0>
P1M<1:0>
CCP1M<3:0>
4
Duty Cycle Registers
2
CCPR1L
(APFCON<0>)
P1ASEL
CCP1/P1A
CCP1/P1A*
0
CCPR1H (Slave)
Comparator
CCP1/P1A
TRISIO2
TRISIO5
1
R
S
Q
Output
Controller
(1)
TMR2
(APFCON<1>)
P1BSEL
P1B
0
1
Comparator
PR2
Clear Timer2,
toggle PWM pin and
latch duty cycle
TRISIO0
TRISIO4
P1B
P1B*
PWM1CON
*
Alternate pin function.
The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.
Note 1:
Note 1: The TRIS register value for each PWM output must be configured appropriately.
2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.
3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.
TABLE 11-6: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES
ECCP Mode
P1M<1:0>
CCP1/P1A
P1B
Single
00
10
Yes(1)
Yes
Yes(1)
Yes
Half-Bridge
2010 Microchip Technology Inc.
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FIGURE 11-6:
EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH
STATE)
PR2+1
Pulse
Width
0
Signal
P1M<1:0>
Period
P1A Modulated
(Single Output)
00
10
Delay(1)
Delay(1)
P1A Modulated
P1B Modulated
(Half-Bridge)
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
FIGURE 11-7:
EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE)
PR2+1
Pulse
Width
0
Signal
P1M<1:0>
Period
P1A Modulated
P1A Modulated
P1B Modulated
(Single Output)
00
10
Delay(1)
Delay(1)
(Half-Bridge)
Relationships:
•
•
•
Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value)
Pulse Width = TOSC * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value)
Delay = 4 * TOSC * (PWM1CON<6:0>)
Note 1: Dead-band delay is programmed using the PWM1CON register (Section 11.4.6 “Programmable Dead-Band Delay
mode”).
DS41302D-page 98
2010 Microchip Technology Inc.
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Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
11.4.1
HALF-BRIDGE MODE
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see Figure 11-8).
This mode can be used for Half-Bridge applications, as
shown in Figure 11-9, or for Full-Bridge applications,
where four power switches are being modulated with
two PWM signals.
FIGURE 11-8:
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
Period
Period
Pulse Width
(2)
(2)
P1A
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in Half-
Bridge power devices. The value of the PDC<6:0> bits of
the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains inactive during the entire cycle. See
Section 11.4.6 “Programmable Dead-Band Delay
mode” for more details of the dead-band delay
operations.
td
td
P1B
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
FIGURE 11-9:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
-
P1A
Load
FET
Driver
+
-
P1B
Half-Bridge Output Driving a Full-Bridge Circuit
V+
FET
Driver
FET
Driver
P1A
Load
FET
FET
Driver
Driver
P1B
2010 Microchip Technology Inc.
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11.4.2
START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the high-
impedance state. The external circuits
must keep the power switch devices in the
OFF state until the microcontroller drives
the I/O pins with the proper signal levels or
activates the PWM output(s).
The CCP1M<1:0> bits of the CCP1CON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each PWM output pin (P1A
and P1B). The PWM output polarities must be selected
before the PWM pin output drivers are enabled.
Changing the polarity configuration while the PWM pin
output drivers are enable is not recommended since it
may result in damage to the application circuits.
The P1A and P1B output latches may not be in the proper
states when the PWM module is initialized. Enabling the
PWM pin output drivers at the same time as the
Enhanced PWM modes may cause damage to the
application circuit. The Enhanced PWM modes must be
enabled in the proper Output mode and complete a full
PWM cycle before configuring the PWM pin output
drivers. The completion of a full PWM cycle is indicated
by the TMR2IF bit of the PIR1 register being set as the
second PWM period begins.
11.4.3
OPERATION DURING SLEEP
When the device is placed in sleep, the allocated timer
will not increment and the state of the module will not
change. If the CCP1 pin is driving a value, it will
continue to drive that value. When the device wakes
up, it will continue from this state.
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A shutdown condition is indicated by the ECCPASE
(Auto-Shutdown Event Status) bit of the ECCPAS
register. If the bit is a ‘0’, the PWM pins are operating
normally. If the bit is a ‘1’, the PWM outputs are in the
shutdown state. Refer to Figure 1.
11.4.4
ENHANCED PWM AUTO-
SHUTDOWN MODE
The PWM mode supports an Auto-Shutdown mode that
will disable the PWM outputs when an external
shutdown event occurs. Auto-Shutdown mode places
the PWM output pins into a predetermined state. This
mode is used to help prevent the PWM from damaging
the application.
When a shutdown event occurs, two things happen:
The ECCPASE bit is set to ‘1’. The ECCPASE will
remain set until cleared in firmware or an auto-restart
occurs (see Section 11.4.5 “Auto-Restart Mode”).
The auto-shutdown sources are selected using the
ECCPASx bits of the ECCPAS register. A shutdown
event may be generated by:
The enabled PWM pins are asynchronously placed in
their shutdown states. The state of P1A is determined by
the PSSAC bit. The state of P1B is determined by the
PSSBD bit. The PSSAC and PSSBD bits are located in
the ECCPAS register. Each pin may be placed into one
of three states:
• A logic ‘0’ on the INT pin
• Comparator
• Setting the ECCPASE bit in firmware
• Drive logic ‘1’
• Drive logic ‘0’
• Tri-state (high-impedance)
FIGURE 11-10:
AUTO-SHUTDOWN BLOCK DIAGRAM
ECCPAS<2:0>
111
110
101
100
011
010
001
000
INT
PSSAC<0>
1
P1A_DRV
0
From Comparator
PRSEN
PSSAC<1>
R
D
S
P1A
TRISx
From Data Bus
ECCPASE
Q
Write to ECCPASE
PSSBD<0>
P1B_DRV
1
0
PSSBD<1>
TRISx
P1B
2010 Microchip Technology Inc.
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REGISTER 11-2: ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ECCPASE
ECCPAS2
ECCPAS1
ECCPAS0
PSSAC1
PSSAC0
PSSBD1
PSSBD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 7
ECCPASE: ECCP Auto-Shutdown Event Status bit
1= A shutdown event has occurred; ECCP outputs are in shutdown state
0= ECCP outputs are operating
bit 6-4
ECCPAS<2:0>: ECCP Auto-shutdown Source Select bits
000=Auto-Shutdown is disabled
001=Comparator output change
010=Auto-Shutdown is disabled
011=Comparator output change(1)
100=VIL on INT pin
101=VIL on INT pin or Comparator change
110=VIL on INT pin(1)
111=VIL on INT pin or Comparator change
bit 3-2
bit 1-0
PSSAC<1:0>: Pin P1A Shutdown State Control bits
00= Drive pin P1A to ‘0’
01= Drive pin P1A to ‘1’
1x= Pin P1A tri-state
PSSBD<1:0>: Pin P1B Shutdown State Control bits
00= Drive pin P1B to ‘0’
01= Drive pin P1B to ‘1’
1x= Pin P1B tri-state
Note 1: If CMSYNC is enabled, the shutdown will be delayed by Timer1.
Note 1: The auto-shutdown condition is a level-
based signal, not an edge-based signal.
As long as the level is present, the auto-
shutdown will persist.
2: Writing to the ECCPASE bit is disabled
while an auto-shutdown condition
persists.
3: Once the auto-shutdown condition has
been removed and the PWM restarted
(either through firmware or auto-restart)
the PWM signal will always restart at the
beginning of the next PWM period.
DS41302D-page 102
2010 Microchip Technology Inc.
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FIGURE 11-11:
PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PRSEN = 0)
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
ECCPASE
Cleared by
Firmware
Event Occurs Event Clears
Start of
PWM Period
Shutdown
Shutdown
PWM
Resumes
11.4.5
AUTO-RESTART MODE
The Enhanced PWM can be configured to automati-
cally restart the PWM signal once the auto-shutdown
condition has been removed. Auto-restart is enabled by
setting the PRSEN bit in the PWM1CON register.
If auto-restart is enabled, the ECCPASE bit will remain
set as long as the auto-shutdown condition is active.
When the auto-shutdown condition is removed, the
ECCPASE bit will be cleared via hardware and normal
operation will resume.
FIGURE 11-12:
PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PRSEN = 1)
Shutdown Event
ECCPASE bit
PWM Activity
PWM Period
Shutdown
Event Occurs Event Clears
Shutdown
PWM
Resumes
Start of
PWM Period
2010 Microchip Technology Inc.
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11.4.6
PROGRAMMABLE DEAD-BAND
DELAY MODE
FIGURE 11-13:
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
In Half-Bridge applications where all power switches
are modulated at the PWM frequency, the power
switches normally require more time to turn off than to
turn on. If both the upper and lower power switches are
switched at the same time (one turned on, and the
other turned off), both switches may be on for a short
period of time until one switch completely turns off.
During this brief interval, a very high current (shoot-
through current) will flow through both power switches,
shorting the bridge supply. To avoid this potentially
destructive shoot-through current from flowing during
switching, turning on either of the power switches is
normally delayed to allow the other switch to
completely turn off.
Period
Period
Pulse Width
(2)
(2)
P1A
td
td
P1B
(1)
(1)
(1)
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
PR2 register.
2: Output signals are shown as active-high.
In Half-Bridge mode, a digitally programmable dead-
band delay is available to avoid shoot-through current
from destroying the bridge power switches. The delay
occurs at the signal transition from the non-active state
to the active state. See Figure 11-13 for illustration. The
lower seven bits of the associated PWMxCON register
(Register 11-3) sets the delay period in terms of
microcontroller instruction cycles (TCY or 4 TOSC).
FIGURE 11-14:
EXAMPLE OF HALF-BRIDGE APPLICATIONS
V+
Standard Half-Bridge Circuit (“Push-Pull”)
FET
Driver
+
V
-
P1A
Load
FET
Driver
+
V
-
P1B
V-
DS41302D-page 104
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 11-3: PWM1CON: ENHANCED PWM CONTROL REGISTER
R/W-0
R/W-0
PDC6
R/W-0
PDC5
R/W-0
PDC4
R/W-0
PDC3
R/W-0
PDC2
R/W-0
PDC1
R/W-0
PDC0
PRSEN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
PRSEN: PWM Restart Enable bit
1= Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
away; the PWM restarts automatically
0= Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
bit 6-0
PDC<6:0>: PWM Delay Count bits
PDCn =Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should
transition active and the actual time it transitions active
TABLE 11-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
CCP1CON(1)
—
—
—
—
T1GSEL
DC1B0
—
—
P1BSEL P1ASEL ---0 --00 ---0 --00
P1M
DC1B1
CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 0-00 0000
xxxx xxxx uuuu uuuu
CCPR1L(1) Capture/Compare/PWM Register 1 Low Byte
CCPR1H(1) Capture/Compare/PWM Register 1 High Byte
xxxx xxxx uuuu uuuu
CMCON0
CMCON1
ECCPAS(1)
PWM1CON
INTCON
PIE1
CMON
—
COUT
—
CMOE
—
CMPOL
T1ACS
—
CMR
—
—
CMCH
0000 -0-0 0000 -0-0
CMHYS
T1GSS CMSYNC ---0 0-10 ---0 0-10
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 0000 0000
PRSEN
GIE
—
PDC6
PEIE
PDC5
T0IE
PDC4
INTE
—
PDC3
GPIE
CMIE
CMIF
PDC2
T0IF
—
PDC1
INTF
PDC0
GPIF
0000 0000 0000 0000
0000 0000 0000 0000
ADIE(1)
ADIF(1)
CCP1IE(1)
CCP1IF(1)
TMR2IE(1) TMR1IE -00- 0-00 -00- 0-00
TMR2IF(1) TMR1IF -00- 0-00 -00- 0-00
PIR1
—
—
—
T2CON(1)
TMR2(1)
TRISIO
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Module Register
0000 0000 0000 0000
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.
Note 1: For PIC12F615/617/HV615 only.
2010 Microchip Technology Inc.
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NOTES:
DS41302D-page 106
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.1 Configuration Bits
12.0 SPECIAL FEATURES OF THE
CPU
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
The PIC12F609/615/617/12HV609/615 has a host of
features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power-saving features and offer
code protection.
Note:
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h-
3FFFh), which can be accessed only during
programming. See Memory Programming
These features are:
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Specification
(DS41204)
for more
information.
• Watchdog Timer (WDT)
• Oscillator selection
• Sleep
• Code protection
• ID Locations
• In-Circuit Serial Programming
The PIC12F609/615/617/12HV609/615 has two timers
that offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in Reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 64 ms (nominal) on power-up only,
designed to keep the part in Reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can use the Power-
up Timer to provide at least a 64 ms Reset. With these
three functions-on-chip, most applications need no
external Reset circuitry.
The Sleep mode is designed to offer a very low-current
Power-Down mode. The user can wake-up from Sleep
through:
• External Reset
• Watchdog Timer Wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of Configuration bits are used to select
various options (see Register 12-1).
2010 Microchip Technology Inc.
DS41302D-page 107
PIC12F609/615/617/12HV609/615
REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER (ADDRESS: 2007h) FOR
PIC12F609/615/HV609/615 ONLY
U-1 U-1 U-1
U-1
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
(1)
(1)
(2)
(3)
—
—
—
BOREN1
BOREN0
IOSCFS CP
MCLRE
PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 13
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
P = Programmable
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
-n = Value at POR
bit 13-10
bit 9-8
Unimplemented: Read as ‘1’
(1)
BOREN<1:0>: Brown-out Reset Selection bits
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
0x= BOR disabled
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
IOSCFS: Internal Oscillator Frequency Select bit
1= 8 MHz
0= 4 MHz
(2)
CP: Code Protection bit
1= Program memory code protection is disabled
0= Program memory code protection is enabled
(3)
MCLRE: MCLR Pin Function Select bit
1= MCLR pin function is MCLR
0= MCLR pin function is digital input, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
FOSC<2:0>: Oscillator Selection bits
111=RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110=RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101=INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on
GP5/OSC1/CLKIN
100= INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on
GP5/OSC1/CLKIN
011=EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010=HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001= XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000= LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
DS41302D-page 108
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
REGISTER 12-2: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h) FOR PIC12F617 ONLY
U-1
—
U-1
—
R/P-1 R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
CP
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1 R/P-1
WRT1 WRT0 BOREN1 BOREN0 IOSCFS
MCLRE PWRTE WDTE FOSC2 F0SC1 F0SC0
bit 0
bit
13
bit 13-12
bit 11-10
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Program Memory Self Write Enable bits
11= Write protection off
10= 000h to 1FFh write protected, 200h to 7FFh may be modified by PMCON1 control
01= 000h to 3FFh write protected, 400h to 7FFh may be modified by PMCON1 control
00= 000h to 7FFh write protected, entire program memory is write protected.
bit 9-8
BOREN<1:0>: Brown-out Reset Enable bits
11= BOR enabled
10= BOR disabled during Sleep and enabled during operation
0X= BOR disabled
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
IOSCFS: Internal Oscillator Frequency Select
1= 8 MHz
0= 4 MHz
CP: Code Protection
1= Program memory is not code protected
0= Program memory is external read and write protected
MCLRE: MCLR Pin Function Select
1= MCLR pin is MCLR function and weak internal pull-up is enabled
0= MCLR pin is alternate function, MCLR function is internally disabled
(1)
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
FOSC<2:0>: Oscillator Selection bits
000=LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
001=XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
010=HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/AN3/T1G/OSC2/CLKOUT
011=EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN
100=INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
101=INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/
CLKIN
110=EXTRCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
111=EXTRC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
Note 1:Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT).
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘1’
0 = bit is cleared
P = Programmable
x = bit is unknown
2010 Microchip Technology Inc.
DS41302D-page 109
PIC12F609/615/617/12HV609/615
Some registers are not affected in any Reset condition;
12.2 Calibration Bits
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on:
The 8 MHz internal oscillator is factory calibrated.
These calibration values are stored in fuses located in
the Calibration Word (2008h). The Calibration Word is
not erased when using the specified bulk erase
sequence in the Memory Programming Specification
(DS41204) and thus, does not require reprogramming.
• Power-on Reset
• MCLR Reset
• MCLR Reset during Sleep
• WDT Reset
12.3 Reset
• Brown-out Reset (BOR)
WDT wake-up does not cause register resets in the
same manner as a WDT Reset since wake-up is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations, as indicated in Table 12-2. Software can use
these bits to determine the nature of the Reset. See
Table 12-5 for a full description of Reset states of all
registers.
The
PIC12F609/615/617/12HV609/615
device
differentiates between various kinds of Reset:
a) Power-on Reset (POR)
b) WDT Reset during normal operation
c) WDT Reset during Sleep
d) MCLR Reset during normal operation
e) MCLR Reset during Sleep
f) Brown-out Reset (BOR)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 12-1.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Section 16.0 “Electrical
Specifications” for pulse-width specifications.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/VPP pin
Sleep
WDT
WDT
Module
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out(1)
Reset
BOREN
S
R
OST/PWRT
OST
10-bit Ripple Counter
Chip_Reset
Q
OSC1/
CLKIN pin
PWRT
11-bit Ripple Counter
On-Chip
RC OSC
Enable PWRT
Enable OST
Note 1: Refer to the Configuration Word register (Register 12-1).
DS41302D-page 110
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.3.1
POWER-ON RESET (POR)
FIGURE 12-2:
RECOMMENDED MCLR
CIRCUIT
The on-chip POR circuit holds the chip in Reset until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply
connect the MCLR pin through a resistor to VDD. This
will eliminate external RC components usually needed
to create Power-on Reset. A maximum rise time for
VDD is required. See Section 16.0 “Electrical
Specifications” for details. If the BOR is enabled, the
maximum rise time specification does not apply. The
BOR circuitry will keep the device in Reset until VDD
reaches VBOR (see Section 12.3.4 “Brown-out Reset
(BOR)”).
VDD
PIC®
MCU
R1
1 kor greater)
R2
MCLR
100
needed with capacitor)
SW1
(optional)
C1
0.1 F
(optional, not critical)
Note:
The POR circuit does not produce an
internal Reset when VDD declines. To re-
enable the POR, VDD must reach Vss for
a minimum of 100 s.
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure proper operation. If these conditions are not
met, the device must be held in Reset until the
operating conditions are met.
12.3.3
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from an internal
RC oscillator. For more information, see Section 4.4
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
VDD to rise to an acceptable level. A Configuration bit,
PWRTE, can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should be enabled when Brown-out Reset is
enabled, although it is not required.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
12.3.2
MCLR
PIC12F609/615/617/12HV609/615 has a noise filter in
the MCLR Reset path. The filter will detect and ignore
small pulses.
The Power-up Timer delay will vary from chip-to-chip
due to:
It should be noted that a WDT Reset does not drive
MCLR pin low.
• VDD variation
Voltages applied to the MCLR pin that exceed its
specification can result in both MCLR Resets and
excessive current beyond the device specification
during the ESD event. For this reason, Microchip
recommends that the MCLR pin no longer be tied
directly to VDD. The use of an RC network, as shown in
Figure 12-2, is suggested.
• Temperature variation
• Process variation
See DC parameters for details (Section 16.0
“Electrical Specifications”).
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the GP3/MCLR pin
becomes an external Reset input. In this mode, the
GP3/MCLR pin has a weak pull-up to VDD.
Note:
Voltage spikes below VSS at the MCLR
pin, inducing currents greater than 80 mA,
may cause latch-up. Thus, a series resis-
tor of 50-100 should be used when
applying a “low” level to the MCLR pin,
rather than pulling this pin directly to VSS.
2010 Microchip Technology Inc.
DS41302D-page 111
PIC12F609/615/617/12HV609/615
On any Reset (Power-on, Brown-out Reset, Watchdog
timer, etc.), the chip will remain in Reset until VDD rises
above VBOR (see Figure 12-3). If enabled, the Power-
up Timer will be invoked by the Reset and keep the chip
in Reset an additional 64 ms.
12.3.4
BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register select one of three BOR modes. One
mode has been added to allow control of the BOR
enable for lower current during Sleep. By selecting
BOREN<1:0> = 10, the BOR is automatically disabled
in Sleep to conserve power and enabled on wake-up.
See Register 12-1 for the Configuration Word
definition.
Note:
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word
register.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
A brown-out occurs when VDD falls below VBOR for
greater than parameter TBOR (see Section 16.0
“Electrical Specifications”). The brown-out condition
will reset the device. This will occur regardless of VDD
slew rate. A Brown-out Reset may not occur if VDD falls
below VBOR for less than parameter TBOR.
FIGURE 12-3:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
64 ms
VDD
VBOR
Internal
Reset
< 64 ms
(1)
64 ms
VDD
VBOR
Internal
Reset
(1)
64 ms
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
DS41302D-page 112
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.3.5
TIME-OUT SEQUENCE
12.3.6
POWER CONTROL (PCON)
REGISTER
On power-up, the time-out sequence is as follows:
• PWRT time-out is invoked after POR has expired.
The Power Control register PCON (address 8Eh) has
two Status bits to indicate what type of Reset occurred
last.
• OST is activated after the PWRT time-out has
expired.
Bit 0 is BOR (Brown-out). BOR is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOR = 0, indicating that
a Brown-out has occurred. The BOR Status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (BOREN<1:0> = 00in the
Configuration Word register).
The total time-out will vary based on oscillator
configuration and PWRTE bit status. For example, in EC
mode with PWRTE bit erased (PWRT disabled), there
will be no time-out at all. Figure 12-4, Figure 12-5 and
Figure 12-6 depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 12-5). This is useful for testing purposes or
to synchronize more than one PIC12F609/615/617/
12HV609/615 device operating in parallel.
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent Reset, if POR is ‘0’, it will indicate that a Power-
on Reset has occurred (i.e., VDD may have gone too
low).
Table 12-6 shows the Reset conditions for some
special registers, while Table 12-5 shows the Reset
conditions for all the registers.
For more information, see Section 12.3.4 “Brown-out
Reset (BOR)”.
TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
Wake-up from
Oscillator Configuration
Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024 •
TOSC
1024 • TOSC
TPWRT + 1024 •
TOSC
1024 • TOSC
1024 • TOSC
—
RC, EC, INTOSC
TPWRT
—
TPWRT
—
TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
u
u
u
x
0
u
u
1
1
0
0
1
1
u
0
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
u
u
u
u
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during Sleep
Legend: u= unchanged, x= unknown
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Value on
Value on
all other
Resets(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOR
PCON
—
—
—
—
—
—
Z
POR
DC
BOR ---- --qq ---- --uu
0001 1xxx 000q quuu
STATUS
IRP
RP1
RP0
TO
PD
C
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.
Shaded cells are not used by BOR.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2010 Microchip Technology Inc.
DS41302D-page 113
PIC12F609/615/617/12HV609/615
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
OST Time-out
Internal Reset
TOST
DS41302D-page 114
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (PIC12F609/HV609)
Wake-up from Sleep through
Interrupt
Wake-up from Sleep through
WDT Time-out
MCLR Reset
WDT Reset
Power-on
Reset
Register
Address
Brown-out Reset(1)
W
—
00h/80h
01h
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
---0 0000
0000 0000
----- 0--0
xxxx xxxx
xxxx xxxx
0000 0000
0-00 0000
0000 -0-0
---0 0-10
1111 1111
--11 1111
----- 0--0
---- --0x
---0 0000
--11 -111
--00 0000
---- 1-11
uuuu uuuu
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu(4)
uuuu uuuu
--u0 u000
---0 0000
0000 0000
---- 0--0
uuuu uuuu
uuuu uuuu
uuuu uuuu
0-00 0000
0000 -0-0
---0 0-10
1111 1111
--11 1111
---- 0--0
---- --uu(1, 5)
---u uuuu
--11 -111
--00 0000
---- 1-11
uuuu uuuu
uuuu uuuu
uuuu uuuu
PC + 1(3)
INDF
TMR0
PCL
02h/82h
03h/83h
04h/84h
05h
STATUS
FSR
uuuq quuu(4)
uuuu uuuu
--uu uuuu
---u uuuu
uuuu uuuu(2)
---- u--u(2)
uuuu uuuu
uuuu uuuu
-uuu uuuu
u-uu uuuu
uuuu -u-u
---u u-qu
uuuu uuuu
--uu uuuu
---- u--u
---- --uu
---u uuuu
--uu -uuu
--uu uuuu
---- q-qq
GPIO
PCLATH
INTCON
PIR1
0Ah/8Ah
0Bh/8Bh
0Ch
TMR1L
TMR1H
T1CON
VRCON
CMCON0
CMCON1
OPTION_REG
TRISIO
PIE1
0Eh
0Fh
10h
19h
1Ah
1Ch
81h
85h
8Ch
PCON
8Eh
OSCTUNE
WPU
90h
95h
IOC
96h
ANSEL
9Fh
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 12-6 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
2010 Microchip Technology Inc.
DS41302D-page 115
PIC12F609/615/617/12HV609/615
TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (PIC12F615/617/HV615)
Wake-up from Sleep through
MCLR Reset
WDT Reset
Brown-out Reset
Interrupt
Wake-up from Sleep through
WDT Time-out
Register
Address
Power-on Reset
(1)
W
—
00h/80h
01h
xxxx xxxx
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--x0 x000
---0 0000
0000 0000
-000 0-00
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
0000 0000
0-00 0000
0000 -0-0
---0 0-10
xxxx xxxx
00-0 0000
1111 1111
--11 1111
-00- 0-00
---- --0x
---0 0000
1111 1111
---0 --00
--11 -111
--00 0000
---- -000
---- ----
0000 0000
uuuu uuuu
xxxx xxxx
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
INDF
TMR0
PCL
(3)
02h/82h
03h/83h
04h/84h
05h
PC + 1
(4)
(4)
STATUS
FSR
000q quuu
uuuu uuuu
--u0 u000
---0 0000
0000 0000
-000 0-00
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0-00 0000
0000 0000
0000 0000
0-00 0000
0000 -0-0
---0 0-10
uuuu uuuu
00-0 0000
1111 1111
--11 1111
-00- 0-00
uuuq quuu
uuuu uuuu
--uu uuuu
---u uuuu
GPIO
PCLATH
INTCON
PIR1
0Ah/8Ah
0Bh/8Bh
0Ch
(2)
uuuu uuuu
(2)
-uuu u-uu
TMR1L
TMR1H
T1CON
0Eh
uuuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu uuuu
uuuu uuuu
u-uu uuuu
uuuu -u-u
---u u-qu
uuuu uuuu
uu-u uuuu
uuuu uuuu
--uu uuuu
-uu- u-uu
---- --uu
---u uuuu
1111 1111
---u --uu
--uu -uuu
--uu uuuu
---- -uuu
---- ----
uuuu uuuu
0Fh
10h
(1)
TMR2
11h
(1)
T2CON
12h
(1)
(1)
CCPR1L
13h
CCPR1H
14h
(1)
CCP1CON
15h
(1)
PWM1CON
16h
(1)
ECCPAS
17h
VRCON
19h
CMCON0
CMCON1
1Ah
1Ch
(1)
ADRESH
1Eh
(1)
ADCON0
1Fh
OPTION_REG
TRISIO
PIE1
81h
85h
8Ch
(1, 5)
PCON
8Eh
---- --uu
OSCTUNE
PR2
90h
---u uuuu
1111 1111
---0 --00
--11 -111
--00 0000
---- -000
---- ----
0000 0000
92h
APFCON
WPU
93h
95h
IOC
96h
(6)
PMCON1
98h
(6)
PMCON2
99h
(6)
PMADRL
9Ah
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 12-6 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: For PIC12F617 only.
DS41302D-page 116
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 12-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)(PIC12F615/617/HV615)
Wake-up from Sleep through
MCLR Reset
Interrupt
Register
Address
Power-on Reset
WDT Reset (Continued)
Wake-up from Sleep through
WDT Time-out (Continued)
(1)
Brown-out Reset
(6)
PMADRH
9Bh
9Ch
9Dh
9Eh
9Fh
---- -000
0000 0000
--00 0000
xxxx xxxx
-000 1111
---- -000
0000 0000
--00 0000
uuuu uuuu
-000 1111
---- -uuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu qqqq
(6)
(6)
PMDATL
PMDATH
(1)
ADRESL
ANSEL
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 12-6 for Reset value for specific condition.
5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.
6: For PIC12F617 only.
TABLE 12-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
Status
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
---- --0x
---- --uu
MCLR Reset during normal operation
---- --uu
MCLR Reset during Sleep
WDT Reset
000h
000h
0001 0uuu
0000 uuuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --uu
---- --uu
---- --10
---- --uu
WDT Wake-up
PC + 1
000h
PC + 1(1)
Brown-out Reset
Interrupt Wake-up from Sleep
Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with
the interrupt vector (0004h) after execution of PC + 1.
2010 Microchip Technology Inc.
DS41302D-page 117
PIC12F609/615/617/12HV609/615
Figure 12-8). The latency is the same for one or two-
12.4 Interrupts
cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
The PIC12F609/615/617/12HV609/615 has 8 sources
of interrupt:
• External Interrupt GP2/INT
• Timer0 Overflow Interrupt
• GPIO Change Interrupts
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
• Comparator Interrupt
• A/D Interrupt (PIC12F615/617/HV615 only)
• Timer1 Overflow Interrupt
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
• Timer2 Match Interrupt (PIC12F615/617/HV615
only)
• Enhanced CCP Interrupt (PIC12F615/617/HV615
only)
• Flash Memory Self Write (PIC12F617 only)
The Interrupt Control register (INTCON) and Peripheral
Interrupt Request Register 1 (PIR1) record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
For additional information on Timer1, Timer2,
comparators, ADC, Enhanced CCP modules, refer to
the respective peripheral section.
12.4.1
GP2/INT INTERRUPT
The Global Interrupt Enable bit, GIE of the INTCON
register, enables (if set) all unmasked interrupts, or
disables (if cleared) all interrupts. Individual interrupts
can be disabled through their corresponding enable
bits in the INTCON register and PIE1 register. GIE is
cleared on Reset.
The external interrupt on the GP2/INT pin is edge-
triggered; either on the rising edge if the INTEDG bit of
the OPTION register is set, or the falling edge, if the
INTEDG bit is clear. When a valid edge appears on the
GP2/INT pin, the INTF bit of the INTCON register is set.
This interrupt can be disabled by clearing the INTE
control bit of the INTCON register. The INTF bit must
be cleared by software in the Interrupt Service Routine
before re-enabling this interrupt. The GP2/INT interrupt
can wake-up the processor from Sleep, if the INTE bit
was set prior to going into Sleep. See Section 12.7
“Power-Down Mode (Sleep)” for details on Sleep and
Figure 12-9 for timing of wake-up from Sleep through
GP2/INT interrupt.
When an interrupt is serviced, the following actions
occur automatically:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
Note:
The ANSEL register must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’ and cannot generate an interrupt.
• INT Pin Interrupt
• GPIO Change Interrupt
• Timer0 Overflow Interrupt
The peripheral interrupt flags are contained in the
special register, PIR1. The corresponding interrupt
enable bit is contained in special register, PIE1.
The following interrupt flags are contained in the PIR1
register:
• A/D Interrupt
• Comparator Interrupt
• Timer1 Overflow Interrupt
• Timer2 Match Interrupt
• Enhanced CCP Interrupt
For external interrupt events, such as the INT pin or
GPIO change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
DS41302D-page 118
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.4.2
TIMER0 INTERRUPT
12.4.3
GPIO INTERRUPT-ON-CHANGE
An overflow (FFh 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 6.0 “Timer0 Module”
for operation of the Timer0 module.
An input change on GPIO sets the GPIF bit of the
INTCON register. The interrupt can be enabled/
disabled by setting/clearing the GPIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOC register.
Note:
If a change on the I/O pin should occur
when any GPIO operation is being
executed, then the GPIF interrupt flag may
not get set.
FIGURE 12-7:
INTERRUPT LOGIC
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
(1)
Wake-up (If in Sleep mode)
T0IF
T0IE
TMR2IF
TMR2IE
only)
(615/617
INTF
INTE
GPIF
Interrupt to CPU
TMR1IF
TMR1IE
GPIE
CMIF
CMIE
PEIE
GIE
ADIF
ADIE
(615/617 only)
CCP1IF
CCP1IE
(615/617 only)
Note 1: Some peripherals depend upon the system clock for
operation. Since the system clock is suspended during Sleep, only
those peripherals which do not depend upon the system clock will wake
the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”.
2010 Microchip Technology Inc.
DS41302D-page 119
PIC12F609/615/617/12HV609/615
FIGURE 12-8:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(2)
(5)
Interrupt Latency
INTF flag
(INTCON reg.)
GIE bit
(INTCON reg.)
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTOSC and RC Oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 16.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 12-7: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Value on
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
INTCON GIE
PEIE
—
ADIF(1) CCP1IF(1)
ADIE(1) CCP1IE(1)
T0IE
INTE
IOC4
—
GPIE
IOC3
CMIF
CMIE
T0IF
IOC2
—
INTF
IOC1
GPIF
IOC0
0000 0000 0000 0000
--00 0000 --00 0000
IOC
—
—
—
IOC5
PIR1
PIE1
TMR2IF(1) TMR1IF -00- 0-00 -000 0-00
TMR2IE(1) TMR1IE -00- 0-00 -000 0-00
—
—
Legend: x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition.
Shaded cells are not used by the interrupt module.
Note 1: PIC12F615/617/HV615 only.
DS41302D-page 120
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.5 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
holding
registers
W_TEMP
and
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-3). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 12-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
Note:
The PIC12F609/615/617/12HV609/615
does not require saving the PCLATH.
However, if computed GOTOs are used in
both the ISR and the main code, the
PCLATH must be saved and restored in
the ISR.
EXAMPLE 12-1:
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
W_TEMP
STATUS,W
;Copy W to TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Save status to bank zero STATUS_TEMP register
MOVWF
:
STATUS_TEMP
:(ISR)
:
;Insert user code here
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
12.6.1
WDT PERIOD
12.6 Watchdog Timer (WDT)
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEPinstruction). During normal oper-
ation, a WDT time out generates a device Reset. If the
device is in Sleep mode, a WDT time out causes the
device to wake-up and continue with normal operation.
The WDT can be permanently disabled by program-
ming the Configuration bit, WDTE, as clear
(Section 12.1 “Configuration Bits”).
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
2010 Microchip Technology Inc.
DS41302D-page 121
PIC12F609/615/617/12HV609/615
12.6.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst-
case conditions (i.e., VDD = Min., Temperature = Max.,
Max. WDT prescaler) it may take several seconds
before a WDT time out occurs.
FIGURE 12-2:
WATCHDOG TIMER BLOCK DIAGRAM
CLKOUT
(= FOSC/4)
Data Bus
8
0
1
1
0
SYNC 2
Cycles
TMR0
T0CKI
pin
0
1
Set Flag bit T0IF
on Overflow
T0CS
T0SE
8-bit
Prescaler
PSA
8
PSA
3
1
0
PS<2:0>
WDT
Time-Out
Watchdog
Timer
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
TABLE 12-8: WDT STATUS
Conditions
WDT
WDTE = 0
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Cleared until the end of OST
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Value on
all other
Resets
Value on
POR, BOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OPTION_REG GPPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
CONFIG
IOSCFS
CP
MCLRE PWRTE WDTE
FOSC2 FOSC1
FOSC0
—
—
Legend:
Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of all Configuration Word register bits.
DS41302D-page 122
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
When the SLEEPinstruction is being executed, the next
12.7 Power-Down Mode (Sleep)
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
The Power-Down mode is entered by executing a
SLEEPinstruction.
If the Watchdog Timer is enabled:
• WDT will be cleared but keeps running.
• PD bit in the STATUS register is cleared.
• TO bit is set.
• Oscillator driver is turned off.
• I/O ports maintain the status they had before SLEEP
was executed (driving high, low or high-impedance).
Note:
If the global interrupts are disabled (GIE is
cleared) and any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from Sleep.
For lowest current consumption in this mode, all I/O pins
should be either at VDD or VSS, with no external circuitry
drawing current from the I/O pin and the comparators
and CVREF should be disabled. I/O pins that are high-
impedance inputs should be pulled high or low externally
to avoid switching currents caused by floating inputs.
The T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip pull-
ups on GPIO should be considered.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
12.7.2
WAKE-UP USING INTERRUPTS
The MCLR pin must be at a logic high level.
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
Note:
It should be noted that a Reset generated
by a WDT time-out does not drive MCLR
pin low.
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
12.7.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the
following events:
1. External Reset input on MCLR pin.
• If the interrupt occurs during or after the
execution of a SLEEPinstruction, the device will
Immediately wake-up from Sleep. The SLEEP
instruction is executed. Therefore, the WDT and
WDT prescaler and postscaler (if enabled) will be
cleared, the TO bit will be set and the PD bit will
be cleared.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from GP2/INT pin, GPIO change or a
peripheral interrupt.
The first event will cause a device Reset. The two latter
events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device Reset.
The PD bit, which is set on power-up, is cleared when
Sleep is invoked. TO bit is cleared if WDT wake-up
occurred.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from Sleep:
To ensure that the WDT is cleared, a CLRWDTinstruction
should be executed before a SLEEP instruction. See
Figure 12-9 for more details.
1. Timer1 interrupt. Timer1 must be operating as
an asynchronous counter.
2. ECCP Capture mode interrupt.
3. A/D conversion (when A/D clock source is RC).
4. Comparator output changes state.
5. Interrupt-on-change.
6. External Interrupt from INT pin.
Other peripherals cannot generate interrupts since
during Sleep, no on-chip clocks are present.
2010 Microchip Technology Inc.
DS41302D-page 123
PIC12F609/615/617/12HV609/615
FIGURE 12-9:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
(2)
TOST
INTF flag
(INTCON reg.)
Interrupt Latency(3)
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(PC – 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes.
3: GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP™ for verification purposes.
Note:
The entire Flash program memory will be
erased when the code protection is turned
off. See the MemoryProgramming
Specification
(DS41204)
for
more
information.
12.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
DS41302D-page 124
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
12.10 In-Circuit Serial Programming™
12.11 In-Circuit Debugger
ThePIC12F609/615/617/12HV609/615
microcontrollers can be serially programmed while in
the end application circuit. This is simply done with five
connections for:
Since in-circuit debugging requires access to three pins,
MPLAB® ICD 2 development with an 14-pin device is
not practical. A special 28-pin PIC12F609/615/617/
12HV609/615 ICD device is used with MPLAB ICD 2 to
provide separate clock, data and MCLR pins and frees
all normally available pins to the user.
• clock
• data
A special debugging adapter allows the ICD device to
be used in place of a PIC12F609/615/617/12HV609/
615 device. The debugging adapter is the only source
of the ICD device.
• power
• ground
• programming voltage
This allows customers to manufacture boards with
unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
When the ICD pin on the PIC12F609/615/617/
12HV609/615 ICD device is held low, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB
ICD 2. When the microcontroller has this feature
enabled, some of the resources are not available for
general use. Table 12-10 shows which features are
consumed by the background debugger.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH. See the Memory
Programming Specification (DS41284) for more
information. GP0 becomes the programming data and
GP1 becomes the programming clock. Both GP0 and
GP1 are Schmitt Trigger inputs in Program/Verify
mode.
TABLE 12-10: DEBUGGER RESOURCES
Resource
Description
I/O pins
Stack
ICDCLK, ICDDATA
1 level
A typical In-Circuit Serial Programming connection is
shown in Figure 12-10.
Program Memory Address 0h must be NOP
700h-7FFh
FIGURE 12-10:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
For more information, see “MPLAB® ICD 2 In-Circuit
Debugger User’s Guide” (DS51331), available on
Microchip’s web site (www.microchip.com).
To Normal
Connections
FIGURE 12-11:
28-Pin PDIP
28 PIN ICD PINOUT
External
Connector
Signals
PIC12F617/
PIC12F615/12HV615
*
PIC12F609/12HV609
In-Circuit Debug Device
+5V
0V
VDD
VSS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CS0
GND
RA0
RA1
SHUNTEN
RA2
RC0
RC1
RC2
NC
VPP
MCLR/VPP/GP3/RA3
2
3
CS1
GP1
GP0
CLK
4
CS2
Data I/O
5
RA5
6
RA4
7
RA3
8
RC5
9
RC4
*
*
*
10
11
12
13
14
RC3
NC
ICDCLK
ICDMCLR
ICDDATA
NC
NC
NC
NC
To Normal
Connections
ICD
* Isolation devices (as required)
Note:
To erase the device VDD must be above
the Bulk Erase VDD minimum given in the
Memory
Programming
Specification
(DS41284)
2010 Microchip Technology Inc.
DS41302D-page 125
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 126
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
An external current limiting resistor, RSER, located
13.0 VOLTAGE REGULATOR
between the unregulated supply, VUNREG, and the VDD
pin, drops the difference in voltage between VUNREG
and VDD. RSER must be between RMAX and RMIN as
defined by Equation 13-1.
The PIC12HV609/HV615 devices include a permanent
internal 5 volt (nominal) shunt regulator in parallel with
the VDD pin. This eliminates the need for an external
voltage regulator in systems sourced by an
unregulated supply. All external devices connected
directly to the VDD pin will share the regulated supply
voltage and contribute to the total VDD supply current
(ILOAD).
EQUATION 13-1: RSER LIMITING RESISTOR
(VUMIN - 5V)
RMAX =
1.05 • (4 MA + ILOAD)
13.1 Regulator Operation
(VUMAX - 5V)
RMIN =
A shunt regulator generates a specific supply voltage
by creating a voltage drop across a pass resistor RSER.
The voltage at the VDD pin of the microcontroller is
monitored and compared to an internal voltage refer-
ence. The current through the resistor is then adjusted,
based on the result of the comparison, to produce a
voltage drop equal to the difference between the supply
voltage VUNREG and the VDD of the microcontroller.
See Figure 13-1 for voltage regulator schematic.
0.95 • (50 MA)
Where:
RMAX = maximum value of RSER (ohms)
RMIN = minimum value of RSER (ohms)
VUMIN = minimum value of VUNREG
VUMAX = maximum value of VUNREG
VDD
= regulated voltage (5V nominal)
FIGURE 13-1:
VOLTAGE REGULATOR
ILOAD = maximum expected load current in mA
including I/O pin currents and external
circuits connected to VDD.
VUNREG
ILOAD
RSER
ISUPPLY
1.05 = compensation for +5% tolerance of RSER
0.95 = compensation for -5% tolerance of RSER
VDD
ISHUNT
CBYPASS
Feedback
13.2 Regulator Considerations
VSS
The supply voltage VUNREG and load current are not
constant. Therefore, the current range of the regulator
is limited. Selecting a value for RSER must take these
three factors into consideration.
Device
Since the regulator uses the band gap voltage as the
regulated voltage reference, this voltage reference is
permanently enabled in the PIC12HV609/HV615
devices.
The shunt regulator will still consume current when
below operating voltage range for the shunt regulator.
13.3 Design Considerations
For more information on using the shunt regulator and
managing current load, see Application Note AN1035,
“Designing with HV Microcontrollers” (DS01035).
2010 Microchip Technology Inc.
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PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 128
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 14-1: OPCODE FIELD
14.0 INSTRUCTION SET SUMMARY
DESCRIPTIONS
The PIC12F609/615/617/12HV609/615 instruction set
is highly orthogonal and is comprised of three basic
categories:
Field
Description
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
• Byte-oriented operations
• Bit-oriented operations
Bit address within an 8-bit file register
Literal field, constant data or label
• Literal and control operations
k
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type and one or
more operands, which further specify the operation of
the instruction. The formats for each of the categories
is presented in Figure 14-1, while the various opcode
fields are summarized in Table 14-1.
x
Don’t care location (= 0or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
Table 14-2 lists the instructions recognized by the
MPASMTM assembler.
PC
TO
C
Program Counter
Time-out bit
Carry bit
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
DC
Z
Digit carry bit
Zero bit
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
PD
Power-down bit
FIGURE 14-1:
GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
For literal and control operations, ‘k’ represents an
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
8-bit or 11-bit constant, or literal value.
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 s. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
Literal and control operations
General
13
8
7
0
0
OPCODE
k (literal)
14.1 Read-Modify-Write Operations
k = 8-bit immediate value
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (RMW)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
For example, a CLRF GPIOinstruction will read GPIO,
clear all the data bits, then write the result back to
GPIO. This example would have the unintended
consequence of clearing the condition that set the
GPIF flag.
2010 Microchip Technology Inc.
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TABLE 14-2: PIC12F609/615/617/12HV609/615 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
1, 2
1, 2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1, 2
1, 2
1, 2, 3
1, 2
1, 2, 3
1, 2
1, 2
Z
Z
Z
Move W to f
No Operation
–
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1, 2
1, 2
1, 2
1, 2
1, 2
00 0010 dfff ffff C, DC, Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
1, 2
1, 2
3
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
–
k
k
k
–
k
–
–
k
k
Add literal and W
AND literal with W
Call Subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C, DC, Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO, PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO, PD
11 110x kkkk kkkk C, DC, Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41302D-page 130
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
14.2 Instruction Descriptions
BCF
Bit Clear f
ADDLW
Add literal and W
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
0 b 7
Operands:
Operation:
Status Affected:
Description:
(W) + k (W)
C, DC, Z
Operation:
0 (f<b>)
Status Affected:
Description:
None
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the
W register.
Bit ‘b’ in register ‘f’ is cleared.
BSF
Bit Set f
ADDWF
Add W and f
Syntax:
[ label ] BSF f,b
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
0 b 7
Operands:
0 f 127
d 0,1
Operation:
1 (f<b>)
Operation:
(W) + (f) (destination)
Status Affected:
Description:
None
Status Affected: C, DC, Z
Bit ‘b’ in register ‘f’ is set.
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.
BTFSC
Bit Test f, Skip if Clear
ANDLW
AND literal with W
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
0 f 127
0 b 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
skip if (f<b>) = 0
Z
Status Affected: None
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is discarded, and a NOP
is executed instead, making this a
two-cycle instruction.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF f,d
Operands:
0 f 127
d 0,1
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
2010 Microchip Technology Inc.
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CLRWDT
Clear Watchdog Timer
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] BTFSS f,b
Operands:
Operation:
None
Operands:
0 f 127
0 b < 7
00h WDT
0 WDT prescaler,
1 TO
Operation:
skip if (f<b>) = 1
Status Affected: None
1 PD
Description:
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
Status Affected: TO, PD
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction.
Status bits TO and PD are set.
CALL
Call Subroutine
COMF
Complement f
Syntax:
[ label ] CALL k
0 k 2047
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<4:3>) PC<12:11>
Operation:
(f) (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’,
the result is stored back in
register ‘f’.
Description:
Call Subroutine. First, return
address (PC + 1) is pushed onto
the stack. The eleven-bit
immediate address is loaded into
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two-cycle instruction.
CLRF
Clear f
DECF
Decrement f
Syntax:
[ label ] CLRF
0 f 127
f
Syntax:
[ label ] DECF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are
cleared and the Z bit is set.
Decrement register ‘f’. If ‘d’ is ‘0’,
the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
DS41302D-page 132
2010 Microchip Technology Inc.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description:
The contents of register ‘f’ are
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOPis
executed instead, making it a
two-cycle instruction.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOPis executed
instead, making it a two-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO k
0 k 2047
Syntax:
[ label ] IORLW k
0 k 255
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<4:3> PC<12:11>
(W) .OR. k (W)
Z
Status Affected: None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a
two-cycle instruction.
IORWF
Inclusive OR W with f
INCF
Increment f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] INCF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(W) .OR. (f) (destination)
Operation:
(f) + 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
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MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
MOVF
Move f
Syntax:
f
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
Operation:
Status Affected:
Description:
0 f 127
d [0,1]
Operation:
(f) (dest)
None
Status Affected:
Description:
Z
Move data from W register to
register ‘f’.
The contents of register ‘f’ is
moved to a destination dependent
upon the status of ‘d’. If d = 0,
destination is W register. If d = 1,
the destination is file register ‘f’
itself. d = 1is useful to test a file
register since Status flag Z is
affected.
Words:
1
1
Cycles:
Example:
MOVW
F
OPTION
Before Instruction
OPTION = 0xFF
Words:
1
1
W
=
0x4F
After Instruction
Cycles:
Example:
OPTION = 0x4F
W
MOVF
FSR, 0
=
0x4F
After Instruction
W
=
value in FSR
register
Z
=
1
MOVLW
Syntax:
Move literal to W
NOP
No Operation
[ label ] MOVLW k
0 k 255
Syntax:
[ label ] NOP
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
Words:
None
k (W)
No operation
Status Affected: None
None
Description:
The eight-bit literal ‘k’ is loaded into
W register. The “don’t cares” will
assemble as ‘0’s.
No operation.
1
Cycles:
1
Words:
1
1
NOP
Example:
Cycles:
Example:
MOVLW
0x5A
After Instruction
W
=
0x5A
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RETFIE
Return from Interrupt
[ label ] RETFIE
None
RETLW
Return with literal in W
[ label ] RETLW k
0 k 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
TOS PC,
1 GIE
k (W);
TOS PC
Status Affected:
Description:
None
Status Affected:
Description:
None
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS)
is loaded in the PC. Interrupts are
enabled by setting Global
Interrupt Enable bit, GIE (INT-
CON<7>). This is a two-cycle
instruction.
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words:
1
2
Cycles:
Example:
Words:
1
CALL TABLE;W contains
Cycles:
Example:
2
;table offset
;value
RETFIE
GOTO DONE
•
•
ADDWF PC ;W = offset
RETLW k1 ;Begin table
After Interrupt
PC = TOS
TABLE
GIE =
1
RETLW k2
;
•
•
•
RETLW kn ;End of table
DONE
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
TOS PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
2010 Microchip Technology Inc.
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RLF
Rotate Left f through Carry
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
See description below
C
Status Affected:
Description:
0 PD
The contents of register ‘f’ are
rotated one bit to the left through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD
is cleared. Time-out Status bit,
TO is set. Watchdog Timer and
its prescaler are cleared.
The processor is put into Sleep
mode with the oscillator stopped.
C
Register f
Words:
1
1
Cycles:
Example:
RLF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW k
0 k 255
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Operands:
0 f 127
d [0,1]
k - (W) W)
Operation:
See description below
C
Status Affected: C, DC, Z
Status Affected:
Description:
Description: The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
The contents of register ‘f’ are
rotated one bit to the right through
the Carry flag. If ‘d’ is ‘0’, the
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed
back in register ‘f’.
Result
Condition
C = 0
W k
C
Register f
C = 1
W k
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
DS41302D-page 136
2010 Microchip Technology Inc.
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SUBWF
Subtract W from f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SUBWF f,d
Syntax:
[ label ] XORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - (W) destination)
Operation:
(W) .XOR. (f) destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
Subtract (2’s complement method)
Exclusive OR the contents of the
W register with register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
W register from register ‘f’. If ‘d’ is
‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
C = 0
W f
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0 f 127
d [0,1]
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If ‘d’ is
‘0’, the result is placed in the W
register. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
XORLW
Exclusive OR literal with W
Syntax:
[ label ] XORLW k
0 k 255
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
2010 Microchip Technology Inc.
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PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 138
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
15.1 MPLAB Integrated Development
Environment Software
15.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2010 Microchip Technology Inc.
DS41302D-page 139
PIC12F609/615/617/12HV609/615
15.2 MPLAB C Compilers for Various
Device Families
15.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
15.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
15.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
15.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41302D-page 140
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
15.7 MPLAB SIM Software Simulator
15.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
15.10 PICkit 3 In-Circuit Debugger/
Programmer and
15.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
2010 Microchip Technology Inc.
DS41302D-page 141
PIC12F609/615/617/12HV609/615
15.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
15.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
15.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41302D-page 142
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias..........................................................................................................-40° to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V
Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin ...................................................................................................................... 95 mA
Maximum current into VDD pin ......................................................................................................................... 95 mA
Input clamp current, IIK (VI < 0 or VI > VDD)20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Maximum current sunk by GPIO...................................................................................................................... 90 mA
Maximum current sourced GPIO...................................................................................................................... 90 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x
IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2010 Microchip Technology Inc.
DS41302D-page 143
PIC12F609/615/617/12HV609/615
FIGURE 16-1:
PIC12F609/615/617 VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0
8
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 16-2:
PIC12HV609/615 VOLTAGE-FREQUENCY GRAPH,
-40°C TA +125°C
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0
8
10
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS41302D-page 144
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.1 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial)
PIC12F609/615/617/12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
DC CHARACTERISTICS
Param
Sym
Characteristic
Min Typ† Max Units
Conditions
No.
VDD
Supply Voltage
D001
PIC12F609/615/617
PIC12HV609/615
PIC12F609/615/617
PIC12HV609/615
PIC12F609/615/617
PIC12HV609/615
PIC12F609/615/617
PIC12HV609/615
2.0
2.0
2.0
2.0
3.0
3.0
4.5
4.5
1.5
—
—
—
—
—
—
—
—
—
5.5
V
V
V
V
V
V
V
V
V
FOSC < = 4 MHz
(2)
D001
—
FOSC < = 4 MHz
FOSC < = 8 MHz
FOSC < = 8 MHz
FOSC < = 10 MHz
FOSC < = 10 MHz
FOSC < = 20 MHz
FOSC < = 20 MHz
Device in Sleep mode
D001B
D001B
D001C
D001C
D001D
D001D
5.5
(2)
—
5.5
(2)
—
5.5
(2)
—
D002* VDR
RAM Data Retention
Voltage(1)
—
D003 VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
—
V
See Section 12.3.1 “Power-on Reset
(POR)” for details.
D004* SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
—
V/ms See Section 12.3.1 “Power-on Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: User defined. Voltage across the shunt regulator should not exceed 5V.
2010 Microchip Technology Inc.
DS41302D-page 145
PIC12F609/615/617/12HV609/615
16.2 DC Characteristics: PIC12F609/615/617-I (Industrial)
PIC12F609/615/617-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Units
Device Characteristics
Min
Typ†
Max
No.
VDD
Note
13
19
25
D010
Supply Current (IDD)(1, 2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
A
A
A
mA
A
A
A
A
A
mA
A
A
mA
A
mA
mA
A
A
A
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
FOSC = 32 kHz
LP Oscillator mode
PIC12F609/615/617
29
32
51
D011*
D012
D013*
D014
D016*
D017
D018
D019
135
185
300
240
360
0.66
75
225
285
405
360
505
1.0
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
110
255
530
255
475
1.0
FOSC = 1 MHz
EC Oscillator mode
155
345
185
325
0.665
245
360
FOSC = 4 MHz
EC Oscillator mode
340
485
FOSC = 4 MHz
INTOSC mode
0.620 0.845
395 550
0.620 0.850
FOSC = 8 MHz
INTOSC mode
1.2
175
285
530
2.2
1.6
235
390
750
3.1
FOSC = 4 MHz
EXTRC mode(3)
FOSC = 20 MHz
HS Oscillator mode
—
2.8
3.35
mA
5.0
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-
rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current con-
sumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in KOhms (K
DS41302D-page 146
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.3 DC Characteristics: PIC12HV609/615-I (Industrial)
PIC12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Units
Device Characteristics
Min
Typ†
Max
No.
VDD
Note
160
240
280
270
400
520
380
575
0.875
215
375
570
330
550
0.85
310
500
0.74
460
0.75
1.2
230
310
400
380
560
780
540
810
1.3
D010
Supply Current (IDD)(1, 2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
A
A
A
mA
A
A
A
A
A
mA
A
A
mA
A
mA
mA
A
A
mA
mA
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
4.5
FOSC = 32 kHz
LP Oscillator mode
PIC12HV609/615
D011*
D012
D013*
D014
D016*
D017
D018
D019
FOSC = 1 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
310
565
870
475
800
1.2
FOSC = 1 MHz
EC Oscillator mode
FOSC = 4 MHz
EC Oscillator mode
435
700
1.1
FOSC = 4 MHz
INTOSC mode
650
1.1
FOSC = 8 MHz
INTOSC mode
1.6
320
510
0.770
2.5
465
750
1.0
FOSC = 4 MHz
EXTRC mode(3)
3.4
FOSC = 20 MHz
HS Oscillator mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can
be extended by the formula IR = VDD/2REXT (mA) with REXT in k
2010 Microchip Technology Inc.
DS41302D-page 147
PIC12F609/615/617/12HV609/615
16.4 DC Characteristics: PIC12F609/615/617 - I (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
VDD
Note
D020
D021
Power-down Base
Current (IPD)(2)
—
0.05
0.9
A
2.0
WDT, BOR, Comparator, VREF and
T1OSC disabled
—
—
0.15
0.35
150
1.2
1.5
500
A
A
nA
3.0
5.0
3.0
PIC12F609/615/617
-40°C TA +25°C for industrial
WDT Current(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.5
2.5
9.5
5.0
6.0
50
1.5
4.0
17
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
D022
D023
BOR Current(1)
12
60
65
75
40
60
105
50
80
130
10
12
14
1.6
1.9
Comparator Current(1), single
comparator enabled
55
60
D024
D025*
D026
D027
30
CVREF Current(1) (high range)
CVREF Current(1) (low range)
T1OSC Current(1), 32.768 kHz
45
75
39
59
98
5.5
7.0
8.5
0.2
0.36
A/D Current(1), no conversion in
progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
DS41302D-page 148
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.5 DC Characteristics: PIC12F609/615/617 - E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +125°C for extended
Conditions
Units
Param
No.
Device Characteristics
Min
Typ†
Max
VDD
Note
D020E Power-down Base
Current (IPD)(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.05
0.15
0.35
0.5
2.5
9.5
5.0
6.0
50
4.0
5.0
8.5
5.0
8.0
19
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
WDT, BOR, Comparator, VREF and
T1OSC disabled
PIC12F609/615/617
D021E
WDT Current(1)
BOR Current(1)
D022E
D023E
15
19
70
Comparator Current(1), single
comparator enabled
55
75
60
80
D024E
D025E*
D026E
D027E
30
40
CVREF Current(1) (high range)
CVREF Current(1) (low range)
T1OSC Current(1), 32.768 kHz
45
60
75
105
50
39
59
80
98
130
16
5.5
7.0
8.5
0.2
0.36
18
22
6.5
10
A/D Current(1), no conversion in
progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
2010 Microchip Technology Inc.
DS41302D-page 149
PIC12F609/615/617/12HV609/615
16.6 DC Characteristics: PIC12HV609/615 - I (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
Conditions
Param
No.
Device Characteristics
Min
Typ†
Max
Units
VDD
Note
D020
Power-down Base
Current (IPD)(2,3)
—
135
200
A
2.0
WDT, BOR, Comparator, VREF and
T1OSC disabled
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
210
260
135
210
265
215
265
185
265
320
165
255
330
175
275
355
140
220
270
210
260
280
350
200
285
360
285
360
270
350
430
235
330
430
245
350
450
205
290
360
280
350
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
3.0
4.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
3.0
4.5
PIC12HV609/615
D021
WDT Current(1)
BOR Current(1)
D022
D023
Comparator Current(1), single
comparator enabled
D024
D025*
D026
D027
CVREF Current(1) (high range)
CVREF Current(1) (low range)
T1OSC Current(1), 32.768 kHz
A/D Current(1), no conversion in
progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Shunt regulator is always on and always draws operating current.
DS41302D-page 150
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.7 DC Characteristics: PIC12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +125°C for extended
Conditions
Units
Param
No.
Device Characteristics Min
Typ†
Max
VDD
Note
D020E Power-down Base
Current (IPD)(2,3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
135
210
260
135
210
265
215
265
185
265
320
165
255
330
175
275
355
140
220
270
210
260
200
280
350
200
285
360
285
360
280
360
430
235
330
430
245
350
450
205
290
360
280
350
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.0
3.0
4.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
2.0
3.0
4.5
3.0
4.5
WDT, BOR, Comparator, VREF and
T1OSC disabled
PIC12HV609/615
D021E
WDT Current(1)
BOR Current(1)
D022E
D023E
Comparator Current(1), single
comparator enabled
D024E
D025E*
D026E
D027E
CVREF Current(1) (high range)
CVREF Current(1) (low range)
T1OSC Current(1), 32.768 kHz
A/D Current(1), no conversion in
progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 4.5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: Shunt regulator is always on and always draws operating current.
2010 Microchip Technology Inc.
DS41302D-page 151
PIC12F609/615/617/12HV609/615
16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial)
PIC12F609/615/617/12HV609/615-E (Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
VIL
Input Low Voltage
I/O port:
with TTL buffer
D030
D030A
D031
D032
D033
D033A
Vss
Vss
Vss
VSS
VSS
VSS
—
—
—
—
—
—
0.8
V
V
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.2 VDD
0.3
2.0V VDD 4.5V
2.0V VDD 5.5V
(NOTE 1)
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
0.3 VDD
VIH
Input High Voltage
I/O ports:
—
—
—
—
—
—
—
—
D040
with TTL buffer
2.0
0.25 VDD + 0.8
0.8 VDD
0.8 VDD
1.6
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
4.5V VDD 5.5V
2.0V VDD 4.5V
2.0V VDD 5.5V
D040A
D041
with Schmitt Trigger buffer
MCLR
D042
D043
OSC1 (XT and LP modes)
OSC1 (HS mode)
D043A
D043B
0.7 VDD
0.9 VDD
OSC1 (RC mode)
(NOTE 1)
(2,3)
IIL
Input Leakage Current
D060
I/O ports
—
0.1
1
A VSS VPIN VDD,
Pin at high-impedance
(3,4)
D061
D063
GP3/MCLR
—
—
0.7
0.1
5
5
A VSS VPIN VDD
OSC1
A VSS VPIN VDD, XT, HS and
LP oscillator configuration
(5)
D070* IPUR
VOL
GPIO Weak Pull-up Current
Output Low Voltage
50
—
250
—
400
0.6
A VDD = 5.0V, VPIN = VSS
V
V
V
V
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
D080
I/O ports
—
—
—
—
0.6
—
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
VOH
Output High Voltage
VDD – 0.7
VDD – 0.7
IOH = -2.5mA, VDD = 4.5V,
-40°C to +125°C
(2)
D090
I/O ports
—
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled.
5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is
configured as MCLR reset pin, the weak pull-up is always enabled.
6: Applies to PIC12F617 only.
DS41302D-page 152
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.8 DC Characteristics: PIC12F609/615/617/12HV609/615-I (Industrial)
PIC12F609/615/617/12HV609/615-E (Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Capacitive Loading Specs on
D101* COSC2 Output Pins
—
—
—
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1
OSC2 pin
D101A* CIO
All I/O pins
—
50
pF
Program Flash Memory
Cell Endurance
Cell Endurance
VDD for Read
D130
EP
10K
1K
100K
10K
—
—
—
E/W -40°C TA +85°C
E/W +85°C TA +125°C
D130A ED
D131
D132
VPR
VMIN
5.5
V
VMIN = Minimum operating
voltage
VPEW
VDD for Bulk Erase/Write
4.5
VMIN
—
—
—
2
5.5
5.5
2.5
—
V
V
(6)
D132A VPEW
VDD for Row Erase/Write
Erase/Write cycle time
Characteristic Retention
D133
D134
TPEW
ms
TRETD
40
—
Year Provided no other specifications
are violated
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: This specification applies to GP3/MCLR configured as GP3 with the internal weak pull-up disabled.
5: This specification applies to all weak pull-up pins, including the weak pull-up found on GP3/MCLR. When GP3/MCLR is
configured as MCLR reset pin, the weak pull-up is always enabled.
6: Applies to PIC12F617 only.
2010 Microchip Technology Inc.
DS41302D-page 153
PIC12F609/615/617/12HV609/615
16.9 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym
No.
Characteristic
Typ
Units
Conditions
8-pin PDIP package
TH01
TH02
JA
Thermal Resistance
Junction to Ambient
84.6*
149.5*
211*
60*
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C
8-pin SOIC package
8-pin MSOP package
8-pin DFN 3x3mm package
8-pin DFN 4x4mm package
8-pin PDIP package
44*
JC
Thermal Resistance
Junction to Case
41.2*
39.9*
39*
8-pin SOIC package
8-pin MSOP package
9*
8-pin DFN 3x3mm package
8-pin DFN 4x4mm package
3.0*
150*
—
TH03
TH04
TH05
TDIE
PD
Die Temperature
Power Dissipation
W
PD = PINTERNAL + PI/O
PINTERNAL Internal Power Dissipation
—
W
PINTERNAL = IDD x VDD
(NOTE 1)
TH06
TH07
PI/O
I/O Power Dissipation
Derated Power
—
—
W
W
PI/O = (IOL * VOL) + (IOH * (VDD -
VOH))
PDER
PDER = PDMAX (TDIE - TA)/JA
(NOTE 2)
*
These parameters are characterized but not tested.
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient temperature.
DS41302D-page 154
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.10 Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O Port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 16-3:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL=50 pF for all pins
15 pF for OSC2 output
2010 Microchip Technology Inc.
DS41302D-page 155
PIC12F609/615/617/12HV609/615
16.11 AC Characteristics: PIC12F609/615/617/12HV609/615 (Industrial, Extended)
FIGURE 16-4:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 16-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
kHz
Conditions
(1)
OS01
FOSC
TOSC
TCY
External CLKIN Frequency
DC
DC
DC
DC
—
—
—
37
4
LP Oscillator mode
MHz XT Oscillator mode
MHz HS Oscillator mode
MHz EC Oscillator mode
—
20
20
—
4
—
(1)
Oscillator Frequency
32.768
—
kHz
LP Oscillator mode
0.1
1
MHz XT Oscillator mode
MHz HS Oscillator mode
MHz RC Oscillator mode
—
20
4
DC
27
250
50
50
—
—
(1)
OS02
External CLKIN Period
—
s
ns
ns
ns
s
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
TCY = 4/FOSC
—
—
—
(1)
Oscillator Period
30.5
—
—
10,000
1,000
—
DC
—
—
—
250
50
250
200
2
—
—
(1)
OS03
Instruction Cycle Time
TCY
—
OS04*
TOSH,
TOSL
External CLKIN High,
External CLKIN Low
LP oscillator
100
20
0
—
XT oscillator
—
HS oscillator
OS05*
TOSR,
TOSF
External CLKIN Rise,
External CLKIN Fall
—
LP oscillator
0
—
XT oscillator
0
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When
an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41302D-page 156
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 16-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
Sym
No.
Freq.
Tolerance
Characteristic
Min
Typ†
Max
Units
Conditions
OS06
TWARM
Internal Oscillator Switch
when running
—
—
—
2
TOSC Slowest clock
(3)
OS07
INTOSC
Internal Calibrated
INTOSC Frequency
(4MHz)
1%
2%
3.96
3.92
4.0
4.0
4.04
4.08
MHz VDD = 3.5V, T = 25°C
A
(2)
MHz 2.5V VDD 5.5V,
0°C TA +85°C
5%
3.80
4.0
4.2
MHz 2.0V VDD 5.5V,
-40°C TA +85°C (Ind.),
-40°C TA +125°C (Ext.)
OS08
INTOSC
Internal Calibrated
INTOSC Frequency
(8MHz)
1%
2%
7.92
7.84
8.0
8.0
8.08
8.16
MHz VDD = 3.5V, T = 25°C
A
(2)
MHz 2.5V VDD 5.5V,
0°C TA +85°C
5%
7.60
8.0
8.40
MHz 2.0V VDD 5.5V,
-40°C TA +85°C (Ind.),
-40°C TA +125°C (Ext.)
OS10*
TIOSC ST INTOSC Oscillator Wake-
up from Sleep
—
—
—
5.5
3.5
3
12
7
24
14
11
s
s
s
VDD = 2.0V, -40°C to +85°C
VDD = 3.0V, -40°C to +85°C
VDD = 5.0V, -40°C to +85°C
Start-up Time
6
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
2010 Microchip Technology Inc.
DS41302D-page 157
PIC12F609/615/617/12HV609/615
FIGURE 16-5:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
TABLE 16-3: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
OS11
OS12
OS13
OS14
OS15
OS16
TOSH2CKL FOSC to CLKOUT (1)
TOSH2CKH FOSC to CLKOUT (1)
—
—
—
—
70
72
20
—
ns VDD = 5.0V
ns VDD = 5.0V
ns
—
—
—
50
—
TCKL2IOV
CLKOUT to Port out valid(1)
TIOV2CKH Port input valid before CLKOUT(1)
TOSC + 200 ns
ns
TOSH2IOV FOSC (Q1 cycle) to Port out valid
—
70*
—
ns VDD = 5.0V
ns VDD = 5.0V
TOSH2IOI
FOSC (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17
OS18
OS19
TIOV2OSH Port input valid to FOSC(Q2 cycle)
20
—
—
ns
(I/O in setup time)
TIOR
TIOF
Port output rise time(2)
Port output fall time(2)
—
—
15
40
72
32
ns VDD = 2.0V
VDD = 5.0V
—
—
28
15
55
30
ns VDD = 2.0V
VDD = 5.0V
OS20* TINP
OS21* TRAP
INT pin input high or low time
25
—
—
—
—
ns
ns
GPIO interrupt-on-change new input
level time
TCY
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25C unless otherwise stated.
†
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
DS41302D-page 158
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 16-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
(1)
Internal Reset
Watchdog Timer
(1)
Reset
31
34
34
I/O pins
Note 1:
Asserted low.
FIGURE 16-7:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR + VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
(due to BOR)
33*
*
64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.
2010 Microchip Technology Inc.
DS41302D-page 159
PIC12F609/615/617/12HV609/615
TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
TMCL
Characteristic
Min
Typ†
Max Units
Conditions
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 5V, -40°C to +85°C
s VDD = 5V, -40°C to +125°C
31*
32
TWDT
TOST
Watchdog Timer Time-out
Period (No Prescaler)
10
10
20
20
30
35
ms VDD = 5V, -40°C to +85°C
ms VDD = 5V, -40°C to +125°C
Oscillation Start-up Timer
Period(1, 2)
—
1024
—
TOSC (NOTE 3)
33*
34*
TPWRT Power-up Timer Period
40
—
65
—
140
2.0
ms
TIOZ
I/O High-impedance from
MCLR Low or Watchdog Timer
Reset
s
35
VBOR
VHYST
TBOR
Brown-out Reset Voltage
2.0
—
2.15
100
—
2.3
—
V
(NOTE 4)
36*
37*
Brown-out Reset Hysteresis
mV
Brown-out Reset Minimum
Detection Period
100
—
s VDD VBOR
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time
limit is “DC” (no clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device
as possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41302D-page 160
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 16-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
40*
41*
42*
TT0H
TT0L
TT0P
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
46*
47*
TT1H
TT1L
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
0.5 TCY + 20
15
—
—
—
—
—
—
ns
ns
ns
T1CKI Low Synchronous, No Prescaler
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
ns
TT1P
FT1
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
—
—
ns
48
Timer1 Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.768
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2010 Microchip Technology Inc.
DS41302D-page 161
PIC12F609/615/617/12HV609/615
FIGURE 16-9:
PIC12F615/617/HV615 CAPTURE/COMPARE/PWM TIMINGS (ECCP)
CCP1
(Capture mode)
CC01
CC02
CC03
Note:
Refer to Figure 16-3 for load conditions.
TABLE 16-6: PIC12F615/617/HV615 CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
CC01* TccL
CC02* TccH
CC03* TccP
CCP1 Input Low Time
CCP1 Input High Time
CCP1 Input Period
No Prescaler
0.5TCY + 20
20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
20
3TCY + 40
N
ns N = prescale
value (1, 4 or
16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
TABLE 16-7: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym
Characteristics
Input Offset Voltage(2)
Min Typ†
Max
Units
Comments
CM01 VOS
CM02 VCM
CM03* CMRR
CM04* TRT
—
0
5.0
—
10
VDD – 1.5
—
mV
V
Input Common Mode Voltage
Common Mode Rejection Ratio
Response Time(1)
+55
—
—
—
—
—
dB
ns
ns
s
mV
Falling
Rising
150
200
—
600
1000
10
CM05* TMC2COV Comparator Mode Change to Output Valid
CM06* VHYS Input Hysteresis Voltage
These parameters are characterized but not tested.
45
60
*
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.
The other input is at (VDD -1.5)/2.
2: Input offset voltage is measured with one comparator input at (VDD - 1.5V)/2.
DS41302D-page 162
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 16-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym
No.
Characteristics
Min
Typ†
Max
Units
Comments
CV01* CLSB
Step Size(2)
Absolute Accuracy(3)
—
—
VDD/24
VDD/32
—
—
V
V
Low Range (VRR = 1)
High Range (VRR = 0)
CV02* CACC
—
—
—
—
1/2
1/2
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
CV03* CR
CV04* CST
Unit Resistor Value (R)
Settling Time(1)
—
—
2k
—
—
10
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.
2: See Section 9.10 “Comparator Voltage Reference” for more information.
3: Absolute Accuracy when CVREF output is (VDD -1.5).
TABLE 16-9: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated)
VR Voltage Reference Specifications
Operating temperature
-40°C TA +125°C
Param
No.
Symbol
Characteristics
VP6 voltage output
Min
Typ
Max
Units
Comments
VR01
VR02
VP6OUT
0.5
1.05
—
0.6
1.20
10
0.7
1.35
—
V
V
V1P2OUT
V1P2 voltage output
Settling Time
VR03* TSTABLE
s
*
These parameters are characterized but not tested.
TABLE 16-10: SHUNT REGULATOR SPECIFICATIONS (PIC12HV609/615 only)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
SHUNT REGULATOR CHARACTERISTICS
Param
Symbol
Characteristics
Min
Typ
Max
Units
Comments
No.
SR01
SR02
SR03*
SR04
VSHUNT Shunt Voltage
ISHUNT Shunt Current
TSETTLE Settling Time
4.75
4
5
5.4
50
V
—
—
—
mA
ns
—
150
10
To 1% of final value
CLOAD
Load Capacitance
0.01
F
Bypass capacitor on VDD
pin
SR05
ISNT
Regulator operating current
—
180
—
A
Includes band gap
reference current
*
These parameters are characterized but not tested.
2010 Microchip Technology Inc.
DS41302D-page 163
PIC12F609/615/617/12HV609/615
TABLE 16-11: PIC12F615/617/HV615 A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
10 bits
1
bit
Integral Error
—
—
LSb VREF = 5.12V(5)
Differential Error
1
LSb No missing codes to 10 bits
VREF = 5.12V(5)
AD04 EOFF Offset Error
AD07 EGN Gain Error
—
—
+1.5
—
+2.0
LSb VREF = 5.12V(5)
LSb VREF = 5.12V(5)
1
AD06 VREF Reference Voltage(3)
AD06A
2.2
2.5
—
—
VDD
V
Absolute minimum to ensure 1 LSb
accuracy
AD07 VAIN Full-Scale Range
VSS
—
—
—
VREF
10
V
AD08 ZAIN Recommended
Impedance of Analog
Voltage Source
k
AD09* IREF
VREF Input Current(3)
10
—
—
—
1000
50
A During VAIN acquisition.
Based on differential of VHOLD to VAIN.
A During A/D conversion cycle.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing
codes.
3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current
specification includes any such leakage from the ADC module.
5: VREF = 5V for PIC12HV615.
DS41302D-page 164
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 16-12: PIC12F615/617/HV615 A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
No.
Sym
Characteristic
A/D Clock Period
Min
Typ†
Max Units
Conditions
AD130* TAD
1.6
3.0
—
—
9.0
9.0
s TOSC-based, VREF 3.0V
s TOSC-based, VREF full range(3)
A/D Internal RC
Oscillator Period
ADCS<1:0> = 11(ADRC mode)
s At VDD = 2.5V
3.0
1.6
—
6.0
4.0
11
9.0
6.0
—
s At VDD = 5.0V
AD131 TCNV Conversion Time
(not including
TAD Set GO/DONE bit to new data in A/D
Result register
Acquisition Time)(1)
AD132* TACQ Acquisition Time
11.5
—
—
5
s
s
—
AD133* TAMP Amplifier Settling Time
AD134 TGO Q4 to A/D Clock Start
—
—
TOSC/2
—
—
TOSC/2 +
TCY
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the SLEEP
instruction to be executed.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.
2: See Section 10.3 “A/D Acquisition Requirements” for minimum conditions.
3: Full range for PIC12HV609/HV615 powered by the shunt regulator is the 5V regulated voltage.
FIGURE 16-10:
PIC12F615/617/HV615 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
AD134
Q4
1 TCY
(1)
(TOSC/2
)
AD131
AD130
A/D CLK
9
8
7
6
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
2010 Microchip Technology Inc.
DS41302D-page 165
PIC12F609/615/617/12HV609/615
FIGURE 16-11:
PIC12F615/617/HV615 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
(1)
(TOSC/2 + TCY
1 TCY
)
AD131
Q4
AD130
A/D CLK
A/D Data
9
8
7
3
2
1
0
6
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
DS41302D-page 166
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
16.12 High Temperature Operation
This section outlines the specifications for the
PIC12F615 device operating in a temperature range
between -40°C and 150°C.(4) The specifications
between -40°C and 150°C(4) are identical to those
shown in DS41288 and DS80329.
Note 1: Writes are not allowed for Flash
Program Memory above 125°C.
2: All AC timing specifications are increased
by 30%. This derating factor will include
parameters such as TPWRT.
3: The temperature range indicator in the
part number is “H” for -40°C to 150°C.(4)
Example: PIC12F615T-H/ST indicates the
device is shipped in a TAPE and reel
configuration, in the MSOP package, and
is rated for operation from -40°C to
150°C.(4)
4: AEC-Q100 reliability testing for devices
intended to operate at 150°C is 1,000
hours. Any design in which the total oper-
ating time from 125°C to 150°C will be
greater than 1,000 hours is not warranted
without prior written approval from
Microchip Technology Inc.
TABLE 16-13: ABSOLUTE MAXIMUM RATINGS
Parameter
Max. Current: VDD
Source/Sink
Value
Units
Source
Sink
20
50
5
mA
mA
mA
mA
mA
mA
mA
mA
°C
Max. Current: VSS
Max. Current: PIN
Source
Sink
Max. Current: PIN
10
3
Pin Current: at VOH
Pin Current: at VOL
Port Current: GPIO
Port Current: GPIO
Maximum Junction Temperature
Source
Sink
8.5
20
50
155
Source
Sink
Note:
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure above
maximum rating conditions for extended periods may affect device reliability.
2010 Microchip Technology Inc.
DS41302D-page 167
PIC12F609/615/617/12HV609/615
TABLE 16-14: DC CHARACTERISTICS FOR IDD SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Condition
Param
No.
Device
Characteristics
Units
Min
Typ
Max
VDD
Note
D010
D011
D012
D013
D014
D016
D017
D018
D019
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
13
19
58
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
Supply Current (IDD)
A
IDD LP OSC (32 kHz)
67
32
92
135
185
300
240
360
0.660
75
316
400
537
495
680
1.20
158
338
792
357
625
1.30
476
672
1.10
757
1.20
2.20
332
518
972
4.10
4.80
A
IDD XT OSC (1 MHz)
IDD XT OSC (4 MHz)
IDD EC OSC (1 MHz)
IDD EC OSC (4 MHz)
IDD INTOSC (4 MHz)
IDD INTOSC (8 MHz)
A
mA
155
345
185
325
0.665
245
360
620
395
0.620
1.20
175
285
530
2.20
2.80
A
A
mA
A
A
mA
A
IDD EXTRC (4 MHz)
mA
IDD HS OSC (20 MHz)
DS41302D-page 168
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
TABLE 16-15: DC CHARACTERISTICS FOR IPD SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Condition
Param
No.
Device
Characteristics
Units
Min
Typ
Max
VDD
Note
D020E
D021E
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.05
0.15
0.35
0.5
2.5
9.5
5.0
6.0
105
110
116
50
12
13
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
3.0
5.0
Power Down Base
Current
IPD Base
A
14
20
A
A
WDT Current
BOR Current
25
36
D022E
D023E
28
36
195
210
220
105
110
125
58
IPD Current (Both
Comparators Enabled)
A
A
IPD Current (One Comparator
Enabled)
55
60
D024E
D025E
D026E
D027E
30
A
A
45
85
IPD (CVREF, High Range)
IPD (CVREF, Low Range)
75
142
76
39
59
114
190
30
98
5.5
7.0
8.5
0.2
0.3
IPD (T1 OSC, 32 kHz)
A
A
35
45
12
IPD (A2D on, not converting)
15
TABLE 16-16: WATCHDOG TIMER SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param
Sym
Characteristic
Units
Min
Typ
Max
Conditions
No.
31
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
ms
6
20
70
150°C Temperature
TABLE 16-17: LEAKAGE CURRENT SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param
Sym
Characteristic
Units
Min
Typ
Max
Conditions
No.
D061
IIL
IIL
Input Leakage Current(1)
(GP3/RA3/MCLR)
Input Leakage Current(2)
µA
—
±0.5
±5.0
VSS VPIN VDD
D062
µA
50
250
400
VDD = 5.0V
(GP3/RA3/MCLR)
Note 1: This specification applies when GP3/RA3/MCLR is configured as an input with the pull-up disabled. The
leakage current for the GP3/RA3/MCLR pin is higher than for the standard I/O port pins.
2: This specification applies when GP3/RA3/MCLR is configured as the MCLR reset pin function with the
weak pull-up enabled.
2010 Microchip Technology Inc.
DS41302D-page 169
PIC12F609/615/617/12HV609/615
TABLE 16-18: OSCILLATOR PARAMETERS FOR PIC12F615-H (High Temp.)
Param
No.
Frequency
Tolerance
Sym
Characteristic
Units
Min
Typ
Max
Conditions
OS08 INTOSC Int. Calibrated INTOSC
Freq.(1)
±10%
MHz
7.2
8.0
8.8
2.0V VDD 5.5V
-40°C TA 150°C
Note 1: To ensure these oscillator frequency tolerances, Vdd and Vss must be capacitively decoupled as close to
the device as possible. 0.1 µF and 0.01 µF values in parallel are recommended.
TABLE 16-19: COMPARATOR SPECIFICATIONS FOR PIC12F615-H (High Temp.)
Param
Sym
Characteristic
Units
Min
Typ
Max
Conditions
No.
CM01 VOS
Input Offset Voltage
mV
—
±5
±20
(VDD - 1.5)/2
DS41302D-page 170
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
17.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein are
not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3) or (mean -
3) respectively, where s is a standard deviation, over each temperature range.
FIGURE 17-1:
PIC12F609/615/617 IDD LP (32 kHz) vs. VDD
60
50
40
30
20
10
0
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
2
4
6
1
3
5
VDD (V)
FIGURE 17-2:
PIC12F609/615/617 IDD EC (1 MHz) vs. VDD
600
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
500
400
300
200
100
0
2
4
6
1
3
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 171
PIC12F609/615/617/12HV609/615
FIGURE 17-3:
PIC12F609/615/617 IDD EC (4 MHz) vs. VDD
1200
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
1000
800
600
400
200
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-4:
PIC12F609/615/617 IDD XT (1 MHz) vs. VDD
1200
1000
800
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
600
Maximum
Typical
400
200
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-5:
PIC12F609/615/617 IDD XT (4 MHz) vs. VDD
1200
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1000
800
600
400
200
0
2
4
6
1
3
VDD (V)
5
DS41302D-page 172
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-6:
PIC12F609/615/617 IDD INTOSC (4 MHz) vs. VDD
900
Maximum
800
700
600
500
400
300
200
100
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typical
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-7:
PIC12F609/615/617 IDD INTOSC (8 MHz) vs. VDD
1800
1600
1400
1200
1000
800
600
400
200
0
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2
4
6
1
3
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 173
PIC12F609/615/617/12HV609/615
FIGURE 17-8:
PIC12F609/615617 IDD EXTRC (4 MHz) vs. VDD
800
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
700
600
500
400
300
200
100
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-9:
PIC12F609/615/617 IDD HS (20 MHz) vs. VDD
4
Maximum
Typical
3
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2
1
0
4
6
5
VDD (V)
DS41302D-page 174
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-10:
PIC12F609/615/617 IPD BASE vs. VDD
9
Extended
Typical: Statistical Mean @25°C
8
7
6
5
4
3
2
1
0
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Industrial
Typical
2
4
6
1
3
5
VDD (V)
FIGURE 17-11:
PIC12F609/615/617 IPD COMPARATOR (SINGLE ON) vs. VDD
90
Extended
80
70
60
50
40
30
Industrial
Typical
Typical: Statistical Mean @25°C
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2
4
6
1
3
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 175
PIC12F609/615/617/12HV609/615
FIGURE 17-12:
PIC12F609/615/617 IPD WDT vs. VDD
20
18
16
14
12
10
8
Extended
Industrial
Typical: Statistical Mean @25°C
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typical
6
4
2
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-13:
PIC12F609/615/617 IPD BOR vs. VDD
20
Typical: Statistical Mean @25°C
Extended
Industrial: Mean (Worst-Case Temp) + 3
18
16
14
12
10
8
(-40°C to 85°C)
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Industrial
Typical
6
4
2
0
2
4
6
1
3
5
VDD (V)
DS41302D-page 176
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-14:
PIC12F609/615/617 IPD CVREF (LOW RANGE) vs. VDD
140
Typical: Statistical Mean @25°C
Maximum
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
120
100
80
60
40
20
0
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typical
2
4
6
1
3
5
VDD (V)
FIGURE 17-15:
PIC12F609/615/617 IPD CVREF (HI RANGE) vs. VDD
120
Typical: Statistical Mean @25°C
Maximum
Typical
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
100
80
60
40
20
0
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1
3
2
4
6
5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 177
PIC12F609/615/617/12HV609/615
FIGURE 17-16:
PIC12F609/615/617 IPD T1OSC vs. VDD
25
Typical: Statistical Mean @25°C
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
Extended
Extended: Mean (Worst-Case Temp) + 3
20
15
10
5
(-40°C to 125°C)
Industrial
Typical
0
2
4
6
1
3
5
VDD (V)
FIGURE 17-17:
PIC12F615/617 IPD A/D vs. VDD
14
Typical: Statistical Mean @25°C
Extended
Industrial: Mean (Worst-Case Temp) + 3
(-40°C to 85°C)
12
10
Extended: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
8
6
4
2
0
Industrial
Typical
2
4
6
1
3
5
VDD (V)
DS41302D-page 178
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-18:
PIC12HV609/615 IDD LP (32 kHz) vs. VDD
450
Maximum
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
400
350
300
250
200
150
100
Typical
50
0
2
1
3
5
4
VDD (V)
FIGURE 17-19:
PIC12HV609/615 IDD EC (1 MHz) vs. VDD
1000
900
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
800
700
600
500
400
300
200
100
2
1
3
5
4
VDD (V)
FIGURE 17-20:
PIC12HV609/615 IDD EC (4 MHz) vs. VDD
1400
1200
1000
800
600
400
200
0
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
2
5
1
3
4
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 179
PIC12F609/615/617/12HV609/615
FIGURE 17-21:
PIC12HV609/615 IDD XT (1 MHz) vs. VDD
900
800
700
600
500
400
300
200
100
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0
2
1
3
5
4
VDD (V)
FIGURE 17-22:
PIC12HV609/615 IDD XT (4 MHz) vs. VDD
1400
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1200
1000
800
600
400
200
0
2
5
1
3
4
VDD (V)
FIGURE 17-23:
PIC12HV609/615 IDD INTOSC (4 MHz) vs. VDD
1200
1000
800
Maximum
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Typical
600
400
200
0
2
1
3
5
4
VDD (V)
DS41302D-page 180
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-24:
PIC12HV609/615 IDD INTOSC (8 MHz) vs. VDD
2000
Maximum
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1500
1000
Typical
500
0
1
2
3
5
4
VDD (V)
FIGURE 17-25:
PIC12HV609/615 IDD EXTRC (4 MHz) vs. VDD
1200
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1000
800
600
400
200
0
1
2
5
3
4
VDD (V)
FIGURE 17-26:
PIC12HV609/615 IPD BASE vs. VDD
400
350
300
250
200
150
100
50
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0
1
2
5
3
4
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 181
PIC12F609/615/617/12HV609/615
FIGURE 17-27:
PIC12HV609/615 IPD COMPARATOR (SINGLE ON) vs. VDD
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
500
400
Maximum
Typical
300
200
100
0
1
2
5
3
4
VDD (V)
FIGURE 17-28:
PIC12HV609/615 IPD WDT vs. VDD
400
350
300
250
200
150
100
50
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0
2
5
1
3
4
VDD (V)
FIGURE 17-29:
PIC12HV609/615 IPD BOR vs. VDD
400
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
350
300
250
200
150
100
3
2
4
5
VDD (V)
DS41302D-page 182
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-30:
PIC12HV609/615 IPD CVREF (LOW RANGE) vs. VDD
500
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
400
300
200
100
0
2
1
3
5
4
VDD (V)
FIGURE 17-31:
PIC12HV609/615 IPD CVREF (HI RANGE) vs. VDD
500
Maximum
Typical
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
400
300
200
100
0
2
1
3
5
4
VDD (V)
FIGURE 17-32:
PIC12HV609/615 IPD T1OSC vs. VDD
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
400
350
300
250
200
150
100
Maximum
Typical
50
0
2
5
1
3
4
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 183
PIC12F609/615/617/12HV609/615
FIGURE 17-33:
PIC12HV615 IPD A/D vs. VDD
Typical: Statistical Mean @25°C
400
350
300
250
200
150
100
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
Maximum
Typical
50
0
2
4
5
3
VDD (V)
FIGURE 17-34:
VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)
0.8
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Max. 125°C
Max. 85°C
Typical 25°C
Min. -40°C
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
DS41302D-page 184
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-35:
VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)
0.45
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
Max. 125°C
Max. 85°C
Typ. 25°C
Min. -40°C
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
IOL (mA)
FIGURE 17-36:
VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)
3.5
3.0
2.5
2.0
1.5
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1.0
0.5
0.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
IOH (mA)
2010 Microchip Technology Inc.
DS41302D-page 185
PIC12F609/615/617/12HV609/615
FIGURE 17-37:
VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)
5.5
5.0
4.5
4.0
Max. -40°C
Typ. 25°C
Min. 125°C
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
3.5
3.0
0.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
IOH (mA)
FIGURE 17-38:
TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
1.7
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
1.5
1.3
1.1
0.9
0.7
0.5
Max. -40°C
Typ. 25°C
Min. 125°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41302D-page 186
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-39:
SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE
4.0
VIH Max. 125°C
Typical: Statistical Mean @25°C
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
VIH Min. -40°C
VIL Max. -40°C
VIL Min. 125°C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-40:
TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
16
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
14
85°C
12
25°C
10
-40°C
8
6
4
2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 187
PIC12F609/615/617/12HV609/615
FIGURE 17-41:
MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
25
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
20
15
10
5
85°C
25°C
-40°C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-42:
MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE
10
9
8
7
6
5
4
3
2
1
Typical: Statistical Mean @25°C
Maximum: Mean (Worst-Case Temp) + 3
(-40°C to 125°C)
85°C
25°C
-40°C
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41302D-page 188
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-43:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-44:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (85°C)
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 189
PIC12F609/615/617/12HV609/615
FIGURE 17-45:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 17-46:
TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)
5
4
3
2
1
0
-1
-2
-3
-4
-5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS41302D-page 190
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-47:
0.6V REFERENCE VOLTAGE vs. TEMP (TYPICAL)
0.61
2.5V
3V
0.6
0.59
0.58
0.57
4V
5V
5.5V
0.56
-60
-40
-20
0
20
40
60
80
100
120
140
Temp (C)
FIGURE 17-48:
1.2V REFERENCE VOLTAGE vs. TEMP (TYPICAL)
1.26
2.5V
1.25
1.24
1.23
1.22
1.21
1.2
3V
4V
5V
5.5V
-60
-40
-20
0
20
40
60
80
100
120
140
Temp (C)
FIGURE 17-49:
SHUNT REGULATOR VOLTAGE vs. INPUT CURRENT (TYPICAL)
5.16
5.14
5.12
5.1
-40°C
25°C
85°C
125°C
5.08
5.06
5.04
5.02
5
4.98
4.96
0
10
20
30
40
50
60
Input Current (mA)
2010 Microchip Technology Inc.
DS41302D-page 191
PIC12F609/615/617/12HV609/615
FIGURE 17-50:
SHUNT REGULATOR VOLTAGE vs. TEMP (TYPICAL)
5.16
5.14
5.12
5.1
50 mA
40 mA
5.08
5.06
5.04
5.02
5
20 mA
15 mA
10 mA
4 mA
4.98
4.96
-60
-40
-20
0
20
40
60
80
100
120
140
Temp (C)
FIGURE 17-51:
COMPARATOR RESPONSE TIME (RISING EDGE)
1000
900
800
700
Max. 125°C
Max. 85°C
VCM = (VDD - 1.5V)/2
Note:
600
500
400
300
200
100
V+ input = VCM
V- input = Transition from VCM + 100mV to VCM - 20mV
Typ. 25°C
Min. -40°C
0
2.0
2.5
4.0
5.5
VDD (V)
DS41302D-page 192
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
FIGURE 17-52:
COMPARATOR RESPONSE TIME (FALLING EDGE)
1000
900
800
700
Max. 125°C
600
500
400
300
200
100
0
Note:
VCM = (VDD - 1.5V)/2
V+ input = VCM
V- input = Transition from VCM - 100mV to VCM + 20MV
Max. 85°C
Typ. 25°C
Min. -40°C
2.0
2.5
4.0
5.5
VDD (V)
FIGURE 17-53:
WDT TIME-OUT PERIOD vs. VDD OVER TEMPERATURE
55
50
45
40
35
30
25
20
15
10
125°C
85°C
25°C
-40°C
5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
2010 Microchip Technology Inc.
DS41302D-page 193
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 194
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
18.0 PACKAGING INFORMATION
18.1 Package Marking Information
8-Lead PDIP (.300”)
Example
XXFXXX/P
XXXXXXXX
XXXXXNNN
YYWW
e
3
017
0610
8-Lead SOIC (.150”)
Example
XXXXXXXX
XXXXYYWW
PICXXCXX
/SN0610
e
3
NNN
017
8-Lead MSOP
Example
XXXXXX
YWWNNN
602/MS
610017
8-Lead DFN (3x3 mm)
Example
XXXX
YYWW
NNN
XXXX
0610
017
8-Lead DFN (4x4 mm) (for PIC12F609/615/HV609/615
devices only)
Example
XXXXXX
XXXXXX
YYWW
NNN
XXXXXX
e
3
XXXX
0610
017
Legend:
XX...X
Y
YY
WW
NNN
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will be
carried over to the next line, thus limiting the number of available characters for
customer-specific information.
*
Standard PIC device marking consists of Microchip part number, year code, week code, and traceability code. For
PIC device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP
devices, any special marking adders are included in QTP price.
2010 Microchip Technology Inc.
DS41302D-page 195
PIC12F609/615/617/12HV609/615
18.2 Package Details
The following sections give the technical details of the packages.
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢐꢁꢂꢋꢐꢃꢆꢑꢇꢒꢆꢓꢆꢔꢕꢕꢆꢖꢋꢈꢆꢗꢘꢅꢙꢆꢚꢇꢍꢏꢇꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
A1
c
e
eB
b1
b
6ꢄꢃ&!
ꢚ7,8.ꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
<
ꢁꢀꢕꢕꢅ1ꢐ,
M
ꢁꢀ-ꢕ
M
ꢁ-ꢀꢕ
ꢁꢎꢘꢕ
ꢁ-?ꢘ
ꢁꢀ-ꢕ
ꢁꢕꢀꢕ
ꢁꢕ?ꢕ
ꢁꢕꢀ<
M
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
ꢙꢋꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
1ꢆ!ꢈꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
ꢐꢍꢋ"ꢇ#ꢈꢉꢅ&ꢋꢅꢐꢍꢋ"ꢇ#ꢈꢉꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
7
ꢈ
ꢗ
ꢗꢎ
ꢗꢀ
.
.ꢀ
ꢒ
9
ꢌ
)ꢀ
)
ꢈ1
M
ꢁꢎꢀꢕ
ꢁꢀꢛꢘ
M
ꢁꢀꢀꢘ
ꢁꢕꢀꢘ
ꢁꢎꢛꢕ
ꢁꢎꢖꢕ
ꢁ-ꢖ<
ꢁꢀꢀꢘ
ꢁꢕꢕ<
ꢁꢕꢖꢕ
ꢁꢕꢀꢖ
M
ꢁ-ꢎꢘ
ꢁꢎ<ꢕ
ꢁꢖꢕꢕ
ꢁꢀꢘꢕ
ꢁꢕꢀꢘ
ꢁꢕꢜꢕ
ꢁꢕꢎꢎ
ꢁꢖ-ꢕ
ꢙꢃꢓꢅ&ꢋꢅꢐꢈꢆ&ꢃꢄꢑꢅꢂꢇꢆꢄꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
6ꢓꢓꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
9ꢋ*ꢈꢉꢅ9ꢈꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅꢝꢋ*ꢅꢐꢓꢆꢌꢃꢄꢑꢅꢅꢏ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢁꢕꢀꢕ/ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2ꢅ1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢀ<1
DS41302D-page 196
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
e
N
E
E1
NOTE 1
1
2
3
α
h
b
h
c
φ
A2
A
L
A1
L1
β
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
<
ꢀꢁꢎꢜꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅꢅꢏ
ꢗ
M
ꢀꢁꢎꢘ
ꢕꢁꢀꢕ
M
M
M
ꢀꢁꢜꢘ
M
ꢕꢁꢎꢘ
ꢗꢎ
ꢗꢀ
.
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
?ꢁꢕꢕꢅ1ꢐ,
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
,ꢍꢆ'%ꢈꢉꢅ@ꢋꢓ&ꢃꢋꢄꢆꢇA
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
.ꢀ
ꢒ
ꢍ
-ꢁꢛꢕꢅ1ꢐ,
ꢖꢁꢛꢕꢅ1ꢐ,
ꢕꢁꢎꢘ
ꢕꢁꢖꢕ
M
M
ꢕꢁꢘꢕ
ꢀꢁꢎꢜ
9
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅꢙꢋꢓ
ꢔꢋꢇ#ꢅꢒꢉꢆ%&ꢅꢗꢄꢑꢇꢈꢅ1ꢋ&&ꢋ'
9ꢀ
ꢀ
ꢀꢁꢕꢖꢅꢝ.3
ꢕꢟ
ꢕꢁꢀꢜ
ꢕꢁ-ꢀ
ꢘꢟ
M
M
M
M
M
<ꢟ
ꢌ
)
ꢁ
ꢕꢁꢎꢘ
ꢕꢁꢘꢀ
ꢀꢘꢟ
ꢂ
ꢘꢟ
ꢀꢘꢟ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢏꢅꢐꢃꢑꢄꢃ%ꢃꢌꢆꢄ&ꢅ,ꢍꢆꢉꢆꢌ&ꢈꢉꢃ!&ꢃꢌꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕꢘꢜ1
2010 Microchip Technology Inc.
DS41302D-page 197
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢑꢞꢜꢒꢆꢓꢆꢜꢄꢠꢠꢘꢡꢢꢆꢔꢣꢤꢕꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢞꢟꢏꢥꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41302D-page 198
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢦꢋꢌꢠꢘꢆꢞꢖꢄꢈꢈꢆꢟꢎꢊꢈꢋꢐꢃꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦꢞꢒꢆꢚꢦꢞꢟꢇꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
D
N
E
E1
NOTE 1
2
b
1
e
c
φ
A2
A
L
L1
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
7
ꢈ
<
ꢕꢁ?ꢘꢅ1ꢐ,
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅꢙꢍꢃꢌ4ꢄꢈ!!
ꢐ&ꢆꢄ#ꢋ%%ꢅ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
ꢔꢋꢇ#ꢈ#ꢅꢂꢆꢌ4ꢆꢑꢈꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
3ꢋꢋ&ꢅ9ꢈꢄꢑ&ꢍ
ꢗ
M
ꢕꢁꢜꢘ
ꢕꢁꢕꢕ
M
ꢕꢁ<ꢘ
ꢀꢁꢀꢕ
ꢕꢁꢛꢘ
ꢕꢁꢀꢘ
ꢗꢎ
ꢗꢀ
.
.ꢀ
ꢒ
M
ꢖꢁꢛꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
-ꢁꢕꢕꢅ1ꢐ,
ꢕꢁ?ꢕ
9
ꢕꢁꢖꢕ
ꢕꢁ<ꢕ
3ꢋꢋ&ꢓꢉꢃꢄ&
3ꢋꢋ&ꢅꢗꢄꢑꢇꢈ
9ꢀ
ꢀ
ꢕꢁꢛꢘꢅꢝ.3
M
ꢕꢟ
<ꢟ
9ꢈꢆ#ꢅꢙꢍꢃꢌ4ꢄꢈ!!
9ꢈꢆ#ꢅ>ꢃ#&ꢍ
ꢌ
)
ꢕꢁꢕ<
ꢕꢁꢎꢎ
M
M
ꢕꢁꢎ-
ꢕꢁꢖꢕ
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄ!ꢅꢒꢅꢆꢄ#ꢅ.ꢀꢅ#ꢋꢅꢄꢋ&ꢅꢃꢄꢌꢇ"#ꢈꢅ'ꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢁꢅꢔꢋꢇ#ꢅ%ꢇꢆ!ꢍꢅꢋꢉꢅꢓꢉꢋ&ꢉ"!ꢃꢋꢄ!ꢅ!ꢍꢆꢇꢇꢅꢄꢋ&ꢅꢈ$ꢌꢈꢈ#ꢅꢕꢁꢀꢘꢅ''ꢅꢓꢈꢉꢅ!ꢃ#ꢈꢁ
-ꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀꢀꢀ1
2010 Microchip Technology Inc.
DS41302D-page 199
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢩꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦꢩꢒꢆꢓꢆꢔꢪꢔꢪꢕꢣꢤꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢩꢜꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
e
D
b
N
N
L
EXPOSED PAD
E
E2
K
NOTE 1
NOTE 1
1
2
2
1
D2
BOTTOM VIEW
TOP VIEW
A
NOTE 2
A3
A1
6ꢄꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ7
7:ꢔ
<
ꢕꢁ?ꢘꢅ1ꢐ,
ꢕꢁꢛꢕ
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
7
ꢈ
ꢗ
ꢗꢀ
ꢗ-
ꢒ
.ꢎ
.
ꢕꢁ<ꢕ
ꢕꢁꢕꢕ
ꢀꢁꢕꢕ
ꢕꢁꢕꢘ
ꢕꢁꢕꢎ
ꢕꢁꢎꢕꢅꢝ.3
-ꢁꢕꢕꢅ1ꢐ,
M
-ꢁꢕꢕꢅ1ꢐ,
M
ꢕꢁ-ꢕ
ꢕꢁ-ꢕ
M
ꢕꢁꢕꢕ
ꢀꢁ?ꢕ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢅꢂꢆ#
ꢒꢎ
)
9
ꢕꢁꢕꢕ
ꢕꢁꢎꢘ
ꢕꢁꢎꢕ
ꢕꢁꢎꢕ
ꢎꢁꢖꢕ
ꢕꢁ-ꢘ
ꢕꢁꢘꢘ
M
C
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅ'ꢆꢊꢅꢍꢆ ꢈꢅꢋꢄꢈꢅꢋꢉꢅ'ꢋꢉꢈꢅꢈ$ꢓꢋ!ꢈ#ꢅ&ꢃꢈꢅ)ꢆꢉ!ꢅꢆ&ꢅꢈꢄ#!ꢁ
-ꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢕ?ꢎ1
DS41302D-page 200
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢩꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦꢍꢒꢆꢓꢆꢫꢪꢫꢪꢕꢣꢤꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢩꢜꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
e
D
b
N
N
L
E
E2
K
EXPOSED
PAD
1
2
2
1
NOTE 1
NOTE 1
A3
D2
BOTTOM VIEW
TOP VIEW
A
A1
NOTE 2
6ꢄꢃ&!
ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢅ9ꢃ'ꢃ&!
ꢔꢚ99ꢚꢔ.ꢙ.ꢝꢐ
7:ꢔ
ꢔꢚ7
ꢔꢗ;
7"')ꢈꢉꢅꢋ%ꢅꢂꢃꢄ!
ꢂꢃ&ꢌꢍ
: ꢈꢉꢆꢇꢇꢅ8ꢈꢃꢑꢍ&
ꢐ&ꢆꢄ#ꢋ%%ꢅ
,ꢋꢄ&ꢆꢌ&ꢅꢙꢍꢃꢌ4ꢄꢈ!!
: ꢈꢉꢆꢇꢇꢅ9ꢈꢄꢑ&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ>ꢃ#&ꢍ
: ꢈꢉꢆꢇꢇꢅ>ꢃ#&ꢍ
.$ꢓꢋ!ꢈ#ꢅꢂꢆ#ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ>ꢃ#&ꢍ
,ꢋꢄ&ꢆꢌ&ꢅ9ꢈꢄꢑ&ꢍ
,ꢋꢄ&ꢆꢌ&ꢞ&ꢋꢞ.$ꢓꢋ!ꢈ#ꢅꢂꢆ#
7
ꢈ
ꢗ
ꢗꢀ
ꢗ-
ꢒ
.ꢎ
.
<
ꢕꢁ<ꢕꢅ1ꢐ,
ꢕꢁꢛꢕ
ꢕꢁꢕꢎ
ꢕꢁꢎꢕꢅꢝ.3
ꢖꢁꢕꢕꢅ1ꢐ,
ꢎꢁꢎꢕ
ꢖꢁꢕꢕꢅ1ꢐ,
-ꢁꢕꢕ
ꢕꢁ<ꢕ
ꢕꢁꢕꢕ
ꢀꢁꢕꢕ
ꢕꢁꢕꢘ
ꢕꢁꢕꢕ
ꢎꢁ<ꢕ
ꢒꢎ
)
9
ꢕꢁꢕꢕ
ꢕꢁꢎꢘ
ꢕꢁ-ꢕ
ꢕꢁꢎꢕ
-ꢁ?ꢕ
ꢕꢁ-ꢘ
ꢕꢁꢘꢕ
M
ꢕꢁ-ꢕ
ꢕꢁꢖꢕ
M
C
ꢜꢘꢊꢃꢉꢝ
ꢀꢁ ꢂꢃꢄꢅꢀꢅ ꢃ!"ꢆꢇꢅꢃꢄ#ꢈ$ꢅ%ꢈꢆ&"ꢉꢈꢅ'ꢆꢊꢅ ꢆꢉꢊ(ꢅ)"&ꢅ'"!&ꢅ)ꢈꢅꢇꢋꢌꢆ&ꢈ#ꢅ*ꢃ&ꢍꢃꢄꢅ&ꢍꢈꢅꢍꢆ&ꢌꢍꢈ#ꢅꢆꢉꢈꢆꢁ
ꢎꢁ ꢂꢆꢌ4ꢆꢑꢈꢅ'ꢆꢊꢅꢍꢆ ꢈꢅꢋꢄꢈꢅꢋꢉꢅ'ꢋꢉꢈꢅꢈ$ꢓꢋ!ꢈ#ꢅ&ꢃꢈꢅ)ꢆꢉ!ꢅꢆ&ꢅꢈꢄ#!ꢁ
-ꢁ ꢂꢆꢌ4ꢆꢑꢈꢅꢃ!ꢅ!ꢆ*ꢅ!ꢃꢄꢑ"ꢇꢆ&ꢈ#ꢁ
ꢖꢁ ꢒꢃ'ꢈꢄ!ꢃꢋꢄꢃꢄꢑꢅꢆꢄ#ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢃꢄꢑꢅꢓꢈꢉꢅꢗꢐꢔ.ꢅ0ꢀꢖꢁꢘꢔꢁ
1ꢐ,2 1ꢆ!ꢃꢌꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄꢁꢅꢙꢍꢈꢋꢉꢈ&ꢃꢌꢆꢇꢇꢊꢅꢈ$ꢆꢌ&ꢅ ꢆꢇ"ꢈꢅ!ꢍꢋ*ꢄꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ!ꢁ
ꢝ.32 ꢝꢈ%ꢈꢉꢈꢄꢌꢈꢅꢒꢃ'ꢈꢄ!ꢃꢋꢄ(ꢅ"!"ꢆꢇꢇꢊꢅ*ꢃ&ꢍꢋ"&ꢅ&ꢋꢇꢈꢉꢆꢄꢌꢈ(ꢅ%ꢋꢉꢅꢃꢄ%ꢋꢉ'ꢆ&ꢃꢋꢄꢅꢓ"ꢉꢓꢋ!ꢈ!ꢅꢋꢄꢇꢊꢁ
ꢔꢃꢌꢉꢋꢌꢍꢃꢓ ꢙꢈꢌꢍꢄꢋꢇꢋꢑꢊ ꢒꢉꢆ*ꢃꢄꢑ ,ꢕꢖꢞꢀ-ꢀꢒ
2010 Microchip Technology Inc.
DS41302D-page 201
PIC12F609/615/617/12HV609/615
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢩꢈꢄꢊꢢꢆꢜꢘꢆꢂꢃꢄꢅꢆꢇꢄꢌꢧꢄꢨꢃꢆꢑꢦDꢒꢆꢓꢆꢫꢪꢫꢪꢕꢣꢤꢆꢖꢖꢆꢗꢘꢅꢙꢆꢚꢍꢩꢜꢛ
ꢜꢘꢊꢃꢝ 3ꢋꢉꢅ&ꢍꢈꢅ'ꢋ!&ꢅꢌ"ꢉꢉꢈꢄ&ꢅꢓꢆꢌ4ꢆꢑꢈꢅ#ꢉꢆ*ꢃꢄꢑ!(ꢅꢓꢇꢈꢆ!ꢈꢅ!ꢈꢈꢅ&ꢍꢈꢅꢔꢃꢌꢉꢋꢌꢍꢃꢓꢅꢂꢆꢌ4ꢆꢑꢃꢄꢑꢅꢐꢓꢈꢌꢃ%ꢃꢌꢆ&ꢃꢋꢄꢅꢇꢋꢌꢆ&ꢈ#ꢅꢆ&ꢅ
ꢍ&&ꢓ255***ꢁ'ꢃꢌꢉꢋꢌꢍꢃꢓꢁꢌꢋ'5ꢓꢆꢌ4ꢆꢑꢃꢄꢑ
DS41302D-page 202
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: MIGRATING FROM
OTHER PIC®
DEVICES
Revision A
This discusses some of the issues in migrating from
other PIC devices to the PIC12F6XX Family of devices.
This is a new data sheet.
Revision B (05/2008)
B.1
PIC12F675 to PIC12F609/615/
12HV609/615
Added Graphs. Revised 28-Pin ICD Pinout, Electrical
Specifications Section, Package Details.
TABLE B-1:
Feature
FEATURE COMPARISON
Revision C (09/2009)
PIC12F609/
PIC12F675
615/
Updated adding the PIC12F617 device throughout the
entire data sheet; Added Figure 2-2 to Memory
12HV609/615
Organization section; Added section
3 ”FLASH
Max Operating Speed
20 MHz
1024
20 MHz
1024
PROGRAM MEMORY SELF READ/SELF WRITE
CONTROL (FOR PIC12F617 ONLY)”; Updated
Register 12-1; Updated Table12-5 adding PMCON1,
PMCON2, PMADRL, PMADRH, PMDATL, PMDATH;
Added section 16-12 in the Electrical Specification
section; Other minor edits.
Max Program
Memory (Words)
SRAM (bytes)
A/D Resolution
64
64
10-bit
10-bit (615
only)
Timers (8/16-bit)
1/1
2/1 (615)
1/1 (609)
Revision D (01/2010)
Oscillator Modes
Brown-out Reset
Internal Pull-ups
8
8
Updated
Figure
17-50;
Revised
16.8
DC
Characteristics; Removed Preliminary Status.
Y
Y
RA0/1/2/4/5 GP0/1/2/4/5,
MCLR
Interrupt-on-change
Comparator
RA0/1/2/3/4/5 GP0/1/2/3/4/5
1
N
1
ECCP
Y (615)
4/8 MHz
INTOSC Frequencies
4 MHz
N
Internal Shunt
Regulator
Y
(PIC12HV609/
615)
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
2010 Microchip Technology Inc.
DS41302D-page 203
PIC12F609/615/617/12HV609/615
NOTES:
DS41302D-page 204
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
INDEX
PIC12F609/12HV609 ................................................... 7
PIC12F615/617/12HV615 ............................................ 8
PWM (Enhanced) ....................................................... 97
A
A/D
Specifications.................................................... 164, 165
Resonator Operation .................................................. 39
Timer1 .................................................................. 57, 58
Timer2 ........................................................................ 65
TMR0/WDT Prescaler ................................................ 53
Watchdog Timer ....................................................... 122
Brown-out Reset (BOR).................................................... 112
Associated Registers................................................ 113
Specifications ........................................................... 160
Timing and Characteristics....................................... 159
Absolute Maximum Ratings .............................................. 143
AC Characteristics
Industrial and Extended ............................................ 156
Load Conditions........................................................ 155
ADC
Acquisition Requirements ........................................... 86
Associated registers.................................................... 88
Block Diagram............................................................. 79
Calculating Acquisition Time....................................... 86
Channel Selection....................................................... 80
Configuration............................................................... 80
Configuring Interrupt ................................................... 83
Conversion Clock........................................................ 80
Conversion Procedure ................................................ 83
Internal Sampling Switch (RSS) Impedance................ 86
Interrupts..................................................................... 81
Operation .................................................................... 82
Operation During Sleep .............................................. 82
Port Configuration....................................................... 80
Reference Voltage (VREF)........................................... 80
Result Formatting........................................................ 82
Source Impedance...................................................... 86
Special Event Trigger.................................................. 82
Starting an A/D Conversion ........................................ 82
ADC (PIC12F615/617/HV615 Only) ................................... 79
ADCON0 Register............................................................... 84
ADRESH Register (ADFM = 0)........................................... 85
ADRESH Register (ADFM = 1)........................................... 85
ADRESL Register (ADFM = 0)............................................ 85
ADRESL Register (ADFM = 1)............................................ 85
Analog Input Connection Considerations............................ 68
Analog-to-Digital Converter. See ADC
C
C Compilers
MPLAB C18.............................................................. 140
MPLAB C30.............................................................. 140
Calibration Bits.................................................................. 109
Capture Module. See Enhanced Capture/Compare/
PWM (ECCP)
Capture/Compare/PWM (CCP)
Associated registers w/ Capture................................. 91
Associated registers w/ Compare............................... 93
Associated registers w/ PWM................................... 105
Capture Mode............................................................. 90
CCP1 Pin Configuration ............................................. 90
Compare Mode........................................................... 92
CCP1 Pin Configuration ..................................... 92
Software Interrupt Mode............................... 90, 92
Special Event Trigger......................................... 92
Timer1 Mode Selection................................. 90, 92
Prescaler .................................................................... 90
PWM Mode................................................................. 94
Duty Cycle .......................................................... 95
Effects of Reset.................................................. 96
Example PWM Frequencies and
ANSEL Register (PIC12F609/HV609) ................................ 45
ANSEL Register (PIC12F615/617/HV615) ......................... 45
APFCON Register............................................................... 24
Assembler
Resolutions, 20 MHZ.................................. 95
Example PWM Frequencies and
Resolutions, 8 MHz .................................... 95
Operation in Sleep Mode.................................... 96
Setup for Operation ............................................ 96
System Clock Frequency Changes .................... 96
PWM Period ............................................................... 95
Setup for PWM Operation .......................................... 96
CCP1CON (Enhanced) Register ........................................ 89
Clock Sources
External Modes........................................................... 38
EC ...................................................................... 38
HS ...................................................................... 39
LP....................................................................... 39
OST .................................................................... 38
RC ...................................................................... 40
XT....................................................................... 39
Internal Modes............................................................ 40
INTOSC.............................................................. 40
INTOSCIO .......................................................... 40
CMCON0 Register.............................................................. 72
CMCON1 Register.............................................................. 73
Code Examples
MPASM Assembler................................................... 140
B
Block Diagrams
(CCP) Capture Mode Operation ................................. 90
ADC ............................................................................ 79
ADC Transfer Function ............................................... 87
Analog Input Model............................................... 68, 87
Auto-Shutdown ......................................................... 101
CCP PWM................................................................... 94
Clock Source............................................................... 37
Comparator................................................................. 67
Compare ..................................................................... 92
Crystal Operation........................................................ 39
External RC Mode....................................................... 40
GP0 and GP1 Pins...................................................... 47
GP2 Pins..................................................................... 48
GP3 Pin....................................................................... 49
GP4 Pin....................................................................... 50
GP5 Pin....................................................................... 51
In-Circuit Serial Programming Connections.............. 125
Interrupt Logic........................................................... 119
MCLR Circuit............................................................. 111
On-Chip Reset Circuit............................................... 110
A/D Conversion .......................................................... 83
Assigning Prescaler to Timer0.................................... 54
Assigning Prescaler to WDT....................................... 54
Changing Between Capture Prescalers ..................... 90
Indirect Addressing..................................................... 25
2010 Microchip Technology Inc.
DS41302D-page 205
PIC12F609/615/617/12HV609/615
Initializing GPIO ..........................................................43
Saving Status and W Registers in RAM ...................121
Writing to Flash Program Memory ..............................34
Code Protection ................................................................124
Comparator .........................................................................67
Associated registers....................................................78
Control ........................................................................69
Gating Timer1 .............................................................73
Operation During Sleep ..............................................71
Overview .....................................................................67
Response Time...........................................................69
Synchronizing COUT w/Timer1 ..................................73
Comparator Hysteresis .......................................................77
Comparator Voltage Reference (CVREF) ............................74
Effects of a Reset........................................................71
Comparator Voltage Reference (CVREF)
Timer Resources ........................................................ 89
Enhanced Capture/Compare/PWM
(PIC12F615/617/HV615 Only).................................... 89
Errata.................................................................................... 6
F
Firmware Instructions ....................................................... 129
Flash Program Memory Self Read/Self Write
Control (For PIC12F617 only)..................................... 27
Fuses. See Configuration Bits
G
General Purpose Register File ........................................... 12
GPIO................................................................................... 43
Additional Pin Functions ............................................. 44
ANSEL Register ................................................. 44
Interrupt-on-Change ........................................... 44
Weak Pull-Ups.................................................... 44
Response Time...........................................................69
Comparator Voltage Reference (CVREF)
Associated registers ................................................... 52
GP0 ............................................................................ 47
GP1 ............................................................................ 47
GP2 ............................................................................ 48
GP3 ............................................................................ 49
GP4 ............................................................................ 50
GP5 ............................................................................ 51
Pin Descriptions and Diagrams .................................. 47
Specifications ........................................................... 158
GPIO Register .................................................................... 43
Specifications............................................................163
Comparators
C2OUT as T1 Gate .....................................................60
Effects of a Reset........................................................71
Specifications............................................................162
Compare Module. See Enhanced Capture/Compare/
PWM (ECCP) (PIC12F615/617/HV615 only)
CONFIG Register..............................................................108
Configuration Bits..............................................................107
CPU Features ...................................................................107
Customer Change Notification Service .............................209
Customer Notification Service...........................................209
Customer Support.............................................................209
H
High Temperature Operation............................................ 167
I
D
ID Locations...................................................................... 124
In-Circuit Debugger........................................................... 125
In-Circuit Serial Programming (ICSP)............................... 125
Indirect Addressing, INDF and FSR registers..................... 25
Instruction Format............................................................. 129
Instruction Set................................................................... 129
ADDLW..................................................................... 131
ADDWF..................................................................... 131
ANDLW..................................................................... 131
ANDWF..................................................................... 131
MOVF ....................................................................... 134
BCF .......................................................................... 131
BSF........................................................................... 131
BTFSC...................................................................... 131
BTFSS ...................................................................... 132
CALL......................................................................... 132
CLRF ........................................................................ 132
CLRW ....................................................................... 132
CLRWDT .................................................................. 132
COMF ....................................................................... 132
DECF........................................................................ 132
DECFSZ ................................................................... 133
GOTO ....................................................................... 133
INCF ......................................................................... 133
INCFSZ..................................................................... 133
IORLW...................................................................... 133
IORWF...................................................................... 133
MOVLW .................................................................... 134
MOVWF.................................................................... 134
NOP.......................................................................... 134
RETFIE..................................................................... 135
RETLW ..................................................................... 135
RETURN................................................................... 135
Data EEPROM Memory
Associated Registers ..................................................35
Data Memory.......................................................................11
DC and AC Characteristics
Graphs and Tables ...................................................171
DC Characteristics
Extended and Industrial ............................................152
Industrial and Extended ............................................145
Development Support .......................................................139
Device Overview ...................................................................7
E
ECCP. See Enhanced Capture/Compare/PWM
ECCPAS Register.............................................................102
EEDAT Register..................................................................28
EEDATH Register ...............................................................28
Effects of Reset
PWM mode .................................................................96
Electrical Specifications ....................................................143
Enhanced Capture/Compare/PWM (ECCP)
Enhanced PWM Mode ................................................97
Auto-Restart......................................................103
Auto-shutdown..................................................101
Half-Bridge Application .......................................99
Half-Bridge Application Examples.....................104
Half-Bridge Mode................................................99
Output Relationships (Active-High and
Active-Low) .................................................98
Output Relationships Diagram............................98
Programmable Dead Band Delay .....................104
Shoot-through Current ......................................104
Start-up Considerations ....................................100
Specifications............................................................162
DS41302D-page 206
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
RLF ........................................................................... 136
Oscillator Parameters ....................................................... 157
Oscillator Specifications.................................................... 156
Oscillator Start-up Timer (OST)
Specifications ........................................................... 160
OSCTUNE Register............................................................ 41
RRF........................................................................... 136
SLEEP ...................................................................... 136
SUBLW ..................................................................... 136
SUBWF..................................................................... 137
SWAPF ..................................................................... 137
XORLW..................................................................... 137
XORWF..................................................................... 137
Summary Table......................................................... 130
INTCON Register................................................................ 20
Internal Oscillator Block
P
P1A/P1B/P1C/P1D.See Enhanced Capture/Compare/
PWM (ECCP) ............................................................. 97
Packaging......................................................................... 195
Marking..................................................................... 195
PDIP Details ............................................................. 196
PCL and PCLATH............................................................... 25
Stack........................................................................... 25
PCON Register........................................................... 23, 113
PICSTART Plus Development Programmer..................... 142
PIE1 Register ..................................................................... 21
Pin Diagram
INTOSC
Specifications............................................ 157, 158
Internal Sampling Switch (RSS) Impedance........................ 86
Internet Address................................................................ 209
Interrupts........................................................................... 118
ADC ............................................................................ 83
Associated Registers ................................................ 120
Context Saving.......................................................... 121
GP2/INT.................................................................... 118
GPIO Interrupt-on-Change........................................ 119
Interrupt-on-Change.................................................... 44
Timer0....................................................................... 119
TMR1 .......................................................................... 60
INTOSC Specifications ............................................. 157, 158
IOC Register ....................................................................... 46
PIC12F609/HV609 (PDIP, SOIC, MSOP, DFN)........... 4
PIC12F615/617/HV615 (PDIP, SOIC, MSOP, DFN).... 5
Pinout Descriptions
PIC12F609/12HV609 ................................................... 9
PIC12F615/617/12HV615 .......................................... 10
PIR1 Register ..................................................................... 22
PMADRH and PMADRL Registers..................................... 27
PMCON1 and PMCON2 Registers..................................... 27
Power-Down Mode (Sleep)............................................... 123
Power-on Reset (POR)..................................................... 111
Power-up Timer (PWRT).................................................. 111
Specifications ........................................................... 160
Precision Internal Oscillator Parameters .......................... 158
Prescaler
Shared WDT/Timer0................................................... 54
Switching Prescaler Assignment ................................ 54
Program Memory................................................................ 11
Map and Stack............................................................ 11
Programming, Device Instructions.................................... 129
Protection Against Spurious Write...................................... 32
PWM Mode. See Enhanced Capture/Compare/PWM........ 97
PWM1CON Register......................................................... 105
L
Load Conditions................................................................ 155
M
MCLR................................................................................ 111
Internal...................................................................... 111
Memory Organization.......................................................... 11
Data ............................................................................ 11
Program ...................................................................... 11
Microchip Internet Web Site.............................................. 209
Migrating from other PICmicro Devices ............................ 203
MPLAB ASM30 Assembler, Linker, Librarian ................... 140
MPLAB ICD 2 In-Circuit Debugger ................................... 141
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator .................................................... 141
MPLAB Integrated Development Environment Software .. 139
MPLAB PM3 Device Programmer .................................... 141
MPLAB REAL ICE In-Circuit Emulator System................. 141
MPLINK Object Linker/MPLIB Object Librarian ................ 140
R
Reader Response............................................................. 210
Reading the Flash Program Memory.................................. 30
Read-Modify-Write Operations ......................................... 129
Registers
ADCON0 (ADC Control 0).......................................... 84
ADRESH (ADC Result High) with ADFM = 0) ............ 85
ADRESH (ADC Result High) with ADFM = 1) ............ 85
ADRESL (ADC Result Low) with ADFM = 0).............. 85
ADRESL (ADC Result Low) with ADFM = 1).............. 85
ANSEL (Analog Select) .............................................. 45
APFCON (Alternate Pin Function Register) ............... 24
CCP1CON (Enhanced CCP1 Control) ....................... 89
CMCON0 (Comparator Control 0).............................. 72
CMCON1 (Comparator Control 1).............................. 73
CONFIG (Configuration Word) ................................. 108
Data Memory Map (PIC12F609/HV609) .................... 12
Data Memory Map (PIC12F615/617/HV615) ............. 13
ECCPAS (Enhanced CCP Auto-shutdown Control). 102
EEDAT (EEPROM Data)............................................ 28
EEDATH (EEPROM Data) ......................................... 28
GPIO........................................................................... 43
INTCON (Interrupt Control) ........................................ 20
IOC (Interrupt-on-Change GPIO) ............................... 46
OPTION_REG (OPTION)........................................... 19
O
OPCODE Field Descriptions............................................. 129
Operation During Code Protect........................................... 32
Operation During Write Protect........................................... 32
Operational Amplifier (OPA) Module
AC Specifications...................................................... 163
OPTION Register................................................................ 19
OPTION_REG Register ...................................................... 55
Oscillator
Associated registers.............................................. 41, 63
Oscillator Module .......................................................... 27, 37
EC............................................................................... 37
HS............................................................................... 37
INTOSC ...................................................................... 37
INTOSCIO................................................................... 37
LP................................................................................ 37
RC............................................................................... 37
RCIO........................................................................... 37
XT ............................................................................... 37
2010 Microchip Technology Inc.
DS41302D-page 207
PIC12F609/615/617/12HV609/615
OPTION_REG (Option) ..............................................55
OSCTUNE (Oscillator Tuning)....................................41
PCON (Power Control Register).................................23
PCON (Power Control) .............................................113
PIE1 (Peripheral Interrupt Enable 1)...........................21
PIR1 (Peripheral Interrupt Register 1) ........................22
PWM1CON (Enhanced PWM Control) .....................105
Reset Values (PIC12F609/HV609) ...........................115
Reset Values (PIC12F615/617/HV615) ....................116
Reset Values (special registers) ...............................117
Special Function Registers .........................................12
Special Register Summary (PIC12F609/HV609).. 14, 16
Special Register Summary
Timer2 (PIC12F615/617/HV615 Only)
Associated registers ................................................... 66
Timers
Timer1
T1CON ............................................................... 62
Timer2
T2CON ............................................................... 66
Timing Diagrams
A/D Conversion......................................................... 165
A/D Conversion (Sleep Mode).................................. 166
Brown-out Reset (BOR)............................................ 159
Brown-out Reset Situations ...................................... 112
CLKOUT and I/O ...................................................... 158
Clock Timing............................................................. 156
Comparator Output..................................................... 67
Enhanced Capture/Compare/PWM (ECCP)............. 162
Half-Bridge PWM Output .................................... 99, 104
INT Pin Interrupt ....................................................... 120
PWM Auto-shutdown
Auto-restart Enabled......................................... 103
Firmware Restart.............................................. 103
PWM Output (Active-High) ......................................... 98
PWM Output (Active-Low).......................................... 98
Reset, WDT, OST and Power-up Timer................... 159
Time-out Sequence
(PIC12F615/617/HV615) .............................. 15, 17
STATUS......................................................................18
T1CON........................................................................62
T2CON........................................................................66
TRISIO (Tri-State GPIO).............................................44
VRCON (Voltage Reference Control) .........................76
WPU (Weak Pull-Up GPIO) ........................................46
Reset.................................................................................110
Revision History ................................................................203
S
Shoot-through Current ......................................................104
Sleep
Case 1 .............................................................. 114
Case 2 .............................................................. 114
Case 3 .............................................................. 114
Timer0 and Timer1 External Clock ........................... 161
Timer1 Incrementing Edge ......................................... 61
Wake-up from Interrupt............................................. 124
Timing Parameter Symbology .......................................... 155
TRISIO................................................................................ 43
TRISIO Register ................................................................. 44
Power-Down Mode ...................................................123
Wake-up....................................................................123
Wake-up using Interrupts..........................................123
Software Simulator (MPLAB SIM).....................................140
Special Event Trigger..........................................................82
Special Function Registers .................................................12
STATUS Register................................................................18
T
V
T1CON Register..................................................................62
T2CON Register..................................................................66
Thermal Considerations....................................................154
Time-out Sequence...........................................................113
Timer0.................................................................................53
Associated Registers ..................................................55
External Clock.............................................................54
Interrupt.......................................................................55
Operation .............................................................. 53, 57
Specifications............................................................161
T0CKI..........................................................................54
Timer1.................................................................................57
Associated registers....................................................63
Asynchronous Counter Mode .....................................59
Reading and Writing ...........................................59
Comparator Synchronization ......................................61
ECCP Special Event Trigger
Voltage Reference (VR)
Specifications ........................................................... 163
Voltage Reference. See Comparator Voltage
Reference (CVREF)
Voltage References
Associated registers ................................................... 78
VP6 Stabilization ........................................................ 74
VREF. SEE ADC Reference Voltage
W
Wake-up Using Interrupts................................................. 123
Watchdog Timer (WDT).................................................... 121
Associated registers ................................................. 122
Specifications ........................................................... 160
WPU Register..................................................................... 46
Writing the Flash Program Memory.................................... 32
WWW Address ................................................................. 209
WWW, On-Line Support ....................................................... 6
(PIC12F615/617/HV615 Only)............................61
ECCP Time Base (PIC12F615/617/HV615 Only).......60
Interrupt.......................................................................60
Modes of Operation ....................................................57
Operation During Sleep ..............................................60
Oscillator.....................................................................59
Prescaler.....................................................................59
Specifications............................................................161
Timer1 Gate
Inverting Gate .....................................................60
Selecting Source...........................................60, 73
Synchronizing COUT w/Timer1 ..........................73
TMR1H Register .........................................................57
TMR1L Register..........................................................57
DS41302D-page 208
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
THE MICROCHIP WEB SITE
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2010 Microchip Technology Inc.
DS41302D-page 209
PIC12F609/615/617/12HV609/615
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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PIC12F609/615/617/12HV609/615
DS41302D
Literature Number:
Device:
Questions:
1. What are the best features of this document?
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3. Do you find the organization of this document easy to follow? If not, why?
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DS41302D-page 210
2010 Microchip Technology Inc.
PIC12F609/615/617/12HV609/615
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature
Range
Package
Pattern
a)
b)
c)
d)
e)
f)
PIC12F615-E/P 301 = Extended Temp., PDIP
package, 20 MHz, QTP pattern #301
PIC12F615-I/SN = Industrial Temp., SOIC
package, 20 MHz
PIC12F615T-E/MF = Tape and Reel, Extended
Temp., 3x3 DFN, 20 MHz
Device:
PIC12F609, PIC12F609T(1), PIC12HV609, PIC12HV609T(1)
PIC12F615, PIC12F615T(1), PIC12HV615, PIC12HV615T(1)
PIC12F617, PIC12F617T(1)
,
,
PIC12F609T-E/MF = Tape and Reel, Extended
Temp., 3x3 DFN, 20 MHz
PIC12HV615T-E/MF = Tape and Reel,
Extended Temp., 3x3 DFN, 20 MHz
PIC12HV609T-E/MF = Tape and Reel,
Extended Temp., 3x3 DFN, 20 MHz
PIC12F617T-E/MF = Tape and Reel, Extended
Temp., 3x3 DFN, 20 MHz
PIC12F617-I/P = Industrial Temp., PDIP pack-
age, 20 MHz
PIC12F615-H/SN = High Temp., SOIC pack-
age, 20 MHz
Temperature
Range:
H
I
E
=
=
=
-40C to +150C (High Temp)(3)
-40C to +85C (Industrial)
-40C to +125C (Extended)
g)
h)
i)
Package:
P
=
Plastic DIP (PDIP)
SN
MS
MF
MD
=
=
=
=
8-lead Small Outline (150 mil) (SOIC)
Micro Small Outline (MSOP)
8-lead Plastic Dual Flat, No Lead (3x3) (DFN)
8-lead Plastic Dual Flat, No Lead
(4x4)(DFN)(1,2)
Note 1:
T
= in tape and reel for MSOP, SOIC and
DFN packages only.
2:
3:
Not available for PIC12F617.
High Temp. available for PIC12F615 only.
Pattern:
QTP, SQTP or ROM Code; Special Requirements
(blank otherwise)
2010 Microchip Technology Inc.
DS41302D-page 211
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Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/05/10
DS41302D-page 212
2010 Microchip Technology Inc.
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