PIC12F639-E/SN_技术文档

PIC12F635/PIC16F636/639

Data Sheet

8/14-Pin, Flash-Based 8-Bit

CMOS Microcontrollers

with nanoWatt Technology

*8-bit, 8-pin Devices Protected by Microchip’s Low Pin Count Patent: U. S. Patent No. 5,847,450. Additional U.S. and

foreign patents and applications may be issued or pending.

DS41232D

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Linear Active Thermistor, Migratable

Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor

and The Embedded Control Solutions Company are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,

MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC^®DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS41232D-page ii

PIC12F635/PIC16F636/639

8/14-Pin Flash-Based, 8-Bit CMOS Microcontrollers

With nanoWatt Technology

High-Performance RISC CPU:

Peripheral Features:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

• 6/12 I/O pins with individual direction control:

- High-current source/sink for direct LED drive

- Interrupt-on-change pin

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt capability

- Individually programmable weak pull-ups/

pull-downs

- Ultra Low-Power Wake-up

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

• Analog Comparator module with:

- Up to two analog comparators

- Programmable On-chip Voltage Reference

(CVREF) module (% of VDD)

- Comparator inputs and outputs externally

accessible

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator if INTOSC mode

selected

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range of

8 MHz to 125 kHz

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

• Clock mode switching for low-power operation

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended Temperature range

• Power-on Reset (POR)

• KEELOQ^®compatible hardware Cryptographic

module

• In-Circuit Serial Programming™ (ICSP™) via

two pins

• Wake-up Reset (WUR)

• Independent weak pull-up/pull-down resistors

• Programmable Low-Voltage Detect (PLVD)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR) with software control

option

• Enhanced Low-Current Watchdog Timer (WDT)

with on-chip oscillator (software selectable

nominal 268 seconds with full prescaler) with

software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection (program and

data independent)

Low-Frequency Analog Front-End

Features (PIC16F639 only):

• Three input pins for 125 kHz LF input signals

• High input detection sensitivity (3 mVPP, typical)

• Demodulated data, Carrier clock or RSSI output

selection

• Input carrier frequency: 125 kHz, typical

• Input modulation frequency: 4 kHz, maximum

• 8 internal Configuration registers

• Bidirectional transponder communication

(LF talk back)

• Programmable antenna tuning capacitance

(up to 63 pF, 1 pF/step)

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

• Low standby current: 5 μA (with 3 channels

enabled), typical

• Low operating current: 15 μA (with 3 channels

enabled), typical

• Serial Peripheral Interface (SPI) with internal

MCU and external devices

• Supports Battery Back-up mode and batteryless

operation with external circuits

Low-Power Features:

• Standby Current:

- 1 nA @ 2.0V, typical

• Operating Current:

- 8.5 μA @ 32 kHz, 2.0V, typical

- 100 μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

- 1 μA @ 2.0V, typical

DS41232D-page 1

PIC12F635/PIC16F636/639

Program Memory

Flash (words)

Data Memory

LowFrequency

Analog

Device

I/O

Comparators

SRAM (bytes)

EEPROM (bytes)

Front-End

PIC12F635

PIC16F636

PIC16F639

1024

2048

64

128

256

6

1

2

N

Y

128

12

Note 1: Any references to PORTA, RAn, TRISA and TRISAn refer to GPIO, GPn, TRISIO and TRISIOn, respectively.

2: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

this document unless otherwise stated.

3: VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated

as VSS in this document unless otherwise stated.

DS41232D-page 2

PIC12F635/PIC16F636/639

8-Pin Diagrams (PDIP, SOIC, DFN, DFN-S)

PDIP, SOIC

VDD

GP5/T1CKI/OSC1/CLKIN

GP4/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

1

2

VSS

8

7

GP0/C1IN+/ICSPDAT/ULPWU

GP1/C1IN-/ICSPCLK

GP2/T0CKI/INT/C1OUT

3

4

6

5

DFN, DFN-S

VDD

GP5/T1CKI/OSC1/CLKIN

GP4/T1G/OSC2/CLKOUT

GP3/MCLR/VDD

VSS

8

7

6

5

1

2

GP0/CIN+/ICSPDAT/ULPWU

GP1/CIN-/ICSPCLK

GP2/T0CKI/INT/COUT

3

4

TABLE 1:

I/O

8-PIN SUMMARY (PDIP, SOIC, DFN, DFN-S)

Comparators

Timer

Interrupts

Pull-ups

Basic

GP0

7

6

5

C1IN+

C1IN-

—

IOC

Y

ICSPDAT/ULPWU

GP1

ICSPCLK

—

GP2

C1OUT

T0CKI

INT/IOC

GP3⁽¹⁾

4

3

2

1

8

—

T1G

T1CKI

—

IOC

—

Y⁽²⁾

Y

MCLR/VPP

OSC2/CLKOUT

OSC1/CLKIN

VDD

GP4

GP5

—

Y

—

VSS

Note 1: Input only.

2: Only when pin is configured for external MCLR.

DS41232D-page 3

PIC12F635/PIC16F636/639

14-Pin Diagram (PDIP, SOIC, TSSOP)

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

1

2

3

4

5

6

7

VSS

14

13

12

11

10

9

RA0/C1IN+/ICSPDAT/ULPWU

RA1/C1IN-/VREF/ICSPCLK

RA2/T0CKI/INT/C1OUT

RC0/C2IN+

RC1/C2IN-

RC2

RC4/C2OUT

RC3

8

TABLE 2:

I/O

14-PIN SUMMARY (PDIP, SOIC, TSSOP)

Comparators

Timer

Interrupts

Pull-ups

Basic

RA0

13

12

11

C1IN+

C1IN-

—

IOC

Y

ICSPDAT/ULPWU

VREF/ICSPCLK

—

RA1

RA2

C1OUT

T0CKI

INT/IOC

RA3⁽¹⁾

4

3

—

T1G

T1CKI

—

IOC

—

Y⁽²⁾

Y

MCLR/VPP

RA4

RA5

RC0

RC1

RC2

RC3

RC4

RC5

—

OSC2/CLKOUT

2

—

Y

OSC1/CLKIN

10

9

C2IN+

C2IN-

—

8

—

7

—

6

C2OUT

—

5

—

1

—

VDD

VSS

—

14

—

Note 1: Input only.

2: Only when pin is configured for external MCLR.

DS41232D-page 4

PIC12F635/PIC16F636/639

16-Pin Diagram

QFN

12

11

10

9

RA0/C1IN+/ICSPDAT/ULPWU

RA1/C1IN-/VREF/ICSPCLK

RA5/T1CKI/OSC1/CLKIN

1

2

3

4

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RC5

PIC16F636

RA2/T0CKI/INT/C1OUT

RC0/C2IN+

TABLE 3:

I/O

RA0

16-PIN SUMMARY

Comparators

Timer

Interrupts

Pull-ups

Basic

12

11

10

C1IN+

C1IN-

—

IOC

Y

ICSPDAT/ULPWU

VREF/ICSPCLK

—

RA1

RA2

C1OUT

T0CKI

INT/IOC

RA3⁽¹⁾

3

2

—

T1G

T1CKI

—

IOC

—

Y⁽²⁾

Y

MCLR/VPP

RA4

RA5

RC0

RC1

RC2

RC3

RC4

RC5

—

OSC2/CLKOUT

1

—

Y

OSC1/CLKIN

9

C2IN+

C2IN-

—

8

—

7

—

6

—

5

C2OUT

—

4

—

16

13

14

15

—

VDD

VSS

NC

—

Note 1: Input only.

2: Only when pin is configured for external MCLR.

DS41232D-page 5

PIC12F635/PIC16F636/639

20-Pin Diagram

SSOP

1

2

3

4

5

6

7

8

9

10

20

19

18

VDD

RA5/T1CKI/OSC1/CLKIN

RA4/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

VSS

RA0/C1IN+/ICSPDAT/ULPWU

RA1/C1IN-/VREF/ICSPCLK

RA2/TOCKI/INT/C1OUT

RC0/C2IN+

17

16

RC5

15

14

13

12

11

RC4/C2OUT

RC1/C2IN-/CS

RC3/LFDATA/RSSI/CCLK/SDIO

RC2/SCLK/ALERT

(3)

(4)

VDDT

VSST

LCZ

LCY

LCCOM

LCX

TABLE 4:

20-PIN SUMMARY

I/O

Analog Front-End Comparators

Timer

Interrupts

Pull-ups

Basic

RA0

19

18

17

—

C1IN+

C1IN-

—

IOC

Y

ICSPDAT/ULPWU

VREF/ICSPCLK

—

RA1

RA2

C1OUT

T0CKI

INT/IOC

RA3⁽¹⁾

4

3

—

T1G

T1CKI

—

IOC

—

Y⁽²⁾

Y

MCLR/VPP

RA4

RA5

RC0

RC1

RC2

RC3

RC4

RC5

—

OSC2/CLKOUT

2

—

Y

OSC1/CLKIN

16

15

14

7

—

C2IN+

C2IN-

—

CS

—

ALERT

—

SCLK

CCLK/SDIO

—

LFDATA/RSSI

—

6

—

C2OUT

—

5

—

(3)

8

—

VDDT

(4)

—

13

11

10

9

—

VSST

—

LCX

LCY

LCZ

LCCOM

—

12

1

—

VDD

VSS

—

20

—

Note 1: Input only.

2: Only when pin is configured for external MCLR.

3: VDDT is the supply voltage of the Analog Front-End section (PIC16F639 only). VDDT is treated as VDD in

this document unless otherwise stated.

4: VSST is the ground reference voltage of the Analog Front-End section (PIC16F639 only). VSST is treated

as VSS in this document unless otherwise stated.

DS41232D-page 6

PIC12F635/PIC16F636/639

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 9

2.0 Memory Organization................................................................................................................................................................. 17

3.0 Clock Sources ............................................................................................................................................................................ 35

4.0 I/O Ports ..................................................................................................................................................................................... 47

5.0 Timer0 Module ........................................................................................................................................................................... 61

6.0 Timer1 Module with Gate Control............................................................................................................................................... 64

7.0 Comparator Module.................................................................................................................................................................... 71

8.0 Programmable Low-Voltage Detect (PLVD) Module.................................................................................................................. 87

9.0 Data EEPROM Memory ............................................................................................................................................................. 91

®

10.0 KEELOQ Compatible Cryptographic Module ............................................................................................................................. 95

11.0 Analog Front-End (AFE) Functional Description (PIC16F639 Only) .......................................................................................... 97

12.0 Special Features of the CPU.................................................................................................................................................... 129

13.0 Instruction Set Summary.......................................................................................................................................................... 149

14.0 Development Support............................................................................................................................................................... 159

15.0 Electrical Specifications............................................................................................................................................................ 163

16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 191

17.0 Packaging Information.............................................................................................................................................................. 211

On-Line Support

223

Systems Information and Upgrade Hot Line ..................................................................................................................................... 223

Reader Response............................................................................................................................................................................. 224

Appendix A: Data Sheet Revision History......................................................................................................................................... 225

Product Identification System ........................................................................................................................................................... 231

Worldwide Sales and Service ........................................................................................................................................................... 232

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•

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DS41232D-page 7

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 8

PIC12F635/PIC16F636/639

Block Diagrams and pinout descriptions of the devices

are as follows:

1.0

DEVICE OVERVIEW

This document contains device specific information for

the PIC12F635/PIC16F636/639 devices.

• PIC12F635 (Figure 1-1, Table 1-1)

• PIC16F636 (Figure 1-2, Table 1-2)

• PIC16F639 (Figure 1-3, Table 1-3)

FIGURE 1-1:

PIC12F635 BLOCK DIAGRAM

Configuration

13

8

GPIO

Data Bus

Program Counter

GP0

GP1

GP2

GP3

GP4

GP5

Flash

1K x 14

Program

RAM

64 bytes

8-level Stack

Memory

(13-bit)

File

Registers

Program

Bus

14

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

7

Direct Addr

8

FSR Reg

STATUS Reg

8

3

MUX

Power-up

Timer

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

Power-on

Reset

OSC1/CLKIN

8

Timing

Generation

Watchdog

Timer

Brown-out

Reset

W Reg

OSC2/CLKOUT

Programmable

8 MHz

Internal

Oscillator Oscillator

31 kHz

Internal

Low-Voltage Detect

Wake-up

Reset

T1G

VDD VSS

MCLR

T1CKI

Timer0

Timer1

T0CKI

Cryptographic

Module

1 Analog

Comparator

and Reference

EEDAT

128 bytes

Data

EEPROM

EEADDR

C1IN- C1IN+ C1OUT

DS41232D-page 9

PIC12F635/PIC16F636/639

FIGURE 1-2:

PIC16F636 BLOCK DIAGRAM

Configuration

13

8

PORTA

Data Bus

Program Counter

RA0

RA1

RA2

RA3

RA4

RA5

Flash

2K x 14

Program

RAM

128

bytes

8-level Stack

(13-bit)

Memory

File

Registers

Program

Bus

14

RAM Addr

9

Addr MUX

Instruction Reg

PORTC

Indirect

Addr

7

Direct Addr

8

RC0

RC1

RC2

RC3

RC4

RC5

FSR Reg

STATUS Reg

8

3

Power-up

Timer

MUX

Oscillator

Instruction

Decode and

Control

Start-up Timer

ALU

Power-on

Reset

8

Watchdog

Timer

OSC1/CLKIN

W Reg

Timing

Generation

Brown-out

Reset

OSC2/CLKOUT

Programmable

Low-Voltage Detect

8 MHz

Internal

Oscillator

31 kHz

Internal

Oscillator

Wake-up

Reset

T1CKI T1G

VDD

VSS

MCLR

Timer0

Timer1

T0CKI

2 Analog Comparators

and Reference

Cryptographic

Module

EEDAT

256 bytes

Data

EEPROM

EEADDR

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

DS41232D-page 10

PIC12F635/PIC16F636/639

FIGURE 1-3:

PIC16F639 BLOCK DIAGRAM

Configuration

PORTA

13

8

Data Bus

Program Counter

RA0

RA1

RA2

RA3

RA4

RA5

Flash

2K x 14

Program

Memory

RAM

128

bytes

8-level Stack

(13-bit)

File

Registers

Program

Bus

14

RAM Addr ⁽¹⁾

9

Addr MUX

Instruction Reg

PORTC

Indirect

Addr

7

Direct Addr

RC0

RC1

RC2

RC3

RC4

RC5

8

FSR Reg

STATUS Reg

8

3

MUX

Power-up

Timer

Oscillator

Instruction

Decode and

Control

Start-up Timer

ALU

Power-on

Reset

8

Watchdog

Timer

OSC1/CLKIN

W Reg

Timing

Generation

VDDT

VSST

Brown-out

Reset

125 kHz

Analog Front-End

(AFE)

OSC2/CLKOUT

Programmable

Low-voltage Detect

LCCOM

8 MHz

Internal

Oscillator

31 kHz

Internal

Oscillator

Wake-up

Reset

T1CKI T1G

LCX

LCY LCZ

VDD VSS

MCLR

Timer0

Timer1

T0CKI

2 Analog

Comparators

EEDAT

KEELOQ Module

and Reference

256 bytes

DATA

EEPROM

EEADDR

C1IN- C1IN+ C1OUT C2IN-

C2IN+ C2OUT

DS41232D-page 11

PIC12F635/PIC16F636/639

TABLE 1-1:

PIC12F635 PINOUT DESCRIPTIONS

Input

Type

Output

Type

Name

Function

Description

GP0/C1IN+/ICSPDAT/ULPWU

GP0

TTL

—

General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

Selectable Ultra Low-Power Wake-up pin.

C1IN+

ICSPDAT

ULPWU

GP1

AN

TTL

AN

—

Comparator 1 input – positive.

CMOS Serial programming data I/O.

Ultra Low-Power Wake-up input.

—

GP1/C1IN-/ICSPCLK

TTL

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

C1IN-

ICSPCLK

GP2

AN

ST

—

Comparator 1 input – negative.

Serial programming clock.

GP2/T0CKI/INT/C1OUT

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

T0CKI

INT

ST

—

External clock for Timer0.

External interrupt.

C1OUT

GP3

CMOS Comparator 1 output.

GP3/MCLR/VPP

TTL

—

General purpose input. Individually controlled

interrupt-on-change.

MCLR

VPP

ST

HV

—

Master Clear Reset. Pull-up enabled when configured as MCLR.

Programming voltage.

GP4/T1G/OSC2/CLKOUT

GP4

TTL

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

T1G

OSC2

CLKOUT

GP5

ST

—

Timer1 gate.

XTAL XTAL connection.

—

CMOS TOSC/4 reference clock.

GP5/T1CKI/OSC1/CLKIN

TTL

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

T1CKI

OSC1

CLKIN

VDD

ST

XTAL

ST

—

Timer1 clock.

XTAL connection.

TOSC reference clock.

VDD

VSS

D

Power supply for microcontroller.

Ground reference for microcontroller.

VSS

D

Legend: AN = Analog input or output

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D = Direct

TTL = TTL compatible input

DS41232D-page 12

PIC12F635/PIC16F636/639

TABLE 1-2:

PIC16F636 PINOUT DESCRIPTIONS

Input

Type

Output

Type

Name

Function

Description

RA0/C1IN+/ICSPDAT/ULPWU

RA0

TTL

—

General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

Selectable Ultra Low-Power Wake-up pin.

C1IN+

ICSPDAT

ULPWU

RA1

AN

TTL

AN

—

Comparator 1 input – positive.

CMOS Serial programming data I/O.

Ultra Low-Power Wake-up input.

—

RA1/C1IN-/VREF/ICSPCLK

RA2/T0CKI/INT/C1OUT

TTL

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

C1IN-

VREF

AN

ST

—

Comparator 1 input – negative.

External voltage reference

Serial programming clock.

ICSPCLK

RA2

CMOS General purpose I/O. Individually controlled

interrupt-on-change. Individually enabled pull-up/pull-down.

T0CKI

INT

ST

—

External clock for Timer0.

External interrupt.

C1OUT

RA3

—

CMOS Comparator 1 output.

RA3/MCLR/VPP

TTL

ST

—

General purpose input. Individually controlled interrupt-on-change.

MCLR

VPP

Master Clear Reset. Pull-up enabled when configured as MCLR.

Programming voltage.

HV

TTL

RA4/T1G/OSC2/CLKOUT

RA4

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

T1G

OSC2

CLKOUT

RA5

ST

—

Timer1 gate.

XTAL XTAL connection.

—

CMOS TOSC/4 reference clock.

RA5/T1CKI/OSC1/CLKIN

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

T1CKI

OSC1

CLKIN

RC0

ST

XTAL

ST

—

Timer1 clock.

XTAL connection.

TOSC reference clock.

RC0/C2IN+

RC1/C2IN-

TTL

AN

CMOS General purpose I/O.

C2IN+

RC1

—

Comparator 1 input – positive.

TTL

AN

CMOS General purpose I/O.

C2IN-

RC2

—

Comparator 1 input – negative.

RC2

TTL

—

CMOS General purpose I/O.

CMOS Comparator 2 output.

CMOS General purpose I/O.

RC3

RC4/C2OUT

RC4

C2OUT

RC5

VDD

VSS

TTL

D

VDD

—

Power supply for microcontroller.

Ground reference for microcontroller.

VSS

D

Legend: AN = Analog input or output

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D = Direct

TTL = TTL compatible input

DS41232D-page 13

PIC12F635/PIC16F636/639

TABLE 1-3:

PIC16F639 PINOUT DESCRIPTIONS

Input

Type

Output

Type

Name

Function

Description

LCCOM

LCX

AN

TTL

—

Common reference for analog inputs.

125 kHz analog X channel input.

125 kHz analog Y channel input.

125 kHz analog Z channel input.

LCX

LCY

LCZ

RA0/C1IN+/ICSPDAT/ULPWU

RA0

General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

Selectable Ultra Low-Power Wake-up pin.

C1IN+

ICSPDAT

ULPWU

RA1

AN

TTL

AN

—

Comparator1 input – positive.

CMOS Serial Programming Data IO.

Ultra Low-Power Wake-up input.

—

RA1/C1IN-/VREF/ICSPCLK

RA2/T0CKI/INT/C1OUT

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

C1IN-

VREF

AN

ST

—

Comparator1 input – negative.

External voltage reference

Serial Programming Clock.

ICSPCLK

RA2

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

T0CKI

INT

ST

—

External clock for Timer0.

External Interrupt.

C1OUT

RA3

CMOS Comparator1 output.

TTL

General purpose input. Individually controlled

interrupt-on-change.

RA3/MCLR/VPP

—

Master Clear Reset. Pull-up enabled when configured as MCLR.

MCLR

VPP

ST

HV

—

Programming voltage.

RA4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

RA4/T1G/OSC2/CLKOUT

ST

—

Timer1 gate.

T1G

OSC2

CLKOUT

RA5

—

XTAL XTAL connection.

CMOS TOSC reference clock.

RA5/T1CKI/OSC1/CLKIN

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up/pull-down.

T1CKI

OSC1

CLKIN

RC0

ST

XTAL

ST

—

Timer1 clock.

XTAL connection.

TOSC/4 reference clock.

RC0/C2IN+

TTL

AN

CMOS General purpose I/O.

C2IN+

RC1

—

Comparator1 input – positive.

TTL

AN

CMOS General purpose I/O.

RC1/C2IN-/CS

C2IN-

—

Comparator1 input – negative.

TTL

Chip select input for SPI communication with internal pull-up

resistor.

CS

RC2

SCLK

ALERT

TTL

—

CMOS General purpose I/O.

RC2/SCLK/ALERT

—

Digital clock input for SPI communication.

Output with internal pull-up resistor for AFE error signal.

= Direct

OD

Legend: AN = Analog input or output

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D

OD = Open Drain

TTL = TTL compatible input

DS41232D-page 14

PIC12F635/PIC16F636/639

TABLE 1-3:

PIC16F639 PINOUT DESCRIPTIONS (CONTINUED)

Input

Type

Output

Type

Name

RC3/LFDATA/RSSI/CCLK/SDO

Function

Description

RC3

LFDATA

RSSI

TTL

—

CMOS General purpose I/O.

CMOS Digital output representation of analog input signal to LC pins.

—

Current Received signal strength indicator. Analog current that is

proportional to input amplitude.

CCLK

SDIO

RC4

—

TTL

—

Carrier clock output.

CMOS Input/Output for SPI communication.

CMOS General purpose I/O.

RC4/C2OUT

C2OUT

RC5

CMOS Comparator2 output.

RC5

TTL

D

CMOS General purpose I/O.

VDDT

—

Power supply for Analog Front-End. In this document, VDDT is

treated the same as VDD, unless otherwise stated.

VSST

D

—

Ground reference for Analog Front-End. In this document, VSST is

treated the same as VSS, unless otherwise stated.

VDD

VSS

VDD

VSS

D

—

Power supply for microcontroller.

Ground reference for microcontroller.

Legend: AN = Analog input or output

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D

= Direct

OD = Open Drain

TTL = TTL compatible input

DS41232D-page 15

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 16

PIC12F635/PIC16F636/639

FIGURE 2-1: PROGRAM MEMORY MAP AND

STACK OF THE PIC12F635

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

PC<12:0>

CALL, RETURN

RETFIE, RETLW

The PIC12F635/PIC16F636/639 devices have a 13-bit

program counter capable of addressing an 8K x 14

program memory space. Only the first 1K x 14

(0000h-03FFh, for the PIC12F635) and 2K x 14

(0000h-07FFh, for the PIC16F636/639) is physically

implemented. Accessing a location above these

boundaries will cause a wraparound within the first

2K x 14 space. The Reset vector is at 0000h and the

interrupt vector is at 0004h (see Figure 2-1).

13

Stack Level 1

Stack Level 8

Reset Vector

0000h

2.2

Data Memory Organization

Interrupt Vector

0004h

0005h

The data memory (see Figure 2-2) is partitioned into

two banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank. Register locations

20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are GPRs,

implemented as static RAM for the PIC16F636/639.

For the PIC12F635, register locations 40h through 7Fh

are GPRs implemented as static RAM. Register

locations F0h-FFh in Bank 1 point to addresses

70h-7Fh in Bank 0. All other RAM is unimplemented

and returns ‘0’ when read. RP0 of the STATUS register

is the bank select bit.

On-chip Program

Memory

03FFh

0400h

Access 0-3FFh

1FFFh

FIGURE 2-2: PROGRAM MEMORY MAP AND

STACK OF THE PIC16F636/639

RP1

0

RP0

0

PC<12:0>

→

Bank 0 is selected

Bank 1 is selected

Bank 2 is selected

Bank 3 is selected

CALL, RETURN

RETFIE, RETLW

13

0

1

0

Stack Level 1

Stack Level 8

1

Reset Vector

0000h

0004h

0005h

Interrupt Vector

On-chip Program

Memory

07FFh

0800h

Access 0-7FFh

1FFFh

DS41232D-page 17

PIC12F635/PIC16F636/639

2.2.1

GENERAL PURPOSE REGISTER

The register file is organized as 64 x 8 for the

PIC12F635 and 128 x 8 for the PIC16F636/639. Each

register is accessed, either directly or indirectly,

through the File Select Register, FSR (see Section 2.4

“Indirect Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers (SFRs) are registers

used by the CPU and peripheral functions for controlling

the desired operation of the device (see Figure 2-1).

These registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

DS41232D-page 18

PIC12F635/PIC16F636/639

FIGURE 2-3:

PIC12F635 SPECIAL FUNCTION REGISTERS

File File

Address Address

Indirect addr.⁽¹⁾00h Indirect addr.⁽¹⁾80h

OPTION_REG 81h

File

Address

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

Address

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

Accesses

00h-0Bh

Accesses

80h-8Bh

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

STATUS

FSR

GPIO

TRISIO

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

TMR1L

TMR1H

T1CON

PCON

OSCCON

OSCTUNE

CRCON

CRDAT0⁽²⁾

CRDAT1⁽²⁾

CRDAT2⁽²⁾

CRDAT3⁽²⁾

LVDCON

WPUDA

IOCA

WDA

WDTCON

CMCON0

CMCON1

VRCON

EEDAT

EEADR

EECON1

EECON2⁽¹⁾

3Fh

40h

General

Purpose

Register

64 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

Accesses

70h-7Fh

Accesses

70h-7Fh

Accesses

Bank 0

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> registers are KEELOQ^®hardware peripheral related registers and require the execution of the

®

“KEELOQ Encoder License Agreement” regarding implementation of the module and access to related

registers. The “KEELOQ^®Encoder License Agreement” may be accessed through the Microchip web site

located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.

DS41232D-page 19

PIC12F635/PIC16F636/639

FIGURE 2-4:

PIC16F636/639 SPECIAL FUNCTION REGISTERS

File

Address

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

Address

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

Indirect addr.⁽¹⁾00h

Indirect addr. ⁽¹⁾80h

Accesses

00h-0Bh

Accesses

80h-8Bh

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

STATUS

FSR

PORTA

TRISA

PORTC

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

TMR1L

TMR1H

T1CON

PCON

OSCCON

OSCTUNE

CRCON

CRDAT0⁽²⁾

CRDAT1⁽²⁾

CRDAT2⁽²⁾

CRDAT3⁽²⁾

LVDCON

WPUDA

IOCA

WDA

WDTCON

CMCON0

CMCON1

VRCON

EEDAT

EEADR

EECON1

EECON2⁽¹⁾

General

Purpose

Register

96 Bytes

General

Purpose

Register

32 Bytes

BFh

C0h

EFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

Accesses

70h-7Fh

F0h

FFh

Accesses

70h-7Fh

Accesses

Bank 0

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: CRDAT<3:0> registers are KEELOQ hardware peripheral related registers and require the execution of the

®

“KEELOQ Encoder License Agreement” regarding implementation of the module and access to related

registers. The “KEELOQ^®Encoder License Agreement” may be accessed through the Microchip web site

located at www.microchip.com/KEELOQ or by contacting your local Microchip Sales Representative.

DS41232D-page 20

PIC12F635/PIC16F636/639

TABLE 2-1:

PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Value on

POR/BOR/

WUR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 0

00h

INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx

32,137

01h

02h

03h

04h

05h

06h

07h

08h

09h

TMR0

PCL

STATUS

FSR

GPIO

—

Timer0 Module Register

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--xx xx00

—

61,137

32,137

26,137

32,137

47,137

—

Program Counter’s (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

—

GP5

GP4

GP3

GP2

GP1

GP0

Unimplemented

—

0Ah PCLATH

0Bh INTCON

0Ch PIR1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

0000 000x

000- 00-0

—

32,137

28,137

30,137

—

GIE

PEIE

T0IE

CRIF

INTE

—

RAIE

C1IF

T0IF

INTF

—

RAIF⁽²⁾

EEIF

LVDIF

OSFIF

TMR1IF

0Dh

—

Unimplemented

0Eh TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1

Holding Register for the Most Significant Byte of the 16-bit TMR1

xxxx xxxx

64,137

0Fh

TMR1H

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

T1CON

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

0000 0000

68,137

—

Unimplemented

—

WDTCON

CMCON0

—

COUT

—

WDTPS3

CINV

—

WDTPS2

CIS

WDTPS1 WDTPS0

SWDTEN

CM0

---0 1000

144,137

79,137

82,137

—

CM2

—

CM1

-0-0 0000

1Ah CMCON1

—

T1GSS

CMSYNC

---- --10

1Bh

—

Unimplemented

—

1Ch

—

1Dh

—

1Eh

—

1Fh

—

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1:

2:

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set again if the mis-

match exists.

DS41232D-page 21

PIC12F635/PIC16F636/639

TABLE 2-2:

PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

POR/BOR/

WUR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 1

32,137

80h INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx

63,137

32,137

26,137

32,137

81h OPTION_REG RAPU INTEDG

T0CS

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO PD

Indirect Data Memory Address Pointer

T0SE

PSA

PS2

PS1

PS0

C

1111 1111

0000 0000

0001 1xxx

xxxx xxxx

82h PCL

83h STATUS

84h FSR

Z

DC

85h TRISIO

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

86h

87h

88h

89h

—

Unimplemented

—

32,137

8Ah PCLATH

8Bh INTCON

8Ch PIE1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

0000 000x

(3)

GIE

EEIE

PEIE

LVDIE

T0IE

CRIE

INTE

—

RAIE

C1IE

T0IF

INTF

—

RAIF

28,137

29,137

—

OSFIE

TMR1IE 000- 00-0

8Dh

—

Unimplemented

—

8Eh PCON

—

IRCF2

—

ULPWUE SBOREN WUR

—

POR

LTS

BOR

SCS

--01 q-qq

-110 q000

31,137

36,137

40,137

—

8Fh OSCCON

90h OSCTUNE

IRCF1

—

IRCF0

TUN4

OSTS

TUN3

HTS

TUN2

TUN1

TUN0 ---0 0000

91h

92h

93h

—

Unimplemented

—

94h LVDCON

—

IRVST

LVDEN

—

LVDL2

LVDL1

LVDL0 --00 -000 --00 -000

(2)

95h WPUDA

96h IOCA

WPUDA5 WPUDA4

WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111

IOCA5

WDA5

IOCA4

WDA4

IOCA3

—

IOCA2

WDA2

IOCA1

WDA1

IOCA0 --00 0000 --00 0000

WDA0 --11 -111 --11 -111

(2)

97h WDA

9Bh

—

Unimplemented

VREN

—

99h VRCON

9Ah EEDAT

9Bh EEADR

9Ch EECON1

9Dh EECON2

—

VRR

—

VR3

VR2

VR1

VR0

0-0- 0000 0-0- 0000

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

—

WRERR WREN

WR

RD

---- x000 ---- q000

---- ---- ---- ----

EEPROM Control Register 2 (not a physical register)

Unimplemented

9Eh

—

9Fh

Unimplemented

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.

3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set

again if the mismatch exists.

DS41232D-page 22

PIC12F635/PIC16F636/639

TABLE 2-3:

PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Value on

POR/BOR/

WUR

Addr Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 0

32,137

00h INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx

61,137

32,137

01h TMR0

02h PCL

Timer0 Module Register

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--xx xx00

—

Program Counter’s (PC) Least Significant Byte

26,137

32,137

03h STATUS

04h FSR

IRP

RP1

RP0

TO

PD

Z

DC

RA1

RC1

C

Indirect Data Memory Address Pointer

05h PORTA

—

RA5

RC5

RA4

RC4

RA3

RC3

RA2

RC2

RA0

RC0

48,137

—

06h

—

Unimplemented

07h PORTC

—

--xx xx00

—

57,137

—

08h

09h

—

Unimplemented

—

32,137

0Ah PCLATH

0Bh INTCON

0Ch PIR1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

0000 000x

(2)

GIE

EEIF

PEIE

LVDIF

T0IE

CRIF

INTE

C2IF

RAIE

C1IF

T0IF

INTF

—

RAIF

28,137

30,137

—

OSFIF

TMR1IF 0000 00-0

—

0Dh

0Eh TMR1L

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1

10h T1CON

—

Unimplemented

64,137

Holding Register for the Least Significant Byte of the 16-bit TMR1

xxxx xxxx

68,137

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000

11h

12h

13h

14h

15h

16h

17h

—

Unimplemented

—

144,137

79,137

82,137

18h WDTCON

19h CMCON0 C2OUT C1OUT

1Ah CMCON1

—

C2INV

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000

C1INV

—

CIS

—

CM2

—

CM1

CM0

0000 0000

—

T1GSS C2SYNC ---- --10

1Bh

—

Unimplemented

—

1Ch

1Dh

1Eh

1Fh

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

DS41232D-page 23

PIC12F635/PIC16F636/639

TABLE 2-4:

PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

POR/BOR/

WUR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 1

32,137

80h INDF

Addressing this location uses contents of FSR to address data memory

(not a physical register)

xxxx xxxx

63,137

32,137

26,137

32,137

81h OPTION_REG RAPU INTEDG

T0CS

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO PD

Indirect Data Memory Address Pointer

T0SE

PSA

PS2

PS1

PS0

C

1111 1111

0000 0000

0001 1xxx

xxxx xxxx

82h PCL

83h STATUS

84h FSR

Z

DC

85h TRISA

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

86h

—

Unimplemented

—

87h TRISC

—

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 --11 1111 --11 1111

88h

89h

—

Unimplemented

—

32,137

8Ah PCLATH

8Bh INTCON

8Ch PIE1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000

0000 000x

(3)

GIE

EEIE

PEIE

LVDIE

T0IE

CRIE

INTE

C2IE

RAIE

C1IE

T0IF

INTF

—

RAIF

28,137

29,137

—

OSFIE

TMR1IE 0000 00-0

8Dh

—

Unimplemented

—

8Eh PCON

—

IRCF2

—

ULPWUE SBOREN WUR

—

POR

LTS

BOR

SCS

--01 q-qq --0u u-uu

-110 q000 -110 x000

8Fh OSCCON

90h OSCTUNE

IRCF1

—

IRCF0

TUN4

OSTS

TUN3

HTS

TUN2

TUN1

TUN0 ---0 0000 ---u uuuu

91h

92h

93h

—

Unimplemented

—

94h LVDCON

—

IRVST

LVDEN

—

LVDL2

LVDL1

LVDL0 --00 -000 --00 -000

(2)

95h WPUDA

96h IOCA

WPUDA5 WPUDA4

WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111

IOCA5

WDA5

IOCA4

WDA4

IOCA3

—

IOCA2

WDA2

IOCA1

WDA1

IOCA0 --00 0000 --00 0000

WDA0 --11 -111 --11 -111

(2)

97h WDA

9Bh

—

Unimplemented

VREN

—

99h VRCON

9Ah EEDAT

9Bh EEADR

9Ch EECON1

9Dh EECON2

—

VRR

—

VR3

VR2

VR1

VR0

0-0- 0000 0-0- 0000

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

—

WRERR WREN

WR

RD

---- x000 ---- q000

---- ---- ---- ----

EEPROM Control Register 2 (not a physical register)

Unimplemented

9Eh

—

9Fh

Unimplemented

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: RA3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.

3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set

again if the mismatch exists.

DS41232D-page 24

PIC12F635/PIC16F636/639

TABLE 2-5:

PIC12F635/PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Value on

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR/BOR/

WUR

Page

Bank 2

10Ch

10Dh

10Eh

10Fh

—

Unimplemented

GO/DONE ENC/DEC

—

110h CRCON

111h CRDAT0

112h CRDAT1

113h CRDAT2

114h CRDAT3

—

CRREG1 CRREG0 00-- --00 00-- --00

0000 0000 0000 0000

(2)

Cryptographic Data Register 0

Cryptographic Data Register 1

Cryptographic Data Register 2

Cryptographic Data Register 3

Unimplemented

0000 0000 0000 0000

115h

—

116h

Unimplemented

Legend:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

®

2: CRDAT<3:0> registers are KEELOQ hardware peripheral related registers and require the execution of the “KEELOQ

Encoder License Agreement” regarding implementation of the module and access to related registers. The “KEELOQ

Encoder License Agreement” may be accessed through the Microchip web site located at www.microchip.com/KEELOQ

or by contacting your local Microchip Sales Representative.

DS41232D-page 25

PIC12F635/PIC16F636/639

For example, CLRF STATUS,will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’(where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see Section 13.0 “Instruction Set

Summary”

• the bank select bits for data memory (GPR and

SFR)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction.

REGISTER 2-1:

STATUS: STATUS REGISTER

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2, 3 (100h-1FFh)

0= Bank 0, 1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

00= Bank 0 (00h-7Fh)

01= Bank 1 (80h-FFh)

10= Bank 2 (100h-17Fh)

11= Bank 3 (180h-1FFh)

bit 4

bit 3

bit 2

bit 1

bit 0

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

DS41232D-page 26

PIC12F635/PIC16F636/639

2.2.2.2

OPTION Register

Note:

To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT by

setting the PSA bit of the OPTION register

to ‘1’. See Section 5.1.3 “Software

Programmable Prescaler”.

The OPTION register is a readable and writable

register which contains various control bits to

configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

• TMR0

• Weak pull-up/pull-downs on PORTA

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

RAPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RAPU: PORTA Pull-up Enable bit

1= PORTA pull-ups are disabled

0= PORTA pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RA2/INT pin

0= Interrupt on falling edge of RA2/INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on RA2/T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on RA2/T0CKI pin

0= Increment on low-to-high transition on RA2/T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

DS41232D-page 27

PIC12F635/PIC16F636/639

2.2.2.3

INTCON Register

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

The INTCON register is a readable and writable

register which contains the various enable and flag bits

for TMR0 register overflow, PORTA change and

external RA2/INT pin interrupts.

REGISTER 2-3:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RAIE^(1,3)

R/W-0

T0IF⁽²⁾

R/W-0

INTF

R/W-x

RAIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: RA2/INT External Interrupt Enable bit

1= Enables the RA2/INT external interrupt

0= Disables the RA2/INT external interrupt

RAIE: PORTA Change Interrupt Enable bit^(1,3)

1= Enables the PORTA change interrupt

0= Disables the PORTA change interrupt

T0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RA2/INT External Interrupt Flag bit

1= The RA2/INT external interrupt occurred (must be cleared in software)

0= The RA2/INT external interrupt did not occur

RAIF: PORTA Change Interrupt Flag bit

1 = When at least one of the PORTA general purpose I/O pins changed state (must be cleared in

software)

0= None of the PORTA general purpose I/O pins have changed state

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

3: Includes ULPWU interrupt.

DS41232D-page 28

PIC12F635/PIC16F636/639

2.2.2.4

PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-4:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

EEIE

R/W-0

LVDIE

R/W-0

CRIE

R/W-0

C2IE⁽¹⁾

R/W-0

C1IE

R/W-0

OSFIE

U-0

—

R/W-0

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EEIE: EE Write Complete Interrupt Enable bit

1= Enables the EE write complete interrupt

0= Disables the EE write complete interrupt

LVDIE: Low-Voltage Detect Interrupt Enable bit

1= Enables the LVD interrupt

0= Disables the LVD interrupt

CRIE: Cryptographic Interrupt Enable bit

1= Enables the cryptographic interrupt

0= Disables the cryptographic interrupt

C2IE: Comparator 2 Interrupt Enable bit⁽¹⁾

1= Enables the Comparator 2 interrupt

0= Disables the Comparator 2 interrupt

C1IE: Comparator 1 Interrupt Enable bit

1= Enables the Comparator 1 interrupt

0= Disables the Comparator 1 interrupt

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the oscillator fail interrupt

0= Disables the oscillator fail interrupt

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

Note 1: PIC16F636/639 only.

DS41232D-page 29

PIC12F635/PIC16F636/639

2.2.2.5

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Interrupt Enable bit, GIE of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

REGISTER 2-5:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0

EEIF

R/W-0

LVDIF

R/W-0

CRIF

R/W-0

C2IF⁽¹⁾

R/W-0

C1IF

R/W-0

OSFIF

U-0

—

R/W-0

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EEIF: EE Write Complete Interrupt Flag bit

1= The write operation completed (must be cleared in software)

0= The write operation has not completed or has not been started

LVDIF: Low-Voltage Detect Interrupt Flag bit

1= The supply voltage has crossed selected LVD voltage (must be cleared in software)

0= The supply voltage has not crossed selected LVD voltage

CRIF: Cryptographic Interrupt Flag bit

1= The Cryptographic module has completed an operation (must be cleared in software)

0= The Cryptographic module has not completed an operation or is Idle

C2IF: Comparator 2 Interrupt Flag bit⁽¹⁾

1= Comparator output (C2OUT bit) has changed (must be cleared in software)

0= Comparator output (C2OUT bit) has not changed

C1IF: Comparator 1 Interrupt Flag bit

1= Comparator output (C1OUT bit) has changed (must be cleared in software)

0= Comparator output (C1OUT bit) has not changed

OSFIF: Oscillator Fail Interrupt Flag bit

1= System oscillator failed, clock input has changed INTOSC (must be cleared in software)

0= System clock operating

bit 1

bit 0

Unimplemented: Read as ‘0’

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Timer1 rolled over (must be cleared in software)

0= Timer1 has not rolled over

Note 1: PIC16F636/639 only.

DS41232D-page 30

PIC12F635/PIC16F636/639

2.2.2.6

PCON Register

The Power Control (PCON) register (see Table 12-3)

contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Wake-up Reset (WUR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR.

The PCON register bits are shown in Register 2-6.

REGISTER 2-6:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

R/W-0

R/W-1

SBOREN⁽¹⁾

R/W-x

WUR

U-0

—

R/W-0

POR

R/W-x

BOR

ULPWUE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ULPWUE: Ultra Low-Power Wake-up Enable bit

1= Ultra low-power wake-up enabled

0= Ultra low-power wake-up disabled

bit 4

bit 3

SBOREN: Software BOR Enable bit⁽¹⁾

1= BOR enabled

0= BOR disabled

WUR: Wake-up Reset Status bit

1= No Wake-up Reset occurred

0= A Wake-up Reset occurred (must be set in software after a Power-on Reset occurs)

bit 2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01in the Configuration Word register for this bit to control the BOR.

DS41232D-page 31

PIC12F635/PIC16F636/639

2.3.2

STACK

2.3

PCL and PCLATH

The PIC12F635/PIC16F636/639 family has an

8-level x 13-bit wide hardware stack (see Figure 2-1).

The stack space is not part of either program or data

space and the Stack Pointer is not readable or writable.

The PC is PUSHed onto the stack when a CALL

instruction is executed or an interrupt causes a branch.

The stack is POPed in the event of a RETURN, RETLW

or a RETFIE instruction execution. PCLATH is not

affected by a PUSH or POP operation.

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 2-5 shows the

two situations for the loading of the PC. The upper

example in Figure 2-5 shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower

example in Figure 2-5 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3> →

PCH).

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

FIGURE 2-5:

LOADING OF PC IN

DIFFERENT SITUATIONS

Note 1: There are no Status bits to indicate stack

PCH

PCL

overflow or stack underflow conditions.

Instruction with

12

8

7

0

PCL as

Destination

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLWand RETFIEinstructions

or the vectoring to an interrupt address.

PC

8

PCLATH<4:0>

PCLATH

5

ALU Result

2.4

Indirect Addressing, INDF and

FSR Registers

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

PCLATH<4:3>

PCLATH

11

2

Opcode<10:0>

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit of the

STATUS register, as shown in Figure 2-6.

2.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

EXAMPLE 2-1:

INDIRECT ADDRESSING

MOVLW 0x20

MOVWF FSR

CLRF INDF

INCF FSR

;initialize pointer

;to RAM

;clear INDF register

;INC POINTER

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

BTFSS FSR,4 ;all done?

GOTO

;yes continue

CONTINUE

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

DS41232D-page 32

PIC12F635/PIC16F636/639

FIGURE 2-6:

DIRECT/INDIRECT ADDRESSING PIC12F635/PIC16F636/639

Direct Addressing

From Opcode

Indirect Addressing

7

6

0

IRP

File Select Register

RP1 RP0

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

Note: For memory map detail, see Figure 2-2.

DS41232D-page 33

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 34

PIC12F635/PIC16F636/639

The Oscillator module can be configured in one of eight

clock modes.

3.0

3.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. EC – External clock with I/O on OSC2/CLKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

Overview

3. XT

– Medium Gain Crystal or Ceramic

The Oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 3-1

illustrates a block diagram of the Oscillator module.

Resonator Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

Clock sources can be configured from external

oscillators, quartz crystal resonators, ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock source can be configured from one of two

internal oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

• Selectable system clock source between external

or internal via software.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word register (CONFIG). The

internal clock can be generated from two internal

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

oscillators. The HFINTOSC is

a

calibrated

high-frequency oscillator. The LFINTOSC is an

uncalibrated low-frequency oscillator.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

FIGURE 3-1:

PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word Register)

External Oscillator

SCS<0>

(OSCCON Register)

OSC2

OSC1

Sleep

LP, XT, HS, RC, RCIO, EC

IRCF<2:0>

(OSCCON Register)

System Clock

(CPU and Peripherals)

8 MHz

111

110

101

INTOSC

Internal Oscillator

4 MHz

2 MHz

1 MHz

HFINTOSC

8 MHz

100

011

010

001

000

500 kHz

250 kHz

125 kHz

31 kHz

LFINTOSC

31 kHz

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

DS41232D-page 35

PIC12F635/PIC16F636/639

3.2

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 3-1)

controls the system clock and frequency selection

options. The OSCCON register contains the following

bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

REGISTER 3-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R/W-1

IRCF2

R/W-1

IRCF1

R/W-0

IRCF0

R-1

OSTS⁽¹⁾

R-0

LTS

R/W-0

SCS

HTS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

111= 8 MHz

110= 4 MHz (default)

101= 2 MHz

100= 1 MHz

011= 500 kHz

010= 250 kHz

001= 125 kHz

000= 31 kHz (LFINTOSC)

bit 3

bit 2

bit 1

bit 0

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Device is running from the external clock defined by FOSC<2:0> of the Configuration Word

0= Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)

1= HFINTOSC is stable

0= HFINTOSC is not stable

LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1= LFINTOSC is stable

0= LFINTOSC is not stable

SCS: System Clock Select bit

1= Internal oscillator is used for system clock

0= Clock source defined by FOSC<2:0> of the Configuration Word

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

DS41232D-page 36

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3.3

Clock Source Modes

3.4

External Clock Modes

Clock Source modes can be classified as external or

internal.

3.4.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the Oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 3-1.

• External Clock modes rely on external circuitry for

the clock source. Examples are: Oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally

within the Oscillator module. The Oscillator

module has two internal oscillators: the 8 MHz

High-Frequency Internal Oscillator (HFINTOSC)

and the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for additional information.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 3.7

“Two-Speed Clock Start-up Mode”).

TABLE 3-1:

OSCILLATOR DELAY EXAMPLES

Switch From

Switch To

Frequency

Oscillator Delay

LFINTOSC

HFINTOSC

31 kHz

125 kHz to 8 MHz

Sleep/POR

Oscillator Warm-Up Delay (TWARM)

Sleep/POR

LFINTOSC (31 kHz)

Sleep/POR

EC, RC

DC – 20 MHz

2 instruction cycles

1 cycle of each

LP, XT, HS

HFINTOSC

32 kHz to 20 MHz

125 kHz to 8 MHz

1024 Clock Cycles (OST)

1 μs (approx.)

LFINTOSC (31 kHz)

3.4.2

EC MODE

FIGURE 3-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 3-2 shows the pin

connections for EC mode.

OSC1/CLKIN

Clock from

Ext. System

PIC^®MCU

(1)

I/O

OSC2/CLKOUT

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

DS41232D-page 37

PIC12F635/PIC16F636/639

3.4.3

LP, XT, HS MODES

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 3-3). The mode selects a low,

medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

LP Oscillator mode selects the lowest gain setting of

the internal inverter-amplifier. LP mode current con-

sumption is the least of the three modes. This mode is

designed to drive only 32.768 kHz tuning-fork type

crystals (watch crystals).

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

Analysis and Design” (DS00943)

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

• AN949, “Making Your Oscillator Work”

(DS00949)

FIGURE 3-4:

CERAMIC RESONATOR

OPERATION

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

(XT OR HS MODE)

FIGURE 3-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

PIC^®MCU

OSC1/CLKIN

C1

PIC^®MCU

To Internal

Logic

OSC1/CLKIN

(3)

(2)

RP

RF

Sleep

C1

To Internal

Logic

Quartz

Crystal

(2)

OSC2/CLKOUT

(1)

C2

RF

Sleep

RS

Ceramic

Resonator

Note 1: A series resistor (RS) may be required for

OSC2/CLKOUT

(1)

C2

RS

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

DS41232D-page 38

PIC12F635/PIC16F636/639

3.4.4

EXTERNAL RC MODES

3.5

Internal Clock Modes

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

The Oscillator module has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

register (Register 3-2).

In RC mode, the RC circuit connects to OSC1.

OSC2/CLKOUT outputs the RC oscillator frequency

divided by 4. This signal may be used to provide a clock

for external circuitry, synchronization, calibration, test

or other application requirements. Figure 3-5 shows

the external RC mode connections.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<2:0> of the OSCCON register.

FIGURE 3-5:

EXTERNAL RC MODES

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for more information.

VDD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

Clock

3.5.1 INTOSC AND INTOSCIO MODES

CEXT

VSS

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the device is programmed using the oscillator selection

or the FOSC<2:0> bits in the Configuration Word

register (CONFIG). See Section 12.0 “Special

Features of the CPU” for more information.

(1)

FOSC/4 or

OSC2/CLKOUT

(2)

I/O

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator frequency divided by 4. The CLKOUT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in the

Section 1.0 “Device Overview”.

2: Output depends upon RC or RCIO clock mode.

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT

are available for general purpose I/O.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

3.5.2

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 3-2).

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). One of seven

frequencies can be selected via software using the

IRCF<2:0> bits of the OSCCON register. See

Section 3.5.4 “Frequency Select Bits (IRCF)” for

more information.

The user also needs to take into account variation due

to tolerance of external RC components used.

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz by setting the IRCF<2:0>

bits of the OSCCON register ≠ 000. Then, set the

System Clock Source (SCS) bit of the OSCCON

register to ‘1’ or enable Two-Speed Start-up by setting

the IESO bit in the Configuration Word register

(CONFIG) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON

register indicates whether the HFINTOSC is stable or not.

DS41232D-page 39

PIC12F635/PIC16F636/639

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift.

There is no indication that the shift has occurred.

3.5.2.1

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

register (Register 3-2).

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number.

REGISTER 3-2:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Oscillator module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

DS41232D-page 40

PIC12F635/PIC16F636/639

3.5.3

LFINTOSC

3.5.5

HF AND LF INTOSC CLOCK

SWITCH TIMING

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power (see Figure 3-6). If this is the case,

there is a delay after the IRCF<2:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The LTS and HTS bits of the

OSCCON register will reflect the current active status

of the LFINTOSC and HFINTOSC oscillators. The

timing of a frequency selection is as follows:

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). Select 31 kHz, via

software, using the IRCF<2:0> bits of the OSCCON

register. See Section 3.5.4 “Frequency Select Bits

(IRCF)” for more information. The LFINTOSC is also the

frequency for the Power-up Timer (PWRT), Watchdog

Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<2:0> bits of the OSCCON register = 000)as the

system clock source (SCS bit of the OSCCON

register = 1), or when any of the following are enabled:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

• Two-Speed Start-up IESO bit of the Configuration

Word register = 1and IRCF<2:0> bits of the

OSCCON register = 000

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits for a rising edge in the new clock.

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

5. CLKOUT is now connected with the new clock.

LTS and HTS bits of the OSCCON register are

updated as required.

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON

register indicates whether the LFINTOSC is stable or

not.

6. Clock switch is complete.

See Figure 3-1 for more details.

3.5.4

FREQUENCY SELECT BITS (IRCF)

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and new frequencies are derived from the HFINTOSC

via the postscaler and multiplexer.

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 3-1). The Internal Oscillator Frequency

Select bits IRCF<2:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

eight frequencies can be selected via software:

Start-up delay specifications are located in the A/C

Specifications (Oscillator Module) in Section 15.0

“Electrical Specifications”.

• 8 MHz

• 4 MHz (Default after Reset)

• 2 MHz

• 1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC)

Note:

Following any Reset, the IRCF<2:0> bits of

the OSCCON register are set to ‘110’ and

the frequency selection is set to 4 MHz.

The user can modify the IRCF bits to

select a different frequency.

DS41232D-page 41

PIC12F635/PIC16F636/639

FIGURE 3-6:

INTERNAL OSCILLATOR SWITCH TIMING

HF

LF⁽¹⁾

HFINTOSC

LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

2-cycle Sync

Running

LFINTOSC

≠ 0

= 0

IRCF <2:0>

System Clock

Note 1: When going from LF to HF.

HFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

2-cycle Sync

Running

LFINTOSC

≠ 0

= 0

IRCF <2:0>

System Clock

LFINTOSC

HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC

= 0

≠ 0

IRCF <2:0>

System Clock

DS41232D-page 42

PIC12F635/PIC16F636/639

When the Oscillator module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

3.6

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit of the OSCCON

register.

enabled (see Section 3.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

execution switches to the external oscillator.

3.6.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

3.7.1

TWO-SPEED START-UP MODE

CONFIGURATION

• When the SCS bit of the OSCCON register = 0,

the system clock source is determined by

configuration of the FOSC<2:0> bits in the

Configuration Word register (CONFIG).

Two-Speed Start-up mode is configured by the

following settings:

• When the SCS bit of the OSCCON register = 1,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<2:0>

bits of the OSCCON register. After a Reset, the

SCS bit of the OSCCON register is always

cleared.

• IESO (of the Configuration Word register) = 1;

Internal/External Switchover bit (Two-Speed

Start-up mode enabled).

• SCS (of the OSCCON register) = 0.

• FOSC<2:0> bits in the Configuration Word

register (CONFIG) configured for LP, XT or HS

mode.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe

Clock Monitor, does not update the SCS bit

of the OSCCON register. The user can

monitor the OSTS bit of the OSCCON

register to determine the current system

clock source.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then

Two-Speed Start-up is disabled. This is because the

external clock oscillator does not require any

stabilization time after POR or an exit from Sleep.

3.6.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word register (CONFIG), or from the internal clock

source. In particular, OSTS indicates that the Oscillator

Start-up Timer (OST) has timed out for LP, XT or HS

modes.

3.7.2

TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<2:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

3.7

Two-Speed Clock Start-up Mode

4. OST timed out, wait for falling edge of the

internal oscillator.

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

DS41232D-page 43

PIC12F635/PIC16F636/639

3.7.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

register will confirm if the microcontroller is running

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word register

(CONFIG), or the internal oscillator.

FIGURE 3-7:

TWO-SPEED START-UP

HFINTOSC

TOST

OSC1

0

1

1022 1023

OSC2

PC - N

PC + 1

Program Counter

PC

System Clock

DS41232D-page 44

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3.8.3

FAIL-SAFE CONDITION CLEARING

3.8

Fail-Safe Clock Monitor

The Fail-Safe condition is cleared after a Reset,

executing a SLEEPinstruction or toggling the SCS bit

of the OSCCON register. When the SCS bit is toggled,

the OST is restarted. While the OST is running, the

device continues to operate from the INTOSC selected

in OSCCON. When the OST times out, the Fail-Safe

condition is cleared and the device will be operating

from the external clock source. The Fail-Safe condition

must be cleared before the OSFIF flag can be cleared.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word register (CONFIG). The FSCM is

applicable to all external oscillator modes (LP, XT, HS,

EC, RC and RCIO).

FIGURE 3-8:

FSCM BLOCK DIAGRAM

3.8.4

RESET OR WAKE-UP FROM SLEEP

Clock Monitor

Latch

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

Clock

S

Q

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 μs)

488 Hz

(~2 ms)

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

Sample Clock

Clock

Failure

Detected

3.8.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 3-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

primary clock goes low.

clock

completed.

switchover

has

successfully

3.8.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR1 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE1

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

DS41232D-page 45

PIC12F635/PIC16F636/639

FIGURE 3-9:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

(1)

Resets

(2)

CONFIG

CPD

GIE

—

CP

PEIE

IRCF2

—

MCLRE PWRTE

WDTE

RAIE

OSTS

TUN3

C1IE

FOSC2

T0IF

FOSC1

INTF

LTS

FOSC0

RAIF

—

INTCON

OSCCON

OSCTUNE

PIE1

T0IE

IRCF1

—

INTE

IRCF0

TUN4

C2IE⁽³⁾

C2IF⁽³⁾

0000 000x 0000 000x

-110 x000 -110 x000

---0 0000 ---u uuuu

HTS

SCS

—

TUN2

OSFIE

OSFIF

TUN1

—

TUN0

EEIE

EEIF

LVDIE

LVDIF

CRIE

CRIF

TMR1IE 000- 00-0 000- 00-0

TMR1IF 000- 00-0 000- 00-0

PIR1

C1IF

—

Legend:

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (CONFIG) for operation of all register bits.

3:

PIC16F636/639 only.

DS41232D-page 46

PIC12F635/PIC16F636/639

4.2

Additional Pin Functions

4.0

I/O PORTS

Every PORTA pin on the PIC12F635/PIC16F636/639

has an interrupt-on-change option and weak

pull-up/pull-down option. RA0 has an Ultra Low-Power

Wake-up option. The next three sections describe

these functions.

There are as many as twelve general purpose I/O pins

available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

a

4.2.1

WEAK PULL-UP/PULL-DOWN

Each of the PORTA pins, except RA3, has an internal

weak pull-up and pull-down. The WDA bits select either

a pull-up or pull-down for an individual port bit.

Individual control bits can turn on the pull-up or

pull-down. These pull-ups/pull-downs are automatically

turned off when the port pin is configured as an output,

as an alternate function or on a Power-on Reset,

setting the RAPU bit of the OPTION register. A weak

pull-up on RA3 is enabled when configured as MCLR

in the Configuration Word register and disabled when

high voltage is detected, to reduce current

consumption through RA3, while in Programming

mode.

4.1

PORTA and the TRISA Registers

PORTA is

a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 4-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., put the

corresponding output driver in a High-Impedance

mode). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., put the

contents of the output latch on the selected pin). The

exception is RA3, which is input only and its TRIS bit will

always read as ‘1’. Example 4-1 shows how to initialize

PORTA.

Note:

PORTA = GPIO

TRISA = TRISIO

Note:

PORTA = GPIO

TRISA = TRISIO

Reading the PORTA register (Register 4-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch. RA3 reads ‘0’ when MCLRE = 1.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

register are maintained set when using them as analog

inputs. I/O pins configured as analog inputs always

read ‘0’.

Note:

The CMCON0 register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

EXAMPLE 4-1:

INITIALIZING PORTA

BANKSELPORTA

;

CLRF

MOVLW 07h

MOVWF CMCON0

BSF

BCF

PORTA

;Init PORTA

;Set RA<2:0> to

;digital I/O

;Bank 1

STATUS,RP0

STATUS,RP1

;

MOVLW 0Ch

MOVWF TRISA

;Set RA<3:2> as inputs

;and set RA<5:4,1:0>

;as outputs

DS41232D-page 47

PIC12F635/PIC16F636/639

REGISTER 4-1:

PORTA: PORTA REGISTER

U-0

—

U-0

—

R/W-x

RA5

R/W-x

RA4

R-x

R/W-x

RA2

R/W-x

RA1

R/W-x

RA0

RA3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 4-2:

TRISA: PORTA TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

R-1

R/W-1

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TRISA<5:0>: PORTA Tri-State Control bits

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.

DS41232D-page 48

PIC12F635/PIC16F636/639

REGISTER 4-3:

WDA: WEAK PULL-UP/PULL-DOWN DIRECTION REGISTER

U-0

—

U-0

—

R/W-1

WDA5

R/W-1

WDA4

U-0

—

R/W-1

WDA2

R/W-1

WDA1

R/W-1

WDA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

WDA<5:4>: Pull-up/Pull-down Selection bits

1= Pull-up selected

0= Pull-down selected

bit 3

Unimplemented: Read as ‘0’

bit 2-0

WDA<2:0>: Pull-up/Pull-down Selection bits

1= Pull-up selected

0= Pull-down selected

Note 1: The weak pull-up/pull-down device is enabled only when the global RAPU bit is enabled, the pin is in Input mode (TRIS

= 1), the individual WDA bit is enabled (WDA = 1) and the pin is not configured as an analog input or clock function.

2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in

Programming mode.

REGISTER 4-4:

WPUDA: WEAK PULL-UP/PULL-DOWN ENABLE REGISTER

U-0

—

U-0

—

R/W-1

U-0

—

R/W-1

(3)

WPUDA5

WPUDA4

WPUDA2

WPUDA1

WPUDA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

(3)

WPUDA<5:4>: Pull-up/Pull-down Direction Selection bits

1= Pull-up/pull-down enabled

0= Pull-up/pull-down disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

WPUDA<2:0>: Pull-up/Pull-down Direction Selection bits

1= Pull-up/pull-down enabled

0= Pull-up/pull-down disabled

Note 1: The weak pull-up/pull-down direction device is enabled only when the global RAPU bit is enabled, the pin is in Input mode

(TRIS = 1), the individual WPUDA bit is enabled (WPUDA = 1) and the pin is not configured as an analog input or clock

function.

2: RA3 pull-up is enabled when the pin is configured as MCLR in the Configuration Word register and the device is not in

Programming mode.

3: WPUDA5 bit can be written if INTOSC is enabled and T1OSC is disabled; otherwise, the bit can not be written and reads

as ‘1’. WPUDA4 bit can be written if not configured as OSC2; otherwise, the bit can not be written and reads as ‘1’

DS41232D-page 49

PIC12F635/PIC16F636/639

A mismatch condition will continue to set flag bit RAIF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOR

Reset. After these Resets, the RAIF flag will continue

to be set if a mismatch is present.

4.2.2

INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as

an interrupt-on-change pin. Control bits, IOCAx, enable

or disable the interrupt function for each pin. Refer to

Register 4-5. The interrupt-on-change is disabled on a

Power-on Reset.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTA Change Interrupt Flag

bit (RAIF) in the INTCON register.

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

a) Any read or write of PORTA. This will end the

mismatch condition, then

b) Clear the flag bit RAIF.

REGISTER 4-5:

IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER

U-0

—

U-0

—

R/W-0

IOCA5⁽²⁾

R/W-0

IOCA4⁽²⁾

R/W-0

IOCA3⁽³⁾

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCA<5:0>: Interrupt-on-Change PORTA Control bits^(2,3)

1= Interrupt-on-change enabled⁽¹⁾

0= Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes.

3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.

DS41232D-page 50

PIC12F635/PIC16F636/639

4.2.3

ULTRA LOW-POWER WAKE-UP

EXAMPLE 4-2:

ULTRA LOW-POWER

WAKE-UP INITIALIZATION

The Ultra Low-Power Wake-up (ULPWU) on RA0 allows

a slow falling voltage to generate an interrupt-on-change

on RA0 without excess current consumption. The mode

is selected by setting the ULPWUE bit of the PCON

register. This enables a small current sink which can be

used to discharge a capacitor on RA0.

BANKSELPORTA

;

BSF

MOVLW

MOVWF

PORTA,0

H’7’

CMCON0

;Set RA0 data latch

;Turn off

; comparators

;

;Output high to

; charge capacitor

BANKSELTRISA

BCF

CALL

BSF

TRISA,0

CapDelay

To use this feature, the RA0 pin is configured to output

‘1’ to charge the capacitor, interrupt-on-change for RA0

is enabled and RA0 is configured as an input. The

ULPWUE bit is set to begin the discharge and a SLEEP

instruction is performed. When the voltage on RA0 drops

below VIL, an interrupt will be generated which will cause

the device to wake-up. Depending on the state of the

GIE bit of the INTCON register, the device will either

jump to the interrupt vector (0004h) or execute the next

instruction when the interrupt event occurs. See

PCON,ULPWUE ;Enable ULP Wake-up

BSF

IOCA,0

;Select RA0 IOC

;RA0 to input

B’10001000’ ;Enable interrupt

BSF

TRISA,0

MOVLW

MOVWF

SLEEP

NOP

INTCON

; and clear flag

;Wait for IOC

;

Section 4.2.2

“Interrupt-on-Change”

and

Section 12.9.3 “PORTA Interrupt” for more

information.

This feature provides a low-power technique for

periodically waking up the device from Sleep. The

time-out is dependent on the discharge time of the RC

circuit on RA0. See Example 4-2 for initializing the Ultra

Low Power Wake-up module.

The series resistor provides overcurrent protection for the

RA0 pin and can allow for software calibration of the

time-out (see Figure 4-1). A timer can be used to measure

the charge time and discharge time of the capacitor. The

charge time can then be adjusted to provide the desired

interrupt delay. This technique will compensate for the

affects of temperature, voltage and component accuracy.

The Ultra Low-Power Wake-up peripheral can also be

configured as a simple Programmable Low-Voltage

Detect or temperature sensor.

Note:

For more information, refer to the

Application Note AN879, “Using the

Microchip Ultra Low-Power Wake-up

Module” (DS00879).

DS41232D-page 51

PIC12F635/PIC16F636/639

4.2.4

PIN DESCRIPTIONS AND

DIAGRAMS

4.2.4.1

RA0/C1IN+/ICSPDAT/ULPWU

Figure 4-2 shows the diagram for this pin. The RA0 pin

is configurable to function as one of the following:

Each PORTA pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions,

such as the comparator, refer to the appropriate section

in this data sheet.

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Programming™ data

• an analog input for the Ultra Low-Power Wake-up

FIGURE 4-1:

BLOCK DIAGRAM OF RA0

Analog

Input Mode⁽¹⁾

VDD

Data Bus

D

Q

Weak

CK

WR

WPUDA

RAPU

RD

Weak

WPUDA

D

Q

CK

WR

WDA

VDD

RD

WDA

D

Q

I/O pin

WR

CK

PORTA

–

+

VSS

VT

D

Q

WR

TRISA

CK

IULP

0

1

RD

TRISA

Analog

Input Mode⁽¹⁾

VSS

ULPWUE

RD

PORTA

D

Q

D

CK

WR

IOCA

Q1

EN

RD

IOCA

Interrupt-on-

Change

Q

EN

RD PORTA

Note 1: Comparator mode determines Analog Input mode.

DS41232D-page 52

PIC12F635/PIC16F636/639

4.2.4.2

RA1/C1IN-/VREF/ICSPCLK

4.2.4.3

RA2/T0CKI/INT/C1OUT

Figure 4-2 shows the diagram for this pin. The RA1 pin

is configurable to function as one of the following:

Figure 4-3 shows the diagram for this pin. The RA2 pin

is configurable to function as one of the following:

• a general purpose I/O

• an analog input to the comparator

• In-Circuit Serial Programming™ clock

• the clock input for Timer0

• an external edge-triggered interrupt

• a digital output from the comparator

FIGURE 4-2:

BLOCK DIAGRAM OF RA1

FIGURE 4-3:

BLOCK DIAGRAM OF RA2

Analog

Input Mode⁽¹⁾

Data Bus

D

Q

Data Bus

D

VDD

Q

WR

CK

WPUDA

VDD

WR

CK

WPUDA

Weak

RAPU

RD

RAPU

RD

WPUDA

Weak

D

Q

D

Q

VSS

WR

WDA

CK

VSS

WR

CK

WDA

RD

WDA

VDD

D

Q

C1OUT

VDD

D

Q

Enable

WR

PORTA

CK

WR

PORTA

CK

C1OUT

1

0

I/O pin

D

Q

I/O pin

D

Q

WR

TRISA

CK

VSS

WR

TRISA

CK

VSS

Analog

Input Mode⁽¹⁾

RD

TRISA

RD

TRISA

RD

PORTA

RD

PORTA

D

Q

D

Q

D

CK

WR

IOCA

Q

D

CK

WR

IOCA

Q1

EN

RD

IOCA

EN

Q1

D

RD

IOCA

D

EN

Interrupt-on-

change

EN

Interrupt-on-

change

RD PORTA

To Comparator

To Timer0

To INT

Note 1: Comparator mode determines Analog Input mode.

DS41232D-page 53

PIC12F635/PIC16F636/639

4.2.4.4

RA3/MCLR/VPP

Figure 4-4 shows the diagram for this pin. The RA3 pin

is configurable to function as one of the following:

• a general purpose input

• as Master Clear Reset with weak pull-up

• a high-voltage detect for Program mode entry

FIGURE 4-4:

BLOCK DIAGRAM OF RA3

VDD

Weak

MCLRE

Program

Mode

HV Detect

Reset

MCLRE

Data Bus

Input

RD

TRISA

VSS

MCLRE

RD

VSS

Q1

PORTA

D

Q

D

CK

WR

IOCA

EN

RD

IOCA

D

EN

RD PORTA

Interrupt-on-

change

WURE

Sleep

DS41232D-page 54

PIC12F635/PIC16F636/639

4.2.4.5

RA4/T1G/OSC2/CLKOUT

4.2.4.6

RA5/T1CKI/OSC1/CLKIN

Figure 4-5 shows the diagram for this pin. The RA4 pin

is configurable to function as one of the following:

Figure 4-6 shows the diagram for this pin. The RA5 pin

is configurable to function as one of the following:

• a general purpose I/O

• a Timer1 gate input

• a crystal/resonator connection

• a clock output

• a general purpose I/O

• a Timer1 clock input

• a crystal/resonator connection

• a clock input

FIGURE 4-5:

BLOCK DIAGRAM OF RA4

FIGURE 4-6:

BLOCK DIAGRAM OF RA5

Data Bus

D

Data Bus

D

CLK⁽¹⁾Modes

VDD

CLK⁽¹⁾Modes

VDD

Q

WR

CK

WPUDA

Weak

RAPU

RD

WPUDA

Weak

D

Q

D

Q

VSS

WR

WDA

CK

WDA

Oscillator

Circuit

RD

WDA

RD

WDA

Oscillator

Circuit

OSC1

VDD

CLKOUT

Enable

OSC2

VDD

D

Q

FOSC/4

1

0

WR

PORTA

CK

D

Q

WR

PORTA

CK

I/O pin

CLKOUT

Enable

D

Q

VSS

WR

TRISA

CK

D

Q

VSS

INTOSC/

RC/EC⁽²⁾

WR

TRISA

INTOSC

Mode

CK

RD

TRISA

CLKOUT

Enable

(2)

RD

TRISA

RD

PORTA

XTAL

D

Q

RD

PORTA

Q

D

CK

WR

IOCA

D

Q

Q1

EN

Q

D

CK

WR

IOCA

RD

IOCA

EN

Q1

D

RD

IOCA

D

EN

Interrupt-on-

change

EN

Interrupt-on-

change

RD PORTA

T1G To Timer1

Note 1: Oscillator modes are XT, HS, LP and LPTMR1.

Note 1: Oscillator modes are XT, HS, LP, LPTMR1 and

CLKOUT Enable.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

2: With CLKOUT option.

DS41232D-page 55

PIC12F635/PIC16F636/639

TABLE 4-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on

POR, BOR,

WUR

Value on all

other Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

INTCON

TMR1L

TMR1H

—

RA5

T0IE

RA4

RA3

RA2

T0IF

RA1

RA0

--xx xx00

0000 000x

xxxx xxxx

--uu uu00

0000 000x

uuuu uuuu

GIE

PEIE

INTE

RAIE

INTF

RAIF

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

T1CON

T1GINV

—

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON

0000 0000

---- --10

0000 0000

1111 1111

--11 1111

--11 -111

--00 0000

--11 -111

uuuu uuuu

---- --10

0000 0000

1111 1111

--11 1111

--11 -111

--00 0000

--11 -111

CMCON1

CMCON0

OPTION_REG

TRISA

—

C1OUT

INTEDG

—

CIS

—

CM2

T1GSS

CM1

CxSYNC

CM0

C2OUT

RAPU

—

C2INV

T0CS

TRISA5

C1INV

T0SE

PSA

TRISA3

—

PS2

PS1

PS0

TRISA4

TRISA2

TRISA1

TRISA0

WPUDA

IOCA

—

WPUDA5 WPUDA4

WPUDA2 WPUDA1 WPUDA0

—

IOCA5

WDA5

IOCA4

WDA4

IOCA3

—

IOCA2

WDA2

IOCA1

WDA1

IOCA0

WDA0

WDA

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

DS41232D-page 56

PIC12F635/PIC16F636/639

EXAMPLE 4-3:

INITIALIZING PORTC

4.3

PORTC

BANKSELPORTC

;

PORTC is a general purpose I/O port consisting of 6

bidirectional pins. The pins can be configured for either

digital I/O or analog input to comparator. For specific

information about individual functions, refer to the

appropriate section in this data sheet.

CLRF

MOVLW

MOVWF

PORTC

07h

CMCON0

;Init PORTC

;Set RC<4,1:0> to

;digital I/O

;

;Set RC<3:2> as inputs

;and set RC<5:4,1:0>

;as outputs

BANKSELTRISC

MOVLW

MOVWF

0Ch

TRISC

Note:

The CMCON0 register must be initialized

to configure an analog channel as a digital

input. Pins configured as analog inputs will

read ‘0’.

REGISTER 4-6:

PORTC: PORTC REGISTER

U-0

—

U-0

—

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-0

RC1

R/W-0

RC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RC<5:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

REGISTER 4-7:

TRISC: PORTC TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

R-1

R/W-1

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TRISC<5:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

DS41232D-page 57

PIC12F635/PIC16F636/639

4.3.1

RC0/C2IN+

FIGURE 4-7:

BLOCK DIAGRAM OF RC0

AND RC1

Figure 4-7 shows the diagram for this pin. The RC0 pin

is configurable to function as one of the following:

Data Bus

• a general purpose I/O

VDD

• an analog input to the comparator

D

Q

WR

PORTC

CK

4.3.2

RC1/C2IN-

Figure 4-7 shows the diagram for this pin. The RC1 pin

is configurable to function as one of the following:

I/O pin

D

Q

• a general purpose I/O

• an analog input to the comparator

WR

TRISC

CK

VSS

Analog Input

Mode

4.3.3

RC2

RD

TRISC

Figure 4-8 shows the diagram for this pin. The RC2 pin

is configurable to function as a general purpose I/O.

RD

PORTC

4.3.4

RC3

Figure 4-8 shows the diagram for this pin. The RC3 pin

is configurable to function as a general purpose I/O.

To Comparators

4.3.5

RC5

FIGURE 4-8:

BLOCK DIAGRAM OF

RC2, RC3 AND RC5

Figure 4-8 shows the diagram for this pin. The RC5 pin

is configurable to function as a general purpose I/O.

Data Bus

VDD

D

CK

Q

WR

PORTC

I/O pin

D

Q

WR

TRISC

CK

VSS

RD

TRISC

RD

PORTC

DS41232D-page 58

PIC12F635/PIC16F636/639

4.3.6

RC4/C2OUT

Figure 4-9 shows the diagram for this pin. The RC4 pin

is configurable to function as one of the following:

• a general purpose I/O

• a digital output from the comparator

FIGURE 4-9:

BLOCK DIAGRAM OF RC4

C2OUT Enable

C2OUT

Data Bus

VDD

D

Q

WR

PORTC

CK

1

0

I/O pin

D

Q

WR

TRISC

CK

VSS

RD

TRISC

RD

PORTC

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on

POR, BOR,

WUR

Value on

all other

Resets

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

CMCON0

TRISC

—

RC5

RC4

RC3

CIS

RC2

CM2

RC1

CM1

RC0

CM0

--xx xx00

0000 0000

--11 1111

--uu uu00

0000 0000

--11 1111

C2OUT C1OUT

C2INV

C1INV

—

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

DS41232D-page 59

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 60

PIC12F635/PIC16F636/639

5.1

Timer0 Operation

5.0

TIMER0 MODULE

When used as a timer, the Timer0 module can be used

as either an 8-bit timer or an 8-bit counter.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

5.1.1

8-BIT TIMER MODE

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

Figure 5-1 is a block diagram of the Timer0 module.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

5.1.2

8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register. Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

8

1

Sync

TMR0

2 TCY

T0CKI

0

1

Set Flag bit T0IF

on Overflow

T0CS

T0SE

8-bit

Prescaler

PSA

8

PSA

WDTE

SWDTEN

1

PS<2:0>

WDT

Time-out

16-bit

Prescaler

0

16

31 kHz

INTOSC

Watchdog

Timer

PSA

WDTPS<3:0>

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.

3: WDTE bit is in the Configuration Word register.

DS41232D-page 61

PIC12F635/PIC16F636/639

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 5-2).

5.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

register. To assign the prescaler to Timer0, the PSA bit

must be cleared to a ‘0’.

EXAMPLE 5-2:

CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT

;Clear WDT and

;prescaler

;

BANKSEL OPTION_REG

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

MOVLW

ANDWF

IORLW

MOVWF

b’11110000’ ;Mask TMR0 select and

OPTION_REG,W ;prescaler bits

b’00000011’ ;Set prescale to 1:16

OPTION_REG

;

5.1.4

TIMER0 INTERRUPT

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The T0IF interrupt

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register..

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

5.1.3.1

Switching Prescaler Between

Timer0 and WDT Modules

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values. When changing the prescaler assignment from

Timer0 to the WDT module, the instruction sequence

shown in Example 5-1, must be executed.

5.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, the

high and low periods of the external clock source must

meet the timing requirements as shown in the

Section 15.0 “Electrical Specifications”.

EXAMPLE 5-1:

CHANGING PRESCALER

(TIMER0 → WDT)

BANKSEL TMR0

CLRWDT

;

;Clear WDT

;Clear TMR0 and

;prescaler

CLRF

TMR0

BANKSEL OPTION_REG

;

BSF

OPTION_REG,PSA ;Select WDT

CLRWDT

;

MOVLW

ANDWF

IORLW

MOVWF

b’11111000’

OPTION_REG,W

b’00000101’

OPTION_REG

;Mask prescaler

;bits

;Set WDT prescaler

;to 1:32

DS41232D-page 62

PIC12F635/PIC16F636/639

REGISTER 5-1:

OPTION_REG: OPTION REGISTER

R/W-1

RAPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RAPU: PORTA Pull-up Enable bit

1= PORTA pull-ups are disabled

0= PORTA pull-ups are enabled by individual PORT latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: TMR0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

BIT VALUE TMR0 RATE

WDT RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.11 “Watchdog Timer (WDT)” for more

information.

TABLE 5-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on:

POR, BOR

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0

Timer0 Module Register

GIE PEIE T0IE

xxxx xxxx uuuu uuuu

INTCON

INTE

T0SE

RAIE

PSA

T0IF

PS2

INTF

PS1

RAIF 0000 000x 0000 000x

PS0 1111 1111 1111 1111

OPTION_REG RAPU INTEDG T0CS

TRISA

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the

Timer0 module.

DS41232D-page 63

PIC12F635/PIC16F636/639

6.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

• Optional LP oscillator

• Synchronous or asynchronous operation

• Timer1 gate (count enable) via comparator or

T1G pin

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Comparator output synchronization to Timer1

clock

Figure 6-1 is a block diagram of the Timer1 module.

6.1

Timer1 Operation

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

When used with an internal clock source, the module is

a timer. When used with an external clock source, the

module can be used as either a timer or counter.

6.2

Clock Source Selection

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied externally.

Clock

Source

FOSC

Mode

T1OSCEN

T1CS

FOSC/4

x

1

xxx

x

1

T1CKI pin

T1LPOSC

LP or

INTOSCIO

DS41232D-page 64

PIC12F635/PIC16F636/639

FIGURE 6-1:

TIMER1 BLOCK DIAGRAM

TMR1GE

T1GINV

TMR1ON

Set flag bit

TMR1IF on

Overflow

To C2 Comparator Module

Timer1 Clock

(2)

TMR1

TMR1H

Synchronized

clock input

0

EN

TMR1L

1

Oscillator

(1)

T1SYNC

OSC1/T1CKI

1

(3)

Synchronize

det

Prescaler

1, 2, 4, 8

0

OSC2/T1G

2

T1CKPS<1:0>

TMR1CS

1

0

INTOSC

Without CLKOUT

FOSC

1

0

CxOUT

T1OSCEN

FOSC/4

Internal

Clock

T1GSS

T1ACS

Note 1: ST Buffer is low power type when using LP osc, or high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

DS41232D-page 65

PIC12F635/PIC16F636/639

6.2.1

INTERNAL CLOCK SOURCE

6.5

Timer1 Operation in

Asynchronous Counter Mode

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of TCY as determined by the Timer1 prescaler.

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 6.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

6.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce a single spurious

increment.

In Counter mode, a falling edge must be registered by

the counter prior to the first incrementing rising edge

after one or more of the following conditions:

• Timer1 is enabled after POR or BOR Reset

• A write to TMR1H or TMR1L

• T1CKI is high when Timer1 is disabled and when

Timer1 is reenabled T1CKI is low. See Figure 6-2.

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

6.3

Timer1 Prescaler

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TTMR1L register

pair.

6.4

Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in

between pins OSC1 (input) and OSC2 (amplifier out-

put). The oscillator is enabled by setting the T1OSCEN

control bit of the T1CON register. The oscillator will

continue to run during Sleep.

6.6

Timer1 Gate

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when in LP oscillator mode. The user must

provide a software time delay to ensure proper oscilla-

tor start-up.

Timer1 gate source is software configurable to be the

T1G pin or the output of Comparator 2. This allows the

device to directly time external events using T1G or

analog events using Comparator 2. See the CMCON1

register (Register 7-3) for selecting the Timer1 gate

source. This feature can simplify the software for a

Delta-Sigma A/D converter and many other applications.

For more information on Delta-Sigma A/D converters,

see the Microchip web site (www.microchip.com).

TRISA5 and TRISA4 bits are set when the Timer1

oscillator is enabled. RA5 and RA4 bits read as ‘0’ and

TRISA5 and TRISA4 bits read as ‘1’.

Note:

TMR1GE bit of the T1CON register must

be set to use either T1G or C2OUT as the

Timer1 gate source. See Register 7-3 for

more information on selecting the Timer1

gate source.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Timer1 gate can be inverted using the T1GINV bit of

the T1CON register, whether it originates from the T1G

pin or Comparator 2 output. This configures Timer1 to

measure either the active-high or active-low time

between events.

DS41232D-page 66

PIC12F635/PIC16F636/639

6.7

Timer1 Interrupt

6.9

Comparator Synchronization

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

The same clock used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comparator changes.

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

For more information, see Section 7.0 “Comparator

Module”.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

6.8

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

DS41232D-page 67

PIC12F635/PIC16F636/639

6.10 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 6-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 6-1:

T1CON: TIMER 1 CONTROL REGISTER

R/W-0

T1GINV⁽¹⁾

R/W-0

TMR1GE⁽²⁾

R/W-0

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

T1GINV: Timer1 Gate Invert bit⁽¹⁾

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

TMR1GE: Timer1 Gate Enable bit⁽²⁾

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 is on if Timer1 gate is active

0= Timer1 is on

bit 5-4

bit 3

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1= LP oscillator is enabled for Timer1 clock

0= LP oscillator is off

Else:

This bit is ignored. LP oscillator is disabled.

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from T1CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS bit of the CMCON1

register, as a Timer1 gate source.

DS41232D-page 68

PIC12F635/PIC16F636/639

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMCON1

INTCON

PIE1

—

T1GSS

INTF

—

CMSYNC

RAIF

---- --10

0000 000x

000- 00-0

xxxx xxxx

00-- --10

0000 000x

000- 00-0

uuuu uuuu

GIE

EEIE

PEIE

T0IE

CRIE

CRIF

INTE

RAIE

C1IE

C1IF

T0IF

LVDIE

LVDIF

C2IE⁽¹⁾

C2IF⁽¹⁾

OSFIE

OSFIF

TMR1IE

TMR1IF

PIR1

EEIF

—

TMR1H

TMR1L

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

T1CON

T1GINV

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

0000 0000

uuuu uuuu

Legend:

x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1:

PIC16F636/639 only.

DS41232D-page 69

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 70

PIC12F635/PIC16F636/639

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

7.0

COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the program execution. The Analog

Comparator module includes the following features:

The PIC12F635 contains a single comparator as

shown in Figure 7-2.

The PIC16F636/639 devices contains two comparators

as shown in Figure 7-3 and Figure 7-4. The comparators

are not independently configurable.

• Dual comparators (PIC16F636/639 only)

• Multiple comparator configurations

FIGURE 7-1:

SINGLE COMPARATOR

• Comparator(s) output is available

internally/externally

VIN+

VIN-

+

Output

• Programmable output polarity

• Interrupt-on-change

–

• Wake-up from Sleep

• Timer1 gate (count enable)

• Output synchronization to Timer1 clock input

• Programmable voltage reference

VIN-

VIN+

7.1

Comparator Overview

A comparator is shown in Figure 7-1 along with the

relationship between the analog input levels and the

digital output. When the analog voltage at VIN+ is less

than the analog voltage at VIN-, the output of the

Output

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

FIGURE 7-2:

COMPARATOR OUTPUT BLOCK DIAGRAM (PIC12F635)

CMSYNC

To Timer1 Gate

To COUT pin

CINV

0

1

D

Q

Timer1

clock source

(1)

To Data Bus

Set CMIF bit

D

Q

Q1

EN

RD CMCON0

D

Q3*RD CMCON0

EN

CL

Reset

Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

DS41232D-page 71

PIC12F635/PIC16F636/639

FIGURE 7-3:

COMPARATOR C1 OUTPUT BLOCK DIAGRAM (PIC16F636/639)

C1INV

To C1OUT pin

To Data Bus

C1

D

Q

Q1

EN

RD CMCON0

Set C1IF bit

D

Q3*RD CMCON0

EN

CL

Reset

Note 1: Q1 and Q3 are phases of the four-phase system clock (FOSC).

2: Q1 is held high during Sleep mode.

FIGURE 7-4:

COMPARATOR C2 OUTPUT BLOCK DIAGRAM (PIC16F636/639)

C2SYNC

To Timer1 Gate

C2INV

0

1

C2

To C2OUT pin

D

Q

Timer1

clock source

(1)

To Data Bus

Set C2IF bit

D

Q

Q1

EN

RD CMCON0

D

Q3*RD CMCON0

EN

CL

Reset

Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

DS41232D-page 72

PIC12F635/PIC16F636/639

7.2

Analog Input Connection

Considerations

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

A simplified circuit for an analog input is shown in

Figure 7-5. Since the analog input pins share their con-

nection with a digital input, they have reverse biased

ESD protection diodes to VDD and VSS. The analog

input, therefore, must be between VSS and VDD. If the

input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur.

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

FIGURE 7-5:

ANALOG INPUT MODEL

VDD

VT ≈ 0.6V

RIC

Rs < 10K

To Comparator

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT ≈ 0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

DS41232D-page 73

PIC12F635/PIC16F636/639

The port pins denoted as “A” will read as a ‘0’

regardless of the state of the I/O pin or the I/O control

TRIS bit. Pins used as analog inputs should also have

the corresponding TRIS bit set to ‘1’ to disable the

digital output driver. Pins denoted as “D” should have

the corresponding TRIS bit set to ‘0’ to enable the

digital output driver.

7.3

Comparator Configuration

There are eight modes of operation for the comparator.

The CM<2:0> bits of the CMCON0 register are used to

select these modes as shown in Figures 7-6 and 7-7.

I/O lines change as a function of the mode and are

designed as follows:

• Analog function (A): digital input buffer is disabled

Note:

Comparator interrupts should be disabled

during a Comparator mode change to

prevent unintended interrupts.

• Digital function (D): comparator digital output,

overrides port function

• Normal port function (I/O): independent of

comparator

FIGURE 7-6:

COMPARATOR I/O OPERATING MODES (PIC12F635)

Comparator Reset (POR Default Value – low power)

Comparator w/o Output and with Internal Reference

CM<2:0> = 000

CM<2:0> = 100

A

CIN-

CIN+

A

CIN-

(1)

COUT

Off

I/O

CIN+

I/O

COUT (pin)

I/O

COUT (pin)

From CVREF Module

Comparator with Output

Multiplexed Input with Internal Reference and Output

CM<2:0> = 001

CM<2:0> = 101

A

CIN-

A

CIN-

CIS = 0

A

COUT

CIS = 1

CIN+

A

COUT

CIN+

D

COUT (pin)

D

COUT (pin)

From CVREF Module

Comparator without Output

Multiplexed Input with Internal Reference

CM<2:0> = 010

CM<2:0> = 110

A

CIN-

CIS = 0

A

COUT

CIS = 1

COUT

A

CIN+

I/O

COUT (pin)

From CVREF Module

Comparator with Output and Internal Reference

Comparator Off (Lowest power)

CM<2:0> = 011

CM<2:0> = 111

A

CIN-

I/O

CIN-

COUT

I/O

(1)

CIN+

Off

CIN+

D

COUT (pin)

I/O

COUT (pin)

From CVREF Module

Legend: A = Analog Input, ports always reads ‘0’

CIS = Comparator Input Switch (CMCON0<3>)

D = Comparator Digital Output

I/O = Normal port I/O

Note 1: Reads as ‘0’, unless CINV = 1.

DS41232D-page 74

PIC12F635/PIC16F636/639

FIGURE 7-7:

COMPARATOR I/O OPERATING MODES (PIC16F636/639)

Comparators Reset (POR Default Value)

CM<2:0> = 000

Two Independent Comparators

CM<2:0> = 100

A

VIN-

A

VIN-

C1IN-

(1)

Off

C1

C2

C1OUT

C2OUT

C1

C2

VIN+

A

VIN+

A

C1IN+

A

VIN-

A

VIN-

C2IN-

C2IN+

C2IN-

C2IN+

(1)

VIN+

Three Inputs Multiplexed to Two Comparators

CM<2:0> = 001

One Independent Comparator

CM<2:0> = 101

I/O

A

C1IN-

VIN-

C1IN-

CIS = 0 VIN-

(1)

Off

C1

VIN+

I/O

A

CIS = 1

C1IN+

C1OUT

C2OUT

C1

C2

VIN+

A

VIN-

A

VIN-

C2IN-

C2IN+

C2IN-

C2IN+

C2OUT

C2

VIN+

Four Inputs Multiplexed to Two Comparators

CM<2:0> = 010

Two Common Reference Comparators with Outputs

CM<2:0> = 110

A

VIN-

C1IN-

CIS = 0

CIS = 1

VIN-

C1OUT

C2OUT

C1

C2

VIN+

A

C1IN+

C1OUT

C2OUT

C1

C2

VIN+

D

C1OUT(pin)

A

C2IN-

C2IN+

VIN-

CIS = 0

CIS = 1

A

VIN-

C2IN-

C2IN+

VIN+

D

C2OUT(pin)

From CVREF Module

Two Common Reference Comparators

CM<2:0> = 011

Comparators Off (Lowest Power)

CM<2:0> = 111

A

VIN-

I/O

VIN-

C1IN-

C1OUT

(1)

C1

C2

VIN+

I/O

Off

C1

VIN+

I/O

C1IN+

A

VIN-

I/O

VIN-

C2IN-

C2IN+

C2IN-

C2IN+

(1)

C2OUT

Off

C2

VIN+

Legend: A = Analog Input, ports always reads ‘0’

CIS = Comparator Input Switch (CMCON0<3>)

D = Comparator Digital Output

I/O = Normal port I/O

Note 1: Reads as ‘0’, unless CxINV = 1.

DS41232D-page 75

PIC12F635/PIC16F636/639

7.4.3

COMPARATOR INPUT SWITCH

7.4

Comparator Control

The inverting input of the comparators may be switched

between two analog pins in the following modes:

The CMCON0 register (Register 7-1) provides access

to the following comparator features:

PIC12F635

• Mode selection

• Output state

• Output polarity

• Input switch

• CM<2:0> = 101

• CM<2:0> = 110

PIC16F636/639

• CM<2:0> = 001(Comparator C1 only)

7.4.1

COMPARATOR OUTPUT STATE

• CM<2:0> = 010(Comparators C1 and C2)

Each comparator state can always be read internally

via the CxOUT bit of the CMCON0 register. The com-

parator state may also be directed to the CxOUT pin in

the following modes:

In the above modes, both pins remain in Analog mode

regardless of which pin is selected as the input. The

CIS bit of the CMCON0 register controls the comparator

input switch.

PIC12F635

• CM<2:0> = 001

• CM<2:0> = 011

• CM<2:0> = 101

PIC16F636/639

• CM<2:0> = 110

When one of the above modes is selected, the

associated TRIS bit of the CxOUT pin must be cleared.

7.4.2

COMPARATOR OUTPUT POLARITY

Inverting the output of a comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of a comparator output can be inverted by set-

ting the CXINV bit of the CMCON0 register. Clearing

CXINV results in a non-inverted output. A complete

table showing the output state versus input conditions

and the polarity bit is shown in Table 7-1.

TABLE 7-1:

OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions

CxINV

CxOUT

VIN- > VIN+

VIN- < VIN+

VIN- > VIN+

VIN- < VIN+

0

1

0

1

0

Note:

CxOUT refers to both the register bit and

output pin.

DS41232D-page 76

PIC12F635/PIC16F636/639

7.5

Comparator Response Time

7.6

Comparator Interrupt Operation

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Specifications in Section 15.0 “Electrical

Specifications” for more details.

The comparator interrupt flag is set whenever there is a

change in the output value of the comparator. Changes

are recognized by means of a mismatch circuit which

consists of two latches and an exclusive-or gate (see

Figures 7-8 and 7-9). One latch is updated with the

comparator output level when the CMCON0 register is

read. This latch retains the value until the next read of

the CMCON0 register or the occurrence of a Reset.

The other latch of the mismatch circuit is updated on

every Q1 system clock. A mismatch condition will occur

when a comparator output change is clocked through

the second latch on the Q1 clock cycle. The mismatch

condition will persist, holding the CxIF bit of the PIR1

register true, until either the CMCON0 register is read

or the comparator output returns to the previous state.

Note:

A write operation to the CMCON0 register

will also clear the mismatch condition

because all writes include

a

read

operation at the beginning of the write

cycle.

Software will need to maintain information about the

status of the comparator output to determine the actual

change that has occurred.

The CxIF bit of the PIR1 register, is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since it is also possible to write a ‘1’ to

this register, a simulated interrupt may be initiated.

The CxIE bit of the PIE1 register and the PEIE and GIE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interrupt is not enabled, although the CxIF bit of the

PIR1 register will still be set if an interrupt condition

occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON0. This will end the

mismatch condition. See Figures 7-8 and 7-9.

b) Clear the CxIF interrupt flag.

A persistent mismatch condition will preclude clearing

the CxIF interrupt flag. Reading CMCON0 will end the

mismatch condition and allow the CxIF bit to be

cleared.

Note:

If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF interrupt flag may

not get set.

DS41232D-page 77

PIC12F635/PIC16F636/639

FIGURE 7-8:

COMPARATOR

INTERRUPT TIMING W/O

CMCON0 READ

Q1

Q3

CIN+

TRT

CxOUT

Set CxIF (level)

CxIF

reset by software

FIGURE 7-9:

COMPARATOR

INTERRUPT TIMING WITH

CMCON0 READ

Q1

Q3

CIN+

TRT

CxOUT

Set CxIF (level)

CxIF

cleared by CMCON0 read

reset by software

Note 1: If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF of the PIR1

register interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is stable.

Allow about 1 μs for bias settling then clear

the mismatch condition and interrupt flags

before enabling comparator interrupts.

DS41232D-page 78

PIC12F635/PIC16F636/639

7.7

Operation During Sleep

7.8

Effects of a Reset

The comparator, if enabled before entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in the

Section 15.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comparator. The comparator is turned off

by selecting mode CM<2:0> = 000or CM<2:0> = 111

of the CMCON0 register.

A device Reset forces the CMCON0 and CMCON1

registers to their Reset states. This forces the Compar-

ator module to be in the Comparator Reset mode

(CM<2:0> = 000). Thus, all comparator inputs are

analog inputs with the comparator disabled to consume

the smallest current possible.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the device from Sleep, the CxIE bit of the PIE1 register

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the Interrupt Service Routine.

REGISTER 7-1:

CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC12F635)

U-0

—

R-0

U-0

—

R/W-0

CINV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

COUT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

COUT: Comparator Output bit

When CINV = 0:

1= VIN+ > VIN-

0= VIN+ < VIN-

When CINV = 1:

1= VIN+ < VIN-

0= VIN+ > VIN-

bit 5

bit 4

Unimplemented: Read as ‘0’

CINV: Comparator Output Inversion bit

1= Output inverted

0= Output not inverted

bit 3

CIS: Comparator Input Switch bit

When CM<2:0> = 110or 101:

1= CIN+ connects to VIN-

0= CIN- connects to VIN-

When CM<2:0> = 0xxor 100or 111:

CIS has no effect.

bit 2-0

CM<2:0>: Comparator Mode bits (See Figure 7-5)

000= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off

001= CIN pins are configured as analog, COUT pin configured as Comparator output

010= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally

011= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as

Comparator output, CVREF is non-inverting input

100= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output

available internally, CVREF is non-inverting input

101= CIN pins are configured as analog and multiplexed, COUT pin is configured as

Comparator output, CVREF is non-inverting input

110= CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O,

Comparator output available internally, CVREF is non-inverting input

111= CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.

DS41232D-page 79

PIC12F635/PIC16F636/639

REGISTER 7-2:

CMCON0: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639)

R-0

C2OUT

bit 7

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

C1OUT

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

1= C2 VIN+ < C2 VIN-

0= C2 VIN+ > C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

1= C1 VIN+ < C1 VIN-

0= C1 VIN+ > C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 output inverted

0= C2 output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 Output inverted

0= C1 Output not inverted

CIS: Comparator Input Switch bit

When CM<2:0> = 010:

1= C1IN+ connects to C1 VIN-

C2IN+ connects to C2 VIN-

0= C1IN- connects to C1 VIN-

C2IN- connects to C2 VIN-

When CM<2:0> = 001:

1= C1IN+ connects to C1 VIN-

0= C1IN- connects to C1 VIN-

bit 2-0

CM<2:0>: Comparator Mode bits (See Figure 7-5)

000= Comparators off. CxIN pins are configured as analog

001= Three inputs multiplexed to two comparators

010= Four inputs multiplexed to two comparators

011= Two common reference comparators

100= Two independent comparators

101= One independent comparator

110= Two comparators with outputs and common reference

111= Comparators off. CxIN pins are configured as digital I/O

DS41232D-page 80

PIC12F635/PIC16F636/639

7.9

Comparator Gating Timer1

This feature can be used to time the duration or inter-

val of analog events. Clearing the T1GSS bit of the

CMCON1 register will enable Timer1 to increment

based on the output of the comparator (or Comparator

C2 for PIC16F636/639). This requires that Timer1 is

on and gating is enabled. See Section 6.0 “Timer1

Module with Gate Control” for details.

It is recommended to synchronize the comparator with

Timer1 by setting the CxSYNC bit when the comparator

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if the comparator changes

during an increment.

Note:

References to the comparator in this

section specifically are referring to

Comparator C2 on the PIC16F636/639.

7.10 Synchronizing Comparator Output

to Timer1

The comparator (or Comparator C2 for PIC16F636/639)

output can be synchronized with Timer1 by setting the

CxSYNC bit of the CMCON1 register. When enabled,

the comparator output is latched on the falling edge of

the Timer1 clock source. If a prescaler is used with

Timer1, the comparator output is latched after the

prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the rising

edge of its clock source. See the Comparator Block

Diagram (Figure 7-2) and the Timer1 Block Diagram

(Figure 6-1) for more information.

Note:

References to the comparator in this

section specifically are referring to

Comparator C2 on the PIC16F636/639.

DS41232D-page 81

PIC12F635/PIC16F636/639

REGISTER 7-3:

CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC12F635)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

T1GSS

CMSYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’

T1GSS: Timer1 Gate Source Select bit⁽¹⁾

1= Timer1 Gate Source is T1G pin (pin should be configured as digital input)

0= Timer1 Gate Source is comparator output

bit 0

CMSYNC: Comparator Output Synchronization bit⁽²⁾

1= Output is synchronized with falling edge of Timer1 clock

0= Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 7-2.

REGISTER 7-4:

CMCON1: COMPARATOR CONFIGURATION REGISTER (PIC16F636/639)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

T1GSS

C2SYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’

T1GSS: Timer1 Gate Source Select bit⁽¹⁾

1= Timer1 gate source is T1G pin (pin should be configured as digital input)

0= Timer1 gate source is Comparator C2 output

bit 0

C2SYNC: Comparator C2 Output Synchronization bit⁽²⁾

1= Output is synchronized with falling edge of Timer1 clock

0= Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 7-4.

DS41232D-page 82

PIC12F635/PIC16F636/639

7.11.3

OUTPUT CLAMPED TO VSS

7.11 Comparator Voltage Reference

The CVREF output voltage can be set to Vss with no

power consumption by configuring VRCON as follows:

The Comparator Voltage Reference module provides

an internally generated voltage reference for the

comparators. The following features are available:

• VREN = 0

• VRR = 1

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

• VR<3:0> = 0000

This allows the comparator to detect a zero-crossing

while not consuming additional CVREF module current.

• Ratiometric with VDD

• Fixed Voltage Reference

7.11.4

OUTPUT RATIOMETRIC TO VDD

The VRCON register (Register 7-5) controls the

Voltage Reference module shown in Figure 7-10.

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 15.0 “Elec-

trical Specifications”.

7.11.1

INDEPENDENT OPERATION

The comparator voltage reference is independent of

the comparator configuration. Setting the VREN bit of

the VRCON register will enable the voltage reference.

7.11.2

OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

register.

The CVREF output voltage is determined by the following

equations:

EQUATION 7-1:

CVREF OUTPUT VOLTAGE

(INTERNAL CVREF)

VRR = 1 (low range):

CVREF = (VR<3:0>/24) × VDD

VRR = 0 (high range):

CVREF = (VDD/4) +

(VR<3:0> × VDD/32)

EQUATION 7-2:

CVREF OUTPUT VOLTAGE

(EXTERNAL CVREF)

VRR = 1 (low range):

CVREF = (VR<3:0>/24) × VLADDER

VRR = 0 (high range):

CVREF = (VLADDER/4) + (VR<3:0> × VLADDER/32)

VLADDER = VDD or ([VREF+] - [VREF-]) or VREF+

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 7-10.

DS41232D-page 83

PIC12F635/PIC16F636/639

REGISTER 7-5:

VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

VREN

U-0

—

R/W-0

VRR

U-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

VREN: CVREF Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down, no IDD drain and CVREF = VSS.

bit 6

bit 5

Unimplemented: Read as ‘0’

VRR: CVREF Range Selection bit

1= Low range

0= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: CVREF Value Selection bits (0 ≤ VR<3:0> ≤ 15)

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

FIGURE 7-10:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

VRR

8R

16-1 Analog

MUX

VREN

15

14

CVREF to

Comparator

Input

2

1

0

(1)

VR<3:0>

VREN

VR<3:0> = 0000

VRR

Note 1: Care should be taken to ensure VREF remains

within the comparator common mode input

range. See Section 15.0 “Electrical Specifica-

tions” for more detail.

DS41232D-page 84

PIC12F635/PIC16F636/639

TABLE 7-2:

SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

CMCON0

CMCON1

INTCON

PIE1

—

COUT

—

CINV

—

CIS

—

CM2

—

CM1

T1GSS

INTF

—

CM0

CMSYNC

RAIF

-0-0 0000 -0-0 0000

---- --10 ---- --10

0000 000x 0000 000x

000- 00-0 000- 00-0

--xx xxxx --uu uuuu

--11 1111 --11 1111

0-0- 0000 0-0- 0000

—

GIE

EEIE

EEIF

—

PEIE

LVDIE

LVDIF

—

T0IE

CRIE

CRIF

RA5

RC5

INTE

—

RAIE

C1IE

C1IF

RA3

RC3

T0IF

OSFIE

OSFIF

RA2

TMR1IE

TMR1IF

RA0

PIR1

—

PORTA

PORTC

TRISA

RA4

RC4

RA1

RC1

—

RC2

RC0

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1

TRISC5 TRISC4 TRISC3 TRISC2 TRISC1

TRISA0

TRISC0

VR0

TRISC

—

VRCON

VREN

—

VRR

—

VR3

VR2

VR1

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for comparator.

DS41232D-page 85

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 86

PIC12F635/PIC16F636/639

The PLVD module includes the following capabilities:

8.0

PROGRAMMABLE

LOW-VOLTAGE DETECT

(PLVD) MODULE

• Eight programmable trip points

• Interrupt on falling VDD

• Stable reference indication

The Programmable Low-Voltage Detect (PLVD)

module is a power supply detector which monitors the

internal power supply. This module is typically used in

key fobs and other devices, where certain actions

need to be taken as a result of a falling battery voltage.

• Operation during Sleep

A Block diagram of the PLVD module is shown in

Figure 8-1.

FIGURE 8-1:

PLVD BLOCK DIAGRAM

8 Stages

VDD

8-to-1

Analog MUX

LVDEN

0

1

2

+

-

LVDIF

det

6

7

LVDL<2:0>

Reference

Voltage

Generator

FIGURE 8-2:

PLVD OPERATION

VDD

PLVD Trip Point

LVDIF

Cleared by

Software

Set by

Hardware

DS41232D-page 87

PIC12F635/PIC16F636/639

8.1

PLVD Operation

8.4

Stable Reference Indication

To setup the PLVD for operation, the following steps

must be taken:

When the PLVD module is enabled, the reference volt-

age must be allowed to stabilize before the PLVD will

provide a valid result. Refer to Electrical Section,

PLVD Characteristics for the stabilization time.

• Enable the module by setting the LVDEN bit of the

LVDCON register.

When the HFINTOSC is running, the IRVST bit of the

LVDCON register indicates the stability of the voltage

reference. The voltage reference is stable when the

IRVST bit is set.

• Configure the trip point by setting the LVDL<2:0>

bits of the LVDCON register.

• Wait for the reference voltage to become stable.

Refer to Section 8.4 “Stable Reference

Indication”.

8.5

Operation During Sleep

• Clear the LVDIF bit of the PIRx register.

To wake from Sleep, set the LVDIE bit of the PIEx

register and the PEIE bit of the INTCON register. When

the LVDIE and PEIE bits are set, the device will wake

from Sleep and execute the next instruction. If the GIE

bit is also set, the program will call the Interrupt Service

Routine upon completion of the first instruction after

waking from Sleep.

The LVDIF bit will be set when VDD falls below the

PLVD trip point. The LVDIF bit remains set until cleared

by software. Refer to Figure 8-2.

8.2

Programmable Trip Point

The PLVD trip point is selectable from one of eight

voltage levels. The LVDL bits of the LVDCON register

select the trip point. Refer to Register 8-1 for the

available PLVD trip points.

8.3

Interrupt on Falling VDD

When VDD falls below the PLVD trip point, the falling

edge detector will set the LVDIF bit. See Figure 8-2. An

interrupt will be generated if the following bits are also

set:

• GIE and PEIE bits of the INTCON register

• LVDIE bit of the PIEx register

The LVDIF bit must be cleared by software. An interrupt

can be generated from a simulated PLVD event when

the LVDIF bit is set by software.

DS41232D-page 88

PIC12F635/PIC16F636/639

REGISTER 8-1:

LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER

U-0

—

U-0

—

R-0

IRVST⁽¹⁾

R/W-0

U-0

—

R/W-1

LVDL2

R/W-0

LVDL1

R/W-0

LVDL0

LVDEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

IRVST: Internal Reference Voltage Stable Status Flag bit⁽¹⁾

1= Indicates that the PLVD is stable and PLVD interrupt is reliable

0= Indicates that the PLVD is not stable and PLVD interrupt must not be enabled

bit 4

LVDEN: Low-Voltage Detect Module Enable bit

1= Enables PLVD Module, powers up PLVD circuit and supporting reference circuitry

0= Disables PLVD Module, powers down PLVD circuit and supporting reference circuitry

bit 3

Unimplemented: Read as ‘0’

bit 2-0

LVDL<2:0>: Low-Voltage Detection Level bits (nominal values)

111= 4.5V

110= 4.2V

101= 4.0V

100= 2.3V (default)

011= 2.2V

010= 2.1V

001= 2.0V⁽²⁾

000= Reserved

Note 1: The IRVST bit is usable only when the HFINTOSC is running.

2: Not tested and below minimum operating conditions.

TABLE 8-1:

REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

OSFIE

OSFIF

—

PEIE

C2IE

C2IF

—

T0IE

C1IE

INTE

LCDIE

LCDIF

LVDEN

RAIE

—

T0IF

LVDIE

LVDIF

LVDL2

INTF

—

RAIF

0000 000x 0000 000x

CCP2IE 0000 -0-0 0000 -0-0

CCP2IF 0000 -0-0 0000 -0-0

PIR1

C1IF

—

LVDCON

IRVST

—

LVDL1

LVDL0

--00 -100 --00 -100

Legend:

x= unknown, -= unimplemented read as ‘0’. Shaded cells are not used by the PLVD module.

DS41232D-page 89

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 90

PIC12F635/PIC16F636/639

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

9.0

DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from chip-to-chip. Please refer to A/C specifications in

Section 15.0 “Electrical Specifications” for exact

limits.

• EECON1

• EECON2 (not a physically implemented register)

When the data memory is code-protected, the CPU

may continue to read and write the data EEPROM

memory. The device programmer can no longer access

the data EEPROM data and will read zeroes.

• EEDAT

• EEADR

EEDAT holds the 8-bit data for read/write and EEADR

holds the address of the EEPROM location being

accessed. PIC16F636/639 has 256 bytes of data

EEPROM and the PIC12F635 has 128 bytes.

REGISTER 9-1:

EEDAT: EEPROM DATA REGISTER

R/W-0

EEDAT7

bit 7

R/W-0

EEDAT6

EEDAT5

EEDAT4

EEDAT3

EEDAT2

EEDAT1

EEDAT0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

EEDATn: Byte Value to Write To or Read From Data EEPROM bits

REGISTER 9-2:

EEADR: EEPROM ADDRESS REGISTER

R/W-0

EEADR7⁽¹⁾

bit 7

R/W-0

EEADR6

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits

Note 1: PIC16F636/639 only. Read as ‘0’ on PIC12F635.

DS41232D-page 91

PIC12F635/PIC16F636/639

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal

operation. In these situations, following Reset, the user

can check the WRERR bit, clear it and rewrite the

location. The data and address will be cleared.

Therefore, the EEDAT and EEADR registers will need

to be re-initialized.

9.1

EECON1 AND EECON2 Registers

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are

non-implemented and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

Interrupt flag, EEIF bit of the PIR1 register, is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

Note:

The EECON1, EEDAT and EEADR

registers should not be modified during a

data EEPROM write (WR bit = 1).

REGISTER 9-3:

EECON1: EEPROM CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

WRERR

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WRERR: EEPROM Error Flag bit

1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0= The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the data EEPROM

WR: Write Control bit

1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only

be set, not cleared, in software.)

0= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set, not cleared, in software.)

0= Does not initiate an EEPROM read

DS41232D-page 92

PIC12F635/PIC16F636/639

9.2

Reading the EEPROM Data

Memory

9.4

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 9-3) to the

desired value to be written.

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD of the EECON1 register, as shown in Example 9-1.

The data is available, in the very next cycle, in the

EEDAT register. Therefore, it can be read in the next

instruction. EEDAT holds this value until another read, or

until it is written to by the user (during a write operation).

EXAMPLE 9-3:

WRITE VERIFY

BANKSEL EEDAT

;

MOVF

BSF

EEDAT,W

;EEDAT not changed

;from previous write

EECON1,RD ;YES, Read the

EXAMPLE 9-1:

DATA EEPROM READ

;value written

;

;Is data the same

BANKSEL EEADR

;

XORWF

BTFSS

GOTO

:

EEDAT,W

STATUS,Z

WRITE_ERR ;No, handle error

;Yes, continue

MOVLW

MOVWF

BSF

CONFIG_ADDR

EEADR

;

;Address to read

EECON1,RD

EEDAT,W

;EE Read

;Move data to W

MOVF

9.4.1

USING THE DATA EEPROM

9.3

Writing to the EEPROM Data

Memory

The data EEPROM is

a high-endurance, byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). When variables in one section change

frequently, while variables in another section do not

change, it is possible to exceed the total number of

write cycles to the EEPROM (specification D124)

without exceeding the total number of write cycles to a

single byte (specifications D120 and D120A). If this is

the case, then a refresh of the array must be

performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 9-2.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental writes

to data EEPROM due to errant (unexpected) code

execution (i.e., lost programs). The user should keep the

WREN bit clear at all times, except when updating

EEPROM. The WREN bit is not cleared by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit of the

PIR1 register must be cleared by software.

EXAMPLE 9-2:

DATA EEPROM WRITE

BANKSEL EEADR

;

BSF

EECON1,WREN

;Enable write

BCF

INTCON,GIE

55h

EECON2

AAh

EECON2

;Disable INTs

;Unlock write

;

MOVLW

MOVWF

MOVLW

MOVWF

BSF

;

EECON1,WR

INTCON,GIE

;Start the write

;Enable INTS

BSF

DS41232D-page 93

PIC12F635/PIC16F636/639

9.5

Protection Against Spurious Write

9.6

Data EEPROM Operation During

Code Protection

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up Timer (nominal 64 ms duration) prevents

EEPROM write.

Data memory can be code-protected by programming

the CPD bit in the Configuration Word (Register 12-1)

to ‘0’.

When the data memory is code-protected, the CPU is

able to read and write data to the data EEPROM. It is

recommended to code-protect the program memory

when code-protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also help prevent data memory code protection

from becoming breached.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

TABLE 9-1:

SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

INTCON

PIR1

GIE

EEIF

EEIE

PEIE

LVDIF

LVDIE

EEDAT6

EEADR6

—

T0IE

CRIF

INTE

C2IF⁽¹⁾

C2IE⁽¹⁾

EEDAT4

EEADR4

—

RAIE

C1IF

T0IF

OSFIF

INTF

—

RAIF

TMR1IF

TMR1IE

EEDAT0

EEADR0

RD

0000 000x

0000 00-0

0000 0000

---- x000

---- ----

0000 000x

0000 00-0

0000 0000

---- q000

---- ----

PIE1

CRIE

C1IE

OSFIE

EEDAT2

EEADR2

WREN

—

EEDAT

EEDAT7

EEADR7⁽¹⁾

—

EEDAT5

EEADR5

—

EEDAT3

EEADR3

WRERR

EEDAT1

EEADR1

WR

EEADR

EECON1

EECON2

Legend:

EEPROM Control Register 2 (not a physical register)

x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by the data EEPROM module.

Note 1: PIC16F636/639 only.

DS41232D-page 94

PIC12F635/PIC16F636/639

®

10.0 KEELOQ COMPATIBLE

CRYPTOGRAPHIC MODULE

To obtain information regarding the implementation of

the KEELOQ module, Microchip Technology requires

®

the execution of the “KEELOQ Encoder License

Agreement”.

®

The “KEELOQ Encoder License Agreement” may be

accessed through the Microchip web site located at

www.microchip.com/KEELOQ. Further information may

be obtained by contacting your local Microchip Sales

Representative.

DS41232D-page 95

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 96

PIC12F635/PIC16F636/639

11.2 Modulation Circuit

11.0 ANALOG FRONT-END (AFE)

FUNCTIONAL DESCRIPTION

(PIC16F639 ONLY)

The modulation circuit consists of a modulation

transistor (FET), internal tuning capacitors and external

LC antenna components. The modulation transistor

The PIC16F639 device consists of the PIC16F636

device and low frequency (LF) Analog Front-End

(AFE), with the AFE section containing three

analog-input channels for signal detection and LF

talk-back. This section describes the Analog Front-End

(AFE) in detail.

and the internal tuning capacitors are connected

between the LC input pin and LCCOM pin. Each LC

input has its own modulation transistor.

When the modulation transistor turns on, its low Turn-on

Resistance (RM) clamps the induced LC antenna

voltage. The coil voltage is minimized when the

modulation transistor turns-on and maximized when the

modulation transistor turns-off. The modulation

transistor’s low Turn-on Resistance (RM) results in a

high modulation depth.

The PIC16F639 device can detect a 125 kHz input

signal as low as 1 mVpp and transmit data by using

internal LF talk-back modulation or via an external

transmitter. The PIC16F639 can also be used for

various bidirectional communication applications.

Figure 11-3 and Figure 11-4 show application examples

of the device.

The LF talk-back is achieved by turning on and off the

modulation transistor.

The modulation data comes from the microcontroller

section via the digital SPI interface as “Clamp On”,

“Clamp Off” commands. Only those inputs that are

enabled will execute the clamp command. A basic

block diagram of the modulation circuit is shown in

Figure 11-1 and Figure 11-2.

Each analog input channel has internal tuning

capacitance, sensitivity control circuits, an input signal

strength limiter and an LF talk-back modulation

transistor. An Automatic Gain Control (AGC) loop is

used for all three input channel gains. The output of

each channel is OR’d and fed into a demodulator. The

digital output is passed to the LFDATA pin. Figure 11-1

shows the block diagram of the AFE and Figure 11-2

shows the LC input path.

The modulation FET is also shorted momentarily after

Soft Reset and Inactivity timer time-out.

11.3 Tuning Capacitor

There are a total of eight Configuration registers. Six of

them are used for AFE operation options, one for

column parity bits and one for status indication of AFE

operation. Each register has 9 bits including one row

parity bit. These registers are readable and writable by

SPI (Serial Protocol Interface) commands except for

the STATUS register, which is read-only.

Each channel has internal tuning capacitors for external

antenna tuning. The capacitor values are programmed

by the Configuration registers up to 63 pF, 1 pF per step.

Note:

The user can control the tuning capacitor

by programming the AFE Configuration

registers.

11.1 RF Limiter

11.4 Variable Attenuator

The RF Limiter limits LC pin input voltage by de-Q’ing

the attached LC resonant circuit. The absolute voltage

limit is defined by the silicon process’s maximum

allowed input voltage (see Section 15.0 “Electrical

Specifications”). The limiter begins de-Q’ing the

external LC antenna when the input voltage exceeds

VDE_Q, progressively de-Q’ing harder to reduce the

antenna input voltage.

The variable attenuator is used to attenuate, via AGC

control, the input signal voltage to avoid saturating the

amplifiers and demodulators.

Note:

The variable attenuator function is

accomplished by the device itself. The

user cannot control its function.

The signal levels from all 3 channels are combined

such that the limiter attenuates all 3 channels

uniformly, in respect to the channel with the strongest

signal.

11.5 Sensitivity Control

The sensitivity of each channel can be reduced by the

channel’s Configuration register sensitivity setting.

This is used to desensitize the channel from optimum.

Note:

The user can desensitize the channel

sensitivity by programming the AFE

Configuration registers.

DS41232D-page 97

PIC12F635/PIC16F636/639

11.6 AGC Control

11.10 Demodulator

The AGC controls the variable attenuator to limit the

internal signal voltage to avoid saturation of internal

amplifiers and demodulators (Refer to Section 11.4

“Variable Attenuator”).

The Demodulator consists of a full-wave rectifier, low

pass filter, peak detector and Data Slicer that detects

the envelope of the input signal.

11.11 Data Slicer

The signal levels from all 3 channels are combined

such that AGC attenuates all 3 channels uniformly in

respect to the channel with the strongest signal.

The Data Slicer consists of a reference generator and

comparator. The Data Slicer compares the input with

the reference voltage. The reference voltage comes

from the minimum modulation depth requirement

setting and input peak voltage. The data from all 3

channels are OR’d together and sent to the output

enable filter.

Note:

The AGC control function is accomplished

by the device itself. The user cannot

control its function.

11.7 Fixed Gain Amplifiers 1 and 2

FGA1 and FGA2 provides a maximum two-stage gain

of 40 dB.

11.12 Output Enable Filter

The Output Enable Filter enables the LFDATA output

once the incoming signal meets the wake-up sequence

requirements (see Section 11.15 “Configurable

Output Enable Filter”).

Note:

The user cannot control the gain of these

two amplifiers.

11.8 Auto Channel Selection

11.13 RSSI (Received Signal Strength

Indicator)

The Auto Channel Selection feature is enabled if the

Auto Channel Select bit AUTOCHSEL<8> in Configu-

ration Register 5 (Register 11-6) is set, and disabled if

the bit is cleared. When this feature is active (i.e.,

AUTOCHSE <8> = 1), the control circuit checks the

demodulator output of each input channel immediately

after the AGC settling time (TSTAB). If the output is high,

it allows this channel to pass data, otherwise it is

blocked.

The RSSI provides a current which is proportional to the

input signal amplitude (see Section 11.31.3 “Received

Signal Strength Indicator (RSSI) Output”).

11.14 Analog Front-End Timers

The AFE has an internal 32 kHz RC oscillator. The

oscillator is used in several timers:

The status of this operation is monitored by AFE Status

Register 7 bits <8:6> (Register 11-8). These bits indicate

the current status of the channel selection activity, and

automatically updates for every Soft Reset period. The

auto channel selection function resets after each Soft

Reset (or after Inactivity timer time-out). Therefore, the

blocked channels are reenabled after Soft Reset.

• Inactivity timer

• Alarm timer

• Pulse Width timer

• Period timer

• AGC settling timer

11.14.1 RC OSCILLATOR

This feature can make the output signal cleaner by

blocking any channel that was not high at the end of

TAGC. This function works only for demodulated data

output, and is not applied for carrier clock or RSSI

output.

The RC oscillator is low power, 32 kHz ± 10% over

temperature and voltage variations.

11.9 Carrier Clock Detector

The Detector senses the input carrier cycles. The

output of the Detector switches digitally at the signal

carrier frequency. Carrier clock output is available

when the output is selected by the DATOUT bit in the

AFE Configuration Register 1 (Register 11-2).

DS41232D-page 98

PIC12F635/PIC16F636/639

The timer is reset when the:

11.14.2 INACTIVITY TIMER

• CS pin is low (any SPI command).

• Output enable filter is disabled.

The Inactivity Timer is used to automatically return the

AFE to Standby mode, if there is no input signal. The

time-out period is approximately 16 ms (TINACT), based

on the 32 kHz internal clock.

• LFDATA pin is enabled (signal passed output

enable filter).

The purpose of the Inactivity Timer is to minimize AFE

current draw by automatically returning the AFE to the

lower current Standby mode, if there is no input signal

for approximately 16 ms.

The timer starts when:

• Receiving a LF signal.

The timer causes a low output on the ALERT pin when:

The timer is reset when:

• Output enable filter is enabled and modulated

input signal is present for TALARM, but does not

pass the output enable filter requirement.

• An amplitude change in LF input signal, either

high-to-low or low-to-high

Note:

The Alarm timer is disabled if the output

enable filter is disabled.

• CS pin is low (any SPI command)

• Timer-related Soft Reset

The timer starts when:

11.14.4 PULSE WIDTH TIMER

• AFE receives any LF signal

The timer causes an AFE Soft Reset when:

The Pulse Width Timer is used to verify that the

received output enable sequence meets both the

minimum TOEH and minimum TOEL requirements.

• A previously received LF signal does not change

either high-to-low or low-to-high for TINACT

11.14.5 PERIOD TIMER

The Soft Reset returns the AFE to Standby mode where

most of the analog circuits, such as the AGC,

demodulator and RC oscillator, are powered down. This

returns the AFE to the lower Standby Current mode.

The Period Timer is used to verify that the received

output enable sequence meets the maximum TOET

requirement.

11.14.6 AGC SETTLING TIMER (TAGC)

11.14.3 ALARM TIMER

This timer is used to keep the output enable filter in

Reset while the AGC settles on the input signal. The

time-out period is approximately 3.5 ms. At end of this

time (TAGC), the input should remain high (TPAGC),

otherwise the counting is aborted and a Soft Reset is

issued. See Figure 11-6 for details.

The Alarm Timer is used to notify the MCU that the AFE

is receiving LF signal that does not pass the output

enable filter requirement. The time-out period is

approximately 32 ms (TALARM) in the presence of

continuing noise.

The Alarm Timer time-out occurs if there is an input

signal for longer than 32 ms that does not meet the

output enable filter requirements. The Alarm Timer

time-out causes:

Note 1: The AFE needs continuous and

uninterrupted high input signal during

AGC settling time (TAGC). Any absence of

signal during this time may reset the timer

and a new input signal is needed for AGC

settling time, or may result in improper

AGC gain settings which will produce

invalid output.

a) The ALERT pin to go low.

b) The ALARM bit to set in the AFE Status

Configuration 7 register (Register 11-8).

The MCU is informed of the Alarm timer time-out by

monitoring the ALERT pin. If the Alarm timer time-out

occurs, the MCU can take appropriate actions such as

lowering channel sensitivity or disabling channels. If

the noise source is ignored, the AFE can return to a

lower standby current draw state.

2: The rest of the AFE section wakes up if

any of these input channels receive the

AGC

settling

time

correctly.

<4:2>

AFE Status Register 7

bits

(Register 11-8) indicate which input

channels have waken up the AFE first.

Valid input signal on multiple input pins

can cause more than one channel’s

indicator bit to be set.

DS41232D-page 99

PIC12F635/PIC16F636/639

FIGURE 11-1:

FUNCTIONAL BLOCK DIAGRAM – ANALOG FRONT-END

÷ 64

AGC

LCX

Detector

WAKEX

Tune X

RF

Lim

Sensitivity

Control X

Mod

A

÷ 64

LCCOM

WAKEY

AGC

LCY

Σ

Detector

WAKEZ

Tune Y

RF

Lim

Sensitivity

Control Y

Mod

A

LCCOM

÷ 64

AGC

LCZ

Detector

Tune Z

RF

Lim

Sensitivity

Control Z

Watchdog

Mod

A

B

Modulation

Depth

To Sensitivity X

32 kHZ

Oscillator

AGC

Timer

Output Enable

Filter

LCCOM

To Sensitivity Y

To Sensitivity Z

AGC Preserve

Command Decoder/Controller

To Modulation

Transistors

To Tuning Cap X

To Tuning Cap Y

To Tuning Cap Z

Configuration

Registers

RSSI

SCLK/ALERT

CS

LFDATA/RSSI/

CCLK/SDIO

VSST

VDDT

MCU

DS41232D-page 100

PIC12F635/PIC16F636/639

FIGURE 11-2:

LC INPUT PATH

DS41232D-page 101

PIC12F635/PIC16F636/639

FIGURE 11-3:

BIDIRECTIONAL PASSIVE KEYLESS ENTRY (PKE) SYSTEM APPLICATION EXAMPLE

d

e

s

t

e

p

d

y

o

r

C

c

n

E

e

s

)

n

F

o

H

p

U

s

(

e

R

LED

UHF

Transmitter

UHF

Receiver

Ant. X

Ant. Y

Ant. Z

d

n

a

H

m

k

m

5

o

2

C

1

F

(

L

PIC16F639

)

z

MCU

(PIC16F636)

LF

+

Transmitter/

Receiver

3 Input

Analog Front-End

Base Station

Transponder

FIGURE 11-4:

PASSIVE KEYLESS ENTRY (PKE) TRANSPONDER CONFIGURATION EXAMPLE

+3V

315 MHz

VDD

VSS

1

20

19

18

+3V

S0

S3

2

S1

S4

3

S2

S5

4

17

16

RF Circuitry

LED

Data

5

(UHF TX)

RFEN

CS

6

15

14

13

12

11

LFDATA/RSSI/CCLK/SDIO

SCLK/ALERT

VSST

LCCOM

LCZ

7

+3V

VDDT

LCX

LCY

8

9

10

air-core

coil

ferrite-core

coil

ferrite-core

coil

DS41232D-page 102

PIC12F635/PIC16F636/639

11.15 Configurable Output Enable Filter

The purpose of this filter is to enable the LFDATA output

and wake the microcontroller only after receiving a

specific sequence of pulses on the LC input pins.

Therefore, it prevents the AFE from waking up the

microcontroller due to noise or unwanted input signals.

The circuit compares the timing of the demodulated

header waveform with a pre-defined value, and enables

the demodulated LFDATA output when a match occurs.

The output enable filter consists of a high (TOEH) and

low duration (TOEL) of a pulse immediately after the

AGC settling gap time. The selection of high and low

times further implies a max period time. The output

enable high and low times are determined by SPI

interface programming. Figure 11-5 and Figure 11-6

show the output enable filter waveforms.

There should be no missing cycles during TOEH.

Missing cycles may result in failing the output enable

condition.

FIGURE 11-5:

OUTPUT ENABLE FILTER TIMING

Required Output Enable Sequence

Data Packet

Start bit

TSTAB

(TAGC + TPAGC)

Demodulator

Output

TGAP

t ≥ TOEH

t ≥ TOEL

AGC

Gap Pulse

AFE Wake-up

and AGC Stabilization

LFDATA output is enabled

on this rising edge

t

≤ TOET

DS41232D-page 103

PIC12F635/PIC16F636/639

FIGURE 11-6:

OUTPUT ENABLE FILTER TIMING EXAMPLE (DETAILED)

Start bit

LFDATA Output

LF Coil Input

3.5 ms

TPAGC

TGAP

Gap

Pulse

Low

t ≥ TOEL

t ≥ TE

Current

Standby

Mode

(need

“high”)

TAGC

(AGC settling time)

t ≥ TOEH

t ≤ TOET

TSTAB

(AFE Stabilization)

Filter

starts

Filter is passed and

LFDATA is enabled

Legend:

TAGC = AGC stabilization time

TE = Time element of pulse

TGAP = AGC stabilization gap

TOEH = Minimum output enable filter high time

TOEL = Minimum output enable filter low time

TOET = Maximum output enable filter period

TPAGC = High time after TAGC

TSTAB = TAGC + TPAGC

DS41232D-page 104

PIC12F635/PIC16F636/639

If the filter resets due to a long high (TOEH > TOET), the

high-pulse timer will not begin timing again until after a

gap of TE and another low-to-high transition occurs on

TABLE 11-1: TYPICAL OUTPUT ENABLE

FILTER TIMING

OEH

OEL

TOEH

(ms)

TOEL

(ms)

TOET

the demodulator output.

<1:0>

(ms)

Disabling the output enable filter disables the TOEH and

TOEL requirement and the AFE passes all received LF

data. See Figure 11-10, Figure 11-11 and Figure 11-12

for examples.

01

00

01

10

11

1

2

4

3

4

6

When viewed from an application perspective, from the

pin input, the actual output enable filter timing must fac-

tor in the analog delays in the input path (such as

demodulator charge and discharge times).

10

00

01

10

11

2

1

2

4

5

8

• TOEH - TDR + TDF

• TOEL + TDR - TDF

The output enable filter starts immediately after TGAP,

the gap after AGC stabilization period.

11

00

01

10

11

4

1

2

4

6

11.16 Input Sensitivity Control

8

10

The AFE is designed to have typical input sensitivity of

3 mVPP. This means any input signal with amplitude

greater than 3 mVPP can be detected. The AFE’s internal

AGC loop regulates the detecting signal amplitude when

the input level is greater than approximately 20 mVPP.

This signal amplitude is called “AGC-active level”. The

AGC loop regulates the input voltage so that the input

signal amplitude range will be kept within the linear range

of the detection circuits without saturation. The AGC

Active Status bit AGCACT<5>, in the AFE Status

Register 7 (Register 11-8) is set if the AGC loop

regulates the input voltage.

00

XX

Filter Disabled

Note 1: Typical at room temperature and

VDD = 3.0V, 32 kHz oscillator.

TOEH is measured from the rising edge of the demodulator

output to the first falling edge. The pulse width must fall

within TOEH ≤ t ≤ TOET.

TOEL is measured from the falling edge of the

demodulator output to the rising edge of the next pulse.

The pulse width must fall within TOEL ≤ t ≤ TOET.

Table 11-2 shows the input sensitivity comparison when

the AGCSIG option is used. When AGCSIG option bit is

set, the demodulated output is available only when the

AGC loop is active (see Table 11-1). The AFE has also

input sensitivity reduction options per each channel. The

Configuration Register 3 (Register 11-4), Configuration

Register 4 (Register 11-5) and Configuration Register 5

(Register 11-6) have the option to reduce the channel

gains from 0 dB to approximately -30 dB.

TOET is measured from rising edge to the next rising

edge (i.e., the sum of TOEH and TOEL). The pulse width

must be t ≤ TOET. If the Configuration Register 0

(Register 11-1), OEL<8:7> is set to ‘00’, then TOEH

must not exceed TOET and TOEL must not exceed

TINACT.

The filter will reset, requiring a complete new successive

high and low period to enable LFDATA, under the

following conditions.

• The received high is not greater than the

configured minimum TOEH value.

• During TOEH, a loss of signal > 56 μs. A loss of

signal < 56 μs may or may not cause a filter

Reset.

• The received low is not greater than the

configured minimum TOEL value.

• The received sequence exceeds the maximum

TOET value:

- TOEH + TOEL > TOET

- or TOEH > TOET

- or TOEL > TOET

• A Soft Reset SPI command is received.

DS41232D-page 105

PIC12F635/PIC16F636/639

TABLE 11-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)

Input

Sensitivity

(Typical)

AGCSIG<7>

(Config. Register 5)

Description

0

Disabled – the AFE passes signal of any amplitude level it is capable of

detecting (demodulated data and carrier clock).

3.0 mVPP

1

Enabled – No output until AGC Status = 1(i.e., VPEAK ≈ 20 mVPP)

(demodulated data and carrier clock).

20 mVPP

• Provides the best signal to noise ratio.

11.17 Input Channels (Enable/Disable)

11.19 AGC Preserve

Each channel can be individually enabled or disabled

by programming bits in Configuration Register 0<3:1>

(Register 11-1).

The AGC preserve feature allows the AFE to preserve

the AGC value during the AGC settling time (TAGC) and

apply the value to the data slicing circuit for the following

data streams instead of using a new tracking value. This

feature is useful to demodulate the input signal correctly

when the input has random amplitude variations at a

given time period. This feature is enabled when the AFE

receives an AGC Preserve On command and disabled

if it receives an AGC Preserve Off command. Once the

AGC Preserve On command is received, the AFE

acquires a new AGC value during each AGC settling

time and preserves the value until a Soft Reset or an

AGC Preserve Off command is issued. Therefore, it

does not need to issue another AGC Preserve On

command. An AGC Preserve Off command is needed to

The purpose of having an option to disable a particular

channel is to minimize current draw by powering down

as much circuitry as possible, if the channel is not

needed for operation. The exact circuits disabled when

an input is disabled are amplifiers, detector, full-wave

rectifier, data slicer, and modulation FET. However, the

RF input limiter remains active to protect the silicon

from excessive antenna input voltages.

11.18 AGC Amplifier

The circuit automatically amplifies input signal voltage

levels to an acceptable level for the data slicer. Fast

attack and slow release by nature, the AGC tracks the

carrier signal level and not the modulated data bits.

disable

Section 11.32.2.5 “AGC Preserve On Command”

and Section 11.32.2.6 “AGC Preserve Off

Command” for AGC Preserve commands).

the

AGC

preserve

feature

(see

The AGC inherently tracks the strongest of the three

antenna input signals. The AGC requires an AGC

stabilization time (TAGC).

The AGC will attempt to regulate a channel’s peak

signal voltage into the data slicer to a desired regulated

AGC voltage – reducing the input path’s gain as the

signal level attempts to increase above regulated AGC

voltage, and allowing full amplification on signal levels

below the regulated AGC voltage.

The AGC has two modes of operation:

1. During the AGC settling time (TAGC), the AGC

time constant is fast, allowing a reasonably short

acquisition time of the continuous input signal.

2. After TAGC, the AGC switches to a slower time

constant for data slicing.

Also, the AGC is frozen when the input signal envelope

is low. The AGC tracks only high envelope levels.

DS41232D-page 106

PIC12F635/PIC16F636/639

TABLE 11-3: SETTING FOR MINIMUM

MODULATION DEPTH

11.20 Soft Reset

The AFE issues a Soft Reset in the following events:

REQUIREMENT

MODMIN Bits

(Config. Register 5)

a) After Power-on Reset (POR),

b) After Inactivity timer time-out,

c) If an “Abort” occurs,

Modulation Depth

Bit 6

Bit 5

d) After receiving SPI Soft Reset command.

0

1

0

1

0

1

50% (default)

75%

The “Abort” occurs if there is no positive signal

detected at the end of the AGC stabilization period

(TAGC). The Soft Reset initializes internal circuits and

brings the AFE into a low current Standby mode

operation. The internal circuits that are initialized by the

Soft Reset include:

25%

12%

• Output Enable Filter

• AGC circuits

• Demodulator

• 32 kHz Internal Oscillator

The Soft Reset has no effect on the Configuration register

setup, except for some of the AFE Status Register 7 bits.

(Register 11-8).

The circuit initialization takes one internal clock cycle

(1/32 kHz = 31.25 μs). During the initialization, the

modulation transistors between each input and

LCCOM pins are turned-on to discharge any inter-

nal/external parasitic charges. The modulation transis-

tors are turned-off immediately after the initialization

time.

The Soft Reset is executed in Active mode only. It is not

valid in Standby mode.

11.21 Minimum Modulation Depth

Requirement for Input Signal

The AFE demodulates the modulated input signal if the

modulation depth of the input signal is greater than the

minimum requirement that is programmed in the AFE

Configuration Register 5 (Register 11-6). Figure 11-7

shows the definition of the modulation depth and

examples. MODMIN<6:5> of the Configuration Register

5 offer four options. They are 75%, 50%, 25% and 12%,

with a default setting of 50%.

The purpose of this feature is to enhance the

demodulation integrity of the input signal. The 12%

setting is the best choice for the input signal with weak

modulation depth, which is typically observed near the

high-voltage base station antenna and also at

far-distance from the base station antenna. It gives the

best demodulation sensitivity, but is very susceptible to

noise spikes that can result in a bit detection error. The

75% setting can reduce the bit errors caused by noise,

but gives the least demodulation sensitivity. See

Table 11-3 for minimum modulation depth requirement

settings.

DS41232D-page 107

PIC12F635/PIC16F636/639

FIGURE 11-7:

MODULATION DEPTH EXAMPLES

(a) Modulation Depth Definition

Amplitude

A - B

A

X 100%

Modulation Depth (%) =

B

A

t

(b) LFDATA Output vs. Input vs. Minimum Modulation Depth Setting

Amplitude

10 mVPP

Coil Input Strength

7 mVPP

10 - 7

10

X 100% = 30%

Modulation Depth (%) =

t

Input signal with modulation depth = 30%

Demodulated LFDATA Output when MODMIN Setting = 25%

(LFDATA output = toggled)

t

Amplitude

Demodulated LFDATA Output if MODMIN Setting = 50%

(LFDATA output = not toggled)

t

0

DS41232D-page 108

PIC12F635/PIC16F636/639

11.22 Low-Current Sleep Mode

11.25 Error Detection of AFE

Configuration Register Data

The Sleep command from the microcontroller, via an

SPI Interface command, places the AFE into an ultra

Low-current mode. All circuits including the RF Limiter,

except the minimum circuitry required to retain register

memory and SPI capability, will be powered down to

minimize the AFE current draw. Power-on Reset or any

SPI command, other than Sleep command, is required

to wake the AFE from Sleep.

The AFE’s Configuration registers are volatile memory.

Therefore, the contents of the registers can be

corrupted or cleared by any electrical incidence such

as battery disconnect. To ensure the data integrity, the

AFE has an error detection mechanism using row and

column parity bits of the Configuration register memory

map. The bit 0 of each register is a row parity bit which

is calculated over the eight Configuration bits (from bit

1 to bit 8). The Column Parity Register (Configuration

Register 6) holds column parity bits; each bit is

calculated over the respective columns (Configuration

registers 0 to 5) of the Configuration bits. The STATUS

register is not included for the column parity bit

calculation. Parity is to be odd. The parity bit set or

cleared makes an odd number of set bits. The user

needs to calculate the row and column parity bits using

the contents of the registers and program them. During

operation, the AFE continuously calculates the row and

column parity bits of the configuration memory map. If

a parity error occurs, the AFE lowers the SCLK/ALERT

pin (interrupting the microcontroller section) indicating

the configuration memory has been corrupted or

unloaded and needs to be reprogrammed.

11.23 Low-Current Standby Mode

The AFE is in Standby mode when no LF signal is

present on the antenna inputs but the AFE is powered

and ready to receive any incoming signals.

11.24 Low-Current Operating Mode

The AFE is in Low-current Operating mode when a LF

signal is present on an LF antenna input and internal

circuitry is switching with the received data.

At an initial condition after a Power-On-Reset, the

values of the registers are all clear (default condition).

Therefore, the AFE will issue the parity bit error by

lowering the SCLK/ALERT pin. If user reprograms the

registers with correct parity bits, the SCLK/ALERT pin

will be toggled to logic high level immediately.

The parity bit errors do not change or affect the AFE’s

functional operation.

Table 11-4 shows an example of the register values

and corresponding parity bits.

TABLE 11-4: AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE

Bit 0

(Row Parity)

Register Name

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3 Bit 2

Bit 1

Configuration Register 0

Configuration Register 1

Configuration Register 2

Configuration Register 3

Configuration Register 4

Configuration Register 5

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Configuration Register 6

(Column Parity Register)

DS41232D-page 109

PIC12F635/PIC16F636/639

11.26 Factory Calibration

11.28 Battery Back-up and Batteryless

Operation

Microchip calibrates the AFE to reduce the

device-to-device variation in standby current, internal

timing and sensitivity, as well as channel-to-channel

sensitivity variation.

The device supports both battery back-up and

batteryless operation by the addition of external

components, allowing the device to be partially or

completely powered from the field.

11.27 De-Q’ing of Antenna Circuit

Figure 11-8 shows an example of the external circuit for

the battery back-up.

When the transponder is close to the base station, the

transponder coil may develop coil voltage higher than

VDE_Q. This condition is called “near field”. The AFE

detects the strong near field signal through the AGC

control, and de-Q’ing the antenna circuit to reduce the

input signal amplitude.

Note:

Voltage on LCCOM combined with coil input

voltage must not exceed the maximum LC

input voltage.

FIGURE 11-8:

LF FIELD POWERING AND BATTERY BACK-UP EXAMPLE

VBAT

VDD

LCX

LCY

LCZ

RLIM

DFLAT1

DBLOCK

CPOOL

LX

DLIM

CX

LY

Air Coil

CY

LZ

CZ

LCCOM

DFLAT2

CCOM

RCOM

Legend: CCOM = LCCOM charging capacitor.

CPOOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device.

DBLOCK = Battery protection from reverse charge.

Schottky for low forward bias drop.

DFLAT = Field rectifier diodes.

DLIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields.

RCOM = CCOM discharge path.

RLIM = Current limiting resistor, required for air coil in strong fields.

DS41232D-page 110

PIC12F635/PIC16F636/639

11.29 Demodulator

The demodulator recovers the modulation data from

the received signal, containing carrier plus data, by

appropriate envelope detection. The demodulator has

a fast rise (charge) time (TDR) and a fall time (TDF)

appropriate to an envelope of input signal (see

Section 15.0 “Electrical Specifications” for TDR

and TDF specifications). The demodulator contains

the full-wave rectifier, low-pass filter, peak detector

and data slicer.

FIGURE 11-9:

DEMODULATOR CHARGE AND DISCHARGE

Signal into LC input pins

Full-wave Rectifier output

Data Slicer output

(demodulator output)

TDR

TDF

For a clean data output or to save operating power, the

input channels can be individually enabled or disabled. If

more than one channel is enabled, the output is the sum

of each output of all enabled channels. There will be no

valid output if all three channels are disabled. When the

demodulated output is selected, the output is available in

two different conditions depending on how the options of

Configuration Register 0 (Register 11-1) are set: Output

Enable Filter is disabled or enabled.

11.30 Power-On Reset

This circuit remains in a Reset state until a sufficient

supply voltage is applied to the AFE. The Reset

releases when the supply is sufficient for correct AFE

operation, nominally VPOR of AFE.

The Configuration registers are all cleared on a

Power-on Reset. As the Configuration registers are

protected by odd row and column parity, the ALERT pin

will be pulled down – indicating to the microcontroller

section that the AFE configuration memory is cleared

and requires loading.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2),

DATOUT <8:7>:

- bit 8 bit 7

11.31 LFDATA Output Selection

0

1

0

0: Demodulator Output

1: Carrier Clock Output

0: RSSI Output

The LFDATA output can be configured to pass the

Demodulator output, Received Signal Strength Indicator

(RSSI) output, or Carrier Clock. See Configuration

Register 1 (Register 11-2) for more details.

1: RSSI Output

• Configuration Register 0 (Register 11-1): all bits

11.31.1 DEMODULATOR OUTPUT

The demodulator output is the default configuration of

the output selection. This is the output of an envelope

detection circuit. See Figure 11-9 for the demodulator

output.

DS41232D-page 111

PIC12F635/PIC16F636/639

Case I. When Output Enable Filter is disabled: Demodulated output is available immediately after the AGC stabilization

time (TAGC). Figure 11-10 shows an example of demodulated output when the Output Enable Filter is disabled.

FIGURE 11-10:

INPUT SIGNAL AND DEMODULATOR OUTPUT WHEN THE OUTPUT ENABLE

FILTER IS DISABLED

Input Signal

LFDATA Output

Case II. When Output Enable Filter is enabled: Demodulated output is available only if the incoming signal meets the

enable filter timing criteria that is defined in the Configuration Register 0 (Register 11-1). If the criteria is met, the output

is available after the low timing (TOEL) of the Enable Filter. Figure 11-11 and Figure 11-12 shows examples of

demodulated output when the Output Enable Filter is enabled.

DS41232D-page 112

PIC12F635/PIC16F636/639

FIGURE 11-11:

INPUT SIGNAL AND DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE

FILTER IS ENABLED AND INPUT MEETS FILTER TIMING REQUIREMENTS)

Input Signal

LFDATA Output

FIGURE 11-12:

NO DEMODULATOR OUTPUT (WHEN OUTPUT ENABLE FILTER IS ENABLED

BUT INPUT DOES NOT MEET FILTER TIMING REQUIREMENTS)

Input Signal

No LFDATA Output

DS41232D-page 113

PIC12F635/PIC16F636/639

11.31.2 CARRIER CLOCK OUTPUT

When the Carrier Clock output is selected, the LFDATA

output is a square pulse of the input carrier clock and

available as soon as the AGC stabilization time (TAGC) is

completed. There are two Configuration register options

for the carrier clock output: (a) clock divide-by one or (b)

clock divide-by four, depending on bit DATOUT<7> of

Configuration Register 2 (Register 11-3). The carrier

clock output is available immediately after the AGC

settling time. The Output Enable Filter, AGCSIG, and

MODMIN options are applicable for the carrier clock

output in the same way as the demodulated output. The

input channel can be individually enabled or disabled for

the output. If more than one channel is enabled, the

output is the sum of each output of all enabled channels.

Therefore, the carrier clock output waveform is not as

precise as when only one channel is enabled. It is

recommended to enable one channel only if a precise

output waveform is desired.

There will be no valid output if all three channels are

disabled. See Figure 11-13 for carrier clock output

examples.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2),

DATOUT <8:7>:

bit 8 bit 7

0

1

0: Demodulator Output

1: Carrier Clock Output

0: RSSI Output

1: RSSI Output

• Configuration Register 2 (Register 11-3),

CLKDIV<7>:

0: Carrier Clock/1

1: Carrier Clock/4

• Configuration Register 0 (Register 11-1): all bits

are affected

• Configuration Register 5 (Register 11-6)

DS41232D-page 114

PIC12F635/PIC16F636/639

FIGURE 11-13:

CARRIER CLOCK OUTPUT EXAMPLES

(A) CARRIER CLOCK OUTPUT WITH CARRIER/1 OPTION

Carrier Clock Output

Carrier Input

(B) CARRIER CLOCK OUTPUT WITH CARRIER/4 OPTION

Carrier Clock Output

Carrier Input

DS41232D-page 115

PIC12F635/PIC16F636/639

11.31.3 RECEIVED SIGNAL STRENGTH

INDICATOR (RSSI) OUTPUT

FIGURE 11-14:

RSSI OUTPUT PATH

An analog current is available at the LFDATA pin when

the Received Signal Strength Indicator (RSSI) output is

selected for the AFE’s Configuration register. The analog

current is linearly proportional to the input signal strength

(see Figure 11-15).

RSSI Output Current

Generator

Current Output

VDD

Off

All timers in the circuit, such as inactivity timer, alarm

timer, and AGC settling time, are disabled during the

RSSI mode. Therefore, the RSSI output is not affected

by the AGC settling time, and available immediately

when the RSSI option is selected. The AFE enters

Active mode immediately when the RSSI output is

selected. The MCU I/O pin (RC3) connected to the

LFDATA pin, must be set to high-impedance state

during the RSSI Output mode.

if RSSI active

RC3/LFDATA/RSSI/CCLK Pin

RSSIFET

When the AFE receives an SPI command during the

RSSI output, the RSSI mode is temporary disabled

until the SPI interface communication is completed. It

returns to the RSSI mode again after the SPI interface

communication is completed. The AFE holds the RSSI

mode until another output type is selected (CS low

turns off the RSSI signal). To obtain the RSSI output

for a particular input channel, or to save operating

power, the input channel can be individually enabled

or disabled. If more than one channel is enabled, the

RSSI output is from the strongest signal channel.

There will be no valid output if all three channels are

disabled.

RSSI Pull-down MOSFET

(controlled by Config. 2, bit 8)

Related AFE Configuration register bits:

• Configuration Register 1 (Register 11-2),

DATOUT<8:7>:

bit 8 bit 7

0

1

0: Demodulated Output

1: Carrier Clock Output

0: RSSI Output

1: RSSI Output

• Configuration Register 2 (Register 11-3),

RSSIFET<8>:

0: Pull-Down MOSFET off

1: Pull-Down MOSFET on.

Note:

The pull-down MOSFET option is valid

only when the RSSI output is selected.

The MOSFET is not controllable by users

when Demodulated or Carrier Clock

output option is selected.

• Configuration Register 0 (Register 11-1): all bits

are affected.

DS41232D-page 116

PIC12F635/PIC16F636/639

FIGURE 11-15:

RSSI OUTPUT CURRENT VS. INPUT SIGNAL LEVEL EXAMPLE

90

80

70

60

50

40

30

20

10

0

1

2

3

4

5

6

7

8

9

10

Input Voltage (VPP)

DS41232D-page 117

PIC12F635/PIC16F636/639

11.31.3.1 ANALOG-TO-DIGITAL DATA

CONVERSION OF RSSI SIGNAL

11.32 AFE Configuration

11.32.1 SPI COMMUNICATION

The AFE’s RSSI output is an analog current. It needs an

external Analog-to-Digital (ADC) data conversion device

for digitized output. The ADC data conversion can be

accomplished by using a stand-alone external ADC

device or by firmware utilizing MCU’s internal

comparator along with a few external resistors and a

capacitor. For slope ADC implementations, the external

capacitor at the LFDATA pad needs to be discharged

before data sampling. For this purpose, the internal

pull-down MOSFET on the LFDATA pad can be utilized.

The MOSFET can be turned on or off with bit

The AFE SPI interface communication is used to read

or write the AFE’s Configuration registers and to send

command only messages. For the SPI interface, the

device has three pads; CS, SCLK/ALERT, and

LFDATA/RSSI/CCLK/SDIO.

Figure 11-15,

Figure 11-14, Figure 11-16 and Figure 11-17 shows

examples of the SPI communication sequences.

When the device powers up, these pins will be

high-impedance inputs until firmware modifies them

appropriately. The AFE pins connected to the MCU

pins will be as follows.

RSSIFET<8> of the Configuration Register

2

(Register 11-3). When it is turned on, the internal

MOSFET provides a discharge path for the external

capacitor. This MOSFET option is valid only if RSSI

output is selected and not controllable by users for

demodulated or carrier clock output options.

CS

• Pin is permanently an input with an internal pull-up.

SCLK/ALERT

• Pin is an open collector output when CS is high.

An internal pull-up resistor exists internal to the

AFE to ensure no spurious SPI communication

between powering and the MCU configuring its

pins. This pin becomes the SPI clock input when

CS is low.

See separate application notes for various external ADC

implementation methods for this device.

LFDATA/RSSI/CCLK/SDIO

• Pin is a digital output (LFDATA) so long as CS is

high. During SPI communication, the pin is the

SPI data input (SDI) unless performing a register

Read, where it will be the SPI data output (SDO).

FIGURE 11-16:

POWER-UP SEQUENCE

CS

SCLK/ALERT

ALERT

(open collector

output)

LFDATA/RSSI/

CCLK/SDIO

LFDATA

(output)

DS41232D-page 118

PIC12F635/PIC16F636/639

FIGURE 11-17:

SPI WRITE SEQUENCE

TCSH

2

6

CS

TCSSC

TSCCS TCS1

TCS0

16 Clocks for Write Command, Address and Data

4

THI

TLO

7

SCLK/

ALERT

MSb

THD

LSb

SCLK

(input)

ALERT

(output)

1/FSCLK

ALERT

(output)

1

TSU

LFDATA/RSSI/

CCLK/SDIO

LFDATA

(output)

SDI

(input)

LFDATA

(output)

5

3

MCU SPI Write Details:

1.

Drive the AFE’s open collector ALERT output low.

To ensure no false clocks occur when CS drops.

Drop CS.

•

2.

•

AFE SCLK/ALERT becomes SCLK input.

LFDATA/RSSI/CCLK/SDIO becomes SDI input.

3.

4.

Change LFDATA/RSSI/CCLK/SDIO connected pin to output.

Driving SPI data.

Clock in 16-bit SPI Write sequence - command, address, data and parity bit.

Command, address, data and parity bit.

•

5.

6.

7.

Change LFDATA/RSSI/CCLK/SDIO connected pin to input.

Raise CS to complete the SPI Write.

Change SCLK/ALERT back to input.

DS41232D-page 119

PIC12F635/PIC16F636/639

FIGURE 11-18:

SPI READ SEQUENCE

TCSH

9

6

7

2

CS

10

4

8

16 Clocks for Read Result

16 Clocks for Read Command,

Address and Dummy Data

TCS

0

TCSSC

TSCCS

_CSSCTCS1

TCSSC

TCS1

T

TCS0

T

HI

TLO

SCLK/ALERT

MSb

LSb

SCLK

(input)

SCLK

(input)

ALERT

(output)

ALERT

(output)

ALERT

(output)

1/FSCLK

1

TSU THD

T

DO

LFDATA/RSSI/

CCLK/SDIO

3

LFDATA

(output)

SDO

(output)

LFDATA

(output)

SDI

(input)

LFDATA

(output)

5

MCU SPI Read Details:

7.

8.

Drop CS.

1.

2.

Drive the AFE’s open collector ALERT output low.

To ensure no false clocks occur when CS drops.

Drop CS

•

AFE SCLK/ALERT becomes SCLK input.

LFDATA/RSSI/CCLK/SDIO becomes SDO output.

•

Clock out 16-bit SPI Read result.

•

AFE SCLK/ALERT becomes SCLK input.

LFDATA/RSSI/CCLK/SDIO becomes SDI input.

•

First seven bits clocked-out are dummy bits.

Next eight bits are the Configuration register data.

The last bit is the Configuration register row parity bit.

3.

4.

Change LFDATA/RSSI/CCLK/SDIO connected pin to output.

Driving SPI data.

Clock in 16-bit SPI Read sequence.

Command, address and dummy data.

Change LFDATA/RSSI/CCLK/SDIO connected pin to input.

Raise CS to complete the SPI Read entry of command and address.

•

9.

Raise CS to complete the SPI Read.

10. Change SCLK/ALERT back to input.

•

5.

6.

Note:

The TCSH is considered as one clock. Therefore, the

Configuration register data appears at 6th clock after TCSH.

DS41232D-page 120

PIC12F635/PIC16F636/639

The AFE operates in SPI mode 0,0. In mode 0,0 the

clock idles in the low state (Figure 11-19). SDI data is

loaded into the AFE on the rising edge of SCLK and

SDO data is clocked out on the falling edge of SCLK.

There must be multiples of 16 clocks (SCLK) while CS

is low or commands will abort.

11.32.2 COMMAND

DECODER/CONTROLLER

The circuit executes 8 SPI commands from the MCU.

The command structure is:

Command (3 bits) + Configuration Address (4 bits) +

Data Byte and Row Parity Bit received by the AFE Most

Significant bit first. Table 11-5 shows the available SPI

commands.

TABLE 11-5: SPI COMMANDS (AFE)

Row

Command Address

Data

Description

Parity

Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.

000

001

010

011

100

101

XXXX

XXXX XXXX

X

Clamp on – enable modulation circuit

Clamp off – disable modulation circuit

Enter Sleep mode (any other command wakes the AFE)

AGC Preserve On – to temporarily preserve the current AGC level

AGC Preserve Off – AGC again tracks strongest input signal

Soft Reset – resets various circuit blocks

Read Command – Data will be read from the specified register address.

110

0000

0001

0010

0011

0100

0101

0110

0111

Config Byte 0

Config Byte 1

Config Byte 2

Config Byte 3

Config Byte 4

Config Byte 5

Column Parity

AFE Status

P

X

General – options that may change during normal operation

LCX antenna tuning and LFDATA output format

LCY antenna tuning

LCZ antenna tuning

LCX and LCY sensitivity reduction

LCZ sensitivity reduction and modulation depth

Column parity byte for Config Byte 0 -> Config Byte 5

AFE status – parity error, which input is active, etc.

Write Command – Data will be written to the specified register address.

111

0000

0001

0010

0011

0100

0101

0110

0111

Config Byte 0

Config Byte 1

Config Byte 2

Config Byte 3

Config Byte 4

Config Byte 5

Column Parity

Not Used

P

X

General – options that may change during normal operation

LCX antenna tuning and LFDATA output format

LCY antenna tuning

LCZ antenna tuning

LCX and LCY sensitivity reduction

LCZ sensitivity reduction and modulation depth

Column parity byte for Config Byte 0 -> Config Byte 5

Register is readable, but not writable

Note:

‘P’ denotes the row parity bit (odd parity) for the respective data byte.

DS41232D-page 121

PIC12F635/PIC16F636/639

FIGURE 11-19:

CS

DETAILED SPI INTERFACE TIMING (AFE)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

SCLK

SDIO

MSb

LSb

Data Byte

Row

Parity Bit

Command

Address

11.32.2.1 Clamp On Command

11.32.2.5 AGC Preserve On Command

This command results in activating (turning on) the

modulation transistors of all enabled channels; channels

enabled in Configuration Register 0 (Register 11-1).

This command results in preserving the AGC level

during each AGC settling time and apply the value to

the data slicing circuit for the following data stream. The

preserved AGC value is reset by a Soft Reset, and a

new AGC value is acquired and preserved when it

starts a new AGC settling time. This feature is disabled

by an AGC Preserve Off command (see Section 11.19

“AGC Preserve”).

11.32.2.2 Clamp Off Command

This command results in de-activating (turning off) the

modulation transistors of all channels.

11.32.2.3 Sleep Command

11.32.2.6 AGC Preserve Off Command

This command places the AFE in Sleep mode –

minimizing current draw by disabling all but the

essential circuitry. Any other command wakes the AFE

(example: Clamp Off command).

This command disables the AGC preserve feature and

returns the AFE to the normal AGC tracking mode, fast

tracking during AGC settling time and slow tracking

after that (see Section 11.19 “AGC Preserve”).

11.32.2.4 Soft Reset Command

11.32.3 CONFIGURATION REGISTERS

The AFE issues a Soft Reset when it receives an

external Soft Reset command. The external Soft Reset

command is typically used to end a SPI communication

sequence or to initialize the AFE for the next signal

detection sequence, etc. See Section 11.20 “Soft

Reset” for more details on Soft Reset.

The AFE includes 8 Configuration registers, including a

column parity register and AFE Status Register. All

registers are readable and writable via SPI, except

STATUS register, which is readable only. Bit 0 of each

register is a row parity bit (except for the AFE Status

Register 7) that makes the register contents an odd

number.

If a Soft Reset command is sent during a “Clamp-on”

condition, the AFE still keeps the “Clamp-on” condition

after the Soft Reset execution. The Soft Reset is

executed in Active mode only, not in Standby mode.

The SPI Soft Reset command is ignored if the AFE is

not in Active mode.

DS41232D-page 122

PIC12F635/PIC16F636/639

TABLE 11-6: ANALOG FRONT-END CONFIGURATION REGISTERS SUMMARY

Register Name

Address

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Configuration Register 0

Configuration Register 1

Configuration Register 2

Configuration Register 3

Configuration Register 4

Configuration Register 5

Column Parity Register 6

AFE Status Register 7

0000

0001

0010

0011

0100

0101

0110

0111

OEH

DATOUT

RSSIFET CLKDIV

Unimplemented

Channel X Sensitivity Control

AUTOCHSEL AGCSIG MODMIN MODMIN

Column Parity Bits

AGCACT Wake-up Channel Indicators

OEL

ALRTIND

LCZEN

LCYEN

LCXEN

R0PAR

R1PAR

R2PAR

R3PAR

R4PAR

R5PAR

R6PAR

PEI

Channel X Tuning Capacitor

Channel Y Tuning Capacitor

Channel Z Tuning Capacitor

Channel Y Sensitivity Control

Channel Z Sensitivity Control

Active Channel Indicators

ALARM

REGISTER 11-1: CONFIGURATION REGISTER 0

R/W-0

OEH1

R/W-0

OEH0

R/W-0

OEL1

R/W-0

OEL0

R/W-0

LCZEN

R/W-0

LCXEN

R/W-0

ALRTIND

LCYEN

R0PAR

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8-7

bit 6-5

OEH<1:0>: Output Enable Filter High Time (TOEH) bit

00= Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)

01= 1 ms

10= 2 ms

11= 4 ms

OEL<1:0>: Output Enable Filter Low Time (TOEL) bit

00= 1 ms

01= 1 ms

10= 2 ms

11= 4 ms

bit 4

bit 3

bit 2

bit 1

bit 0

ALRTIND: ALERT bit, output triggered by:

1= Parity error and/or expired Alarm timer (receiving noise, see Section 11.14.3 “Alarm Timer”)

0= Parity error

LCZEN: LCZ Enable bit

1= Disabled

0= Enabled

LCYEN: LCY Enable bit

1= Disabled

0= Enabled

LCXEN: LCX Enable bit

1= Disabled

0= Enabled

R0PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

DS41232D-page 123

PIC12F635/PIC16F636/639

REGISTER 11-2: CONFIGURATION REGISTER 1

R/W-0

DATOUT1 DATOUT0 LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0

bit 8

R1PAR

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8-7

DATOUT<1:0>: LFDATA Output type bit

00= Demodulated output

01= Carrier Clock output

10= RSSI output

11= RSSI output

bit 6-1

bit 0

LCXTUN<5:0>: LCX Tuning Capacitance bit

000000= +0 pF (Default)

:

111111= +63 pF

R1PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set

bits

REGISTER 11-3: CONFIGURATION REGISTER 2

R/W-0

RSSIFET

bit 8

R/W-0

CLKDIV

LCYTUN5 LCYTUN4 LCYTUN3 LCYTUN2 LCYTUN1 LCYTUN0

R2PAR

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)

1= Pull-down RSSI MOSFET on

0= Pull-down RSSI MOSFET off

bit 7

CLKDIV: Carrier Clock Divide-by bit

1= Carrier Clock/4

0= Carrier Clock/1

bit 6-1

LCYTUN<5:0>: LCY Tuning Capacitance bit

000000= +0 pF (Default)

:

111111= +63 pF

bit 0

R2PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set

bits

DS41232D-page 124

PIC12F635/PIC16F636/639

REGISTER 11-4: CONFIGURATION REGISTER 3

U-0

—

U-0

—

R/W-0

LCZTUN5 LCZTUN4 LCZTUN3 LCZTUN2 LCZTUN1 LCZTUN0

R3PAR

bit 8

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8-7

bit 6-1

Unimplemented: Read as ‘0’

LCZTUN<5:0>: LCZ Tuning Capacitance bit

000000= +0 pF (Default)

:

111111= +63 pF

bit 0

R3PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set

bits

REGISTER 11-5: CONFIGURATION REGISTER 4

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0

LCXSEN3 LCXSEN2 LCXSEN1 LCXSEN0 LCYSEN3 LCYSEN2 LCYSEN1 LCYSEN0

bit 8

R4PAR

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8-5

LCXSEN<3:0>⁽¹⁾: Typical LCX Sensitivity Reduction bit

0000= -0 dB (Default)

0001= -2 dB

0010= -4 dB

0011= -6 dB

0100= -8 dB

0101= -10 dB

0110= -12 dB

0111= -14 dB

1000= -16 dB

1001= -18 dB

1010= -20 dB

1011= -22 dB

1100= -24 dB

1101= -26 dB

1110= -28 dB

1111= -30 dB

bit 4-1

bit 0

LCYSEN<3:0>⁽¹⁾: Typical LCY Sensitivity Reduction bit

0000= -0 dB (Default)

:

1111= -30 dB

R4PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set

bits

Note 1: Assured monotonic increment (or decrement) by design.

DS41232D-page 125

PIC12F635/PIC16F636/639

REGISTER 11-6: CONFIGURATION REGISTER 5

R/W-0

AUTOCHSEL

bit 8

R/W-0

AGCSIG

MODMIN1

MODMIN0

LCZSEN3

LCZSEN2

LCZSEN1

LCZSEN0

R5PAR

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

AUTOCHSEL: Auto Channel Select bit

1= Enabled – AFE selects channel(s) that has demodulator output “high” at the end of TSTAB; or otherwise, blocks the

channel(s).

0= Disabled – AFE follows channel enable/disable bits defined in Register 0

bit 7

AGCSIG: Demodulator Output Enable bit, after the AGC loop is active

1= Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The AGC Active Status bit is set

when the AGC begins regulating.

0= Disabled – the AFE passes signal of any level it is capable of detecting

bit 6-5

MODMIN<1:0>: Minimum Modulation Depth bit

00= 50%

01= 75%

10= 25%

11= 12%

bit 4-1

bit 0

LCZSEN<3:0>⁽¹⁾: LCZ Sensitivity Reduction bit

0000= -0dB (Default)

:

1111= -30dB

R5PAR: Register Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

Note 1: Assured monotonic increment (or decrement) by design.

REGISTER 11-7: COLUMN PARITY REGISTER 6

R/W-0

COLPAR7

COLPAR6

COLPAR5

COLPAR4

COLPAR3

COLPAR2

COLPAR1

COLPAR0

R6PAR

bit 8

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Configuration register row parity bits contain an odd

number of set bits.

COLPAR6: Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR5: Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR4: Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR3: Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR2: Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Configuration Registers 0 through 5 contain

an odd number of set bits.

COLPAR0: Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Configuration Registers 0 through 5 contain an

odd number of set bits.

R6PAR: Register Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

DS41232D-page 126

PIC12F635/PIC16F636/639

REGISTER 11-8: AFE STATUS REGISTER 7

R-0

PEI

CHZACT

CHYACT

CHXACT

AGCACT

WAKEZ

WAKEY

WAKEX

ALARM

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 8

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

CHZACT: Channel Z Active bit (cleared via Soft Reset)

1= Channel Z is passing data after TAGC

0= Channel Z is not passing data after TAGC

(1)

CHYACT: Channel Y Active bit (cleared via Soft Reset)

1= Channel Y is passing data after TAGC

0= Channel Y is not passing data after TAGC

(1)

CHXACT: Channel X Active bit (cleared via Soft Reset)

1= Channel X is passing data after TAGC

0= Channel X is not passing data after TAGC

AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)

1= AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP range.

0= AGC is inactive (Input signal is weak)

WAKEZ: Wake-up Channel Z Indicator Status bit (cleared via Soft Reset)

1= Channel Z caused a AFE wake-up (passed ÷64 clock counter)

0= Channel Z did not cause a AFE wake-up

WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset)

1= Channel Y caused a AFE wake-up (passed ÷64 clock counter)

0= Channel Y did not cause a AFE wake-up

WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)

1= Channel X caused a AFE wake-up (passed ÷64 clock counter)

0= Channel X did not cause a AFE wake-up

ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read “Status Register command”)

1= The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the state of bit 4 of the

Configuration register 0

0= The Alarm timer is not timed out

bit 0

PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred (real time)

1= A parity error has occurred and caused the ALERT output to go low

0= A parity error has not occurred

Note 1:

Bit is high whenever channel is passing data. Bit is low in Standby mode.

See Table 11-7 for the bit conditions of the AFE Status

Register after various SPI commands and the AFE

Power-on Reset.

TABLE 11-7: AFE STATUS REGISTER BIT CONDITION (AFTER POWER-ON RESET AND

VARIOUS SPI COMMANDS)

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PEI

Condition

CHZACT CHYACT CHXACT AGCACT WAKEZ

WAKEY

WAKEX

ALARM

POR

0

u

0

u

0

u

0

u

0

u

0

u

0

u

0

1

u

Read Command

(STATUS Register only)

Sleep Command

u

0

u

0

u

0

u

0

u

0

u

0

u

0

u

(1)

Soft Reset Executed

Legend:

u= unchanged

Note 1: See Section 11.20 “Soft Reset” and Section 11.32.2.4 “Soft Reset Command” for the condition of Soft Reset

execution.

DS41232D-page 127

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 128

PIC12F635/PIC16F636/639

12.1 Configuration Bits

12.0 SPECIAL FEATURES OF THE

CPU

The Configuration Word bits can be programmed (read

as ‘0’), or left unprogrammed (read as ‘1’) to select

The PIC12F635/PIC16F636/639 has a host of features

intended to maximize system reliability, minimize cost

through elimination of external components, provide

power saving features and offer code protection.

various device configurations as shown in Register 12-1.

These bits are mapped in program memory location

2007h.

These features are:

Note:

Address 2007h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC12F6XX/16F6XX

Memory Programming Specification”

(DS41204) for more information.

• Reset

- Power-on Reset (POR)

- Wake-up Reset (WUR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator selection

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming™

The PIC12F635/PIC16F636/639 has two timers that

offer necessary delays on power-up. One is the

Oscillator Start-up Timer (OST), intended to keep the

chip in Reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 64 ms (nominal) on power-up only,

designed to keep the part in Reset while the power

supply stabilizes. There is also circuitry to reset the

device if a brown-out occurs, which can use the

Power-up Timer to provide at least a nominal 64 ms

Reset. With these three functions on-chip, most

applications need no external Reset circuitry.

The Sleep mode is designed to offer a very low-current

Power-down mode. The user can wake-up from Sleep

through:

• External Reset

• Watchdog Timer Wake-up

• An Interrupt

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost while the LP crystal option saves

power. A set of Configuration bits are used to select

various options (see Register 12-1).

DS41232D-page 129

PIC12F635/PIC16F636/639

REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER

—

WURE

FCMEN

WDTE

IESO

BOREN1

FOSC1

BOREN0

bit 8

bit 15

bit 7

CPD

CP

MCLRE

PWRTE

FOSC2

FOSC0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

P = Programmable’

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘1’

WURE: Wake-up Reset Enable bit

1= Standard wake-up and continue enabled

0= Wake-up and Reset enabled

bit 11

bit 10

bit 9-8

FCMEN: Fail-Safe Clock Monitor Enabled bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled

0= Internal External Switchover mode is disabled

(1)

BOREN<1:0>: Brown-out Reset Selection bits

11= BOR enabled, SBOREN bit disabled

10= BOR enabled during operation and disabled in Sleep, SBOREN bit disabled

01= BOR controlled by SBOREN bit of the PCON register

00= BOR and SBOREN bits disabled

(2)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

CPD: Data Code Protection bit

1= Data memory code protection is disabled

0= Data memory code protection is enabled

(3)

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

(4)

MCLRE: MCLR pin function select bit

1= MCLR pin function is MCLR

0= MCLR pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled and can be enabled by SWDTEN bit of the WDTCON register

FOSC<2:0>: Oscillator Selection bits

111= EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin

110= EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin

101= INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN

100= INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN

011= EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN

010= HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

001= XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

000= LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased when the code protection is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

DS41232D-page 130

PIC12F635/PIC16F636/639

They are not affected by a WDT wake-up since this is

viewed as the resumption of normal operation. TO and

12.2 Reset

The PIC12F635/PIC16F636/639 differentiates between

various kinds of Reset:

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 12-3. These bits are

used in software to determine the nature of the Reset.

See Table 12-4 for a full description of Reset states of

all registers.

a) Power-on Reset (POR)

b) Wake-up Reset (WUR)

c) WDT Reset during normal operation

d) WDT Reset during Sleep

e) MCLR Reset during normal operation

f) MCLR Reset during Sleep

g) Brown-out Reset (BOR)

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 12-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 15.0 “Electrical

Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset

FIGURE 12-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Sleep

WURE

External Reset

Sleep

Wake-up Interrupt

RA3 Change

MCLR/VPP pin

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

<1>

BOREN

BOREN<0>

SBOREN

S

R

OST/PWRT

Chip_Reset

OST

10-bit Ripple Counter

Q

OSC1/

CLKI pin

PWRT

11-bit Ripple Counter

LFINTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word register (Register 12-1).

DS41232D-page 131

PIC12F635/PIC16F636/639

12.4.1

POWER-UP TIMER (PWRT)

12.3 Power-on Reset

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.5 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A

Configuration bit, PWRTE, can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Reset is enabled, although it is not required.

The on-chip POR circuit holds the chip in Reset until VDD

has reached a high enough level for proper operation. To

take advantage of the POR, simply connect the MCLR

pin through a resistor to VDD. This will eliminate external

RC components usually needed to create Power-on

Reset. A maximum rise time for VDD is required. See

Section 15.0 “Electrical Specifications” for details. If

the BOR is enabled, the maximum rise time specification

does not apply. The BOR circuitry will keep the device in

Reset until VDD reaches VBOD (see Section 12.6

“Brown-out Reset (BOR)”).

The Power-up Timer delay will vary from chip-to-chip

due to:

Note:

The POR circuit does not produce an

internal Reset when VDD declines. To

re-enable the POR, VDD must reach VSS

for a minimum of 100 μs.

• VDD variation

• Temperature variation

• Process variation

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

See DC parameters for details (Section 15.0

“Electrical Specifications”).

Note:

Voltage spikes below VSS at the MCLR

pin, inducing currents greater than 80 mA,

may cause latch-up. Thus, a series resis-

tor of 50-100 Ω should be used when

applying a “low” level to the MCLR pin,

rather than pulling this pin directly to VSS.

For additional information, refer to the Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

12.4 Wake-up Reset (WUR)

The PIC12F635/PIC16F636/639 has

a

modified

wake-up from Sleep mechanism. When waking from

Sleep, the WUR function resets the device and

releases Reset when VDD reaches an acceptable level.

12.5 MCLR

PIC12F635/PIC16F636/639 has a noise filter in the

MCLR Reset path. The filter will ignore small pulses.

If the WURE bit is enabled (‘0’) in the Configuration

Word register, the device will Wake-up Reset from

Sleep through one of the following events:

It should be noted that a WDT Reset does not drive

MCLR pin low. See Figure 12-2 for the recommended

MCLR circuit.

1. On any event that causes a wake-up event. The

peripheral must be enabled to generate an

interrupt or wake-up, GIE state is ignored.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

cleared, MCLR is internally tied to VDD and an internal

weak pull-up is enabled for the MCLR pin. In-Circuit

Serial Programming is not affected by selecting the

internal MCLR option.

2. When WURE is enabled, RA3 will always

generate an interrupt-on-change signal during

Sleep.

The WUR, POR and BOR bits in the PCON register

and the TO and PD bits in the STATUS register can be

used to determine the cause of device Reset.

To allow WUR upon RA3 change:

1. Enable the WUR function, WURE Configuration

Bit = 0.

2. Enable RA3 as an input, MCLRE Configuration

Bit = 0.

3. Read PORTA to establish the current state of

RA3.

4. Execute SLEEPinstruction.

5. When RA3 changes state, the device will

wake-up and then reset. The WUR bit in PCON

will be cleared to ‘0’.

DS41232D-page 132

PIC12F635/PIC16F636/639

FIGURE 12-2:

RECOMMENDED MCLR

CIRCUIT

VDD

R1

PIC12F635/PIC16F636/639

1 kΩ (or greater)

MCLR

C1

0.1 μF

(optional, not critical)

DS41232D-page 133

PIC12F635/PIC16F636/639

On any Reset (Power-on, Brown-out Reset, Watchdog

12.6 Brown-out Reset (BOR)

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOD (see Figure 12-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional nominal 64 ms.

The BOREN0 and BOREN1 bits in the Configuration

Word register select one of four BOR modes. Two

modes have been added to allow software or hardware

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit of the PCON register enables/disables

the BOR allowing it to be controlled in software. By

selecting BOREN<1:0>, the BOR is automatically

disabled in Sleep to conserve power and enabled on

wake-up. In this mode, the SBOREN bit is disabled. See

Register 12-1 for the Configuration Word definition.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

register.

If VDD drops below VBOD while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOD, the Power-up Timer will execute a

64 ms Reset.

If VDD falls below VBOD for greater than parameter

(TBOD) (see Section 15.0 “Electrical Specifications”),

the Brown-out situation will reset the device. This will

occur regardless of VDD slew rate. A Reset is not

ensured to occur if VDD falls below VBOD for less than

parameter (TBOD).

FIGURE 12-3:

BROWN-OUT RESET SITUATIONS

VDD

VBOD

Internal

Reset

(1)

64 ms

VDD

VBOD

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOD

Internal

Reset

(1)

64 ms

Note 1: Nominal 64 ms delay only if PWRTE bit is programmed to ‘0’.

DS41232D-page 134

PIC12F635/PIC16F636/639

12.7 Time-out Sequence

12.8 Power Control (PCON) Register

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired, then

OST is activated after the PWRT time-out has expired.

The total time-out will vary based on oscillator

Configuration and PWRTE bit status. For example, in

EC mode with PWRTE bit erased (PWRT disabled),

there will be no time-out at all. Figure 12-4, Figure 12-5

and Figure 12-6 depict time-out sequences. The device

can execute code from the INTOSC, while OST is active,

by enabling Two-Speed Start-up or Fail-Safe Clock

Monitor (See Section 3.7.2 “Two-Speed Start-up

Sequence” and Section 3.8 “Fail-Safe Clock

Monitor”).

The Power Control register, PCON (address 8Eh), has

two Status bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00 in the Configuration Word

register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 12-5). This is useful for testing purposes or

to

synchronize

more

than

one

For more information, see Section 4.2.3 “Ultra

Low-Power Wake-up” and Section 12.6 “Brown-out

Reset (BOR)”.

PIC12F635/PIC16F636/639 device operating in parallel.

Table 12-5 shows the Reset conditions for some

special registers, while Table 12-4 shows the Reset

conditions for all the registers.

TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up

Oscillator

Brown-out Reset

Wake-up

Configuration

from Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

XT, HS, LP

TPWRT + 1024 • TOSC

TPWRT

1024 • TOSC

—

TPWRT + 1024 • TOSC

TPWRT

1024 • TOSC

—

1024 • TOSC

—

RC, EC, INTOSC

TABLE 12-2: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Value on

all other

Resets⁽¹⁾

Value on

POR, BOR

Name

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CONFIG⁽²⁾BOREN1 BOREN0

CPD

—

CP

—

MCLRE

PWRTE

WDTE FOSC2 FOSC1 FOSC0

—

PCON

ULPWUE SBOREN

RP0 TO

WUR

PD

—

Z

POR

DC

BOR

C

--01 --qq

0001 1xxx

--0u --uu

000q quuu

STATUS

IRP

RP1

Legend:

Note 1:

2:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are not used by BOR.

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

See Configuration Word register (Register 12-1) for operation of all register bits.

TABLE 12-3: PCON BITS AND THEIR SIGNIFICANCE

POR

BOR

WUR

TO

PD

Condition

0

u

x

0

u

0

x

u

0

u

1

0

u

1

u

0

u

0

1

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during Sleep

Wake-up Reset during Sleep

Brown-out Reset during Sleep

Legend: u= unchanged, x= unknown

DS41232D-page 135

PIC12F635/PIC16F636/639

FIGURE 12-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 12-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 12-6:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

DS41232D-page 136

PIC12F635/PIC16F636/639

TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS

MCLR Reset

Wake-up from Sleep

through Interrupt

Wake-up from Sleep

through WDT Time-out

Power-on

Reset

Wake-up Reset

WDT Reset

Brown-out Reset⁽¹⁾

Wake-up Reset

Register

Address

W

—

00h/80h

01h

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--xx xx00

---0 0000

0000 000x

0000 00-0

xxxx xxxx

0000 0000

---0 1000

0000 0000

---- --10

1111 1111

--11 1111

0000 00-0

--01 q-qq

-110 q000

---0 0000

--11 -111

--00 0000

--11 -111

0-0- 0000

0000 0000

---- x000

---- ----

xxxx xxxx

-000 ----

--00 -000

00-- --00

uuuu uuuu

xxxx xxxx

uuuu uuuu

0000 0000

000q quuu⁽⁴⁾

uuuu uuuu

--00 0000

---0 0000

0000 000x

0000 00-0

uuuu uuuu

---0 1000

0000 0000

---- --10

1111 1111

--11 1111

0000 00-0

--0u u-uu^(1,5)

-110 q000

---u uuuu

--11 -111

--00 0000

--11 -111

0-0- 0000

0000 0000

---- q000

---- ----

uuuu uuuu

-000 ----

--00 -000

00-- --00

uuuu uuuu

PC + 1⁽³⁾

INDF

TMR0

PCL

02h/82h

03h/83h

04h/84h

05h

STATUS

FSR

uuuq quuu⁽⁴⁾

uuuu uuuu

--uu uu00

---u uuuu

uuuu uuuu⁽²⁾

uuuu uu-u⁽²⁾

uuuu uuuu

-uuu uuuu

---u uuuu

uuuu uuuu

---- --uu

uuuu uuuu

--uu 1uuu

uuuu uu-u

--0u u-uu

-uuu uuuu

---u uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

u-u- uuuu

uuuu uuuu

---- uuuu

---- ----

uuuu uuuu

-uuu ----

--uu -uuu

uu-- --uu

PORTA

PORTC⁽⁶⁾

PCLATH

INTCON

PIR1

07h

0Ah/8Ah

0Bh/8Bh

0Ch

TMR1L

TMR1H

T1CON

WDTCON

CMCON0

CMCON1

OPTION_REG

TRISA

0Eh

0Fh

10h

18h

19h

1Ah

81h

85h

TRISC⁽⁶⁾

87h

PIE1

8Ch

PCON

8Eh

OSCCON

OSCTUNE

WPUDA

IOCA

8Fh

90h

95h

96h

WDA

97h

VRCON

EEDAT

EEADR

EECON1

EECON2

ADRESL

ADCON1

LVDCON

CRCON

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

94h

110h

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

4: See Table 12-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: PIC16F636/639 only.

DS41232D-page 137

PIC12F635/PIC16F636/639

TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

Status

Register

PCON

Register

Condition

Power-on Reset

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

0001 1xxx

--01 --0x

--0u --uu

--uu --uu

--01 --10

--uu --uu

--01 --0x

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

000h

WDT Wake-up

PC + 1

000h

PC + 1⁽¹⁾

Brown-out Reset

Interrupt Wake-up from Sleep

Wake-up Reset

000h

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and the Global Interrupt Enable bit, GIE, is set, the PC is loaded

with the interrupt vector (0004h) after execution of PC + 1.

DS41232D-page 138

PIC12F635/PIC16F636/639

For external interrupt events, such as the INT pin or

PORTA change interrupt, the interrupt latency will be

12.9 Interrupts

The PIC12F635/PIC16F636/639 has multiple interrupt

sources:

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 12-8). The latency is the same for one or

two-cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

• External Interrupt RA2/INT

• Timer0 Overflow Interrupt

• PORTA Change Interrupts

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

The Interrupt Control register (INTCON) and Peripheral

Interrupt Request Register 1 (PIR1) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

A Global Interrupt Enable bit GIE of the INTCON regis-

ter enables (if set) all unmasked interrupts, or disables

(if cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in the

INTCON register and PIE1 register. GIE is cleared on

Reset.

For additional information on Timer1, comparators or

data EEPROM modules, refer to the respective

peripheral section.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

12.9.1

RA2/INT INTERRUPT

The following interrupt flags are contained in the

INTCON register:

External interrupt on RA2/INT pin is edge-triggered;

either rising if the INTEDG bit of the OPTION register is

set, or falling if the INTEDG bit is clear. When a valid

edge appears on the RA2/INT pin, the INTF bit of the

INTCON register is set. This interrupt can be disabled

by clearing the INTE control bit of the INTCON register.

The INTF bit must be cleared in software in the Interrupt

Service Routine before re-enabling this interrupt. The

RA2/INT interrupt can wake-up the processor from

Sleep if the INTE bit was set prior to going into Sleep.

The status of the GIE bit decides whether or not the

processor branches to the interrupt vector following

wake-up (0004h). See Section 12.12 “Power-Down

Mode (Sleep)” for details on Sleep and Figure 12-10 for

timing of wake-up from Sleep through RA2/INT interrupt.

• INT Pin Interrupt

• PORTA Change Interrupt

• TMR0 Overflow Interrupt

The peripheral interrupt flags are contained in the

special register, PIR1. The corresponding interrupt

enable bit is contained in special register, PIE1.

The following interrupt flags are contained in the PIR1

register:

• EEPROM Data Write Interrupt

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• Fail-Safe Clock Monitor Interrupt

Note:

The CMCON0 (19h) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

DS41232D-page 139

PIC12F635/PIC16F636/639

12.9.2

TIMER INTERRUPT

12.9.3

PORTA INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF bit of the INTCON register. The interrupt can be

enabled/disabled by setting/clearing T0IE bit of the

INTCON register. See Section 5.0 “Timer0 Module”

for operation of the Timer0 module.

An input change on PORTA change sets the RAIF bit of

the INTCON register. The interrupt can be

enabled/disabled by setting/clearing the RAIE bit of the

INTCON register. Plus, individual pins can be configured

through the IOCA register.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

FIGURE 12-7:

INTERRUPT LOGIC

IOC-RA0

IOCA0

IOC-RA1

IOCA1

IOC-RA2

IOCA2

IOC-RA3

IOCA3

IOC-RA4

IOCA4

IOC-RA5

IOCA5

Wake-up (If in Sleep mode)

Interrupt to CPU

T0IF

T0IE

LVDIF

LVDIE

INTF

INTE

RAIF

TMR1IF

TMR1IE

RAIE

C1IF

C1IE

PEIE

GIE

(1)

C2IF

(1)

C2IE

EEIF

EEIE

OSFIF

OSFIE

CRIF

CRIE

Note 1: PIC16F636/639 only.

DS41232D-page 140

PIC12F635/PIC16F636/639

FIGURE 12-8:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

(1)

(5)

(2)

Interrupt Latency

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

PC

0004h

PC + 1

—

0005h

Inst (0005h)

Inst (0004h)

PC

Instruction

Fetched

Inst (PC)

Inst (PC + 1)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Value on

Value on:

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

INTCON

IOCA

PIR1

GIE

—

PEIE

—

T0IE

INTE

RAIE

T0IF

INTF

IOCA1

—

RAIF

0000 000x 0000 000x

IOCA5 IOCA4 IOCA3 IOCA2

CRIF C2IF⁽¹⁾C1IF OSFIF

CRIE C2IE⁽¹⁾C1IE OSFIE

IOCA0 --00 0000 --00 0000

TMR1IF 0000 00-0 0000 00-0

TMR1IE 0000 00-0 0000 00-0

EEIF

EEIE

LVDIF

LVDIE

PIE1

—

Legend: x= unknown, u= unchanged, – = unimplemented, read as ‘0’, q= value depends upon condition.

Shaded cells are not used by the Interrupt module.

Note 1: PIC16F636/639 only.

DS41232D-page 141

PIC12F635/PIC16F636/639

12.10 Context Saving During Interrupts

Note:

The PIC12F635/PIC16F636/639 normally

does not require saving the PCLATH.

However, if computed GOTO’s are used in

the ISR and the main code, the PCLATH

must be saved and restored in the ISR.

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since the lower 16 bytes of all banks are common in the

PIC12F635/PIC16F636/639 (see Figure 2-2), temporary

holding registers, W_TEMP and STATUS_TEMP, should

be placed in here. These 16 locations do not require

banking and therefore, make it easier to context save and

restore. The same code shown in Example 12-1 can be

used to:

• Store the W register.

• Store the STATUS register.

• Execute the ISR code.

• Restore the Status (and Bank Select Bit register).

• Restore the W register.

EXAMPLE 12-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

W_TEMP

STATUS,W

;Copy W to TEMP register

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

;Save status to bank zero STATUS_TEMP register

MOVWF

:

STATUS_TEMP

:(ISR)

:

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS41232D-page 142

PIC12F635/PIC16F636/639

A new prescaler has been added to the path between

the INTRC and the multiplexers used to select the path

for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTRC by 32 to 65536,

giving the WDT a nominal range of 1 ms to 268s.

12.11 Watchdog Timer (WDT)

The PIC12F635/PIC16F636/639 WDT is code and

functionally compatible with other PIC16F WDT

modules and adds a 16-bit prescaler to the WDT. This

allows the user to have a scaler value for the WDT and

TMR0 at the same time. In addition, the WDT time-out

value can be extended to 268 seconds. WDT is cleared

under certain conditions described in Table 12-7.

12.11.2 WDT CONTROL

The WDTE bit is located in the Configuration Word

register. When set, the WDT runs continuously.

12.11.1 WDT OSCILLATOR

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 16 ms, which is

compatible with the time base generated with previous

PIC12F635/PIC16F636/639 microcontroller versions.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC16F family of microcontrollers. See Section 5.0

“Timer0 Module” for more information.

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

FIGURE 12-9:

WATCHDOG TIMER BLOCK DIAGRAM

0

1

From TMR0 Clock Source

Prescaler⁽¹⁾

16-bit WDT Prescaler

8

PSA

PS<2:0>

To TMR0

PSA

31 kHz

LFINTOSC Clock

WDTPS<3:0>

1

0

WDTE from Configuration Word Register

SWDTEN from WDTCON

WDT Time-out

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 “Software Programmable Prescaler” for more information.

TABLE 12-7: WDT STATUS

Conditions

WDT

WDTE = 0

CLRWDTCommand

Oscillator Fail Detected

Cleared

Exit Sleep + System Clock = T1OSC, EXTRC, HFINTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

DS41232D-page 143

PIC12F635/PIC16F636/639

REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

SWDTEN⁽¹⁾

bit 0

WDTPS3

WDTPS2

WDTPS1

WDTPS0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

bit 0

SWDTEN: Software Enable or Disable the Watchdog Timer bit⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE

Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.

TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDTCON

—

INTEDG

CP

—

WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN

---0 1000

1111 1111

—

---0 1000

1111 1111

—

OPTION_REG

CONFIG

RAPU

CPD

T0CS

MCLRE

T0SE

PSA

PS2

PS1

PS0

PWRTE

WDTE

FOSC2

FOSC1

FOSC0

Legend:

Note 1:

Shaded cells are not used by the Watchdog Timer.

See Register 12-1 for operation of all Configuration Word register bits.

DS41232D-page 144

PIC12F635/PIC16F636/639

Other peripherals cannot generate interrupts, since

during Sleep, no on-chip clocks are present.

12.12 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

SLEEPinstruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

• PD bit in the STATUS register is cleared.

• TO bit is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or

high-impedance).

For lowest current consumption in this mode, all I/O pins

should be either at VDD or VSS, with no external circuitry

drawing current from the I/O pin and the comparators

and CVREF should be disabled. I/O pins that are

high-impedance inputs should be pulled high or low

externally to avoid switching currents caused by floating

inputs. The T0CKI input should also be at VDD or VSS for

lowest current consumption. The contribution from

on-chip pull-ups on PORTA should be considered.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEPinstruction is completely executed.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

The MCLR pin must be at a logic high level.

Note:

If WUR is enabled (WURE = 0 in

Configuration Word), then the Wake-up

Reset module will force a device Reset.

Note 1: It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

2: The Analog Front-End (AFE) section in

the PIC16F639 device is independent of

the microcontroller’s power-down mode

(Sleep). See Section 11.32.2.3 “Sleep

Command” for AFE’s Sleep mode.

12.12.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

12.12.1 WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin.

2. Watchdog Timer wake-up (if WDT was enabled).

• If the interrupt occurs during or after the

execution of a SLEEPinstruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set and the PD bit will be cleared.

3. Interrupt from RA2/INT pin, PORTA change or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device Reset. The

PD bit, which is set on power-up, is cleared when Sleep is

invoked. TO bit is cleared if WDT wake-up occurred.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

The following peripheral interrupts can wake the device

from Sleep:

1. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

2. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

3. EEPROM write operation completion.

4. Comparator output changes state.

5. Interrupt-on-change.

6. External Interrupt from INT pin.

DS41232D-page 145

PIC12F635/PIC16F636/639

FIGURE 12-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT⁽⁴⁾

INT pin

(2)

TOST

INTF Flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIE bit

(INTCON<7>)

Processor in

Sleep

INSTRUCTION FLOW

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Inst(PC – 1)

Fetched

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

3: GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

4: CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

12.13 Code Protection

12.14 ID Locations

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP for verification purposes.

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

Note:

The entire data EEPROM and Flash pro-

gram memory will be erased when the

code protection is turned off. See the

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

DS41232D-page 146

PIC12F635/PIC16F636/639

12.15 In-Circuit Serial Programming

12.16 In-Circuit Debugger

The PIC12F635/PIC16F636/639 microcontrollers can

be serially programmed while in the end application

circuit. This is simply done with two lines for clock and

data and three other lines for:

Since in-circuit debugging requires the loss of clock,

data and MCLR pins, MPLAB^®ICD 2 development with

a 14-pin device is not practical. A special 20-pin

PIC16F636 ICD device is used with MPLAB ICD 2 to

provide separate clock, data and MCLR pins and frees

all normally available pins to the user.

• Power

• Ground

Use of the ICD device requires the purchase of a

special header. On the top of the header is an

MPLAB ICD 2 connector. On the bottom of the

header is a 14-pin socket that plugs into the user’s

target via the 14-pin stand-off connector.

• Programming Voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

When the ICD pin on the PIC16F636 ICD device is held

low, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB ICD 2. When the microcontroller has

this feature enabled, some of the resources are not

available for general use. Table 12-9 shows which

features are consumed by the background debugger:

The device is placed into a Program/Verify mode by hold-

ing the RA0 and RA1 pins low, while raising the MCLR

(VPP) pin from VIL to VIHH. See the “PIC12F6XX/16F6XX

Memory Programming Specification” (DS41204) for

more information. RA0 becomes the programming data

and RA1 becomes the programming clock. Both RA0

and RA1 are Schmitt Trigger inputs in this mode.

TABLE 12-9: DEBUGGER RESOURCES

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the “PIC12F6XX/16F6XX Memory Programming

Specification” (DS41204).

Resource

I/O pins

Stack

Description

ICDCLK, ICDDATA

1 level

Program Memory Address 0h must be NOP

700h-7FFh

For more information, see the “MPLAB^®ICD 2 In-Circuit

Debugger User’s Guide” (DS51331), available on

Microchip’s web site (www.microchip.com).

A typical In-Circuit Serial Programming connection is

shown in Figure 12-11.

FIGURE 12-12:

20-Pin PDIP

20-PIN ICD PINOUT

FIGURE 12-11:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

In-Circuit Debug Device

To Normal

1

20

NC

ICDMCLR/VPP

VDD

ICDCLK

ICDDATA

VSS

RA0

RA1

RA2

RC0

RC1

RC2

Connections

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

12

External

Connector

Signals

*

RA5

RA4

RA3

RC5

RC4

RC3

PIC16F636

+5V

0V

VDD

VSS

VPP

MCLR/VPP/RA3

RA1

RA0

CLK

10

11

ICD

ENPORT

Data I/O

*

To Normal

Connections

*Isolation devices (as required).

DS41232D-page 147

PIC12F635/PIC16F636/639

NOTES:

DS41232D-page 148

PIC12F635/PIC16F636/639

TABLE 13-1: OPCODE FIELD

13.0 INSTRUCTION SET SUMMARY

DESCRIPTIONS

The PIC12F635/PIC16F636/639 instruction set is

highly orthogonal and is comprised of three basic

categories:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Byte-oriented operations

• Bit-oriented operations

Bit address within an 8-bit file register

Literal field, constant data or label

• Literal and control operations

k

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 13-1, while the various opcode

fields are summarized in Table 13-1.

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 13-2 lists the instructions recognized by the

MPASM^TMassembler.

PC

TO

C

Program Counter

Time-out bit

Carry bit

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

DC

Z

Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

PD

Power-down bit

FIGURE 13-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

For literal and control operations, ‘k’ represents an

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

8-bit or 11-bit constant, or literal value.

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 μs. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

13.1 Read-Modify-Write Operations

k = 8-bit immediate value

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the

instruction, or the destination designator ‘d’. A read

operation is performed on a register even if the

instruction writes to that register.

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

consequence of clearing the condition that set the RAIF

flag.

DS41232D-page 149

PIC12F635/PIC16F636/639

TABLE 13-2: PIC12F635/PIC16F636/639 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

Z

Move W to f

No Operation

–

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS41232D-page 150

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13.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) + k → (W)

C, DC, Z

Operation:

0→ (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1→ (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOPis executed instead, making

this a two-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

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CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

00h → WDT

0→ WDT prescaler,

1→ TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1→ PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

00h → (f)

1→ Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h → (W)

1→ Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - 1 → (destination);

skip if result = 0

Operation:

(f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

two-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a two-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

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PIC12F635/PIC16F636/639

MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) → (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register f is

moved to a destination dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k → (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

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PIC12F635/PIC16F636/639

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

TOS → PC,

1→ GIE

k → (W);

TOS → PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

;offset value

RETFIE

•

;W now has table value

TABLE

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

DS41232D-page 155

PIC12F635/PIC16F636/639

RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → WDT,

0→ WDT prescaler,

1→ TO,

Operation:

See description below

C

Status Affected:

Description:

0→ PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

k - (W) → (W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W > k

C = 1

W ≤ k

DC = 0

DC = 1

W<3:0> > k<3:0>

W<3:0> ≤ k<3:0>

C

Register f

DS41232D-page 156

PIC12F635/PIC16F636/639

SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k → (W)

Z

Operation:

(f) - (W) → (destination)

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f.

C = 0

W > f

C = 1

W ≤ f

DC = 0

DC = 1

W<3:0> > f<3:0>

W<3:0> ≤ f<3:0>

SWAPF

Swap Nibbles in f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Operation:

(W) .XOR. (f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

DS41232D-page 157

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NOTES:

DS41232D-page 158

PIC12F635/PIC16F636/639

14.1 MPLAB Integrated Development

Environment Software

14.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS41232D-page 159

PIC12F635/PIC16F636/639

14.2 MPASM Assembler

14.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

14.6 MPLAB SIM Software Simulator

14.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

14.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41232D-page 160

PIC12F635/PIC16F636/639

14.7 MPLAB ICE 2000

High-Performance

14.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

14.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

14.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

DS41232D-page 161

PIC12F635/PIC16F636/639

14.11 PICSTART Plus Development

Programmer

14.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

14.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41232D-page 162

PIC12F635/PIC16F636/639

15.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V

Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾............................................................................................................................... 800 mW

Maximum current out of VSS/VSST pin .............................................................................................................. 95 mA

Maximum current into VDD/VDDT pin................................................................................................................. 95 mA

Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA

Output clamp current, IOK (VO < 0 or VO >VDD)....................................................................................................... 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by PORTA and PORTC (combined) ............................................................................ 95 mA

Maximum current sourced PORTA and PORTC (combined)............................................................................ 95 mA

Maximum LC Input Voltage (LCX, LCY, LCZ)⁽²⁾loaded, with device ............................................................ 10.0 VPP

Maximum LC Input Voltage (LCX, LCY, LCZ)⁽²⁾unloaded, without device ................................................. 700.0 VPP

Maximum Input Current (rms) into device per LC Channel⁽²⁾........................................................................... 10 mA

Human Body ESD rating........................................................................................................................4000 (min.) V

Machine Model ESD rating ......................................................................................................................400 (min.) V

Note 1: Power dissipation for PIC12F635/PIC16F636/639 (AFE section not included) is calculated as follows:

PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL).

Power dissipation for AFE section is calculated as follows:

PDIS = VDD x IACT = 3.6V x 16 μA = 57.6 μW

2: Specification applies to the PIC16F639 only.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note:

Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a ‘low’ level to the MCLR pin, rather than

pulling this pin directly to VSS.

DS41232D-page 163

PIC12F635/PIC16F636/639

FIGURE 15-1:

PIC12F635/16F636 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0

8

10

20

4

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Cross-hatched area is for HFINTOSC and EC modes only.

FIGURE 15-2:

PIC16F639 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

5.5

5.0

4.5

4.0

3.6

3.0

2.5

2.0

0

4

8

10

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: Cross-hatched area is for HFINTOSC and EC modes only.

DS41232D-page 164

PIC12F635/PIC16F636/639

FIGURE 15-3:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

± 5%

85

60

25

± 2%

± 1%

0

-40

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

DS41232D-page 165

PIC12F635/PIC16F636/639

15.1 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)

PIC12F635/PIC16F636-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym

Characteristic

Min Typ† Max Units

Conditions

VDD

Supply Voltage

D001

2.0

3.0

4.5

—

5.5

V

FOSC < = 4 MHz

FOSC < = 8 MHz, HFINTOSC, EC

FOSC < = 10 MHz

D001A

D001B

D001C

FOSC < = 20 MHz

D002

VDR

RAM Data Retention

Voltage⁽¹⁾

1.5*

—

V

Device in Sleep mode

D003

VPOR

VDD Start Voltage to

ensure internal Power-on

Reset signal

—

VSS

—

V

See Section 12.3 “Power-on Reset” for

details.

D004

D005

SVDD

VDD Rise Rate to ensure 0.05*

internal Power-on Reset

signal

—

V/ms See Section 12.3 “Power-on Reset” for

details.

VBOD

Brown-out Reset

2.0

2.1

2.2

V

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS41232D-page 166

PIC12F635/PIC16F636/639

15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Sym

Device Characteristics

Supply Current^(1,2)

Min Typ† Max Units

VDD

Note

D010

IDD

—

11

18

16

28

μA

mA

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32.768 kHz

LP Oscillator mode

35

54

D011

D012

D013

D014

D015

D016

D017

D018

D019

140

220

380

260

420

0.8

240

380

550

360

650

1.1

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

130

215

360

220

375

0.65

8

220

360

520

340

550

1.0

FOSC = 1 MHz

EC Oscillator mode

FOSC = 4 MHz

EC Oscillator mode

20

FOSC = 31 kHz

LFINTOSC mode

16

40

31

65

340

500

0.8

450

700

1.2

FOSC = 4 MHz

HFINTOSC mode

410

700

1.30

230

400

0.63

2.6

650

950

1.65

400

680

1.1

FOSC = 8 MHz

HFINTOSC mode

FOSC = 4 MHz

EXTRC mode

3.25

FOSC = 20 MHz

HS Oscillator mode

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. MCU only, Analog

Front-End not included.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption. MCU only, Analog Front-End not included.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41232D-page 167

PIC12F635/PIC16F636/639

15.2 DC Characteristics: PIC12F635/PIC16F636-I (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Sym

Device Characteristics

Min Typ† Max Units

VDD

Note

D020

IPD

Power-down Base

Current⁽⁴⁾

—

0.15

0.20

0.35

1.0

2.0

3.0

58

1.2

1.5

1.8

2.2

4.0

7.0

60

μA

2.0 WDT, BOR,

Comparators, VREF

and T1OSC disabled

3.0

5.0

D021

2.0 WDT Current⁽¹⁾

3.0

5.0

D022A

D022B

3.0 BOR Current⁽¹⁾

109

22

122

28

5.0

2.0 PLVD Current

25

35

3.0

33

45

5.0

D023

32

45

2.0 Comparator Current⁽³⁾

60

78

3.0

5.0

120

30

160

36

D024A

D024B

D025

2.0

3.0

5.0

2.0

3.0

5.0

CVREF Current⁽¹⁾

(high-range)

45

55

75

95

39

47

CVREF Current⁽¹⁾

(low-range)

59

72

98

124

7.0

8.0

12

4.5

5.0

6.0

2.0 T1OSC Current⁽³⁾