PIC12F683-E/PG_技术文档

PIC12F683

Data Sheet

8-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

nanoWatt Technology

DS41211D

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EEPROMs, microperipherals, nonvolatile memory and analog

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manufacture of development systems is ISO 9001:2000 certified.

DS41211D-page ii

PIC12F683

8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

nanoWatt Technology

High-Performance RISC CPU:

Low-Power Features:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

• Standby Current:

- 50 nA @ 2.0V, typical

• Operating Current:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt capability

- 11 μA @ 32 kHz, 2.0V, typical

- 220 μA @ 4 MHz, 2.0V, typical

• Watchdog Timer Current:

- 1 μA @ 2.0V, typical

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

Peripheral Features:

Special Microcontroller Features:

• 6 I/O pins with individual direction control:

- High current source/sink for direct LED drive

- Interrupt-on-pin change

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range of

8 MHz to 125 kHz

- Individually programmable weak pull-ups

- Ultra Low-Power Wake-up on GP0

• Analog Comparator module with:

- One analog comparator

- Software tunable

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Comparator inputs and output externally

accessible

• Power-Saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended temperature range

• Power-on Reset (POR)

• A/D Converter:

- 10-bit resolution and 4 channels

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Enhanced Timer1:

• Brown-out Reset (BOR) with software control

option

- 16-bit timer/counter with prescaler

- External Timer1 Gate (count enable)

• Enhanced Low-Current Watchdog Timer (WDT)

with on-chip oscillator (software selectable nomi-

nal 268 seconds with full prescaler) with software

enable

- Option to use OSC1 and OSC2 in LP mode as

Timer1 oscillator if INTOSC mode selected

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• Capture, Compare, PWM module:

- 16-bit Capture, max resolution 12.5 ns

- Compare, max resolution 200 ns

- 10-bit PWM, max frequency 20 kHz

• High Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM Retention: > 40 years

• In-Circuit Serial Programming™ (ICSP™) via

two pins

Program Memory

Flash (words)

2048

Data Memory

Timers

I/O 10-bit A/D (ch) Comparators

8/16-bit

Device

SRAM (bytes)

EEPROM (bytes)

256

PIC12F683

128

6

4

1

2/1

DS41211D-page 1

PIC12F683

8-Pin Diagram (PDIP, SOIC)

1

2

3

4

8

7

VSS

VDD

GP0/AN0/CIN+/ICSPDAT/ULPWU

GP1/AN1/CIN-/VREF/ICSPCLK

GP2/AN2/T0CKI/INT/COUT/CCP1

GP5/T1CKI/OSC1/CLKIN

GP4/AN3/T1G/OSC2/CLKOUT

GP3/MCLR/VPP

6

5

8-Pin Diagram (DFN)

VDD

GP5/TICKI/OSC1/CLKIN

GP4/AN3/TIG/OSC2/CLKOUT

GP3/MCLR/VPP

VSS

8

7

6

5

1

2

GP0/AN0/CIN+/ICSPDAT/ULPWU

GP1/AN1/CIN-/VREF/ICSPCLK

GP2/AN2/T0CKI/INT/COUT/CCP1

PIC12F683

3

4

8-Pin Diagram (DFN-S)

VDD

GP5/TICKI/OSC1/CLKIN

GP4/AN3/TIG/OSC2/CLKOUT

GP3/MCLR/VPP

VSS

8

7

6

5

1

2

GP0/AN0/CIN+/ICSPDAT/ULPWU

GP1/AN1/CIN-/VREF/ICSPCLK

GP2/AN2/T0CKI/INT/COUT/CCP1

PIC12F683

3

4

TABLE 1:

8-PIN SUMMARY

I/O

Analog

Comparators

Timer

CCP

Interrupts Pull-ups

Basic

GP0

7

6

5

AN0

AN1/VREF

AN2

CIN+

CIN-

—

IOC

Y

ICSPDAT/ULPWU

GP1

ICSPCLK

—

GP2

COUT

T0CKI

CCP1

INT/IOC

GP3⁽¹⁾

4

3

—

IOC

Y⁽²⁾

Y

MCLR/VPP

GP4

AN3

OSC2/CLKOUT

T1G

T1CKI

—

GP5

—

2

1

8

—

IOC

—

Y

OSC1/CLKIN

VDD

—

VSS

Note 1: Input only.

2: Only when pin is configured for external MCLR.

DS41211D-page 2

PIC12F683

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................... 7

3.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 19

4.0 GPIO Port................................................................................................................................................................................... 31

5.0 Timer0 Module ........................................................................................................................................................................... 41

6.0 Timer1 Module with Gate Control............................................................................................................................................... 44

7.0 Timer2 Module ........................................................................................................................................................................... 49

8.0 Comparator Module.................................................................................................................................................................... 51

9.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 61

10.0 Data EEPROM Memory ............................................................................................................................................................. 71

11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 75

12.0 Special Features of the CPU...................................................................................................................................................... 83

13.0 Instruction Set Summary.......................................................................................................................................................... 101

14.0 Development Support............................................................................................................................................................... 111

15.0 Electrical Specifications............................................................................................................................................................ 115

16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 137

17.0 Packaging Information.............................................................................................................................................................. 159

Appendix A: Data Sheet Revision History.......................................................................................................................................... 165

Appendix B: Migrating From Other PIC® Devices............................................................................................................................. 165

The Microchip Web Site..................................................................................................................................................................... 171

Customer Change Notification Service .............................................................................................................................................. 171

Customer Support.............................................................................................................................................................................. 171

Reader Response.............................................................................................................................................................................. 172

Product Identification System ............................................................................................................................................................ 173

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DS41211D-page 3

PIC12F683

NOTES:

DS41211D-page 4

PIC12F683

1.0

DEVICE OVERVIEW

The PIC12F683 is covered by this data sheet. It is

available in 8-pin PDIP, SOIC and DFN-S packages.

Figure 1-1 shows a block diagram of the PIC12F683

device. Table 1-1 shows the pinout description.

FIGURE 1-1:

PIC12F683 BLOCK DIAGRAM

INT

Configuration

13

8

Data Bus

Program Counter

GP0

GP1

GP2

GP3

GP4

GP5

Flash

2k x 14

Program

RAM

8-Level Stack

(13-bit)

Memory

128 bytes

File

Registers

Program

Bus

14

RAM Addr

9

Addr MUX

Instruction Reg

Indirect

Addr

7

Direct Addr

8

FSR Reg

STATUS Reg

MUX

8

3

Power-up

Timer

Instruction

Decode &

Control

Oscillator

Start-up Timer

ALU

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

OSC1/CLKIN

W Reg

Brown-out

Reset

OSC2/CLKOUT

Internal

Oscillator

Block

CCP1

T1G

VDD

VSS

MCLR

T1CKI

Timer0

Timer1

Timer2

CCP

T0CKI

EEDATA

Analog-to-Digital Converter

AN0 AN1 AN2 AN3

1 Analog Comparator

256 bytes

Data

EEPROM

8

EEADDR

VREF

CVREF CIN- CIN+ COUT

DS41211D-page 5

PIC12F683

TABLE 1-1:

PIC12F683 PINOUT DESCRIPTION

Input

Type

Output

Type

Name

Function

Description

VDD

GP5

Power

TTL

ST

—

Positive supply

GP5/T1CKI/OSC1/CLKIN

CMOS GPIO I/O with prog. pull-up and interrupt-on-change

T1CKI

OSC1

CLKIN

GP4

—

Timer1 clock

XTAL

ST

Crystal/Resonator

External clock input/RC oscillator connection

GP4/AN3/T1G/OSC2/CLKOUT

TTL

AN

ST

CMOS GPIO I/O with prog. pull-up and interrupt-on-change

AN3

—

A/D Channel 3 input

Timer1 gate

T1G

OSC2

CLKOUT

GP3

—

XTAL

Crystal/Resonator

—

CMOS FOSC/4 output

GP3/MCLR/VPP

TTL

ST

—

GPIO input with interrupt-on-change

MCLR

VPP

Master Clear with internal pull-up

Programming voltage

HV

ST

GP2/AN2/T0CKI/INT/COUT/CCP1

GP2

CMOS GPIO I/O with prog. pull-up and interrupt-on-change

AN2

AN

ST

—

A/D Channel 2 input

Timer0 clock input

External Interrupt

T0CKI

INT

ST

COUT

CCP1

GP1

—

CMOS Comparator 1 output

ST

CMOS Capture input/Compare output/PWM output

CMOS GPIO I/O with prog. pull-up and interrupt-on-change

GP1/AN1/CIN-/VREF/ICSPCLK

GP0/AN0/CIN+/ICSPDAT/ULPWU

VSS

TTL

AN

ST

AN1

—

A/D Channel 1 input

CIN-

Comparator 1 input

VREF

External Voltage Reference for A/D

Serial Programming Clock

ICSPCLK

GP0

TTL

AN

ST

CMOS GPIO I/O with prog. pull-up and interrupt-on-change

AN0

—

A/D Channel 0 input

Comparator 1 input

CIN+

ICSPDAT

ULPWU

VSS

CMOS Serial Programming Data I/O

AN

Power

—

Ultra Low-Power Wake-up input

Ground reference

Legend:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

DS41211D-page 6

PIC12F683

2.2

Data Memory Organization

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The data memory (see Figure 2-2) is partitioned into two

banks, which contain the General Purpose Registers

(GPR) and the Special Function Registers (SFR). The

Special Function Registers are located in the first 32

locations of each bank. Register locations 20h-7Fh in

Bank 0 and A0h-BFh in Bank 1 are General Purpose

Registers, implemented as static RAM. Register

locations F0h-FFh in Bank 1 point to addresses 70h-7Fh

in Bank 0. All other RAM is unimplemented and returns

‘0’ when read. RP0 of the STATUS register is the bank

select bit.

The PIC12F683 has a 13-bit program counter capable

of addressing an 8k x 14 program memory space. Only

the first 2k x 14 (0000h-07FFh) for the PIC12F683 is

physically implemented. Accessing a location above

these boundaries will cause a wraparound within the

first 2K x 14 space. The Reset vector is at 0000h and

the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC12F683

RP0

0

1

→

Bank 0 is selected

Bank 1 is selected

PC<12:0>

13

CALL, RETURN

RETFIE, RETLW

Note:

The IRP and RP1 bits of the STATUS

register are reserved and should always

be maintained as ‘0’s.

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

0000h

Interrupt Vector

0004h

0005h

On-chip Program

Memory

07FFh

0800h

Wraps to 0000h-07FFh

1FFFh

DS41211D-page 7

PIC12F683

2.2.1

GENERAL PURPOSE REGISTER

FILE

FIGURE 2-2:

DATA MEMORY MAP OF

THE PIC12F683

The register file is organized as 128 x 8 in the

PIC12F683. Each register is accessed, either directly

or indirectly, through the File Select Register FSR (see

Section 2.4 “Indirect Addressing, INDF and FSR

Registers”).

File

Address

File

Address

Indirect addr.⁽¹⁾

OPTION_REG

PCL

00h

01h

02h

80h

81h

82h

TMR0

PCL

STATUS

FSR

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

STATUS

FSR

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-1). These

registers are static RAM.

GPIO

TRISIO

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

TMR1L

TMR1H

T1CON

TMR2

PCON

OSCCON

OSCTUNE

PR2

T2CON

CCPR1L

CCPR1H

CCP1CON

WPU

IOC

WDTCON

CMCON0

CMCON1

VRCON

EEDAT

EEADR

EECON1

EECON2⁽¹⁾

ADRESL

ADRESH

ADCON0

ANSEL

General

Purpose

Registers

32 Bytes

9Fh

A0h

BFh

C0h

General

Purpose

Registers

96 Bytes

EFh

F0h

Accesses 70h-7Fh

BANK 1

FFh

7Fh

BANK 0

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

DS41211D-page 8

PIC12F683

TABLE 2-1:

PIC12F683 SPECIAL REGISTERS SUMMARY BANK 0

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 0

00h INDF

01h TMR0

02h PCL

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90

Timer0 Module Register

xxxx xxxx 41, 90

0000 0000 17, 90

0001 1xxx 11, 90

xxxx xxxx 17, 90

--xx xxxx 31, 90

Program Counter’s (PC) Least Significant Byte

(1)

03h STATUS

04h FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

05h GPIO

—

GP5

GP4

GP3

GP2

GP1

GP0

06h

07h

08h

09h

—

Unimplemented

—

0Ah PCLATH

0Bh INTCON

0Ch PIR1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000 17, 90

0000 0000 13, 90

GIE

EEIF

PEIE

ADIF

T0IE

INTE

—

GPIE

CMIF

T0IF

INTF

GPIF

CCP1IF

OSFIF

TMR2IF

TMR1IF 000- 0000 15, 90

0Dh

—

Unimplemented

—

0Eh TMR1L

0Fh TMR1H

10h T1CON

Holding Register for the Least Significant Byte of the 16-bit TMR1

Holding Register for the Most Significant Byte of the 16-bit TMR1

xxxx xxxx 44, 90

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 47, 90

Timer2 Module Register 0000 0000 49, 90

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50, 90

11h

TMR2

12h T2CON

—

13h CCPR1L Capture/Compare/PWM Register 1 Low Byte

14h CCPR1H Capture/Compare/PWM Register 1 High Byte

xxxx xxxx 76, 90

15h CCP1CON

—

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 75, 90

16h

17h

—

Unimplemented

—

18h WDTCON

19h CMCON0

1Ah CMCON1

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 97, 90

COUT

—

CINV

—

CIS

—

CM2

—

CM1

CM0

-0-0 0000 56, 90

T1GSS

CMSYNC ---- --10 57, 90

1Bh

1Ch

1Dh

—

Unimplemented

—

1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result

1Fh ADCON0 ADFM VCFG CHS1 CHS0 GO/DONE

Legend:

xxxx xxxx 61,90

—

ADON 00-- 0000 65,90

– = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,

shaded = unimplemented

Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

DS41211D-page 9

PIC12F683

TABLE 2-2:

PIC12F683 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 1

80h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 17, 90

81h OPTION_REG GPPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 12, 90

0000 0000 17, 90

0001 1xxx 11, 90

xxxx xxxx 17, 90

82h PCL

Program Counter’s (PC) Least Significant Byte

(1)

83h STATUS

84h FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

85h TRISIO

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 32, 90

86h

87h

88h

89h

—

Unimplemented

—

8Ah PCLATH

8Bh INTCON

8Ch PIE1

—

Write Buffer for upper 5 bits of Program Counter

---0 0000 17, 90

0000 0000 13, 90

GIE

EEIE

PEIE

ADIE

T0IE

INTE

—

GPIE

CMIE

T0IF

INTF

GPIF

CCP1IE

OSFIE

TMR2IE TMR1IE 000- 0000 14, 90

8Dh

—

Unimplemented

—

8Eh PCON

—

ULPWUE SBOREN

—

POR

LTS

BOR

SCS

--01 --qq 16, 90

-110 x000 20, 90

(2)

8Fh OSCCON

90h OSCTUNE

IRCF2

—

IRCF1

—

IRCF0

TUN4

OSTS

TUN3

HTS

TUN2

TUN1

TUN0 ---0 0000 24, 90

91h

—

Unimplemented

—

92h PR2

93h

Timer2 Module Period Register

Unimplemented

1111 1111 49, 90

—

94h

Unimplemented

(3)

95h WPU

96h IOC

97h

—

WPU5

IOC5

WPU4

IOC4

—

WPU2

IOC2

WPU1

IOC1

WPU0 --11 -111 34, 90

IOC3

IOC0

--00 0000 34, 90

—

Unimplemented

—

98h

99h VRCON

9Ah EEDAT

9Bh EEADR

9Ch EECON1

9Dh EECON2

9Eh ADRESL

9Fh ANSEL

VREN

—

VRR

—

VR3

VR2

VR1

VR0

0-0- 0000 58, 90

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 71, 90

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 71, 90

—

WRERR

EEPROM Control Register 2 (not a physical register)

Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result

ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1

WREN

WR

RD

---- x000 72, 91

---- ---- 72, 91

xxxx xxxx 66, 91

—

ANS0 -000 1111 33, 91

Legend:

– = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,

shaded = unimplemented

Note 1: IRP and RP1 bits are reserved, always maintain these bits clear.

2: OSTS bit of the OSCCON register reset to ‘0’ with Dual Speed Start-up and LP, HS or XT selected as the oscillator.

3: GP3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.

DS41211D-page 10

PIC12F683

For example, CLRF STATUS, will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• Arithmetic status of the ALU

• Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not affect-

ing any Status bits, see the “Instruction Set Summary”.

• Bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: Bits IRP and RP1 of the STATUS register

are not used by the PIC12F683 and

should be maintained as clear. Use of

these bits is not recommended, since this

may affect upward compatibility with

future products.

2: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction.

REGISTER 2-1:

STATUS: STATUS REGISTER

Reserved

IRP

Reserved

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

bit 6

bit 5

IRP: This bit is reserved and should be maintained as ‘0’

RP1: This bit is reserved and should be maintained as ‘0’

RP0: Register Bank Select bit (used for direct addressing)

1= Bank 1 (80h – FFh)

0= Bank 0 (00h – 7Fh)

bit 4

bit 3

bit 2

bit 1

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions), For Borrow, the polarity is

reversed.

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

bit 0

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

DS41211D-page 11

PIC12F683

2.2.2.2

OPTION Register

Note:

To achieve a 1:1 prescaler assignment for

Timer0, assign the prescaler to the WDT

by setting PSA bit of the OPTION register

to ‘1’ See Section 5.1.3 “Software Pro-

grammable Prescaler”.

The OPTION register is a readable and writable

register, which contains various control bits to

configure:

• TMR0/WDT prescaler

• External GP2/INT interrupt

• TMR0

• Weak pull-ups on GPIO

REGISTER 2-2:

OPTION_REG: OPTION REGISTER

R/W-1

GPPU

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

GPPU: GPIO Pull-up Enable bit

1= GPIO pull-ups are disabled

0= GPIO pull-ups are enabled by individual PORT latch values in WPU register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

BIT VALUE TIMER0 RATE WDT RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more

information.

DS41211D-page 12

PIC12F683

2.2.2.3

INTCON Register

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, GPIO change and external

GP2/INT pin interrupts.

REGISTER 2-3:

INTCON: INTERRUPT CONTROL REGISTER

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

GPIE

R/W-0

T0IF

R/W-0

INTF

R/W-0

GPIF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

INTE: GP2/INT External Interrupt Enable bit

1= Enables the GP2/INT external interrupt

0= Disables the GP2/INT external interrupt

GPIE: GPIO Change Interrupt Enable bit⁽¹⁾

1= Enables the GPIO change interrupt

0= Disables the GPIO change interrupt

T0IF: Timer0 Overflow Interrupt Flag bit⁽²⁾

1= Timer0 register has overflowed (must be cleared in software)

0= Timer0 register did not overflow

INTF: GP2/INT External Interrupt Flag bit

1= The GP2/INT external interrupt occurred (must be cleared in software)

0= The GP2/INT external interrupt did not occur

GPIF: GPIO Change Interrupt Flag bit

1= When at least one of the GPIO <5:0> pins changed state (must be cleared in software)

0= None of the GPIO <5:0> pins have changed state

Note 1: IOC register must also be enabled.

2: T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before

clearing T0IF bit.

DS41211D-page 13

PIC12F683

2.2.2.4

PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-4.

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt.

REGISTER 2-4:

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0

EEIE

R/W-0

ADIE

R/W-0

U-0

—

R/W-0

CMIE

R/W-0

OSFIE

R/W-0

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

EEIE: EE Write Complete Interrupt Enable bit

1= Enables the EE write complete interrupt

0= Disables the EE write complete interrupt

ADIE: A/D Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

bit 4

bit 3

Unimplemented: Read as ‘0’

CMIE: Comparator Interrupt Enable bit

1= Enables the Comparator 1 interrupt

0= Disables the Comparator 1 interrupt

bit 2

bit 1

bit 0

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the oscillator fail interrupt

0= Disables the oscillator fail interrupt

TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

DS41211D-page 14

PIC12F683

2.2.2.5

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE of the INTCON register.

User software should ensure the appropri-

ate interrupt flag bits are clear prior to

enabling an interrupt.

REGISTER 2-5:

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0

EEIF

R/W-0

ADIF

R/W-0

U-0

—

R/W-0

CMIF

R/W-0

OSFIF

R/W-0

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

EEIF: EEPROM Write Operation Interrupt Flag bit

1= The write operation completed (must be cleared in software)

0= The write operation has not completed or has not been started

ADIF: A/D Interrupt Flag bit

1= A/D conversion complete

0= A/D conversion has not completed or has not been started

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4

bit 3

Unimplemented: Read as ‘0’

CMIF: Comparator Interrupt Flag bit

1= Comparator 1 output has changed (must be cleared in software)

0= Comparator 1 output has not changed

bit 2

bit 1

bit 0

OSFIF: Oscillator Fail Interrupt Flag bit

1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0= System clock operating

TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1= Timer2 to PR2 match occurred (must be cleared in software)

0= Timer2 to PR2 match has not occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Timer1 register overflowed (must be cleared in software)

0= Timer1 has not overflowed

DS41211D-page 15

PIC12F683

2.2.2.6

PCON Register

The Power Control (PCON) register contains flag bits

(see Table 12-2) to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the Ultra Low-Power

Wake-up and software enable of the BOR.

The PCON register bits are shown in Register 2-6.

REGISTER 2-6:

PCON: POWER CONTROL REGISTER

U-0

—

U-0

—

R/W-0

R/W-1

U-0

—

U-0

—

R/W-0

POR

R/W-x

BOR

ULPWUE

SBOREN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5

Unimplemented: Read as ‘0’

ULPWUE: Ultra Low-Power Wake-Up Enable bit

1= Ultra Low-Power Wake-up enabled

0= Ultra Low-Power Wake-up disabled

bit 4

SBOREN: Software BOR Enable bit⁽¹⁾

1= BOR enabled

0= BOR disabled

bit 3-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

Note 1: Set BOREN<1:0> = 01in the Configuration Word register for this bit to control the BOR.

DS41211D-page 16

PIC12F683

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

2.3

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from PCLATH.

On any Reset, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower exam-

ple in Figure 2-3 shows how the PC is loaded during a

CALLor GOTOinstruction (PCLATH<4:3> → PCH).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW and RETFIE

instructions or the vectoring to an

interrupt address.

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.4

Indirect Addressing, INDF and

FSR Registers

PCH

PCL

Instruction with

PCL as

12

8

7

0

Destination

PC

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

8

PCLATH<4:0>

PCLATH

5

ALU Result

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit of

the STATUS register, as shown in Figure 2-4.

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

PCLATH<4:3>

PCLATH

11

2

OPCODE<10:0>

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

2.3.1

COMPUTED GOTO

EXAMPLE 2-1:

INDIRECT ADDRESSING

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTOmethod, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

MOVLW

MOVWF

CLRF

INCF

BTFSS

GOTO

0x20

FSR

INDF

FSR

FSR,4

;to RAM

;clear INDF register

;inc pointer

;all done?

;no clear next

;yes continue

2.3.2

STACK

The PIC12F683 family has an 8-level x 13-bit wide

hardware stack (see Figure 2-1). The stack space is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALLinstruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN,RETLWor a RETFIEinstruction

execution. PCLATH is not affected by a PUSH or POP

operation.

DS41211D-page 17

PIC12F683

FIGURE 2-4:

DIRECT/INDIRECT ADDRESSING PIC12F683

Direct Addressing

From Opcode

Indirect Addressing

(1)

7

RP1

RP0

6

0

IRP

File Select Register

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

Not Used

7Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

For memory map detail, see Figure 2-2.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

DS41211D-page 18

PIC12F683

The Oscillator module can be configured in one of eight

clock modes.

3.0

3.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

1. EC – External clock with I/O on OSC2/CLKOUT.

2. LP – 32 kHz Low-Power Crystal mode.

Overview

3. XT

– Medium Gain Crystal or Ceramic

The Oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing perfor-

mance and minimizing power consumption. Figure 3-1

illustrates a block diagram of the Oscillator module.

Resonator Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on OSC2/CLKOUT.

Clock sources can be configured from external

oscillators, quartz crystal resonators, ceramic resonators

and Resistor-Capacitor (RC) circuits. In addition, the

system clock source can be configured from one of two

internal oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. RCIO – External Resistor-Capacitor (RC) with

I/O on OSC2/CLKOUT.

7. INTOSC – Internal oscillator with FOSC/4 output

on OSC2 and I/O on OSC1/CLKIN.

8. INTOSCIO – Internal oscillator with I/O on

OSC1/CLKIN and OSC2/CLKOUT.

• Selectable system clock source between external

or internal via software.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word register (CONFIG). The

internal clock can be generated from two internal

• Two-Speed Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

oscillators. The HFINTOSC is

a

calibrated

high-frequency oscillator. The LFINTOSC is an

uncalibrated low-frequency oscillator.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch

automatically to the internal oscillator.

FIGURE 3-1:

PIC^®MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word Register)

External Oscillator

SCS<0>

(OSCCON Register)

OSC2

OSC1

Sleep

LP, XT, HS, RC, RCIO, EC

IRCF<2:0>

(OSCCON Register)

System Clock

(CPU and Peripherals)

8 MHz

111

110

101

INTOSC

Internal Oscillator

4 MHz

2 MHz

1 MHz

HFINTOSC

8 MHz

100

011

010

001

000

500 kHz

250 kHz

125 kHz

31 kHz

LFINTOSC

31 kHz

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

DS41211D-page 19

PIC12F683

3.2

Oscillator Control

The Oscillator Control (OSCCON) register (Figure 3-1)

controls the system clock and frequency selection

options. The OSCCON register contains the following

bits:

• Frequency selection bits (IRCF)

• Frequency Status bits (HTS, LTS)

• System clock control bits (OSTS, SCS)

REGISTER 3-1:

OSCCON: OSCILLATOR CONTROL REGISTER

U-0

—

R/W-1

IRCF2

R/W-1

IRCF1

R/W-0

IRCF0

R-1

OSTS⁽¹⁾

R-0

LTS

R/W-0

SCS

HTS

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

111= 8 MHz

110= 4 MHz (default)

101= 2 MHz

100= 1 MHz

011= 500 kHz

010= 250 kHz

001= 125 kHz

000= 31 kHz (LFINTOSC)

bit 3

bit 2

bit 1

bit 0

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Device is running from the external clock defined by FOSC<2:0> of the Configuration Word register

0= Device is running from the internal oscillator (HFINTOSC or LFINTOSC)

HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)

1= HFINTOSC is stable

0= HFINTOSC is not stable

LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)

1= LFINTOSC is stable

0= LFINTOSC is not stable

SCS: System Clock Select bit

1= Internal oscillator is used for system clock

0= Clock source defined by FOSC<2:0> of the Configuration Word register

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe

mode is enabled.

DS41211D-page 20

PIC12F683

3.3

Clock Source Modes

3.4

External Clock Modes

Clock Source modes can be classified as external or

internal.

3.4.1 OSCILLATOR START-UP TIMER (OST)

If the Oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR) and when the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

is providing a stable system clock to the Oscillator

module. When switching between clock sources, a

delay is required to allow the new clock to stabilize.

These oscillator delays are shown in Table 3-1.

• External Clock modes rely on external circuitry for

the clock source. Examples are: Oscillator mod-

ules (EC mode), quartz crystal resonators or

ceramic resonators (LP, XT and HS modes) and

Resistor-Capacitor (RC) mode circuits.

• Internal clock sources are contained internally

within the Oscillator module. The Oscillator

module has two internal oscillators: the 8 MHz

High-Frequency Internal Oscillator (HFINTOSC)

and the 31 kHz Low-Frequency Internal Oscillator

(LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Select

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for additional information.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 3.7

“Two-Speed Clock Start-up Mode”).

TABLE 3-1:

OSCILLATOR DELAY EXAMPLES

Switch From

Switch To

Frequency

Oscillator Delay

LFINTOSC

HFINTOSC

31 kHz

125 kHz to 8 MHz

Sleep/POR

Oscillator Warm-Up Delay (TWARM)

Sleep/POR

LFINTOSC (31 kHz)

Sleep/POR

EC, RC

DC – 20 MHz

2 instruction cycles

1 cycle of each

LP, XT, HS

HFINTOSC

32 kHz to 20 MHz

125 kHz to 8 MHz

1024 Clock Cycles (OST)

1 μs (approx.)

LFINTOSC (31 kHz)

3.4.2

EC MODE

FIGURE 3-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

The External Clock (EC) mode allows an externally

generated logic level as the system clock source. When

operating in this mode, an external clock source is

connected to the OSC1 input and the OSC2 is available

for general purpose I/O. Figure 3-2 shows the pin

connections for EC mode.

OSC1/CLKIN

Clock from

Ext. System

PIC^®MCU

(1)

I/O

OSC2/CLKOUT

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

Note 1: Alternate pin functions are listed in the

Device Overview.

DS41211D-page 21

PIC12F683

3.4.3

LP, XT, HS MODES

Note 1: Quartz crystal characteristics vary according

to type, package and manufacturer. The

user should consult the manufacturer data

sheets for specifications and recommended

application.

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 3-3). The mode selects a low,

medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals).

3: For oscillator design assistance, reference

the following Microchip Applications Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification.

Analysis and Design” (DS00943)

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require a high drive setting.

• AN949, “Making Your Oscillator Work”

(DS00949)

FIGURE 3-4:

CERAMIC RESONATOR

OPERATION

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

(XT OR HS MODE)

FIGURE 3-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

PIC^®MCU

OSC1/CLKIN

C1

PIC^®MCU

To Internal

Logic

OSC1/CLKIN

(3)

(2)

RP

RF

Sleep

C1

To Internal

Logic

Quartz

Crystal

(2)

OSC2/CLKOUT

(1)

C2

RF

Sleep

RS

Ceramic

Resonator

Note 1: A series resistor (RS) may be required for

OSC2/CLKOUT

(1)

C2

RS

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ to 10 MΩ).

DS41211D-page 22

PIC12F683

3.4.4

EXTERNAL RC MODES

3.5

Internal Clock Modes

The external Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes: RC and RCIO.

The Oscillator module has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The frequency of the HFINTOSC can be

user-adjusted via software using the OSCTUNE

register (Register 3-2).

In RC mode, the RC circuit connects to OSC1.

OSC2/CLKOUT outputs the RC oscillator frequency

divided by 4. This signal may be used to provide a clock

for external circuitry, synchronization, calibration, test

or other application requirements. Figure 3-5 shows

the external RC mode connections.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at 31 kHz.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select bits

IRCF<2:0> of the OSCCON register.

FIGURE 3-5:

EXTERNAL RC MODES

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit of the OSCCON register. See Section 3.6

“Clock Switching” for more information.

VDD

PIC^®MCU

REXT

OSC1/CLKIN

Internal

Clock

3.5.1 INTOSC AND INTOSCIO MODES

CEXT

VSS

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when

the device is programmed using the oscillator selection

or the FOSC<2:0> bits in the Configuration Word

register (CONFIG). See Section 12.0 “Special

Features of the CPU” for more information.

(1)

FOSC/4 or

OSC2/CLKOUT

(2)

I/O

Recommended values: 10 kΩ ≤ REXT ≤ 100 kΩ, <3V

3 kΩ ≤ REXT ≤ 100 kΩ, 3-5V

In INTOSC mode, OSC1/CLKIN is available for general

purpose I/O. OSC2/CLKOUT outputs the selected

internal oscillator frequency divided by 4. The CLKOUT

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

CEXT > 20 pF, 2-5V

Note 1: Alternate pin functions are listed in the Device

Overview.

2: Output depends upon RC or RCIO clock mode.

In RCIO mode, the RC circuit is connected to OSC1.

OSC2 becomes an additional general purpose I/O pin.

In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT

are available for general purpose I/O.

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT) values

and the operating temperature. Other factors affecting

the oscillator frequency are:

3.5.2

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered via

software using the OSCTUNE register (Register 3-2).

• threshold voltage variation

• component tolerances

• packaging variations in capacitance

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). One of seven

frequencies can be selected via software using the

IRCF<2:0> bits of the OSCCON register. See

Section 3.5.4 “Frequency Select Bits (IRCF)” for

more information.

The user also needs to take into account variation due

to tolerance of external RC components used.

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz by setting the IRCF<2:0>

bits of the OSCCON register ≠ 000. Then, set the

System Clock Source (SCS) bit of the OSCCON

register to ‘1’ or enable Two-Speed Start-up by setting

the IESO bit in the Configuration Word register

(CONFIG) to ‘1’.

The HF Internal Oscillator (HTS) bit of the OSCCON

register indicates whether the HFINTOSC is stable or not.

DS41211D-page 23

PIC12F683

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. Code execution continues during this shift.

There is no indication that the shift has occurred.

3.5.2.1

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

register (Register 3-2).

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number.

REGISTER 3-2:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Oscillator module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

DS41211D-page 24

PIC12F683

3.5.3

LFINTOSC

3.5.5

HF AND LF INTOSC CLOCK

SWITCH TIMING

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated 31 kHz internal clock source.

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power (see Figure 3-6). If this is the case,

there is a delay after the IRCF<2:0> bits of the

OSCCON register are modified before the frequency

selection takes place. The LTS and HTS bits of the

OSCCON register will reflect the current active status

of the LFINTOSC and HFINTOSC oscillators. The

timing of a frequency selection is as follows:

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). Select 31 kHz, via

software, using the IRCF<2:0> bits of the OSCCON

register. See Section 3.5.4 “Frequency Select Bits

(IRCF)” for more information. The LFINTOSC is also the

frequency for the Power-up Timer (PWRT), Watchdog

Timer (WDT) and Fail-Safe Clock Monitor (FSCM).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<2:0> bits of the OSCCON register = 000)as the

system clock source (SCS bit of the OSCCON

register = 1), or when any of the following are enabled:

1. IRCF<2:0> bits of the OSCCON register are

modified.

2. If the new clock is shut down, a clock start-up

delay is started.

• Two-Speed Start-up IESO bit of the Configuration

Word register = 1and IRCF<2:0> bits of the

OSCCON register = 000

3. Clock switch circuitry waits for a falling edge of

the current clock.

4. CLKOUT is held low and the clock switch

circuitry waits for a rising edge in the new clock.

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

5. CLKOUT is now connected with the new clock.

LTS and HTS bits of the OSCCON register are

updated as required.

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit of the OSCCON

register indicates whether the LFINTOSC is stable or

not.

6. Clock switch is complete.

See Figure 3-1 for more details.

3.5.4

FREQUENCY SELECT BITS (IRCF)

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and new frequencies are derived from the HFINTOSC

via the postscaler and multiplexer.

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see Figure 3-1). The Internal Oscillator Frequency

Select bits IRCF<2:0> of the OSCCON register select

the frequency output of the internal oscillators. One of

eight frequencies can be selected via software:

Start-up delay specifications are located in the

Electrical Specifications Chapter of this data sheet,

under AC Specifications (Oscillator Module).

• 8 MHz

• 4 MHz (Default after Reset)

• 2 MHz

• 1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz (LFINTOSC)

Note:

Following any Reset, the IRCF<2:0> bits of

the OSCCON register are set to ‘110’ and

the frequency selection is set to 4 MHz.

The user can modify the IRCF bits to

select a different frequency.

DS41211D-page 25

PIC12F683

FIGURE 3-6:

INTERNAL OSCILLATOR SWITCH TIMING

HF

LF⁽¹⁾

HFINTOSC

LFINTOSC (FSCM and WDT disabled)

HFINTOSC

Start-up Time

2-cycle Sync

Running

LFINTOSC

≠ 0

= 0

IRCF <2:0>

System Clock

Note 1: When going from LF to HF.

HFINTOSC

LFINTOSC (Either FSCM or WDT enabled)

2-cycle Sync

Running

LFINTOSC

≠ 0

= 0

IRCF <2:0>

System Clock

LFINTOSC

HFINTOSC

LFINTOSC turns off unless WDT or FSCM is enabled

Running

LFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC

= 0

≠ 0

IRCF <2:0>

System Clock

DS41211D-page 26

PIC12F683

When the Oscillator module is configured for LP, XT or

HS modes, the Oscillator Start-up Timer (OST) is

enabled (see Section 3.4.1 “Oscillator Start-up Timer

(OST)”). The OST will suspend program execution until

1024 oscillations are counted. Two-Speed Start-up

mode minimizes the delay in code execution by

operating from the internal oscillator as the OST is

counting. When the OST count reaches 1024 and the

OSTS bit of the OSCCON register is set, program

execution switches to the external oscillator.

3.6

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit of the OSCCON

register.

3.6.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit of the OSCCON

register selects the system clock source that is used for

the CPU and peripherals.

3.7.1

TWO-SPEED START-UP MODE

CONFIGURATION

• When the SCS bit of the OSCCON register = 0,

the system clock source is determined by

configuration of the FOSC<2:0> bits in the

Configuration Word register (CONFIG).

Two-Speed Start-up mode is configured by the

following settings:

• When the SCS bit of the OSCCON register = 1,

the system clock source is chosen by the internal

oscillator frequency selected by the IRCF<2:0>

bits of the OSCCON register. After a Reset, the

SCS bit of the OSCCON register is always

cleared.

• IESO (of the Configuration Word register) = 1;

Internal/External Switchover bit (Two-Speed

Start-up mode enabled).

• SCS (of the OSCCON register) = 0.

• FOSC<2:0> bits in the Configuration Word

register (CONFIG) configured for LP, XT or HS

mode.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or Fail-Safe

Clock Monitor, does not update the SCS bit

of the OSCCON register. The user can

monitor the OSTS bit of the OSCCON

register to determine the current system

clock source.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

Power-up Timer (PWRT) has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then

Two-Speed Start-up is disabled. This is because the

external clock oscillator does not require any

stabilization time after POR or an exit from Sleep.

3.6.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of

the OSCCON register indicates whether the system

clock is running from the external clock source, as

defined by the FOSC<2:0> bits in the Configuration

Word register (CONFIG), or from the internal clock

source. In particular, OSTS indicates that the Oscillator

Start-up Timer (OST) has timed out for LP, XT or HS

modes.

3.7.2

TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF<2:0>

bits of the OSCCON register.

3. OST enabled to count 1024 clock cycles.

3.7

Two-Speed Clock Start-up Mode

4. OST timed out, wait for falling edge of the

internal oscillator.

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit of the OSCCON register to

remain clear.

DS41211D-page 27

PIC12F683

3.7.3

CHECKING TWO-SPEED CLOCK

STATUS

Checking the state of the OSTS bit of the OSCCON

register will confirm if the microcontroller is running

from the external clock source, as defined by the

FOSC<2:0> bits in the Configuration Word register

(CONFIG), or the internal oscillator.

FIGURE 3-7:

TWO-SPEED START-UP

HFINTOSC

TOST

OSC1

0

1

1022 1023

OSC2

PC - N

PC + 1

Program Counter

PC

System Clock

DS41211D-page 28

PIC12F683

3.8.3

FAIL-SAFE CONDITION CLEARING

3.8

Fail-Safe Clock Monitor

The Fail-Safe condition is cleared after a Reset,

executing a SLEEPinstruction or toggling the SCS bit

of the OSCCON register. When the SCS bit is toggled,

the OST is restarted. While the OST is running, the

device continues to operate from the INTOSC selected

in OSCCON. When the OST times out, the Fail-Safe

condition is cleared and the device will be operating

from the external clock source. The Fail-Safe condition

must be cleared before the OSFIF flag can be cleared.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM can detect oscillator failure any time after

the Oscillator Start-up Timer (OST) has expired. The

FSCM is enabled by setting the FCMEN bit in the

Configuration Word register (CONFIG). The FSCM is

applicable to all external oscillator modes (LP, XT, HS,

EC, RC and RCIO).

FIGURE 3-8:

FSCM BLOCK DIAGRAM

3.8.4

RESET OR WAKE-UP FROM SLEEP

Clock Monitor

Latch

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC or

RC Clock modes so that the FSCM will be active as

soon as the Reset or wake-up has completed. When

the FSCM is enabled, the Two-Speed Start-up is also

enabled. Therefore, the device will always be executing

code while the OST is operating.

External

Clock

S

Q

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 μs)

488 Hz

(~2 ms)

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit of the OSCCON register to verify

the oscillator start-up and that the system

Sample Clock

Clock

Failure

Detected

3.8.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 3-8. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire

half-cycle of the sample clock elapses before the

primary clock goes low.

clock

completed.

switchover

has

successfully

3.8.2

FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the

device clock to an internal clock source and sets the bit

flag OSFIF of the PIR1 register. Setting this flag will

generate an interrupt if the OSFIE bit of the PIE1

register is also set. The device firmware can then take

steps to mitigate the problems that may arise from a

failed clock. The system clock will continue to be

sourced from the internal clock source until the device

firmware successfully restarts the external oscillator

and switches back to external operation.

The internal clock source chosen by the FSCM is

determined by the IRCF<2:0> bits of the OSCCON

register. This allows the internal oscillator to be

configured before a failure occurs.

DS41211D-page 29

PIC12F683

FIGURE 3-9:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

(1)

Resets

(2)

CONFIG

CPD

GIE

—

CP

PEIE

IRCF2

—

MCLRE

T0IE

WDTE

GPIE

OSTS

TUN3

CMIE

CMIF

FOSC2

T0IF

FOSC1

INTF

FOSC0

GPIF

—

PWRTE

INTE

IRCF0

TUN4

—

INTCON

OSCCON

OSCTUNE

PIE1

0000 0000 0000 000x

-110 x000 -110 x000

---0 0000 ---u uuuu

IRCF1

—

HTS

LTS

SCS

—

TUN2

TUN1

TUN0

EEIE

EEIF

ADIE

ADIF

CCP1IE

CCP1IF

OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

PIR1

—

Legend:

x= unknown, u= unchanged, –= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2: See Configuration Word register (Register 12-1) for operation of all register bits.

DS41211D-page 30

PIC12F683

Therefore, a write to a port implies that the port pins are

read, this value is modified and then written to the

PORT data latch. GP3 reads ‘0’ when MCLRE = 1.

4.0

GPIO PORT

There are as many as six general purpose I/O pins

available. Depending on which peripherals are

enabled, some or all of the pins may not be available as

general purpose I/O. In general, when a peripheral is

enabled, the associated pin may not be used as a

general purpose I/O pin.

The TRISIO register controls the direction of the GPIO

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISIO register

are maintained set when using them as analog inputs.

I/O pins configured as analog input always read ‘0’.

Note:

The ANSEL and CMCON0 registers must

be initialized to configure an analog

channel as a digital input. Pins configured

as analog inputs will read ‘0’.

4.1

GPIO and the TRISIO Registers

GPIO is

a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISIO.

Setting a TRISIO bit (= 1) will make the corresponding

GPIO pin an input (i.e., put the corresponding output

driver in a High-Impedance mode). Clearing a TRISIO

bit (= 0) will make the corresponding GPIO pin an

output (i.e., put the contents of the output latch on the

selected pin). An exception is GP3, which is input only

and its TRISIO bit will always read as ‘1’. Example 4-1

shows how to initialize GPIO.

EXAMPLE 4-1:

INITIALIZING GPIO

BANKSEL GPIO

CLRF

MOVLW

MOVWF

BANKSEL ANSEL

CLRF

MOVLW

MOVWF

;

GPIO

07h

CMCON0

;Init GPIO

;Set GP<2:0> to

;digital I/O

;

ANSEL

0Ch

TRISIO

;digital I/O

;Set GP<3:2> as inputs

;and set GP<5:4,1:0>

;as outputs

Reading the GPIO register reads the status of the pins,

whereas writing to it will write to the PORT latch. All

write operations are read-modify-write operations.

REGISTER 4-1:

GPIO: GENERAL PURPOSE I/O REGISTER

U-0

—

U-0

—

R/W-x

GP5

R/W-0

GP4

R-x

R/W-0

GP2

R/W-0

GP1

R/W-0

GP0

GP3

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

GP<5:0>: GPIO I/O Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

DS41211D-page 31

PIC12F683

REGISTER 4-2:

TRISIO GPIO TRI-STATE REGISTER

U-0

—

U-0

—

R/W-1

R-1

R/W-1

(2,3)

(2)

(1)

TRISIO5

TRISIO4

TRISIO3

TRISIO2

TRISIO1

TRISIO0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

bit 5:4

Unimplemented: Read as ‘0’

TRISIO<5:4>: GPIO Tri-State Control bit

1= GPIO pin configured as an input (tri-stated)

0= GPIO pin configured as an output

bit 3

TRISIO<3>: GPIO Tri-State Control bit

Input only

bit 2:0

TRISIO<2:0>: GPIO Tri-State Control bit

1= GPIO pin configured as an input (tri-stated)

0= GPIO pin configured as an output

Note 1: TRISIO<3> always reads ‘1’.

2: TRISIO<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

3: TRISIO<5> always reads ‘1’ in RC and RCIO and EC modes.

4.2.3

INTERRUPT-ON-CHANGE

4.2

Additional Pin Functions

Each of the GPIO pins is individually configurable as an

interrupt-on-change pin. Control bits IOCx enable or

disable the interrupt function for each pin. Refer to

Register 4-5. The interrupt-on-change is disabled on a

Power-on Reset.

Every GPIO pin on the PIC12F683 has an

interrupt-on-change option and a weak pull-up option.

GP0 has an Ultra Low-Power Wake-up option. The

next three sections describe these functions.

4.2.1

ANSEL REGISTER

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

GPIO. The ‘mismatch’ outputs of the last read are OR’d

together to set the GPIO Change Interrupt Flag bit

(GPIF) in the INTCON register (Register 2-3).

The ANSEL register is used to configure the Input

mode of an I/O pin to analog. Setting the appropriate

ANSEL bit high will cause all digital reads on the pin to

be read as ‘0’ and allow analog functions on the pin to

operate correctly.

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

The state of the ANSEL bits has no affect on digital

output functions. A pin with TRIS clear and ANSEL set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

a) Any read or write of GPIO. This will end the

mismatch condition, then,

b) Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor

Brown-out Reset. After these resets, the GPIF flag will

continue to be set if a mismatch is present.

4.2.2

WEAK PULL-UPS

Each of the GPIO pins, except GP3, has an individually

configurable internal weak pull-up. Control bits WPUx

enable or disable each pull-up. Refer to Register 4-4.

Each weak pull-up is automatically turned off when the

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the GPPU bit of the

OPTION register). A weak pull-up is automatically

enabled for GP3 when configured as MCLR and

disabled when GP3 is an I/O. There is no software

control of the MCLR pull-up.

Note:

If a change on the I/O pin should occur

when any GPIO operation is being

executed, then the GPIF interrupt flag may

not get set.

DS41211D-page 32

PIC12F683

REGISTER 4-3:

ANSEL: ANALOG SELECT REGISTER

U-0

—

R/W-0

R/W-1

ANS3

R/W-1

ANS2

R/W-1

ANS1

R/W-1

ANS0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100= FOSC/4

101= FOSC/16

110= FOSC/64

bit 3-0

ANS<3:0>: Analog Select bits

Analog select between analog or digital function on pins AN<3:0>, respectively.

(1)

1= Analog input. Pin is assigned as analog input

.

0= Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change,

if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on

the pin.

DS41211D-page 33

PIC12F683

REGISTER 4-4:

WPU: WEAK PULL-UP REGISTER

U-0

—

U-0

—

R/W-1

WPU5

R/W-1

WPU4

U-0

—

R/W-1

WPU2

R/W-1

WPU1

R/W-1

WPU0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

WPU<5:4>: Weak Pull-up Control bits

1= Pull-up enabled

0= Pull-up disabled

bit 3

Unimplemented: Read as ‘0’

bit 2-0

WPU<2:0>: Weak Pull-up Control bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).

3: The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.

4: WPU<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

REGISTER 4-5:

IOC: INTERRUPT-ON-CHANGE GPIO REGISTER

U-0

—

U-0

—

R/W-0

IOC5

R/W-0

IOC4

R/W-0

IOC3

R/W-0

IOC2

R/W-0

IOC1

R/W-0

IOC0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOC<5:0>: Interrupt-on-change GPIO Control bits

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.

2: IOC<5:4> always reads ‘0’ in XT, HS and LP OSC modes.

DS41211D-page 34

PIC12F683

4.2.4

ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on GP0

allows a slow falling voltage to generate an inter-

rupt-on-change on GP0 without excess current con-

sumption. The mode is selected by setting the

ULPWUE bit of the PCON register. This enables a

small current sink which can be used to discharge a

capacitor on GP0.

Note:

For more information, refer to the Applica-

tion Note AN879, “Using the Microchip

Ultra Low-Power Wake-up Module”

(DS00879).

EXAMPLE 4-2:

ULTRA LOW-POWER

WAKE-UP INITIALIZATION

To use this feature, the GP0 pin is configured to output

‘1’ to charge the capacitor, interrupt-on-change for GP0

is enabled and GP0 is configured as an input. The ULP-

WUE bit is set to begin the discharge and a SLEEP

instruction is performed. When the voltage on GP0

drops below VIL, an interrupt will be generated which will

cause the device to wake-up. Depending on the state of

the GIE bit of the INTCON register, the device will either

jump to the interrupt vector (0004h) or execute the next

instruction when the interrupt event occurs. See

BANKSEL CMCON0

;

MOVLW

MOVWF

H’7’

CMCON0

;Turn off

;comparators

;

;RA0 to digital I/O

;Output high to

;

;charge capacitor

;

BANKSEL ANSEL

BCF

ANSEL,0

TRISA,0

BANKSEL PORTA

BSF

CALL

PORTA,0

CapDelay

BANKSEL PCON

BSF

PCON,ULPWUE ;Enable ULP Wake-up

Section 4.2.3

“Interrupt-on-Change”

and

BSF

IOCA,0

;Select RA0 IOC

;RA0 to input

Section 12.4.3 “GPIO Interrupt” for more information.

BSF

TRISA,0

MOVLW

MOVWF

SLEEP

NOP

B’10001000’ ;Enable interrupt

This feature provides a low-power technique for period-

ically waking up the device from Sleep. The time-out is

dependent on the discharge time of the RC circuit

on GP0. See Example 4-2 for initializing the Ultra

Low-Power Wake-up module.

INTCON

; and clear flag

;Wait for IOC

;

The series resistor provides overcurrent protection for

the GP0 pin and can allow for software calibration of the

time-out (see Figure 4-1). A timer can be used to mea-

sure the charge time and discharge time of the capaci-

tor. The charge time can then be adjusted to provide the

desired interrupt delay. This technique will compensate

for the affects of temperature, voltage and component

accuracy. The Ultra Low-Power Wake-up peripheral

can also be configured as a simple Programmable

Low-Voltage Detect or temperature sensor.

DS41211D-page 35

PIC12F683

4.2.5

PIN DESCRIPTIONS AND

DIAGRAMS

4.2.5.1

GP0/AN0/CIN+/ICSPDAT/ULPWU

Figure 4-1 shows the diagram for this pin. The GP0 pin

is configurable to function as one of the following:

Each GPIO pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the comparator or the ADC, refer to the

appropriate section in this data sheet.

• a general purpose I/O

• an analog input for the ADC

• an analog input to the comparator

• In-Circuit Serial Programming™ data

• an analog input to the Ultra Low-Power Wake-up

FIGURE 4-1:

BLOCK DIAGRAM OF GP0

Analog

Input Mode⁽¹⁾

VDD

Data Bus

D

Q

Weak

CK

WR

WPU

GPPU

RD

WPU

VDD

D

Q

I/O pin

WR

CK

GPIO

VSS

-

+

VT

D

Q

WR

TRISIO

CK

IULP

0

1

RD

TRISIO

Analog

Input Mode⁽¹⁾

VSS

ULPWUE

RD

GPIO

D

Q

D

CK

WR

IOC

Q3

EN

RD

IOC

Q

EN

Interrupt-on-

Change

RD GPIO

To Comparator

To A/D Converter

Note 1: Comparator mode and ANSEL determines Analog Input mode.

DS41211D-page 36

PIC12F683

4.2.5.2

GP1/AN1/CIN-/VREF/ICSPCLK

4.2.5.3

GP2/AN2/T0CKI/INT/COUT/CCP1

Figure 4-2 shows the diagram for this pin. The GP1 pin

is configurable to function as one of the following:

Figure 4-3 shows the diagram for this pin. The GP2 pin

is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the ADC

• the clock input for Timer0

• a analog input to the comparator

• a voltage reference input for the ADC

• In-Circuit Serial Programming clock

• an external edge triggered interrupt

• a digital output from the Comparator

• a digital input/output for the CCP (refer to

Section 11.0 “Capture/Compare/PWM (CCP)

Module”).

FIGURE 4-2:

BLOCK DIAGRAM OF GP1

Analog

Data

Input Mode⁽¹⁾

Bus

FIGURE 4-3:

BLOCK DIAGRAM OF GP2

D

Q

VDD

WR

WPU

CK

Analog

Input Mode

Weak

Data

Bus

D

Q

VDD

GPPU

RD

WR

WPU

CK

WPU

Weak

GPPU

Analog

RD

WPU

VDD

D

Q

COUT

Input

WR

GPIO

CK

Enable

Mode

VDD

D

Q

I/O pin

WR

GPIO

D

Q

CK

COUT

1

0

WR

CK

VSS

Analog

TRISIO

I/O pin

D

Q

Input Mode⁽¹⁾

RD

WR

TRISIO

CK

VSS

Analog

Input Mode

RD

GPIO

RD

TRISIO

D

Q

D

CK

WR

IOC

RD

GPIO

EN

Q3

D

Q

RD

IOC

Q

D

WR

IOC

D

CK

EN

Q3

EN

Interrupt-on-

change

RD

IOC

D

RD GPIO

EN

Interrupt-on-

change

To Comparator

To A/D Converter

RD GPIO

Note 1: Comparator mode and ANSEL determines Analog

To Timer0

Input mode.

To INT

To A/D Converter

Note 1: Comparator mode and ANSEL determines Analog

Input mode.

DS41211D-page 37

PIC12F683

4.2.5.4

GP3/MCLR/VPP

4.2.5.5

GP4/AN3/T1G/OSC2/CLKOUT

Figure 4-4 shows the diagram for this pin. The GP3 pin

is configurable to function as one of the following:

Figure 4-5 shows the diagram for this pin. The GP4 pin

is configurable to function as one of the following:

• a general purpose input

• a general purpose I/O

• an analog input for the ADC

• a Timer1 gate input

• as Master Clear Reset with weak pull-up

FIGURE 4-4:

BLOCK DIAGRAM OF GP3

• a crystal/resonator connection

• a clock output

VDD

MCLRE

Weak

FIGURE 4-5:

BLOCK DIAGRAM OF GP4

Data

Bus

Analog

Input Mode

MCLRE

Reset

CLK⁽¹⁾

Input

Data

Modes

VDD

Bus

RD

TRISIO

VSS

D

Q

MCLRE

VSS

WR

WPU

CK

Weak

RD

GPIO

D

Q

GPPU

RD

WPU

Q

D

Oscillator

Circuit

WR

IOC

CK

OSC1

Q3

EN

VDD

CLKOUT

Enable

RD

IOC

D

FOSC/4

1

0

D

Q

EN

Interrupt-on-

change

I/O pin

WR

GPIO

CK

CLKOUT

Enable

RD GPIO

VSS

D

Q

INTOSC/

RC/EC⁽²⁾

WR

TRISIO

CK

CLKOUT

Enable

RD

TRISIO

Analog

Input Mode

RD

GPIO

D

Q

D

CK

WR

IOC

EN

Q3

RD

IOC

Q

EN

Interrupt-on-

change

RD GPIO

To T1G

To A/D Converter

Note 1: CLK modes are XT, HS, LP, optional LP oscillator and

CLKOUT Enable.

2: With CLKOUT option.

DS41211D-page 38

PIC12F683

4.2.5.6

GP5/T1CKI/OSC1/CLKIN

FIGURE 4-6:

BLOCK DIAGRAM OF GP5

INTOSC

Mode

Figure 4-6 shows the diagram for this pin. The GP5 pin

is configurable to function as one of the following:

TMR1LPEN⁽¹⁾

VDD

Data

Bus

• a general purpose I/O

• a Timer1 clock input

• a crystal/resonator connection

• a clock input

D

Q

WR

WPU

CK

Weak

GPPU

RD

WPU

Oscillator

Circuit

OSC2

VDD

D

Q

WR

GPIO

CK

I/O pin

D

Q

WR

TRISIO

CK

VSS

INTOSC

Mode

RD

TRISIO

(1)

RD

GPIO

D

Q

D

CK

WR

IOC

EN

Q3

RD

IOC

D

EN

Interrupt-on-

change

RD GPIO

To Timer1 or CLKGEN

Note 1: Timer1 LP oscillator enabled.

2: When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

TABLE 4-1:

SUMMARY OF REGISTERS ASSOCIATED WITH GPIO

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ANSEL

—

ADCS2

—

ADCS1

DC1B1

—

ADCS0

DC1B0

CINV

ANS3

ANS2

ANS1

ANS0

-000 1111

--00 0000

-0-0 0000

--01 --qq

0000 0000

--00 0000

1111 1111

--xx xxxx

-000 1111

--00 0000

-0-0 0000

--0u --uu

0000 000x

--00 0000

1111 1111

--x0 x000

CCP1CON

CMCON0

PCON

CCP1M3 CCP1M2 CCP1M1 CCP1M0

—

COUT

—

CIS

—

CM2

—

CM1

POR

INTF

IOC1

PS1

CM0

BOR

GPIF

IOC0

PS0

—

ULPWUE SBOREN

INTCON

IOC

GIE

—

PEIE

—

T0IE

IOC5

T0CS

GP5

INTE

IOC4

T0SE

GP4

GPIE

IOC3

PSA

GP3

T0IF

IOC2

PS2

GP2

OPTION_REG

GPIO

GPPU

—

INTEDG

—

GP1

GP0

T1CON

TRISIO

WPU

T1GINV

—

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

0000 0000

--11 1111

--11 -111

0000 0000

--11 1111

--11 -111

—

TRISIO5 TRISIO4

WPU5 WPU4

TRISIO3

—

TRISIO2 TRISIO1 TRISIO0

WPU2 WPU1 WPU0

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by GPIO.

DS41211D-page 39

PIC12F683

NOTES:

DS41211D-page 40

PIC12F683

5.1

Timer0 Operation

5.0

TIMER0 MODULE

When used as a timer, the Timer0 module can be used

as either an 8-bit timer or an 8-bit counter.

The Timer0 module is an 8-bit timer/counter with the

following features:

• 8-bit timer/counter register (TMR0)

5.1.1

8-BIT TIMER MODE

• 8-bit prescaler (shared with Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

When used as a timer, the Timer0 module will

increment every instruction cycle (without prescaler).

Timer mode is selected by clearing the T0CS bit of the

OPTION register to ‘0’.

Figure 5-1 is a block diagram of the Timer0 module.

When TMR0 is written, the increment is inhibited for

two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can

be adjusted, in order to account for the two

instruction cycle delay when TMR0 is

written.

5.1.2

8-BIT COUNTER MODE

When used as a counter, the Timer0 module will

increment on every rising or falling edge of the T0CKI

pin. The incrementing edge is determined by the T0SE

bit of the OPTION register. Counter mode is selected by

setting the T0CS bit of the OPTION register to ‘1’.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4

Data Bus

0

1

8

1

Sync

TMR0

2 Tcy

T0CKI

0

1

Set Flag bit T0IF

on Overflow

T0CS

T0SE

8-bit

Prescaler

PSA

8

PSA

WDTE

SWDTEN

1

PS<2:0>

WDT

Time-out

16-bit

Prescaler

0

16

31 kHz

INTOSC

Watchdog

Timer

PSA

WDTPS<3:0>

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.

2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.

3: WDTE bit is in the Configuration Word register.

DS41211D-page 41

PIC12F683

When changing the prescaler assignment from the

WDT to the Timer0 module, the following instruction

sequence must be executed (see Example 5-2).

5.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A single software programmable prescaler is available

for use with either Timer0 or the Watchdog Timer

(WDT), but not both simultaneously. The prescaler

assignment is controlled by the PSA bit of the OPTION

register. To assign the prescaler to Timer0, the PSA bit

must be cleared to a ‘0’.

EXAMPLE 5-2:

CHANGING PRESCALER

(WDT → TIMER0)

CLRWDT

;Clear WDT and

;prescaler

;

BANKSEL OPTION_REG

There are 8 prescaler options for the Timer0 module

ranging from 1:2 to 1:256. The prescale values are

selectable via the PS<2:0> bits of the OPTION register.

In order to have a 1:1 prescaler value for the Timer0

module, the prescaler must be assigned to the WDT

module.

MOVLW

ANDWF

IORLW

MOVWF

b’11110000’ ;Mask TMR0 select and

OPTION_REG,W ;prescaler bits

b’00000011’ ;Set prescale to 1:16

OPTION_REG

;

5.1.4

TIMER0 INTERRUPT

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing to

the TMR0 register will clear the prescaler.

Timer0 will generate an interrupt when the TMR0

register overflows from FFh to 00h. The T0IF interrupt

flag bit of the INTCON register is set every time the

TMR0 register overflows, regardless of whether or not

the Timer0 interrupt is enabled. The T0IF bit must be

cleared in software. The Timer0 interrupt enable is the

T0IE bit of the INTCON register.

When the prescaler is assigned to WDT, a CLRWDT

instruction will clear the prescaler along with the WDT.

5.1.3.1

Switching Prescaler Between

Timer0 and WDT Modules

Note:

The Timer0 interrupt cannot wake the

processor from Sleep since the timer is

frozen during Sleep.

As a result of having the prescaler assigned to either

Timer0 or the WDT, it is possible to generate an

unintended device Reset when switching prescaler

values. When changing the prescaler assignment from

Timer0 to the WDT module, the instruction sequence

shown in Example 5-1, must be executed.

5.1.5

USING TIMER0 WITH AN

EXTERNAL CLOCK

When Timer0 is in Counter mode, the synchronization

of the T0CKI input and the Timer0 register is accom-

plished by sampling the prescaler output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, the

high and low periods of the external clock source must

meet the timing requirements as shown in the

Section 15.0 “Electrical Specifications”.

EXAMPLE 5-1:

CHANGING PRESCALER

(TIMER0 → WDT)

BANKSEL TMR0

CLRWDT

;

;Clear WDT

;Clear TMR0 and

;prescaler

CLRF

TMR0

BANKSEL OPTION_REG

;

BSF

OPTION_REG,PSA ;Select WDT

CLRWDT

;

MOVLW

ANDWF

IORLW

MOVWF

b’11111000’

OPTION_REG,W

b’00000101’

OPTION_REG

;Mask prescaler

;bits

;Set WDT prescaler

;to 1:32

DS41211D-page 42

PIC12F683

REGISTER 5-1:

OPTION_REG: OPTION REGISTER

R/W-1

GPPU

bit 7

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

GPPU: GPIO Pull-up Enable bit

1= GPIO pull-ups are disabled

0= GPIO pull-ups are enabled by individual PORT latch values in WPU register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

T0CS: Timer0 Clock Source Select bit

1= Transition on T0CKI pin

0= Internal instruction cycle clock (FOSC/4)

T0SE: Timer0 Source Edge Select bit

1= Increment on high-to-low transition on T0CKI pin

0= Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

BIT VALUE TIMER0 RATE WDT RATE

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 1

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 12.6 “Watchdog Timer (WDT)” for more

information.

TABLE 5-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

0000 0000 0000 000x

1111 1111 1111 1111

INTCON

OPTION_REG

TRISIO

GIE

PEIE

T0IE

INTE

T0SE

GPIE

PSA

T0IF

PS2

INTF

PS1

GPIF

PS0

GPPU INTEDG

T0CS

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

Legend:

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0

module.

DS41211D-page 43

PIC12F683

6.1

Timer1 Operation

6.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit incrementing counter

which is accessed through the TMR1H:TMR1L register

pair. Writes to TMR1H or TMR1L directly update the

counter.

The Timer1 module is a 16-bit timer/counter with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 3-bit prescaler

When used with an internal clock source, the module is

a timer. When used with an external clock source, the

module can be used as either a timer or counter.

• Optional LP oscillator

• Synchronous or asynchronous operation

6.2

Clock Source Selection

• Timer1 gate (count enable) via comparator or

T1G pin

The TMR1CS bit of the T1CON register is used to select

the clock source. When TMR1CS = 0, the clock source

is FOSC/4. When TMR1CS = 1, the clock source is

supplied externally.

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

Clock Source

TMR1CS

• Special Event Trigger (with CCP)

• Comparator output synchronization to Timer1

clock

FOSC/4

0

1

T1CKI pin

Figure 6-1 is a block diagram of the Timer1 module.

FIGURE 6-1:

TIMER1 BLOCK DIAGRAM

TMR1GE

T1GINV

TMR1ON

Set flag bit

To Comparator Module

Timer1 Clock

TMR1IF on

Overflow

(2)

TMR1

TMR1H

Synchronized

clock input

0

EN

TMR1L

1

Oscillator

(1)

T1SYNC

OSC1/T1CKI

1

(3)

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

OSC2/T1G

2

T1CKPS<1:0>

TMR1CS

1

0

INTOSC

Without CLKOUT

COUT

T1OSCEN

T1GSS

Note 1: ST Buffer is low power type when using LP oscillator, or high speed type when using T1CKI.

2: Timer1 register increments on rising edge.

3: Synchronize does not operate while in Sleep.

DS41211D-page 44

PIC12F683

6.2.1

INTERNAL CLOCK SOURCE

6.5

Timer1 Operation in

Asynchronous Counter Mode

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples

of TCY as determined by the Timer1 prescaler.

If control bit T1SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

continues to increment asynchronous to the internal

phase clocks. The timer will continue to run during

Sleep and can generate an interrupt on overflow,

which will wake-up the processor. However, special

precautions in software are needed to read/write the

timer (see Section 6.5.1 “Reading and Writing

Timer1 in Asynchronous Counter Mode”).

6.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1

module may work as a timer or a counter.

When counting, Timer1 is incremented on the rising

edge of the external clock input T1CKI. In addition, the

Counter mode clock can be synchronized to the

microcontroller system clock or run asynchronously.

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce a single spurious

increment.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKOUT),

Timer1 can use the LP oscillator as a clock source.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge.

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

6.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TTMR1L register

pair.

6.4

Timer1 Oscillator

A low-power 32.768 kHz crystal oscillator is built-in

between pins OSC1 (input) and OSC2 (amplifier

output). The oscillator is enabled by setting the

T1OSCEN control bit of the T1CON register. The

oscillator will continue to run during Sleep.

6.6

Timer1 Gate

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is derived from the internal

oscillator or when in LP oscillator mode. The user must

provide a software time delay to ensure proper oscilla-

tor start-up.

Timer1 gate source is software configurable to be the

T1G pin or the output of the Comparator. This allows the

device to directly time external events using T1G or

analog events using Comparator 2. See the CMCON1

register (Register 8-2) for selecting the Timer1 gate

source. This feature can simplify the software for a

Delta-Sigma A/D converter and many other applications.

For more information on Delta-Sigma A/D converters,

see the Microchip web site (www.microchip.com).

TRISIO<5:4> bits are set when the Timer1 oscillator is

enabled. GP5 and GP4 bits read as ‘0’ and TRISIO5

and TRISIO4 bits read as ‘1’.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Note:

TMR1GE bit of the T1CON register must

be set to use either T1G or COUT as the

Timer1 gate source. See Register 8-2 for

more information on selecting the Timer1

gate source.

Timer1 gate can be inverted using the T1GINV bit of

the T1CON register, whether it originates from the T1G

pin or Comparator 2 output. This configures Timer1 to

measure either the active-high or active-low time

between events.

DS41211D-page 45

PIC12F683

6.7

Timer1 Interrupt

6.9

CCP Special Event Trigger

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit of the PIR1 register is

set. To enable the interrupt on rollover, you must set

these bits:

If a CCP is configured to trigger a special event, the

trigger will clear the TMR1H:TMR1L register pair. This

special event does not cause a Timer1 interrupt. The

CCP module may still be configured to generate a CCP

interrupt.

• Timer1 interrupt enable bit of the PIE1 register

• PEIE bit of the INTCON register

In this mode of operation, the CCPR1H:CCPR1L regis-

ter pair effectively becomes the period register for

Timer1.

• GIE bit of the INTCON register

Timer1 should be synchronized to the FOSC to utilize

the Special Event Trigger. Asynchronous operation of

Timer1 can cause a Special Event Trigger to be

missed.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

In the event that a write to TMR1H or TMR1L coincides

with a Special Event Trigger from the CCP, the write will

take precedence.

6.8

Timer1 Operation During Sleep

For more information, see Section on CCP.

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

6.10 Comparator Synchronization

The same clock used to increment Timer1 can also be

used to synchronize the comparator output. This

feature is enabled in the Comparator module.

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

When using the comparator for Timer1 gate, the

comparator output should be synchronized to Timer1.

This ensures Timer1 does not miss an increment if the

comparator changes.

The device will wake-up on an overflow and execute

the next instruction. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine (0004h).

For more information, see Section 8.0 “Comparator

Module”.

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of

the clock.

DS41211D-page 46

PIC12F683

6.11 Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 6-1, is used to control Timer1 and select the

various features of the Timer1 module.

REGISTER 6-1:

T1CON: TIMER1 CONTROL REGISTER

R/W-0

T1GINV⁽¹⁾

R/W-0

TMR1GE⁽²⁾

R/W-0

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC

TMR1CS

TMR1ON

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

T1GINV: Timer1 Gate Invert bit⁽¹⁾

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

TMR1GE: Timer1 Gate Enable bit⁽²⁾

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 is on if Timer1 gate is not active

0= Timer1 is on

bit 5-4

bit 3

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKOUT oscillator is active:

1= LP oscillator is enabled for Timer1 clock

0= LP oscillator is off

Else:

This bit is ignored. LP oscillator is disabled.

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from T1CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G pin or COUT, as selected by the T1GSS bit of the CMCON1

register, as a Timer1 gate source.

DS41211D-page 47

PIC12F683

TABLE 6-1:

SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

CONFIG

CPD

CP

MCLRE

WDTE

FOSC2

FOSC1

FOSC0

—

PWRTE

CMCON1

INTCON

PIE1

—

INTE

—

T1GSS

INTF

CMSYNC

GPIF

---- --10

0000 0000

000- 0000

xxxx xxxx

0000 0000

---- --10

0000 000x

000- 0000

uuuu uuuu

GIE

PEIE

ADIE

ADIF

T0IE

GPIE

CMIE

CMIF

T0IF

EEIE

EEIF

CCP1IE

CCP1IF

OSFIE

OSFIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

TMR1H

TMR1L

T1CON

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

T1GINV

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

TMR1ON

Legend:

x= unknown, u= unchanged, –= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Note 1:

See Configuration Word register (Register 12-1) for operation of all register bits.

DS41211D-page 48

PIC12F683

The TMR2 and PR2 registers are both fully readable

and writable. On any Reset, the TMR2 register is set to

00h and the PR2 register is set to FFh.

7.0

TIMER2 MODULE

The Timer2 module is an 8-bit timer with the following

features:

Timer2 is turned on by setting the TMR2ON bit in the

T2CON register to a ‘1’. Timer2 is turned off by clearing

the TMR2ON bit to a ‘0’.

• 8-bit timer register (TMR2)

• 8-bit period register (PR2)

• Interrupt on TMR2 match with PR2

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

The Timer2 prescaler is controlled by the T2CKPS bits

in the T2CON register. The Timer2 postscaler is

controlled by the TOUTPS bits in the T2CON register.

The prescaler and postscaler counters are cleared

when:

See Figure 7-1 for a block diagram of Timer2.

• A write to TMR2 occurs.

• A write to T2CON occurs.

7.1

Timer2 Operation

The clock input to the Timer2 module is the system

instruction clock (FOSC/4). The clock is fed into the

Timer2 prescaler, which has prescale options of 1:1,

1:4 or 1:16. The output of the prescaler is then used to

increment the TMR2 register.

• Any device Reset occurs (Power-on Reset, MCLR

Reset, Watchdog Timer Reset, or Brown-out

Reset).

Note:

TMR2 is not cleared when T2CON is

written.

The values of TMR2 and PR2 are constantly compared

to determine when they match. TMR2 will increment

from 00h until it matches the value in PR2. When a

match occurs, two things happen:

• TMR2 is reset to 00h on the next increment cycle.

• The Timer2 postscaler is incremented

The match output of the Timer2/PR2 comparator is

then fed into the Timer2 postscaler. The postscaler has

postscale options of 1:1 to 1:16 inclusive. The output of

the Timer2 postscaler is used to set the TMR2IF

interrupt flag bit in the PIR1 register.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

DS41211D-page 49

PIC12F683

REGISTER 7-1:

T2CON: TIMER 2 CONTROL REGISTER

U-0

—

R/W-0

TOUTPS3

TOUTPS2

TOUTPS1

TOUTPS0

TMR2ON

T2CKPS1

T2CKPS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7

Unimplemented: Read as ‘0’

bit 6-3

TOUTPS<3:0>: Timer2 Output Postscaler Select bits

0000= 1:1 Postscaler

0001= 1:2 Postscaler

0010= 1:3 Postscaler

0011= 1:4 Postscaler

0100= 1:5 Postscaler

0101= 1:6 Postscaler

0110= 1:7 Postscaler

0111= 1:8 Postscaler

1000= 1:9 Postscaler

1001= 1:10 Postscaler

1010= 1:11 Postscaler

1011= 1:12 Postscaler

1100= 1:13 Postscaler

1101= 1:14 Postscaler

1110= 1:15 Postscaler

1111= 1:16 Postscaler

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0

T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

TABLE 7-1:

SUMMARY OF ASSOCIATED TIMER2 REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE1

GIE

EEIE

EEIF

PEIE

ADIE

ADIF

T0IE

INTE

—

GPIE

CMIE

CMIF

T0IF

INTF

GPIF

0000 0000

000- 0000

1111 1111

0000 0000

-000 0000

0000 000x

000- 0000

1111 1111

0000 0000

-000 0000

CCP1IE

CCP1IF

OSFIE

OSFIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Module Period Register

Holding Register for the 8-bit TMR2 Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

TMR2

T2CON

Legend:

—

TMR2ON

T2CKPS1

T2CKPS0

x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

DS41211D-page 50

PIC12F683

FIGURE 8-1:

SINGLE COMPARATOR

8.0

COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

The comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of the program execution. The analog

comparator module includes the following features:

VIN+

VIN-

+

Output

–

VIN-

VIN+

• Multiple comparator configurations

• Comparator output is available internally/externally

• Programmable output polarity

• Interrupt-on-change

• Wake-up from Sleep

Output

• Timer1 gate (count enable)

• Output synchronization to Timer1 clock input

• Programmable voltage reference

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

8.1

Comparator Overview

The comparator is shown in Figure 8-1 along with the

relationship between the analog input levels and the

digital output. When the analog voltage at VIN+ is less

than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

FIGURE 8-2:

COMPARATOR OUTPUT BLOCK DIAGRAM

CMSYNC

To Timer1 Gate

CINV

0

To COUT pin

1

D

Q

Timer1

clock source

(1)

To Data Bus

D

Q

Q1

EN

RD CMCON0

Set CMIF bit

D

Q3*RD CMCON0

EN

CL

Reset

Note 1: Comparator output is latched on falling edge of Timer1 clock source.

2: Q1 and Q3 are phases of the four-phase system clock (FOSC).

3: Q1 is held high during Sleep mode.

DS41211D-page 51

PIC12F683

8.2

Analog Input Connection

Considerations

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

A simplified circuit for an analog input is shown in

Figure 8-3. Since the analog input pins share their con-

nection with a digital input, they have reverse biased

ESD protection diodes to VDD and VSS. The analog

input, therefore, must be between VSS and VDD. If the

input voltage deviates from this range by more than

0.6V in either direction, one of the diodes is forward

biased and a latch-up may occur.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

A maximum source impedance of 10 kΩ is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

FIGURE 8-3:

ANALOG INPUT MODEL

VDD

VT ≈ 0.6V

RIC

Rs < 10K

To ADC Input

AIN

ILEAKAGE

±500 nA

CPIN

5 pF

VA

VT ≈ 0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

DS41211D-page 52

PIC12F683

The port pins denoted as “A” will read as a ‘0’

regardless of the state of the I/O pin or the I/O control

TRIS bit. Pins used as analog inputs should also have

the corresponding TRIS bit set to ‘1’ to disable the

digital output driver. Pins denoted as “D” should have

the corresponding TRIS bit set to ‘0’ to enable the

digital output driver.

8.3

Comparator Configuration

There are eight modes of operation for the comparator.

The CM<2:0> bits of the CMCON0 register are used to

select these modes as shown in Figure 8-4.

• Analog function (A): digital input buffer is disabled

• Digital function (D): comparator digital output,

overrides port function

Note:

Comparator interrupts should be disabled

during a Comparator mode change to

prevent unintended interrupts.

• Normal port function (I/O): independent of com-

parator

FIGURE 8-4:

COMPARATOR I/O OPERATING MODES

Comparator Reset (POR Default Value – low power)

Comparator w/o Output and with Internal Reference

CM<2:0> = 000

CM<2:0> = 100

A

CIN-

CIN+

A

CIN-

(1)

COUT

Off

I/O

CIN+

I/O

COUT (pin)

I/O

COUT (pin)

From CVREF Module

Comparator with Output

Multiplexed Input with Internal Reference and Output

CM<2:0> = 001

CM<2:0> = 101

A

CIN-

A

CIN-

CIS = 0

A

COUT

CIS = 1

CIN+

A

COUT

CIN+

D

COUT (pin)

D

COUT (pin)

From CVREF Module

Comparator without Output

Multiplexed Input with Internal Reference

CM<2:0> = 010

CM<2:0> = 110

A

CIN-

CIS = 0

A

COUT

CIS = 1

COUT

A

CIN+

I/O

COUT (pin)

I/O

COUT (pin)

From CVREF Module

Comparator with Output and Internal Reference

Comparator Off (Lowest power)

CM<2:0> = 011

CM<2:0> = 111

A

CIN-

I/O

CIN-

COUT

I/O

(1)

Off

CIN+

D

COUT (pin)

I/O

COUT (pin)

From CVREF Module

Legend: A = Analog Input, ports always reads ‘0’

CIS = Comparator Input Switch (CMCON0<3>)

D = Comparator Digital Output

I/O = Normal port I/O

Note 1: Reads as ‘0’, unless CINV = 1.

DS41211D-page 53

PIC12F683

8.4

Comparator Control

8.5

Comparator Response Time

The CMCON0 register (Register 8-1) provides access

to the following comparator features:

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the

comparator differs from the settling time of the voltage

reference. Therefore, both of these times must be

considered when determining the total response time

to a comparator input change. See the Comparator and

Voltage Reference Specifications in Section 15.0

“Electrical Specifications” for more details.

• Mode selection

• Output state

• Output polarity

• Input switch

8.4.1

COMPARATOR OUTPUT STATE

The Comparator state can always be read internally via

the COUT bit of the CMCON0 register. The comparator

state may also be directed to the COUT pin in the

following modes:

• CM<2:0> = 001

• CM<2:0> = 011

• CM<2:0> = 101

When one of the above modes is selected, the associ-

ated TRIS bit of the COUT pin must be cleared.

8.4.2

COMPARATOR OUTPUT POLARITY

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CINV bit of the CMCON0 register. Clearing

CINV results in a non-inverted output. A complete table

showing the output state versus input conditions and

the polarity bit is shown in Table 8-1.

TABLE 8-1:

OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions

CINV

COUT

VIN- > VIN+

VIN- < VIN+

VIN- > VIN+

VIN- < VIN+

0

1

0

1

0

Note:

COUT refers to both the register bit and

output pin.

8.4.3

COMPARATOR INPUT SWITCH

The inverting input of the comparator may be switched

between two analog pins in the following modes:

• CM<2:0> = 101

• CM<2:0> = 110

In the above modes, both pins remain in analog mode

regardless of which pin is selected as the input. The

CIS bit of the CMCON0 register controls the comparator

input switch.

DS41211D-page 54

PIC12F683

FIGURE 8-5:

COMPARATOR

8.6

Comparator Interrupt Operation

INTERRUPT TIMING W/O

CMCON0 READ

The comparator interrupt flag is set whenever there is

a change in the output value of the comparator.

Changes are recognized by means of a mismatch cir-

cuit which consists of two latches and an exclusive-or

gate (see Figure 8.2). One latch is updated with the

comparator output level when the CMCON0 register is

read. This latch retains the value until the next read of

the CMCON0 register or the occurrence of a Reset.

The other latch of the mismatch circuit is updated on

every Q1 system clock. A mismatch condition will occur

when a comparator output change is clocked through

the second latch on the Q1 clock cycle. The mismatch

condition will persist, holding the CMIF bit of the PIR1

register true, until either the CMCON0 register is read

or the comparator output returns to the previous state.

Q1

Q3

CIN+

TRT

COUT

Set CMIF (level)

CMIF

reset by software

FIGURE 8-6:

COMPARATOR

INTERRUPT TIMING WITH

CMCON0 READ

Q1

Note:

A write operation to the CMCON0 register

will also clear the mismatch condition

Q3

CIN+

TRT

because all writes include

a

read

operation at the beginning of the write

cycle.

COUT

Set CMIF (level)

CMIF

Software will need to maintain information about the

status of the comparator output to determine the actual

change that has occurred.

cleared by CMCON0 read

reset by software

The CMIF bit of the PIR1 register, is the comparator

interrupt flag. This bit must be reset in software by

clearing it to ‘0’. Since it is also possible to write a ‘1’ to

this register, a simulated interrupt may be initiated.

Note 1: If a change in the CMCON0 register

(COUT) should occur when a read opera-

tion is being executed (start of the Q2

cycle), then the CMIF of the PIR1 register

interrupt flag may not get set.

The CMIE bit of the PIE1 register and the PEIE and GIE

bits of the INTCON register must all be set to enable

comparator interrupts. If any of these bits are cleared,

the interrupt is not enabled, although the CMIF bit of

the PIR1 register will still be set if an interrupt condition

occurs.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is

stable. Allow about 1 μs for bias settling

then clear the mismatch condition and

interrupt flags before enabling comparator

interrupts.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

a) Any read or write of CMCON0. This will end the

mismatch condition.

b) Clear the CMIF interrupt flag.

A persistent mismatch condition will preclude clearing

the CMIF interrupt flag. Reading CMCON0 will end the

mismatch condition and allow the CMIF bit to be

cleared.

Note:

If a change in the CMCON0 register

(COUT) should occur when read

a

operation is being executed (start of the

Q2 cycle), then the CMIF interrupt flag

may not get set.

DS41211D-page 55

PIC12F683

8.7

Operation During Sleep

8.8

Effects of a Reset

The comparator, if enabled before entering Sleep mode,

remains active during Sleep. The additional current

consumed by the comparator is shown separately in

Section 15.0 “Electrical Specifications”. If the

comparator is not used to wake the device, power

consumption can be minimized while in Sleep mode by

turning off the comparator. The comparator is turned off

by selecting mode CM<2:0> = 000or CM<2:0> = 111

of the CMCON0 register.

A device Reset forces the CMCON0 and CMCON1

registers to their Reset states. This forces the Compar-

ator module to be in the Comparator Reset mode

(CM<2:0> = 000). Thus, all comparator inputs are

analog inputs with the comparator disabled to consume

the smallest current possible.

A change to the comparator output can wake-up the

device from Sleep. To enable the comparator to wake

the device from Sleep, the CMIE bit of the PIE1 register

and the PEIE bit of the INTCON register must be set.

The instruction following the Sleep instruction always

executes following a wake from Sleep. If the GIE bit of

the INTCON register is also set, the device will then

execute the Interrupt Service Routine.

REGISTER 8-1:

CMCON0: COMPARATOR CONFIGURATION REGISTER

U-0

—

R-0

U-0

—

R/W-0

CINV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

COUT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

bit 6

Unimplemented: Read as ‘0’

COUT: Comparator Output bit

When CINV = 0:

1= VIN+ > VIN-

0= VIN+ < VIN-

When CINV = 1:

1= VIN+ < VIN-

0= VIN+ > VIN-

bit 5

bit 4

Unimplemented: Read as ‘0’

CINV: Comparator Output Inversion bit

1= Output inverted

0= Output not inverted

bit 3

CIS: Comparator Input Switch bit

When CM<2:0> = 110or 101:

1= CIN+ connects to VIN-

0= CIN- connects to VIN-

When CM<2:0> = 0xxor 100or 111:

CIS has no effect.

bit 2-0

CM<2:0>: Comparator Mode bits (See Figure 8-5)

000= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output turned off

001= CIN pins are configured as analog, COUT pin configured as Comparator output

010= CIN pins are configured as analog, COUT pin configured as I/O, Comparator output available internally

011= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin configured as

Comparator output, CVREF is non-inverting input

100= CIN- pin is configured as analog, CIN+ pin is configured as I/O, COUT pin is configured as I/O, Comparator output

available internally, CVREF is non-inverting input

101= CIN pins are configured as analog and multiplexed, COUT pin is configured as

Comparator output, CVREF is non-inverting input

110= CIN pins are configured as analog and multiplexed, COUT pin is configured as I/O,

Comparator output available internally, CVREF is non-inverting input

111= CIN pins are configured as I/O, COUT pin is configured as I/O, Comparator output disabled, Comparator off.

DS41211D-page 56

PIC12F683

8.9

Comparator Gating Timer1

8.10 Synchronizing Comparator Output

to Timer1

This feature can be used to time the duration or interval

of analog events. Clearing the T1GSS bit of the

CMCON1 register will enable Timer1 to increment

based on the output of the comparator. This requires

that Timer1 is on and gating is enabled. See

Section 6.0 “Timer1 Module with Gate Control” for

details.

The comparator output can be synchronized with

Timer1 by setting the CMSYNC bit of the CMCON1

register. When enabled, the comparator output is

latched on the falling edge of the Timer1 clock source.

If a prescaler is used with Timer1, the comparator

output is latched after the prescaling function. To

prevent a race condition, the comparator output is

latched on the falling edge of the Timer1 clock source

and Timer1 increments on the rising edge of its clock

source. See the Comparator Block Diagram (Figure 8-

2) and the Timer1 Block Diagram (Figure 6-1) for more

information.

It is recommended to synchronize the comparator with

Timer1 by setting the CMSYNC bit when the

comparator is used as the Timer1 gate source. This

ensures Timer1 does not miss an increment if the

comparator changes during an increment.

REGISTER 8-2:

CMCON1: COMPARATOR CONFIGURATION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

T1GSS

CMSYNC

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1

Unimplemented: Read as ‘0’

T1GSS: Timer1 Gate Source Select bit⁽¹⁾

1= Timer 1 Gate Source is T1G pin (pin should be configured as digital input)

0= Timer 1 Gate Source is comparator output

bit 0

CMSYNC: Comparator Output Synchronization bit⁽²⁾

1= Output is synchronized with falling edge of Timer1 clock

0= Output is asynchronous

Note 1: Refer to Section 6.6 “Timer1 Gate”.

2: Refer to Figure 8-2.

DS41211D-page 57

PIC12F683

EQUATION 8-1:

CVREF OUTPUT VOLTAGE

VRR = 1 (low range):

CVREF = (VR<3:0>/24) × VDD

VRR = 0 (high range):

CVREF = (VDD/4) +

8.11 Comparator Voltage Reference

The Comparator Voltage Reference module provides

an internally generated voltage reference for the

comparators. The following features are available:

• Independent from Comparator operation

• Two 16-level voltage ranges

• Output clamped to VSS

(VR<3:0> × VDD/32)

The full range of VSS to VDD cannot be realized due to

the construction of the module. See Figure 8-1.

• Ratiometric with VDD

The VRCON register (Register 8-3) controls the

Voltage Reference module shown in Figure 8-7.

8.11.3

OUTPUT CLAMPED TO VSS

The CVREF output voltage can be set to Vss with no

power consumption by configuring VRCON as follows:

8.11.1

INDEPENDENT OPERATION

• VREN = 0

The comparator voltage reference is independent of

the comparator configuration. Setting the VREN bit of

the VRCON register will enable the voltage reference.

• VRR = 1

• VR<3:0> = 0000

This allows the comparator to detect a zero-crossing

while not consuming additional CVREF module current.

8.11.2

OUTPUT VOLTAGE SELECTION

The CVREF voltage reference has 2 ranges with 16

voltage levels in each range. Range selection is

controlled by the VRR bit of the VRCON register. The

16 levels are set with the VR<3:0> bits of the VRCON

register.

8.11.4

OUTPUT RATIOMETRIC TO VDD

The comparator voltage reference is VDD derived and

therefore, the CVREF output changes with fluctuations in

VDD. The tested absolute accuracy of the Comparator

Voltage Reference can be found in Section 15.0

“Electrical Specifications”.

The CVREF output voltage is determined by the following

equations:

REGISTER 8-3:

VRCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

VREN

U-0

—

R/W-0

VRR

U-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

VREN: CVREF Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down, no IDD drain and CVREF = VSS.

bit 6

bit 5

Unimplemented: Read as ‘0’

VRR: CVREF Range Selection bit

1= Low range

0= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: CVREF Value Selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

DS41211D-page 58

PIC12F683

FIGURE 8-7:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

VRR

8R

16-1 Analog

MUX

VREN

15

14

CVREF to

Comparator

Input

2

1

0

(1)

VR<3:0>

VREN

VR<3:0> = 0000

VRR

Note 1: Care should be taken to ensure VREF

remains within the comparator Common

mode input range. See Section 15.0

“Electrical Specifications” for more detail.

TABLE 8-2:

SUMMARY OF REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE

REFERENCE MODULES

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

ANSEL

CMCON0

CMCON1

INTCON

PIE1

—

ADCS2

COUT

—

ADCS1 ADCS0 ANS3

ANS2

CM2

—

ANS1

CM1

ANS0

CM0

-000 1111 -000 1111

-0-0 0000 -0-0 0000

---- --10 ---- --10

0000 0000 0000 000x

000- 0000 0000 0000

000- 0000 000- 0000

--xx xxxx --uu uuuu

--11 1111 --11 1111

0-0- 0000 -0-0 0000

—

CINV

—

CIS

—

T1GSS

INTF

CMSYNC

GPIF

GIE

EEIE

EEIF

—

PEIE

ADIE

ADIF

—

T0IE

INTE

—

GPIE

CMIE

CMIF

GP3

T0IF

CCP1IE

CCP1IF

GP5

OSFIE TMR2IE

OSFIF TMR2IF

TMR1IE

TMR1IF

GP0

PIR1

—

GPIO

GP4

GP2

GP1

TRISIO

VRCON

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1

VRR VR3 VR2 VR1

TRISIO0

VR0

VREN

—

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for comparator.

DS41211D-page 59

PIC12F683

NOTES:

DS41211D-page 60

PIC12F683

The ADC voltage reference is software selectable to

either VDD or a voltage applied to the external reference

pins.

9.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

Figure 9-1 shows the block diagram of the ADC.

generates

a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESL and ADRESH).

FIGURE 9-1:

ADC BLOCK DIAGRAM

VDD

VCFG = 0

VCFG = 1

VREF

GP0/AN0

GP1/AN1/VREF

A/D

GP2/AN2

GP4/AN3

10

GO/DONE

0= Left Justify

1= Right Justify

ADFM

CHS

ADON

10

ADRESH ADRESL

9.1.2

CHANNEL SELECTION

9.1

ADC Configuration

The CHS bits of the ADCON0 register determine which

channel is connected to the sample and hold circuit.

When configuring and using the ADC the following

functions must be considered:

When changing channels, a delay is required before

starting the next conversion. Refer to Section 9.2

“ADC Operation” for more information.

• GPIO configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Results formatting

9.1.1

GPIO CONFIGURATION

The ADC can be used to convert both analog and digital

signals. When converting analog signals, the I/O pin

should be configured for analog by setting the associated

TRIS and ANSEL bits. See the corresponding GPIO

section for more information.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

DS41211D-page 61

PIC12F683

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11 TAD periods

as shown in Figure 9-2.

9.1.3

ADC VOLTAGE REFERENCE

The VCFG bit of the ADCON0 register provides control

of the positive voltage reference. The positive voltage

reference can be either VDD or an external voltage

source. The negative voltage reference is always

connected to the ground reference.

For correct conversion, the appropriate TAD specification

must be met. See A/D conversion requirements in

Section 15.0 “Electrical Specifications” for more

information. Table 9-1 gives examples of appropriate

ADC clock selections.

9.1.4

CONVERSION CLOCK

The source of the conversion clock is software select-

able via the ADCS bits of the ANSEL register. There

are seven possible clock options:

Note:

Unless using the FRC, any changes in the

system clock frequency will change the

ADC clock frequency, which may

adversely affect the ADC result.

• FOSC/2

• FOSC/4

• FOSC/8

• FOSC/16

• FOSC/32

• FOSC/64

• FRC (dedicated internal oscillator)

TABLE 9-1:

ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC Clock Source

ADCS<2:0>

20 MHz

8 MHz

4 MHz

1 MHz

FOSC/2

FOSC/4

FOSC/8

FOSC/16

FOSC/32

FOSC/64

FRC

000

100

001

101

010

110

x11

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

250 ns⁽²⁾

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

4.0 μs

8.0 μs⁽³⁾

16.0 μs⁽³⁾

32.0 μs⁽³⁾

64.0 μs⁽³⁾

2-6 μs^(1,4)

4.0 μs

8.0 μs⁽³⁾

16.0 μs⁽³⁾

2-6 μs^(1,4)

3.2 μs

2-6 μs^(1,4)

8.0 μs⁽³⁾

2-6 μs^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The FRC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the

conversion will be performed during Sleep.

FIGURE 9-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY to TAD

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Conversion Starts

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

Set GO/DONE bit

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

DS41211D-page 62

PIC12F683

9.1.5

INTERRUPTS

9.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC interrupt flag is the ADIF bit in the

PIR1 register. The ADC interrupt enable is the ADIE bit

in the PIE1 register. The ADIF bit must be cleared in

software.

The 10-bit A/D conversion result can be supplied in two

formats, left justified or right justified. The ADFM bit of

the ADCON0 register controls the output format.

Figure 9-3 shows the two output formats.

Note:

The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the global interrupt must be disabled. If the

global interrupt is enabled, execution will switch to the

interrupt service routine.

Please see Section 12.4 “Interrupts” for more

information.

FIGURE 9-3:

10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

ADRESL

LSB

(ADFM = 0)

MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

9.2.3

TERMINATING A CONVERSION

9.2

ADC Operation

If a conversion must be terminated before completion,

the GO/DONE bit can be cleared in software. The

ADRESH:ADRESL registers will not be updated with

the partially complete Analog-to-Digital conversion

sample. Instead, the ADRESH:ADRESL register pair

will retain the value of the previous conversion. Addi-

tionally, a 2 TAD delay is required before another acqui-

sition can be initiated. Following this delay, an input

acquisition is automatically started on the selected

channel.

9.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the

GO/DONE bit of the ADCON0 register to a ‘1’ will start

the Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the ADC.

Refer to Section 9.2.6 “A/D Conversion

Procedure”.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

9.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF flag bit

• Update the ADRESH:ADRESL registers with new

conversion result

DS41211D-page 63

PIC12F683

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

9.2.4

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the FRC

option. When the FRC clock source is selected, the

ADC waits one additional instruction before starting the

conversion. This allows the SLEEP instruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: See Section 9.3 “A/D Acquisition

Requirements”.

EXAMPLE 9-1:

A/D CONVERSION

;This code block configures the ADC

When the ADC clock source is something other than

FRC, a SLEEP instruction causes the present conver-

sion to be aborted and the ADC module is turned off,

although the ADON bit remains set.

;for polling, Vdd reference, Frc clock

;and GP0 input.

;

;Conversion start & polling for completion

; are included.

;

9.2.5

SPECIAL EVENT TRIGGER

BANKSEL TRISIO

;

The CCP Special Event Trigger allows periodic ADC

measurements without software intervention. When

this trigger occurs, the GO/DONE bit is set by hardware

and the Timer1 counter resets to zero.

BSF

TRISIO,0

;Set GP0 to input

;

BANKSEL ANSEL

MOVLW

IORWF

B’01110001’ ;ADC Frc clock,

ANSEL

; and GP0 as analog

;

BANKSEL ADCON0

Using the Special Event Trigger does not assure proper

ADC timing. It is the user’s responsibility to ensure that

the ADC timing requirements are met.

MOVLW

MOVWF

CALL

BSF

BTFSC

GOTO

BANKSEL ADRESH

MOVF

MOVWF

BANKSEL ADRESL

B’10000001’ ;Right justify,

ADCON0

SampleTime

ADCON0,GO

$-1

;Vdd Vref, AN0, On

;Acquisiton delay

;Start conversion

;Is conversion done?

;No, test again

;

;Read upper 2 bits

;Store in GPR space

;

See Section 11.0 “Capture/Compare/PWM (CCP)

Module” for more information.

9.2.6

A/D CONVERSION PROCEDURE

ADRESH,W

RESULTHI

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

MOVF

MOVWF

ADRESL,W

RESULTLO

;Read lower 8 bits

;Store in GPR space

1. Configure GPIO Port:

• Disable pin output driver (See TRIS register)

• Configure pin as analog

9.2.7

ADC REGISTER DEFINITIONS

2. Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Select result format

The following registers are used to control the

operation of the ADC.

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

.

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts

enabled)

7. Read ADC Result

DS41211D-page 64

PIC12F683

REGISTER 9-1:

ADCON0: A/D CONTROL REGISTER 0

R/W-0

ADFM

bit 7

R/W-0

VCFG

U-0

—

U-0

—

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

GO/DONE

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7

bit 6

ADFM: A/D Conversion Result Format Select bit

1= Right justified

0= Left justified

VCFG: Voltage Reference bit

1= VREF pin

0= VDD

bit 5-4

bit 3-2

Unimplemented: Read as ‘0’

CHS<1:0>: Analog Channel Select bits

00= AN0

01= AN1

10= AN2

11= AN3

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

DS41211D-page 65

PIC12F683

REGISTER 9-2:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x

ADRES9

bit 7

R/W-x

ADRES8

ADRES7

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 9-3:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x

ADRES1

bit 7

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

ADRES0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved: Do not use.

REGISTER 9-4:

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

—

R/W-x

ADRES9

ADRES8

bit 0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 9-5:

ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x

ADRES7

bit 7

R/W-x

ADRES6

ADRES5

ADRES4

ADRES3

ADRES2

ADRES1

ADRES0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

DS41211D-page 66

PIC12F683

an A/D acquisition must be done before the conversion

can be started. To calculate the minimum acquisition

time, Equation 9-1 may be used. This equation

assumes that 1/2 LSb error is used (1024 steps for the

ADC). The 1/2 LSb error is the maximum error allowed

for the ADC to meet its specified resolution.

9.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 9-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the

capacitor CHOLD. The sampling switch (RSS) impedance

varies over the device voltage (VDD), see Figure 9-4.

The maximum recommended impedance for analog

sources is 10 kΩ. As the source impedance is

decreased, the acquisition time may be decreased.

After the analog input channel is selected (or changed),

EQUATION 9-1:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10kΩ 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]

The value for TC can be approximated with the following equations:

1

2047

⎛

⎞

= VCHOLD

-----------

;[1] VCHOLD charged to within 1/2 lsb

VAPPLIED 1 –

⎝

⎠

–TC

---------

⎛

⎞

VAPPLIED 1 – e ^RC= V^CHOLD

;[2] VCHOLD charge response to VAPPLIED

⎜

⎝

⎟

⎠

–Tc

--------

⎛

⎞

1

2047

VAPPLIED 1 – e^RC= V^APPLIED1 –

⎛

⎞

⎠

;combining [1] and [2]

-----------

⎜

⎝

⎟

⎠

⎝

Solving for TC:

TC = –CHOLD(RIC + RSS + RS) ln(1/2047)

= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885)

= 1.37µs

Therefore:

TACQ = 2µS + 1.37µS + [(50°C- 25°C)(0.05µS/°C)]

= 4.67µS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

DS41211D-page 67

PIC12F683

FIGURE 9-4:

ANALOG INPUT MODEL

VDD

VT = 0.6V

Sampling

Switch

ANx

SS

RIC ≤ 1k

Rss

Rs

CPIN

5 pF

VA

I LEAKAGE

± 500 nA

CHOLD = 10 pF

VSS/VREF-

VT = 0.6V

6V

5V

RSS

VDD 4V

3V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance

5 6 7 8 9 1011

Sampling Switch

(kΩ)

FIGURE 9-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

1 LSB ideal

Full-Scale

Transition

004h

003h

002h

001h

000h

Analog Input Voltage

1 LSB ideal

Zero-Scale

Transition

VDD/VREF+

VSS/VREF-

DS41211D-page 68

PIC12F683

TABLE 9-2:

SUMMARY OF ASSOCIATED ADC REGISTERS

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

Resets

ADCON0

ANSEL

ADFM

—

VCFG

—

CHS1

ANS3

CHS0

ANS2

GO/DONE ADON 00-- 0000 0000 0000

ADCS2

ADCS1

ADCS0

ANS1

ANS0

-000 1111 -000 1111

xxxx xxxx uuuu uuuu

0000 0000 0000 000x

ADRESH A/D Result Register High Byte

ADRESL A/D Result Register Low Byte

INTCON

PIE1

GIE

EEIE

EEIF

—

PEIE

ADIE

ADIF

—

T0IE

CCP1IE

CCP1IF

GP5

INTE

—

GPIE

CMIE

CMIF

GP3

T0IF

OSFIE

OSFIF

GP2

INTF

TMR2IE

TMR2IF

GP1

GPIF

TMR1IE 000- 0000 0000 0000

TMR1IF 000- 0000 000- 0000

PIR1

—

GPIO

GP4

GP0

--xx xxxx --uu uuuu

TRISIO

Legend:

—

TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111

x= unknown, u= unchanged, —= unimplemented read as ‘0’. Shaded cells are not used for ADC module.

DS41211D-page 69

PIC12F683

NOTES:

DS41211D-page 70

PIC12F683

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature as well as

from chip-to-chip. Please refer to AC Specifications in

Section 15.0 “Electrical Specifications” for exact

limits.

10.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

When the data memory is code-protected, the CPU

may continue to read and write the data EEPROM

memory. The device programmer can no longer access

the data EEPROM data and will read zeroes.

• EEDAT

• EEADR

EEDAT holds the 8-bit data for read/write, and EEADR

holds the address of the EEPROM location being

accessed. PIC12F683 has 256 bytes of data EEPROM

with an address range from 0h to FFh.

REGISTER 10-1: EEDAT: EEPROM DATA REGISTER

R/W-0

EEDAT7

EEDAT6

EEDAT5

EEDAT4

EEDAT3

EEDAT2

EEDAT1

EEDAT0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

EEDATn: Byte Value to Write To or Read From Data EEPROM bits

REGISTER 10-2: EEADR: EEPROM ADDRESS REGISTER

R/W-0

EEADR7

EEADR6

EEADR5

EEADR4

EEADR3

EEADR2

EEADR1

EEADR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-0

EEADR: Specifies One of 256 Locations for EEPROM Read/Write Operation bits

DS41211D-page 71

PIC12F683

operation. In these situations, following Reset, the user

can check the WRERR bit, clear it and rewrite the

location. The data and address will be cleared.

Therefore, the EEDAT and EEADR registers will need

to be re-initialized.

10.1 EECON1 and EECON2 Registers

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are non-

implemented and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

Interrupt flag, EEIF bit of the PIR1 register, is set when

write is complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

Note:

The EECON1, EEDAT and EEADR

registers should not be modified during a

data EEPROM write (WR bit = 1).

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set when a write operation is interrupted by a MCLR

Reset, or a WDT Time-out Reset during normal

REGISTER 10-3: EECON1: EEPROM CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

WRERR

bit 7

bit 0

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WRERR: EEPROM Error Flag bit

1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0= The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the data EEPROM

WR: Write Control bit

1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only

be set, not cleared, in software.)

0= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only

be set, not cleared, in software.)

0= Does not initiate an EEPROM read

DS41211D-page 72

PIC12F683

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

10.2 Reading the EEPROM Data

Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD of the EECON1 register, as shown in Example 10-1.

The data is available, at the very next cycle, in the

EEDAT register. Therefore, it can be read in the next

instruction. EEDAT holds this value until another read, or

until it is written to by the user (during a write operation).

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit of the

PIR1 register must be cleared by software.

10.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 10-3) to the

desired value to be written.

EXAMPLE 10-1:

DATA EEPROM READ

BANKSEL

MOVLW

MOVWF

BSF

EEADR

;

CONFIG_ADDR;

EEADR

;Address to read

EECON1,RD ;EE Read

MOVF

EEDAT,W

;Move data to W

EXAMPLE 10-3:

WRITE VERIFY

BANKSELEEDAT

;

10.3 Writing to the EEPROM Data

Memory

MOVF

BSF

EEDAT,W

;EEDAT not changed

;from previous write

;YES, Read the

EECON1,RD

;value written

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 10-2.

XORWF

BTFSS

GOTO

:

EEDAT,W

STATUS,Z

WRITE_ERR

;Is data the same

;No, handle error

;Yes, continue

10.4.1

USING THE DATA EEPROM

high-endurance, byte

EXAMPLE 10-2:

DATA EEPROM WRITE

BANKSEL EECON1

;

The data EEPROM is

a

BSF

EECON1,WREN ;Enable write

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

When variables in one section change frequently, while

variables in another section do not change, it is possible

to exceed the total number of write cycles to the

EEPROM (specification D124) without exceeding the

BCF

INTCON,GIE

$-2

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

;Disable INTs

;See AN576

;

;Unlock write

;

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

;Start the write

;Enable INTS

total number of write cycles to

a single byte

BSF

(specifications D120 and D120A). If this is the case,

then a refresh of the array must be performed. For this

reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

DS41211D-page 73

PIC12F683

10.5 Protection Against Spurious Write

10.6 Data EEPROM Operation During

Code-Protect

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Data memory can be code-protected by programming

the CPD bit in the Configuration Word register

(Register 12-1) to ‘0’.

Power-up

Timer

(64 ms

duration)

prevents

When the data memory is code-protected, the CPU is

able to read and write data to the data EEPROM. It is

recommended to code-protect the program memory

when code-protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also help prevent data memory code protection

from becoming breached.

EEPROM write.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• Brown-out

• Power Glitch

• Software Malfunction

TABLE 10-1: SUMMARY OF ASSOCIATED DATA EEPROM REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIR1

GIE

EEIF

EEIE

PEIE

ADIF

ADIE

T0IE

INTE

—

GPIE

CMIF

CMIE

T0IF

INTF

GPIF

0000 0000 0000 0000

CCP1IF

CCP1IE

OSFIF

OSFIE

TMR2IF TMR1IF 000- 0000 000- 0000

TMR2IE TMR1IE 000- 0000 000- 0000

PIE1

—

EEDAT

EEADR

EECON1

EECON2

Legend:

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

—

WRERR

WREN

WR

RD

---- x000 ---- q000

---- ---- ---- ----

(1)

EEPROM Control Register 2

x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition. Shaded cells are not

used by the Data EEPROM module.

Note 1: EECON2 is not a physical register.

DS41211D-page 74

PIC12F683

Additional information on CCP modules is available in

the Application Note AN594, “Using the CCP Modules”

(DS00594).

11.0 CAPTURE/COMPARE/PWM

(CCP) MODULE

The Capture/Compare/PWM module is a peripheral

which allows the user to time and control different

events. In Capture mode, the peripheral allows the

timing of the duration of an event.The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate a Pulse-Width Modulated signal of

varying frequency and duty cycle.

TABLE 11-1: CCP MODE – TIMER

RESOURCES REQUIRED

CCP Mode

Timer Resource

Capture

Compare

PWM

Timer1

Timer2

The timer resources used by the module are shown in

Table 11-1

REGISTER 11-1: CCP1CON: CCP1 CONTROL REGISTER

U-0

—

U-0

—

R/W-0

DC1B1

R/W-0

DC1B0

R/W-0

CCP1M1

R/W-0

CCP1M3

CCP1M2

CCP1M0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused.

Compare mode:

Unused.

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: CCP Mode Select bits

0000= Capture/Compare/PWM off (resets CCP module)

0001= Unused (reserved)

0010= Unused (reserved)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCP1IF bit is set)

1001= Compare mode, clear output on match (CCP1IF bit is set)

1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin

is unaffected)

1011= Compare mode, trigger special event (CCP1IF bit is set, TMR1 is reset and A/D

conversion is started if the ADC module is enabled. CCP1 pin is unaffected.)

110x= PWM mode active-high

111x= PWM mode active-low

DS41211D-page 75

PIC12F683

11.1.2

TIMER1 MODE SELECTION

11.1 Capture Mode

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin CCP1. An event is defined as one of the

following and is configured by the CCP1M<3:0> bits of

the CCP1CON register:

11.1.3

SOFTWARE INTERRUPT

• Every falling edge

• Every rising edge

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCP1IE interrupt enable bit of the PIE1 register clear to

avoid false interrupts. Additionally, the user should

clear the CCP1IF interrupt flag bit of the PIR1 register

following any change in operating mode.

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the Interrupt Request Flag bit

CCP1IF of the PIR1 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPR1H, CCPR1L register pair

is read, the old captured value is overwritten by the new

captured value (see Figure 11-1).

11.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCP1M<3:0> bits of the CCP1CON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

11.1.1

CCP1 PIN CONFIGURATION

In Capture mode, the CCP1 pin should be configured

as an input by setting the associated TRIS control bit.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCP1CON register before changing the

prescaler (see Example 11-1).

Note:

If the CCP1 pin is configured as an output,

a write to the GPIO port can cause a

capture condition.

FIGURE 11-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

EXAMPLE 11-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSELCCP1CON

;Set Bank bits to point

;to CCP1CON

;Turn CCP module off

Set Flag bit CCP1IF

(PIR1 register)

Prescaler

÷ 1, 4, 16

CLRF

CCP1CON

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

CCP1

CCPR1H

CCPR1L

; move value and CCP ON

Capture

Enable

MOVWF

CCP1CON

;Load CCP1CON with this

; value

and

Edge Detect

TMR1H

TMR1L

CCP1CON<3:0>

System Clock (FOSC)

DS41211D-page 76

PIC12F683

11.2.2

TIMER1 MODE SELECTION

11.2 Compare Mode

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCP1 module may:

• Toggle the CCP1 output.

• Set the CCP1 output.

11.2.3

SOFTWARE INTERRUPT MODE

• Clear the CCP1 output.

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 module does not

assert control of the CCP1 pin (see the CCP1CON

register).

• Generate a Special Event Trigger.

• Generate a Software Interrupt.

The action on the pin is based on the value of the

CCP1M<3:0> control bits of the CCP1CON register.

11.2.4

SPECIAL EVENT TRIGGER

All Compare modes can generate an interrupt.

When Special Event Trigger mode is chosen

(CCP1M<3:0> = 1011), the CCP1 module does the

following:

FIGURE 11-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

CCP1CON<3:0>

Mode Select

The CCP1 module does not assert control of the CCP1

pin in this mode (see the CCP1CON register).

Set CCP1IF Interrupt Flag

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPR1H, CCPR1L

register pair. The TMR1H, TMR1L register pair is not

reset until the next rising edge of the Timer1 clock. This

allows the CCPR1H, CCPR1L register pair to

effectively provide a 16-bit programmable period

register for Timer1.

(PIR1)

4

CCP1

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

TMR1H TMR1L

TRIS

Output Enable

Special Event Trigger

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMRxIF of the PIR1 register.

Special Event Trigger will:

•

Clear TMR1H and TMR1L registers.

NOT set interrupt flag bit TMR1IF of the PIR1 register.

Set the GO/DONE bit to start the ADC conversion.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

11.2.1

CCP1 PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the associated TRIS bit.

Note:

Clearing the CCP1CON register will force

the CCP1 compare output latch to the

default low level. This is not the GPIO I/O

data latch.

DS41211D-page 77

PIC12F683

The PWM output (Figure 11-4) has a time base

(period) and a time that the output stays high (duty

cycle).

11.3 PWM Mode

The PWM mode generates a Pulse-Width Modulated

signal on the CCP1 pin. The duty cycle, period and

resolution are determined by the following registers:

FIGURE 11-4:

CCP PWM OUTPUT

• PR2

Period

• T2CON

• CCPR1L

• CCP1CON

Pulse Width

TMR2 = PR2

TMR2 = CCPR1L:CCP1CON<5:4>

In Pulse-Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the CCP1 pin. Since the CCP1 pin is multiplexed

with the PORT data latch, the TRIS for that pin must be

cleared to enable the CCP1 pin output driver.

TMR2 = 0

Note:

Clearing the CCP1CON register will

relinquish CCP1 control of the CCP1 pin.

Figure 11-1 shows a simplified block diagram of PWM

operation.

Figure 11-4 shows a typical waveform of the PWM

signal.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 11.3.7

“Setup for PWM Operation”.

FIGURE 11-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty Cycle Registers

CCPR1L

CCPR1H⁽²⁾(Slave)

Comparator

CCP1

R

S

Q

(1)

TMR2

TRIS

Comparator

PR2

Clear Timer2,

toggle CCP1 pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (FOSC), or

2 bits of the prescaler, to create the 10-bit time

base.

2: In PWM mode, CCPR1H is a read-only register.

DS41211D-page 78

PIC12F683

11.3.1

PWM PERIOD

EQUATION 11-2: PULSE WIDTH

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 11-1.

Pulse Width = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 Prescale Value)

EQUATION 11-1: PWM PERIOD

EQUATION 11-3: DUTY CYCLE RATIO

PWM Period = [(PR2) + 1] • 4 • TOSC •

(TMR2 Prescale Value)

(CCPR1L:CCP1CON<5:4>)

Duty Cycle Ratio = -----------------------------------------------------------------------

4(PR2 + 1)

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

• TMR2 is cleared

• The CCP1 pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or 2 bits of

the prescaler, to create the 10-bit time base. The system

clock is used if the Timer2 prescaler is set to 1:1.

• The PWM duty cycle is latched from CCPR1L into

CCPR1H.

Note:

The Timer2 postscaler (see Section 7.0

“Timer2 Module”) is not used in the

determination of the PWM frequency.

When the 10-bit time base matches the CCPR1H and 2-

bit latch, then the CCP1 pin is cleared (see Figure 11-1).

11.3.3

PWM RESOLUTION

11.3.2

PWM DUTY CYCLE

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

The PWM duty cycle is specified by writing a 10-bit

value to multiple registers: CCPR1L register and

DC1B<1:0> bits of the CCP1CON register. The

CCPR1L contains the eight MSbs and the CCP1<1:0>

bits of the CCP1CON register contain the two LSbs.

CCPR1L and DC1B<1:0> bits of the CCP1CON

register can be written to at any time. The duty cycle

value is not latched into CCPR1H until after the period

completes (i.e., a match between PR2 and TMR2

registers occurs). While using the PWM, the CCPR1H

register is read-only.

The maximum PWM resolution is 10 bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 11-4.

EQUATION 11-4: PWM RESOLUTION

log[4(PR2 + 1)]

Resolution = ----------------------------------------- bits

log(2)

Equation 11-2 is used to calculate the PWM pulse

width.

Equation 11-3 is used to calculate the PWM duty cycle

ratio.

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

TABLE 11-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 11-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

Maximum Resolution (bits)

DS41211D-page 79

PIC12F683

11.3.4

OPERATION IN SLEEP MODE

11.3.7

SETUP FOR PWM OPERATION

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCP1

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Disable the PWM pin (CCP1) output drivers by

setting the associated TRIS bit.

2. Set the PWM period by loading the PR2 register.

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

11.3.5

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 3.0 “Oscillator Module (With Fail-Safe

Clock Monitor)” for additional details.

4. Set the PWM duty cycle by loading the CCPR1L

register and DC1B bits of the CCP1CON register.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the

PIR1 register.

11.3.6

EFFECTS OF RESET

• Set the Timer2 prescale value by loading the

T2CKPS bits of the T2CON register.

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

• Enable Timer2 by setting the TMR2ON bit of

the T2CON register.

6. Enable PWM output after a new PWM cycle has

started:

• Wait until Timer2 overflows (TMR2IF bit of

the PIR1 register is set).

• Enable the CCP1 pin output driver by

clearing the associated TRIS bit.

DS41211D-page 80

PIC12F683

TABLE 11-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CCP1CON

CCPR1L

CCPR1H

CMCON1

INTCON

PIE1

—

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

xxxx xxxx

---- --10

0000 0000

000- 0000

0000 0000

xxxx xxxx

--11 1111

--00 0000

xxxx xxxx

---- --10

0000 000x

000- 0000

0000 0000

xxxx xxxx

--11 1111

Capture/Compare/PWM Register 1 Low Byte (LSB)

Capture/Compare/PWM Register 1 High Byte (MSB)

—

GIE

—

PEIE

—

INTE

—

T1GSS

INTF

CMSYNC

GPIF

T0IE

GPIE

CMIE

CMIF

T0IF

EEIE

EEIF

T1GINV

ADIE

CCP1IE

CCP1IF

OSFIE

OSFIF

T1SYNC

TMR2IE

TMR2IF

TMR1CS

TMR1IE

TMR1IF

TMR1ON

PIR1

ADIF

—

T1CON

TMR1L

TMR1H

TRISIO

TMR1GE

T1CKPS1 T1CKPS0 T1OSCEN

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

—

TRISIO5

TRISIO4

TRISIO3

TRISIO2

TRISIO1

TRISIO0

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture and Compare.

TABLE 11-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CCP1CON

CCPR1L

CCPR1H

INTCON

PIE1

—

DC1B1

DC1B0

CCP1M3

CCP1M2

CCP1M1

CCP1M0

--00 0000

xxxx xxxx

0000 0000

000- 0000

1111 1111

--00 0000

xxxx xxxx

0000 000x

-000 0000

1111 1111

-000 0000

0000 0000

--11 1111

Capture/Compare/PWM Register 1 Low Byte (LSB)

Capture/Compare/PWM Register 1 High Byte (MSB)

GIE

EEIE

EEIF

PEIE

ADIE

ADIF

T0IE

INTE

—

GPIE

CMIE

CMIF

T0IF

INTF

GPIF

CCP1IE

CCP1IF

OSFIE

OSFIF

TMR2IE

TMR2IF

TMR1IE

TMR1IF

PIR1

—

PR2

Timer2 Period Register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0

Timer2 Module Register

T2CON

TMR2

—

TMR2ON

TRISIO2

T2CKPS1 T2CKPS0 -000 0000

0000 0000

TRISIO

—

TRISIO5

TRISIO4

TRISIO3

TRISIO1

TRISIO0

--11 1111

Legend: – = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the PWM.

DS41211D-page 81

PIC12F683

NOTES:

DS41211D-page 82

PIC12F683

The PIC12F683 has two timers that offer necessary

delays on power-up. One is the Oscillator Start-up Timer

(OST), intended to keep the chip in Reset until the crys-

tal oscillator is stable. The other is the Power-up Timer

(PWRT), which provides a fixed delay of 64 ms (nomi-

nal) on power-up only, designed to keep the part in

Reset while the power supply stabilizes. There is also

circuitry to reset the device if a brown-out occurs, which

can use the Power-up Timer to provide at least a 64 ms

Reset. With these three functions on-chip, most

applications need no external Reset circuitry.

12.0 SPECIAL FEATURES OF THE

CPU

The PIC12F683 has a host of features intended to

maximize system reliability, minimize cost through

elimination of external components, provide power

saving features and offer code protection.

These features are:

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

The Sleep mode is designed to offer a very low-current

Power-down mode. The user can wake-up from Sleep

through:

• External Reset

• Watchdog Timer (WDT)

• Oscillator Selection

• Sleep

• Watchdog Timer Wake-up

• An interrupt

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost while the LP crystal option saves

power. A set of Configuration bits are used to select

various options (see Register 12-1).

• Code Protection

• ID Locations

• In-Circuit Serial Programming™

Note:

Address 2007h is beyond the user

program memory space. It belongs to the

special configuration memory space

(2000h-3FFFh), which can be accessed

only

during

programming.

See

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

12.1 Configuration Bits

The Configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 12-1.

These bits are mapped in program memory location

2007h.

DS41211D-page 83

PIC12F683

REGISTER 12-1: CONFIG: CONFIGURATION WORD REGISTER

—

FCMEN

IESO

BOREN1

FOSC1

BOREN0

bit 8

bit 15

bit 7

CPD

CP

MCLRE

PWRTE

WDTE

FOSC2

FOSC0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

P = Programmable’

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

bit 15-12

bit 11

Unimplemented: Read as ‘1’

FCMEN: Fail-Safe Clock Monitor Enabled bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

bit 10

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled

0= Internal External Switchover mode is disabled

(1)

bit 9-8

BOREN<1:0>: Brown-out Reset Selection bits

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit of the PCON register

00= BOR disabled

(2)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

CPD: Data Code Protection bit

1= Data memory code protection is disabled

0= Data memory code protection is enabled

(3)

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

(4)

MCLRE: GP3/MCLR pin function select bit

1= GP3/MCLR pin function is MCLR

0= GP3/MCLR pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled and can be enabled by SWDTEN bit of the WDTCON register

FOSC<2:0>: Oscillator Selection bits

111= RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN

110= RCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN

101= INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

100= INTOSCIO oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN

011= EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN

010= HS oscillator: High-speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

001= XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

000= LP oscillator: Low-power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased when the code protection is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

DS41211D-page 84

PIC12F683

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

12.2 Calibration Bits

Brown-out Reset (BOR), Power-on Reset (POR) and

8 MHz internal oscillator (HFINTOSC) are factory cali-

brated. These calibration values are stored in fuses

located in the Calibration Word (2009h). The Calibra-

tion Word is not erased when using the specified bulk

erase sequence in the “PIC12F6XX/16F6XX Memory

Programming Specification” (DS41244) and thus, does

not require reprogramming.

• Power-on Reset

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

WDT wake-up does not cause register resets in the

same manner as a WDT Reset since wake-up is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 12-2. Software can use

these bits to determine the nature of the Reset. See

Table 12-4 for a full description of Reset states of all

registers.

12.3 Reset

The PIC12F683 differentiates between various kinds of

Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 12-1.

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 15.0 “Electrical

Specifications” for pulse-width specifications.

FIGURE 12-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

SLEEP

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

BOREN

SBOREN

S

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

R

Q

OSC1/

CLKI pin

PWRT

11-bit Ripple Counter

LFINTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word register (Register 12-1).

DS41211D-page 85

PIC12F683

12.3.1

POWER-ON RESET

FIGURE 12-2:

RECOMMENDED MCLR

CIRCUIT

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the POR, simply

connect the MCLR pin through a resistor to VDD. This

will eliminate external RC components usually needed

to create Power-on Reset. A maximum rise time for

VDD is required. See Section 15.0 “Electrical

Specifications” for details. If the BOR is enabled, the

maximum rise time specification does not apply. The

BOR circuitry will keep the device in Reset until VDD

reaches VBOD (see Section 12.3.4 “Brown-Out Reset

(BOR)”).

VDD

PIC^®

MCU

R1

1 kΩ (or greater)

R2

MCLR

100 Ω

(needed with capacitor)

SW1

(optional)

C1

0.1 μF

(optional, not critical)

Note:

The POR circuit does not produce an

internal Reset when VDD declines. To

re-enable the POR, VDD must reach Vss

for a minimum of 100 μs.

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

12.3.3

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.5 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A

Configuration bit, PWRTE, can disable (if set) or enable

(if cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Reset is enabled, although it is not required.

For additional information, refer to the Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

12.3.2

MCLR

PIC12F683 has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

The Power-up Timer delay will vary from chip-to-chip

due to:

Voltages applied to the MCLR pin that exceed its

specification can result in both MCLR Resets and

excessive current beyond the device specification

during the ESD event. For this reason, Microchip

recommends that the MCLR pin no longer be tied

directly to VDD. The use of an RC network, as shown in

Figure 12-2, is suggested.

• VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 15.0

“Electrical Specifications”).

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

MCLRE = 0, the Reset signal to the chip is generated

internally. When the MCLRE = 1, the GP3/MCLR pin

becomes an external Reset input. In this mode, the

GP3/MCLR pin has a weak pull-up to VDD.

Note:

Voltage spikes below VSS at the MCLR

pin, inducing currents greater than 80 mA,

may cause latch-up. Thus, a series resis-

tor of 50-100 Ω should be used when

applying a “low” level to the MCLR pin,

rather than pulling this pin directly to VSS.

DS41211D-page 86

PIC12F683

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

12.3.4

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word register select one of four BOR modes. Two

modes have been added to allow software or hardware

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit of the PCON register enables/disables

the BOR, allowing it to be controlled in software. By

selecting BOREN<1:0> = 10, the BOR is automatically

disabled in Sleep to conserve power and enabled on

wake-up. In this mode, the SBOREN bit is disabled.

See Register 12-1 for the Configuration Word

definition.

12.3.5

BOR CALIBRATION

The PIC12F683 stores the BOR calibration values in

fuses located in the Calibration Word register (2008h).

The Calibration Word register is not erased when using

the specified bulk erase sequence in the

“PIC12F6XX/16F6XX Memory Programming Specifi-

cation” (DS41204) and thus, does not require

reprogramming.

A brown-out occurs when VDD falls below VBOR for

greater than parameter TBOR (see Section 15.0

“Electrical Specifications”). The brown-out condition

will reset the device. This will occur regardless of VDD

slew rate. A Brown-out Reset may not occur if VDD falls

below VBOR for less than parameter TBOR.

Note:

Address 2008h is beyond the user pro-

gram memory space. It belongs to the

special configuration memory space

(2000h-3FFFh), which can be accessed

only

during

programming.

See

On any Reset (Power-on, Brown-out Reset, Watchdog

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 12-3). If enabled, the

Power-up Timer will be invoked by the Reset and keep

the chip in Reset an additional 64 ms.

“PIC12F6XX/16F6XX Memory Program-

ming Specification” (DS41204) for more

information.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word

register.

FIGURE 12-3:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

DS41211D-page 87

PIC12F683

12.3.6

TIME-OUT SEQUENCE

12.3.7

POWER CONTROL (PCON)

REGISTER

On power-up, the time-out sequence is as follows:

• PWRT time-out is invoked after POR has expired.

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset occurred

last.

• OST is activated after the PWRT time-out has

expired.

Bit 0 is BOR (Brown-out). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

The total time-out will vary based on oscillator

configuration and PWRTE bit status. For example, in EC

mode with PWRTE bit erased (PWRT disabled), there

will be no time-out at all. Figure 12-4, Figure 12-5 and

Figure 12-6 depict time-out sequences. The device can

execute code from the INTOSC while OST is active by

enabling Two-Speed Start-up or Fail-Safe Monitor (see

Section 3.7.2 “Two-Speed Start-up Sequence” and

Section 3.8 “Fail-Safe Clock Monitor”).

(BOREN<1:0>

register).

= 00 in the Configuration Word

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a subse-

quent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 12-5). This is useful for testing purposes or

to synchronize more than one PIC12F683 device

operating in parallel.

For more information, see Section 4.2.4 “Ultra

Low-Power

“Brown-Out Reset (BOR)”.

Wake-up”

and

Section 12.3.4

Table 12-5 shows the Reset conditions for some

special registers, while Table 12-4 shows the Reset

conditions for all the registers.

TABLE 12-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Sleep

Oscillator Configuration

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

1024 • TOSC

XT, HS, LP

TPWRT + 1024 •

TOSC

1024 • TOSC

TPWRT + 1024 •

TOSC

1024 • TOSC

—

RC, EC, INTOSC

TPWRT

—

TPWRT

—

TABLE 12-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

u

x

0

u

1

0

1

u

0

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET

Value on

POR, BOR

Name

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets⁽¹⁾

CONFIG⁽²⁾BOREN1 BOREN0

CPD

CP

MCLRE

PWRTE

WDTE FOSC2 FOSC1 FOSC0

—

PCON

—

ULPWUE SBOREN

RP0 TO

—

Z

POR

DC

BOR

C

--01 --qq

0001 1xxx

--0u --uu

000q quuu

STATUS

IRP

RP1

PD

Legend:

Note 1:

2:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are not used by BOR.

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

See Configuration Word register (Register 12-1) for operation of all register bits.

DS41211D-page 88

PIC12F683

FIGURE 12-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 12-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 12-6:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

DS41211D-page 89

PIC12F683

TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS

MCLR Reset

Wake-up from Sleep

through Interrupt

Wake-up from Sleep through

WDT Time-out

Register

Address Power-on Reset

WDT Reset

Brown-out Reset⁽¹⁾

W

—

00h/80h

01h

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--x0 x000

---0 0000

0000 0000

xxxx xxxx

0000 0000

-000 0000

xxxx xxxx

--00 0000

---0 1000

0000 0000

---- --10

xxxx xxxx

00-- 0000

1111 1111

--11 1111

0000 0000

--01 --0x

-110 q000

---0 0000

1111 1111

--11 -111

--00 0000

0-0- 0000

0000 0000

uuuu uuuu

xxxx xxxx

uuuu uuuu

0000 0000

000q quuu⁽⁴⁾

uuuu uuuu

--x0 x000

---0 0000

0000 0000

uuuu uuuu

0000 0000

-000 0000

uuuu uuuu

--00 0000

---0 1000

0000 0000

---- --10

uuuu uuuu

00-- 0000

1111 1111

--11 1111

0000 0000

--0u --uu^(1,5)

-110 q000

---u uuuu

1111 1111

--11 -111

--00 0000

0-0- 0000

0000 0000

uuuu uuuu

PC + 1⁽³⁾

INDF

TMR0

PCL

02h/82h

03h/83h

04h/84h

05h

STATUS

FSR

uuuq quuu⁽⁴⁾

uuuu uuuu

--uu uuuu

---u uuuu

uuuu uuuu⁽²⁾

uuuu uuuu

-uuu uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

---u uuuu

uuuu uuuu

---- --uu

uuuu uuuu

uu-- uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu --uu

-uuu uuuu

---u uuuu

1111 1111

uuuu uuuu

--uu uuuu

u-u- uuuu

uuuu uuuu

GPIO

PCLATH

INTCON

PIR1

0Ah/8Ah

0Bh/8Bh

0Ch

TMR1L

TMR1H

T1CON

TMR2

0Eh

0Fh

10h

11h

T2CON

CCPR1L

CCPR1H

CCP1CON

WDTCON

CMCON0

CMCON1

ADRESH

ADCON0

OPTION_REG

TRISIO

PIE1

12h

13h

14h

15h

18h

19h

20h

1Eh

1Fh

81h

85h

8Ch

PCON

8Eh

OSCCON

OSCTUNE

PR2

8Fh

90h

92h

WPU

95h

IOC

96h

VRCON

EEDAT

EEADR

99h

9Ah

9Bh

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 12-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DS41211D-page 90

PIC12F683

TABLE 12-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

Wake-up from Sleep

through Interrupt

Wake-up from Sleep through

WDT Time-out

MCLR Reset

Register

Address Power-on Reset

WDT Reset

Brown-out Reset⁽¹⁾

EECON1

9Ch

9Dh

9Eh

9Fh

---- x000

---- ----

xxxx xxxx

-000 1111

---- q000

---- ----

uuuu uuuu

-000 1111

---- uuuu

---- ----

uuuu uuuu

-uuu uuuu

EECON2

ADRESL

ANSEL

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 12-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

TABLE 12-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

Status

Register

PCON

Register

Condition

Power-on Reset

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

--01 --0x

--0u --uu

--uu --uu

--01 --10

--uu --uu

MCLR Reset during Normal Operation

MCLR Reset during Sleep

WDT Reset

000h

WDT Wake-up

PC + 1

000h

PC + 1⁽¹⁾

Brown-out Reset

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with

the interrupt vector (0004h) after execution of PC + 1.

DS41211D-page 91

PIC12F683

For external interrupt events, such as the INT pin or

GPIO change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 12-8). The latency is the same for one or

two-cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

12.4 Interrupts

The PIC12F683 has multiple interrupt sources:

• External Interrupt GP2/INT

• Timer0 Overflow Interrupt

• GPIO Change Interrupts

• Comparator Interrupt

• A/D Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

The Interrupt Control register (INTCON) and Peripheral

Interrupt Request Register 1 (PIR1) record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

The Global Interrupt Enable bit, GIE of the INTCON

register, enables (if set) all unmasked interrupts, or

disables (if cleared) all interrupts. Individual interrupts

can be disabled through their corresponding enable

bits in the INTCON register and PIE1 register. GIE is

cleared on Reset.

For additional information on Timer1, Timer2,

comparators, ADC, data EEPROM or Enhanced CCP

modules, refer to the respective peripheral section.

12.4.1

GP2/INT INTERRUPT

When an interrupt is serviced, the following actions

occur automatically:

The external interrupt on the GP2/INT pin is

edge-triggered; either on the rising edge if the INTEDG

bit of the OPTION register is set, or the falling edge, if

the INTEDG bit is clear. When a valid edge appears on

the GP2/INT pin, the INTF bit of the INTCON register is

set. This interrupt can be disabled by clearing the INTE

control bit of the INTCON register. The INTF bit must

be cleared by software in the Interrupt Service Routine

before re-enabling this interrupt. The GP2/INT interrupt

can wake-up the processor from Sleep, if the INTE bit

was set prior to going into Sleep. See Section 12.7

“Power-Down Mode (Sleep)” for details on Sleep and

Figure 12-10 for timing of wake-up from Sleep through

GP2/INT interrupt.

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

The following interrupt flags are contained in the

INTCON register:

• INT Pin Interrupt

• GPIO Change Interrupt

• Timer0 Overflow Interrupt

Note:

The ANSEL and CMCON0 registers must

be initialized to configure an analog

channel as a digital input. Pins configured

as analog inputs will read ‘0’ and cannot

generate an interrupt.

The peripheral interrupt flags are contained in the PIR1

register. The corresponding interrupt enable bit is

contained in the PIE1 register.

The following interrupt flags are contained in the PIR1

register:

• EEPROM Data Write Interrupt

• A/D Interrupt

• Comparator Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• Fail-Safe Clock Monitor Interrupt

•

CCP Interrupt

DS41211D-page 92

PIC12F683

12.4.2

TIMER0 INTERRUPT

12.4.3

GPIO INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF (INTCON<2>) bit. The interrupt can be

enabled/disabled by setting/clearing the T0IE bit of the

INTCON register. See Section 5.0 “Timer0 Module”

for operation of the Timer0 module.

An input change on GPIO change sets the GPIF bit of

the INTCON register. The interrupt can be

enabled/disabled by setting/clearing the GPIE bit of the

INTCON register. Plus, individual pins can be

configured through the IOC register.

Note:

If a change on the I/O pin should occur

when any GPIO operation is being

executed, then the GPIF interrupt flag may

not get set.

FIGURE 12-7:

INTERRUPT LOGIC

IOC-GP0

IOC0

IOC-GP1

IOC1

IOC-GP2

IOC2

IOC-GP3

IOC3

IOC-GP4

IOC4

IOC-GP5

IOC5

Wake-up (If in Sleep mode)

Interrupt to CPU

T0IF

T0IE

TMR2IF

TMR2IE

INTF

INTE

TMR1IF

TMR1IE

GPIF

GPIE

CMIF

CMIE

PEIE

GIE

ADIF

ADIE

EEIF

EEIE

OSFIF

OSFIE

CCP1IF

CCP1IE

DS41211D-page 93

PIC12F683

FIGURE 12-8:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF flag

(INTCON reg.)

GIE bit

(INTCON reg.)

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency

is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 15.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

INTCON

IOC

GIE

—

PEIE

—

T0IE

INTE

IOC4

—

GPIE

IOC3

T0IF

INTF

IOC1

GPIF

IOC0

0000 0000 0000 0000

--00 0000 --00 0000

IOC5

IOC2

PIR1

EEIF

EEIE

ADIF CCP1IF

ADIE CCP1IE

CMIF OSFIF TMR2IF TMR1IF 000- 0000 000- 0000

CMIE OSFIE TMR2IE TMR1IE 000- 0000 000- 0000

PIE1

—

Legend: x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by the interrupt module.

DS41211D-page 94

PIC12F683

12.5 Context Saving During Interrupts

Note:

The PIC12F683 normally does not require

saving the PCLATH. However, if com-

puted GOTO’s are used in the ISR and the

main code, the PCLATH must be saved

and restored in the ISR.

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since the lower 16 bytes of all banks are common in the

PIC12F683 (see Figure 2-2), temporary holding regis-

ters, W_TEMP and STATUS_TEMP, should be placed

in here. These 16 locations do not require banking and

therefore, makes it easier to context save and restore.

The same code shown in Example 12-1 can be used

to:

• Store the W register.

• Store the STATUS register.

• Execute the ISR code.

• Restore the Status (and Bank Select Bit register).

• Restore the W register.

EXAMPLE 12-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

W_TEMP

STATUS,W

;Copy W to TEMP register

;Swap status to be saved into W

;Swaps are used because they do not affect the status bits

;Save status to bank zero STATUS_TEMP register

MOVWF

:

STATUS_TEMP

:(ISR)

:

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS41211D-page 95

PIC12F683

12.6.2

WDT CONTROL

12.6 Watchdog Timer (WDT)

The WDTE bit is located in the Configuration Word

register. When set, the WDT runs continuously.

The WDT has the following features:

• Operates from the LFINTOSC (31 kHz)

• Contains a 16-bit prescaler

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 1 ms to 268 seconds

• Configuration bit and software controlled

WDT is cleared under certain conditions described in

Table 12-7.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC12F683

Family

of

microcontrollers.

See

12.6.1

WDT OSCILLATOR

Section 5.0 “Timer0 Module” for more information.

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit of the OSCCON register does

not reflect that the LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 17 ms.

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

FIGURE 12-9:

WATCHDOG TIMER BLOCK DIAGRAM

0

1

From Timer0 Clock Source

Prescaler⁽¹⁾

16-bit WDT Prescaler

8

PSA

PS<2:0>

31 kHz

LFINTOSC Clock

WDTPS<3:0>

To Timer0

1

0

PSA

WDTE from Configuration Word register

SWDTEN from WDTCON

WDT Time-out

Note 1:

This is the shared Timer0/WDT prescaler. See Section 5.0 “Timer0 Module” for more information.

TABLE 12-7: WDT STATUS

Conditions

WDT

WDTE = 0

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

DS41211D-page 96

PIC12F683

REGISTER 12-2: WDTCON: WATCHDOG TIMER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

WDTPS3

WDTPS2

WDTPS1

WDTPS0

SWDTEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

bit 0

SWDTEN: Software Enable or Disable the Watchdog Timer⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: If WDTE Configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTE

Configuration bit = 0, then it is possible to turn WDT on/off with this control bit.

TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Value on

all other

Resets

Value on

POR, BOR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDTCON

—

WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

OPTION_REG GPPU INTEDG T0CS

T0SE

MCLRE PWRTE WDTE

Shaded cells are not used by the Watchdog Timer.

PSA

PS2

PS1

PS0

1111 1111 1111 1111

CONFIG

CPD

CP

FOSC2 FOSC1

FOSC0

—

Legend:

Note 1: See Register 12-1 for operation of all Configuration Word register bits.

DS41211D-page 97

PIC12F683

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up

occurs regardless of the state of the GIE bit. If the GIE

bit is clear (disabled), the device continues execution at

the instruction after the SLEEPinstruction. If the GIE bit

is set (enabled), the device executes the instruction

after the SLEEPinstruction, then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOPafter the SLEEPinstruction.

12.7 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEPinstruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

• PD bit in the STATUS register is cleared.

• TO bit is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before SLEEP

was executed (driving high, low or high-impedance).

Note:

If the global interrupts are disabled (GIE is

cleared) and any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep.

For lowest current consumption in this mode, all I/O pins

should be either at VDD or VSS, with no external circuitry

drawing current from the I/O pin and the comparators

and CVREF should be disabled. I/O pins that are

high-impedance inputs should be pulled high or low

externally to avoid switching currents caused by floating

inputs. The T0CKI input should also be at VDD or VSS for

lowest current consumption. The contribution from

on-chip pull-ups on GPIO should be considered.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

12.7.2

WAKE-UP USING INTERRUPTS

The MCLR pin must be at a logic high level.

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

Note:

It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

12.7.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin.

• If the interrupt occurs during or after the

execution of a SLEEPinstruction, the device will

Immediately wake-up from Sleep. The SLEEP

instruction is executed. Therefore, the WDT and

WDT prescaler and postscaler (if enabled) will be

cleared, the TO bit will be set and the PD bit will

be cleared.

2. Watchdog Timer wake-up (if WDT was

enabled).

3. Interrupt from GP2/INT pin, GPIO change or a

peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of a device Reset.

The PD bit, which is set on power-up, is cleared when

Sleep is invoked. TO bit is cleared if WDT wake-up

occurred.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

The following peripheral interrupts can wake the device

from Sleep:

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEP instruction. See

Figure 12-10 for more details.

1. Timer1 interrupt. Timer1 must be operating as

an asynchronous counter.

2. ECCP Capture mode interrupt.

3. A/D conversion (when A/D clock source is FRC).

4. EEPROM write operation completion.

5. Comparator output changes state.

6. Interrupt-on-change.

7. External Interrupt from INT pin.

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

DS41211D-page 98

PIC12F683

FIGURE 12-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIE bit

(INTCON<7>)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC – 1)

Inst(0004h)

Note 1:

XT, HS or LP Oscillator mode assumed.

2:

3:

4:

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.

GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

12.8 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP^™for verification purposes.

Note:

The entire data EEPROM and Flash pro-

gram memory will be erased when the

code protection is turned off. See the

“PIC12F6XX/16F6XX Memory

Programming Specification” (DS41204)

for more information.

12.9 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

DS41211D-page 99

PIC12F683

12.10 In-Circuit Serial Programming™

12.11 In-Circuit Debugger

The PIC12F683 microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with five connections for:

Since in-circuit debugging requires access to three

pins, MPLAB^®ICD 2 development with a 14-pin device

is not practical. A special 14-pin PIC12F683 ICD device

is used with MPLAB ICD 2 to provide separate clock,

data and MCLR pins and frees all normally available

pins to the user.

• clock

• data

• power

A special debugging adapter allows the ICD device to

be used in place of a PIC12F683 device. The

debugging adapter is the only source of the ICD device.

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

When the ICD pin on the PIC12F683 ICD device is held

low, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB ICD 2. When the microcontroller has

this feature enabled, some of the resources are not

available for general use. Table 12-9 shows which

features are consumed by the background debugger.

The device is placed into a Program/Verify mode by

holding the GP0 and GP1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH. See the

“PIC12F6XX/16F6XX

Memory

Programming

TABLE 12-9: DEBUGGER RESOURCES

Specification” (DS41204) for more information. GP0

becomes the programming data and GP1 becomes the

programming clock. Both GP0 and GP1 are Schmitt

Trigger inputs in Program/Verify mode.

Resource

Description

Stack

1 level

Program Memory Address 0h must be NOP

700h-7FFh

A typical In-Circuit Serial Programming connection is

shown in Figure 12-11.

For more information, see “MPLAB^®ICD 2 In-Circuit

Debugger User’s Guide” (DS51331), available on

Microchip’s web site (www.microchip.com).

FIGURE 12-11:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

FIGURE 12-12:

14-Pin PDIP

14-PIN ICD PINOUT

To Normal

Connections

External

Connector

Signals

In-Circuit Debug Device

*

PIC12F683

NC

ICDMCLR

VDD

1

2

3

4

5

6

7

ICDCLK

ICDDATA

GND

14

13

12

11

10

9

+5V

0V

VDD

VSS

VPP

MCLR/VPP/GP3

GP5

GP0

GP4

GP1

GP0

CLK

GP3

GP2

Data I/O

ICD

NC

8

*

To Normal

Connections

* Isolation devices (as required)

DS41211D-page 100

PIC12F683

TABLE 13-1: OPCODE FIELD

13.0 INSTRUCTION SET SUMMARY

DESCRIPTIONS

The PIC12F683 instruction set is highly orthogonal and

is comprised of three basic categories:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Bit address within an 8-bit file register

Literal field, constant data or label

k

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 13-1, while the various opcode

fields are summarized in Table 13-1.

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

Table 13-2 lists the instructions recognized by the

MPASM^TMassembler.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

C

Program Counter

Time-out bit

Carry bit

DC

Z

Digit carry bit

Zero bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

PD

Power-down bit

FIGURE 13-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a

nominal instruction execution time of 1 μs. All

instructions are executed within a single instruction

cycle, unless a conditional test is true, or the program

counter is changed as a result of an instruction. When

this occurs, the execution takes two instruction cycles,

with the second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Literal and control operations

General

13

8

7

0

13.1 Read-Modify-Write Operations

OPCODE

k (literal)

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

consequence of clearing the condition that set the RAIF

flag.

DS41211D-page 101

PIC12F683

TABLE 13-2: PIC12F683 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Description

Operands

Status

Affected

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C, DC, Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

Move W to f

No Operation

–

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C, DC, Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

–

k

–

k

–

k

Add literal and W

AND literal with W

Call Subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C, DC, Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO, PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO, PD

11 110x kkkk kkkk C, DC, Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

DS41211D-page 102

PIC12F683

13.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) + k → (W)

C, DC, Z

Operation:

0→ (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the

W register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1→ (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND literal with W

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOPis executed instead, making

this a 2-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

DS41211D-page 103

PIC12F683

CLRWDT

Clear Watchdog Timer

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] CLRWDT

Syntax:

[ label ] BTFSS f,b

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

00h → WDT

0→ WDT prescaler,

1→ TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1→ PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

2-cycle instruction.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

CLRF

Clear f

DECF

Decrement f

Syntax:

[ label ] CLRF

0 ≤ f ≤ 127

f

Syntax:

[ label ] DECF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

00h → (f)

1→ Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are

cleared and the Z bit is set.

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h → (W)

1→ Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

DS41211D-page 104

PIC12F683

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - 1 → (destination);

skip if result = 0

Operation:

(f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the

W register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

DS41211D-page 105

PIC12F683

MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

MOVF

Move f

Syntax:

f

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

Operation:

Status Affected:

Description:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) → (dest)

None

Status Affected:

Description:

Z

Move data from W register to

register ‘f’.

The contents of register f is

moved to a destination dependent

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f

itself. d = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVW

F

OPTION

Before Instruction

OPTION = 0xFF

Words:

1

W

=

0x4F

After Instruction

Cycles:

Example:

OPTION = 0x4F

W

MOVF

FSR, 0

=

0x4F

After Instruction

W

=

value in FSR

register

Z

=

1

MOVLW

Syntax:

Move literal to W

NOP

No Operation

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

[ label ] NOP

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

Words:

None

k → (W)

No operation

Status Affected: None

None

Description:

The eight-bit literal ‘k’ is loaded into

W register. The “don’t cares” will

assemble as ‘0’s.

No operation.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

DS41211D-page 106

PIC12F683

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with literal in W

Syntax:

[ label ] RETLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

TOS → PC,

1→ GIE

k → (W);

TOS → PC

Status Affected:

Description:

None

Status Affected:

Description:

None

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

The W register is loaded with the

eight bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

(INTCON<7>). This is a two-cycle

instruction.

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains

table

Cycles:

Example:

2

;offset value

RETFIE

•

;W now has table value

TABLE

After Interrupt

PC = TOS

GIE =

1

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

DS41211D-page 107

PIC12F683

RLF

Rotate Left f through Carry

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Syntax:

Operands:

[ label ]

RLF f,d

Syntax:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → WDT,

0→ WDT prescaler,

1→ TO,

Operation:

See description below

C

Status Affected:

Description:

0→ PD

The contents of register ‘f’ are

rotated one bit to the left through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

Cycles:

Example:

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

REG1

W

C

=

1110 0110

1100 1100

1

SUBLW

Subtract W from literal

RRF

Rotate Right f through Carry

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

Syntax:

[ label ] RRF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

k - (W) → (W)

Operation:

See description below

C

Status Affected: C, DC, Z

Status Affected:

Description:

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

The contents of register ‘f’ are

rotated one bit to the right through

the Carry flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

C = 0

W > k

C = 1

W ≤ k

DC = 0

DC = 1

W<3:0> > k<3:0>

W<3:0> ≤ k<3:0>

C

Register f

DS41211D-page 108

PIC12F683

SUBWF

Subtract W from f

XORLW

Exclusive OR literal with W

Syntax:

[ label ] SUBWF f,d

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k → (W)

Z

Operation:

(f) - (W) → (destination)

Status Affected: C, DC, Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f.

C = 0

W > f

C = 1

W ≤ f

DC = 0

DC = 1

W<3:0> > f<3:0>

W<3:0> ≤ f<3:0>

SWAPF

Swap Nibbles in f

XORWF

Exclusive OR W with f

Syntax:

[ label ] SWAPF f,d

Syntax:

[ label ] XORWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Operation:

(W) .XOR. (f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Description: The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

DS41211D-page 109

PIC12F683

NOTES:

DS41211D-page 110

PIC12F683

14.1 MPLAB Integrated Development

Environment Software

14.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers are supported with a full

range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

• Drag and drop variables from source to watch

windows

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

- PICkit™ 2 Development Programmer

• Extensive on-line help

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PIC MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

DS41211D-page 111

PIC12F683

14.2 MPASM Assembler

14.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PIC MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

14.6 MPLAB SIM Software Simulator

14.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC^®DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 and PIC24 families of microcontrol-

lers and the dsPIC30 and dsPIC33 family of digital sig-

nal controllers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the hardware laboratory environment, making it an

excellent, economical software development tool.

14.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41211D-page 112

PIC12F683

14.7 MPLAB ICE 2000

High-Performance

14.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PIC

MCUs and can be used to develop for these and other

PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes

the in-circuit debugging capability built into the Flash

devices. This feature, along with Microchip’s In-Circuit

Serial Programming^TM(ICSP^TM) protocol, offers cost-

effective, in-circuit Flash debugging from the graphical

user interface of the MPLAB Integrated Development

Environment. This enables a designer to develop and

debug source code by setting breakpoints, single step-

ping and watching variables, and CPU status and

peripheral registers. Running at full speed enables

testing hardware and applications in real time. MPLAB

ICD 2 also serves as a development programmer for

selected PIC devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PIC

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PIC microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

14.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

14.8 MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC^®and MCU devices. It debugs and

programs PIC^®and dsPIC^®Flash microcontrollers with

the easy-to-use, powerful graphical user interface of the

MPLAB Integrated Development Environment (IDE),

included with each kit.

The MPLAB REAL ICE probe is connected to the design

engineer’s PC using a high-speed USB 2.0 interface and

is connected to the target with either a connector

compatible with the popular MPLAB ICD 2 system

(RJ11) or with the new high speed, noise tolerant, low-

voltage differential signal (LVDS) interconnection

(CAT5).

MPLAB REAL ICE is field upgradeable through future

firmware downloads in MPLAB IDE. In upcoming

releases of MPLAB IDE, new devices will be supported,

and new features will be added, such as software break-

points and assembly code trace. MPLAB REAL ICE

offers significant advantages over competitive emulators

including low-cost, full-speed emulation, real-time

variable watches, trace analysis, complex breakpoints, a

ruggedized probe interface and long (up to three meters)

interconnection cables.

DS41211D-page 113

PIC12F683

14.11 PICSTART Plus Development

Programmer

14.13 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PIC devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

14.12 PICkit 2 Development Programmer

The PICkit™ 2 Development Programmer is a low-cost

programmer and selected Flash device debugger with

an easy-to-use interface for programming many of

Microchip’s baseline, mid-range and PIC18F families of

Flash memory microcontrollers. The PICkit 2 Starter Kit

includes a prototyping development board, twelve

sequential lessons, software and HI-TECH’s PICC™

Lite C compiler, and is designed to help get up to speed

quickly using PIC^®microcontrollers. The kit provides

everything needed to program, evaluate and develop

applications using Microchip’s powerful, mid-range

Flash memory family of microcontrollers.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41211D-page 114

PIC12F683

15.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40° to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V

Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾............................................................................................................................... 800 mW

Maximum current out of VSS pin ...................................................................................................................... 95 mA

Maximum current into VDD pin ......................................................................................................................... 95 mA

Input clamp current, IIK (VI < 0 or VI > VDD)............................................................................................................... 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD)......................................................................................................... 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by GPIO...................................................................................................................... 90 mA

Maximum current sourced GPIO...................................................................................................................... 90 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

DS41211D-page 115

PIC12F683

FIGURE 15-1:

PIC12F683 VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

0

8

10

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

FIGURE 15-2:

HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE

125

85

60

25

0

± 5%

± 2%

± 1%

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

DS41211D-page 116

PIC12F683

15.1 DC Characteristics: PIC12F683-I (Industrial)

PIC12F683-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym

Characteristic

Min Typ† Max Units

Conditions

VDD

Supply Voltage

2.0

3.0

4.5

—

5.5

V

FOSC < = 8 MHz: HFINTOSC, EC

FOSC < = 4 MHz

FOSC < = 10 MHz

D001

D001C

D001D

FOSC < = 20 MHz

D002* VDR

RAM Data Retention

Voltage⁽¹⁾

1.5

—

V

Device in Sleep mode

D003 VPOR

VDD Start Voltage to

ensure internal Power-on

Reset signal

—

VSS

—

V

See Section 12.3.1 “Power-on Reset”

for details.

D004* SVDD

VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05

—

V/ms See Section 12.3.1 “Power-on Reset”

for details.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

DS41211D-page 117

PIC12F683

15.2 DC Characteristics: PIC12F683-I (Industrial)

PIC12F683-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Conditions

Units

Device Characteristics

Min

Typ†

Max

No.

VDD

Note

D010

Supply Current (IDD)^{(1, 2)}

—

11

18

16

28

μA

mA

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

35

54

D011*

D012

D013*

D014

D015

D016*

D017

D018

D019

140

220

380

260

420

0.8

240

380

550

360

650

1.1

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

130

215

360

220

375

0.65

8

220

360

520

340

550

1.0

FOSC = 1 MHz

EC Oscillator mode

FOSC = 4 MHz

EC Oscillator mode

20

FOSC = 31 kHz

LFINTOSC mode

16

40

31

65

340

500

0.8

450

700

1.2

FOSC = 4 MHz

HFINTOSC mode

410

700

1.30

230

400

0.63

2.6

650

950

1.65

400

680

1.1

FOSC = 8 MHz

HFINTOSC mode

FOSC = 4 MHz

EXTRC mode⁽³⁾

3.25

3.35

FOSC = 20 MHz

HS Oscillator mode

2.8

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can

be extended by the formula IR = VDD/2REXT (mA) with REXT in kΩ.

DS41211D-page 118

PIC12F683

15.3 DC Characteristics: PIC12F683-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

DC CHARACTERISTICS

Conditions

Note

Param

No.

Device Characteristics

Min

Typ†

Max

Units

VDD

D020

Power-down Base

Current(IPD)⁽²⁾

—

0.05

0.15

0.35

150

1.0

2.0

3.0

42

1.2

1.5

1.8

500

2.2

4.0

7.0

60

μA

nA

μA

2.0

3.0

5.0

3.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF and

T1OSC disabled

-40°C ≤ TA ≤ +25°C

WDT Current⁽¹⁾

D021

D022

D023

BOR Current⁽¹⁾

85

122

45

32

Comparator Current⁽¹⁾, both

comparators enabled

60

78

120

30

160

36

D024

D025*

D026

D027

CVREF Current⁽¹⁾(high range)

CVREF Current⁽¹⁾(low range)

T1OSC Current⁽¹⁾, 32.768 kHz

45

55

75

95

39

47

59

72

98

124

7.0

8.0

12

4.5

5.0

6.0

0.30

0.36

1.6

1.9

A/D Current⁽¹⁾, no conversion in

progress

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41211D-page 119

PIC12F683

15.4 DC Characteristics: PIC12F683-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Units

Param

No.

Device Characteristics Min

Typ†

Max

VDD

Note

D020E Power-down Base

—

0.05

0.15

0.35

1

9

11

μA

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF and

T1OSC disabled

Current (IPD)⁽²⁾

15

D021E

17.5

19

WDT Current⁽¹⁾

BOR Current⁽¹⁾

2

3

22

D022E

D023E

42

85

32

60

120

30

45

75

39

59

98

4.5

5

65

127

45

Comparator Current⁽¹⁾, both

comparators enabled

78

160

70

D024E

D025E*

D026E

D027E

CVREF Current⁽¹⁾(high range)

CVREF Current⁽¹⁾(low range)

T1OSC Current⁽¹⁾, 32.768 kHz

90

120

91

117

156

25

30

6

40

0.30

0.36

12

A/D Current⁽¹⁾, no conversion in

progress

16

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41211D-page 120

PIC12F683

15.5 DC Characteristics: PIC12F683-I (Industrial)

PIC12F683-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

VIL

Input Low Voltage

I/O Port:

D030

D030A

D031

D032

D033

D033A

with TTL buffer

Vss

VSS

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

0.15 VDD

0.2 VDD

0.3

2.0V ≤ VDD ≤ 4.5V

2.0V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

(1)

MCLR, OSC1 (RC mode)

OSC1 (XT and LP modes)

OSC1 (HS mode)

Input High Voltage

I/O ports:

0.3 VDD

VIH

—

D040

with TTL buffer

2.0

0.25 VDD + 0.8

0.8 VDD

1.6

VDD

V

4.5V ≤ VDD ≤ 5.5V

2.0V ≤ VDD ≤ 4.5V

2.0V ≤ VDD ≤ 5.5V

D040A

D041

with Schmitt Trigger buffer

MCLR

D042

D043

OSC1 (XT and LP modes)

OSC1 (HS mode)

D043A

D043B

0.7 VDD

0.9 VDD

OSC1 (RC mode)

(Note 1)

(2)

IIL

Input Leakage Current

D060

I/O ports

—

0.1

1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

(3)

D061

D063

MCLR

—

0.1

5

μA VSS ≤ VPIN ≤ VDD

OSC1

μA VSS ≤ VPIN ≤ VDD, XT, HS and

LP oscillator configuration

D070* IPUR

VOL

GPIO Weak Pull-up Current

50

—

250

—

400

0.6

—

μA VDD = 5.0V, VPIN = VSS

(5)

Output Low Voltage

D080

I/O ports

V

IOL = 8.5 mA, VDD = 4.5V (Ind.)

IOH = -3.0 mA, VDD = 4.5V (Ind.)

(5)

VOH

Output High Voltage

D090

I/O ports

VDD – 0.7

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.4.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

DS41211D-page 121

PIC12F683

15.5 DC Characteristics: PIC12F683-I (Industrial)

PIC12F683-E (Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Param

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

No.

D100

IULP

Ultra Low-Power Wake-Up

Current

—

200

—

nA See Application Note AN879,

“Using the Microchip Ultra

Low-Power Wake-up Module”

(DS00879)

Capacitive Loading Specs on

Output Pins

D101* COSC2 OSC2 pin

—

15

50

pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101A* CIO

All I/O pins

pF

Data EEPROM Memory

Byte Endurance

VDD for Read/Write

D120

ED

100K

10K

1M

100K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D120A ED

D121

VDRW

VMIN

5.5

V

Using EECON1 to read/write

VMIN = Minimum operating

voltage

D122

D123

TDEW

Erase/Write Cycle Time

Characteristic Retention

—

5

6

ms

TRETD

40

—

Year Provided no other specifications

are violated

D124

TREF

Number of Total Erase/Write

Cycles before Refresh

1M

10M

—

E/W -40°C ≤ TA ≤ +85°C

(4)

Program Flash Memory

Cell Endurance

D130

EP

10K

1K

100K

10K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D130A ED

Cell Endurance

D131

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

D133

D134

VPEW

TPEW

TRETD

VDD for Erase/Write

4.5

—

2

5.5

2.5

—

V

Erase/Write cycle time

Characteristic Retention

ms

40

—

Year Provided no other specifications

are violated

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

4: See Section 10.4.1 “Using the Data EEPROM” for additional information.

5: Including OSC2 in CLKOUT mode.

DS41211D-page 122

PIC12F683

15.6 Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Typ

Units

Conditions

TH01

θ^JA

Thermal Resistance

Junction to Ambient

84.6

163.0

52.4

46.3

41.2

38.8

3.0

°C/W 8-pin PDIP package

°C/W 8-pin SOIC package

°C/W 8-pin DFN-S 4x4x0.9 mm package

°C/W 8-pin DFN-S 6x5 mm package

°C/W 8-pin PDIP package

TH02

θ^JC

Thermal Resistance

Junction to Case

°C/W 8-pin SOIC package

°C/W 8-pin DFN-S 4x4x0.9 mm package

°C/W 8-pin DFN-S 6x5 mm package

2.6

TH03

TH04

TH05

TJ

Junction Temperature

Power Dissipation

150

—

°C

W

For derated power calculations

PD = PINTERNAL + PI/O

PD

PINTERNAL Internal Power Dissipation

—

PINTERNAL = IDD x VDD

(NOTE 1)

TH06

TH07

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O = Σ (IOL * VOL) + Σ (IOH * (VDD - VOH))

PDER = (TJ - TA)/θJA

(NOTE 2, 3)

PDER

Note 1: IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature.

3: Maximum allowable power dissipation is the lower value of either the absolute maximum total power

dissipation or derated power (PDER).

DS41211D-page 123

PIC12F683

15.7

Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O PORT

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 15-3:

LOAD CONDITIONS

Load Condition

CL

VSS

Legend: CL

=

50 pF for all pins

15 pF for OSC2 output

DS41211D-page 124

PIC12F683

15.8 AC Characteristics: PIC12F683 (Industrial, Extended)

FIGURE 15-4:

CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1/CLKIN

OS02

OS04

OS03

OSC2/CLKOUT

(LP,XT,HS Modes)

OSC2/CLKOUT

(CLKOUT Mode)

TABLE 15-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

(1)

OS01

OS02

OS03

FOSC

TOSC

TCY

External CLKIN Frequency

DC

—

37

kHz LP Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz EC Oscillator mode

kHz LP Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz RC Oscillator mode

4

—

20

—

20

(1)

Oscillator Frequency

32.768

—

0.1

1

4

—

20

DC

27

250

50

—

4

(1)

External CLKIN Period

—

•

μs

ns

μs

ns

μs

ns

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

EC Oscillator mode

LP Oscillator mode

XT Oscillator mode

HS Oscillator mode

RC Oscillator mode

TCY = 4/FOSC

—

•

—

•

—

•

(1)

Oscillator Period

30.5

—

250

50

250

200

2

10,000

—

1,000

—

DC

—

•

—

(1)

Instruction Cycle Time

TCY

—

OS04* TosH, External CLKIN High,

TosL External CLKIN Low

LP oscillator

100

20

0

—

XT oscillator

—

HS oscillator

OS05* TosR, External CLKIN Rise,

TosF External CLKIN Fall

—

LP oscillator

0

—

•

XT oscillator

0

—

•

HS oscillator

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and

are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for

all devices.

DS41211D-page 125

PIC12F683

TABLE 15-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Freq.

Tolerance

Characteristic

Min

Typ†

Max

Units

TOSC Slowest clock

ms LFINTOSC/64

Conditions

OS06

OS07

OS08

TWARM

Internal Oscillator Switch

—

2

(3)

when running

TSC

Fail-Safe Sample Clock

—

21

—

(1)

Period

HFOSC

Internal Calibrated

HFINTOSC Frequency

1%

2%

7.92

7.84

8.0

8.08

8.16

MHz VDD = 3.5V, 25°C

(2)

MHz 2.5V ≤ VDD ≤ 5.5V,

0°C ≤ TA ≤ +85°C

5%

—

7.60

15

8.0

31

8.40

45

MHz 2.0V ≤ VDD ≤ 5.5V,

-40°C ≤ TA ≤ +85°C (Ind.),

-40°C ≤ TA ≤ +125°C (Ext.)

OS09*

OS10*

LFOSC

Internal Uncalibrated

LFINTOSC Frequency

kHz

TIOSC

ST

HFINTOSC Oscillator

Wake-up from Sleep

Start-up Time

—

5.5

3.5

3

12

7

24

14

11

μs

VDD = 2.0V, -40°C to +85°C

VDD = 3.0V, -40°C to +85°C

VDD = 5.0V, -40°C to +85°C

6

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min” values with an external

clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)

for all devices.

2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the

device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.

3: By design.

DS41211D-page 126

PIC12F683

FIGURE 15-5:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

Fosc

OS12

OS18

OS11

OS20

OS21

CLKOUT

OS19

OS13

OS16

OS17

I/O pin

(Input)

OS14

OS15

I/O pin

(Output)

New Value

Old Value

OS18, OS19

TABLE 15-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ† Max Units

Conditions

OS11

OS12

OS13

OS14

TOSH2CKL FOSC↑ to CLKOUT↓ ⁽¹⁾

TOSH2CKH FOSC↑ to CLKOUT↑ ⁽¹⁾

—

70

72

20

—

70

—

ns VDD = 5.0V

—

50

—

ns VDD = 5.0V

ns

TCKL2IOV

TIOV2CKH Port input valid before CLKOUT↑⁽¹⁾

CLKOUT↓ to Port out valid⁽¹⁾

TOSC + 200 ns

ns

OS15* TOSH2IOV FOSC↑ (Q1 cycle) to Port out valid

—

ns VDD = 5.0V

OS16

OS17

OS18

OS19

TOSH2IOI

FOSC↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

50

TIOV2OSH Port input valid to FOSC↑ (Q2 cycle)

20

—

ns

(I/O in setup time)

TIOR

TIOF

Port output rise time⁽²⁾

—

15

40

72

32

ns VDD = 2.0V

VDD = 5.0V

Port output fall time⁽²⁾

—

28

15

55

30

ns VDD = 2.0V

VDD = 5.0V

OS20* TINP

OS21* TGPP

INT pin input high or low time

25

—

ns

GPIO interrupt-on-change new input

level time

TCY

*

These parameters are characterized but not tested.

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated.

†

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

2: Includes OSC2 in CLKOUT mode.

DS41211D-page 127

PIC12F683

FIGURE 15-6:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Start-Up Time

(1)

Internal Reset

Watchdog Timer

(1)

Reset

31

34

I/O pins

Note 1: Asserted low.

FIGURE 15-7:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR + VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

37

Reset

(due to BOR)

33*

*

64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’.

DS41211D-page 128

PIC12F683

TABLE 15-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

TMCL

Characteristic

Min

Typ†

Max Units

Conditions

30

MCLR Pulse Width (low)

2

5

—

μs VDD = 5V, -40°C to +85°C

μs VDD = 5V

31

32

TWDT

TOST

Watchdog Timer Time-out

Period (No Prescaler)

10

16

29

31

ms VDD = 5V, -40°C to +85°C

ms VDD = 5V

Oscillation Start-up Timer

Period^{(1, 2)}

—

1024

—

TOSC (NOTE 3)

33*

34*

TPWRT Power-up Timer Period

40

—

65

—

140

2.0

ms

TIOZ

I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

μs

35

VBOR

VHYST

TBOR

Brown-out Reset Voltage

2.0

—

50

—

2.2

—

V

(NOTE 4)

36*

37*

Brown-out Reset Hysteresis

mV

Brown-out Reset Minimum

Detection Period

100

—

μs VDD ≤ VBOR

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at “min” values

with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time

limit is “DC” (no clock) for all devices.

2: By design.

3: Period of the slower clock.

4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as

possible. 0.1 μF and 0.01 μF values in parallel are recommended.

DS41211D-page 129

PIC12F683

FIGURE 15-8:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 15-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

40*

41*

42*

TT0H

TT0L

TT0P

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale value

(2, 4, ..., 256)

45*

46*

47*

TT1H

TT1L

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Time

Synchronous,

with Prescaler

Asynchronous

30

0.5 TCY + 20

15

—

ns

T1CKI Low Synchronous, No Prescaler

Time

Synchronous,

with Prescaler

Asynchronous

30

—

ns

TT1P

FT1

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale value

(1, 2, 4, 8)

Asynchronous

60

—

ns

48

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.768

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS41211D-page 130

PIC12F683

FIGURE 15-9:

CAPTURE/COMPARE/PWM TIMINGS (ECCP)

CCP1

(Capture mode)

CC01

CC02

CC03

Note:

Refer to Figure 15-3 for load conditions.

TABLE 15-6: CAPTURE/COMPARE/PWM REQUIREMENTS (ECCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ† Max Units

Conditions

CC01* TccL

CC02* TccH

CC03* TccP

CCP1 Input Low Time

CCP1 Input High Time

CCP1 Input Period

No Prescaler

0.5TCY + 20

20

—

ns

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

20

3TCY + 40

N

ns N = prescale

value (1, 4 or

16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41211D-page 131

PIC12F683

TABLE 15-7: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristics

Min Typ†

Max

Units

Comments

CM01 VOS

CM02 VCM

CM03* CMRR

CM04* TRT

Input Offset Voltage

—

0

5.0

—

10

VDD – 1.5

—

mV (VDD - 1.5)/2

Input Common Mode Voltage

Common Mode Rejection Ratio

Response Time

V

+55

—

dB

Falling

Rising

150

200

—

600

ns

μs

(NOTE 1)

—

1000

10

CM05* TMC2COV Comparator Mode Change to

Output Valid

—

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Response time is measured with one comparator input at (VDD - 1.5)/2 - 100 mV to (VDD - 1.5)/2 + 20 mV.

TABLE 15-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Sym

No.

Characteristics

Min

Typ†

Max

Units

Comments

CV01* CLSB

Step Size⁽²⁾

Absolute Accuracy

—

VDD/24

VDD/32

—

V

Low Range (VRR = 1)

High Range (VRR = 0)

CV02* CACC

—

1/2

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

CV03* CR

CV04* CST

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

2k

—

Ω

μs

10

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.

2: See Section 8.11 “Comparator Voltage Reference” for more information.

DS41211D-page 132

PIC12F683

TABLE 15-9: PIC12F683 A/D CONVERTER (ADC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

AD01 NR

AD02 EIL

AD03 EDL

Resolution

—

10 bits

bit

Integral Error

—

1

LSb VREF = 5.12V

Differential Error

LSb No missing codes to 10 bits

VREF = 5.12V

AD04 EOFF Offset Error

AD07 EGN Gain Error

AD06 VREF Reference Voltage⁽³⁾

—

1

LSb VREF = 5.12V

2.2

2.7

—

VDD

V

AD06A

Absolute minimum to ensure 1 LSb

accuracy

AD07 VAIN Full-Scale Range

VSS

—

VREF

10

V

AD08 ZAIN Recommended

Impedance of Analog

Voltage Source

kΩ

AD09* IREF

VREF Input Current⁽³⁾

10

—

1000

50

μA During VAIN acquisition.

Based on differential of VHOLD to VAIN.

μA During A/D conversion cycle.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Total Absolute Error includes integral, differential, offset and gain errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: ADC VREF is from external VREF or VDD pin, whichever is selected as reference input.

4: When ADC is off, it will not consume any current other than leakage current. The power-down current

specification includes any such leakage from the ADC module.

DS41211D-page 133

PIC12F683

TABLE 15-10: PIC12F683 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristic

A/D Clock Period

Min

Typ†

Max Units

Conditions

AD130* TAD

1.6

3.0

—

9.0

μs TOSC-based, VREF ≥ 3.0V

μs TOSC-based, VREF full range

A/D Internal RC

Oscillator Period

ADCS<1:0> = 11(ADRC mode)

μs At VDD = 2.5V

3.0

1.6

—

6.0

4.0

11

9.0

6.0

—

μs At VDD = 5.0V

AD131 TCNV Conversion Time

(not including

TAD Set GO/DONE bit to new data in A/D

Result register.

Acquisition Time)⁽¹⁾

AD132* TACQ Acquisition Time

11.5

—

5

μs

—

AD133* TAMP Amplifier Settling Time

AD134 TGO Q4 to A/D Clock Start

—

TOSC/2

—

TOSC/2 + TCY

—

If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock starts. This allows the SLEEP

instruction to be executed.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Section 9.3 “A/D Acquisition Requirements” for minimum conditions.

DS41211D-page 134

PIC12F683

FIGURE 15-10:

PIC12F683 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

AD134

1 TCY

(1)

(TOSC/2

)

AD131

Q4

AD130

A/D CLK

A/D Data

9

8

7

6

3

2

1

0

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

FIGURE 15-11:

PIC12F683 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

Q4

(1)

(TOSC/2 + TCY

)

1 TCY

AD131

AD130

A/D CLK

A/D Data

9

8

7

3

2

1

0

6

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

DS41211D-page 135

PIC12F683

NOTES:

DS41211D-page 136

PIC12F683

16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein are

not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range.

FIGURE 16-1:

TYPICAL IDD vs. FOSC OVER VDD (EC MODE)

3.5

Typical: Statistical Mean @25°C

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

DS41211D-page 137

PIC12F683

FIGURE 16-2:

MAXIMUM IDD vs. FOSC OVER VDD (EC MODE)

4.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.0V

3.0V

2.0V

1 MHz

2 MHz

4 MHz

6 MHz

8 MHz

10 MHz 12 MHz 14 MHz 16 MHz 18 MHz 20 MHz

FOSC

FIGURE 16-3:

TYPICAL IDD vs. FOSC OVER VDD (HS MODE)

Typical IDD vs. FOSC Over Vdd

HS Mode

4.0

Typical: Statistical Mean @25°C

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

DS41211D-page 138

PIC12F683

FIGURE 16-4:

MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)

Maximum IDD vs. FOSC Over Vdd

HS Mode

5.0

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

4 MHz

10 MHz

16 MHz

20 MHz

FOSC

FIGURE 16-5:

TYPICAL IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

900

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

800

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 139

PIC12F683

FIGURE 16-6:

MAXIMUM IDD vs. VDD OVER FOSC (XT MODE)

XT Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-7:

TYPICAL IDD vs. VDD OVER FOSC (EXTRC MODE)

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

700

600

500

400

300

200

100

0

4 MHz

1 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 140

PIC12F683

FIGURE 16-8:

MAXIMUM IDD vs. VDD (EXTRC MODE)

EXTRC Mode

1,400

1,200

1,000

800

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

4 MHz

1 MHz

600

400

200

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-9:

IDD vs. VDD OVER FOSC (LFINTOSC MODE, 31 kHz)

LFINTOSC Mode, 31KHZ

80

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

70

60

50

40

30

20

10

0

Maximum

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 141

PIC12F683

FIGURE 16-10:

IDD vs. VDD (LP MODE)

70

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

60

50

40

30

20

10

0

32 kHz Maximum

32 kHz Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-11:

TYPICAL IDD vs. FOSC OVER VDD (HFINTOSC MODE)

1,600

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

1,400

1,200

1,000

800

5.0V

4.0V

3.0V

2.0V

600

400

200

0

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

8 MHz

FOSC

DS41211D-page 142

PIC12F683

FIGURE 16-12:

MAXIMUM IDD vs. FOSC OVER VDD (HFINTOSC MODE)

HFINTOSC

2,000

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

5.5V

5.0V

1,800

1,600

1,400

1,200

1,000

800

4.0V

3.0V

600

2.0V

400

200

0

125 kHz

250 kHz

500 kHz

1 MHz

2 MHz

4 MHz

8 MHz

FOSC

FIGURE 16-13:

TYPICAL IPD vs. VDD (SLE_TE_yP_piM_caO_lDE, ALL PERIPHERALS DISABLED)

(Sleep Mode all Peripherals Disabled)

0.45

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 143

PIC12F683

FIGURE 16-14:

MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)

Maximum

(Sleep Mode all Peripherals Disabled)

18.0

Typical: Statistical Mean @25°C

Maximum: Mean + 3σ

16.0

14.0

12.0

10.0

8.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 125°C

6.0

4.0

Max. 85°C

3.5

2.0

0.0

2.0

2.5

3.0

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-15:

COMPARATOR IPD vs. VDD (BOTH COMPARATORS ENABLED)

180

160

140

120

100

80

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Maximum

Typical

60

40

20

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 144

PIC12F683

FIGURE 16-16:

BOR IPD vs. VDD OVER TEMPERATURE

160

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

140

120

100

80

Maximum

Typical

60

40

20

0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-17:

TYPICAL WDT IPD vs. VDD OVER TEMPERATURE

Typical

3.0

TTyyppicicaal:l:SSttaattisistticicaallMMeeaann@@2255°°CC

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

2.5

2.0

1.5

1.0

0.5

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 145

PIC12F683

FIGURE 16-18:

MAXIMUM WDT IPD vs. VDD OVER TEMPERATURE

Maximum

25.0

20.0

15.0

10.0

5.0

Max. 125°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Max. 85°C

0.0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-19:

WDT PERIOD vs. VDD OVER TEMPERATURE

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Max. (125°C)

Max. (85°C)

Typical

Minimum

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 146

PIC12F683

FIGURE 16-20:

WDT PERIOD vs. TEMPER_VA_dT_dU₌R₅E_VOVER VDD (5.0V)

30

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

28

26

24

22

20

18

16

14

12

10

Maximum

Typical

Minimum

-40°C

25°C

85°C

125°C

Temperature (°C)

FIGURE 16-21:

CVREF IPD vs. VDD OVER_HT_igE_hM_RP_aE_ngR_eATURE (HIGH RANGE)

140

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

120

100

80

60

40

20

0

Max. 125°C

Max. 85°C

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 147

PIC12F683

FIGURE 16-22:

CVREF IPD vs. VDD OVER TEMPERATURE (LOW RANGE)

180

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

160

140

120

100

80

Max. 125°C

Max. 85°C

Typical

60

40

20

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-23:

VOL vs. IOL OVER TEMPERATURE (VDD = 3.0V)

(VDD = 3V, -40×C TO 125×C)

0.8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Max. 125°C

Max. 85°C

Typical 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

DS41211D-page 148

PIC12F683

FIGURE 16-24:

VOL vs. IOL OVER TEMPERATURE (VDD = 5.0V)

0.45

Typical: Statistical Mean @25°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Typical: Statistical Mean @25×C

Maximum: Mean (Worst-case Temp) + 3σ

Maximum: Mean(s-4+0×3C to 125×C)

(-40°C to 125°C)

Max. 125°C

Max. 85°C

Typ. 25°C

Min. -40°C

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

IOL (mA)

FIGURE 16-25:

VOH vs. IOH OVER TEMPERATURE (VDD = 3.0V)

3.5

3.0

2.5

2.0

1.5

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

IOH (mA)

DS41211D-page 149

PIC12F683

FIGURE 16-26:

VOH vs. IOH OVER TEMPERATURE (VDD = 5.0V)

5.5

5.0

4.5

4.0

Max. -40°C

Typ. 25°C

Min. 125°C

Typical: Statistical Mean @25°C

3.5

3.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

-4.0

-4.5

-5.0

IOH (mA)

FIGURE 16-27:

TTL INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(TTL Input, -40×C TO 125×C)

1.7

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

1.5

1.3

1.1

0.9

0.7

0.5

Max. -40°C

Typ. 25°C

Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 150

PIC12F683

FIGURE 16-28:

SCHMITT TRIGGER INPUT THRESHOLD VIN vs. VDD OVER TEMPERATURE

(ST Input, -40×C TO 125×C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

VIH Max. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

VIH Min. -40°C

VIL Max. -40°C

VIL Min. 125°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-29:

T1OSC IPD vs. VDD OVER TEMPERATURE (32 kHz)

45.0

Typical: Statistical Mean @25°C

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

Maximum: Mean(-4+03×C to 125×C)

Max. 125°C

Max. 85°C

Typ. 25°C

3.5

0.0

2.0

2.5

3.0

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 151

PIC12F683

FIGURE 16-30:

COMPARATOR RESPONSE TIME (RISING EDGE)

531

806

1000

900

800

700

Max. 125°C

Max. 85°C

VCM = VDD - 1.5V)/2

V+ input = VCM

V- input = Transition from VCM + 100MV to VCM - 20MV

Note:

600

500

400

300

200

100

Typ. 25°C

Min. -40°C

0

2.0

2.5

4.0

5.5

VDD (V)

FIGURE 16-31:

COMPARATOR RESPONSE TIME (FALLING EDGE)

1000

900

800

700

Max. 125°C

Max. 85°C

VCM = VDD - 1.5V)/2

600

500

400

300

200

100

0

Note:

V+ input = VCM

V- input = Transition from VCM - 100MV to VCM + 20MV

Typ. 25°C

Min. -40°C

2.0

2.5

4.0

5.5

VDD (V)

DS41211D-page 152

PIC12F683

FIGURE 16-32:

LFINTOSC FREQUENCY vs. VDD OVER TEMPERATURE (31 kHz)

LFINTOSC 31Khz

45,000

40,000

35,000

30,000

25,000

20,000

15,000

10,000

5,000

Max. -40°C

Typ. 25°C

Min. 85°C

Min. 125°C

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-33:

ADC CLOCK PERIOD vs. VDD OVER TEMPERATURE

8

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

125°C

85°C

6

4

2

0

25°C

-40°C

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 153

PIC12F683

FIGURE 16-34:

TYPICAL HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

16

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

14

85°C

12

25°C

10

-40°C

8

6

4

2

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-35:

MAXIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

-40C to +85C

25

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

20

15

10

5

85°C

25°C

-40°C

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 154

PIC12F683

FIGURE 16-36:

MINIMUM HFINTOSC START-UP TIMES vs. VDD OVER TEMPERATURE

10

9

Typical: Statistical Mean @25°C

Maximum: Mean (Worst-case Temp) + 3σ

(-40°C to 125°C)

8

7

85°C

6

25°C

5

-40°C

4

3

2

1

0

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-37:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (25°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 155

PIC12F683

FIGURE 16-38:

TYPICAL HFINTOSC FREQUENCY CHANGE OVER DEVICE VDD (85°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 16-39:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (125°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 156

PIC12F683

FIGURE 16-40:

TYPICAL HFINTOSC FREQUENCY CHANGE vs. VDD (-40°C)

5

4

3

2

1

0

-1

-2

-3

-4

-5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

VDD (V)

DS41211D-page 157

PIC12F683

NOTES:

DS41211D-page 158

PIC12F683

17.0 PACKAGING INFORMATION

17.1 Package Marking Information

8-Lead PDIP

Example

12F683

XXXXXXXX

XXXXXNNN

YYWW

e

3

I/P

017

0415

8-Lead SOIC (3.90 mm)

Example

12F683

e

3

XXXXXXXX

XXXXYYWW

I/SN0415

017

NNN

8-Lead DFN (4x4x0.9 mm)

Example

XXXXXX

YYWW

NNN

12F683

e3

I/MD

0415

017

8-Lead DFN-S (6x5 mm)

Example

XXXXXXX

XXYYWW

NNN

12F683

I/MF

0415

e

3

017

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PIC^®device marking consists of Microchip part number, year code, week code and traceability

code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip

Sales Office. For QTP devices, any special marking adders are included in QTP price.

DS41211D-page 159

PIC12F683

17.2 Package Details

The following sections give the technical details of the packages.

8-Lead Plastic Dual In-Line (P or PA) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

Units

INCHES

Dimension Limits

MIN

NOM

8

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.348

.115

.008

.040

.014

–

.130

–

.310

.250

.365

.130

.010

.060

.018

–

.325

.280

.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-018B

DS41211D-page 160

PIC12F683

8-Lead Plastic Small Outline (SN or OA) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff

A2

A1

E

1.25

0.10

–

§

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

3.90 BSC

4.90 BSC

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-057B

DS41211D-page 161

PIC12F683

8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

b

N

L

E

E2

K

EXPOSED

PAD

1

2

1

NOTE 1

D2

BOTTOM VIEW

TOP VIEW

A3

A

A1

NOTE 2

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

8

0.80 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

D

0.02

Contact Thickness

Overall Length

Exposed Pad Width

Overall Width

0.20 REF

4.00 BSC

2.20

E2

E

0.00

2.80

4.00 BSC

3.00

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

D2

b

0.00

0.25

0.30

0.20

3.60

0.35

0.65

–

0.30

L

0.55

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Package is saw singulated.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-131C

DS41211D-page 162

PIC12F683

8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S]

PUNCH SINGULATED

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

e

L

D1

b

N

K

E

E2

E1

EXPOSED

PAD

NOTE 1

1

2

1

NOTE 1

D2

TOP VIEW

BOTTOM VIEW

φ

A2

A

A3

A1

NOTE 2

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

8

1.27 BSC

0.85

Overall Height

A

–

1.00

0.80

0.05

Molded Package Thickness

Standoff

A2

A1

A3

D

0.65

0.00

0.01

Base Thickness

0.20 REF

4.92 BSC

4.67 BSC

4.00

Overall Length

Molded Package Length

Exposed Pad Length

Overall Width

D1

D2

E

3.85

4.15

5.99 BSC

5.74 BSC

2.31

Molded Package Width

Exposed Pad Width

Contact Width

E1

E2

b

2.16

0.35

0.50

0.20

–

2.46

0.47

0.75

–

0.40

Contact Length

L

0.60

Contact-to-Exposed Pad

Model Draft Angle Top

K

–

φ

–

12°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-113B

DS41211D-page 163

PIC12F683

NOTES:

DS41211D-page 164

PIC12F683

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PIC^®

DEVICES

Revision A

This discusses some of the issues in migrating from

other PIC devices to the PIC12F683 device.

This is a new data sheet.

Revision B

B.1

PIC16F676 to PIC12F683

TABLE B-1:

Feature

FEATURE COMPARISON

Rewrites of the Oscillator and Special Features of the

CPU sections. General corrections to Figures and

formatting.

PIC16F676

PIC12F683

Max Operating

Speed

20 MHz

Revision C

Max Program

Memory (Words)

1024

2048

Revisions throughout document. Incorporated Golden

Chapters.

SRAM (bytes)

A/D Resolution

64

128

10-bit

256

10-bit

128

Revision D

Data EEPROM

(Bytes)

Replaced Package Drawings; Revised Product ID

Section (SN package to 3.90 mm); Replaced PICmicro

with PIC; Replaced Dev Tool Section.

Timers (8/16-bit)

Oscillator Modes

Brown-out Reset

Internal Pull-ups

1/1

8

2/1

8

Y

RA0/1/2/4/5 GP0/1/2/4/5,

MCLR

Interrupt-on-change RA0/1/2/3/4/5 GP0/1/2/3/4/5

Comparator

ECCP

1

N

1

N

Y

Ultra Low-Power

Wake-Up

Extended WDT

N

Y

Software Control

Option of WDT/BOR

INTOSC

Frequencies

4 MHz

N

32 kHz-

8 MHz

Clock Switching

Y

Note: This device has been designed to perform

to the parameters of its data sheet. It has

been tested to an electrical specification

designed to determine its conformance

with these parameters. Due to process

differences in the manufacture of this

device, this device may have different

performance characteristics than its earlier

version. These differences may cause this

device to perform differently in your

application than the earlier version of this

device.

DS41211D-page 165

PIC12F683

NOTES:

DS41211D-page 166

PIC12F683

INDEX

Timer2 ........................................................................ 49

TMR0/WDT Prescaler ................................................ 41

Watchdog Timer (WDT).............................................. 96

Brown-out Reset (BOR)...................................................... 87

Associated.................................................................. 88

Calibration .................................................................. 87

Specifications ........................................................... 129

Timing and Characteristics....................................... 128

A

A/D

Specifications.................................................... 133, 134

Absolute Maximum Ratings .............................................. 115

AC Characteristics

Industrial and Extended ............................................ 125

Load Conditions........................................................ 124

ADC .................................................................................... 61

Acquisition Requirements ........................................... 67

Associated registers.................................................... 69

Block Diagram............................................................. 61

Calculating Acquisition Time....................................... 67

Channel Selection....................................................... 61

Configuration............................................................... 61

Configuring Interrupt ................................................... 64

Conversion Clock........................................................ 62

Conversion Procedure ................................................ 64

GPIO Configuration..................................................... 61

Internal Sampling Switch (RSS) IMPEDANCE ................ 67

Interrupts..................................................................... 63

Operation .................................................................... 63

Operation During Sleep .............................................. 64

Reference Voltage (VREF)........................................... 62

Result Formatting........................................................ 63

Source Impedance...................................................... 67

Special Event Trigger.................................................. 64

Starting an A/D Conversion ........................................ 63

ADCON0 Register............................................................... 65

ADRESH Register (ADFM = 0)........................................... 66

ADRESH Register (ADFM = 1)........................................... 66

ADRESL Register (ADFM = 0)............................................ 66

ADRESL Register (ADFM = 1)............................................ 66

Analog Input Connection Considerations............................ 52

Analog-to-Digital Converter. See ADC

C

C Compilers

MPLAB C18.............................................................. 112

MPLAB C30.............................................................. 112

Calibration Bits.................................................................... 85

Capture Module. See Capture/Compare/PWM (CCP)

Capture/Compare/PWM (CCP) .......................................... 75

Associated registers w/ Capture, Compare

and Timer1 ......................................................... 81

Associated registers w/ PWM and Timer2.................. 81

Capture Mode............................................................. 76

CCPx Pin Configuration.............................................. 76

Compare Mode........................................................... 77

CCPx Pin Configuration...................................... 77

Software Interrupt Mode............................... 76, 77

Special Event Trigger......................................... 77

Timer1 Mode Selection................................. 76, 77

Prescaler .................................................................... 76

PWM Mode................................................................. 78

Duty Cycle .......................................................... 79

Effects of Reset.................................................. 80

Example PWM Frequencies and

Resolutions, 20 MHZ.................................. 79

Example PWM Frequencies and

Resolutions, 8 MHz .................................... 79

Operation in Sleep Mode.................................... 80

Setup for Operation ............................................ 80

System Clock Frequency Changes .................... 80

PWM Period ............................................................... 79

Setup for PWM Operation .......................................... 80

Timer Resources ........................................................ 75

CCP. See Capture/Compare/PWM (CCP)

ANSEL Register.................................................................. 33

Assembler

MPASM Assembler................................................... 112

B

Block Diagrams

(CCP) Capture Mode Operation ................................. 76

ADC ............................................................................ 61

ADC Transfer Function ............................................... 68

Analog Input Model............................................... 52, 68

CCP PWM................................................................... 78

Clock Source............................................................... 19

Comparator................................................................. 51

Compare ..................................................................... 77

Crystal Operation........................................................ 22

External RC Mode....................................................... 23

Fail-Safe Clock Monitor (FSCM)................................. 29

GP1 Pin....................................................................... 37

GP2 Pin....................................................................... 37

GP3 Pin....................................................................... 38

GP4 Pin....................................................................... 38

GP5 Pin....................................................................... 39

In-Circuit Serial Programming Connections.............. 100

Interrupt Logic............................................................. 93

MCLR Circuit............................................................... 86

On-Chip Reset Circuit................................................. 85

PIC12F683.................................................................... 5

Resonator Operation................................................... 22

Timer1......................................................................... 44

CCP1CON Register............................................................ 75

Clock Sources

External Modes........................................................... 21

EC ...................................................................... 21

HS ...................................................................... 22

LP....................................................................... 22

OST .................................................................... 21

RC ...................................................................... 23

XT....................................................................... 22

Internal Modes............................................................ 23

Frequency Selection........................................... 25

HFINTOSC ......................................................... 23

INTOSC.............................................................. 23

INTOSCIO .......................................................... 23

LFINTOSC.......................................................... 25

Clock Switching .................................................................. 27

Code Examples

A/D Conversion .......................................................... 64

Assigning Prescaler to Timer0.................................... 42

Assigning Prescaler to WDT....................................... 42

Changing Between Capture Prescalers ..................... 76

Data EEPROM Read.................................................. 73

Data EEPROM Write.................................................. 73

DS41211D-page 167

PIC12F683

Indirect Addressing .....................................................18

Initializing GPIO ..........................................................31

Saving STATUS and W Registers in RAM .................95

Ultra Low-Power Wake-up Initialization ......................35

Write Verify .................................................................73

Code Protection ..................................................................99

Comparator .........................................................................51

C2OUT as T1 Gate .....................................................57

Configurations.............................................................53

I/O Operating Modes...................................................53

Interrupts.....................................................................55

Operation .............................................................. 51, 54

Operation During Sleep ..............................................56

Response Time...........................................................54

Synchronizing COUT w/Timer1 ..................................57

Comparator Module

F

Fail-Safe Clock Monitor ...................................................... 29

Fail-Safe Condition Clearing....................................... 29

Fail-Safe Detection ..................................................... 29

Fail-Safe Operation..................................................... 29

Reset or Wake-up from Sleep .................................... 29

Firmware Instructions ....................................................... 101

Fuses. See Configuration Bits

G

General Purpose Register File ............................................. 8

GPIO................................................................................... 31

Additional Pin Functions ............................................. 32

ANSEL Register ................................................. 32

Interrupt-on-Change ........................................... 32

Ultra Low-Power Wake-up............................ 32, 35

Weak Pull-up ...................................................... 32

Associated Registers.................................................. 39

GP0 ............................................................................ 36

GP1 ............................................................................ 37

GP2 ............................................................................ 37

GP3 ............................................................................ 38

GP4 ............................................................................ 38

GP5 ............................................................................ 39

Pin Descriptions and Diagrams .................................. 36

Specifications ........................................................... 127

GPIO Register .................................................................... 31

Associated registers....................................................59

Comparator Voltage Reference (CVREF)

Response Time...........................................................54

Comparator Voltage Reference (CVREF) ............................58

Effects of a Reset........................................................56

Specifications............................................................132

Comparators

C2OUT as T1 Gate .....................................................45

Effects of a Reset........................................................56

Specifications............................................................132

Compare Module. See Capture/Compare/PWM (CCP)

CONFIG Register................................................................84

Configuration Bits................................................................83

CPU Features .....................................................................83

Customer Change Notification Service .............................171

Customer Notification Service...........................................171

Customer Support.............................................................171

I

ID Locations........................................................................ 99

In-Circuit Debugger........................................................... 100

In-Circuit Serial Programming (ICSP)............................... 100

Indirect Addressing, INDF and FSR Registers ................... 18

Instruction Format............................................................. 101

Instruction Set................................................................... 101

ADDLW..................................................................... 103

ADDWF..................................................................... 103

ANDLW..................................................................... 103

ANDWF..................................................................... 103

BCF .......................................................................... 103

BSF........................................................................... 103

BTFSC...................................................................... 103

BTFSS ...................................................................... 104

CALL......................................................................... 104

CLRF ........................................................................ 104

CLRW ....................................................................... 104

CLRWDT .................................................................. 104

COMF ....................................................................... 104

DECF........................................................................ 104

DECFSZ ................................................................... 105

GOTO ....................................................................... 105

INCF ......................................................................... 105

INCFSZ..................................................................... 105

IORLW...................................................................... 105

IORWF...................................................................... 105

MOVF ....................................................................... 106

MOVLW .................................................................... 106

MOVWF.................................................................... 106

NOP.......................................................................... 106

RETFIE..................................................................... 107

RETLW ..................................................................... 107

RETURN................................................................... 107

RLF........................................................................... 108

RRF .......................................................................... 108

SLEEP ...................................................................... 108

D

Data EEPROM Memory

Associated Registers ..................................................74

Code Protection .................................................... 71, 74

Data Memory Organization ...................................................7

Map of the PIC12F683..................................................8

DC and AC Characteristics

Graphs and Tables ...................................................137

DC Characteristics

Extended and Industrial ............................................121

Industrial and Extended ............................................117

Development Support .......................................................111

Device Overview ...................................................................5

E

EEADR Register .................................................................71

EECON1 Register...............................................................72

EECON2 Register...............................................................72

EEDAT Register..................................................................71

EEPROM Data Memory

Avoiding Spurious Write..............................................74

Reading.......................................................................73

Write Verify .................................................................73

Writing.........................................................................73

Effects of Reset

PWM mode .................................................................80

Electrical Specifications ....................................................115

Enhanced Capture/Compare/PWM (ECCP)

Specifications............................................................131

Errata ....................................................................................3

DS41211D-page 168

PIC12F683

SUBLW ..................................................................... 108

SUBWF..................................................................... 109

SWAPF ..................................................................... 109

XORLW..................................................................... 109

XORWF..................................................................... 109

INTCON Register................................................................ 14

Internal Oscillator Block

Oscillator Switching

Fail-Safe Clock Monitor .............................................. 29

Two-Speed Clock Start-up ......................................... 27

OSCTUNE Register............................................................ 24

P

Packaging......................................................................... 159

Details....................................................................... 160

Marking..................................................................... 159

PCL and PCLATH............................................................... 18

Computed GOTO ....................................................... 18

Stack........................................................................... 18

PCON Register............................................................. 17, 88

PICSTART Plus Development Programmer..................... 114

PIE1 Register ..................................................................... 15

Pin Diagram.......................................................................... 2

Pinout Descriptions

PIC12F683 ................................................................... 6

PIR1 Register ..................................................................... 16

Power-Down Mode (Sleep)................................................. 98

Power-On Reset (POR)...................................................... 86

Power-up Timer (PWRT).................................................... 86

Specifications ........................................................... 129

Precision Internal Oscillator Parameters .......................... 127

Prescaler

INTOSC

Specifications............................................ 126, 127

Internal Sampling Switch (RSS) IMPEDANCE ........................ 67

Internet Address................................................................ 171

Interrupts............................................................................. 92

ADC ............................................................................ 64

Associated Registers .................................................. 94

Comparator................................................................. 55

Context Saving............................................................ 95

Data EEPROM Memory Write .................................... 72

GP2/INT...................................................................... 92

GPIO Interrupt-on-change .......................................... 93

Interrupt-on-Change.................................................... 32

Timer0......................................................................... 93

TMR1 .......................................................................... 46

INTOSC Specifications ............................................. 126, 127

IOC Register ....................................................................... 34

L

Shared WDT/Timer0................................................... 42

Switching Prescaler Assignment ................................ 42

Program Memory Organization............................................. 7

Map and Stack for the PIC12F683 ............................... 7

Programming, Device Instructions.................................... 101

Load Conditions................................................................ 124

M

MCLR.................................................................................. 86

Internal........................................................................ 86

Memory Organization

R

Data EEPROM Memory.............................................. 71

Microchip Internet Web Site.............................................. 171

Migrating from other PIC Devices..................................... 165

MPLAB ASM30 Assembler, Linker, Librarian ................... 112

MPLAB ICD 2 In-Circuit Debugger ................................... 113

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator .................................................... 113

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator .................................................... 113

MPLAB Integrated Development Environment Software .. 111

MPLAB PM3 Device Programmer .................................... 113

MPLINK Object Linker/MPLIB Object Librarian ................ 112

Reader Response............................................................. 172

Read-Modify-Write Operations ......................................... 101

Registers

ADCON0 (ADC Control 0).......................................... 65

ADRESH (ADC Result High) with ADFM = 0) ............ 66

ADRESH (ADC Result High) with ADFM = 1) ............ 66

ADRESL (ADC Result Low) with ADFM = 0).............. 66

ADRESL (ADC Result Low) with ADFM = 1).............. 66

ANSEL (Analog Select) .............................................. 33

CCP1CON (CCP1 Control) ........................................ 75

CMCON0 (Comparator Control) Register................... 56

CMCON1 (Comparator Control) Register................... 57

CONFIG (Configuration Word) ................................... 84

EEADR (EEPROM Address)...................................... 71

EECON1 (EEPROM Control 1) .................................. 72

EECON2 (EEPROM Control 2) .................................. 72

EEDAT (EEPROM Data)............................................ 71

GPIO........................................................................... 31

INTCON (Interrupt Control) ........................................ 14

IOC (Interrupt-on-Change GPIO) ............................... 34

OPTION_REG (OPTION)..................................... 13, 43

OSCCON (Oscillator Control)..................................... 20

OSCTUNE (Oscillator Tuning).................................... 24

PCON (Power Control Register)................................. 17

PCON (Power Control)............................................... 88

PIE1 (Peripheral Interrupt Enable 1) .......................... 15

PIR1 (Peripheral Interrupt Register 1)........................ 16

Reset Values .............................................................. 90

Reset Values (Special Registers)............................... 91

STATUS ..................................................................... 12

T1CON ....................................................................... 47

T2CON ....................................................................... 50

TRISIO (Tri-State GPIO) ............................................ 32

VRCON (Voltage Reference Control)......................... 58

O

OPCODE Field Descriptions............................................. 101

OPTION Register.......................................................... 13, 43

OSCCON Register.............................................................. 20

Oscillator

Associated registers.............................................. 30, 48

Oscillator Module ................................................................ 19

EC............................................................................... 19

HFINTOSC.................................................................. 19

HS............................................................................... 19

INTOSC ...................................................................... 19

INTOSCIO................................................................... 19

LFINTOSC .................................................................. 19

LP................................................................................ 19

RC............................................................................... 19

RCIO........................................................................... 19

XT ............................................................................... 19

Oscillator Parameters ....................................................... 126

Oscillator Specifications.................................................... 125

Oscillator Start-up Timer (OST)

Specifications............................................................ 129

DS41211D-page 169

PIC12F683

WDTCON (Watchdog Timer Control)..........................97

WPU (Weak Pull-Up GPIO) ........................................34

Resets.................................................................................85

Brown-out Reset (BOR)..............................................85

MCLR Reset, Normal Operation .................................85

MCLR Reset, Sleep ....................................................85

Power-on Reset (POR)...............................................85

WDT Reset, Normal Operation ...................................85

WDT Reset, Sleep ......................................................85

Revision History ................................................................165

INT Pin Interrupt ......................................................... 94

Internal Oscillator Switch Timing ................................ 26

Reset, WDT, OST and Power-up Timer................... 128

Time-out Sequence on Power-up (Delayed MCLR) ... 89

Time-out Sequence on Power-up (MCLR with VDD) .. 89

Timer0 and Timer1 External Clock ........................... 130

Timer1 Incrementing Edge ......................................... 46

Two Speed Start-up.................................................... 28

Wake-up from Sleep Through Interrupt ...................... 99

Timing Parameter Symbology .......................................... 124

TRISIO Register ................................................................. 32

Two-Speed Clock Start-up Mode........................................ 27

S

Sleep

U

Power-Down Mode .....................................................98

Wake-up......................................................................98

Wake-up Using Interrupts ...........................................98

Software Simulator (MPLAB SIM).....................................112

Special Event Trigger..........................................................64

Special Function Registers ...................................................8

STATUS Register................................................................12

Ultra Low-Power Wake-up............................................ 32, 35

V

Voltage Reference. See Comparator Voltage

Reference (CVREF)

Voltage References

Associated registers ................................................... 59

VREF. SEE ADC Reference Voltage

T

T1CON Register..................................................................47

T2CON Register..................................................................50

Thermal Considerations....................................................123

Time-out Sequence.............................................................88

Timer0.................................................................................41

Associated Registers ..................................................43

External Clock.............................................................42

Interrupt................................................................. 13, 43

Operation .............................................................. 41, 44

Specifications............................................................130

T0CKI..........................................................................42

Timer1.................................................................................44

Associated registers....................................................48

Asynchronous Counter Mode .....................................45

Reading and Writing ...........................................45

Interrupt.......................................................................46

Modes of Operation ....................................................44

Operation During Sleep ..............................................46

Oscillator.....................................................................45

Prescaler.....................................................................45

Specifications............................................................130

Timer1 Gate

W

Wake-up Using Interrupts................................................... 98

Watchdog Timer (WDT)...................................................... 96

Associated Registers.................................................. 97

Clock Source .............................................................. 96

Modes......................................................................... 96

Period ......................................................................... 96

Specifications ........................................................... 129

WDTCON Register ............................................................. 97

WPU Register..................................................................... 34

WWW Address ................................................................. 171

WWW, On-Line Support ....................................................... 3

Inverting Gate .....................................................45

Selecting Source...........................................45, 57

Synchronizing COUT w/Timer1 ..........................57

TMR1H Register .........................................................44

TMR1L Register..........................................................44

Timer2

Associated registers....................................................50

Timers

Timer1

T1CON................................................................47

Timer2

T2CON................................................................50

Timing Diagrams

A/D Conversion.........................................................135

A/D Conversion (Sleep Mode) ..................................135

Brown-out Reset (BOR)............................................128

Brown-out Reset Situations ........................................87

CLKOUT and I/O.......................................................127

Clock Timing .............................................................125

Comparator Output .....................................................51

Enhanced Capture/Compare/PWM (ECCP).............131

Fail-Safe Clock Monitor (FSCM).................................30

DS41211D-page 170

PIC12F683

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following informa-

tion:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers should contact their distributor, representa-

tive or field application engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included in

the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change Notifi-

cation and follow the registration instructions.

DS41211D-page 171

PIC12F683

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC12F683

DS41211D

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41211D-page 172

PIC12F683

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC12F683-E/P 301 = Extended Temp., PDIP

package, 20 MHz, QTP pattern #301

b)

PIC12F683-I/SN

package, 20 MHz

= Industrial Temp., SOIC

Device:

PIC12F683⁽¹⁾, PIC12F683T⁽²⁾

VDD range 2.0V to 5.5V

Temperature

Range:

I

E

=

-40°C to +85°C(Industrial)

-40°C to +125°C (Extended)

Package:

P

=

Plastic DIP

MD

MF

SN

Dual-Flat, No Leads (DFN-S, 4x4x0.9 mm)

Dual-Flat, No Leads (DFN-S, 6x5 mm)

8-lead Small Outline (3.90 mm)

Note 1:

2:

F

LF

=

Standard Voltage Range

Wide Voltage Range

Pattern:

3-digit Pattern Code for QTP (blank otherwise)

T = in tape and reel PLCC, and TQFP

packages only.

DS41211D-page 173

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS41211D-page 174


型号：	PIC12F683-E/PG
厂家：	MICROCHIP
描述：	8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP8, 0.300 INCH, PLASTIC, DIP-8 时钟光电二极管外围集成电路
文件：	总176页 (文件大小：2986K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC12F683-E/PG [MICROCHIP]

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PIC12F683-E/SN

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PIC12F683-E/SNQTP

PIC12F683-E/SNVAO

PIC12F683-I/MD

PIC12F683-I/MDQTP

PIC12F683-I/MF

PIC12F683-I/MFG

PIC12F683-I/MFQTP

PIC12F683-I/P

PIC12F683-I/PG