PIC12LCE674-10/JW [MICROCHIP]
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory; 8引脚， 8位CMOS微控制器与A / D转换器和EEPROM数据存储器
| 型号： | PIC12LCE674-10/JW |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory |
| 文件： | 总116页 (文件大小：649K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12CE67X
M
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
and EEPROM Data Memory
Devices Included in this Data Sheet:
Pin Diagram:
• PIC12CE673
• PIC12CE674
PDIP, Windowed CERDIP
VDD
VSS
1
2
3
4
8
7
6
5
High-Performance RISC CPU:
GP5/OSC1/CLKIN
GP0/AN0
• Only 35 single word instructions to learn
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
GP4/OSC2/AN3/CLKOUT
GP3/MCLR/VPP
• All instructions are single cycle (400 ns) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Special Microcontroller Features:
Memory
• In-Circuit Serial Programming (ICSP™)
Device
• Internal 4 MHz oscillator with programmable
calibration
Data
RAM
Data
EEPROM
Program
• Selectable clockout
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
PIC12CE673 1024 x 14
PIC12CE674 2048 x 14
128 x 8
128 x 8
16 x 8
16 x 8
• 14-bit wide instructions
• 8-bit wide data path
• Interrupt capability
• Special function hardware registers
• 8-level deep hardware stack
• Programmable code protection
• Power saving SLEEP mode
• Direct, indirect and relative addressing modes for
data and instructions
• Internal pull-ups on I/O pins (GP0, GP1, GP3)
• Internal pull-up on MCLR pin
• Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
Peripheral Features:
• Four-channel, 8-bit A/D converter
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Interrupt on pin change (GP0, GP1, GP3)
• 1,000,000 erase/write cycle EEPROM data
memory
- XT:
- HS:
- LP:
Standard crystal/resonator
High speed crystal/resonator
Power saving, low frequency crystal
CMOS Technology:
• EEPROM data retention > 40 years
• Low-power, high-speed CMOS EPROM/
EEPROM technology
• Fully static design
• Wide operating voltage range 2.5V to 5.5V
• Commercial, Industrial, and Extended
temperature ranges
• Low power consumption
< 2 mA @ 5V, 4 MHz
15 µA typical @ 3V, 32 kHz
< 1 µA typical standby current
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 1
PIC12CE67X
Table of Contents
1.0 General Description ....................................................................................................................................................................... 3
2.0 PIC12CE67X Device Varieties....................................................................................................................................................... 5
3.0 Architectural Overview................................................................................................................................................................... 7
4.0 Memory Organization................................................................................................................................................................... 11
5.0 I/O Port......................................................................................................................................................................................... 25
6.0 EEPROM Peripheral Operation ................................................................................................................................................... 27
7.0 Timer0 Module............................................................................................................................................................................. 31
8.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................... 37
9.0 Special Features of the CPU ....................................................................................................................................................... 45
10.0 Instruction Set Summary.............................................................................................................................................................. 61
11.0 Development Support .................................................................................................................................................................. 75
12.0 Electrical Characteristics for PIC12CE67X.................................................................................................................................. 81
13.0 DC and AC Characteristics - PIC12CE67X ................................................................................................................................. 99
14.0 Packaging Information ............................................................................................................................................................... 103
Index .................................................................................................................................................................................................. 107
PIC12CE67X Product Identification System ..................................................................................................................................... 113
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet.The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include lit-
erature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
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We appreciate your assistance in making this a better document.
DS40181B-page 2
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
1.0
GENERAL DESCRIPTION
The PIC12CE67X devices are low-cost, high-perfor-
mance, CMOS, fully-static, 8-bit microcontroller with
integrated analog-to-digital (A/D) converter and
EEPROM data memory in the PIC12CEXXX Micro-
controller family.
A UV erasable windowed package version is ideal for
code development while the cost-effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.The customer can take full advantage of
Microchip’s price leadership in OTP microcontrollers
while benefiting from the OTP’s flexibility.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC12C67X microcontrollers
have enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
The PIC12CE67X device fits perfectly in applications
ranging from security and remote sensors to appliance
control and automotive. The EPROM technology
makes customization of application programs (trans-
mitter codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC12CE67X very versatile even in areas
where no microcontroller use has been considered
before (e.g. timer functions, communications and
coprocessor applications).
PIC12C67X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
1.1
Family and Upward Compatibility
The PIC12CE67X devices have 128 bytes of RAM, 16
bytes of EEPROM data memory, 5 I/O pins and 1 input
pin. In addition a timer/counter is available. Also a 4-
channel high-speed 8-bit A/D is provided.The 8-bit res-
olution is ideally suited for applications requiring low-
cost analog interface, e.g. thermostat control, pressure
sensing, etc.
The PIC12CE67X products are compatible with other
members of the 14-Bit, PIC12C67X and PIC16CXXX
families.
1.2
Development Support
The PIC12CE67X device is supported by a full-fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a low-cost development programmer and
a full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
The PIC12CE67X device has special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power con-
sumption. The Power-On Reset (POR), Power-up
Timer (PWRT), and Oscillator Start-up Timer (OST)
eliminate the need for external reset circuitry.There are
five oscillator configurations to choose from, including
INTRC precision internal oscillator mode and the
power-saving LP (Low Power) oscillator mode. Power
saving SLEEP mode, Watchdog Timer and code
protection features improve system cost, power and
reliability.The SLEEP (power-down) feature provides a
power saving mode. The user can wake up the chip
from SLEEP through several external and internal
interrupts and resets.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 3
PIC12CE67X
TABLE 1-1:
PIC12CXXX & PIC12CEXXX FAMILY OF DEVICES
PIC12C508(A) PIC12C509(A) PIC12CE518 PIC12CE519 PIC12C671 PIC12C672 PIC12CE673 PIC12CE674
Maximum
4
4
4
4
10
10
10
10
Frequency
of Operation
(MHz)
Clock
EPROM
Program
Memory
512 x 12
1024 x 12
512 x 12
25
1024 x 12
1024 x 14
128
2048 x 14
128
1024 x 14
128
2048 x 14
128
Memory
RAM Data
Memory
(bytes)
25
—
41
—
41
16
EEPROM
Data Memory
(bytes)
16
—
—
16
16
Timer
Module(s)
TMR0
—
TMR0
—
TMR0
—
TMR0
—
TMR0
4
TMR0
4
TMR0
4
TMR0
4
Peripherals
A/D Con-
verter (8-bit)
Channels
Wake-up
from SLEEP
on pin
Yes
—
Yes
—
Yes
—
Yes
—
Yes
4
Yes
4
Yes
4
Yes
4
change
Interrupt
Sources
I/O Pins
5
5
5
5
5
5
5
5
Features
Input Pins
1
1
1
1
1
1
1
1
Internal
Pull-ups
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
In-Circuit
Serial
Programming
Yes
33
Yes
33
Yes
33
Yes
33
Yes
35
Yes
35
Yes
35
Yes
35
Number of
Instructions
Packages
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW, SOIC
8-pin DIP,
JW
8-pin DIP,
JW
All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable
code protect and high I/O current capability.
All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1.
DS40181B-page 4
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
2.3
Quick-Turn-Programming (QTP)
Devices
2.0
PIC12CE67X DEVICE
VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC12CE67X Product Iden-
tification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
For example, the PIC12CE67X device “type” is indi-
cated in the device number:
1. CE, as in PIC12CE674. These devices have
OTP program memory, EEPROM data memory
and operate over the standard voltage range.
2.4
Serialized Quick-Turn Programming
(SQTPSM) Devices
2.1
UV Erasable Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers.The serial num-
bers may be random, pseudo-random, or sequential.
The UV erasable version, offered in windowed pack-
age, is optimal for prototype development and pilot pro-
grams.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes.
Microchip's PICSTART Plus and PRO MATE pro-
grammers both support the PIC12CE67X. Third party
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 5
PIC12CE67X
NOTES:
DS40181B-page 6
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
The PIC12CE67X can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC12CE67X has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC12CE67X simple yet efficient. In addition, the learn-
ing curve is reduced significantly.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC12CE67X family can
be attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC12CE67X uses a Harvard architecture, in which
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
over traditional von Neumann architecture in which pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses also allow instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 14-
bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (400 ns @ 10 MHz) except for
program branches.
PIC12CE67X devices contain an 8-bit ALU and work-
ing register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between the data in the working register and any regis-
ter file.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The table below lists program memory (EPROM), data
memory (RAM), and non-volatile memory (EEPROM)
for each PIC12CE67X device.
RAM
Data
EEPROM
Data
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Program
Memory
Device
Memory Memory
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register.The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
PIC12CE673
PIC12CE674
1K x 14
2K x 14
128 x 8
128 x 8
16x8
16x8
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 7
PIC12CE67X
FIGURE 3-1: PIC12CE67X BLOCK DIAGRAM
Device
Program Memory Data Memory (RAM) Non-Volatile Memory (EEPROM)
PIC12CE673
PIC12CE674
1K x 14
2K x 14
128 x 8
128 x 8
16 x 8
16 x 8
13
8
GPIO
Data Bus
Program Counter
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
GP3/MCLR/Vpp
GP4/OSC2/AN3/CLKOUT
EPROM
Program
Memory
RAM
8 Level Stack
(13 bit)
128 bytes
File
Registers
GP5/OSC1/CLKIN
Program
Bus
14
RAM Addr (1)
9
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
16x8
EEPROM
Data
FSR reg
Memory
STATUS reg
8
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
Watchdog
Timer
8
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
W reg
Internal
4 MHz Clock
Timer0
MCLR
VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS register.
DS40181B-page 8
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 3-1:
PIC12CE67X PINOUT DESCRIPTION
DIP Pin
#
I/O/P
Type
Buffer
Type
Name
Description
GP0/AN0
7
6
I/O
I/O
TTL/ST Bi-directional I/O port/serial programming data/analog input
0. Can be software programmed for internal weak pull-up
and interrupt on pin change.This buffer is a Schmitt Trigger
input when used in serial programming mode.
GP1/AN1/VREF
TTL/ST Bi-directional I/O port/serial programming clock/analog
input 1/voltage reference. Can be software programmed for
internal weak pull-up and interrupt on pin change. This
buffer is a Schmitt Trigger input when used in serial pro-
gramming mode.
GP2/T0CKI/AN2/INT
GP3/MCLR/VPP
5
4
I/O
I
ST
Bi-directional I/O port/analog input 2. Can be configured as
T0CKI or external interrupt.
TTL/ST Input port/master clear (reset) input/programming voltage
input. When configured as MCLR, this pin is an active low
reset to the device.Voltage on MCLR/VPP must not exceed
VDD during normal device operation. Can be software pro-
grammed for internal weak pull-up and interrupt on pin
change. Weak pull-up always on if configured as MCLR .
This buffer is Schmitt Trigger when in MCLR mode.
GP4/OSC2/AN3/
CLKOUT
3
2
I/O
I/O
TTL
Bi-directional I/O port/oscillator crystal output/analog input
3. Connections to crystal or resonator in crystal oscillator
mode (HS, XT and LP modes only, GPIO in other modes).
In EXTRC and INTRC modes, the pin output can be config-
ured to CLKOUT which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
GP5/OSC1/CLKIN
TTL/ST Bidirectional IO port/oscillator crystal input/external clock
source input (GPIO in INTRC mode only, OSC1 in all other
oscillator modes). Schmitt trigger in EXTRC mode only.
VDD
VSS
1
8
P
P
—
—
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 9
PIC12CE67X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute
are pipelined such that fetch takes one instruction
cycle while decode and execute takes another
instruction cycle. However, due to the pipelining, each
instruction effectively executes in one cycle. If an
instruction causes the program counter to change
(e.g. GOTO) then two cycles are required to complete
the instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the “Instruction Register" (IR) in cycle
Q1. This instruction is then decoded and executed
during the Q2, Q3, and Q4 cycles. Data memory is
read during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(EXTRC and
INTRC modes)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Tcy2
Tcy3
Tcy4
Tcy5
1. MOVLW 55h
2. MOVWF GPIO
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
GPIO, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches.These take two cycles since the fetch instruc-
tion is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40181B-page 10
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
4.1
Program Memory Organization
The PIC12CE67X has a 13-bit program counter capa-
ble of addressing an 8K x 14 program memory space.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
For the PIC12CE673 the first 1K x 14 (0000h-03FFh) is
implemented.
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
For the PIC12CE674, the first 2K x 14 (0000h-07FFh)
is implemented. Accessing a location above the physi-
cally implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC12CE67X PROGRAM
MEMORY MAP AND STACK
Also note that F0h through FFh on the PIC12CE67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
Stack Level 1
Stack Level 8
Reset Vector
0000h
Peripheral
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0400h
(PIC12CE674 only)
07FFh
0800h
1FFFh
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 11
PIC12CE67X
4.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 4-2: PIC12CE67X REGISTER FILE
MAP
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
File
Address
File
Address
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
GPIO
TRIS
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADRES
ADCON0
ADCON1
A0h
General
Purpose
Register
BFh
C0h
General
Purpose
Register
EFh
F0h
70h
7Fh
Mapped
in Bank 0
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
DS40181B-page 12
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 4-1:
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-on
Reset
Value on
all other
Resets(3)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00h(1)
01h
INDF
TMR0
PCL
STATUS
FSR
GPIO
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
11xx xxxx 11uu uuuu
02h(1)
03h(1)
04h(1)
05h
Program Counter's (PC) Least Significant Byte
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
SCL
SDA
GP5
GP4
GP3
GP2
GP1
GP0
06h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
07h
—
08h
—
09h
—
0Ah(1,2) PCLATH
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
0Bh(1)
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INTCON
GIE
—
PEIE
ADIF
INTE
—
GPIE
—
T0IF
—
INTF
—
GPIF
—
PIR1
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRES
ADCON0
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
ADCS1
ADCS0
r
CHS1
CHS0
GO/DONE
r
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 13
PIC12CE67X
TABLE 4-1:
Address Name
Bank 1
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)
Value on
Power-on
Reset
Value on
all other
Resets(3)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
80h(1)
81h
INDF
OPTION
PCL
STATUS
FSR
TRIS
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
0011 1111 0011 1111
GPPU
Program Counter's (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(1)
83h(1)
84h(1)
85h
PD
Z
DC
C
—
—
GPIO Data Direction Register
86h
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
87h
—
88h
—
89h
—
8Ah(1,2) PCLATH
—
—
T0IE
—
Write Buffer for the upper 5 bits of the PC
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
8Bh(1)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INTCON
GIE
—
PEIE
ADIE
INTE
—
GPIE
—
T0IF
—
INTF
—
GPIF
—
PIE1
—
Unimplemented
—
—
—
PCON
—
—
—
—
—
POR
—
—
—
---- --0- ---- --u-
1000 00-- uuuu uu--
OSCCAL
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCON1
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
DS40181B-page 14
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register, shown in Figure 4-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled.These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC12CE67X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recom-
mended, since this may affect upward
compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
FIGURE 4-3: STATUS REGISTER (ADDRESS 03h, 83h)
Reserved Reserved R/W-0
IRP RP1 RP0
bit7
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 15
PIC12CE67X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION<3>).
The OPTION register is a readable and writable regis-
ter which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0, and the weak pull-ups on GPIO.
FIGURE 4-4: OPTION REGISTER (ADDRESS 81h)
R/W-1
GPPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
= Readable bit
W = Writable bit
U
bit7
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
GPPU: Weak pullup enable
1 = Weak pullups disabled
0 = Weak pullups enabled (GP0, GP1, GP3)
INTEDG: Interrupt edge
1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin
0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI/AN2/INT pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin
0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS40181B-page 16
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, GPIO Port change and Exter-
nal GP2/INT Pin interrupts.
FIGURE 4-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
GPIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
GPIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin
0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin
GPIE: GPIO Interrupt on Change Enable bit
1 = Enables the GPIO Interrupt on Change
0 = Disables the GPIO Interrupt on Change
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)
0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur
GPIF: GPIO Interrupt on Change Flag bit
1 = GP0, GP1, or GP3 pins changed state (must be cleared in software)
0 = Neither GP0, GP1, nor GP3 pins have changed state
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 17
PIC12CE67X
4.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the
Peripheral interrupts.
enable any peripheral interrupt.
FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
R/W-0
ADIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-0: Unimplemented: Read as '0'
DS40181B-page 18
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
R/W-0
ADIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-0: Unimplemented: Read as '0'
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 19
PIC12CE67X
4.2.2.6
PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), an external MCLR Reset, and WDT Reset.
FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
U-0
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1: POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
Unimplemented: Read as '0'
DS40181B-page 20
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.2.2.7
OSCCAL REGISTER
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains six
bits for calibration. Increasing the cal value increases
the frequency.
FIGURE 4-9: OSCCAL REGISTER (ADDRESS 8Fh)
R/W-1
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
U-0
—
U-0
—
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: CAL<5:0>: Calibration
bit 1-0: Unimplemented, read as 0
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 21
PIC12CE67X
4.3.2
STACK
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide.The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-10 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH).The lower exam-
ple in the figure shows how the PC is loaded during a
CALLor GOTOinstruction (PCLATH<4:3> → PCH).
The PIC12C67X family has an 8 level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALLinstruction is executed or an inter-
rupt causes a branch. The stack is POPed in the event
of a RETURN, RETLWor a RETFIEinstruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer.This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 4-10: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Note 1: There are no status bits to indicate stack
12
8
7
0
Instruction with
PCL as
overflow or stack underflow conditions.
PC
Destination
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt
address.
8
PCLATH<4:0>
PCLATH
5
ALU result
PCH
12 11 10
PCL
8
7
0
4.4
Program Memory Paging
GOTO, CALL
PC
The PIC12CE67X ignores both paging bits
PCLATH<4:3>, which are used to access program
memory when more than one page is available. The
use of PCLATH<4:3> as general purpose read/write
bits for the PIC12CE67X is not recommended since
this may affect upward compatibility with future prod-
ucts.
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an off-
set to the program counter (ADDWF PCL).When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
DS40181B-page 22
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20
movwf FSR
;initialize pointer
;to RAM
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
clrf
incf
INDF
;clear INDF register
FSR,F ;inc pointer
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-11. However, IRP
is not used in the PIC12CE67X.
btfss FSR,4 ;all done?
goto
NEXT
;no clear next
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
FIGURE 4-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(1)
(1)
from opcode
7
RP1 RP0
6
0
0
IRP
FSR register
bank select
180h
location select
bank select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
For register file map detail see Figure 4-2.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 23
PIC12CE67X
NOTES:
DS40181B-page 24
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
rewritten. To use
a
port pin as output, the
5.0
I/O PORT
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except GP3) can be
programmed individually as input or output.
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF GPIO,W) always read the
I/O pins independent of the pin’s input/output modes.
On RESET, all I/O ports are defined as input (inputs
are at hi-impedance) since the I/O control registers are
all set.
Port pins GP6 and GP7 are used for the serial
EEPROM interface. These port pins are not available
externally on the package. Users should avoid writing
to pins GP6 and GP7 when not communicating with
the serial EEPROM memory. Please see section 6.0,
EEPROM Peripheral Operation, for information on
serial EEPROM communication.
5.1
GPIO
GPIO is an 8-bit I/O register. Only the low order 6 bits
are used (GP5:GP0). Bits 6 and 7 (SDA and SCL) are
used by the EEPROM peripheral. Refer to Section 6.0
and Appendix A for use of SDA and SCL. Please note
that GP3 is an input only pin. The configuration word
can set several I/O’s to alternate functions. When
acting as alternate functions the pins will read as ‘0’
during port read. Pins GP0, GP1, and GP3 can be
configured with weak pull-ups and also with interrupt
on change. The interrupt on change and weak pull-up
functions are not pin selectable. If pin 4 is configured
as MCLR, the weak pull-up is always on. Interrupt on
change for this pin is not set and GP3 will read as '0'.
Interrupt on change is enabled by setting INTCON<3>.
Note that external oscillator use overrides the GPIO
functions on GP4 and GP5.
Note:
On a Power-on Reset, GP0, GP1, GP2,
GP4 are configured as analog inputs and
read as '0'.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
VDD
P
WR
Port
Latch
CK
5.2
TRIS Register
N
I/O
pin(1)
W
Reg
This register controls the data direction for GPIO. A '1'
from a TRIS register bit puts the corresponding output
driver in a hi-impedance mode. A '0' puts the contents
of the output data latch on the selected pins, enabling
the output buffer. The exceptions are GP3 which is
input only and its TRIS bit will always read as '1'.
D
Q
Q
TRIS
Latch
VSS
TRIS ‘f’
CK
Reset
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
Upon reset, the TRIS register is all '1's, making all pins
inputs.
GP3 is input only with no data latch and no
output drivers.
TRIS for pins GP4 and GP5 is forced to a 1 where
appropriate. Writes to TRIS <5:4> will have an effect
in EXTRC and INTRC oscillator modes only. When
GP4 is configured as CLKOUT, changes to TRIS<4>
will have no effect.
5.3
I/O Interfacing
The equivalent circuit for an I/O port pin is shown in
Figure 5-2. All port pins, except GP3 which is input
only, may be used for both input and output
operations. For input operations these ports are non-
latching. Any input must be present until read by an
input instruction (e.g., MOVF GPIO,W). The outputs are
latched and remain unchanged until the output latch is
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 25
PIC12CE67X
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-on
Reset
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
85h
81h
03h
05h
TRIS
—
—
GPIO Data Direction Register
--11 1111
1111 1111
0001 1xxx
11xx xxxx
--11 1111
1111 1111
000q quuu
11uu uuuu
OPTION
STATUS
GPIO
GPPU
IRP(1)
SCL
INTEDG
RP1(1)
SDA
T0CS
RP0
T0SE
TO
PSA
PD
PS2
Z
PS1
DC
PS0
C
GP5
GP4
GP3
GP2
GP1 GP0
Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x= unknown, u= unchanged,
q = see tables in Section 9.4 for possible values.
Note 1: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.
Example 5-1 shows the effect of two sequential read-
modify-write instructions on an I/O port.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial GPIO Settings
; GPIO<5:3> Inputs
; GPIO<2:0> Outputs
;
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of GPIO will cause all eight bits of GPIO to be read into
the CPU. Then the BSF operation takes place on bit5
and GPIO is written to the output latches. If another bit
of GPIO is used as a bi-directional I/O pin (e.g., bit0)
and it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU
and rewritten to the data latch of this particular pin,
overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched to an output, the content of the data
latch may now be unknown.
;
;
GPIO latch GPIO pins
---------- ----------
BCF
BCF
MOVLW 007h
TRIS GPIO
GPIO, 5
GPIO, 4
;--01 -ppp
;--10 -ppp
;
--11 pppp
--11 pppp
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;GP5 to be latched as the pin value (High).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
MOVWF GPIO
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
This example shows a write to GPIO followed
by a read from GPIO.
Instruction
fetched
MOVF GPIO,W
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
GP5:GP0
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
executed
MOVWF GPIO
(Write to
MOVF GPIO,W
(Read
NOP
GPIO)
GPIO)
DS40181B-page 26
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
• Data transfer may be initiated only when the bus
is not busy.
6.0
EEPROM PERIPHERAL
OPERATION
During data transfer, the data line must remain stable
whenever the clock line is HIGH. Changes in the data
line while the clock line is HIGH will be interpreted as a
START or STOP condition.
The PIC12CE673 and PIC12CE674 each have 16
bytes of EEPROM data memory. The EEPROM mem-
ory has an endurance of 1,000,000 erase/write cycles
and a data retention of greater than 40 years. The
EEPROM data memory supports a bi-directional 2-wire
bus and data transmission protocol. These two-wires
are serial data (SDA) and serial clock (SCL), that are
mapped to bit6 and bit7, respectively, of the GPIO reg-
ister (SFR 06h). Unlike the GP0-GP5 that are con-
nected to the I/O pins, SDA and SCL are only
connected to the internal EEPROM peripheral. For
most applications, all that is required is calls to the fol-
lowing functions:
Accordingly, the following bus conditions have been
defined (Figure 6-1).
6.1.1
Both data and clock lines remain HIGH.
6.1.2 START DATA TRANSFER (B)
BUS NOT BUSY (A)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
; Byte_Write: Byte write routine
;
;
;
Inputs:EEPROM Address
EEPROM Data
EEADDR
EEDATA
6.1.3
STOP DATA TRANSFER (C)
Outputs:
Return 01 in W if OK, else
return 00 in W
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
;
;
Inputs:NONE
Outputs:
6.1.4
DATA VALID (D)
EEPROM Data
EEDATA
Return 01 in W if OK, else
return 00 in W
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
;
; Read_Random: Read EEPROM byte at supplied
address
;
;
;
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Inputs:EEPROM Address
Outputs: EEPROM Data
EEADDR
EEDATA
Return 01 in W if OK,
else return 00 in W
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor
device and is theoretically unlimited.
The code for these functions is available on our web
site (www.microchip.com). The code will be accessed
by either including the source code FL67XINC.ASM or
by linking FLASH67X.ASM. FLASH62.IMC provides
external definition to the calling program.
6.1.5
ACKNOWLEDGE
6.0.1
SERIAL DATA
The EEPROM, when addressed, will generate an
acknowledge after the reception of each byte. The pro-
cessor must generate an extra clock pulse which is
associated with this acknowledge bit.
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the device.
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
Note: Acknowledge bits are not generated if an
internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-2).
6.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
from and to the EEPROM.
6.1
BUS CHARACTERISTICS
The following bus protocol is to be used with the
EEPROM data memory. In this section, the term “pro-
cessor” is used to denote the portion of the
PIC12CE67X that interfaces to the EEPROM via soft-
ware.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 27
PIC12CE67X
FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(C)
(D)
(C)
(A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
FIGURE 6-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
Device Addressing
FIGURE 6-3: CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed.The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
Device Select
Don’t Care
Bits
Bits
S
1
0
1
0
X
X
X R/W ACK
The last bit of the control byte determines the operation
to be performed. When set to a one a read operation is
selected, and when set to a zero a write operation is
selected. (Figure 6-3). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
EEPROM Address
Acknowledge Bit
Start Bit
DS40181B-page 28
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
6.3
WRITE OPERATIONS
6.4
ACKNOWLEDGE POLLING
6.3.1
BYTE WRITE
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the processor, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the proces-
sor sending a start condition followed by the control
byte for a write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If no ACK is returned, then the start bit and control byte
must be re-sent. If the cycle is complete, then the
device will return the ACK and the processor can then
proceed with the next read or write command. See
Figure 6-4 for flow diagram.
Following the start signal from the processor, the
device code (4 bits), the don't care bits (3 bits), and the
R/W bit (which is a logic low) are placed onto the bus
by the processor. This indicates to the addressed
EEPROM that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the processor is the word address and will be written
into the address pointer. Only the lower four address
bits are used by the device, and the upper four bits are
don’t cares. The address byte is acknowledgeable and
the processor will then transmit the data word to be
written into the addressed memory location. The mem-
ory acknowledges again and the processor generates
a stop condition. This initiates the internal write cycle,
and during this time will not generate acknowledge sig-
nals (Figure 6-5). After a byte write command, the inter-
nal address counter will not be incremented and will
point to the same address location that was just written.
If a stop bit is transmitted to the device at any point in
the write command sequence before the entire
sequence is complete, then the command will abort
and no data will be written. If more than 8 data bits are
transmitted before the stop bit is sent, then the device
will clear the previously loaded byte and begin loading
the data buffer again. If more than one data byte is
transmitted to the device and a stop bit is sent before a
full eight data bits have been transmitted, then the write
command will abort and no data will be written. The
EEPROM memory employs a VCC threshold detector
circuit which disables the internal erase/write logic if the
VCC is below minimum VDD. Byte write operations
must be preceded and immediately followed by a bus
not busy bus cycle where both SDA and SCL are held
high.
FIGURE 6-4: ACKNOWLEDGE POLLING
FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 6-5: BYTE WRITE
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
PROCESSOR
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
P
S
1
0
1
0
X
X
X
0
X
X
X X
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = Don’t Care Bit
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 29
PIC12CE67X
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again but with the R/W bit set to a one. It will then
issue an acknowledge and transmits the eight bit data
word. The processor will not acknowledge the transfer
but does generate a stop condition and the EEPROM
discontinues transmission (Figure 6-7). After this com-
mand, the internal address counter will point to the
address location following the one that was just read.
6.5
READ OPERATIONS
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations: current address read, random
read, and sequential read.
6.5.1
CURRENT ADDRESS READ
It contains an address counter that maintains the
address of the last word accessed, internally incre-
mented by one. Therefore, if the previous read access
was to address n, the next current address read opera-
tion would access data from address n + 1. Upon
receipt of the EEPROM address with the R/W bit set to
one, the EEPROM issues an acknowledge and trans-
mits the eight bit data word. The processor will not
acknowledge the transfer but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-6).
6.5.3
SEQUENTIAL READ
Sequential reads are initiated in the same way as a ran-
dom read except that after the device transmits the first
data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-8).
To provide sequential reads, it contains an internal
address pointer which is incremented by one at the
completion of each read operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
6.5.2
RANDOM READ
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set.This is done by sending the word address to the
FIGURE 6-6: CURRENT ADDRESS READ
S
T
S
BUS ACTIVITY
A
CONTROL
BYTE
T
PROCESSOR
R
O
P
T
SDA LINE
S 1 0 1 0 X X X 1
P
A
C
K
N
O
BUS ACTIVITY
DATA
A
C
K
X = Don’t Care Bit
FIGURE 6-7: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY
PROCESSOR
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
X X X X
P
S 1 0 1 0 X X X 0
S 1 0 1 0 X X X 1
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
DATA (n)
BUS ACTIVITY
A
C
K
X = Don’t Care Bit
FIGURE 6-8: SEQUENTIAL READ
S
T
O
P
BUS ACTIVITY
PROCESSOR
CONTROL
BYTE
DATA n
DATA n + 1
DATA n + 2
DATA n + X
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
DS40181B-page 30
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 7.2.
7.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable.When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer0 Interrupt
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt.The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP. See Figure 7-
4 for Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
Source Edge Select bit T0SE (OPTION<4>). Clearing
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
1
8
PSout
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
GP2/T0CKI/
AN2/INT
PSout
(2 TCY delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 31
PIC12CE67X
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 7-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
FFh
00h
01h
02h
1
1
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (0004h)
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 3Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS40181B-page 32
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
7.2
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
7.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler output
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 33
PIC12CE67X
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler.When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
GP2/T0CKI/
AN2/INT
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS40181B-page 34
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 mod-
ule use the sequence shown in Example 7-2.
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT→TIMER0)
Note: To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
CLRWDT
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
OPTION_REG ;clock source
STATUS, RP0 ;Bank 0
BSF
MOVLW
MOVWF
BCF
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0→WDT)
BCF
STATUS, RP0 ;Bank 0
CLRF
BSF
TMR0
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
CLRWDT
;Clears WDT
MOVLW b'xxxx1xxx' ;Select new prescale
MOVWF OPTION_REG ;value & WDT
STATUS, RP0 ;Bank 0
BCF
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
0Bh/8Bh INTCON
GIE
OPTION GPPU INTEDG
TRIS
PEIE
T0IE
T0CS
TRIS5
INTE
T0SE
TRIS4
GPIE
PSA
T0IF
PS2
INTF
PS1
GPIF
PS0
81h
85h
—
—
TRIS3
TRIS2
TRIS1
TRIS0 --11 1111 --11 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 35
PIC12CE67X
NOTES:
DS40181B-page 36
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
The ADCON0 register, shown in Figure 8-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 8-2, configures the functions of the
port pins. The port pins can be configured as analog
inputs (GP1 can also be a voltage reference) or as dig-
ital I/O.
8.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The analog-to-digital (A/D) converter module has four
analog inputs.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the device’s positive supply voltage (VDD)
or the voltage level on the GP1/AN1/VREF pin.The A/D
converter has a unique feature of being able to operate
while the device is in SLEEP mode.
Note: If the port pins are configured as analog
inputs (reset condition), reading the port
(MOVF GP,W) results in reading '0's.
Note: Changing ADCON1 register can cause the
GPIF and INTF flags to be set in the
INTCON register. These interrupts should
be disabled prior to modifying ADCON1.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
FIGURE 8-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0
R/W-0
CHS1
R/W-0
R/W-0
R/W-0
r
R/W-0
ADON
ADCS1 ADCS0
bit7
r
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5:
Reserved
bit 4-3: CHS1:CHS0: Analog Channel Select bits
00= channel 0, (GP0/AN0)
01= channel 1, (GP1/AN1)
10= channel 2, (GP2/AN2)
11= channel 3, (GP4/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-
sion is complete)
bit 1:
bit 0:
Reserved
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 37
PIC12CE67X
FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
bit7
bit0
U =Unimplemented
bit, read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
GP4
GP2
GP1
GP0
VREF
(1)
A
A
A
A
VDD
000
001
010
011
100
101
110
111
A
D
D
D
D
D
D
A
A
A
D
D
D
D
VREF
A
A
A
A
A
A
A
D
GP1
VDD
GP1
VDD
GP1
VDD
VDD
VREF
A
VREF
D
D
A = Analog input
D = Digital I/O
Note 1: Value on reset.
Note 2: Any instruction that reads a pin configured as an analog input will read a '0'.
DS40181B-page 38
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF (PIE1<6>) is set. The block diagrams of the A/D
module are shown in Figure 8-3.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input.To determine sample time, see Section 8.1. After
this acquisition time has elapsed the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
1. Configure the A/D module:
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 8-3: A/D BLOCK DIAGRAM
CHS1:CHS0
11
GP4/AN3
VIN
10
(Input voltage)
GP2/AN2
01
A/D
Converter
GP1/AN1/VREF
00
GP0/AN0
VDD
000 or
010 or
100 or
110 or
VREF
(Reference
voltage)
001 or
011 or
101
PCFG2:PCFG0
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 39
PIC12CE67X
8.1
A/D Sampling Requirements
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 8-4. The maximum recommended imped-
ance for analog sources is 10 kΩ. After the analog
input channel is selected (changed) this acquisition
must be done before the conversion can be started.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time the holding capacitor is not con-
nected to the selected A/D input channel.
To calculate the minimum acquisition time, Equation 8-
1 may be used. This equation assumes that 1/2 LSb
error is used (512 steps for the A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
EXAMPLE 8-1: CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
EQUATION 8-1:
A/D MINIMUM CHARGING
TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
(-Tc/CHOLD(RIC + RSS + RS))
VHOLD = (VREF - (VREF/512)) • (1 - e
)
or
TACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
TC =
-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2146)
Example 8-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
Rs = 10 kΩ
1/2 LSb error
5.724 µs
VDD = 5V → Rss = 7 kΩ
Temp (system max.) = 50°C
VHOLD = 0 @ t = 0
TACQ = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.724 µs + 1.25 µs
11.974 µs
FIGURE 8-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
RAx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS40181B-page 40
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
8.2
Selecting the A/D Conversion Clock
8.3
Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
The ADCON1 and TRIS registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
• 2TOSC
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 8TOSC
• 32TOSC
• Internal ADC RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 8-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN3:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 8-1:
TAD vs. DEVICE OPERATING FREQUENCIES
Device Frequency
AD Clock Source (TAD)
ADCS1:ADCS0
Operation
2TOSC
4 MHz
1.25 MHz
1.6 µs
333.33 kHz
(2)
00
01
10
11
6 µs
500 ns
(3)
8TOSC
2.0 µs
6.4 µs
24 µs
(3)
(3)
32TOSC
8.0 µs
25.6 µs
96 µs
(5)
(1,4)
(1,4)
(1)
Internal ADC RC Oscillator
2 - 6 µs
2 - 6 µs
2 - 6 µs
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 41
PIC12CE67X
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started
on the selected channel.
8.4
A/D Conversions
Example 8-2 show how to perform an A/D conversion.
The GP pins are configured as analog inputs.The ana-
log reference (VREF) is the device VDD. The A/D inter-
rupt is enabled, and the A/D conversion clock is FRC.
The conversion is performed on the GP0 channel.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
EXAMPLE 8-2: DOING AN A/D CONVERSION
BSF
CLRF
BSF
STATUS, RP0
ADCON1
; Select Page 1
; Configure A/D inputs
; Enable A/D interrupts
; Select Page 0
; RC Clock, A/D is on, Channel 0 is selected
;
; Clear A/D interrupt flag bit
; Enable peripheral interrupts
; Enable all interrupts
PIE1,
ADIE
BCF
STATUS, RP0
0xC1
ADCON0
MOVLW
MOVWF
BCF
BSF
BSF
PIR1,
ADIF
INTCON, PEIE
INTCON, GIE
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
ADCON0, GO
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
:
;
is cleared upon completion of the A/D Conversion.
DS40181B-page 42
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
8.5
A/D Operation During Sleep
8.7
Effects of a RESET
The A/D module can operate during SLEEP mode.This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Reset. The ADRES regis-
ter will contain unknown data after a Power-on Reset.
8.8
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specification.
Note: For the PIC12CE67X, care must be taken
when using the GP4 pin in A/D conver-
sions due to its proximity to the OSC1 pin.
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEPinstruc-
tion.
8.9
Transfer Function
The ideal transfer function of the A/D converter is as fol-
lows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 8-5).
8.6
A/D Accuracy/Error
FIGURE 8-5: A/D TRANSFER FUNCTION
The overall accuracy of the A/D is less than ± 1 LSb for
VDD = 5V ± 10% and the analog VREF = VDD.This over-
all accuracy includes offset error, full scale error, and
integral error. The A/D converter is guaranteed to be
monotonic. The resolution and accuracy may be less
when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
FFh
FEh
The maximum pin leakage current is ± 5 µA.
In systems where the device frequency is low, use of
the A/D RC clock is preferred. At moderate to high fre-
quencies, TAD should be derived from the device oscil-
lator. TAD must not violate the minimum and should be
≤ 8 µs for preferred operation. This is because TAD,
when derived from TOSC, is kept away from on-chip
phase clock transitions.This reduces, to a large extent,
the effects of digital switching noise.This is not possible
with the RC derived clock. The loss of accuracy due to
digital switching noise can be significant if many I/O
pins are active.
04h
03h
02h
01h
00h
Analog input voltage
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 43
PIC12CE67X
FIGURE 8-6: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Acquire
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
SLEEP
Instruction?
A/D Clock
= RC?
GO = 0
ADIF = 1
No
No
Yes
Yes
Abort Conversion
GO = 0
Wake-up
From Sleep?
Finish Conversion
Device in
SLEEP?
Wait 2 TAD
GO = 0
ADIF = 1
ADIF = 0
No
No
SLEEP
Power-down A/D
Finish Conversion
Stay in Sleep
Power-down A/D
Wait 2 TAD
GO = 0
ADIF = 1
Wait 2 TAD
TABLE 8-2:
SUMMARY OF A/D REGISTERS
Value on
Power-on
Reset
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
INTCON
GIE
—
PEIE
ADIF
ADIE
T0IE
—
INTE GPIE
T0IF
—
INTF
—
GPIF
—
0000 000x 0000 000u
-0-- ---- -0-- ----
-0-- ---- -0-- ----
xxxx xxxx uuuu uuuu
0Bh/8Bh
0Ch
8Ch
1Eh
PIR1
—
—
—
—
PIE1
—
—
—
—
—
ADRES
A/D Result Register
ADCON0 ADCS1 ADCS0
r
CHS1 CHS0 GO/DONE
r
ADON 0000 0000 0000 0000
1Fh
ADCON1
—
—
—
—
—
PCFG2
PCFG1 PCFG0 ---- -000 ---- -000
9Fh
--xx xxxx --uu uuuu
--11 1111 --11 1111
05h
GPIO
TRIS
—
—
—
—
GP5
GP4
GP3
GP2
GP1
GP0
85h
TRIS5 TRIS4 TRIS3
TRIS2
TRIS1
TRIS0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0', r = reserved. Shaded cells are not used for A/D conversion.
Note 1: These registers can be addressed from either bank.
DS40181B-page 44
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
the chip in reset until the crystal oscillator is stable.The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC12CE67X family has a host
of such features intended to maximize system reliabil-
ity, minimize cost through elimination of external com-
ponents, provide power saving operating modes and
offer code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode.The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up, or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The EXTRC oscillator option saves system cost while
the LP crystal option saves power. A set of configura-
tion bits are used to select various options.
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
• Interrupts
9.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h-
3FFFh), which can be accessed only during
programming.
• In-circuit serial programming
The PIC12CE67X has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
FIGURE 9-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1
bit13
CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0
bit0
Register: CONFIG
Address
2007h
(1)
bit 13-8, CP1:CP0: Code Protection bit pairs
6-5: 11= Code protection off
10= Locations 400h through 7FEh code protected (do not use for PIC12CE673)
01= Locations 200h through 7FEh code protected
00= All memory is code protected
bit 7:
bit 4:
bit 3:
MCLRE: Master Clear Reset Enable bit
1 = Master Clear Enabled
0 = Master Clear Disabled
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC2:FOSC0: Oscillator Selection bits
111= EXTRC, Clockout on OSC2
110= EXTRC, OSC2 is I/O
101= INTRC, Clockout on OSC2
100= INTRC, OSC2 is I/O
011= Invalid Selection
010= HS Oscillator
001= XT Oscillator
000= LP Oscillator
Note 1: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 45
PIC12CE67X
9.2
Oscillator Configurations
TABLE 9-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC12CE67X
9.2.1
OSCILLATOR TYPES
The PIC12CE67X can be operated in seven different
oscillator modes. The user can program three
configuration bits (FOSC2:FOSC0) to select one of
these seven modes:
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
• LP:
• HS:
• XT:
Low Power Crystal
High Speed Crystal Resonator
Crystal/Resonator
HS
4.0 MHz
8.0 MHz
10.0 MHz
15-68 pF
10-68 pF
10-22 pF
15-68 pF
10-68 pF
10-22 pF
• INTRC*: Internal 4 MHz Oscillator
• EXTRC*: External Resistor/Capacitor
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
*Can be configured to support CLKOUT
9.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
TABLE 9-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC12CE67X
In XT, HS or LP modes, a crystal or ceramic resonator
is connected to the GP5/OSC1/CLKIN and GP4/OSC2
pins to establish oscillation (Figure 9-2). The
PIC12CE67X oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may give
Osc
Type
Resonator Cap.Range Cap. Range
Freq
C1
C2
(1)
LP
32 kHz
15 pF
15 pF
a
frequency out of the crystal manufacturers
100 kHz
200 kHz
15-30 pF
15-30 pF
30-47 pF
15-82 pF
specifications. When in XT, HS or LP modes, the
device can have an external clock source drive the
GP5/OSC1/CLKIN pin (Figure 9-3).
XT
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
FIGURE 9-2: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(XT, HS OR LP OSC
CONFIGURATION)
HS
4 MHz
8 MHz
10 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
(1)
C1
OSC1
PIC12CE67X
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
SLEEP
XTAL
(3)
RF
To internal
logic
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
OSC2
(2)
RS
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 9-3: EXTERNAL CLOCK INPUT
OPERATION (XT, HS OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC12CE67X
Open
DS40181B-page 46
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
9.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 9-4 shows implementation of
a
parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
Figure 9-6 shows how the R/C combination is
connected to the PIC12CE67X. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
FIGURE 9-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
PIC12CE67X
4.7k
74AS04
CLKIN
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
10k
XTAL
10k
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
20 pF
20 pF
Figure 9-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 9-6: EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
Internal
FIGURE 9-5: EXTERNAL SERIES
RESONANT CRYSTAL
clock
OSC1
N
OSCILLATOR CIRCUIT
To Other
Devices
Cext
VSS
PIC12CE67X
330
330
74AS04
74AS04
74AS04
PIC12CE67X
OSC2/CLKOUT
FOSC/4
CLKIN
0.1 µF
XTAL
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 47
PIC12CE67X
9.2.5
INTERNAL 4 MHz RC OSCILLATOR
9.3
Reset
The PIC12CE67X differentiates between various kinds
of reset:
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see "Electri-
cal Specifications" section for information on variation
over voltage and temperature.
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
In addition, a calibration instruction is programmed into
the last address of the program memory which contains
the calibration value for the internal RC oscillator. This
value is programmed as a RETLW XXinstruction where
XX is the calibration value. In order to retrieve the cali-
bration value, issue a CALL YYinstruction where YY is
the last location in program memory (03FFh for the
PIC12CE673, 07FFh for the PIC12CE674). Control will
be returned to the user’s program with the calibration
value loaded into the W register. The program should
then perform a MOVWF OSCCAL instruction to load
the value into the internal RC oscillator trim register.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), MCLR Reset, WDT
Reset, and MCLR Reset during SLEEP. They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different reset situations
as indicated in Table 9-4. These bits are used in
software to determine the nature of the reset. See
Table 9-5 for a full description of reset states of all
registers.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. Only bits <7:2> of OSC-
CAL are implemented, and bits <1:0> should be written
as 0 for compatibility with future devices. The oscillator
calibration location is not code protected.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 9-7.
The PIC12CE67X has a MCLR noise filter in the MCLR
reset path.The filter will detect and ignore small pulses.
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
It should be noted that a WDT Reset does not drive
MCLR pin low.
9.2.6
CLKOUT
The PIC12CE67X can be configured to provide a clock
out signal (CLKOUT) on pin 3 when the configuration
word address (2007h) is programmed with FOSC2,
FOSC1, FOSC0 equal to 101 for INTRC or 111 for
EXTRC. The oscillator frequency, divided by 4 can be
used for test purposes or to synchronize other logic.
DS40181B-page 48
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Weak
Pull-up
GP3/MCLR/VPP Pin
MCLRE
INTERNAL MCLR
WDT
Module
SLEEP
WDT Time-out
VDD rise
detect
Power-on Reset
VDD
S
R
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
Q
OSC1/
CLKIN
Pin
PWRT
(1)
On-chip
RC OSC
10-bit Ripple-counter
Enable PWRT
Enable OST
See Table 9-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 49
PIC12CE67X
9.4.3
OSCILLATOR START-UP TIMER (OST)
9.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over.This ensures that the crystal oscil-
lator or resonator has started and stabilized.
9.4.1
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
9.4.4
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 9-8,
Figure 9-9, and Figure 9-10 depict time-out sequences
on power-up.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 9-9). This is useful for testing purposes or to
synchronize more than one PIC12CE67X device oper-
ating in parallel.
9.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active.The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
Table 9-5 shows the reset conditions for all the regis-
ters.
9.4.5
POWER CONTROL (PCON)/STATUS
REGISTER
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
The power control/status register, PCON (address
8Eh) has one bit. See Figure 4-8 for register.
Bit1 is POR (Power-on Reset). It is cleared on a Power-
on Reset and is unaffected otherwise.The user set this
bit following a Power-on Reset. On subsequent resets
if POR is ‘0’, it will indicate that a Power-on Reset must
have occurred.
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0 PWRTE = 1
Wake-up from SLEEP
XT, HS, LP
72 ms + 1024TOSC
72 ms
1024TOSC
—
1024TOSC
—
INTRC, EXTRC
TABLE 9-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
TO
PD
0
0
0
1
1
1
1
1
0
x
0
0
u
1
1
x
0
u
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
DS40181B-page 50
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 9-5:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
uuu1 0uuu
---- --0-
---- --u-
---- --u-
---- --u-
---- --u-
---- --u-
MCLR Reset during normal operation
MCLR Reset during SLEEP
000h
000h
WDT Reset during normal operation
WDT Wake-up from SLEEP
000h
PC + 1
(1)
Interrupt wake-up from SLEEP
PC + 1
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 9-6:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or Interrupt
W
xxxx xxxx
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
11xx xxxx
---0 0000
0000 000x
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --0-
1000 00--
---- -000
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
INDF
TMR0
PCL
(2)
PC + 1
(3)
(3)
STATUS
FSR
000q quuu
uuuq quuu
uuuu uuuu
11uu uuuu
---0 0000
0000 000u
-0-- ----
0000 0000
1111 1111
--11 1111
-0-- ----
---- --u-
uuuu uu--
---- -000
uuuu uuuu
11uu uuuu
---u uuuu
GPIO
PCLATH
INTCON
PIR1
(1)
uuuu uqqq
(4)
-q-- ----
(5)
ADCON0
OPTION
TRIS
uuuu uquu
uuuu uuuu
--uu uuuu
-u-- ----
---- --u-
uuuu uu--
---- -uuu
PIE1
PCON
OSCCAL
ADCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 9-5 for reset value for specific condition.
4: If wake-up was due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause
bit 6 = u.
5: If wake-up was due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause
bit 3 = u.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 51
PIC12CE67X
FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 9-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS40181B-page 52
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-11: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 9-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
VDD
10k
D
R
MCLR
R1
4.3k
MCLR
PIC12CE67X
PIC12CE67X
C
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow.The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: Internal brown-out detection should be
disabled when using this circuit.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: Resistors should be adjusted for the char-
acteristics of the transistor.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
FIGURE 9-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
4.3k
PIC12CE67X
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
R1
= 0.7V
VDD •
R1 + R2
2: Internal brown-out detection should be
disabled, if available, when using this
circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 53
PIC12CE67X
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
9.5
Interrupts
There are four sources of interrupt:
Interrupt Sources
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
TMR0 overflow interrupt
External interrupt GP2/INT pin
GPIO Port change interrupts (pins GP0, GP1, GP3)
A/D Interrupt
The peripheral interrupt flag ADIF, is contained in the
special function register PIR1. The corresponding
interrupt enable bit is contained in special function reg-
ister PIE1, and the peripheral interrupt enable bit is
contained in special function register INTCON.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles.The exact latency depends when the
interrupt event occurs (Figure 8-15). The latency is the
same for one or two cycle instructions. Individual inter-
rupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
FIGURE 9-14: INTERRUPT LOGIC
Wakeup
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
GPIF
GPIE
PEIE
ADIF
ADIE
GIE
DS40181B-page 54
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-15: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC+1
PC+1
—
0005h
PC
Instruction
fetched
Inst (0004h)
Inst (PC)
Inst (PC+1)
Inst (0005h)
Inst (0004h)
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in INTRC and EXTRC oscillator modes.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 55
PIC12CE67X
9.5.1
TMR0 INTERRUPT
9.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack.Typically, users may wish to save key reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 7.0)
Example 9-1 store and restore the STATUS and W
registers. The register, W_TEMP, must be defined in
both banks and must be defined at the same offset
from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1).
9.5.2
INT INTERRUPT
External interrupt on GP2/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP.The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 9.8 for details on SLEEP mode.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Executes the ISR code.
d) Restores the STATUS register (and bank select
bit).
e) Restores the W register.
9.5.3
GPIO INTCON CHANGE
An input change on GP3, GP1 or GP0 sets flag bit
GPIF (INTCON<0>). The interrupt can be enabled/dis-
abled by setting/clearing enable bit GPIE
(INTCON<3>). (Section 5.1)
EXAMPLE 9-1: SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
BCF
MOVWF
:
W_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
STATUS,W
STATUS,RP0
STATUS_TEMP
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS40181B-page 56
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out early and generating a premature
device RESET condition.
9.7
Watchdog Timer (WDT)
The WatchdogTimer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEP instruction. During
normal operation, a WDT time-out generates a device
RESET (Watchdog Timer Reset). If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 9.1).
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
Note: When the prescaler is assigned to the
WDT, always execute a CLRWDTinstruction
before changing the prescale value, other-
wise a WDT reset may occur.
9.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
DD
ture, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
FIGURE 9-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-5)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 7-5)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 9-17: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Bit 7
MCLRE
GPPU
Bit 6
Bit 5
Bit 4
PWRTE WDTE FOSC2 FOSC1 FOSC0
T0SE PSA PS2 PS1 PS0
Bit 3
Bit 2
Bit 1
Bit 0
(1)
CP1
CP0
Config. bits
OPTION
INTEDG T0CS
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 9-1 for operation of these bits. Not all CP0 and CP1 bits are shown.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 57
PIC12CE67X
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
9.8
Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input if enabled should also be at VDD or VSS for
lowest current consumption. The contribution from on-
chip pull-ups on GPIO should be considered.
9.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin if enabled must be at a logic high level
(VIHMC).
• If the interrupt occurs before the the execution of
a SLEEPinstruction, the SLEEPinstruction will
complete as a NOP. Therefore, the WDT and
WDT postscaler will not be cleared, the TO bit will
not be set and PD bits will not be cleared.
9.8.1
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep . The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. GP2/INT interrupt, interrupt GPIO port change,
or some Peripheral Interrupts.
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes.To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupt can wake the device
from SLEEP:
1. A/D conversion (when A/D clock source is RC).
DS40181B-page 58
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
GPIO pin
GPIF flag
(INTCON<0>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in XT, HS or LP osc modes, but shown here for timing reference.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A 6-
bit command is then supplied to the device. Depending
on the command, 14-bits of program data are then sup-
plied to or from the device, depending if the command
was a load or a read. For complete details of serial pro-
gramming, please refer to the PIC12CE67X Program-
ming Specifications.
9.9
Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip does not recommend code pro-
tecting windowed devices.
9.10
ID Locations
FIGURE 9-19: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC12CE67X
9.11
In-Circuit Serial Programming
+5V
0V
VDD
PIC12CE67X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
VSS
VPP
MCLR/VPP
GP1
GP0
CLK
Data I/O
VDD
To Normal
Connections
The device is placed into a program/verify mode by
holding the GP1 and GP0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). GP1 (clock) becomes the programming
clock and GP0 (data) becomes the programming data.
Both GP0 and GP1 are Schmitt Trigger inputs in this
mode.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 59
PIC12CE67X
NOTES:
DS40181B-page 60
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
The instruction set is highly orthogonal and is grouped
into three basic categories:
10.0 INSTRUCTION SET SUMMARY
Each PIC12CE67X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC12CE67X instruc-
tion set summary in Table 10-2 lists byte-oriented, bit-
oriented, and literal and control operations. Table 10-
1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table 10-2 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure 10-1 shows the three general formats that the
instructions can have.
Note: To maintain upward compatibility with
future PIC12CE67X products, do not use
the OPTIONand TRISinstructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
All examples use the following format to represent a
hexadecimal number:
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 10-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
8
7
6
0
0
Don't care location (= 0 or 1)
OPCODE
d
f (FILE #)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
7 6
label Label name
TOS Top of Stack
PC Program Counter
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
General
13
8
7
0
0
OPCODE
k (literal)
PD Power-down bit
dest Destination either the W register or the specified
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
register file location
[ ] Options
Contents
( )
→
k (literal)
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 61
PIC12CE67X
10.1.3 PCL AS SOURCE OR DESTINATION
10.1
Special Function Registers as
Source/Destination
Read, write or read-modify-write on PCL may have the
following results:
The PIC12CE67X’s orthogonal instruction set allows
read and write of all file registers, including special
function registers. There are some special situations
the user should be aware of:
Read PC:
PCL → dest
Write PCL:
PCLATH → PCH;
8-bit destination value → PCL
10.1.1 STATUS AS DESTINATION
Read-Modify-Write: PCL→ ALU operand
PCLATH → PCH;
If an instruction writes to STATUS, the Z, C and DC bits
may be set or cleared as a result of the instruction and
overwrite the original data bits written. For example,
executing CLRF STATUSwill clear register STATUS, and
then set the Z bit leaving 0000 0100bin the register.
8-bit result → PCL
Where PCH = program counter high byte (not an
addressable register), PCLATH = Program counter
high holding latch, dest = destination, WREG or f.
10.1.4 BIT MANIPULATION
10.1.2 TRIS AS DESTINATION
All bit manipulation instructions are done by first read-
ing the entire register, operating on the selected bit and
writing the result back (read-modify-write). The user
should keep this in mind when operating on special
function registers, such as ports.
Bit 3 of the TRIS register always reads as a '1' since
GP3 is an input only pin.This fact can affect some read-
modify-write operations on the TRIS register.
DS40181B-page 62
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 10-2: INSTRUCTION SET SUMMARY
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 63
PIC12CE67X
10.2
Instruction Descriptions
ANDLW
And Literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
ADDLW
Add Literal and W
Syntax:
k
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Operation:
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'.The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR, 1
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
DS40181B-page 64
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
Bit 'b' in register 'f' is cleared.
Description:
1
1
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
After Instruction
Words:
Cycles:
Example
1
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 65
PIC12CE67X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Words:
Cycles:
Example
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
1(2)
=
0x5A
HERE
FALSE
TRUE
BTFSS FLAG,1
=
=
0x00
1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRW
None
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → (W)
1 → Z
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
0001
0000
0011
10
0kkk
kkkk
kkkk
W register is cleared. Zero bit (Z) is
set.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two cycle instruction.
Description:
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
2
Before Instruction
W
=
0x5A
After Instruction
HERE
CALL THERE
W
=
0x00
1
Before Instruction
Z
=
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
DS40181B-page 66
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT, 1
1
Before Instruction
CLRWDT
CNT
Z
=
=
0x01
0
Before Instruction
After Instruction
WDT counter
After Instruction
=
=
?
CNT
Z
=
=
0x00
1
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Words:
Cycles:
Example
1
Before Instruction
1(2)
REG1
After Instruction
REG1
=
0x13
HERE
DECFSZ
GOTO
CNT, 1
LOOP
=
=
0x13
0xEC
CONTINUE •
W
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
=
=
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 67
PIC12CE67X
GOTO
Unconditional Branch
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Syntax:
[ label ] GOTO k
Operands:
Operation:
0 ≤ k ≤ 2047
Operands:
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two cycle instruction.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
two cycle instruction.
Description:
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
GOTO THERE
1(2)
After Instruction
HERE
INCFSZ
GOTO
CNT,
LOOP
1
PC
=
Address THERE
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. k → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
11
1000
kkkk
kkkk
00
1010
dfff
ffff
The contents of the W register is
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
Before Instruction
INCF
CNT, 1
W
=
0x9A
Before Instruction
After Instruction
CNT
Z
=
=
0xFF
0
W
=
0xBF
1
Z
=
After Instruction
CNT
Z
=
=
0x00
1
DS40181B-page 68
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 127
MOVF
Move f
Syntax:
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register f is moved to
a destination dependant upon the sta-
tus of d. If d = 0, destination is W reg-
ister. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Description:
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
1
Before Instruction
RESULT =
0x13
0x91
MOVF
FSR, 0
W
=
After Instruction
After Instruction
RESULT =
W
Z
0x13
0x93
1
W = value in FSR register
=
=
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Syntax:
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
11
00xx
kkkk
kkkk
00
0000
1fff
ffff
The eight bit literal 'k' is loaded into W
register.The don’t cares will assemble
as 0’s.
Move data from W register to register
'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
MOVLW
0x5A
Before Instruction
OPTION =
After Instruction
0xFF
0x4F
W
=
0x5A
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 69
PIC12CE67X
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
[ label ] RETFIE
None
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Description:
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
k → (W);
TOS → PC
Status Affected: None
00
0000
0110
0010
Encoding:
Status Affected:
Encoding:
None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Description:
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE
;W contains table
;offset value
•
;Wnowhastablevalue
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
•
•
TABLE
ADDWF PC
;W = offset
;Begin table
;
RETLW k1
RETLW k2
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
DS40181B-page 70
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
RETURN
Return from Subroutine
[ label ] RETURN
None
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
Operation:
See description below
C
None
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
Cycles:
Example
1
2
C
Register f
RETURN
After Interrupt
Words:
Cycles:
Example
1
1
PC
=
TOS
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ] SLEEP
None
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1101
dfff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
Description:
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
Example
1
1
Words:
1
Cycles:
Example:
1
RLF
REG1,0
SLEEP
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 71
PIC12CE67X
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ]
SUBLW k
[ label ]
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d
[0,1]
k - (W) → (W)
Operation:
(f) - (W) → (dest)
Status
C, DC, Z
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Subtract (2’s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
=
=
=
2
2
?
1; result is zero
C
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is nega-
Example 3:
Before Instruction
tive
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
DS40181B-page 72
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
XORLW
Exclusive OR Literal with W
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
Operands:
Operation:
Status Affected:
Encoding:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
11
1010 kkkk kkkk
Status Affected:
Encoding:
None
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Description:
00
1110
dfff
ffff
The upper and lower nibbles of regis-
ter 'f' are exchanged. If 'd' is 0 the
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
Words:
Cycles:
Example
1
1
XORLW
0xAF
Before Instruction
SWAPF REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] TRIS
f
Operands:
Operation:
5 ≤ f ≤ 7
Operands:
d
[0,1]
(W) → TRIS register f;
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
00
Encoding:
0000 0110
0fff
Status Affected:
Encoding:
Z
The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Description:
00
0110
dfff
ffff
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC12C67X products,
do not use this instruction.
REG
1
XORWF
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 73
PIC12CE67X
NOTES:
DS40181B-page 74
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
11.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
11.0 DEVELOPMENT SUPPORT
11.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• MPLAB™-ICE Real-Time In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 386 through Pentium based
machines under Windows 3.x, Windows 95, or Win-
dows NT environment. ICEPIC features real time, non-
intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
11.4
PRO MATE II: Universal Programmer
• SIMICE
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
®
• KEELOQ Evaluation Kits and Programmer
11.2
MPLAB-ICE: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
11.5
PICSTART Plus Entry Level
Development System
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). MPLAB-ICE is sup-
plied with the MPLAB Integrated Development Environ-
ment (IDE), which allows editing, “make” and
download, and source debugging from a single envi-
ronment.
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive
development tools.The PC compatible 386 (and higher)
machine platform and Microsoft Windows 3.x or
Windows 95 environment were chosen to best make
these features available to you, the end user.
MPLAB-ICE
is
available
in
two
versions.
MPLAB-ICE 1000 is a basic, low-cost emulator system
with simple trace capabilities. It shares processor mod-
ules with the MPLAB-ICE 2000. This is a full-featured
emulator system with enhanced trace, trigger, and data
monitoring features. Both systems will operate across
the entire operating speed reange of the PICmicro
MCU.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 75
PIC12CE67X
11.6
SIMICE Entry-Level Hardware
Simulator
11.8
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB™-SIM. Both SIM-
ICE and MPLAB-SIM run under Microchip Technol-
ogy’s MPLAB Integrated Development Environment
(IDE) software. Specifically, SIMICE provides hardware
simulation for Microchip’s PIC12C5XX, PIC12CE5XX,
and PIC16C5X families of PICmicro™ 8-bit microcon-
trollers. SIMICE works in conjunction with MPLAB-SIM
to provide non-real-time I/O port emulation. SIMICE
enables a developer to run simulator code for driving
the target system. In addition, the target system can
provide input to the simulator code. This capability
allows for simple and interactive debugging without
having to manually generate MPLAB-SIM stimulus
files. SIMICE is a valuable debugging tool for entry-
level system development.
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
11.7
PICDEM-1 Low-Cost PICmicro
Demonstration Board
11.9
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
DS40181B-page 76
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
11.10 MPLAB Integrated Development
Environment Software
11.12 Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPASM. The Software Simulator
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
11.13 MPLAB-C17 Compiler
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
The MPLAB-C17 Code Development System is a
complete ANSI ‘C’ compiler and integrated develop-
ment environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
- absolute listing file
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
11.14 Fuzzy Logic Development System
(fuzzyTECH-MP)
11.11 Assembler (MPASM)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
11.15 SEEVAL Evaluation and
Programming System
MPASM allows full symbolic debugging from MPLAB-
ICE, Microchip’s Universal Emulator System.
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
MPASM has the following features to assist in develop-
ing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol, and
special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 77
PIC12CE67X
11.16 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS40181B-page 78
Preliminary
1998 Microchip Technology Inc.
24CXX
HCS200
HCS300
HCS301
PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 25CXX
93CXX
MPLAB™-ICE
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ICEPIC Low-Cost
In-Circuit Emulator
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB
Integrated
Development
Environment
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB C17*
Compiler
fuzzyTECH -MP
Explorer/Edition
Fuzzy Logic
ü
ü
ü
ü
ü
ü
Dev. Tool
Total Endurance
Software Model
ü
PICSTART Plus
Low-Cost
Universal Dev. Kit
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PRO MATE II
Universal
ü
ü
ü
ü
Programmer
KEELOQ
Programmer
SEEVAL
Designers Kit
SIMICE
ü
ü
ü
PICDEM-14A
PICDEM-1
PICDEM-2
PICDEM-3
ü
ü
ü
ü
ü
ü
ü
®
KEELOQ
Evaluation Kit
ü
ü
KEELOQ
Transponder Kit
PIC12CE67X
NOTES:
DS40181B-page 80
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
12.0 ELECTRICAL CHARACTERISTICS FOR PIC12CE67X
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................. .–40° to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)................................................... –0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Total power dissipation (Note 1)...........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................125 mA
Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by GPIO pins combined...................................................................................................100 mA
Maximum current sourced by GPIO pins combined..............................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 81
PIC12CE673-04
PIC12CE674-04
PIC12CE673-10
PIC12CE674-10
PIC12LCE673-04
PIC12LCE674-04
PIC12CE673/JW
PIC12CE674/JW
OSC
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
VDD: 3.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 3.0V to 5.5V
IDD:
IPD:
2.7 mA typ. at 5.5V
1.5 µA typ. at 4V
IDD:
IPD:
2.0 mA typ. at 2.5V
0.9 µA typ. at 2.5V
IDD:
IPD:
5 mA max. at 5.5V
21 µA max. at 4V
INTRC
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
VDD: 2.5V to 5.5V
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
IDD:
IPD:
2.7 mA typ. at 5.5V
1.5 µA typ. at 4V
IDD:
IPD:
2.0 mA typ. at 2.5V
0.9 µA typ. at 2.5V
IDD:
IPD:
5 mA max. at 5.5V
21 µA max. at 4V
EXTRC
XT
IPD:
21 µA max. at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 3.0V to 5.5V
IDD: 5 mA max. at 5.5V
VDD: 3.0V to 5.5V
IDD:
IPD:
VDD: 2.5V to 5.5V
IDD:
IPD:
VDD: 3.0V to 5.5V
IDD:
IPD:
2.7 mA typ. at 5.5V
1.5 µA typ. at 4V
2.0 mA typ. at 2.5V
0.9 µA typ. at 2.5V
5 mA max. at 5.5V
21 µA max. at 4V
IPD:
21 µA max. at 4V
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 3.0V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IDD:
IPD:
30 mA max. at 5.5V
1.5 µA typ. at 4.5V
IDD:
IPD:
30 mA max. at 5.5V
1.5 µA typ. at 4.5V
HS
LP
N/A
IPD:
1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
Freq: 10 MHz max.
VDD: 3.0V to 5.5V
48 µA max. at 32 kHz, 2.5V IDD: 48 µA max. at 32 kHz, 2.5V
5.0 µA max. at 2.5V IPD: 5.0 µA max. at 2.5V
Freq: 200 kHz max.
VDD: 3.0V to 5.5V
IDD: 52.5 µA typ. at 32 kHz, 4.0V
VDD: 2.5V to 5.5V
IDD:
IPD:
N/A
IPD:
0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user
select the device type that ensures the specifications required.
PIC12CE67X
(5)
12.1
DC Characteristics:
PIC12CE673-04 (Commercial, Industrial, Extended )
(5)
(5)
(5)
PIC12CE673-10 (Commercial, Industrial, Extended
PIC12CE674-04 (Commercial, Industrial, Extended
PIC12CE674-10 (Commercial, Industrial, Extended
)
)
)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
Parm
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
Supply Voltage
VDD 3.0
4.5
-
-
5.5
V
XT, INTRC, EXTRC and LP osc configura-
tion
HS osc configuration
D001A
D002
5.5
-
V
V
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
Device in SLEEP mode
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPO VSS
R
VSS
V
See section on Power-on Reset for details
D004
D010
VDD rise rate to ensure inter- SVD 0.05
-
-
V/ms See section on Power-on Reset for details
nal Power-on Reset signal
D
Supply Current (Note 2)
No read/write to EEPROM
peripheral
IDD
-
2.7
3.3
mA XT, EXTRC osc configuration
(PIC12CE67X-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
mA INTRC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 6)
mA HS osc configuration (PIC12CE67X-10)
FOSC = 10 MHz, VDD = 5.5V
D010A
D013
2.7
3.3
-
TBD 15
D028
∆IEE
0.1
0.2
VDD = 5.5V
SCL = 400 kHz
D020
D021
D021A
D021B
Power-down Current (Note 3) IPD
-
-
-
-
5.5
1.5
1.5
32
16
14
µA VDD = 4.0V, WDT enabled, –40°C to +85°C
µA VDD = 4.0V, WDT disabled, 0°C to +70°C
µA VDD = 4.0V, WDT disabled, –40°C to
1.5 TBD µA +85°C
VDD = 4.0V, WDT disabled, –40°C to
+125°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For EXTRC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Extended operating range is Advance Information for this device.
6: INTRC calibration value is for 4 MHz nominal at 5V, 35°C.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 83
PIC12CE67X
12.2
DC Characteristics:
PIC12LCE673-04 (Commercial, Industrial)
PIC12LCE674-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature 0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Supply Voltage
Sym Min Typ† Max Units
Conditions
D001
D002*
D003
VDD
2.5
-
5.5
V
V
V
XT, INTRC, EXTRC and LP osc configuration
(DC - 4 MHz)
RAM Data Retention VDR
Voltage (Note 1)
-
-
TBD
VSS
-
-
Device in SLEEP mode
VDD start voltage to
ensure internal
Power-on Reset
signal
VPOR
SVDD
IDD
See section on Power-on Reset for details
D004*
VDD rise rate to
ensure internal
Power-on Reset
signal
TBD
-
-
V/ms See section on Power-on Reset for details
D010
Supply Current
(Note 2)
-
-
TBD TBD mA XT, EXTRC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
TBD TBD mA INTRC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 5)
D010B
D010A
TBD TBD µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
Power-down Current IPD
(Note 3)
-
-
-
TBD
TBD
TBD
µA VDD = 3.0V, WDT enabled, –40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, –40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For EXTRC osc configuration, current through Rext is not included. The current through the resistor can be
estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: INTRC calibration value is for 4 MHz nominal at 5V, 25°C.
DS40181B-page 84
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
(4)
12.3
DC Characteristics:
PIC12CE673-04 (Commercial, Industrial, Extended )
(4)
PIC12CE673-10 (Commercial, Industrial, Extended )
(4)
PIC12CE674-04 (Commercial, Industrial, Extended )
(4)
PIC12CE674-10 (Commercial, Industrial, Extended )
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D033
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
2.0
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
0.8VDD
0.8VDD
0.8VDD
0.7VDD
0.9VDD
50
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
D042A OSC1 (XT, HS and LP)
D043
D070
Note1
OSC1 (in EXTRC mode)
GPIO weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
IPUR
IIL
250 400
µA VDD = 5V, VPIN = VSS
D060
-
-
+1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
(5)
D061
D063
MCLR, GP2/T0CKI
OSC1
-
-
-
-
µA Vss ≤ VPIN ≤ VDD
+5
+5
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
D080
D080A
D083
D083A
†
I/O ports/CLKOUT
VOL
-
-
-
-
-
-
-
-
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
–40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
–40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
–40°C to +125°C
OSC2
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Extended operating range is Advance Information for this device.
5: When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum.
This pull-up is weaker than the standard I/O pull-up.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 85
PIC12CE67X
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
–40°C ≤ TA ≤ +125˚C (extended)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Output High Voltage
Sym
Min
Typ Max Units
†
Conditions
D090
I/O ports/CLKOUT (Note 3)
VOH VDD - 0.7
VDD - 0.7
-
-
-
-
-
-
-
-
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
–40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
–40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
–40°C to +125°C
D090A
D092
OSC2
VDD - 0.7
D092A
VDD - 0.7
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
CIO
-
-
-
-
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
†
All I/O pins and OSC2
pF
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Extended operating range is Advance Information for this device.
5: When configured as external reset, the input leakage current is the weak pulll-up current of -10mA minimum.
This pull-up is weaker than the standard I/O pull-up.
DS40181B-page 86
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
12.4
DC Characteristics:
PIC12LCE671-04 (Commercial, Industrial)
PIC12LCE672-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
TBD
TBD
TBD
V
V
V
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
(in EXTRC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D033
VSS
-
TBD
V
Note1
VIH
-
-
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
TBD
TBD
TBD
TBD
TBD
TBD
TBD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
with Schmitt Trigger buffer
MCLR, GP2/T0CKI/AN2/INT
D042A OSC1 (XT, HS and LP)
D043
D070
Note1
OSC1 (in EXTRC mode)
GPIO weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
IPUR
IIL
TBD TBD
µA VDD = 5V, VPIN = VSS
D060
-
TBD TBD
µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061
D063
MCLR, GP3
OSC1
-
-
TBD TBD
TBD TBD
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
D080
I/O ports/CLKOUT
VOL
-
-
-
-
TBD 0.6
TBD 0.6
TBD 0.6
TBD 0.6
V
V
V
V
IOL = TBD, VDD = 4.5V,
–40°C to +85°C
IOL = TBD, VDD = 4.5V,
–40°C to +125°C
IOL = TBD, VDD = 4.5V,
–40°C to +85°C
IOL = TBD, VDD = 4.5V,
–40°C to +125°C
D080A
D083
OSC2
D083A
Output High Voltage
D090
D090A
D092
D092A
†
I/O ports/CLKOUT (Note 3)
VOH VDD - 0.7
VDD - 0.7
-
-
-
-
-
-
-
-
V
V
V
V
IOH = TBD, VDD = 4.5V,
–40°C to +85°C
IOH = TBD, VDD = 4.5V,
–40°C to +125°C
IOH = TBD, VDD = 4.5V,
–40°C to +85°C
IOH = TBD, VDD = 4.5V,
–40°C to +125°C
OSC2
VDD - 0.7
VDD - 0.7
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Extended operating range is Advance Information for this device.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 87
PIC12CE67X
Standard Operating Conditions (unless otherwise specified)
Operating temperature
0˚C ≤ TA ≤ +70˚C (commercial)
–40˚C ≤ TA ≤ +85˚C (industrial)
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 12.1 and
Section 12.2.
Param
No.
Characteristic
Sym
Min
Typ Max Units
†
Conditions
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
CIO
-
-
-
-
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
†
All I/O pins and OSC2
pF
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that
the PIC12C67X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Extended operating range is Advance Information for this device.
DS40181B-page 88
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
12.5
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 12-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 89
PIC12CE67X
12.6
Timing Diagrams and Specifications
FIGURE 12-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
3
4
2
CLKOUT
TABLE 12-2: CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ†
Max
Units Conditions
Fosc External CLKIN Frequency
DC
DC
DC
DC
DC
.455
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz XT and EXTRC osc mode
MHz HS osc mode (PIC12CE67X-04)
MHz HS osc mode (PIC12CE67X-10)
kHz LP osc mode
(Note 1)
10
200
4
Oscillator Frequency
(Note 1)
MHz EXTRC osc mode
4
MHz XT osc mode
4
MHz HS osc mode (PIC12CE67X-04)
MHz HS osc mode (PIC12CE67X-10)
kHz LP osc mode
4
10
200
—
5
1
Tosc External CLKIN Period
250
250
100
5
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
XT and EXTRC osc mode
HS osc mode (PIC12CE67X-04)
HS osc mode (PIC12CE67X-10)
LP osc mode
(Note 1)
—
—
—
Oscillator Period
(Note 1)
250
250
250
100
5
—
EXTRC osc mode
XT osc mode
10,000
250
250
—
HS osc mode (PIC12CE67X-04)
HS osc mode (PIC12CE67X-10)
LP osc mode
2
3
TCY
Instruction Cycle Time (Note 1) 400
DC
—
TCY = 4/FOSC
TosL, External Clock in (OSC1) High
TosH or Low Time
50
2.5
10
—
XT oscillator
—
LP oscillator
—
HS oscillator
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
25
50
15
XT oscillator
—
LP oscillator
—
HS oscillator
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC12CE67X.
DS40181B-page 90
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
Sym
(1)
Characteristic
Min*
Max* Units
Conditions
MHz VDD = 5.0V
MHz VDD = 2.5V
Typ
No.
Internal Calibrated RC Frequency
TBD
4.00
TBD
TBD
Internal Calibrated RC Frequency
TBD
4.00
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 91
PIC12CE67X
FIGURE 12-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
10
—
—
—
25
25
—
—
ns
ns
ns
ns
ns
TioR
TioF
Tinp
Trbp
Port output rise time
Port output fall time
INT pin high or low time
PIC12CE67X
PIC12CE67X
21*
—
22††*
23††*
20
GPIO change INT high or low time
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.
DS40181B-page 92
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
36
RESET
34
31
34
I/O Pins
TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
7
—
—
µs VDD = 5V, –40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
18
33
ms VDD = 5V, –40˚C to +125˚C
(No Prescaler)
32
33*
34
Tost
Oscillation Start-up Timer Period
—
28
—
1024TOSC
—
132
2.1
—
TOSC = OSC1 period
Tpwrt Power up Timer Period
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
These parameters are characterized but not tested.
72
—
ms VDD = 5V, –40˚C to +125˚C
TIOZ
µs
*
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 93
PIC12CE67X
FIGURE 12-5: TIMER0 CLOCK TIMINGS
GP2/T0CKI
41
40
42
TMR0
Note: Refer to Figure 12-1 for load conditions.
TABLE 12-6: TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20*
10*
Greater of:
ns N = prescale value
(1, 2, 4,..., 256)
20µs or TCY + 40*
N
48
Tcke2tmrI Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2Tosc
—
7Tosc
—
*
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TABLE 12-7: GPIO PULL-UP RESISTOR RANGES
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
GP0/GP1
2.5
–40
25
38K
42K
42K
50K
15K
18K
19K
22K
42K
48K
49K
55K
17K
20K
22K
24K
63K
63K
63K
63K
20K
23K
25K
28K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
–40
25
5.5
85
125
GP3
2.5
5.5
–40
25
285K
343K
368K
431K
247K
288K
306K
351K
346K
414K
457K
504K
292K
341K
371K
407K
417K
532K
532K
593K
360K
437K
448K
500K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
–40
25
85
125
*
These parameters are characterized but not tested.
DS40181B-page 94
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
TABLE 12-8: A/D CONVERTER CHARACTERISTICS:
PIC12CE673-04 (COMMERCIAL, INDUSTRIAL, EXTENDED
(3)
)
)
)
)
(3)
(3)
(3)
PIC12CE673-10 (COMMERCIAL, INDUSTRIAL, EXTENDED
PIC12CE674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED
PIC12CE674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
—
—
—
—
—
—
8-bits
—
—
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
(Notes 4,5)
NINT Integral error
less than
±1 LSb
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
(Notes 4,5)
NDIF Differential error
less than
±1 LSb
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
(Notes 4,5)
NFS
Full scale error
less than
±1 LSb
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
(Notes 4,5)
NOFF Offset error
less than
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
±1 LSb
(Notes 4,5)
—
Monotonicity
—
Typ
—
—
—
V
VSS ≤ AIN ≤ VREF
VREF Reference voltage
3.0V
VDD + 0.3
VREF + 0.3
10.0
VAIN Analog input voltage VSS - 0.3
—
V
ZAIN Recommended
impedance of analog
—
—
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
3: Extended operating range is Advance Information for this device.
4: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
5: When using external VREF, VDD must be greater than 3V for +1 LSB accuracy. If VDD is less than 3V, you must
use internal VREF for +1 LSB.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 95
PIC12CE67X
TABLE 12-9: A/D CONVERTER CHARACTERISTICS:
PIC12LCE673-04 (COMMERCIAL, INDUSTRIAL)
PIC12LCE674-04 (COMMERCIAL, INDUSTRIAL)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 3.0V (Notes 1,4)
VREF = VDD = 3.0V (Notes 1,4)
NINT
Integral error
less than
±1 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 3.0V (Notes 1,4)
VREF = VDD = 3.0V (Notes 1,4)
VREF = VDD = 3.0V (Notes 1,4)
VSS ≤ AIN ≤ VREF
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
Typ
—
—
—
V
VREF Reference voltage
TBD
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage VSS - 0.3
—
V
Recommended
—
—
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
TBD
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
TBD
TBD
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from GP1 pin or VDD pin, whichever is selected as reference input.
4: When using external VREF, VDD must be greater than 3V for +1 LSB accuracy. If VDD is less than 3V, you
must use internal VREF for +1 LSB.
DS40181B-page 96
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 12-6: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
OLD_DATA
ADRES
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-10: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
VREF ≥ 3.0V
130
TAD
TAD
A/D clock period
1.6
2.0
—
—
µs
µs VREF full range
130
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
3.0
2.0
—
6.0
4.0
9.0
6.0
—
µs PIC12LCE67X, VDD = 3.0V
µs PIC12CE67X
131
132
TCNV Conversion time
(not including S/H
time). Note 1
9.5TAD
—
TACQ Acquisition time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 97
PIC12CE67X
NOTES:
DS40181B-page 98
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
13.0 DC AND AC CHARACTERISTICS - PIC12CE67X
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the
data presented are outside specified operating range (e.g., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 13-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
TO BE DETERMINED
FIGURE 13-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 3.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
TO BE DETERMINED
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 99
PIC12CE67X
TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
Oscillator
External RC
Frequency
VDD = 2.5V
VDD = 5.5V
4 MHz
4 MHz
4 MHz
32 KHz
TBD µA*
TBD µA
TBD µA
TBD µA
620 µA*
1.1 mA
775 µA
37 µA
Internal RC
XT
LP
*Does not include current through external R&C.
FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs. VDD
50
45
40
35
30
Max +125°C
25
Max +85°C
20
Typ +25°C
15
10
MIn –40°C
5
2
3
4
5
6
7
VDD (Volts)
DS40181B-page 100
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V
FIGURE 13-6: IOL vs. VOL, VDD = 2.5 V
25
20
15
10
0
-1
-2
Max –40°C
Typ +25°C
-3
-4
Min +85°C
-5
Min +125°C
5
0
-6
-7
500m
1.0
1.5
2.0
2.5
VOH (Volts)
0
250.0m
500.0m
1.0
VOL (Volts)
FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V
FIGURE 13-7: IOL vs. VOL, VDD = 3.5 V
0
-3
-5
40
Max –40°C
30
20
-8
-10
Typ +25°C
Min +85°C
-13
-15
Min +125°C
10
0
-18
-20
.50
1.5
2.0
2.5
3.0
0
.50
.75
1.0
VOH (Volts)
VOL (Volts)
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 101
PIC12CE67X
FIGURE 13-8: IOH vs. VOH, VDD = 5.5 V
FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V
50
0
Max –40°C
-5
40
30
20
-10
Typ +25°C
-15
-20
Min +85°C
Min +125°C
-25
-30
10
0
3.5
4.0
4.5
5.0
5.5
VOH (Volts)
.25
.50
.75
1.0
VOL (Volts)
DS40181B-page 102
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
14.0 PACKAGING INFORMATION
14.1
Package Marking Information
8-Lead PDIP (300 mil)
Example
12CE674
MMMMMMMM
XXXXXCDE
04/PSAZ
AABB
9725
Example
8-Lead Windowed Ceramic Side Brazed (300 mil)
JW
MM
CE674
MMMMMM
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 103
PIC12CE67X
Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
1
n
α
E1
A
A1
L
R
c
A2
β
B1
p
eB
B
INCHES*
NOM
0.300
8
MILLIMETERS
Units
MAX
MIN
NOM
7.62
8
MAX
Dimension Limits
PCB Row Spacing
Number of Pins
MIN
n
Pitch
p
B
B1
R
c
0.100
0.018
0.060
0.005
0.012
0.150
0.080
0.020
0.130
0.370
0.250
0.280
0.342
10
2.54
0.56
Lower Lead Width
Upper Lead Width
Shoulder Radius
0.014
0.022
0.36
1.40
0.46
1.52
0.13
0.29
3.81
2.03
0.51
3.30
9.40
6.35
7.10
8.67
10
†
1.65
0.25
0.38
4.06
2.54
0.89
3.56
9.78
6.60
7.42
9.65
15
0.055
0.000
0.006
0.140
0.060
0.005
0.120
0.355
0.245
0.267
0.310
5
0.065
0.010
0.015
0.160
0.100
0.035
0.140
0.385
0.260
0.292
0.380
15
0.00
0.20
3.56
1.52
0.13
3.05
9.02
6.22
6.78
7.87
5
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A1
A2
L
D
E
E1
eB
α
‡
‡
β
5
10
15
5
10
15
* Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40181B-page 104
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil
E
W
T
D
2
1
n
U
A
A1
L
A2
c
B1
p
eB
B
Units
MILLIMETERS
INCHES*
NOM
0.300
8
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Lead Thickness
Top to Seating Plane
Top of Body to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
MIN
MAX
MIN
NOM
7.62
8
MAX
n
p
B
B1
c
0.098
0.016
0.050
0.008
0.145
0.103
0.025
0.130
0.510
0.280
0.310
0.161
0.440
0.260
0.100
0.018
0.055
0.010
0.165
0.123
0.035
0.140
0.520
0.290
0.338
0.166
0.450
0.270
0.102
2.49
0.41
2.54
0.46
1.40
0.25
4.19
3.12
0.89
3.56
13.21
7.37
8.57
4.22
11.43
6.86
2.59
0.020
0.060
0.012
0.185
0.143
0.045
0.150
0.530
0.300
0.365
0.171
0.460
0.280
0.51
1.52
0.30
4.70
3.63
1.14
3.81
13.46
7.62
9.27
4.34
11.68
7.11
1.27
0.20
3.68
2.62
0.64
3.30
12.95
7.11
7.87
4.09
11.18
6.60
A
A1
A2
L
D
E
eB
W
T
Package Width
Overall Row Spacing
Window Diameter
Lid Length
Lid Width
U
* Controlling Parameter.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 105
PIC12CE67X
NOTES:
DS40181B-page 106
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
CALSLW bit........................................................................ 21
Carry bit.................................................................................7
Clocking Scheme................................................................ 10
CLRF Instruction................................................................. 66
CLRW Instruction ............................................................... 66
CLRWDT Instruction........................................................... 67
Code Examples
Changing Prescaler (Timer0 to WDT) ........................ 35
Changing Prescaler (WDT to Timer0) ........................ 35
Indirect Addressing..................................................... 23
Code Protection............................................................ 45, 59
COMF Instruction ............................................................... 67
Computed GOTO ............................................................... 22
Configuration Bits ............................................................... 45
INDEX
A
A/D
Accuracy/Error ............................................................ 43
ADCON0 Register....................................................... 37
ADIF bit....................................................................... 39
Analog Input Model Block Diagram............................. 40
Analog-to-Digital Converter......................................... 37
Configuring Analog Port Pins...................................... 41
Configuring the Interrupt ............................................. 39
Configuring the Module............................................... 39
Connection Considerations......................................... 43
Conversion Clock........................................................ 41
Conversions................................................................ 42
Converter Characteristics ........................................... 95
Delays......................................................................... 40
Effects of a Reset........................................................ 43
Equations.................................................................... 40
Flowchart of A/D Operation......................................... 44
GO/DONE bit .............................................................. 39
Internal Sampling Switch (Rss) Impedence................ 40
Operation During Sleep .............................................. 43
Sampling Requirements.............................................. 40
Sampling Time............................................................ 40
Source Impedence...................................................... 40
Time Delays................................................................ 40
Transfer Function........................................................ 43
Absolute Maximum Ratings ................................................ 81
ADDLW Instruction ............................................................. 64
ADDWF Instruction ............................................................. 64
ADIE bit............................................................................... 18
ADIF bit............................................................................... 19
ADRES Register ..................................................... 13, 37, 39
ALU....................................................................................... 7
ANDLW Instruction ............................................................. 64
ANDWF Instruction ............................................................. 64
Application Notes
D
DC bit.................................................................................. 15
DC Characteristics
PIC12CE673............................................................... 83
PIC12CE674............................................................... 83
DECF Instruction ................................................................ 67
DECFSZ Instruction............................................................ 67
Development Support..................................................... 3, 75
Development Tools............................................................. 75
Diagrams - See Block Diagrams
Digit Carry bit.........................................................................7
Direct Addressing ............................................................... 23
E
EEPROM Peripheral Operation.......................................... 27
Electrical Characteristics
PIC12CE67X .............................................................. 81
Errata.....................................................................................2
External Brown-out Protection Circuit................................. 53
External Power-on Reset Circuit ........................................ 53
F
Family of Devices ..................................................................4
Features ................................................................................1
FSR Register.......................................................... 13, 14, 23
Fuzzy Logic Dev. System (fuzzyTECH -MP).................... 77
AN546......................................................................... 37
AN556......................................................................... 22
Architecture
Harvard ......................................................................... 7
Overview....................................................................... 7
von Neumann................................................................ 7
Assembler
G
General Description...............................................................3
GIE bit................................................................................. 54
GOTO Instruction ............................................................... 68
GPIF bit .............................................................................. 56
GPIO............................................................................. 25, 51
GPIO Register .................................................................... 13
GPPU bit............................................................................. 16
MPASM Assembler..................................................... 77
B
BCF Instruction ................................................................... 65
Bit Manipulation .................................................................. 62
Block Diagrams
I
I/O Interfacing..................................................................... 25
I/O Ports ............................................................................. 25
I/O Programming Considerations ....................................... 26
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator............ 75
ID Locations........................................................................ 45
INCF Instruction.................................................................. 68
INCFSZ Instruction............................................................. 68
In-Circuit Serial Programming ...................................... 45, 59
INDF Register............................................................... 14, 23
Indirect Addressing............................................................. 23
Initialization Conditions for All Registers ............................ 51
Instruction Cycle................................................................. 10
Instruction Flow/Pipelining.................................................. 10
Instruction Format............................................................... 61
Instruction Set
Analog Input Model..................................................... 40
On-Chip Reset Circuit................................................. 49
Timer0......................................................................... 31
Timer0/WDT Prescaler ............................................... 34
Watchdog Timer.......................................................... 57
BSF Instruction ................................................................... 65
BTFSC Instruction............................................................... 65
BTFSS Instruction............................................................... 66
C
C bit..................................................................................... 15
CAL0 bit .............................................................................. 21
CAL1 bit .............................................................................. 21
CAL2 bit .............................................................................. 21
CAL3 bit .............................................................................. 21
CALFST bit ......................................................................... 21
CALL Instruction ................................................................. 66
ADDLW....................................................................... 64
ADDWF ...................................................................... 64
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 107
PIC12CE67X
ANDLW.......................................................................64
ANDWF.......................................................................64
BCF.............................................................................65
BSF.............................................................................65
BTFSC ........................................................................65
BTFSS ........................................................................66
CALL...........................................................................66
CLRF...........................................................................66
CLRW .........................................................................66
CLRWDT.....................................................................67
COMF .........................................................................67
DECF ..........................................................................67
DECFSZ......................................................................67
GOTO .........................................................................68
INCF............................................................................68
INCFSZ.......................................................................68
IORLW ........................................................................68
IORWF........................................................................69
MOVF..........................................................................69
MOVLW ......................................................................69
MOVWF ......................................................................69
NOP ............................................................................70
OPTION ......................................................................70
RETFIE .......................................................................70
RETLW .......................................................................70
RETURN.....................................................................71
RLF .............................................................................71
RRF.............................................................................71
SLEEP ........................................................................71
SUBLW .......................................................................72
SUBWF.......................................................................72
SWAPF .......................................................................73
TRIS............................................................................73
XORLW.......................................................................73
XORWF.......................................................................73
Section........................................................................61
INTCON Register................................................................17
INTEDG bit..........................................................................16
Internal Sampling Switch (Rss) Impedence ........................40
Interrupts.............................................................................45
A/D..............................................................................54
GP2/INT......................................................................54
GPIO Port ...................................................................54
Section........................................................................54
TMR0 ..........................................................................56
TMR0 Overflow...........................................................54
IORLW Instruction...............................................................68
IORWF Instruction...............................................................69
IRP bit .................................................................................15
MPLAB Integrated Development Environment Software.... 77
N
NOP Instruction .................................................................. 70
O
Opcode ............................................................................... 61
OPTION Instruction ............................................................ 70
OPTION Register................................................................ 16
Orthogonal............................................................................ 7
OSC selection..................................................................... 45
OSCCAL Register............................................................... 21
Oscillator
EXTRC ....................................................................... 50
HS............................................................................... 50
INTRC......................................................................... 50
LP ............................................................................... 50
XT............................................................................... 50
Oscillator Configurations..................................................... 46
Oscillator Types
EXTRC ....................................................................... 46
HS............................................................................... 46
INTRC......................................................................... 46
LP ............................................................................... 46
XT............................................................................... 46
P
Package Marking Information........................................... 103
Packaging Information...................................................... 103
Paging, Program Memory................................................... 22
PCL..................................................................................... 62
PCL Register .......................................................... 13, 14, 22
PCLATH.............................................................................. 51
PCLATH Register ................................................... 13, 14, 22
PCON Register............................................................. 20, 50
PD bit............................................................................ 15, 48
PIC12CE67X DC and AC Characteristics .......................... 99
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 76
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 76
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 76
PICSTART Plus Entry Level Development System......... 75
PIE1 Register...................................................................... 18
Pinout Description
PIC12CE67X ................................................................ 9
PIR1 Register ..................................................................... 19
POP .................................................................................... 22
POR.................................................................................... 50
Oscillator Start-up Timer (OST)............................ 45, 50
Power Control Register (PCON)................................. 50
Power-on Reset (POR)................................... 45, 50, 51
Power-up Timer (PWRT)...................................... 45, 50
Power-Up-Timer (PWRT) ........................................... 50
Time-out Sequence .................................................... 50
Time-out Sequence on Power-up............................... 52
TO............................................................................... 48
Power.................................................................................. 48
Power-down Mode (SLEEP)............................................... 58
Prescaler, Switching Between Timer0 and WDT................ 35
PRO MATE II Universal Programmer .............................. 75
Product Identification System - PIC12CE67X................... 113
Program Branches................................................................ 7
Program Memory
K
KeeLoq Evaluation and Programming Tools....................78
L
Loading of PC .....................................................................22
M
MCLR............................................................................48, 51
Memory
Data Memory ..............................................................11
Program Memory ........................................................11
Program Memory Map
PIC12CE67X.......................................................11
Register File Map
Paging ........................................................................ 22
Program Memory Map
PIC12CE67X.......................................................12
MOVF Instruction ................................................................69
MOVLW Instruction.............................................................69
MOVWF Instruction.............................................................69
PIC12CE67X .............................................................. 11
Program Verification ........................................................... 59
PS0 bit ................................................................................ 16
PS1 bit ................................................................................ 16
DS40181B-page 108
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
PS2 bit ................................................................................ 16
PSA bit................................................................................ 16
PUSH.................................................................................. 22
Timers
Timer0
Block Diagram.................................................... 31
External Clock .................................................... 33
External Clock Timing ........................................ 33
Increment Delay ................................................. 33
Interrupt.............................................................. 31
Interrupt Timing .................................................. 32
Prescaler ............................................................ 34
Prescaler Block Diagram.................................... 34
Section ............................................................... 31
Switching Prescaler Assignment........................ 35
Synchronization.................................................. 33
T0CKI ................................................................. 33
T0IF.................................................................... 56
Timing................................................................. 31
TMR0 Interrupt ................................................... 56
R
RC Oscillator....................................................................... 47
Read Modify Write .............................................................. 26
Read-Modify-Write.............................................................. 26
Register File........................................................................ 11
Registers
Map
PIC12CE67X ...................................................... 12
Reset Conditions......................................................... 51
Reset............................................................................. 45, 48
Reset Conditions for Special Registers .............................. 51
RETFIE Instruction.............................................................. 70
RETLW Instruction.............................................................. 70
RETURN Instruction ........................................................... 71
RLF Instruction.................................................................... 71
RP0 bit .......................................................................... 11, 15
RP1 bit ................................................................................ 15
RRF Instruction................................................................... 71
Timing Diagrams
A/D Conversion .......................................................... 97
CLKOUT and I/O ........................................................ 92
External Clock Timing................................................. 90
Time-out Sequence .................................................... 52
Timer0 .................................................................. 31, 94
Timer0 Interrupt Timing .............................................. 32
Timer0 with External Clock......................................... 33
Wake-up from Sleep via Interrupt............................... 59
TO bit.................................................................................. 15
TOSE bit............................................................................. 16
TRIS Instruction.................................................................. 73
TRIS Register......................................................... 14, 25, 26
Two’s Complement................................................................7
S
SEEVAL Evaluation and Programming System............... 77
Services
One-Time-Programmable (OTP) .................................. 5
Quick-Turnaround-Production (QTP)............................ 5
Serialized Quick-Turnaround Production (SQTP)......... 5
SFR..................................................................................... 62
SFR As Source/Destination ................................................ 62
SLEEP .......................................................................... 45, 48
SLEEP Instruction............................................................... 71
Software Simulator (MPLAB-SIM) ...................................... 77
Special Features of the CPU .............................................. 45
Special Function Register
U
UV Erasable Devices.............................................................5
W
PIC12CE67X............................................................... 13
Special Function Registers ................................................. 62
Special Function Registers, Section ................................... 12
Stack................................................................................... 22
Overflows.................................................................... 22
Underflow.................................................................... 22
STATUS Register ............................................................... 15
SUBLW Instruction.............................................................. 72
SUBWF Instruction ............................................................. 72
SWAPF Instruction.............................................................. 73
W Register
ALU................................................................................7
Wake-up from SLEEP ........................................................ 58
Watchdog Timer (WDT).................................... 45, 48, 51, 57
WDT ................................................................................... 51
Block Diagram ............................................................ 57
Period ......................................................................... 57
Programming Considerations..................................... 57
Timeout....................................................................... 51
WWW, On-Line Support........................................................2
T
X
T0CS bit.............................................................................. 16
TAD...................................................................................... 41
Timer0
XORLW Instruction............................................................. 73
XORWF Instruction............................................................. 73
Z
RTCC.......................................................................... 51
Z bit..................................................................................... 15
Zero bit ..................................................................................7
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 109
PIC12CE67X
DS40181B-page 110
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
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ety of Microchip specific business information is also
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available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trade-
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• Job Postings
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• Links to other useful web sites related to
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technical information and more
All other trademarks mentioned herein are the property of
their respective companies.
• Listing of seminars and events
1998 Microchip Technology Inc.
DS40181B-page10-111
PIC12CE67X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Literature Number:
DS40181B
Device:
PIC12CE67X
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
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DS40181B-page10-112
1998 Microchip Technology Inc.
PIC12CE67X
PIC12CE67X PRODUCT IDENTIFICATION SYSTEM
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
a)
b)
c)
PIC12CE673-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
Package:
P
JW
= 300 mil PDIP
= 300 mil Windowed Ceramic Side Brazed
Temperature
Range:
-
= 0°C to +70°C
= -40°C to +85°C
= -40°C to +125°C
PIC12CE673-04I/P
Industrial Temp., PDIP
package,4 MHz,normal
VDD limits
I
E
Frequency
Range:
04
10
= 4 MHz/200 kHz
= 10 MHz
PIC12CE673-10I/P
Industrial Temp.,
PDIP package, 10 MHz,
normal VDD limits
Device
PIC12CE673
PIC12CE674
PIC12LCE673
PIC12LCE674
Please contact your local sales office for exact ordering procedures.
SALES AND SUPPORT
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
Your local Microchip sales office.
The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 113
PIC12CE67X
NOTES:
DS40181B-page 114
Preliminary
1998 Microchip Technology Inc.
PIC12CE67X
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS40181B-page 115
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
AMERICAS (continued)
Toronto
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Microchip Technology Inc.
5925 Airport Road, Suite 200
Microchip Technology Singapore Pte Ltd.
200 Middle Road
Chandler, AZ 85224-6199
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
ASIA/PACIFIC
Hong Kong
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Atlanta
Microchip Technology Inc.
Microchip Asia Pacific
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tung Hua North Road
Taipei, Taiwan, ROC
RM 3801B, Tower Two
Metroplaza
Tel: 770-640-0034 Fax: 770-640-0307
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
EUROPE
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
India
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
France
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Müchen, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Italy
Detroit
Microchip Technology Inc.
42705 Grand River, Suite 201
Novi, MI 48375-1727
Tel: 248-374-1888 Fax: 248-374-2874
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Los Angeles
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
7/7/98
Tel: 714-263-1888 Fax: 714-263-1338
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Organization (ISO).
All rights reserved. © 8/28/98, Microchip Technology Incorporated, USA. Friday, August 28, 1998
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40181B-page 116
1998 Microchip Technology Inc.
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