PIC12LF1612 [MICROCHIP]
HIGH-VOLTAGE ICSP PROGRAMMING;
| 型号： | PIC12LF1612 |
| 厂家： | 
MICROCHIP |
| 描述： | HIGH-VOLTAGE ICSP PROGRAMMING |
| 文件： | 总38页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC12(L)F1612/16(L)F161X
PIC12(L)F1612/16(L)F161X Memory Programming Specification
This document includes the programming specifications for the following devices:
• PIC12F1612 • PIC12LF1612
• PIC16F1613 • PIC16LF1613
• PIC16F1614 • PIC16LF1614
• PIC16F1615 • PIC16LF1615
• PIC16F1618 • PIC16LF1618
• PIC16F1619 • PIC16LF1619
1.0
OVERVIEW
The devices can be programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the
low-voltage ICSP™ method.
1.1
Hardware Requirements
1.1.1
HIGH-VOLTAGE ICSP PROGRAMMING
In High-Voltage ICSP™ mode, these devices require two programmable power supplies: one for VDD and one for the
MCLR/VPP pin.
1.1.2
LOW-VOLTAGE ICSP PROGRAMMING
In Low-Voltage ICSP™ mode, these devices can be programmed using a single VDD source in the operating range. The
MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage.
1.1.2.1
Single-Supply ICSP Programming
The LVP bit in Configuration Word 2 enables single-supply (low-voltage) ICSP programming. The LVP bit defaults to a
‘1’ (enabled) from the factory. The LVP bit may only be programmed to ‘0’ by entering the High-Voltage ICSP mode,
where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode
is available and only the High-Voltage ICSP mode can be used to program the device.
Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH
to the MCLR/VPP pin.
2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port
pin can no longer be used as a general purpose input.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 1
PIC12(L)F1612/16(L)F161X
1.2
Pin Utilization
Five pins are needed for ICSP™ programming. The pins are listed in Table 1-1.
TABLE 1-1:
Pin Name
PIN DESCRIPTIONS DURING PROGRAMMING
During Programming
Pin Type
Function
Pin Description
ICSPCLK
ICSPDAT
ICSPCLK
ICSPDAT
I
Clock Input – Schmitt Trigger Input
I/O
Data Input/Output – Schmitt Trigger Input
MCLR/VPP
VDD
Program/Verify mode
P(1)
P
Program Mode Select/Programming Power Supply
VDD
VSS
Power Supply
Ground
VSS
P
Legend: I = Input, O = Output, P = Power
Note 1: The programming high voltage is internally generated. To activate the Program/Verify mode, high voltage
needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any
significant current.
DS40001720C-page 2
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
2.0
DEVICE PINOUTS
The pin diagrams are shown in Figure 2-1 through Figure 2-6. The pins that are required for programming are listed in
Table 1-1 and shown in bold lettering in the pin diagrams.
FIGURE 2-1:
8-PIN PDIP, SOIC, DFN, UDFN
VDD
RA5
1
2
VSS
8
7
6
5
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA4
3
4
MCLR/VPP/RA3
FIGURE 2-2:
14-PIN PDIP, SOIC, TSSOP
VDD
RA5
1
VSS
14
RA0/ICSPDAT
13
12
11
10
9
2
3
4
RA4
RA1/ICSPCLK
MCLR/VPP/RA3
RA2
RC5
RC4
RC3
RC0
5
6
7
RC1
RC2
8
FIGURE 2-3:
16-PIN QFN, UQFN
16 1514 13
RA5
1
12 RA0/ICSPDAT
11 RA1/ICSPCLK
RA4
MCLR/VPP/RA3
RC5
2
3
4
10
9
RA2
RC0
5 6 7
8
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 3
PIC12(L)F1612/16(L)F161X
FIGURE 2-4:
16-PIN QFN
16 15 14 13
1
12
RA5
RA4
MCLR/VPP/RA3
RA0/ICSPDAT
RA1/ICSPCLK
RA2
2
3
4
11
10
9
RC5
RC0
5
6
7
8
FIGURE 2-5:
20-PIN PDIP, SOIC, SSOP
VDD
RA5
RA4
1
VSS
20
19
18
17
16
15
14
13
12
11
RA0/ICSPDAT
RA1/ICSPCLK
RA2
2
3
4
MCLR/VPP/RA3
RC5
RC4
RC3
RC6
RC7
RB7
RC0
5
RC1
6
RC2
7
RB4
8
RB5
9
RB6
10
DS40001720C-page 4
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
FIGURE 2-6:
20-PIN QFN
20 19 18 17 16
MCLR/VPP/RA3
1
2
3
4
5
15
14
13
12
RA1/ICSPCLK
RA2
RC0
RC5
RC4
RC3
RC6
RC1
11 RC2
6
7 8 9 10
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 5
PIC12(L)F1612/16(L)F161X
3.0
MEMORY MAP
The memory is broken into two sections: program memory and configuration memory.
FIGURE 3-1:
PIC12(L)F1612/16(L)F1613 PROGRAM MEMORY MAPPING
2 KW
0000h
Implemented
07FFh
Maps to
0-07FFh
Program Memory
User ID Location
8000h
User ID Location
8001h
7FFF
h
h
User ID Location
User ID Location
Reserved
8002h
8003h
8000
Implemented
81FF
h
8004h
8005h
8006h
Mask/Rev ID
Maps to
8000-81FFh
Configuration Memory
Device ID
Configuration Word 1
Configuration Word 2
Configuration Word 3
Calibration Word 1
Calibration Word 2
Calibration Word 3
Reserved
8007h
8008h
8009h
800Ah
FFFF
h
800Bh
800Ch
800Dh-81FFh
DS40001720C-page 6
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
FIGURE 3-2:
PIC16(L)F1614/8 PROGRAM MEMORY MAPPING
4 KW
0000h
0FFFh
Implemented
Maps to
0-0FFFh
Program Memory
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
8000h
8001h
7FFF
h
8002h
8003h
8000
h
Implemented
81FF
h
8004h
8005h
8006h
Mask/Rev ID
Maps to
8000-81FFh
Configuration Memory
Device ID
Configuration Word 1
Configuration Word 2
Configuration Word 3
Calibration Word 1
Calibration Word 2
Calibration Word 3
Reserved
8007h
8008h
8009h
800Ah
FFFF
h
800Bh
800Ch
800Dh-81FFh
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 7
PIC12(L)F1612/16(L)F161X
FIGURE 3-3:
PIC16(L)F1615/9 PROGRAM MEMORY MAPPING
8 KW
0000h
Implemented
1FFFh
Maps to
0-1FFFh
Program Memory
User ID Location
User ID Location
User ID Location
User ID Location
Reserved
8000h
8001h
7FFF
h
8002h
8003h
8000
h
Implemented
81FF
h
8004h
8005h
8006h
Mask/Rev ID
Maps to
8000-81FFh
Configuration Memory
Device ID
Configuration Word 1
Configuration Word 2
Configuration Word 3
Calibration Word 1
Calibration Word 2
Calibration Word 3
Reserved
8007h
8008h
8009h
800Ah
FFFF
h
800Bh
800Ch
800Dh-81FFh
DS40001720C-page 8
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
3.1
User ID Location
A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to
8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location
may be read with code protection enabled or disabled.
Note:
MPLAB® IDE only displays the seven Least Significant bits (LSb) of each user ID location, the upper bits
are not read. It is recommended that only the seven LSbs be used if MPLAB® IDE is the primary tool used
to read these addresses.
3.2
Revision ID
The revision ID word is located at 8005h. This location is read-only and cannot be erased or modified.
REGISTER 3-1:
REVISION ID: REVISION ID REGISTER(1)
R
R
R
R
R
R
1
0
MJRREV5
MJRREV4
MJRREV3
MJRREV2
bit 13
bit 8
R
MJRREV1
bit 7
R
R
R
R
R
R
R
MJRREV0
MNREV5
MNREV4
MNREV3
MNREV2
MNREV1
MNREV0
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’ x = Bit is unknown
bit 13
Reserved: Read as ‘1’
bit 12
Reserved: Read as ‘0’
bit 11-6
bit 5-0
MJRREV<5:0>: Major Revision ID bits
MNREV<5:0>: Minor Revision ID bits
Note 1: This location cannot be written.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 9
PIC12(L)F1612/16(L)F161X
3.3
Device ID
The device ID word is located at 8006h. This location is read-only and cannot be erased or modified.
REGISTER 3-2:
DEVICE ID: DEVICE ID REGISTER(1)
R
R
R
R
R
R
1
1
DEV11
DEV10
DEV9
DEV8
bit 13
bit 8
R
DEV7
bit 7
R
R
R
R
R
R
R
DEV6
DEV5
DEV4
DEV3
DEV2
DEV1
DEV0
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
U = Unimplemented bit,
read as ‘0’
x = Bit is unknown
bit 13
Reserved: Read as ‘1’
Reserved: Read as ‘1’
DEV<11:0>: Device ID bits
bit 12
bit 11-0
These bits are used to identify the part number.
Note 1: This location cannot be written.
TABLE 3-1:
DEVICE ID VALUES
DEVICE ID VALUES
DEVICE
DEV
REV
PIC12F1612
PIC12LF1612
PIC16F1613
PIC16LF1613
PIC16F1614
PIC16LF1614
PIC16F1615
PIC16LF1615
PIC16F1618
PIC16LF1618
PIC16F1619
PIC16LF1619
11 0000 0101 1000
11 0000 0101 1001
11 0000 0100 1100
11 0000 0100 1101
11 0000 0111 1000
11 0000 0111 1010
11 0000 0111 1100
11 0000 0111 1110
11 0000 0111 1001
11 0000 0111 1011
11 0000 0111 1101
11 0000 0111 1111
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
10 xxxx xxxx xxxx
3.4
Configuration Words
There are three Configuration Words, Configuration Word 1 (8007h), Configuration Word 2 (8008h) and Configuration
Word 3 (8009h). The individual bits within these Configuration Words are used to enable or disable device functions such
as the Brown-out Reset, code protection and Power-up Timer.
DS40001720C-page 10
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
3.5
Calibration Words
The internal calibration values are factory calibrated and stored in Calibration Words 1, 2 and 3 (800Ah, 800Bh and
800Ch).
The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration
Words.
REGISTER 3-3:
CONFIGURATION WORD 1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
U-1
(4)
(4)
(1)
(1)
(3)
FCMEN
IESO
CLKOUTEN
BOREN1
BOREN0
—
bit 13
bit 8
R/P-1
R/P-1
R/P-1
U-1
—
U-1
—
R/P-1
R/P-1
R/P-1
(2)
(5)
CP
MCLRE
PWRTE
FOSC2
FOSC1
FOSC0
bit 7
bit 0
Legend:
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
P = Programmable Bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit
(4)
bit 13
bit 12
bit 11
FCMEN: Fail-Safe Clock Monitor Enable bit
1= ON - Fail-Safe Clock Monitor is enabled
0= OFF - Fail-Safe Clock Monitor is disabled
(4)
IESO: Internal External Switchover bit
1= ON
- Internal/External Switchover (Two-Speed Start-up) mode is enabled
0= OFF - Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
1 = OFF - CLKOUT function is disabled. I/O or oscillator function on CLKOUT pin.
0 = ON - CLKOUT function is enabled on CLKOUT pin
(1)
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11 = ON
- Brown-out Reset enabled
10 = SLEEP
- Brown-out Reset enabled during operation and disabled in Sleep
01 = SBODEN - Brown-out Reset controlled by SBOREN bit of the PCON register
00 = OFF
- Brown-out Reset disabled
(3)
bit 8
bit 7
Unimplemented: Read as ‘1’
(2)
CP: Code Protection bit
1 = OFF - Program memory code protection is disabled
0 = ON - Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1 (ON):
This bit is ignored.
If LVP bit = 0 (OFF):
1 = ON - MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = OFF - MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA
register.
(1)
bit 5
PWRTE: Power-up Timer Enable bit
1 = OFF - PWRT disabled
0 = ON - PWRT enabled
bit 4-3
Unimplemented: Read as ‘1’
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: This bit should be maintained as ‘1’ when programmed.
4: These bits are only implemented on the PIC16(L)F1615/9. They act as Unimplemented: Read as ‘1’ on all other parts
in the family.
5: This bit is forced to ‘1’ on the PIC12(L)F1612 and PIC16(L)F1613/4/8.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 11
PIC12(L)F1612/16(L)F161X
REGISTER 3-3:
CONFIGURATION WORD 1 (CONTINUED)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111
110
101
100
011
010
001
000
= ECH
= ECM
= ECL
- External Clock, High-Power mode: on CLKIN pin
- External Clock, Medium-Power mode: on CLKIN pin
- External Clock, Low-Power mode: on CLKIN pin
= INTOSC - I/O function on OSC1 pin
= Reserved
= HS
= Reserved
= Reserved
- HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins
Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.
2: The entire program memory will be erased when the code protection is turned off.
3: This bit should be maintained as ‘1’ when programmed.
4: These bits are only implemented on the PIC16(L)F1615/9. They act as Unimplemented: Read as ‘1’ on all other parts
in the family.
5: This bit is forced to ‘1’ on the PIC12(L)F1612 and PIC16(L)F1613/4/8.
REGISTER 3-4:
CONFIGURATION WORD 2
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
(1)
(2)
LVP
DEBUG
LPBOR
BORV
STVREN
PLLEN
bit 13
bit 8
R/P-1
ZCD
U-1
—
U-1
—
U-1
—
U-1
—
R/P-1
R/P-1
R/P-1
(3)
PPS1WAY
WRT1
WRT0
bit 7
bit 0
Legend:
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
R = Readable bit
-n = Value at POR
U = Unimplemented bit
P = Programmable Bit
(1)
bit 13
bit 12
bit 11
bit 10
bit 9
LVP: Low-Voltage Programming Enable bit
1 = ON - Low-voltage programming enabled
0 = OFF - High voltage on MCLR/VPP must be used for programming
(2)
DEBUG: Debugger mode
1 = OFF - In-circuit debugger is disabled
0 = ON
- In-circuit debugger is enabled
LPBOR: Low-Power BOR bit
1 = OFF - Low-Power BOR is disabled
0 = ON
- Low-Power BOR is enabled
BORV: Brown-out Reset Voltage Selection bit
1 = LOW - Brown-out Reset Voltage (VBOR) set to 1.9V on LF devices, and 2.45V on F devices
0 = HIGH - Brown-out Reset Voltage (VBOR) set to 2.7V
STVREN: Stack Overflow/Underflow Reset Enable bit
1 = ON
- Stack Overflow or Underflow will cause a Reset
0 = OFF - Stack Overflow or Underflow will not cause a Reset
bit 8
PLLEN: PLL Enable bit
1 = ON
- 4x PLL will be enabled for external clock, if FOSC = EC, or for INTOSC, if IRCF = 8 MHz or 16 MHz
0 = OFF - 4x PLL disabled
bit 7
ZCD: ZCD Disable bit
1 = OFF - ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0 = ON
- ZCD always enabled
bit 6-3
Unimplemented: Read as ‘1’
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
®
2: The Debug mode is controlled by the MPLAB IDE.
3: This bit is only implemented on the PIC16(L)F1614/5/8/9. It acts as Unimplemented: Read as '1' on all other parts in
the family.
DS40001720C-page 12
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
REGISTER 3-4:
CONFIGURATION WORD 2 (CONTINUED)
bit 2
(3)
PPS1WAY: PPSLOCK bit, One-Way Set Enable bit
1 = ON - The PPSLOCK bit is permanently set after the first access sequence that sets it.
0 = OFF - The PPSLOCK bit can be set and cleared as needed by the PPSLOCK access sequence.
bit 1-0
WRT<1:0>: Flash Memory Self-Write Protection bits
2 kW Flash memory (PIC12(L)F1612/16(L)F1613):
11 = OFF
- Write protection off
10 = BOOT - 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control
01 = HALF - 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control
00 = ALL
4 kW Flash memory (PIC16(L)F1614/8):
11 = OFF - Write protection off
- 000h to 7FFh write-protected, no addresses may be modified by PMCON control
10 = BOOT - 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control
01 = HALF - 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control
00 = ALL
8 kW Flash memory (PIC16(L)F1615/9):
11 = OFF - Write protection off
- 000h to FFFh write-protected, no addresses may be modified by PMCON control
10 = BOOT - 0000h to 01FFh write-protected, 0200h to 1FFF may be modified by PMCON control
01 = HALF - 0000h to 0FFFh write-protected, 1000h to 1FFF may be modified by PMCON control
00 = ALL
- 0000h to 1FFFh write-protected, no addresses may be modified by PMCON control
Note 1: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP.
®
2: The Debug mode is controlled by the MPLAB IDE.
3: This bit is only implemented on the PIC16(L)F1614/5/8/9. It acts as Unimplemented: Read as '1' on all other parts in
the family.
REGISTER 3-5:
CONFIGURATION WORD 3
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTCCS2
WDTCCS1
WDTCCS0
WDTCWS2
WDTCWS1
WDTCWS0
bit 13
bit 8
U-1
—
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
WDTE1
WDTE1
WDTCPS4
WDTCPS3
WDTCPS2
WDTCPS1
WDTCPS0
bit 7
bit 0
Legend:
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
P = Programmable Bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit
bit 13-11
WDTCCS<2:0>: WDT Input Clock Selector bit:
000= WDT reference clock is the 31.0 kHz LFINTOSC (default value)
001= WDT reference clock is the 31.25 kHz MFINTOSC output
010= Reserved
...
110= Reserved
111= SWC - Software Control, controlled by WDTCS bits
bit 10-8
WDTCWS<2:0>: WDT Window Select bits:
000= WDTCWS125 - 12.5% window open time (87.5% delay time)
001= WDTCWS25
010= WDTCWS375 - 37.5% window open time (62.5% delay time)
011= WDTCWS50 - 50% window open time (50% delay time)
100= WDTCWS625 - 62.5% window open time (37.5% delay time)
101= WDTCWS75 - 75% window open time (25% delay time)
110= WDTCWS100 - 100% window open time (Legacy WDT)
- 25% window open time (75% delay time)
111= WDTCWSSW
- Software WDT window size control (controlled by WDTWS)
bit 7
Unimplemented: Read as ‘1’
Note 1: Typical time-out based on 31 kHz clock.
2: Software-controlled (WDTPS).
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 13
PIC12(L)F1612/16(L)F161X
REGISTER 3-5:
CONFIGURATION WORD 3 (CONTINUED)
bit 6-5
WDTE<1:0>: WDT Operating mode:
00= OFF
- WDT disabled, SWDTEN is ignored
01= SWDTEN
10= NSLEEP
11= ON
- WDT enabled/disabled by SWDTEN bit in WDTCON0
- WDT enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN ignored
- WDT enabled regardless of Sleep; SWDTEN is ignored
bit 4-0
WDTCPS<4:0>: WDT Period Select bits:
00000= WDTCPS0 - 1:32 (1 ms period)
00001= WDTCPS1 - 1:64 (2 ms period)
(1)
(1)
(1)
00010= WDTCPS2
- 1:128 (4 ms period)
(1)
(1)
00011= WDTCPS3 - 1:256 (8 ms period)
00100= WDTCPS4 - 1:512 (16 ms period)
00101= WDTCPS5 - 1:1024 (32 ms period)
00110= WDTCPS6 - 1:2048 (64 ms period)
(1)
(1)
(1)
00111= WDTCPS7
- 1:4096 (128 ms period)
(1)
01000= WDTCPS8 - 1:8192 (256 ms period)
01001= WDTCPS9 - 1:16384 (512 ms period)
01010= WDTCPSA - 1:32768 (1s period)
01011= WDTCPSB - 1:65536 (2s period)
01100= WDTCPSC - 1:131072 (4s period)
01101= WDTCPSD - 1:262144 (8s period)
(1)
(1)
(1)
(1)
(1)
(1)
01110= WDTCPSE - 1:524299 (16s period)
(1)
01111= WDTCPSF - 1:1048576 (32s period)
10000= WDTCPS10 - 1:2097152 (64s period)
10001= WDTCPS11 - 1:4194304 (128s period)
10010= WDTCPS12 - 1:8388608 (256s period)
10011= Reserved
(1)
(1)
(1)
...
11110= Reserved
11111= WDTCPS1F - 1:65536 (2s period)
(1), (2)
Note 1: Typical time-out based on 31 kHz clock.
2: Software-controlled (WDTPS).
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Preliminary
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PIC12(L)F1612/16(L)F161X
4.0
PROGRAM/VERIFY MODE
In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in
serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data
words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and is latched on the falling edge.
In Program/Verify mode both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the
device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all
I/Os are automatically configured as high-impedance inputs and the address is cleared.
4.1
High-Voltage Program/Verify Mode Entry and Exit
There are two different methods of entering Program/Verify mode via high voltage:
• VPP – First entry mode
• VDD – First entry mode
4.1.1
VPP – FIRST ENTRY MODE
To enter Program/Verify mode via the VPP-first method the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered.
2. Raise the voltage on MCLR from 0V to VIHH.
3. Raise the voltage on VDD from 0V to the desired operating voltage.
The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, the
device will execute code when Configuration Word 1 has MCLR disabled (MCLRE = 0), the Power-up Timer is disabled
(PWRTE = 0), the internal oscillator is selected (FOSC = 100), and ICSPCLK and ICSPDAT pins are driven by the user
application. Since this may prevent entry, VPP-first entry mode is strongly recommended. See the timing diagram in
Figure 8-2.
4.1.2
VDD – FIRST ENTRY MODE
To enter Program/Verify mode via the VDD-first method the following sequence must be followed:
1. Hold ICSPCLK and ICSPDAT low.
2. Raise the voltage on VDD from 0V to the desired operating voltage.
3. Raise the voltage on MCLR from VDD or below to VIHH.
The VDD-first method is useful when programming the device when VDD is already applied, for it is not necessary to
disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-1.
4.1.3
PROGRAM/VERIFY MODE EXIT
To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figure 8-3 and Figure 8-4.
Note:
In systems where the VDD and MCLR/VPP signals can be controlled independently, the VPP-last method
of exit should be used to keep the device in Reset, thereby preventing any issues that may be caused by
program execution.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 15
PIC12(L)F1612/16(L)F161X
4.2
Low-Voltage Programming (LVP) Mode
The Low-Voltage Programming mode allows devices to be programmed using VDD only, without high voltage. When the
LVP bit of Configuration Word 2 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry
mode.
Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps:
1. MCLR is brought to VIL.
2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.
The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily
remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least
Significant bit of the Least Significant nibble must be shifted in first.
Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained.
For low-voltage programming timing, see Figure 8-8 and Figure 8-9.
Exiting Program/Verify mode is done by no longer driving MCLR to VIL. See Figure 8-8 and Figure 8-9.
Note:
To enter LVP mode, the LSB of the Least Significant nibble must be shifted in first. This differs from entering
the key sequence on other parts.
DS40001720C-page 16
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PIC12(L)F1612/16(L)F161X
4.3
Program/Verify Commands
The devices implement ten programming commands; each six bits in length. The commands are summarized in Table 4-1.
Commands that have data associated with them are specified to have a minimum delay of TDLY between the command
and the data. After this delay 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is
for the Start bit and the last clock is for the Stop bit.
TABLE 4-1:
COMMAND MAPPING
Command
Mapping
Data/Note
Binary (MSb … LSb)
Hex
Load Configuration
x
x
x
x
x
0
0
0
0
1
0
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
00h 0, data (14), 0
02h 0, data (14), 0
04h 0, data (14), 0
Load Data For Program Memory
Read Data From Program Memory
Increment Address
06h
16h
08h
18h
0Ah
09h
11h
—
Reset Address
—
Begin Internally Timed Programming x
Begin Externally Timed Programming x
—
—
End Externally Timed Programming
Bulk Erase Program Memory
Row Erase Program Memory
x
x
x
—
Internally Timed
Internally Timed
4.3.1
LOAD CONFIGURATION
The Load Configuration command is used to access the configuration memory (user ID locations, Configuration Words,
Calibration Words). The Load Configuration command sets the address to 8000h and loads the data latches with one
word of data (see Figure 4-1).
After issuing the Load Configuration command, use the Increment Address command until the proper address to be
programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or
Begin Externally Timed Programming command.
Note:
Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write
to the Configuration or Calibration Word will have no effect on the targeted word.
The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address
command after the configuration memory has been accessed by the Load Configuration command.
FIGURE 4-1:
LOAD CONFIGURATION
1
2
3
4
5
2
16
6
1
15
TDLY
ICSPCLK
ICSPDAT
0
0
0
0
LSb
MSb 0
0
0
X
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Preliminary
DS40001720C-page 17
PIC12(L)F1612/16(L)F161X
4.3.2
LOAD DATA FOR PROGRAM MEMORY
The Load Data for Program Memory command is used to load one 14-bit word into the
data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin
Externally Timed Programming command is issued (see Figure 4-2).
FIGURE 4-2:
LOAD DATA FOR PROGRAM MEMORY
1
2
3
4
5
16
6
1
2
15
TDLY
ICSPCLK
0
1
0
0
X
0
LSb
MSb
0
0
ICSPDAT
4.3.3
READ DATA FROM PROGRAM MEMORY
The Read Data from Program Memory command will transmit data bits out of the program memory map currently
accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first
falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program
memory is code-protected (CP), the data will be read as zeros (see Figure 4-3).
FIGURE 4-3:
READ DATA FROM PROGRAM MEMORY
1
2
3
4
5
6
1
2
15
16
TDLY
ICSPCLK
ICSPDAT
0
0
1
0
0
X
(from Programmer)
ICSPDAT
LSb
MSb
x
(from device)
Input
Output
Input
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PIC12(L)F1612/16(L)F161X
4.3.4
INCREMENT ADDRESS
The address is incremented when this command is received. It is not possible to decrement the address. To reset this
counter, the user must use the Reset Address command or exit Program/Verify mode and re-enter it. If the address is
incremented from address 07FFh, it will wrap-around to location 0000h. If the address is incremented from FFFFh, it
will wrap-around to location 8000h.
FIGURE 4-4:
INCREMENT ADDRESS
Next Command
1
2
3
4
5
2
6
1
3
TDLY
ICSPCLK
0
1
1
0
X
0
X
X
X
ICSPDAT
Address
Address + 1
4.3.5
RESET ADDRESS
The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in
program memory or the configuration memory.
FIGURE 4-5:
RESET ADDRESS
Next Command
1
2
3
4
5
2
6
1
3
TDLY
ICSPCLK
0
1
1
0
1
X
X
X
X
ICSPDAT
Address
0000h
N
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Preliminary
DS40001720C-page 19
PIC12(L)F1612/16(L)F161X
4.3.6
BEGIN INTERNALLY TIMED PROGRAMMING
A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming
command. Programming of the addressed memory will begin after this command is received. An internal timing
mechanism executes the write. The user must allow for the program cycle time, TPINT, for the programming to complete.
The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used
to start the programming.
The program memory address that is being programmed is not erased prior to being programmed.
FIGURE 4-6:
BEGIN INTERNALLY TIMED PROGRAMMING
Next Command
1
2
3
4
5
6
1
2
3
TPINT
ICSPCLK
0
0
0
1
0
X
X
X
X
ICSPDAT
4.3.7
BEGIN EXTERNALLY TIMED PROGRAMMING
A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming
command. Programming of the addressed memory will begin after this command is received. To complete the
programming the End Externally Timed Programming command must be sent in the specified time window defined by
TPEXT (see Figure 4-7).
Externally timed writes are not supported for Configuration and Calibration bits. Any externally timed write to the
Configuration or Calibration Word will have no effect on the targeted word.
FIGURE 4-7:
BEGIN EXTERNALLY TIMED PROGRAMMING
End Externally Timed Programming
Command
1
2
3
4
5
6
1
2
3
TPEXT
ICSPCLK
0
0
0
0
1
X
1
1
0
ICSPDAT
DS40001720C-page 20
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
4.3.8
END EXTERNALLY TIMED PROGRAMMING
This command is required after a Begin Externally Timed Programming command is given. This command must be sent
within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent.
After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending
the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 4-8).
FIGURE 4-8:
END EXTERNALLY TIMED PROGRAMMING
Next Command
1
2
3
4
5
2
6
1
3
TDIS
ICSPCLK
ICSPDAT
1
0
0
X
1
1
X
X
X
4.3.9
BULK ERASE PROGRAM MEMORY
The Bulk Erase Program Memory command performs two different functions dependent on the current state of the
address.
Address 0000h-07FFh:
Program Memory is erased
Configuration Words are erased
Address 8000h-8009h:
Program Memory is erased
Configuration Words are erased
User ID Locations are erased
A Bulk Erase Program Memory command should not be issued when the address is greater than 8009h.
After receiving the Bulk Erase Program Memory command the erase will not complete until the time interval, TERAB, has
expired.
Note:
The code protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command.
BULK ERASE PROGRAM MEMORY
FIGURE 4-9:
Next Command
1
2
3
4
5
6
1
2
3
TERAB
ICSPCLK
ICSPDAT
0
1
0
1
0
X
X
X
X
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DS40001720C-page 21
PIC12(L)F1612/16(L)F161X
4.3.10
ROW ERASE PROGRAM MEMORY
The Row Erase Program Memory command will erase an individual row. Refer to Table 4-2 for row sizes of specific
devices and the PC bits used to address them. If the program memory is code-protected, the Row Erase Program
Memory command will be ignored. When the address is 8000h-8009h, the Row Erase Program Memory command will
only erase the user ID locations, regardless of the setting of the CP Configuration bit.
After receiving the Row Erase Program Memory command, the erase will not complete until the time interval, TERAR,
has expired.
TABLE 4-2:
PROGRAMMING ROW SIZE AND LATCHES
Devices
PC
Row Size
Number of Latches
PIC12(L)F1612
PIC16(L)F1613
PIC16(L)F1614
PIC16(L)F1615
PIC16(L)F1618
PIC16(L)F1619
<15:5>
<15:5>
<15:5>
<15:5>
<15:5>
<15:5>
16
16
32
32
32
32
16
16
32
32
32
32
FIGURE 4-10:
ROW ERASE PROGRAM MEMORY
Next Command
1
2
3
4
5
6
1
2
3
TERAR
ICSPCLK
ICSPDAT
0
1
0
0
1
X
X
X
X
DS40001720C-page 22
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2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
5.0
PROGRAMMING ALGORITHMS
The devices use internal latches to temporarily store the 14-bit words used for programming. Refer to Table 4-2 for
specific latch information. The data latches allow the user to write the program words with a single Begin Externally
Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load
Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally
Timed Programming or Begin Internally Timed Programming command is given.
The data latches are aligned with the LSbs of the address. The PC’s address at the time the Begin Externally Timed
Programming or Begin Internally Timed Programming command is given will determine which location(s) in memory are
written.
If more than the maximum number of data latches are written without a Begin Externally Timed Programming or Begin
Internally Timed Programming command, the data in the data latches will be overwritten. The following figures show the
recommended flowcharts for programming.
FIGURE 5-1:
DEVICE PROGRAM/VERIFY FLOWCHART
Start
Enter
Programming Mode
Bulk Erase
Device
Write Program
(1)
Memory
Write User IDs
Verify Program
Memory
Verify User IDs
Write Configuration
(2)
Words
Verify Configuration
Words
Exit Programming
Mode
Done
Note 1: See Figure 5-2.
2: See Figure 5-5.
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PIC12(L)F1612/16(L)F161X
FIGURE 5-2:
PROGRAM MEMORY FLOWCHART
Start
Bulk Erase
Program
(1, 2)
Memory
(3)
Program Cycle
Read Data
from
Program Memory
Report
No
Programming
Data Correct?
Failure
Yes
Increment
No
All Locations
Done?
Address
Command
Yes
Done
Note 1: This step is optional if the device has already been erased or has not been previously programmed.
2: If the device is code-protected or must be completely erased, then Bulk Erase the device per Figure 5-6.
3: See Figure 5-3 or Figure 5-4.
DS40001720C-page 24
Preliminary
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PIC12(L)F1612/16(L)F161X
FIGURE 5-3:
ONE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Program Memory
Begin
Begin
Programming
Command
(Internally timed)
Programming
Command
(Externally timed)(1)
Wait TPEXT
Wait TPINT
End
Programming
Command
Wait TDIS
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2013-2014 Microchip Technology Inc.
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DS40001720C-page 25
PIC12(L)F1612/16(L)F161X
FIGURE 5-4:
MULTIPLE-WORD PROGRAM CYCLE
Program Cycle
Load Data
for
Latch 1
Program Memory
Increment
Address
Command
Load Data
for
Latch 2
Program Memory
Increment
Address
Command
Load Data
for
Latch n
Program Memory
Begin
Begin
Programming
Programming
Command
Command
(Internally timed)
(Externally timed)
Wait TPEXT
Wait TPINT
End
Programming
Command
Wait TDIS
DS40001720C-page 26
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PIC12(L)F1612/16(L)F161X
FIGURE 5-5:
CONFIGURATION MEMORY PROGRAM FLOWCHART
Start
Load
Configuration
Bulk Erase
Program
Memory(1)
One-word
Program Cycle(2)
(User ID)
Read Data
From Program
Memory Command
Report
Programming
Failure
No
Data Correct?
Yes
Increment
Address
Command
Increment
Address
Command
No
Yes
Address =
8004h?
Increment
Address
Command
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 1)
Read Data
From Program
Memory Command
Report
Programming
Failure
No
Data Correct?
Yes
Increment
Address
Command
One-word
Program Cycle(2)
(Config. Word 2)
Report
Programming
Failure
Read Data
From Program
Memory Command
No
Data Correct?
Yes
Done
Note 1: This step is optional if the device is erased or not previously programmed.
2: See Figure 5-3.
2013-2014 Microchip Technology Inc.
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PIC12(L)F1612/16(L)F161X
FIGURE 5-6:
ERASE FLOWCHART
Start
Load Configuration
Bulk Erase
Program Memory
Done
Note:
This sequence does not erase the Calibration Words.
DS40001720C-page 28
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PIC12(L)F1612/16(L)F161X
6.0
CODE PROTECTION
Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program
memory locations (0000h-07FFh) read as ‘0’. Further programming is disabled for the program memory (0000h-07FFh).
The user ID locations and Configuration Words can be programmed and read out regardless of the code protection
settings.
6.1
Program Memory
Code protection is enabled by programming the CP bit in Configuration Word 1 register to ‘0’.
The only way to disable code protection is to use the Bulk Erase Program Memory command.
7.0
HEX FILE USAGE
In the hex file there are two bytes per program word stored in the Intel® INHX32 hex format. Data is stored LSB first,
MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program
memory. (Example: Configuration Word 1 is stored at 8007h. In the hex file this will be referenced as 1000Eh-1000Fh).
7.1
Configuration Word
To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words
and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple
warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should
be included.
7.2
Device ID
If a device ID is present in the hex file at 1000Ch-1000Dh (8006h on the part), the programmer should verify the device
ID against the value read from the part. On a mismatch condition the programmer should generate a warning message.
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PIC12(L)F1612/16(L)F161X
7.3
Checksum Computation
The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit.
TABLE 7-1:
CONFIGURATION WORD MASK VALUES
Part Variant
Config. Word 1 Mask
Config. Word 2 Mask
Config. Word 3 Mask
PIC12(L)F1612/16(L)F1613
PIC16(L)F1614/8
0EE3h
0EE3h
3EE3h
3F83h
3F87h
3F87h
3F7Fh
3F7Fh
3F7Fh
PIC16(L)F1615/9
7.3.1
PROGRAM CODE PROTECTION DISABLED
With the program code protection disabled, the checksum is computed by reading the contents of the program memory
locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable
location. Any Carry bit exceeding 16 bits are ignored. Additionally, the relevant bits of the Configuration Words are added
to the checksum. All unimplemented Configuration bits are masked to ‘0’.
7.3.2
PROGRAM CODE PROTECTION ENABLED
When the MPLAB® IDE check box for DashboardProject PropertiesConf:BuildingInsert Checksum in User ID
Memory is checked, then the 16-bit checksum of the equivalent unprotected device is computed and stored in the user
ID. Each nibble of the unprotected checksum is stored in the Least Significant nibble of each of the four user ID
locations. The Most Significant checksum nibble is stored in the user ID at location 8000h, the second Most Significant
nibble is stored at location 8001h, and so forth for the remaining nibbles and ID locations. The protected checksums in
Table 7-2 assume that the Insert Checksum in User ID Memory box is checked.
The checksum of a code-protected device is computed in the following manner: the Least Significant nibble of each user
ID is used to create a 16-bit value. The Least Significant nibble of user ID location 8000h is the Most Significant nibble
of the 16-bit value. The Least Significant nibble of user ID location 8001h is the second Most Significant nibble, and so
forth for the remaining user IDs and 16-bit value nibbles. The resulting 16-bit value is summed with the Configuration
Words. All unimplemented Configuration bits are masked to ‘0’.
TABLE 7-2:
CHECKSUMS
Config1
Config2
Config3
Checksum
Unprotected
Code-protected
Device
00AAh
First
00AAh
First
Unprotected Protected Mask Word Mask Word Mask
Blank
Blank
and Last
and Last
PIC12F1612
PIC16F1613
PIC16F1614
PIC16F1615
PIC16F1618
PIC16F1619
PIC12LF1612
PIC16LF1613
PIC16LF1614
PIC16LF1615
PIC16LF1618
PIC16LF1619
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3FFFh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
3F7Fh
0EE3h 3FFFh 3F83h 3FFFh 3F7Fh 85E5h
0EE3h 3FFFh 3F83h 3FFFh 3F7Fh 85E5h
073Bh 134Ah 94A0h
073Bh 134Ah 94A0h
0EE3h 3FFFh 3F87h 3FFFh 3F7Fh 7DE9h FF3Fh 0B4Eh 8CA4h
3EE7h 3FFFh 3F87h 3FFFh 3F7Fh 9DEDh 1F43h 5B56h DCACh
0EE3h 3FFFh 3F87h 3FFFh 3F7Fh 7DE9h FF3Fh 0B4Eh 8CA4h
3EE7h 3FFFh 3F87h 3FFFh 3F7Fh 9DEDh 1F43h 5B56h DCACh
0EE3h 3FFFh 3F83h 3FFFh 3F7Fh 85E5h
0EE3h 3FFFh 3F83h 3FFFh 3F7Fh 85E5h
073Bh 134Ah 94A0h
073Bh 134Ah 94A0h
0EE3h 3FFFh 3F87h 3FFFh 3F7Fh 7DE9h FF3Fh 0B4Eh 8CA4h
3EE7h 3FFFh 3F87h 3FFFh 3F7Fh 9DEDh 1F43h 5B56h DCACh
0EE3h 3FFFh 3F87h 3FFFh 3F7Fh 7DE9h FF3Fh 0B4Eh 8CA4h
3EE7h 3FFFh 3F87h 3FFFh 3F7Fh 9DEDh 1F43h 5B56h DCACh
DS40001720C-page 30
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PIC12(L)F1612/16(L)F161X
8.0
ELECTRICAL SPECIFICATIONS
Refer to the device specific data sheet for absolute maximum ratings.
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units Conditions/Comments
Supply Voltages and Currents
VDD
VDD
Read/Write and Row Erase operations
Bulk Erase operations
Current on VDD, Idle
VDD min.
—
VDD max.
VDD max.
1.0
V
V
2.7
—
—
—
—
IDDI
mA
mA
IDDP
Current on VDD, Programming
VPP
—
3.0
IPP
Current on MCLR/VPP
—
—
—
600
9.0
A
High voltage on MCLR/VPP for
Program/Verify mode entry
VIHH
8.0
V
MCLR rise time (VIL to VIHH) for
Program/Verify mode entry
TVHHR
—
—
1.0
s
I/O pins
VIH
VIL
(ICSPCLK, ICSPDAT, MCLR/VPP) input high level
0.8 VDD
—
—
—
—
V
(ICSPCLK, ICSPDAT, MCLR/VPP) input low level
ICSPDAT output high level
0.2 VDD
V
VDD-0.7
VDD-0.7
VDD-0.7
IOH = 3.5 mA, VDD = 5V
IOH = 3 mA, VDD = 3.3V
IOH = 2 mA, VDD = 1.8V
VOH
VOL
—
—
—
V
V
ICSPDAT output low level
VSS+0.6
VSS+0.6
VSS+0.6
IOH = 8 mA, VDD = 5V
IOH = 6 mA, VDD = 3.3V
IOH = 3 mA, VDD = 1.8V
—
Programming Mode Entry and Exit
Programing mode entry setup time: ICSPCLK,
ICSPDAT setup time before VDD or MCLR
TENTS
TENTH
100
250
—
—
—
—
ns
Programing mode entry hold time: ICSPCLK,
ICSPDAT hold time after VDD or MCLR
s
Serial Program/Verify
TCKL
TCKH
TDS
Clock Low Pulse Width
100
100
100
100
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Clock High Pulse Width
Data in setup time before clock
Data in hold time after clock
TDH
Clock to data out valid (during a Read Data
command)
TCO
0
0
0
—
—
—
80
80
80
ns
ns
ns
Clock to data low-impedance (during a Read Data
command)
TLZD
THZD
Clock to data high-impedance (during a Read Data
command)
Data input not driven to next clock input (delay
required between command/data or command/
command)
TDLY
1.0
—
—
s
TERAB
TERAR
Bulk Erase cycle time
Row Erase cycle time
—
—
—
—
5
ms
ms
2.5
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 31
PIC12(L)F1612/16(L)F161X
TABLE 8-1:
AC/DC CHARACTERISTICS TIMING REQUIREMENTS FOR PROGRAM/VERIFY
MODE (CONTINUED)
Standard Operating Conditions
Production tested at 25°C
AC/DC CHARACTERISTICS
Sym.
Characteristics
Min.
Typ.
Max.
Units Conditions/Comments
Internally timed programming operation time
—
—
—
—
2.5
5
ms Program memory
ms Configuration Words
TPINT
TPEXT
TDIS
Externally timed programming pulse
1.0
300
1
—
—
—
2.1
ms Note 1
Time delay from program to compare
(HV discharge time)
—
s
s
TEXIT
Time delay when exiting Program/Verify mode
—
Note 1: Externally timed writes are not supported for Configuration and Calibration bits.
8.1
AC Timing Diagrams
FIGURE 8-1:
PROGRAMMING MODE ENTRY – VDD FIRST
TENTS
TENTH
VIHH
VIL
VPP
VDD
ICSPDAT
ICSPCLK
FIGURE 8-2:
PROGRAMMING MODE ENTRY – VPP FIRST
TENTS
TENTH
VIHH
VIL
VPP
VDD
ICSPDAT
ICSPCLK
DS40001720C-page 32
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
FIGURE 8-3:
PROGRAMMING MODE EXIT – VPP LAST
TEXIT
VIHH
VIL
VPP
VDD
ICSPDAT
ICSPCLK
FIGURE 8-4:
PROGRAMMING MODE EXIT – VDD LAST
TEXIT
VIHH
VPP
VIL
VDD
ICSPDAT
ICSPCLK
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 33
PIC12(L)F1612/16(L)F161X
FIGURE 8-5:
CLOCK AND DATA TIMING
TCKL
TCKH
ICSPCLK
TDH
TDS
ICSPDAT
as
input
TCO
ICSPDAT
as
output
TLZD
ICSPDAT
from input
to output
THZD
ICSPDAT
from output
to input
FIGURE 8-6:
WRITE COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
16
6
1
2
15
ICSPCLK
X
X
X
LSb
0
X
MSb 0
Next
X
X
ICSPDAT
Payload
Command
Command
FIGURE 8-7:
READ COMMAND-PAYLOAD TIMING
TDLY
1
2
3
4
5
16
6
1
2
15
ICSPCLK
ICSPDAT
X
X
X
X
X
X
(from Programmer)
LSb
MSb
0
x
ICSPDAT
(from Device)
Next
Command
Payload
Command
DS40001720C-page 34
Preliminary
2013-2014 Microchip Technology Inc.
PIC12(L)F1612/16(L)F161X
FIGURE 8-8:
LVP ENTRY (POWERED)
VDD
MCLR
TENTS
TENTH
33 clocks
TCKH
TCKL
ICSPCLK
ICSPDAT
TDH
TDS
LSb of Pattern
0
MSb of Pattern
31
1
2
FIGURE 8-9:
LVP ENTRY (POWERING UP)
VDD
MCLR
TENTH
33 Clocks
TCKH
TCKL
ICSPCLK
ICSPDAT
TDH
TDS
LSb of Pattern
0
MSb of Pattern
31
1
2
Note 1: Sequence matching can start with no edge on MCLR first.
2013-2014 Microchip Technology Inc.
Preliminary
DS40001720C-page 35
PIC12(L)F1612/16(L)F161X
APPENDIX A: REVISION HISTORY
Revision A (09/2013)
Initial release of this document.
Revision B (04/2014)
Added PIC16(L)F1614/5/8/9 to the device family;
Updated Figures 2-1 and 2-3; Added Figures 2-4
through 2-7, Figure 3-2 and Figure 3-3; Updated
Registers 3-3 and 3-4; Updated Tables 3-1 and 4-2;
Added Note to Section 4.1.3; Updated Section 7.3;
Other minor corrections.
Revision C (08/2014)
Updated part number in Figure 2-2 (14-Pin PDIP, SOIC,
TSSOP); Deleted Figure 2-4 (14-Pin PDIP, SOIC,
TSSOP); Added Note 3 to Register 3-4; Updated Note
5 in Register 3-3; Updated Tables 7-1 and 7-2; Other
minor corrections.
DS40001720C-page 36
Preliminary
2013-2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
32
OptoLyzer, PIC, PICSTART, PIC logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-538-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2013-2014 Microchip Technology Inc.
Preliminary
DS400001720C-page 37
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03/25/14
DS40001720C-page 38
Preliminary
2013-2014 Microchip Technology Inc.
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