PIC14000T-04E/SS_技术文档

PIC14000

28-Pin Programmable Mixed Signal Controller

FEATURES

PACKAGE TYPES

High-Performance RISC-like CPU core

PDIP, SOIC, SSOP, Windowed CERDIP

•

Based on PIC16C74 microcontroller

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 20 MHz clock input

• 4096 x 14 on-chip EPROM program memory

• 192 x 8 general purpose registers (SRAM)

• 6 internal and 5 external interrupt sources

• 38 special function hardware registers

• Eight-level hardware stack

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RA2/AN2

RA3/AN3

RD4/AN4

RD5/AN5

RD6/AN6

RD7/AN7

CDAC

• 1

2

RA1/AN1

RA0/AN0

3

RD3/LDACB

RD2/CMPB

RD1/SDAB

RD0/SCLB

OSC2/CLKOUT

OSC1/PBTN

VDD

4

5

6

7

SUM

8

VSS

9

RC0/LDACA

RC1/CMPA

RC2

10

11

12

13

14

VREG

RC7/SDAA

RC6/SCLA

RC5

RC3/T0CKI

RC4

Analog Peripherals Features

MCLR/VPP

• Slope Analog-to-Digital (A/D) converter

- Eight external input channels

- Two channels with selectable input ranges

of -0.3V to VDD -2.0V or 0V to VDD -1.5V

- Seven internal input channels

- Programmable A/D resolution, up to 16 bits

- 16 ms maximum conversion time at maxi-

mum (16-bit) resolution and 4 MHz clock

Digital Peripherals Features

• 20 I/O pins with individual direction control

• High current sink/source for direct LED drive

• ADTMR: A/D counter, 16-bit counter with pre-load

and capture

• TMR0: 8-bit timer/counter with 8-bit programma-

- 4-bit current DAC

ble prescaler

- Internal bandgap voltage reference

- Factory calibrated with calibration constants

stored in EPROM

2

•

I C serial port compatible with:

- ACCESS.bus

- SMBus (System Management Bus)

- Provisions for measuring energy in high fre-

quency pulses (e.g. GSM cellular telephone)

CMOS Technology

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide-operating voltage range (2.7V to 6.0V)

• Commercial and Industrial Temperature Range

• Low power dissipation (typical)

• On-chip temperature sensor

• Voltage regulator control output for 5V operation

• Two multi-range DACs for programmable level/

window detect or constant current/voltage charge

control

- < 3 mA @5V, 4 MHz operating mode

- < 200 µA @3V (Sleep mode: clocks stopped

with analog circuits active)

• On-chip low voltage detector

Special Microcontroller Features

- < 5 µA @3V (Hibernate mode: clocks

stopped and analog inactive)

• Power-on Reset (POR), Power-up Timer (PWRT)

and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Multi-segment programmable code-protection

• Selectable oscillator options

APPLICATIONS

• Battery chargers

• Battery Capacity Monitoring

-

Internal 4 MHz oscillator

External crystal oscillator

• Uninterruptable power supply controllers

• Power Management Controllers

• HVAC controllers

•

Two pin serial in-system EPROM programming

• Sensing and Data Acquisition

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 1

PIC14000

TABLE OF CONTENTS

1.0:

2.0:

3.0:

4.0:

5.0:

6.0:

7.0:

8.0:

9.0:

General Description ......................................................................................................................... 3

Device Varieties ............................................................................................................................... 5

Architectural Overview ..................................................................................................................... 7

Memory Organization..................................................................................................................... 13

I/O Ports......................................................................................................................................... 27

Timer Modules ............................................................................................................................... 39

2

Inter-integrated Circuit Serial Port (I C) ......................................................................................... 43

Analog Modules for A/D Conversion.............................................................................................. 57

Other Analog Modules ................................................................................................................... 65

10.0: Special Features of the CPU.......................................................................................................... 73

11.0: Instruction Set Summary................................................................................................................ 91

12.0: Development Support .................................................................................................................. 103

13.0: Electrical Characteristics for PIC14000.........................................................................................107

14.0: Analog Specifications................................................................................................................... 118

15.0: DC and AC Characteristics Graphs and Tables for PIC14000 .................................................... 119

Appendix A: Differences between PIC14000 and PIC16C74 ......................................................125

List of Examples............................................................................................................................127

List of Figures................................................................................................................................127

List of Tables.................................................................................................................................128

Connecting to Microchip BBS .......................................................................................................129

Reader Response .........................................................................................................................130

PIC14000 Product Identification System.......................................................................................132

Worldwide Sales and Service .......................................................................................................132

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted

to a new publishing software package which we believe will enhance our entire documentation process and product.

As in any conversion process, information may have accidently been altered or deleted. We have spent an excep-

tional amount of time to ensure that these documents are correct. However, we realize that we may have missed a

few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

DS40122A-page 2

Preliminary

1995 Microchip Technology Inc.

PIC14000

The internal band-gap reference is used for calibrating

the measurements of the analog peripherals. The

calibration factors are stored in EPROM and can be

used to achieve high measurement accuracy.

1.0

GENERAL DESCRIPTION

The PIC14000 is a low-cost, high-performance, CMOS,

fully-static, mixed signal, factory calibrated, 8-bit

microcontroller. Its features include medium to high

resolution A/D conversion (10 to 16 bits), temperature

sensing, closed loop charge control, serial communica-

tion, and low power operation.

Power savings modes are required for in-battery pack

applications. The SLEEP and HIBERNATE modes offer

different levels of power savings. The PIC14000 can

wake up from these modes through interrupts or reset.

The PIC14000 is based on the high-performance

A UV erasable CERDIP packaged version is ideal for

code development, while the cost-effective One-Time

Programmable (OTP) version is suitable for production

in any volume.

PIC16C74 core. It uses

a

RISC-like Harvard

architecture CPU with separate 14-bit instruction and

8-bit data buses. A two-stage instruction pipeline

allows all instructions to execute in a single cycle,

except for program branches, which require two cycles.

A total of 35 instructions are available. Additionally, a

large register set is included.

The PIC14000 ﬁts perfectly in applications for battery

charging, capacity monitoring, and data logging. The

EPROM technology makes customization of

application programs (battery characteristics, feature

sets, etc.) extremely fast and convenient. The small

footprint packages make this microcontroller based

mixed signal device perfect for all applications with

space limitations. Low-cost, low-power, high perfor-

mance, ease of use and I/O ﬂexibility make the

PIC14000 very versatile in other applications such as

temperature monitors/controllers and transducer com-

pensators.

PIC16/17 microcontrollers typically achieve a 2:1 code

compression and a 4:1 speed improvement over other

8-bit microcontrollers.

Features:

The PIC14000 is a 28-pin device with these features:

• 4K of EPROM

• 192 bytes of RAM

•

20 I/O pins

1.1

Family and Upward Compatibility

The analog peripherals include:

• 8 external analog input channels, including

2 current sense input channels

Code written for PIC16C6X/7X can be easily ported to

the PIC14000 (see Appendix A).

• 6 internal analog input channels

1.2

Development Support

• 2 charge-control channels with comparators

• A bandgap reference

• An internal temperature sensor

• A programmable current source for dynamic

range control of the A/D conversion

• Two 8-bit logarithmic DACs

The PIC14000 is supported by a full-featured macro

assembler, a software simulator, an in-circuit emulator,

a

full-featured programmer. A “C” compiler and fuzzy

logic support tools are also available.

low-cost development programmer and

a

2

In addition, the I C serial port through a multiplexer

2

supports two separate I C channels.

A special oscillator option allows either an internal

4 MHz oscillator or an external crystal oscillator. Using

the internal 4 MHz oscillator requires no external com-

ponents. Using the external oscillator option requires

the PIC14000 to be in HS mode.

The PIC14000 contains two timers, WDT and TMR0.

The Watchdog Timer (WDT) includes its own on-chip

RC oscillator providing protection against software

lock-up. TMR0 is a general purpose 8-bit timer/counter

with an 8-bit prescaler. It may be clocked externally

using the RC3/T0CKI pin.

Internal low-voltage detect circuit allows for tracking of

voltage levels. Upon detecting the low voltage condi-

tion, the PIC14000 can be instructed to save its operat-

ing state then enter reset mode.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 3

PIC14000

NOTES:

DS40122A-page 4

Preliminary

1995 Microchip Technology Inc.

PIC14000

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. The PIC14000 Product Selection System

section at the end of this data sheet provides the

devices options to be selected for your speciﬁc applica-

tion and production requirements. When placing

orders, please use the “PIC14000 Product Identiﬁca-

tion System” at the back of this data sheet to specify the

correct part number.

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devices but with all EPROM locations and

fuse options already programmed by the factory.

Certain code and prototype veriﬁcation procedures do

apply before production shipments are available.

Please contact your local Microchip Technology sales

ofﬁce for more details.

2.1

UV Erasable Devices

The UV erasable version, offered in CERDIP package,

is optimal for prototype development and pilot

programs.

2.4

Serialized Quick-Turnaround

Production (SQTP^SM) Devices

The UV erasable version can be erased and

reprogrammed to any of the conﬁguration modes.

Microchip offers a unique programming service where

a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

Note: Please note that erasing the device erases

the pre-programmed calibration factors.

Before erasing the device, read out the cal-

ibration information, store these values, and

use them when programming the program

memory. Please refer to the section on Pro-

gram Memory for more details on these

locations.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password or ID number.

Microchip's PICSTART and PRO MATE programmers

both support programming of the PIC14000. Third party

programmers are also available, refer to Microchip’s

Third Party Guide for a list of sources.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the ﬂexibility for frequent code

updates or small volume applications.

The OTP devices, packaged in plastic packages permit

the user to program them once. In addition to the

program memory, the conﬁguration bits must also be

programmed.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 5

PIC14000

NOTES:

DS40122A-page 6

Preliminary

1995 Microchip Technology Inc.

PIC14000

The ALU is capable of addition, subtraction, shift, and

logical operations. Unless otherwise mentioned,

arithmetic operations are two's complement. In

two-operand instructions, typically one operand is the

working register (W register). The other operand is a

ﬁle register or an immediate constant. In single

operand instructions, the operand is either the

W register or a ﬁle register.

3.0

ARCHITECTURAL OVERVIEW

The PIC14000 addresses 4K x 14 program memory. All

program memory is internal. The PIC14000 can directly

or indirectly address its register ﬁles or data memory. All

special function registers including the program counter

are mapped in the data memory. The PIC14000 has an

orthogonal instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘special optimal situations’ make programming with the

PIC14000 simple yet efﬁcient. In addition, the learning

curve is reduced signiﬁcantly.

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC), and

Zero (Z) bits in the STATUS register. The C and DC bits

operate as a Borrow and Digit Borrow, respectively, in

subtraction operations. See the SUBLW and SUBWF

instructions for examples.

The PIC14000 contains an 8-bit ALU and working

register. The ALU performs arithmetic and Boolean

functions between data in the working register and any

register ﬁle.

A simpliﬁed block diagram for the PIC14000 is shown

in Figure 3-1, its corresponding pin description is

shown in Table 3-1.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 7

PIC14000

FIGURE 3-1: PIC14000 SIMPLIFIED BLOCK DIAGRAM

OSC1

OSC2/CLKOUT

8-bit RISC CPU

Oscillator

Select

Internal 4 MHz

Oscillator

VREG

External Voltage

Regulator Control

Watchdog

Timer

VDD

LVD

Low Voltage Detector

T0CKI

Bandgap

Reference

TMR0

ALU

Slope Reference

Generator

RD4/AN4

RD6/AN6

RD7/AN7

RA0/AN0

RA2/AN2

RA3/AN3

4K EPROM

192 RAM

16:1

MUX

Slope A/D

Internal

Temperature

Sensor

GP I/O*

I/O Control

RA1/AN1

Summing Junctions,

Interrupt

RD5/AN5

SUM

Filtering & Zeroing

Circuits

Controller

CDAC

CMPA

LDACA

Dual, 3 Decade

Logarithmic

DACs

2

I C

Controller

SDA

SCL

4:2 MUX

LDACB

SDAA

SCLA

SCLB

SDAB

CMPB

*Denotes general purpose I/O pins.

DS40122A-page 8

Preliminary

1995 Microchip Technology Inc.

PIC14000

TABLE 3-1:

PIN DESCRIPTIONS

NO.

PIN TYPE

INPUT OUTPUT

PIN NAME

I/O

DESCRIPTION

CDAC

22

O

-

AN

A/D ramp DAC current output. Normally connected to

external capacitor to generate a linear voltage ramp.

RA0/AN0

RA1/AN1

2

I/O

AN/ST

CMOS

Analog input channel 0. This pin can also serve as a

general-purpose I/O.

1

Analog input channel 1. This pin has an internal summing

junction and a zeroing network. If enabled, a +0.5V offset

is added to the input voltage. Also contains a switch to

disconnect the input voltage from the summing junction.

This pin can also serve as a general-purpose I/O.

RA2/AN2

RA3/AN3

SUM

28

27

21

I/O

O

AN/ST

-

CMOS

AN

Analog input channel 2. This pin can also serve as a

general purpose digital I/O.

Analog input channel 3. Can also serve as a general

purpose digital I/O.

AN1 summing junction output. This pin can be connected

to an external capacitor for averaging small duration

pulses.

RC0/LDACA

RC1/CMPA

RC2

19

18

17

16

15

I/O-PU

ST

CMOS

LED direct-drive segment output or comparator A input /

DAC output. This pin can also serve as a GPIO. If

enabled, this pin has a weak internal pull-up to VDD.

LED direct-drive output or comparator A output. This pin

can also serve as a GPIO. If enabled, this pin has a

weak internal pull-up to VDD.

LED direct-drive segment output. This pin can also serve

as a GPIO. If enabled, this pin has a weak internal pull-up

to VDD

RC3/T0CKI

RC4

LED direct-drive segment output. This pin can also serve

as a GPIO, or an external clock input for Timer0. If

enabled, this pin has a weak internal pull-up to VDD.

LED direct-drive segment output. This pin can also serve

as a GPIO. If enabled, a change on this pin can cause a

CPU interrupt. If enabled, this pin has a weak internal

pull-up to VDD.

RC5

13

12

I/O-PU

I/O

ST

CMOS

LED direct-drive segment output. This pin can also serve

as a GPIO. If enabled, a change on this pin can cause a

CPU interrupt. If enabled, this pin has a weak internal

pull-up to VDD.

RC6/SCLA

ST/SM

NPU/OC

General purpose I/O. If enabled, is multiplexed as

2

(No P-diode) synchronous serial clock for I C interface. Also is the

serial programming clock. If enabled, a change on this pin

can cause a CPU interrupt. This pin has an N-channel

pull-up device which can be disabled. Pull-ups are nor-

mally active. Programmable control for compatibility with

SMBus voltage levels.

RC7/SDAA

11

I/O

ST/SM

NPU/OC

General purpose I/O. If enabled, is multiplexed as

2

(No P-diode) synchronous serial data I/O for I C interface. Also is the

serial programming data line. If enabled, a change on this

pin can cause a CPU interrupt. This pin has an N-channel

pull-up device which can be disabled. Pull-ups are nor-

mally active. Programmable control for compatibility with

SM-BUS voltage levels.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 9

PIC14000

TABLE 3-1:

PIN DESCRIPTIONS (CONTINUED)

NO.

PIN TYPE

INPUT OUTPUT

PIN NAME

I/O

DESCRIPTION

RD0/SCLB

6

I/O

ST/SM

NPU/OC

General purpose I/O. If enabled, is multiplexed as

2

(No P-diode) synchronous serial clock for I C interface. This pin has an

N-channel pull-up device which can be disabled.

Pull-ups are normally active. Programmable control for

compatibility with SMBus

voltage levels.

RD1/SDAB

5

I/O

ST/SM NPU/OC

General purpose I/O. If enabled, is multiplexed as

2

(No P-diode) synchronous serial data I/O for I C interface. This pin has

an N-channel pull-up device which can be disabled.

Pull-ups are normally active. Programmable control for

compatibility with SMBus voltage levels.

RD2/CMPB

RD3/LDACB

4

3

I/O-PU AN/ST CMOS

General purpose I/O or comparator B output.

General purpose I/O or comparator B input / DAC

output.

RD4/AN4

RD5/AN5

26

25

I/O

AN/ST CMOS

Analog input channel 4. This pin can also serve as a

general purpose digital I/O.

Analog input channel 5. This pin has an internal summing

junction and a zeroing network. If enabled, a +0.5V offset

is added to the input voltage. Also contains a switch to

disconnect the input voltage from the summing junction.

This pin can also serve as a general-purpose I/O.

RD6/AN6

RD7/AN7

VREG

24

23

10

8

I/O

O

AN/ST CMOS

Analog input channel 6. This pin can also serve as a

general purpose digital I/O.

Analog input channel 7. Can also serve as a general

purpose digital I/O.

-

AN

-

This pin is an output to control the gate of an external

N-FET for voltage regulation.

OSC1/PBTN

I-PU

ST

Input with weak pull-up resistor, can be used to generate

an interrupt to the CPU on a falling edge, if in IN mode.

Becomes oscillator input in HS mode. Connect to

external crystal/resonator, or external oscillator.

OSC2/CLK-

OUT

7

O

-

CMOS

Digital output in IN mode. Becomes oscillator output in

HS mode. Connect to external crystal/resonator. Refer to

Section 10.1 for oscillator conﬁguration.

MCLR/VPP

14

I/PWR

ST

Master clear (reset) input / programming voltage pin. This

pin is an active low reset to the device.

VDD

VSS

9

PWR

GND

Positive supply connection

Return supply connection

20

Legend:

TYPE:

Deﬁnition:

TTL

CMOS

ST

TTL-compatible input

CMOS-compatible input or output

Schmitt trigger input, with CMOS levels

SM

SM-bus compatible input. VIL=0.6V, VIH=1.4V

OC

Open-collector output. An external pull-up resistor is required if this pin is used as an output.

N-channel pull-up. This pin will pull-up to approximately VDD - 1.0V when outputting a logical ‘1’.

Weak internal pull-up (10K-50K ohms)

NPU

PU

No-P diode

No P-diode to VDD. This pin may be pulled above the supply rail (to 6.0V maximum).

Analog input or output

AN

DS40122A-page 10

Preliminary

1995 Microchip Technology Inc.

PIC14000

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (from OSC1 or the internal oscillator) is

internally divided by four to generate four

non-overlapping quadrature clocks, namely Q1, Q2, Q3

and Q4. The program counter (PC) is incremented

every Q1, the instruction is fetched from the program

memory and latched into the instruction register in Q4.

The instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution ﬂow are shown in Figure 3-2.

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the instruction

(Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register (IR)” in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Internal

Phase

Clock

Q4

PC

PC+1

PC+2

CLKOUT

(IN mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Execute 1

Fetch 2

Fetch 1

1. MOVLW

2. MOVWF

3. CALL

4. BSF

55h

PORTB

SUB_1

PORTA, BIT3

Execute 2

Fetch 3

Execute 3

Fetch 4

Fetch SUB_1

Flush

Fetch SUB_1

All instructions are single cycle, except for program branches. These take two cycles

since the fetched instruction is “flushed” from the pipeline while the new instruction is be-

ing fetched and then executed.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 11

PIC14000

NOTES:

DS40122A-page 12

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.1.1

CALIBRATION SPACE

4.0

MEMORY ORGANIZATION

The Calibration Space is not used for instructions. This

section stores constants and factors for the arithmetic

calculations to calibrate the analog measurements.

4.1

Program Memory Organization

The PIC14000 family has a 13-bit program counter

capable of addressing an 8K x 14 program memory

space. Only the ﬁrst 4K x 14 (0000-0FFFh) are

physically implemented. Accessing a location above

the physically implemented address will cause a

wraparound. The reset vector is at 0000h and the

interrupt vector is at 0004h (Figure 4-1).

TABLE 4-1:

CALIBRATION DATA

FORMATS

Address Parameter Symbol Units Min/Max Format

32-bit

0FC0h-0 Slope

unit-less

ratio

K

0.1/0.15 ﬂoating

ref

bg

FC3h

reference

point**

The 4096 words of Program Memory space are divided

into:

Bandgap

reference

voltage

32-bit

ﬂoating

point

0FC4h-0

FC7h

K

Volts

1.0/1.5

• Address Vectors (addr 0000h-0004h)

Tempera-

ture sensor

voltage

32-bit

• Program Memory Page 0 (addr 0005h-07FFH)

• Program Memory Page 1 (addr 0800h-0DFFh)

0FC8h-0

FCBh

V

0.0/1.0 ﬂoating

point

thrm

• User Program Space (448 words, addr

0E00h-0FBFh)

Tempera-

0FCCh-0 ture sensor

Volts/

degree

Celsius

32-bit

0.001/

K

ﬂoating

0.0010

• Calibration Space (64 words, addr 0FC0h-0FFFh)

tc

FCFh

voltage

point

coefﬁcient

Program code may reside in Page 0, Page 1, and User

Program Space. PCLATH set to select Page 1 allows

access to the User Program Space.

Internal

main

oscillator

frequency

byte *

10KHz

+3.0MHz

F

0FD0h

0FD2h

byte

osc

FIGURE 4-1: PIC14000 PROGRAM

MEMORY MAP AND STACK

WDT fre-

quency

Hz

25-200

byte

wdt

PC <12:0>

(optional)

13

CALL, RETURN,

RETFIE, RETLW

** Microchip modiﬁed IEEE754 32-bit ﬂoating point for-

mat. Refer to application note AN575 for details.

Stack Level 1

•

Stack Level 8

0000h

Reset Vector

•

Interrupt Vector

0004h

0005h

On-chip Program

Memory (Page 0)

07FFh

0800h

On-chip Program

Memory (Page 1)

0DFFh

0E00h

User Program Space

(448 words)

Calibration Space

(64 words)

0FBFh

0FC0h

0FFFh

1000h

1FFFh

2000h

Unimplemented

2007h

20FFh

Conﬁguration Fuses*

* In Test Program Memory Space

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 13

PIC14000

4.2.1

GENERAL PURPOSE REGISTER FILE

TABLE 4-2:

CALIBRATION CONSTANT

ADDRESSES

The register ﬁle is accessed either directly, or indirectly

through the ﬁle select register FSR (Section 4.4).

Address Data

FIGURE 4-2: REGISTER FILE MAP

K

V

, exponent (eb)

0FC0

0FC1

0FC2

0FC3

0FC4

0FC5

0FC6

0FC7

0FC8

0FC9

0FCA

0FCB

0FCC

0FCD

0FCE

0FCF

0FD0

0FD1

0FD2

ref

bg

File Address

, mantissa high byte (f0)

, mantissa middle byte (f1)

, mantissa low byte (f2)

, exponent (eb)

00

01

02

03

04

05

06

07

Indirect add.(*)

Indirect addr.(*)

OPTION

PCL

80

81

82

83

84

85

86

TMR0

PCL

STATUS

FSR

STATUS

FSR

, mantissa high byte (f0)

, mantissa middle byte (f1)

, mantissa low byte (f2)

, exponent (eb)

PORTA

RESERVED

PORTC

PORTD

TRISA

RESERVED

TRISC

87

88

89

8A

8B

8C

8D

8E

8F

90

91

92

93

thrm

08

09

0A

0B

0C

0D

0E

0F

10

11

TRISD

, mantissa high byte (f0)

, mantissa middle byte (f1)

, mantissa low byte (f2)

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

K , exponent (eb)

tc

K , mantissa high byte (f0)

ADTMRL

ADTMRH

PCON

tc

SLPCON

K , mantissa middle byte (f1)

tc

K , mantissa low byte (f2)

tc

F , unsigned byte

12

13

in

2

I CBUF

I CADD

reserved

2

14

94

I CCON

I CSTAT

F

, unsigned byte (optional)

wdt

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

ADCAPL

ADCAPH

95

96

97

98

99

9A

9B

9C

9D

9E

9F

A0

0FD3 -

0FFE

reserved

0FFE

0FFF

calibration space checksum, low byte

calibration space checksum, high byte

4.2

Data Memory Organization

LDACA

LDACB

CHGCON

MISC

The data memory (Figure 4-2) is partitioned into two

Banks which contain the general purpose registers and

the special function registers. Bank 0 is selected when

the RP0 bit in the STATUS register is cleared. Bank 1 is

selected when the RP0 bit in the STATUS register is

set. Each Bank extends up to 7Fh (128 bytes). The ﬁrst

32 locations of each Bank are reserved for the Special

Function Registers. Several Special Function

Registers are mapped in both Bank 0 and Bank 1. The

General Purpose Registers, implemented as static

RAM, are located from address 20h through 7Fh.

ADCON0

ADCON1

General

Purpose

Register

(96 Bytes)

General

Purpose

Register

(96 Bytes)

7F

FF

* Not a physical register.

Shaded areas are unimplemented memory locations,

read as ’0’s.

DS40122A-page 14

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.2.2

SPECIAL FUNCTION REGISTERS

The special registers are classiﬁed into two sets.

Special registers associated with the “core” functions

are described in this section. Those registers related to

the operation of the peripheral features are described in

the section speciﬁc to that peripheral.

The Special Function Registers are registers used by

the CPU and Peripheral functions for controlling the

desired operation of the device (Table 4-3). These reg-

isters are static RAM.

TABLE 4-3:

SPECIAL REGISTERS FOR THE PIC14000

Address

Bank0

Name

B7

B6

B5

B4

B3

B2

B1

B0

INDF

(Indirect

Address)

Addressing this location uses contents of the FSR to address data memory (not a physical

register).

00 *

01

02*

03*

04*

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

TMR0

Timer0 data

PCL

Program Counter’s (PC’s) least significant byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect data memory address pointer

PORTA data latch.

PORTA

Reserved

PORTC

PORTD

Reserved

PCLATH

INTCON

PIR1

Reserved for emulation.

PORTC data latch

PORTD data latch

Buffered register for the upper 5 bits of the Program Counter (PC)

GIE

PEIE

-

T0IE

-

r

T0IF

r

2

WUIF

PBIF

I CIF

RCIF

ADCIF

OVFIF

Reserved

ADTMRL

ADTMRH

Reserved

A/D capture timer data least significant byte

A/D capture timer data most significant byte

2

I CBUF

I C Serial Port Receive Buffer/Transmit Register

2

I CCON

WCOL

I COV

I CEN

CKP

I CM3

I CM2

I CM1

I CM0

ADCAPL

ADCAPH

Reserved

ADCON0

A/D capture latch least significant byte

A/D capture latch most significant byte

ADCS3

ADCS2

ADCS1

ADCS0

-

AMUXOE

ADRST ADZERO

Legend

— indicates unimplemented locations, read as ’0’ but cannot be overwritten

indicates reserved locations, default is POR value and should not be overwritten with any value

r

Reserved indicates reserved register and should not be overwritten with any value

* indicates registers that can be addressed from either bank

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 15

PIC14000

TABLE 4-3:

SPECIAL REGISTERS FOR THE PIC14000 (CONTINUED)

Address

Bank1

Name

B7

B6

B5

B4

B3

B2

B1

B0

INDF

(Indirect Ad-

dress)

Addressing this location uses contents of FSR to address data memory (not a physical regis-

ter).

80 *

81

82 *

83 *

84 *

85

OPTION

PCL

RCPU

Program Counter’s (PC’s) least significant byte

IRP RP1 RP0 TO

r

TOCS

TOSE

PSA

PD

PS2

Z

PS1

DC

PS0

C

STATUS

FSR

Indirect data memory address pointer

PORTA Data Direction Register

Reserved for emulation

TRISA

86

Reserved

TRISC

87

PORTC Data Direction Register

PORTD Data Direction Register

88

TRISD

89

Reserved

PCLATH

INTCON

PIE1

8A

8B

8C

8D

8E

8F

90

Buffered register for the upper 5 bits of the Program Counter (PC)

GIE

PEIE

-

T0IE

-

r

T0IF

r

2

WUIE

PBIE

I CIE

RCIE

ADCIE

OVFIE

Reserved

PCON

-

POR

LVD

SLPCON

Reserved

HIBEN

REFOFF BIASOFF OSCOFF CWUOFF TEMPOFF ADOFF

91

92

2

93

I CADD

I C Synchronous Serial Port Address Register

D/A

2

94

I CSTAT

-

P

S

R/W

UA

BF

95

Reserved

LDACA

96

97

98

99

9A

9B

9C

9D

9E

9F

LDASEL7 LDASEL6 LDASEL5 LDASEL4 LDASEL3 LDASEL2 LDASEL1 LDASEL0

LDBSEL7 LDBSEL6 LDBSEL5 LDBSEL4 LDBSEL3 LDBSEL2 LDBSEL1 LDBSEL0

LDACB

CHGCON

MISC

-

CCOMPB CCBEN

CPOLB

-

CCOMPA CCAEN

CPOLA

OSC1

2

SMHOG SPGND SPGND

I CSEL

SMBUS INCLKEN

ACFG2

OSC2

ADCON1

ADDAC3 ADDAC2 ADDAC1 ADDAC0 ACFG3

ACFG1

ACFG0

Legend

— indicates unimplemented locations, read as ’0’ but cannot be overwritten

indicates reserved locations, default is POR value and should not be overwritten with any value

r

Reserved indicates reserved register and should not be overwritten with any value

* indicates registers that can be addressed from either bank

DS40122A-page 16

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.2.2.1

STATUS REGISTER

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

status registers because these instructions do not

affect any status bit. For other instructions, not affecting

any status bits, see the “Instruction Set Summary

The STATUS register (Address 03h or 83h) contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

The STATUS register (03h) can be the destination for

any instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared. Furthermore,

the TO and PD bits are not writable. Therefore, the

result of an instruction with the STATUS register as

destination may be different than intended.

Note 1: The IRP and RP1 bits (STATUS<7:6>) are

not used by the PIC14000 and should be

programmed as cleared. Use of these bits

as general purpose R/W bits is NOT

recommended, since this may affect

upward compatibility with future products.

Note 2: The C and DC bits operate as a borrow

and digit borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the status register as

000UU1UU (where U = unchanged).

FIGURE 4-3: STATUS REGISTER

83h

B7

B6

B5

B4

TO

R

B3

PD

R

B2

Z

B1

DC

R/W

X

B0

C

STATUS

IRP

R/W

0

RP1

R/W

0

RP0

R/W

0

Read/Write

POR value FFh

R/W

X

R/W

X

1

Bit

Name

Function

Not used. This bit should be programmed as ’0’.

B7

IRP

Use of this bit as a general purpose read/write bit is not recommended, since this may

affect upward compatibility with future products.

Not used. This bit should be programmed as ’0’.

B6

B5

RP1

RP0

Use of this bit as a general purpose read/write bit is not recommended, since this may

affect upward compatibility with future products.

Register page select for direct addressing.

1 = Bank1 (80h - FFh)

0 = Bank0 (00h - 7Fh)

Each page is 128 bytes. Only the RP0 bit is used.

Time-out bit.

B4

B3

B2

TO

PD

Z

1 = After power-up and by the CLRWDTand SLEEPinstruction.

0 = A watchdog timer time-out has occurred.

Power down bit.

1 = After power-up or by a CLRWDTinstruction.

0 = By execution of the SLEEPinstruction.

Zero bit.

1 = The result of an arithmetic or logic operation is zero.

0 = The result of an arithmetic or logical operation is not zero.

Digit carry / borrow bit.

For ADDWFand ADDLWinstructions.

B1

B0

DC

1 = A carry-out from the 4th low order bit of the result.

0 = No carry-out from the 4th low order bit of the result.

Note: For Borrow, the polarity is reversed.

Carry / borrow bit.

For ADDWFand ADDLWinstructions.

1 = A carry-out from the most signiﬁcant bit of the result occurred. Note that a

subtraction is executed by adding the two’s complement of the second operand. For

rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

C

0 = No carry-out from the most signiﬁcant bit of the result.

Note: For Borrow the polarity is reversed.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 17

PIC14000

FIGURE 4-4: EVENTS AFFECTING PD/TO STATUS BITS

Event

TO

PD

Remarks

Power-up

1

0

1

U

0

WDT Time-out

SLEEPInstruction

CLRWDT

No effect on PD

Hibernate accessed via SLEEPinstruction

1

TABLE 4-4:

TO

PD/TO STATUS AFTER RESET

PD

RESET was caused by

0

1

0

1

U

WDT Wake-up from SLEEP or Hibernate

WDT time-out (not during SLEEP)

MCLR wake-up from SLEEP or Hibernate

Power-up

U

1

U

MCLR reset during normal operation

DS40122A-page 18

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.2.2.2

OPTION REGISTER

Note: To achieve a 1:1 prescaler assignment,

The OPTION register (Address 81h) is a readable and

writable register which contains various control bits to

conﬁgure the TMR0/WDT prescaler, the external PBTN

interrupt, TMR0, and the weak pull-ups on PORTC

<5:0>. Bit6 is reserved in PIC14000.

assign the prescaler to the WDT (PSA=1)

FIGURE 4-5: OPTION REGISTER

R/W

r

R/W R/W R/W R/W R/W R/W

T0CS T0SE PSA PS2 PS1 PS0

W:

R:

U:

Writable

Readable

Unimplemented.

Read as '0'

Register:

Address:

POR value:

OPTION

81h

RCPU

FFh

bit7

bit0

PRESCALER VALUE

TMR0 RATE WDT RATE

PS2:PS0

PS2

0

PS1 PS0

0

1

0

1

0

1

0

1

0

1

0

1

1 : 2

1 : 1

0

1

1 : 4

1 : 2

1 : 8

1 : 4

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

PSA: Prescaler assignment bit.

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to TMR0

T0SE: TMR0 source edge.

1 = Increment on high-to-low transition on RC3/T0CKI pin

0 = Increment on low-to-high transition on RC3/T0CKI pin

T0CS: TMR0 clock source.

1 = Transition on RC3/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

Reserved. This bit should be programmed as a “1”. Use of this bit as

general purpose read/write is not recommended since this may affect

upward compatibility with future products.

RCPU: PORTC pull-up enable.

1 = PORTC pull-ups are disabled overriding any port latch value (RC <5:0> only)

0 = PORTC pull-ups are enabled by individual port-latch values (RC <5:0>)

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 19

PIC14000

4.2.2.3

INTCON REGISTER

Note: The T0IF will be set by the speciﬁed

condition even if the corresponding Inter-

rupt Enable Bit is cleared (interrupt

disabled) or the GIE bit is cleared (all

interrupts disabled). Before enabling

interrupt, clear the interrupt ﬂag, to ensure

that the program does not immediately

branch to the peripheral interrupt service

routine

The INTCON Register is a readable and writable

register which contains the various enable and ﬂag bits

for the Timer0 overﬂow, peripheral pin interrupts.

Figure 4-6 shows the bits for the INTCON register for

the PIC14000.

FIGURE 4-6: INTCON REGISTER

R/W R/W

R/W

R/W R/W R/W R/W R/W

W: Writable

Register:

Address:

INTCON

0Bh or 8Bh

R:

Readable

Unimplemented,

r

GIE PEIE T0IE

r

T0IF

r

POR value: 0000 000xb U:

read as '0'

bit0

bit7

Reserved. This bit should be programmed as ’0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

Reserved. This bit should be programmed as ’0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

T0IF: TMR0 overflow interrupt flag.

1 = The TMR0 has overflowed.

Must be cleared by software.

0 = TMR0 did not overflow.

Reserved. This bit should be programmed as ’0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

Reserved. This bit should be programmed as ’0’. Use of this bit

as a general purpose read/write bit is not recommended, since

this may affect upward compatibility with future products.

T0IE: TMR0 interrupt enable bit.

1 = Enables T0IF interrupt

0 = Disables T0IF interrupt

PEIE: Peripheral interrupt enable bit.

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

GIE: Global interrupt enable.

1 = Enables all un-masked interrupts

0 = Disables all interrupts

DS40122A-page 20

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.2.2.4

PIE1 REGISTER

Note: INTCON<6> must be enabled to enable

This register contains the individual enable bits for the

Peripheral interrupts including A/D capture event, I C

any interrupt in PIE1.

2

serial port, PORTC change and A/D capture timer

overﬂow.

FIGURE 4-7: PIE1 REGISTER

R/W

R

R/W

Register:

Address:

PIE1

W: Writable

PBIE I²CIE

RCIE

ADCIE

OVFIE

—

WUIE

—

8Ch R:

Readable

00h

U:

bit0

POR value:

Unimplemented,

read as '0'

bit7

OVFIE: A/D Counter Overflow Interrupt Enable.

1 = Enables A/D counter overflow interrupt (OVFIF)

0 = Disables A/D counter overflow interrupt (OVFIF)

ADCIE: A/D Capture Event Interrupt Enable

1 = A/D capture interrupt is enabled

0 = A/D capture interrupt is disabled

RCIE:

PORTC Interrupt on change Enalbe

1 = Enables RCIF interrupt on pinsRC<7:4>

0 = Disables RCIF interrupt

I²CIE: I²C Port Interrupt Enable

1 = Enables I²CIF interrupt.

0 = Disables I²CIF interrupt.

PBIE: External Pushbutton Interrupt Enable

1 = Enable PBTN (pushbutton)interrupt on OSC1/PBTN.

(Note this interrupt not available if crystal oscillator

selected).

0 = Disable PBTN interrupt on OSC1/PBTN

Unimplemented. Read as ’0’.

WUIE: Wake-up on Current Flow Interrupt Enable

1 = Enables wake-up on current flow (WUIF) interrupt

0 = Disables wake-up on current flow (WUIF) interrupt

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 21

PIC14000

4.2.2.5

PIR1 REGISTER

Note: These bits will be set by the speciﬁed

condition, even if the corresponding

Interrupt Enable bit is cleared (interrupt

disabled) or the GIE bit is cleared (all

interrupts disabled). Before enabling an

interrupt, the user may wish to clear the

corresponding interrupt ﬂag, to ensure that

the program does not immediately branch

to the Peripheral Interrupt service routine.

This register contains the individual ﬂag bits for the

Peripheral interrupts (Figure 4-8).

FIGURE 4-8: PIR1 REGISTER

R/W

R

R/W

W: Writable

Register: PIR1

Address: 0Ch

POR value: 00h

2

WUIF

—

PBIF

OVFIF

—

I CIF

RCIF

ADCIF

R: Readable

U: Unimplemented,

read as ‘0’

bit7

bit0

OVFIF: A/D counter Overflow Interrupt Flag

1 =An A/D counter overflow has occurred (error).

Must be cleared in software.

0 = An A/D counter overflow has not occurred

ADCIF: A/D Conversion Capture Complete Interrupt Flag

1 =An A/D capture event has completed.

Must be cleared in software.

0 = An A/D conversion has not completed

RCIF: PORTC Interrupt on Change Flag

1 =At least one RC<7:4> input changed.

Must be cleared in software.

0 =None of the RC<7:4> inputs have changed

2

I CIF: I²C Port Interrupt Flag

1 =A transmission/reception is completed.

Must be cleared in software.

0 =Waiting to transmit/receive

PBIF: External Pushbutton Interrupt Flag

1 =The external pushbutton interrupt has occurred

on OSC1/PBTN. Note: This interrupt is not available

if crystal oscillator mode.

0 =The external pushbutton interrupt did not occur.

Unimplemented. Read as ’0’

WUIF: Wake-up on Current Flow Interrupt Flag

1 =The wake-up on current detect interrupt has occurred

Must be cleared in software.

0 = The wake-up on current flow did not occur

DS40122A-page 22

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.2.2.6

PCON REGISTER

These bits are cleared on POR. The user must set

these bits following POR. On a subsequent reset if

POR is cleared, this is an indication that the reset was

due to a power-on reset condition.

The Power Control (PCON) register status contains

2 ﬂag bits to allow differentiation between a Power-on

Reset/low-voltage condition to an external MCLRreset,

or WDT reset (Figure 4-9).

FIGURE 4-9: PCON REGISTER

R/W

r

R/W

r

R/W

r

R/W R/W

R/W

POR

R/W

W: Writable

Register: PCON

Address: 8Eh

POR value: 02h

r

LVD

bit0

R: Readable

U: Unimplemented,

read as ‘0’

bit7

LVD: Low Voltage detect Flag

1 = A low-voltage detect condition has not occurred.

0 = A low-voltage detect condition has occurred

Software must set this bit after a

power-on-reset condition has occured.

POR: Power on Reset Flag

1 = A power on reset condition has not occurred.

Reset must be due to some other source

(WDT, MCLR).

0 = A power on reset condition has occurred.

Software must set this bit after a

power-on-reset condition has occured.

Reserved. Bits 7-2 are reserved. They should be

programmed as ’0’

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 23

PIC14000

push (and so on).

4.3

PCL and PCLATH

The program counter (PC) is 13-bits wide. The low

byte, PCL, is a readable and writable register. The high

byte of the PC (PCH) is not directly readable or

writable. PCLATH is a holding register for PC<12:8>

where contents are transferred to the upper byte of the

program counter. When PC is loaded with a new value

during a CALL, GOTOor a write to PCL, the high bits

of PC are loaded from PCLATH as shown in

Figure 4-10.

Note 1: There are no STATUS bits to indicate

stack overﬂow or stack underﬂow

conditions.

Note 2: There are no instruction mnemonics

called PUSH nor POP. These are actions

that occur from the execution of theCALL,

RETURN,RETLW,orRETFIEinstructions,

or the vectoring to an interrupt address

4.3.3

PROGRAM MEMORY PAGING

FIGURE 4-10: LOADING OF PC IN

DIFFERENT SITUATIONS

The PIC14000 has 4K of program memory, but the

CALLand GOTOinstructions only have a 11-bit address

range. This 11-bit address range allows a branch within

a 2K program memory page size. To allow CALLand

GOTO instructions to address the entire 4K program

memory address range, there must be another bit to

specify the program memory page. This paging bit

comes from the PCLATH<3> bit (Figure 4-10). When

doing a CALLor GOTOinstruction, the user must ensure

that this page bit (PCLATH<3>) is programmed to the

desired program memory page. If aCALLinstruction (or

interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<3> is not required for the return instructions

(which pops the PC from the stack).

PCH

PCL

12

8

7

0

INST with PCL

as dest

PC

8

PCLATH<4:0>

PCLATH

ALU result

5

PCH

12 11 10

PCL

8

7

0

GOTO, CALL

PC

11

PCLATH<4:3>

PCLATH

Opcode <10:0>

2

Note: The PIC14000 ignores the PCLATH<4>

bit, which is used for program memory

pages 2 and 3 (1000h - 1FFFh). The use of

PCLATH<4> as

a

general purpose

Note: On POR, the contents of the PCLATH

register are unknown. The PCLATH should

be initialized before a CALL, GOTO, or any

instruction that modiﬁes the PCL register is

executed.

read/write bit is not recommended since

this may affect upward compatibility with

future products.

Example 4-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that the PCLATH is saved and restored by the interrupt

service routine (if interrupts are used).

4.3.1

COMPUTED GOTO

When doing a table read using a computed GOTO

method, care should be exercised if the table location

crosses a PCL memory boundary (each 256 byte

block). Refer to the application note “Table Read Using

the PIC16CXX”(AN556).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0X500

BSF

PCLATH, 3 ; Select page 1 (800h-FFFh)

CALL

SUB1_P1

:

; Call subroutine in

; page 1 (800h-FFFh)

4.3.2

STACK

:

The PIC140XX has an 8 deep x 13-bit wide hardware

stack (Figure 4-1). The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed in the stack

when a CALLinstruction is executed or an interrupt is

acknowledged. The stack is POPped in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a “PUSH” or a “POP”

operation.

ORG

0X900

SUB1 P1:

; called subroutine

; page 1 (800h-FFFh)

:

RETURN

; return to page 0

; (000h-7FFh)

The stack operates as a circular buffer. This means

that after the stack has been “PUSHed” eight times, the

ninth push overwrites the value that was stored from

the ﬁrst push. The tenth push overwrites the second

DS40122A-page 24

Preliminary

1995 Microchip Technology Inc.

PIC14000

4.4

Indirect Addressing, INDF and FSR

Registers

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20

;initialize pointer

;to RAM

movf

clrf

inc

FSR

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

FSR

;clear INDF register

;inc pointer

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register actually

accesses data pointed to by the ﬁle select register

(FSR). Reading INDF itself indirectly will produce 00h.

Writing to the INDF register indirectly results in a

no-operation (although status bits may be affected). An

effective 9-bit address is obtained by concatenating the

8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 4-11. However, IRP is not used in the

PIC14000.

btfss FSR,4 ;all done?

goto

;yes continue

CONTINUE:

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 4-2.

FIGURE 4-11: INDIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

6

RP1

0

RP0

from opcode

IRP

7

FSR

00

location select

bank select

00

location select

00

01

10

11

00

Data

Memory

not used

7F

Bank 0

Bank 1 Bank 2

Bank 3

Note: For memory map detail see Figure 4-1

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 25

PIC14000

NOTES:

DS40122A-page 26

Preliminary

1995 Microchip Technology Inc.

PIC14000

5.0

I/O PORTS

Note: On Power-on Reset, PORTA is conﬁgured

PIC14000 has three ports, PORTA, PORTC and

PORTD, described in the following paragraphs.

Generally, PORTA is used as the analog input port for

measuring battery voltage, current and temperature.

PORTC is used for general purpose I/O and for host

communication. PORTD provides additional I/O lines.

Four lines of PORTD may function as analog inputs.

They may be used to measure individual cell voltages,

for example, for rechargeable Lithium packs.

as analog inputs

The TRISA register controls the direction of the PORTA

pins, even when they are being used as analog inputs.

The user must make sure to keep the pins conﬁgured

as inputs when using them as analog inputs. A ‘1’ in

each location conﬁgures the corresponding port pin as

an input. This register resets to all ‘1’s, meaning all

PORTA pins are initially inputs. The data register

should be initialized prior to conﬁguring the port as out-

puts. See Figure 5-2 and Figure 5-3.

5.1

PORTA and TRISA

PORTA is a 4-bit wide port with data register located at

location 05h and corresponding data direction register

(TRISA) at 85h. PORTA can operate as either

analog inputs for the internal A/D convertor or as

general purpose digital I/O ports. These inputs are

Schmitt-compatible when used as digital inputs, and

have CMOS drivers as outputs. For example, in a bat-

tery management application, the analog inputs can be

connected to the battery voltage, battery current

through an external sense resistor and external ther-

mistor.

PORTA inputs go through a Schmitt-compatible AND

gate that is disabled when the input is in analog mode.

Refer to Figure 5-1.

Note that bits RA7:RA4 are unimplemented and always

read as ‘0’. Unused inputs should not be left ﬂoating to

avoid leakage currents. All pins have input protection

diodes to VDD and VSS.

EXAMPLE 5-1: INITIALIZING PORTA

CLRF PORTA

;Initialize PORTA by setting

;output data latches

PORTA pins are multiplexed with analog inputs.

ADCFG<1:0> bits control whether these pins are ana-

log or digital through the ADCON1 register (9Fh) as

shown in Section 8.7. When conﬁgured to the digital

mode, reading the PORTA register reads the status of

the pins whereas writing to it will write to the port latch.

When selected as an analog input, these pins will read

as ‘0’s.

BSF

STATUS, RP0 ;Select Bank1

MOVLW 0x0F

;Value used to initialize

;data direction

MOVWF TRISA

;Set RA<3:0> as inputs

;RA<5:4> as outputs

;TRISA<7:6> are always

;read as '0'.

FIGURE 5-1: PORTA BLOCK DIAGRAM

VDD

Data

D

Q

Bus

P

N

I/O

Write

PORTA

CK

D

Q

Write

TRISA

VSS

CK

Q

Analog Input Mode

(determined by

ADCFG)

Read

TRISA

Schmitt

Input Buffer

Q

D

EN

Read

PORTA

To A/D Converter

Note: I/O pins have protection diodes to VDD and VSS.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 27

PIC14000

FIGURE 5-2: PORTA DATA REGISTER

05h

B7

B6

B5

B4

B3

RA3/AN3

R/W

B2

RA2/AN2

R/W

B1

RA1/AN1

R/W

B0

RA0/AN0

R/W

PORTA

-

Read/Write

U

0

U

0

U

0

U

0

POR value 0xh

X

Bit

Name

Function

Unimplemented. Reads as’0’.

B7-B4

B3

-

RA3/AN3

GPIO or analog input. Returns value on pin RA3/AN3 when used as digital input.

When conﬁgured as analog input, reads as’0’.

B2

B1

RA2/AN2

GPIO or analog input. Returns value on pin RA2/AN2 when used as digital input.

When conﬁgured as analog input, reads as’0’. Can be connected to an external

thermistor in a battery management application.

RA1/AN1

RA0/AN0

GPIO or analog input. Returns value on pin RA1/AN1 when used as digital input.

When conﬁgured as analog input, reads as’0’. Can be connected to an external

current sense resistor in a battery management application. This pin has special

input characteristics. See Table 3-1 for additional information.

B0

GPIO or analog input. Returns value on pin RA0/AN0 when used as digital input.

When conﬁgured as analog input, reads as’0’. Normally connected to the battery

voltage (through an external voltage divider if battery voltage exceeds 6.0V).

FIGURE 5-3: SUMMARY OF PORTA REGISTERS

Register

Name

Function

Address

Power-on Reset Value

1

PORTA

PORTA pins when read

PORTA data latch when written

05h

85h

--xx xxxx

1

TRISA

PORTA data direction register

0 = output, 1 = input

--11 1111

ADCON1

PORTA Analog or Digital conﬁguration

9Fh (74/73)

88h (71)

0000 0000

Legend: x = unknown, -= unimplemented, read as a '0'. For reset values of registers in other reset situations refer to Table 14-7.

Note1: The PIC16C71 does not have PORTA or TRISA bit 5, read as ‘0’.

weak pull-up is automatically turned off when the port

pin is conﬁgured as an output. The pull-ups are

disabled on power-on reset.

5.2

PORTC and TRISC

PORTC is a 8-bit wide bidirectional port, with Schmitt

trigger inputs, that serves the following functions

depending on programming:

Four of the PORTC pins, RC<7:4> have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur. In other words, any pin

RC<7:4> conﬁgured as an output is excluded from the

interrupt on change comparison. The input pins of

RC<7:4> are compared with the old value latched on

the last read of PORTC. The “mismatch” outputs of

RC<7:4> are OR’ed together to assert the RCIF ﬂag

(PIR1 register <0>) and cause a CPU interrupt, if

enabled.

• Direct LED drive (PORTC<7:0>).

2

• I C communication lines (PORTC<7:6>), refer to

2

Section 7.0 I C Serial Port.

• Interrupt on change function (PORTC<7:4>),

discussed below and in Section 10.3 Interrupts.

• Hardware charge control for a constant current

switching regulator (PORTC<1:0>). Refer to

Section 9.5.

• Timer0 on RC3

2

Note: If the I C function is enabled, (I CCON

The PORTC data register is located at location 06h and

its data direction register (TRISC) is at 86h.

<5>, address 14h), RC<7:6> are

automatically

excluded

from

the

PORTC <5:0> have weak internal pull-ups (~100uA

typical). A single control bit can turn on all the pull-ups.

This is done by clearing bit RCPU (OPTION <7>). The

interrupt-on-change comparison.

This interrupt can wake the device up from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in one of two ways:

DS40122A-page 28

Preliminary

1995 Microchip Technology Inc.

PIC14000

• Disable the interrupt by clearing RCIE (PIR1<3>)

bit

The TRISC register controls the direction of the RC

pins.

A

‘1’ in each location conﬁgures the

corresponding port pin as an input. This register resets

to all ‘1’s, meaning all PORTC pins are initially inputs.

The data register should be initialized prior to

conﬁguring the port as outputs.

• Read PORTC. This will end mismatch condition.

Then, clear the RCIF bit.

A mismatch condition will continue to set the RCIF bit.

Reading PORTC will end the mismatch condition, and

allow the RCIF bit to be cleared.

Unused inputs should not be left floating to avoid

leakage currents. All pins have input protection diodes

to VDD and VSS.

If the charge control function is enabled, (bit CCAEN

(CHGCON <1>) is set) the RC0/LDACA pin becomes

the charge DAC analog output and should be

connected to an external ﬁlter capacitor. Pin

RC1/CMPA is the output from the charge control

comparator and is used to switch an external power

FET as part of a switching regulator.

EXAMPLE 5-2: INITIALIZING PORTC

CLRF PORTC

;Initialize PORTC data

;

latches before setting

the data direction

register

BSF

MOVLW 0xCF

STATUS, RPO ;Select Bank1

Note: Setting CCAEN changes the deﬁnition of

RC0/LDACA and RC1/CMPA to their

charge control functions, bypassing the

PORTC data and TRISC register settings.

;Value used to initialize

;data direction

;SetRC<3:0> as inputs

MOVWF TRISC

;

RC<5:4> as outputs

RC<7:6> as inputs

PORTC<7:6> also serve multiple functions. These pins

;

2

act as the I C data and clock lines when the I C module

is enabled. They also serve as the serial programming

interface data and clock line for in-circuit programming

of the EPROM.

FIGURE 5-4: BLOCK DIAGRAM OF PORTC <7:4> PINS

RCPU

VDD

P

Data

Bus

D

Q

Write

I/O

PORTC

CK

D

Q

Write

Schmitt

Input Buffer

TRISC

CK

Read

TRISC

Q

D

Read

PORTC

EN

Set

RCIF

D

From other

PORTC pins

Read PORTC

EN

1. I/O pins have protection diodes to VDD and VSS.

2. Port Latch = ‘1’ and TRISC = ‘1’ enables weak pull-up if RCPU= ‘0’ in OPTION register.

2

3. RC7/SDA, RC6/SCL have N-channel pull-ups to VDD which are disabled in I C mode.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 29

PIC14000

FIGURE 5-5: BLOCK DIAGRAM OF PORTC <3:0> PINS

RCPU

VDD

Data

Bus

D

Q

P

Write

PORTC

I/O

CK

D

Q

Write

TRISC

CK

HIBERNATE

Schmitt

Input Buffer

Read

TRISC

Q

D

Read

PORTC

EN

Read PORTC

1. I/O pins have protection diodes to VDD and VSS.

2. Port Latch =’1’ and TRISC =’1’ enables weak pull-up if RCPU=’0’ in OPTION register.

3. If the CCAEN bit in CHGCON is set to’1’, RC0 becomes analog output LDACA, RC1 becomes

CMPA, ignoring the PORTC<1:0> data, TRISC<1:0> register settings.

DS40122A-page 30

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 5-6:

07h

PORTC DATA REGISTER

B7

B6

B5

B4

B3

B2

B1

B0

RC7/SDA RC6/SCL

RC5

RC4

RC3/TOCK

I

RC2

RC1/CMPA RC0/LDAC

A

PORTC

R/W

x

R/W

x

R/W

x

R/W

x

R/W

x

R/W

Read/Write

x

POR value xxh

Bit

Name

Function

2

Synchronous serial data I/O for I C interface. Also is the serial programming data line.

This pin can also serve as a general purpose I/O. If enabled, a change on this pin can

cause a CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in

B7

RC7/SDAA

2

I C mode.

2

Synchronous serial clock for I C interface. Also is the serial programming clock. This pin

B6

B5

RC6/SCLA

RC5

can also serve as a general purpose I/O. If enabled, a change on this pin can cause a

CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in I C mode.

2

LED direct-drive output. This pin can also serve as a GPIO. If enabled, a change on this

pin can cause a CPU interrupt. If enabled, this pin has a weak internal pull-up to VDD.

The Option Register controls pull-up enable.

B4

B3

RC4

LED direct-drive segment output. This pin can also serve as a GPIO. If enabled, a

change on this pin can cause a CPU interrupt. If enabled, this pin has a weak internal

pull-up to VDD. The Option Register controls pull-up enable.

RC3/T0CKI

LED direct-drive segment output. This pin can also serve as a GPIO. If enabled, this pin

has a weak internal pull-up to VDD. TOCKI is enabled as TMR0 clock via the OPTION

register. The Option Register controls pull-up enable.

B2

B1

RC2

LED direct-drive segment output. This pin can also serve as a GPIO. If enabled, this pin

has a weak internal pull-up to VDD. The Option Register controls pull-up enable.

RC1/CMPA

LED direct-drive segment output. This pin can also serve as a GPIO. As a charge

controller, this pin can be used as part of a constant-current switching regulator. If

enabled, this pin has a weak internal pull-up to VDD. The Option Register controls pull-up

enable.

B0

RC0/LDACA LED direct-drive segment output. This pin can also serve as a GPIO. As a charge

controller, this pin can be used as part of a constant-current switching regulator. If

enabled, this pin has a weak internal pull-up to VDD. The Option Register controls pull-up

enable.

U= unimplemented. X = unknown.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 31

PIC14000

5.2.1

TRISC PORTC DATA DIRECTION

REGISTER

This register deﬁnes each pin of PORTC as either an

input or output under software control. A ‘1’ in each

location conﬁgures the corresponding port pin as an

input. This register resets to all ‘1’s, meaning all

PORTC pins are initially inputs. The data register

should be initialized prior to conﬁguring the port as

outputs.

FIGURE 5-7: TRISC REGISTER

B7

B6

B5

B4

B3

TRISC3

R/W

1

B2

TRISC2

R/W

1

B1

TRISC1

R/W

1

B0

TRISC0

R/W

1

87h

TRISC7 TRISC6 TRISC5 TRISC4

TRISC

R/W

1

R/W

1

R/W

1

R/W

1

Read/Write

POR value FFh

Bit

Name

Function

2

B7

TRISC7

Control direction on pin RC7/SDAA (has no effect if I C is enabled):

0 = pin is an output.

1 = pin is an input.

2

B6

TRISC6

Control direction on pin RC6/SCLA (has no effect if I C is enabled):

0 = pin is an output.

1 = pin is an input.

B5

B4

B3

B2

B1

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

Control direction on pin RC5:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RC4:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RC3:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RC2:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RC1/CMPA (has no effect if the charge control function is

enabled):

0 = pin is an output.

1 = pin is an input.

B0

TRISC0

Control direction on pin RC0/LDACA (has no effect if the charge control function is

enabled):

0 = pin is an output.

1 = pin is an input.

U= unimplemented. X = unknown.

DS40122A-page 32

Preliminary

1995 Microchip Technology Inc.

PIC14000

5.3

PORTD and TRISD

PORTD is an 8-bit port that may be used for general

purpose I/O. Four pins can be conﬁgured as analog

inputs. For example, they could be used to measure

individual cell voltages in rechargeable Lithium battery

packs. Together with the analog channels of PORTA, 8

analog inputs are supplied.

FIGURE 5-8: BLOCK DIAGRAM OF PORTD <7:4> PINS

VDD

P

Data

Bus

D

Q

Write

PORTD

I/O

CK

N

D

Q

Write

TRISD

VSS

CK

Analog Input Mode

(determined by

ADCFG)

Read

TRISA

ST

Input Buffer

D

Q

EN

Read

PortD

To A/D Converter

Note: I/O pins have protection diodes to VDD and VSS.

FIGURE 5-9: BLOCK DIAGRAM OF PORTD<3:0> PINS

Data

Bus

D

Q

I/O

Write

PORTD

CK

D

Q

Schmitt

Input Buffer

Write

TRISD

CK

Read

TRISD

Q

D

Read

PORTD

EN

1. I/O pins have protection diodes to VDD and VSS.

Read PORTD

2. If CCBEN is set to’1’, RD2 becomes CMPB, RD3

becomes LDACB, ignoring the PORTD<3:2> data,

TRISD<1:0> register settings.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 33

PIC14000

FIGURE 5-10: PORTD DATA REGISTER

08h

B7

B6

B5

B4

B3

B2

B1

B0

RD3/LDA RD2/CMP RD1/SD RD0/SC

PORTD

RD7/AN7 RD6/AN6 RD5/AN5 RD4/AN4

CB

R/W

x

B

R/W

x

AB

R/W

x

LB

R/W

x

Read/Write

R/W

x

R/W

x

R/W

x

R/W

x

POR value xxh

Bit

Name

RD7/AN7

Function

GPIO or analog input. Returns value on pin RD7/AN7 when used as digital

input. When configured as analog input, reads as ’0’.

B7

B6

GPIO or analog input. Returns value on pin RD6/AN6 when used as digital

input. When configured as analog input, reads as ’0’. In a battery manage-

ment application, connected to an external thermistor (channel B) for du-

al-pocket charge control.

RD6/AN6

GPIO or analog input. Returns value on pin RD5/AN5 when used as digital

input. When configured as analog input, reads as ’0’. In a battery manage-

ment application, connected to an external current sense resistor (channel

B) for dual-pocket charge control. This pin has special input characteristics.

See Table 3-1 for additional information.

B5

B4

RD5/AN5

RD4/AN4

GPIO or analog input. Returns value on pin RD4/AN4 when used as digital

input. When configured as analog input, reads as ’0’. In a battery manage-

ment application, connected to the battery voltage (channel B) for du-

al-pocket charge control.

This pin can serve as a GPIO. In a dual-pocket charge controller application,

this pin can be used as part of a constant-current switching regulator for a

2nd battery pack.

B3

B2

B1

RD3/LDACB

RD2/CMPB

RD1/SDAB

This pin can serve as a GPIO. In a dual-pocket charge controller application,

this pin can be used as part of a constant-current switching regulator for a

2nd battery pack.

2

Alternate synchronous serial data I/O for I C interface enabled by setting

2

the I CSEL bit in the MISC register. This pin can also serve as a general

purpose I/O. This pin has an N-channel pull-up which can be disabled.

2

Alternate synchronous serial clock for I C interface, enabled by setting the

2

I CSEL bit in the MISC register. Also is the serial programming clock. This

B0

RD0/SCLB

pin can also serve as a general purpose I/O. If enabled, a change on this

pin can cause a CPU interrupt. This pin has an N-Channel pull-up which can

be disabled.

Legend: U = unimplemented, read as ’0’. x = unknown.

DS40122A-page 34

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 5-11: TRISD REGISTER

88h

B7

B6

B5

B4

B3

TRISD3

R/W

1

B2

TRISD2

R/W

1

B1

TRISD1

R/W

1

B0

TRISD0

R/W

1

TRISD

TRISD7 TRISD6 TRISD5 TRISD4

Read/Write

POR value FFh

R/W

1

R/W

1

R/W

1

R/W

1

Bit

Name

Function

Control direction on pin RD7/AN7:

0 = pin is an output.

1 = pin is an input.

B7

B6

B5

B4

TRISD7

TRISD6

TRISD5

TRISD4

Control direction on pin RD6/AN6:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RD5/AN5:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RD4/AN4:

0 = pin is an output.

1 = pin is an input.

Control direction on pin RD3/LDACB (has no effect if the charge enable bit CCBEN

is set to ’1’):

0 = pin is an output.

1 = pin is an input.

B3

TRISD3

TRISD2

Control direction on pin RD2/CMPB (has no effect if the charge enable bit CCBEN

is set to ’1’):

0 = pin is an output.

1 = pin is an input.

B2

B1

Control direction on pin RD1/SDAB:

0 = pin is an output.

1 = pin is an input.

TRISD1

TRISD0

Control direction on pin RD0/SCLB:

0 = pin is an output.

B0

1 = pin is an input.

TABLE 5-1:

RESET CONDITION FOR REGISTERS

MCLR reset during

- normal operation

- SLEEP

Wake-up from SLEEP

through interrupt

Wake up from SLEEP

WDT time-out during nor- through WDT time-out

mal operation

Register

PORTD

TRISD

Address

08h

Power-on Reset

xxxx xxxx

uuuu uuuu

1111 1111

uuuu uuuu

88h

1111 1111

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 35

PIC14000

If the charge control function is enabled, (bit CCBEN

(CHGCON <5>) is set) the RD3/LDACB pin becomes

the charge DAC analog output and should be

connected to an external ﬁlter capacitor. Pin

RD2/CMPB is the output from the charge control

comparator and is used to switch an external power

FET as part of a switching regulator (Section 9.5).

5.4

I/O Programming Considerations

5.4.1

BI-DIRECTIONAL I/O PORTS

Reading the port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. Some instructions operate internally as

read-modify-write. The BCF and BSF instructions, for

example, read the register into the CPU, execute the bit

operation, and write the result back to the register.

Caution must be used when these instructions are

applied to a port with both inputs and outputs deﬁned.

For example, a BSF operation on bit5 of PORTC will

cause all eight bits of PORTC to be read into the CPU.

Then the BSF operation takes place on bit5 and

PORTC is written to the output latches. If another bit of

PORTC is used as a bi-directional I/O pin (say bit0) and

it is deﬁned as an input at this time, the input signal

present on the pin itself would be read into the CPU and

re-written to the data latch of this particular pin, over-

writing the previous content. As long as the pin stays in

the input mode, no problem occurs. However, if bit0 is

switched into output mode later on, the content of the

data latch may now be unknown.

Note: Setting CCBEN changes the deﬁnition of

RD3/LDACB and RD2/CMPB to their

charge control functions, bypassing the

PORTD data and TRISD register settings.

PORTD<1:0> also serve multiple functions. These pins

2

act as the I C data and clock lines when the I C module

is enabled.

The TRISD register controls the direction of the RD

pins.

A

’1’ in each location conﬁgures the

corresponding port pin as an input. This register resets

to all ’1’s, meaning all PORTD pins are initially inputs.

The data register should be initialized prior to

conﬁguring the port as outputs.

Unused inputs should not be left floating to avoid

leakage currents. All pins have input protection diodes

to VDD and VSS.

A pin actively outputting a LOW or HIGH should not be

driven from external devices at the same time in order

to change the level on this pin (“wire-or”, “wire-and”).

The resulting high output currents may damage the

chip.

EXAMPLE 5-3: INITIALIZING PORTD

CLRF PORTD

;Initialize PORTD data

;

latches before setting

the data direction

register

Example 5-4 shows the effect of two sequential read

modify write instructions (ex. BCF, BSF, etc.) on an I/O

Port.

BSF

STATUS, RPO ;Select Bank1

MOVLW 0xFF

;Value used to initialize

;data direction

EXAMPLE 5-4: READ MODIFY WRITE

INSTRUCTIONS ON AN

MOVWF TRISD

;SetRD<7:0> as inputs

I/O PORT

;Initial PORT settings: PORTC<7:4> Inputs

;

PORTC<3:0> Outputs

;PORTC<7:6> have external pull-up and are not

;connected to other circuitry

;

PORT latch PORTpins

---------- ----------

BCF PORTC, 7

BCF PORTC, 6

BSF STATUS,RP0

BCF TRISC, 7

BCF TRISC, 6

;01pp pppp 11pppppp

;10pp pppp 11pppppp

;

;10pp pppp 11pppppp

;10pp pppp 10pppppp

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

DS40122A-page 36

Preliminary

1995 Microchip Technology Inc.

PIC14000

5.4.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be

valid at the beginning of the instruction cycle.

Therefore, care must be exercised if a write operation

is followed by a read operation on the same I/O port.

The sequence of instructions should be such to allow

the pin voltage to stabilize before the next instruction

which causes that port to be read into the CPU is

executed. Otherwise, the previous state of that pin may

be read into the CPU rather than the new state. When

in doubt, it is better to separate these instructions with

a NOP or another instruction not accessing this I/O

port.

FIGURE 5-12: SUCCESSIVE I/O OPERATION

Example showing write to PORTC followed by immediate read. Some delays in settling may cause “old”

Port data to be read, especially at higher clock frequencies. Data setup time = (0.25 Tcyc- Tpd), where

Tcyc = instruction cycle time.

Q1 | Q2 | Q3 | Q4

Q1 | Q2 | Q3 | Q4 Q1 | Q2

|

Q3

|

Q4 Q1 | Q2 | Q3 | Q4

PC + 3

PC

PC + 2

NOP

PC + 1

MOVWF PORTC

Write to PORTC

MOVF PORTC, W

Read PORTC

NOP

Pin values

RC<x>

Port pin sampled

here

Execute NOP

Execute MOVF

PORTC, W

Execute MOVWF

PORTC

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 37

PIC14000

NOTES:

DS40122A-page 38

Preliminary

1995 Microchip Technology Inc.

PIC14000

The Timer0 module has the following features:

6.0

TIMER MODULES

• 8-bit timer

The PIC14000 contains two general purpose timer

modules, Timer0 (TMR0) and the Watchdog Timer

(WDT). The A/D capture timer/counter is described in

the A/D section.

• Readable and writable (ﬁle address 01h)

• 8-bit software programmable prescaler

• Interrupt on overﬂow from FFh to 00h

The Timer0 module is identical to the Timer0 module of

the PIC16C7X enhanced core products. It is an 8-bit

overﬂow counter.

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module.

The Timer0 module will increment every instruction

cycle (without prescaler). If TMR0 is written, increment

is inhibited for the following two cycles (Figure 6-2 and

Figure 6-3. The user can compensate by writing an

adjusted value to TMR0.

The Timer0 module has a programmable prescaler

option. This prescaler can be assigned to either the

Timer0 module or the Watchdog Timer (WDT). PSA

(OPTION <3>) assigns the prescaler, and PS2:PS0

(OPTION <2:0>) determines the prescaler value.

Timer0 can increment at the following rates: 1:1 (when

prescaler assigned to Watchdog Timer), 1:2, 1:4, 1:8,

1:16, 1:32, 1:64, 1:128, 1:256.

FIGURE 6-1: TIMER0 AND WATCHDOG TIMER BLOCK DIAGRAM

Timer0

Data bus

8

FOSC/4

0

1

PSout

1

0

Sync with

Internal

clocks

TMR0

RC3/T0CKI

PSout

Set T0IF

Interrupt on

Overﬂow

(2 cycle delay)

T0SE

PSA

T0CS

Prescaler/

Postscaler

Local

8-bit Counter

Oscillator

0

1

8

18 mS

Timer

3

8-to-1 MUX

PS2:PS0

PSA

Enable

1

0

PSA

WDT

Time-out

Watchdog Timer

WDT

Enable Bit

Note: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

Hibernate

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 39

PIC14000

6.0.1

TIMER0 (TMR0) INTERRUPT

service routine before re-enabling this interrupt. The

Timer0 module interrupt cannot wake the processor

from SLEEP since the timer is shut off during SLEEP.

The timing of the TIMER0 interrupt is shown in

Figure 6-4.

TMR0 interrupt is generated when the Timer0 module

timer overﬂows from FFh to 00h. This overﬂow sets the

T0IF bit. The interrupt can be masked by clearing bit

T0IE (INTCON <5>). Flag bit T0IF (INTCON <2>) must

be cleared in software by the TMR0 module interrupt

FIGURE 6-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

Fetch

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

T0

T0+1

T0+2

NT0

NT0+1

NT0+2

TMR0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

FIGURE 6-3: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

NT0

TMR0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

FIGURE 6-4: TIMER0 (TMR0) INTERRUPT TIMING

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

Q1 Q2 Q3

Q4

OSC1

CLKOUT(3)

TMR0 timer

FEh

1

FFh

1

00h

01h

02h

T0IF bit

(INTCON<2>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC +1

0004h

0005h

Instruction

fetched

Inst (PC)

Inst (PC+1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

executed

Inst (PC-1)

Dummy cycle

Inst (PC)

Note 1: T0IF interrupt ﬂag is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.

3: CLKOUT is available only in HS oscillator mode.

DS40122A-page 40

Preliminary

1995 Microchip Technology Inc.

PIC14000

6.1.2

TIMER0 INCREMENT DELAY

6.1

Using Timer0 with External Clock

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

When an external clock input is used for Timer0, it must

meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of TMR0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

6.2

Prescaler

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2Tosc (and a small RC delay of 20 ns)

and low for at least 2Tosc (and a small RC delay of

20 ns).

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a post-scaler for the Watchdog

Timer (Figure 6-1). For simplicity, this counter is being

referred to as “prescaler” throughout this data sheet.

Note that there is only one prescaler available which is

mutually exclusive between the Timer0 module and the

Watchdog Timer. Thus, a prescaler assignment for the

Timer0 module means that there is no prescaler for the

Watchdog Timer, and vice-versa.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4Tosc (and a small RC delay of 40 ns)

divided by the prescaler value. The only requirement

on T0CKI high and low time is that they do not violate

the minimum pulse width requirement of 10 ns.

Bit PSA and PS2:PS0 (OPTION<3:0>) determine the

prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the Timer0 module (e.g.,CLRF 1, MOVWF 1,

BSF 1,x) will clear the prescaler. When assigned to

WDT, a CLRWDT instruction will clear the prescaler

along with the Watchdog Timer. The prescaler is not

readable or writable.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

EXT CLOCK INPUT OR

misses sampling

PRESCALER OUT (NOTE 2)

EXT CLOCK/PRESCALER

OUTPUT AFTER SAMPLING

(note 3)

INCREMENT TMR0 (Q4)

T0

T0 + 1

T0 + 2

TMR0

Notes:

1. Delay from clock input change to TMR0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).

Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4 tosc max.

2. External clock if no prescaler selected, Prescaler output otherwise.

3. The arrows indicate the points in time where sampling occurs.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 41

PIC14000

6.2.1

SWITCHING PRESCALER ASSIGNMENT

To change prescaler from the WDT to the TMR0

module use the sequence shown in Example 6-2. This

precaution must be taken even if the WDT is disabled.

The prescaler assignment is fully under software

control, i.e., it can be changed “on the ﬂy” during

program execution. To avoid an unintended device

EXAMPLE 6-2: CHANGING PRESCALER

RESET,

the

following

instruction

sequence

(WDT→TMR0)

(Example 6-1) must be executed when changing the

prescaler assignment from TMR0 to WDT.

CLRWDT

;Clear WDT and

;prescaler

BSF

STATUS, RP0

EXAMPLE 6-1: CHANGING PRESCALER

MOVLW

B'xxxx0xxx' ;Select TMR0, new

;prescale value and

;clock source

OPTION

STATUS, RP0

(TMR0→WDT)

BCF

STATUS,RP0 ;Bank 0

MOVWF

BCF

CLRF

BSF

TMR0

;Clear TMR0 & Prescaler

STATUS, RP0 ;Bank 1

CLRWDT

;Clears WDT

MOVLW B'xxxx1xxx' ;Select new prescaler

MOVWF OPTION

;value

BCF STATUS, RP0 ;Bank 0

TABLE 6-1:

SUMMARY OF TMR0 REGISTERS

Register Name

Function

Address

Power-on Reset Value

TMR0

Timer/counter register

01h

81h

xxxx xxxx

1111 1111

OPTION

Conﬁguration and prescaler assign-

ment bits for TMR0. PIC.

INTCON

TMR0 overﬂow interrupt ﬂag and

mask bits.

0Bh

0000 000x

Legend: x = unknown,

Note 1: For reset values of registers in other reset situations refer to Table 10-4.

TABLE 6-2:

REGISTERS ASSOCIATED WITH TIMER0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

TIMER0 TIMER/COUNTER

0Bh/8Bh INTCON

GIE

PEIE

—

T0IE

T0CS

—

T0IF

PS2

—

81h

87h

OPTION

TRISC

RCPU

T0SE

PSA

PS1

PS0

TRISC7 TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

Legend: — = Unimplemented or reserved locations

Shaded boxes are not used by Timer0 module

DS40122A-page 42

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

In the I C interface protocol each device has an

address. When a master wishes to initiate a data

transfer, it ﬁrst transmits the address of the device that

it wishes to talk to. All devices “listen” to see if this is

their address. Within this address, a bit speciﬁes if the

master wishes to read from or write to the slave device.

The master and slave are always in opposite modes

7.0

INTER-INTEGRATED CIRCUIT

SERIAL PORT (I C )

2

The I C module is a serial interface useful for

communicating with other peripheral or microcontroller

devices. These peripheral devices may be serial

EEPROMs, shift registers, display drivers, A/D

2

converters, etc. The I C module is compatible with the

(transmitter/receiver) of operation during

a data

following interface speciﬁcations:

transfer. They may operate in either of these two states:

2

• Inter-Integrated Circuit (I C)

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver

• System Management Bus (SMBus)

• Access.bus

In both cases the master generates the clock signal.

2

Note: The I C module on PIC14000 only

The output stages of the clock (SCL) and data (SDA)

lines must have an open-drain or open-collector in

order to perform the wired-AND function of the bus.

External pull-up resistors are used to ensure a high

level when no device is pulling the line down. The

number of devices that may be attached to the I C bus

is limited only by the maximum bus loading speciﬁca-

tion of 400 pF.

2

supports I C mode. This is different from

the standard module used on the

PIC16C7X family, which supports both I C

and SPI modes. Caution should be exer-

cised to avoid enabling SPI mode on the

PIC14000

2

This section provides an overview of the Inter-IC(I C)

bus. The I C bus is a two-wire serial interface

2

7.0.1

INITIATING AND TERMINATING DATA

TRANSFER

developed by the Philips Corporation. The original

speciﬁcation, or standard mode, was for data transfers

of up to 100 Kbps. An enhanced speciﬁcation, or fast

mode, supports data transmission up to 400 Kbps.

Both standard mode and fast mode devices will

inter-operate if attached to the same bus.

During times of no data transfer (idle time), both the

clock line (SCL) and the data line (SDA) are pulled high

through the external pull-up resistors. The START and

STOP determine the start and stop of data

transmission. The START is deﬁned as a high to low

transition of SDA when SCL is high. The STOP is

deﬁned as a low to high transition of SDA when SCL is

high. Figure 7-1 shows the START and STOP. The

master generates these conditions for starting and ter-

minating data transfer. Due to the deﬁnition of the

START and STOP, when data is being transmitted the

SDA line can only change state when the SCL line is

low.

2

The I C interface employs a comprehensive protocol to

ensure reliable transmission and reception of data.

When transmitting data, one device is the “master”

(generates the clock) while the other device(s) acts as

the “slave”. All portions of the slave protocol are

implemented in the I C module’s hardware, while

portions of the master protocol will need to be

addressed in the PIC14000 software. Table 7-1 deﬁnes

some of the I C bus terminology. For additional infor-

mation on the I C interface speciﬁcation, please refer to

the Philips Corporation document “The I C-bus and

2

how to use it”. The order number for this document is

98-8080-575.

2

FIGURE 7-1: I C START AND STOP CONDITIONS

SDA

S

P

SCL

Change

of Data

Allowed

Stop

Condition

Start

Condition

Change

of Data

Allowed

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 43

PIC14000

2

FIGURE 7-2: I CSTAT: I C PORT STATUS REGISTER

U

_

U

_

R

P

R

S

R

2

Register:

Address:

POR value:

I CSTAT

94h

W: Writable bit

R: Readable bit

D/A

R/W

UA

BF

00h U: Unimplemented, read as ‘0’

bit0

bit7

BF: Buffer full

Receive

1 = Receive complete, I CBUF is full

2

0 = Receive not complete, I CBUF is empty

Transmit

2

1 = Transmit in progress, I CBUF is full

0 = Transmit complete, I CBUF is empty

2

UA: Update Address (10-bit I C slave mode only)

1 = Indicate that the user needs to update the address in the I CADD

register.

2

0 = Address does not need to be updated.

R/W: Read/write bit information

This bit holds the R/W bit information received following the last address

match. This bit is only valid during the transmission.

The user may use this bit in software to determine whether transmission

or reception is in progress.

1 = Read

0 = Write

S: Start bit

2

This bit is cleared when the I C module is disabled (I CEN is cleared)

1 = Indicates that a start bit has been detected last. This bit is 0 on

reset.

0 = Start bit was not detected last

P: Stop bit

2

This bit is cleared when the I C module is disabled (I CEN is cleared)

1 = Indicates that a stop bit has been detected last.

0 = Stop bit was not detected last

D/A: Data/Address bit

1 = Indicates that the last byte received was data

0 = Indicates that the last byte received was address

Unimplemented, read as ‘0’.

DS40122A-page 44

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

FIGURE 7-3: I CCON: I C PORT CONTROL REGISTER

R/W

R/W R/W R/W

R/W

2

WCOL I²COV I²CEN CKP I²CM3 I²CM2 I²CM1 I²CM0

Register:

Address:

POR value:

I CCON

14h

00h

W: Writable bit

R: Readable bit

U: Unimplemented, read as ‘0’

bit7

bit0

I²CM<3:0>: I²C mode select

0110 = I²C slave mode, 7-bit address

0111 = I²C slave mode, 10-bit address

1011 = I²C master mode support enabled (slave idle)

1110 = I²C slave mode, 7-bit address with master mode support

enabled

1111 = I²C slave mode, 10-bit address with master mode support

enabled

0000

0001

0010

0011

0100

0101

These combinations are illegal and

should NEVER be used.

CKP: Clock polarity select.

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch)

Note: Used to ensure data setup time

I²CEN: I²C enable

1 = Enables the serial port and conﬁgures SDA and SCL pins as serial

port pins.

0 = Disables serial port and conﬁgures these pins as I/O port pins.

I²COV: Receive overﬂow ﬂag.

1 = A byte is received while the I²CBUF is still holding the previous

byte. I²COV is a don't care in transmit mode. I²COV must be

cleared in software.

WCOL: Write collision detect.

1 = the I²CBUF register is written while it is still transmitting the previ-

ous word.

Must be cleared in software.

0 = No collision

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 45

PIC14000

2

TABLE 7-1:

I C BUS TERMINOLOGY

Term

Description

Transmitter

Receiver

Master

The device that sends the data to the bus

The device that receives the data from the bus

The device which initiates the transfer, generates the clock, and terminates the transfer

The device addressed by a master

Slave

Multi-master

More than one master device in a system. These masters can attempt to control the bus

at the same time without corrupting the message

Arbitration

Procedure that ensures that only one of the master devices will control the bus. This

ensures that the transfer data does not get corrupted.

Synchronization

Procedure where the clock signals of two or more devices are synchronized.

2

7.0.2

ADDRESSING I C DEVICES

FIGURE 7-4: I C 7-BIT ADDRESS FORMAT

MSb

LSb

There are two address formats. The simplest is the 7-bit

address format with a R/W bit (Figure 7-4). The

address is the most signiﬁcant seven bits of the byte.

R/W ACK

S

2

For example when loading the I CADD register, the

slave address

Sent by

Slave

least signiﬁcant bit is a “don’t care”. The more complex

is the 10-bit address with a R/W bit (Figure 7-5). For

10-bit address format, two bytes must be transmitted

with the ﬁrst ﬁve bits specifying this to be a 10-bit

address.

S

R/W

ACK

Start Condition

Read/Write pulse

Acknowledge

2

FIGURE 7-5: I C 10-BIT ADDRESS FORMAT

S 1 111 0 A9 A8 RW ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

sent by slave

= 0 for write

S

- Start Condition

R/W - Read/Write Pulse

ACK - Acknowledge

DS40122A-page 46

Preliminary

1995 Microchip Technology Inc.

PIC14000

7.0.3

TRANSFER ACKNOWLEDGE

before allowing the clock to start. This wait state

technique can also be implemented at the bit level.

Figure 7-7 shows a data transfer waveform.

All data must be transmitted per byte, with no limit to

the number of bytes transmitted per data transfer. After

each byte, the slave-receiver generates an

acknowledge bit (ACK). This is shown in Figure 7-6.

When a slave-receiver doesn’t acknowledge the slave

address or received data, the master must abort the

transfer. The slave must leave SDA high so that the

master can generate the STOP (Figure 7-1).

Figure 7-8 and Figure 7-9 show master-transmitter and

master-receiver data transfer sequences.

2

FIGURE 7-6: I C SLAVE-RECEIVER

ACKNOWLEDGE

Data

Output by

If the master is receiving the data (master-receiver), it

generates an acknowledge signal for each received

byte of data, except for the last byte. To signal the end

of data to the slave-transmitter, the master does not

generate an acknowledge. The slave then releases the

SDA line so the master can generate the STOP. The

master can also generate the STOP during the

acknowledge pulse for valid termination of data

transfer.

Transmitter

not acknowledge

Data

Output by

Receiver

acknowledge

SCL from

Master

1

2

8

9

S

Start

Clock pulse for

acknowledgement

Condition

If the slave needs to delay the transmission of the next

byte, holding the SCL line low will force the master into

a wait state. Data transfer continues when the slave

releases the SCL line. This allows the slave to move

the received data or fetch the data it needs to transfer

2

FIGURE 7-7: SAMPLE I C DATA TRANSFER

SDA

MSB

acknowledgement

signal from receiver

acknowledgement

signal from receiver

byte complete.

interrupt with receiver

clock line held low while

interrupts are serviced

SCL

S

9

8

9

1

2

7

3 • 8

1

P

Stop

Condition

Start

Condition

ACK

Address

R/W

Wait

Data

ACK

State

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 47

PIC14000

When a master does not wish to relinquish the bus (by

generating a STOP condition), a repeated START (Sr)

must be generated. This condition is identical to the

START (SDA goes high-to-low while SCL is high), but

occurs after a data transfer acknowledge pulse (not the

bus-free state). This allows a master to send

“commands” to the slave and then receive the

requested information or to address a different slave

device. This sequence is shown in Figure 7-10.

FIGURE 7-8: MASTER - TRANSMITTER SEQUENCE

For 7-bit address:

For 10-bit address:

S Slave Address R/W A1 Slave Address A2

S Slave Address R/W A DATA A DATA A/A

P

first 7 bits

second byte

"0" (write)

data transferred

(n bytes - acknowledge)

(write)

A master transmitter addresses a slave receiver with a

7-bit address. The transfer direction is not changed.

Data A

Data A/A P

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

S = START condition

P = STOP condition

From master to slave

From slave to master

A master transmitter addresses a slave receiver with a

10-bit address.

FIGURE 7-9: MASTER - RECEIVER SEQUENCE

For 7-bit address:

For 10-bit address:

S Slave Address R/W A1 Slave Address A2

S Slave Address R/W A DATA A DATA

A

P

first 7 bits

second byte

(read)

data transferred

(n bytes - acknowledge)

(write)

A master reads a slave immediately after the first byte.

Sr

Slave Address R/W A3 Data A

first 7 bits

Data A P

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

S = START condition

(read)

From master to slave

From slave to master

A master transmitter addresses a slave receiver with a

10-bit address.

P = STOP condition

FIGURE 7-10: COMBINED FORMAT

(read or write)

(n bytes + acknowledge)

Sr

S Slave Address R/W A DATA A/A

Slave Address R/W A DATA A/A P

Direction of transfer

may change at this point

(write)

Sr = repeated

START condition

(read)

Transfer direction of data and acknowledgement bits depends on R/W bits.

Combined Format:

S Slave Address R/W A Slave Address A Data A

first 7 bits second byte

Data A/A Sr Slave Address R/W A Data A

Data A P

first 7 bits

(write)

(read)

Combined format - A master addresses a slave with a 10-bit address, then transmits

data to this slave and reads data from this slave.

A = acknowledge (SDA low)

A = not acknowledge (SDA high)

S = START condition

P = STOP condition

From master to slave

From slave to master

DS40122A-page 48

Preliminary

1995 Microchip Technology Inc.

PIC14000

7.0.4

MULTI-MASTER OPERATION

FIGURE 7-11: MULTI-MASTER

ARBITRATION (2 MASTERS)

2

The I C protocol allows a system to have more than

one master. This is called multi-master. When two or

more masters try to transfer data at the same time,

arbitration and synchronization occur.

transmitter 1 loses arbitration

DATA 1- SDA

DATA 1

DATA 2

SDA

7.0.4.1

ARBITRATION

Arbitration takes place on the SDA line, while the SCL

line is high. The master which transmits a high when

the other master transmits a low loses arbitration

(Figure 7-11) and turns off its data output stage. A

master which lost arbitrating can generate clock pulses

until the end of the data byte where it lost arbitration.

When the master devices are addressing the same

device, arbitration continues into the data.

SCL

2

FIGURE 7-12: I C CLOCK

SYNCHRONIZATION

Masters that also incorporate the slave function, and

have lost arbitration must immediately switch over to

slave-receiver mode. This is because the winning

master-transmitter may be addressing it.

start counting

HIGH period

wait

state

CLK

1

Arbitration is not allowed between:

• A repeated START

counter

reset

CLK

2

• A STOP and a data bit

• A repeated START and a STOP

Care needs to be taken to ensure that these conditions

do not occur.

SCL

7.0.4.2

CLOCK SYNCHRONIZATION

Clock synchronization occurs after the devices have

started arbitration. This is performed using

a

wired-AND connection to the SCL line. A high to low

transition on the SCL line causes the concerned

devices to start counting off their low period. Once a

device clock has gone low, it will hold the SCL line low

until its SCL high state is reached. The low to high

transition of this clock may not change the state of the

SCL line, if another device clock is still within its low

period. The SCL line is held low by the device with the

longest low period. Devices with shorter low periods

enter a high wait-state, until the SCL line comes high.

When the SCL line comes high, all devices start

counting off their high periods. The ﬁrst device to

complete its high period will pull the SCL line low. The

SCA line high time is determined by the device with the

shortest high period. This is shown in the Figure 7-12.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 49

PIC14000

2

FIGURE 7-13: I C BLOCK DIAGRAM

Internal

data bus

Read

Write

RC6/SCLA

2

I CBUF

SCK

SDA

RC7/SDAA

Shift

4:2

MUX

clock

2

I CSR

RD0/SCLB

RD1/SDAB

MSB

Match Detect

Addr_Match

2

I CADD

Set, Reset

S, P bits

(I CSTAT Reg)

Start and

Stop bit detect

2

• I C Slave mode (10-bit address), with

master-mode support

7.1

I²C Operation

2

The I C module in I C mode fully implements all slave

functions, and provides support in hardware to facilitate

software implementations of the master functions. The

2

• I C Master mode, slave is idle

2

Selection of any I C mode with the I CEN bit set, forces

the SCL and SDA pins to be open collector, provided

these pins are set to inputs through the TRISC bits.

2

I C module implements the standard and fast mode

speciﬁcations as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the

RC6/SCLA pin, which is the I C clock, and the

RC7/SDAA pin which acts as the I C data. The users

must conﬁgure these pins as inputs or outputs through

2

The I CSTAT register gives the status of the data

2

transfer. This information includes detection of a

START or STOP bit, speciﬁes if the received byte was

data or address, if the next byte is the completion of

10-bit address, and if this will be a read or write data

2

the TRISC<7:6> bits. A block diagram of the I C mod-

ule in I C mode is shown in Figure 7-13. The I C mod-

2

transfer. The I CSTAT register is read only.

2

ule functions are enabled by setting the I C Enable

2

The I CBUF is the register to which transfer data is

written to or read from. The I CSR register shifts the

data in or out of the device. In receive operations, the

I CBUF and I CSR create a double buffered receiver.

This allows reception of the next byte before reading

the last byte of received data. When the complete byte

is received, it is transferred to the I CBUF and the I CIF

is set. If another complete byte is received before the

2

(I CEN) bit in the I CCON register (14h, bit 5).

2

The I C module has ﬁve registers for I C operation.

These are the:

2

•

I C Control Register (I CCON)

2

I C Status Register (I CSTAT)

2

• Serial Receive / Transmit Buffer (I CBUF)

2

•

I C Shift Register (I CSR) - Not directly accessi-

I CBUF is read, a receiver overﬂow has occurred and

the I COV bit (I CCON<6>) is set.

2

ble

2

• Address Register (I CADD)

2

The I CADD register holds the slave address. In 10-bit

2

The I CCON register (14h) allows control of the I C

operation. Four mode selection bits (I CCON<3:0>)

allow one of the following I C modes to be selected:

mode, the user needs to write the high byte of the

address (1 1 1 1 0 A9 A8 0). Following the high byte

address match, the low byte of the address needs to be

loaded (A7-A0).

2

• I C Slave mode (7-bit address)

2

• I C Slave mode (10-bit address)

2

• I C Slave mode (7-bit address), with mas-

ter-mode support

DS40122A-page 50

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

7.1.1

SLAVE MODE

In this case, the I CSR value is not loaded into the

2

I CBUF, but the I CIF bit is set. Table 7-2 shows what

happens when a data transfer byte is received, given

the status of the BF and I COV bits. The shaded boxes

show the conditions where user software did not

properly clear the overﬂow condition. The BF ﬂag is

cleared by reading the I CBUF register while the

In slave mode, the SCL and SDA pins must be

conﬁgured as inputs (TRISC <7:6> are set). The I C

module will override the input state with the output data

when required (slave-transmitter).

2

When an address is matched or the data transfer from

an address match is received, the hardware

automatically will generate the acknowledge (ACK)

pulse, and then load the I CBUF with the received

value in the I CSR.

2

I COV bit is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I C speciﬁcation as well as the requirement of the I C

module is shown in the AC timing speciﬁcations.

2

There are two conditions that will cause the I C module

not to give this ACK pulse. These are if either (or both)

occur:

• the Buffer Full (BF) bit was set before the transfer

was received, or

2

• the Overﬂow (I COV) bit was set before the trans-

fer was received.

TABLE 7-2:

DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data Transfer

2

is Received

Set I CIF bit

2

Generate ACK Pulse

BF

I COV

I CSR-> I CBUF

(I C interrupt if enabled)

0

1

0

1

Yes

No

Yes

No

Yes

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 51

PIC14000

2

7.1.1.1

ADDRESSING

4. Receive second (low) byte of address (I CIF, BF

and UA are set).

2

Once the I C module has been enabled, the I C waits

for a START to occur. Following the START, the 8-bits

2

5. Update I CADD with ﬁrst (high) byte of address

(clears UA, if match releases SCL line).

2

are shifted into the I CSR. All incoming bits are

sampled with the rising edge of the clock (SCL) line.

The I CSR<7:1> is compared to the I CADD register.

The address is compared on the falling edge of the

eighth clock (SCL) pulse. If the addresses match, and

2

6. Read I CBUF (clears BF) and clear I CIF

7. Receive Repeated START.

2

8. Receive ﬁrst (high) byte of address (I CIF and

BF are set).

2

the BF and I COV bits are clear, the following things

9. Read I CBUF (clears BF) and clear I CIF.

happen:

7.1.1.2 RECEPTION

2

•

I CSR loaded into I CBUF

• Buffer Full (BF) bit is set

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the I CSTAT

2

• ACK pulse is generated

2

register is cleared. The received address is loaded into

•

I C Interrupt Flag (I CIF) is set (interrupt is

2

the I CBUF.

generated if enabled (I CIE set) on falling edge of

ninth SCL pulse.

When the address byte overﬂow condition exists then

no acknowledge (ACK) pulse is given. An overﬂow

In 10-bit address mode, two address bytes need to be

received by the slave (Figure 7-5). The ﬁve most

signiﬁcant bits (MSbs) of the ﬁrst address byte specify

if this is a 10-bit address. The R/W bit (bit 0) must

specify a write, so the slave device will received the

second address byte. For a 10-bit address the ﬁrst byte

would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are

the two MSbs of the address. The sequence of events

for 10-bit address are as follows, with steps 7-9 for

slave-transmitter:

2

condition is deﬁned as either the BF bit (I CSTAT<0>)

2

is set or the I COV bit (I CCON<6>) is set

(Figure 7-14).

2

An I CIF interrupt is generated for each data transfer

2

byte. The I CIF bit must be cleared in software, and the

2

I CSTAT register is used to determine the status of the

byte. In master mode with slave enabled, three inter-

rupt sources are possible. Reading BF, P and S will

indicate the source of the interrupt.

2

1. Receive ﬁrst (high) byte of address (I CIF, BF

Caution: BF is set after receipt of eight bits and auto-

2

and UA are set).

matically cleared after the I CBUF is read.

2

However, the ﬂag is not actually cleared

until receipt of the acknowledge pulse. Oth-

erwise extra reads appear to be valid.

2. Update I CADD with second (low) byte of

address (clears UA and releases SCL line).

2

3. Read I CBUF (clears BF) and clear I CIF.

2

FIGURE 7-14: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W=0

Receiving Address

Receiving Data

ACK

9

ACK

9

A7 A6 A5 A4

SDA

SCL

A3 A2 A1

D5

D2

D0

8

D5

D2

D0

8

D7 D6

D4 D3

D7 D6

D4 D3

D1

7

D1

7

3

7

1

2

4

9

5

4

3

6

5

6

1

2

3

6

1

2

4

8

5

P

S

I²CIF (PIR1<3>)

BF (I²CSTAT<0>)

Bus Master

terminates

transfer

Cleared in software

I²CBUF is read

I²COV (I²CCON<6>)

I²COV is set

because I²CBUF is

still full. ACK is not sent.

DS40122A-page 52

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

7.1.1.3

TRANSMISSION

A I CIF interrupt is generated for each data transfer

2

byte. The I CIF bit must be cleared in software, and the

I CSTAT register is used to determine the status of the

byte. The I CIF bit is set on the falling edge of the ninth

clock pulse.

2

When the R/W bit of the address byte is set and an

address match occurs, the R/W bit of the I CSTAT

2

register is set. The received address is loaded into the

2

I CBUF The ACK pulse will be sent on the ninth bit, and

As a slave-transmitter, the ACK pulse from the

master-receiver is latched on the rising edge of the

ninth SCL input pulse. If the SDA line was high (not

ACK), then the data transfer is complete. The slave

then monitors for another occurrence of the START bit.

If the SDA line was low (ACK), the transmit data must

the SCL pin is held low. The transmit data must be

2

loaded into the I CBUF register, which also loads the

2

I CSR register. Then the SCL pin should be enabled by

2

setting the CKP bit (I CCON<4>). The eight data bits

are shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time (Figure 7-15).

2

be loaded into the I CBUF register, which also loads

2

the I CSR register. Then the SCL pin should be

2

enabled by setting the CKP bit (I CCON<4>).

2C

FIGURE 7-15: I WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address

R/W = 1

ACK

Transmitting Data

ACK

9

SDA

SCL

A7 A6 A5 A4 A3 A2 A1

D7 D6 D5 D4 D3 D2 D1 D0

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

P

SCL held low

while CPU

responds to I²CPIF

Data in

sampled

I²CPIF (PIR1<3>)

BF (I²CSTAT<0>)

From I²CPIF interrupt

service routine

cleared in software

I²CBUF is written in software

CKP (I²CCON<4>)

Set bit after writing to I2CBUF

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 53

PIC14000

7.1.2

MASTER MODE

7.1.3

MULTI-MASTER MODE

Master mode operation is supported by interrupt

generation on the detection of the START and STOP.

The STOP(P) and START(S) bits are cleared from a

In multi-master mode, the interrupt generation on the

detection of the START and STOP allows the

determination of when the bus is free. The STOP (P)

and START (S) bits are cleared from a reset or when

2

reset or when the I C module is disabled. Control of the

2

I C bus may be taken when the P bit is set, or the bus

the I C module is disabled. Control of the I C bus may

be taken when the P bit is set, or the bus is idle and

both the S and P bits are cleared. When the bus is

is idle and both the S and P bits are cleared.

In master mode, the SCL and SDA lines are

manipulated by changing the corresponding

TRISC<7:6> bits to an output (cleared). The output

level is always low, regardless of the value(s) in

PORTC<7:6>. So when transmitting data, a “1” data bit

must have the TRISC<7> bit set (input) and a “0” data

bit must have the TRISC<7> bit cleared (output). The

same scenario is true for the SCL line with the

TRISC<6> bit.

2

busy, enabling the I C interrupt will generate the

interrupt when the STOP occurs.

In multi-master operation, the SDA line must be

monitored to see if the signal level is the expected

output level. This check only needs to be done when a

high level is output. If a high level is expected and low

level is present, the device needs to release the SDA

and SCL lines (set TRISC<7:6>). There are two stages

where this arbitration can be lost, these are:

2

The following events will cause the I C interrupt Flag

2

(I CIF) to be set (I C interrupt if enabled):

• Address Transfer

• Data Transfer

• START

• STOP

When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address

transfer stage, the device may being addressed. If

addressed an ACK pulse will be generated. If

arbitration was lost during the data transfer stage, the

device will need to re-transfer the data at a later time.

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

2

slave mode idle (I CM3...I CM0 = 1011b) or with the

slave active. When both master and slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

2

TABLE 7-3:

Address

REGISTERS ASSOCIATED WITH I C OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0B/8Bh

0Ch

8Ch

13h

INTCON

PIR1

GIE

PEIE

—

T0IE

—

r

T0IF

RCIF

RCIE

r

2

WUIF

PBIF

PBIE

I CIF

ADIF

ADIE

OVFIF

OVFIE

2

PIE1

WUIE

—

I CIE

2

I CBUF

I C Serial Port Receive Buffer/Transmit Register

2

93h

I CADD

I C mode Synchronous Serial Port (I C mode) Address Register

2

14h

I CCON

WCOL

—

I CON

I CEN

CKP

P

I CM3

I CM2

I CM1

I CM0

2

94h

I CSTAT

—

D/A

S

R/W

UA

BF

Legend: — = Unimplemented location, read as ’0’

r

indicates reserved locations, default is POR value and should not be overwritten with any value

2

Note: Shaded boxes are not used by the I C module.

DS40122A-page 54

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

FIGURE 7-16: OPERATION OF THE I C IN IDLE_MODE, RCV_MODE OR XMIT_MODE

IDLE_MODE (7-bit):

if (Addr_match)

{

Set interrupt;

if (R/W = 1)

{

}

Send ACK = 0;

set XMIT_MODE;

else if (R/W = 0) set RCV_MODE;

}

RCV_MODE:

if ((I2CBUF=Full) OR (I²COV = 1))

{

Set I²COV;

Do not acknowledge;

}

{

else

transfer I²CSR → I²CBUF;

send ACK = 0;

}

Receive 8-bits in I²CSR;

Set interrupt;

XMIT_MODE:

While ((I2CBUF = Empty) AND (CKP=0)) Hold SCL Low;

Send byte;

Set interrupt;

if (ACK Received = 1)

{

}

End of transmission;

Go back to IDLE_MODE;

else if (ACK Received = 0) Go back to XMIT_MODE;

IDLE_MODE (10-Bit):

If (High_byte_addr_match AND (R/W = 0))

{

PRIOR_ADDR_MATCH = FALSE;

Set interrupt;

if ((I2CBUF = Full) OR ((I2COV = 1))

{

Set I2COV;

Do not acknowledge;

}

{

else

Set UA = 1;

Send ACK = 0;

While (I2CADD not updated) Hold SCL low;

Clear UA = 0;

Receive Low_addr_byte;

Set interrupt;

Set UA = 1;

If (Low_byte_addr_match)

{

PRIOR_ADDR_MATCH = TRUE;

Send ACK = 0;

while (I2CADD not updated) Hold SCL low;

Clear UA = 0;

Set RCV_MODE;

}

else if (High_byte_addr_match AND (R/W = 1)

if (PRIOR_ADDR_MATCH)

{

send ACK = 0;

set XMIT_MODE;

}

else PRIOR_ADDR_MATCH = FALSE;

}

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 55

PIC14000

7.1.4

SMBus AND ACCESS.bus

CONSIDERATIONS

7.1.4.1

SMHOG STATE MACHINE

While SMHOG = 1 do

do

PIC14000 is compliant with the SMBus speciﬁcation

published by Intel and ACCESS.bus speciﬁcations.

Some key points to note regarding the differences

between the two bus speciﬁcations and how it pertains

to the PIC14000 hardware are listed below:

if SMHOG = 0 then exit

2

(while)

ing until it’s serviced

; if I C int. pending do noth-

2

until I CIF = 0

do

if SMHOG = 0 then exit

• SMBus has ﬁxed input voltage thresholds.

PIC14000 I/O buffers have programmable levels

that can be selected to be compatible with both

SMBus threshold levels via the SMBus and

SPGND bits in the MISC register.

2

(while)

; wait for I C interrupt

until I CIF =1

2

do

if SMHOG = 0 then exit (while)

2

• PIC14000 IOL levels and VOL levels have been

set to meet the worst-case of both the SMBus and

ACCESS bus speciﬁcations. Speciﬁcally,

VOL = 0.4V and IOL = 6 mA.

until (SCL = 0 or I CIF = 0)

2

if I CIF = 1 then

do

hold SCL low

2

until I CIF = 0 or SMHOG=0

• A mechanism to stretch the I C clock time has

if SMHOG = 0 then exit (while)

forever

while end

been implemented to support SMBus slave

transactions. The SMHOG bit in the MISC register

allows hardware to automatically force and hold

2

the I C clock line low when a data byte has been

received. This prevents the SMBus master from

overﬂowing the receive buffer in instances where

the microcontroller may be to busy servicing

2

higher priority tasks to respond to a I C module

interrupt. Or, if the microcontroller is in SLEEP

mode and needs time to wake-up and respond to

2

the I C interrupt

DS40122A-page 56

Preliminary

1995 Microchip Technology Inc.

PIC14000

the current A/D timer value into the 16-bit capture

register.

8.0

ANALOG MODULES FOR A/D

CONVERSION

• An interrupt is generated to the CPU if enabled.

8.1

Overview

Note: The A/D timer continues to run following a

capture event.

PIC14000 includes analog components to create a pre-

cision slope A/D converter that is used to translate bat-

tery voltage, current and temperature into digital values

for both battery monitoring and charging control. A

slope conversion method is especially suited to

applications in which a relatively lengthy time may be

taken for conversion (several milliseconds) to obtain the

beneﬁts of noise reduction through signal averaging.

This can lead to greater resolutions and accuracies than

achievable with a successive-approximation converter

for the same cost. PIC14000 uses a digital integration

method to eliminate many of the inaccuracies and com-

plexity associated with an analog integrator.

The maximum A/D timer count is 65,536. Its frequency

is ﬁxed to the oscillator frequency, as determined by the

on-chip crystal or IN oscillator. At a 4 MHz oscillation

frequency, the maximum conversion time is 16.38 ms

for a full count. A typical conversion should complete

before full-count is reached. A timer overﬂow ﬂag is set

once the timer rolls over (FFFFh to 0000h), and an

interrupt is sent to the CPU, if enabled.

End-user calibration is greatly simpliﬁed or eliminated

by making use of the on-chip EPROM. Internal

component values are measured at factory ﬁnal test

and stored in the memory for use by the application

ﬁrmware.

The slope A/D converter (Figure 8-1) includes:

•

Comparator

Periodic conversion cycles should be performed on the

bandgap reference to compensate for A/D component

drift. Measurements for the reference voltage count are

equated to the voltage value stored into EPROM during

calibration. All other channel measurements are

compensated for by ratioing the actual count with the

bandgap count any multiplying by the bandgap voltage

value stored in EPROM. In addition, a bias/zeroing

network is provided on chip for the current sense input.

The result is, the zero point of the current provides

very high accuracies at low current values, where

most needed. Since all measurements are relative

to the reference, offset voltages inherent in the

comparator are cancelled out. The combination of

slope-conversion with automatic zeroing, plus

factory calibration allow A/D resolutions of 16-bits with

accuracies exceeding 12 bits.

• 4-bit current DAC

• 16-channel analog mux

• 16-bit A/D capture timer

The 16 analog channels can be assigned to:

• External voltage or external reference

• Temperature (internal)

• Temperature (external)

• External current

• Internal bandgap reference

• SREFHI

• SREFLO

• Charge/wake-up controller DAC outputs

For a battery management application, external voltage

would be the battery voltage and the external current

would be the charge/discharge current of the battery

pack.

Most of the analog components used in the conversion

and the A/D timer clock are automatically disabled dur-

ing idle periods for maximum power savings. Several

other power-saving modes can be enabled via software

and/or hardware control (Section 10.7).

Each channel is converted independently by means of

a slope conversion method using a single precision

comparator. The current DAC feeds an external 0.1µF

(nominal) capacitor to generate the ramp voltage used

in the conversion.

8.3

A/D Capture Timer (ADTMR) Module

8.2

Conversion Process

The A/D capture timer (ADTMR) is used as the

reference counter for theA/D conversion(s) and is com-

prised of a 16-bit up timer, which is incremented every

oscillator cycle. ADTMR is reset to 0000h by a

power-up reset; otherwise the software must reset it

after each conversion. A separate 16-bit capture

register (ADCAP) is used to capture the ADTMR

count if an A/D capture event occurs (see below). Both

the A/D timer and capture register are readable and

writable. The low byte of the A/D timer (ADTMRL) is

accessed at location 0Eh while the high byte

(ADTMRH) is accessed at location 0Fh. Similarly, the

low byte of the A/D capture register (ADCAP) is

accessed at location 15h, and the high byte is located

at 16h.

These are the steps to perform data conversion:

• Set ADRST (ADCON0<2>), which stops the timer

and discharges the ramp capacitor to ground.

• Be sure to set ADRST for a minimum of 200 µs.

• After conversion takes place, reset ADRST

through software, it will allow the capture timer to

begin counting and the ramp capacitor to begin

charging.

• The capture timer is an up-counter, and must be

reset by software to 0000h before each conver-

sion.

• When the ramp voltage exceeds the analog input,

the comparator output changes from high to low.

• This transition causes a capture event and copies

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 57

PIC14000

Caution: Reading or writing the ADTMR register

during an A/D conversion cycle can pro-

duce unpredictable results and is not

recommended.

for clearing the ADCIF ﬂag prior to the next conversion

cycle. Note that this interrupt can only occur once per

conversion cycle.

In a capture timer overﬂow condition, no valid capture

event occurs (comparator does not trip). In this case,

the timer rolls over from FFFFh to 0000h, and a capture

overﬂow ﬂag (OVFIF) is asserted (PIR1<0>). The timer

continues to increment following a timer overﬂow. A

CPU interrupt can be generated if bit OVFIE (PIE1<0>)

is programmed to ’1’ (interrupt enabled). In addition, the

Global Interrupt Enable (GIE, INTCON<7>) must also

be set. Software is responsible for clearing the OVFIF

ﬂag prior to the next conversion cycle.

The correct sequence for writing the ADTMR register is

as follows:

Action

Result

1. Write the HI byte

ﬁrst.

This stops the timer from

counting

After it is written, the timer

will start counting automati-

cally.

2. Write the LOW

byte last.

Reversing this order will yield unpredictable results.

During conversion one of two events will occur:

To initiate a conversion you must do three things:

1. Set the ADRST bit (ADCON0<1>) in software.

The hardware responds by stopping the A/D

timer (ADTMR) and discharging the external

capacitor connected to the CDAC pin. The tim-

ing of the reset is determined by the software to

allow enough time for the ramp capacitor to fully

discharge. The minimum reset pulse width

requirement for a 0.1uF ramp capacitor is 200

micro-seconds.

1. capture event, or

2. timer overﬂow

In a capture event, the comparator trips when the slope

voltage on the CDAC output exceeds the input voltage,

causing the comparator output to transition from high to

low. This causes a transfer of the current timer count to

the capture register and setting of the ADCIF ﬂag

(PIR1<1>). A CPU interrupt will be generated if bit

ADCIE (PIE1<1>) is programmed to ’1’ (interrupt

enabled). In addition, the Global Interrupt Enable (GIE,

INTCON<7>) must also be set. Software is responsible

2. Reset ADTMR in software. ADTMR will not

count while ADRST is set.

3. Reset the ADRST bit to low (0). This internal

hold/discharge is released allowing the capture

time to count and the ramp capacitor to begin

charging. Figure 8-2 shows a typical A/D con-

version cycle.

DS40122A-page 58

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 8-1: A/D BLOCK DIAGRAM

OSC1

0

1

ADOFF

WRITE_TMR

ADRST

Internal

Oscillator

Clock

Stop

Logic

FOSC

(Conﬁguration Fuse)

15

14

13

12

11

GND

AMUX

Note 2

GND

RA7/AN7

RA6/AN6

RA5/AN5

RA4/AN4

ADOFF

10

ADTMRH

A/D Capture

ADCAPH

ADTMRL

ADCAPL

Interrupt

Overﬂow

(OVFIF)

9

Analog

Mux

LogDAC B

LogDAC A

Temp sensor

SREFLO

SREFHI

Bandgap Ref.

RA3/AN3

8

~ 1 kohm

7

6

5

4

3

2

1

0

RA0

Internal

Data

RA2/AN2

RA1/AN1

Bus

A/D

RA0/AN0

Capture Interrupt

(ADIF)

4

ADCS<3:0>

~2.5uA~5uA~10uA~20uA

ADOFF

CDAC

ADDAC <3:0> *

0.1µF

(nominal)

~100 Ω

ADRST (ADCON0, bit 1)

Note 1

4-Bit Current DAC

Note 1:

Note 2:

All current sources are disabled if ADRST = ’1’

Approximately 5 microsecond time constant

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 59

PIC14000

FIGURE 8-2: EXAMPLE A/D CONVERSION CYCLE

CAPTURE

CLK

ADTMR INCREMENTS

ADRST

ADCON0, b1

ADTMR

COUNT

XX+1 XX+2 XX+3

XX

XX+8 XX+9

COMPARE

CDAC

ADCIF,

PIR1, b1

(must be cleared by software)

Capture

Reg

XX

XX+8

FIGURE 8-3: A/D CAPTURE TIMER (LOW BYTE)

0Eh

B7

b7

R/W

0

B6

b6

R/W

0

B5

b5

R/W

0

B4

b4

R/W

0

B3

b3

R/W

0

B2

b2

R/W

0

B1

b1

R/W

0

B0

b0

R/W

0

ADTMRL

Read/Write

POR value 00h

FIGURE 8-4: A/D CAPTURE TIMER (HIGH BYTE)

0Fh

B7

B6

b14

R/W

0

B5

b13

R/W

0

B4

b12

R/W

0

B3

b11

R/W

0

B2

b10

R/W

0

B1

b9

R/W

0

B0

b8

R/W

0

ADTMRH

Read/Write

POR value 00h

b15

R/W

0

FIGURE 8-5: A/D CAPTURE REGISTER (LOW BYTE)

15h

B7

b7

R/W

0

B6

b6

R/W

0

B5

b5

R/W

0

B4

b4

R/W

0

B3

b3

R/W

0

B2

b2

R/W

0

B1

b1

R/W

0

B0

b0

R/W

0

ADCAPL

Read/Write

POR value 00h

FIGURE 8-6: A/D CAPTURE REGISTER (HIGH BYTE)

16h

B7

B6

B5

b13

R/W

0

B4

b12

R/W

0

B3

b11

R/W

0

B2

b10

R/W

0

B1

b9

R/W

0

B0

b8

R/W

0

ADCAPH

Read/Write

POR value 00h

b15

R/W

0

b14

R/W

0

Legend: U= unimplemented. X = unknown.

DS40122A-page 60

Preliminary

1995 Microchip Technology Inc.

PIC14000

8.4

A/D Comparator

8.5

Analog Mux

A precision comparator is the heart of the slope A/D

converter. The positive terminal of the comparator is

connected to the output of an analog mux. The negative

terminal is connected to the external 0.1 µF (nominal)

ramp capacitor. An RC low-pass ﬁlter is connected

between the output of the analog mux and the compar-

ator input. The nominal time-constant for the RC ﬁlter is

5 µs.

A total of 15 channels are internally multiplexed to the

single A/D comparator positive input. Four

conﬁguration bits ADCS<3:0> (ADCON0< 7:4>) select

the channel to be converted. These channels may be

assigned to external thermistor, voltage, current, inter-

nal

thermistor,

internal

bandgap

voltage,

charge/wake-up control DAC outputs, SREFHI and

SREFLO from the slope reference divider, and ground.

Additional channels are available depending on system

requirements. Refer to Table 8-1.

TABLE 8-1:

A/D CHANNEL SELECT DECODE

ADCS(3:0)

A/D CHANNEL

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RA0/AN0 pin

RA1/AN1 pin

RA2/AN2 pin

RA3/AN3 pin

Bandgap voltage (internal)

Slope reference SREFHI (internal)

Slope reference SREFLO (internal)

Internal temperature sensor

Charge control/wake-up detect logDAC A output

Charge control/wake-up detect logDAC B output

RD4/AN4 pin

RD5/AN5 pin

RD6/AN6 pin

RD7/AN7 pin

Tied to analog ground

For example in a dual pocket battery charger application, the following pins can be assigned to measure voltages as

follows:

• RA0/AN0 pin (Battery A voltage)

• RA1/AN1 pin (Current sense A voltage)

• RA2/AN2 pin (External thermistor A voltage)

• RD4/AN4 pin (Battery B voltage)

• RD5/AN5 pin (Current sense B voltage)

• RD6/AN6 pin (External thermistor B voltage)

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 61

PIC14000

The 4-bit DAC output is tied to the CDAC pin and is

used to charge an external 0.1uF capacitor for

establishing the slope voltage to the A/D comparator.

(Refer to Figure 8-1.) This capacitor should have a low

voltage-coefﬁcient for optimum results. The CDAC

output must be discharged at the beginning of each

conversion cycle by asserting bit ADRST (ADCON0

<1>) for at least 200 µs to allow a complete discharge.

Asserting bit ADRST temporarily disables the ramp

DAC current sources internally. Current ﬂow begins

with the de-assertion of ADRST. The DAC output

current will be stable no more than 10 µs after

de-asserting ADRST.

8.6

Programmable Slope Control DAC

Four conﬁguration bits ADDAC<3:0> (ADCON1 <7:4>)

are used to control a 4-bit current DAC for generating

the comparison slope voltage to the A/D comparator. It

allows slope compensation for voltage, frequency and

capacitor tolerance variations. It also ensures that the

dynamic range of the inputs is not compromised by the

slope voltage. The current values range from 0 to

37.5 µA (nominal) in 2.5 µA increments. The

intermediate values of the 4-bit DAC current source are

as follows:

TABLE 8-2:

A/D CDAC CURRENT DAC

OUTPUT DECODE

DAC CURRENT

ADDAC(3:0)

OUTPUT

0

OFF - all current

sources disabled

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.5 µA

5 µA

7.5 µA

10 µA

12.5 µA

15 µA

17.5 µA

20 µA

22.5 µA

25 µA

27.5 µA

30 µA

32.5 µA

35 µA

37.5 µA

DS40122A-page 62

Preliminary

1995 Microchip Technology Inc.

PIC14000

8.7

A/D Control Registers

Two A/D control registers are provided on PIC14000 to

control the conversion process. These are ADCON0

(1Fh) and ADCON1 (9Fh). Both registers are readable

and writable.

TABLE 8-3:

1Fh

A/D CONTROL AND STATUS REGISTER 1

B7

B6

B5

B4

B3

-

B2

B1

B0

ADCON1

ADCS3

ADCON0

ADCS2 ADCS1 ADCS0

AMUXOE

ADRST

ADZERO

Read/Write

R/W

0

R/W

0

R/W

0

R/W

0

U

0

R/W

0

R/W

1

R/W

0

POR value 02h

Bit

Name

ADCS3

Function

ADCS2

ADCS1

ADCS0

A/D Channel Selects. Refer to the Table 8-1 for decoding.

B7-B4

B3

B2

-

Unimplemented. Read as ’0’.

Analog Mux Output Enable

1 = Tie AMux Output to AN0 pin

0 = AN0 pin normal

AMUXOE

A/D Reset Control Bit

B1

ADRST

1 = Reset the A/D Capture Timer, discharge CDAC capacitor

0 = Normal operation (A/D running)

A/D Zero Select Control.

B0

ADZERO

1 = Enable zeroing operation on current sense input.

0 = Disable zeroing operation on current sense input.

TABLE 8-4:

A/D CONTROL AND STATUS REGISTER 2

9Fh

B7

B6

B5

B4

B3

B2

B1

B0

ADCON1

Read/Write

POR value 00h

ADDAC3 ADDAC2 ADDAC1 ADDAC0 ACFG3 ACFG2 ACFG1

ACFG0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

Name

Function

ADDAC3

ADDAC2

ADDAC1

ADDAC0

B7-B4

A/D Current DAC Selects. Refer to Table 8-2 for decoding.

ACFG3

ACFG2

PORTD Configuration Selects

(See Table 8-5 for decoding)

B3-B2

ACFG1

ACFG0

PORTA Configuration Selects

(See Table 8-5 for decoding)

B1-B0

TABLE 8-5:

PORTA AND PORTD CONFIGURATION SELECT DECODE

ACFG<1:0>

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3

ACFG<3:2>

RD4/AN4

RD5/AN5

RD6/AN6

RD7/AN7

0 0

0 1

1 0

1 1

A

D

A

D

A

D

A

D

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 63

PIC14000

The PIC14000 analog peripherals form a slope voltage

converter. Choosing the correct ramp capacitor for the

CDAC pin (pin 22) is required to achieve the desired res-

olution and conversion time. The equation for selecting

the ramp capacitor value is:

8.8

A/D Speed, Resolution and Capacitor

Selection

The conversion time for the A/D converter on the

PIC14000 can be calculated using the equation:

Capacitor = (conversion time in seconds) X (current

DAC in amps) / (full scale in volts)

Conversion Time = (1/Fosc) x 2(N bits of resolution)

where Fosc is the oscillator frequency

Table 8-6 provides example capacitor values for the

desired A/D resolution, conversion time, and full scale

voltage measurement.

N is the numbers of bits resolution desired

Therefore at 4MHz, the conversion time for 16 bits is

16.384 msec. Conversely, it is 256 µsec for 10 bits.

TABLE 8-6:

RAMP CAPACITOR SELECTION (EXAMPLES FOR FULL SCALE OF 3.5V AND 1.5V)

A/D

Resolution

(Bits)

Conversion Time

Full Scale

A/D Current

DAC

(µamps)

Ramp Cap

Ramp Capacitor

Nearest Standard

Value

(Seconds)

0.016384

0.004096

0.001024

(Volts)

3.5

(Farads)

1.17E-07

2.93E-08

7.31E-09

16

14

12

25

.1uF

3.5

.022uF

6800pF

3.5

16

14

12

0.016384

0.004096

0.001024

1.5

25

2.73E-07

6.83E-08

1.71E-08

.022uF

6800pF

1500pF

Note: Assumes FOSC of 4MHz and current DAC value of 25 µA.

8.10

Current Reference

8.9

Precision Voltage Reference

PIC14000 contains a current reference that generates

a 1uA (nominal) current reference accurate to within

25% absolute, and less than 4% over temperature and

voltage. The output of the current reference is used to

generate the current sources for the comparators,

DACs, temperature sensor, and the current sense

biasing network.

The bandgap reference circuit is used to generate a

precision voltage reference accurate to within 1% after

calibration. The output of the bandgap reference is

used to reference the A/D and the low-voltage detector.

The bandgap reference is channel 4 of the analog mux

and is selected using conﬁguration bits ADCS<3:0>.

Refer to Section 9.0 for additional details of

temperature and current sense bias network.

DS40122A-page 64

Preliminary

1995 Microchip Technology Inc.

PIC14000

A current zeroing technique is used to increase

accuracy of the current measurement. Two matched

pass gates are used in the zeroing process. One gate

disconnects the current sense input from the bias net-

work. The second gate grounds the input. This simu-

lates a zero current condition. An A/D reading is taken

(zeroed). Subsequent readings are calculated relative

to this zero count from the A/D. This “zeroing” of the

current provides very high accuracies at low current

values, where it is most needed.

9.0

OTHER ANALOG MODULES

PIC14000 has additional analog hardware modules to

optimize performance for battery management

applications. These include:

• bandgap voltage reference (refer to Section 8.9)

• current reference (refer to Section 8.10)

• charge controller/current ﬂow detector

• internal temperature sensor

• voltage regulator control

For capturing short duration current pulses, such as in

GSM digital cellular phone applications, an optional ﬁl-

ter capacitor may be connected to the SUM pin to

ground. This forms an RC network with the internal 100

kΩ (nominal) bias resistor to act as a DC averaging ﬁl-

ter. The capacitor size can be adjusted for the target

time constant. A switch is included between the zero-

ing/bias network and the SUM pin. This switch is closed

during A/D sampling periods and is automatically

opened during the zeroing operation (i.e., if ADZERO =

’1’). If not required in the system, this pin should be left

no-connected (ﬂoating).

• supply voltage divider

The analog circuitry can be shut off during idle periods

for power savings. Refer to Section 10.7 for additional

information on the PIC14000 power-down modes.

9.1

Current Bias and Zeroing Network

Current is measured at the RA1/BATI input by

connecting an external sense resistor in series with the

battery. For example, in a battery pack exhibiting charge

and discharge currents of ±5A and using a 0.05 Ω

sense resistor, results in voltages of -0.25V to +0.25V

at the pin. Acurrent source and resistor are used to bias

this voltage into a range usable by the comparator

(0.5V nominal bias). The nominal value of the bias

current source is 5 µA and the resistor is 100 kΩ.

The current bias source can be turned off by setting the

BIASOFF bit (SLPCON register 8Fh <4>) to ’1’. This

also forces the ZERO and SUM switches open, so the

AN1/RA1 pin can continue to be used as

general-purpose analog input.

a

Note: The minimum voltage permissible at the

RA1/BATI pin is -0.3V. The input protection

diode(s) will begin to turn on beyond -0.3V,

introducing signiﬁcant error in the current

measurement. Under no conditions should

the pin voltage fall below -0.5V. The

suggested system design is to orient the

battery polarity so that a negative voltage

occurs during charge, not discharge cycles.

Figure 9-1 shows the current bias and zero network in

simpliﬁed form.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 65

PIC14000

FIGURE 9-1: CURRENT BIAS AND ZEROING NETWORK

BIASOFF

5 µA (nominal)

SUM

(SLPCON, <4>)

VDD

Input Protection

Diodes

External

ADZERO**

Capacitor

(Optional)

Closed if BIASOFF bit is ’1’

< 300Ω

RA1/AN1

To A/D mux,

100 kΩ

Charge controller

(nominal)

Open if BIASOFF bit is ’1’

ADZERO

(ADCON0 <6>)

** SUM switch is automatically opened during zeroing (i.e., if ADZERO = ’1’) or if

the BIASOFF bit in the SLPCON register is set to ’1’.

temperature range. If more precise temperature

monitoring is necessary, an external thermistor should

be used.

9.2

Slope Reference Divider

A bandgap reference and ampliﬁer with a resistor

divider is used to compensate for the zero offset of the

A/D converter. There may be a slight time lag (less than

10 µs) between de-assertion of the internal reset

condition and the beginning of the ramp capacitor

charge. Firmware must be able to determine this time

lag (offset) and compensate for A/D measurements.

The voltage divider provides two tap points for this pur-

pose, named SREFHI and SREFLO. The value of

SREFHI is approximately 9 times the value of

SREFLO. The value of SREFHI is approximately 1.23V

and is used for the slope detect upper limit in the A/D

conversions. The trip point SREFLO is approximately

0.14V and is used for the slope detect lower trip point.

By converting the SREFHI and SREFLO slope detect

points the slope ramp offset can be calculated. The

ﬁrmware can then use this information to compensate

the A/D and optimize accuracy. This offset delay is

subtracted from subsequent conversion outputs to

arrive at the true digital count corresponding to the

analog input voltage.

Note:

In most cases it is recommended that an

external temperature sensor (thermistor)

be used for fast charge control. The

external thermistor should be afﬁxed

directly to the battery pack for reducing

temperature response time and improving

accuracy.

9.4

Voltage Regulator Output

For systems where the battery voltage (during

charging) exceeds the maximum VDD limit of the device

(6.0V), a control for an inexpensive external voltage

regulator (FET + resistor) is included to reduce system

cost. The VREG output pin can be connected to an

external N-channel FET, which is in series with the

battery voltage and the VDD pin. Its nominal output

voltage is 6 V. This will provide a VDD of about 5 V, after

the voltage drop across the FET. Figure 9-2 shows a

typical circuit connection of the voltage regulator.

9.3

Internal Temperature Sensor

An internal temperature sensor will be used as one

input to the A/D. The temperature sensor is able to

measure resolutions to 0.1°C and absolute

temperature to +/- 2.5°C over the 0° to 70°C

DS40122A-page 66

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 9-2: VOLTAGE REGULATOR (EXAMPLE FOR A BATTERY PACK APPLICATION)

PIC14000

1-10 MΩ typical

Battery +

Terminal

VREG

10

N-FET

VDD

9

Optional External

Voltage Regulator

(Not required for battery voltages

below 6.0 V)

current sense voltage equal to the charge DAC output

voltage effectively controlling the amount of charging

current seen by the battery. The status of the charge

control/current-ﬂow detect comparators can be read via

the CCOMPA and CCOMPB bits (CHGCON<2:6>).

These are read-only bits and writes to these locations

have no effect.

9.5

Charge Controller / Current Flow

Detector

PIC14000 includes much of the hardware required to

form a constant-current switching regulator for battery

charging. This circuit can also be used to sense current

ﬂow and generate an interrupt to the CPU. This

interrupt is able to wake the device from SLEEP mode

as described in Section 10.7.1. The circuit is comprised

of two DACs and comparator channels A and B. Chan-

nel A is reserved for the charge control function, while

both channels are used for the current ﬂow detector to

detect both positive and negative current. Each DAC

output is tied to one of the comparators as shown in

Figure 9-7. Two registers LDACA (9Bh) and LDACB

(9Ch) are used to select the DAC output voltages.

Note: The CCAEN bit does not affect the charge

DAC voltages nor comparator. These cir-

cuits are disabled by setting the CWUOFF

bit in the SLPCON register (8Fh).

The two DACs are built using two resistor ladders, cur-

rent source and analog multiplexers. One of the resistor

ladders is used for a coarse adjustment of the output

voltage. The second ladder is used to ﬁne tune the out-

put from the ﬁrst ladder. The DAC voltage granularity

and range varies depending on the value of the LDx-

SEL<7:0> bits in LDACA and LDACB registers. LDx-

SEL<7:3> selects the output from the coarse ladder

according to Table 9-1, while LDxSEL<2:0> are for the

ﬁne-tune adjustment (Table 9-2).

To enable hardware charge control, the CCAEN bit

(CHGCON<1>) must be set. Setting CCAEN to ’1’

causes the pins RC0/LDACA and RC1/CMPA to

assume their charge control functions. In this situation,

pin RC0/LDACA becomes the analog output from DAC

"A" and is normally connected to an external ﬁlter

capacitor. Pin RC1/CMPA becomes the output from the

charge control comparator and is used to switch an

external power FET to control the battery charge cur-

rent. The charge controller also includes a comparator

that examines the current sense voltage (after the bias

network). During charging, the circuit acts to make the

The coarse resistor ladder is matched to the current

sense bias resistor so that the center point of the ladder

is approximately equal to zero current ﬂow. This allows

the DAC to control or monitor both charge and

discharge current ﬂow. This ladder is comprised of

32 taps, and is divided into two regions. The ﬁrst region

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 67

PIC14000

is deﬁned for controlling trickle or topping charge rates

and has a range of ±50 mV. The resolution in this region

is 5 mV and the range is ±50mV. This corresponds to

currents of 100 mA resolution up to 1A with an external

0.05 Ω sense resistor. The second region is deﬁned for

fast charge applications. The resolution here is 50 mV

(1A) with a maximum range of±0.35V (+/- 7A, with 0.05

Ω resistor).

The ﬁne-tune resistor ladder has 8 taps, and is used to

divide the buffered output voltage from the coarse

ladder. This yields a minimum DAC voltage resolution

of approximately 0.714 mV or 14.3 mA with a 0.05 Ω

sense resistor.

Note: The current granularity and ranges men-

tioned assume an external 0.05 ohm

sense resistor. These values will change

depending on the actual sense resistor

value used.

TABLE 9-1:

DIGITAL DAC DECODE (COURSE ADJUST)

NOMINAL

SENSE CURRENT RANGE (with

OUTPUT VOLTAGE

0.05 ohm sense resistor)-mA

RANGE (V)

LDxSEL<7:3>

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.5000 - 0.5050

0.5050 - 0.5100

0.5100 - 0.5150

0.5150 - 0.5200

0.5200 - 0.5250

0.5250 - 0.5300

0.5300 - 0.5350

0.5350 - 0.5400

0.5400 - 0.5450

0.5450 - 0.5500

0.5500 - 0.6000

0.6000 - 0.6500

0.6500 - 0.7000

0.7000 - 0.7500

0.7500 - 0.8000

0.8000 - 0.8500

0.4950 - 0.5000

0.4900 - 0.4950

0.4850 - 0.4900

0.4800 - 0.4850

0.4750 - 0.4800

0.4700 - 0.4750

0.4650 - 0.4700

0.4600 - 0.4650

0.4550 - 0.4600

0.4500 - 0.4550

0.4000 - 0.4500

0.3500 - 0.4000

0.3000 - 0.3500

0.2500 - 0.3000

0.2000 - 0.2500

0.1500 - 0.2000

0 - 100

100 - 200

200 - 300

300 - 400

400 - 500

500 - 600

600 - 700

700 - 800

800 - 900

900 - 1000

1000 - 2000

2000 - 3000

3000 - 4000

4000 - 5000

5000 - 6000

6000 - 7000

0 - (100)

(100) - (200)

(200) - (300)

(300) - (400)

(400) - (500)

(500) - (600)

(600) - (700)

(700) - (800)

(800) - (900)

(900) - (1000)

(1000) - (2000)

(2000) - (3000)

(3000) - (4000)

(4000) - (5000)

(5000) - (6000)

(6000) - (7000)

DS40122A-page 68

Preliminary

1995 Microchip Technology Inc.

PIC14000

For example, if a topping off current of 340 mA was

required, LDxSEL<7:4> would be set to a value of

’00011010’ binary. This yields a coarse range of

300-400 mA. The ﬁne-tune setting selects 3/8 times the

coarse range maximum or approximately 37.5 mA.

TABLE 9-2:

DIGITAL DAC DECODE (FINE

ADJUST)

FRACTIONAL VALUE OF

THE COARSE RANGE

LDxSEL<2:0>

Two polarity bits are provided in the CHGCON register

that allow the comparator outputs to be inverted under

ﬁrmware control. This allows the same comparators to

be used as both a charge control output and for the

current ﬂow detector, for generating a positive triggered

interrupt.

0

1

0

1

0

1

0

1

0

1

1/8

1/4

0

1

0

1

3/8

1/2

5/8

3/4

7/8

MAXIMUM

FIGURE 9-3: DAC TRANSFER FUNCTION

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

7F 7B 71 6A 63 5C 55 4E 47 40 39 32 2B 24 1D 16 0F 08 01 82 8B 94 9D AB AF AB B1 BA C3 CC D5 DE E7 EF F2 FB

LDxSEL Value (hex)

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 69

PIC14000

FIGURE 9-4: CHARGE/CURRENT FLOW DETECT CONTROL REGISTER

9Dh

B7

U

-

B6

B5

B4

CPOLB

R/W

0

B3

U

-

B2

B1

CCAEN

R/W

0

B0

CPOLA

R/W

0

CHGCON

Read/Write

POR value 00h

CCOMPB CCBEN

CCOMPA

R

0

R/W

0

R

0

Bit

Name

Function

B7

-

Unimplemented. Read as ’0’.

Charge Control Comparator Output B.

B6

B5

CCOMPB

CCBEN

Reading this bit returns the status of the charge control/wake-up comparator B output

before the inverter stage. Writes to this bit have no effect.

Charge Control Function Enable Bit. (Channel B)

1 = Charge Control is Enabled. RD2/CMPB and RD3/LDACB are used to control

switching regulator.

0 = Charge Control is Disabled (default). RD2/CMPB and RD3/LDACB assume normal

PORTD function.

Charge Control Polarity Bit B

B4

B3

B2

CPOLB

-

1 = Invert the output from the charge/wake-up comparator B.

0 = Do not invert the output from the charge/wake-up comparator B (default)

Unimplemented. Read as ’0’.

Charge Control Comparator Output A.

CCOMPA

Reading this bit returns the status of the charge control/wake-up comparator A output

before the inverter stage. Writes to this bit have no effect.

Charge Control Function Enable Bit. (Channel A)

1 = Charge Control is Enabled. RC0/LDACA and RC1/CMPA are used to control

switching regulator.

B1

B0

CCAEN

CPOLA

0 = Charge Control is Disabled (default). RC0/LDACA and RC1/CMPA assume normal

PORTC function.

Charge Control Polarity Bit A

1 = Invert the output from the charge/wake-up comparator A

0 = Do not invert the output from the charge/wake-up comparator A

(default)

DS40122A-page 70

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 9-5:

LDACA REGISTER

9Bh

B7

B6

B5

B4

B3

B2

B1

B0

LDACA

LDASEL7 LDASEL6 LDASEL5 LDASEL4 LDASEL3 LDASEL2 LDASEL1 LDASEL0

Read/Write

POR value 00h

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

Name

Function

LDASEL7

LDASEL6

LDASEL5

LDASEL4

LDASEL3

LDASEL2

LDASEL1

LDASEL0

B7-B0

DAC A Voltage Select Bits. See Table 9-1 and Table 9-2 for decoding.

FIGURE 9-6:

LDACB REGISTER

9Ch

B7

B6

B5

B4

B3

B2

B1

B0

LDACB

LDBSEL7 LDBSEL6 LDBSEL5 LDBSEL4 LDBSEL3 LDBSEL2 LDBSEL1 LDBSEL0

Read/Write

POR value 00h

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

Bit

Name

Function

LDBSEL7

LDBSEL6

LDBSEL5

LDBSEL4

LDBSEL3

LDBSEL2

LDBSEL1

LDBSEL0

B7-B0

DAC B Voltage Select Bits. See Table 9-1 and Table 9-2 for decoding.

9.5.1

WAKE-UP ON CURRENT DETECT

Note: The wake-up on current ﬂow feature can be

used even though charging is not used in

the system. In this case, the CCAEN bit

(CHGCON<1>) would always remain

cleared to ’0’.

The charge controller/current ﬂow detector can also be

used to detect current ﬂow during SLEEP or idle modes

and cause an interrupt to force a system wake-up. The

two DACs are used to adjust the current wake-up

threshold by programming the LDxSEL<7:4> bits in the

LDACA (9Bh) and LDACB (9Ch) registers according to

Table 9-1 and Table 9-2. By programming the two

DACs to detect opposite polarities, both positive and

negative current ﬂow can cause an interrupt. Either

DAC/comparator pair can cause a CPU interrupt. The

interrupt ﬂag (WUIF) is located in the PIR1<7> and is

enabled by the WUIE bit in the PIE1 register. The

enable bit must be set to ’1’ to enable the CPU interrupt.

The outputs of the two comparators can be read

(CCOMPA, CCOMPB) to determine which of the two

detectors caused the interrupt.

When using this feature, the CWUOFF and BIASOFF

bits must be cleared to ’0’. This enables charge

controller/wake-up DACs, comparators and the current

sense bias source.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 71

PIC14000

FIGURE 9-7: CHARGE CONTROL/CURRENT FLOW DETECT BLOCK DIAGRAM

(ONE OF TWO SHOWN)

CWUOFF

~5 µA

LDxSEL<7:3>

Coarse Adjust

Fine Tune Adjust

~0.85V

Analog

Mux

(1 of 32)

To RC0/LDACA

(Channel A only)

Analog

Mux

(1-of-8)

Analog

Mux

(1 of 32)

LDxSEL<2:0>

~0.15V

LDxSEL<7:3>

DAC (1 of 2)

To A/D

Converter

To CCOMPx bit,

CHGCON register

From Current Bias/

Zero Network

+

-

To RC1/CMPA

(channel A only)

CPOLx

To Interrupt Logic

(WUIF)

Note: The CCAEN bit (CHGCON <1>) controls the function of RC0 and RC1.

DS40122A-page 72

Preliminary

1995 Microchip Technology Inc.

PIC14000

10.1

Oscillator Conﬁgurations

10.0 SPECIAL FEATURES OF THE

CPU

PIC14000 can be operated with two different oscillator

options. The user can program a conﬁguration fuse

(FUSES<0>) to select one of these:

What sets apart

a

microcontroller from other

processors are special circuits to deal with the needs of

real time applications. PIC14000 has a host of such

features intended to maximize system reliability,

minimize cost through elimination of external

components, provide power saving operating modes

and offer code protection. These are:

• HS

High Speed Crystal/Ceramic Resonator

(FOSC =’0’)

• IN

Internal oscillator (FOSC =’1’)(Default)

The FOSC fuse bit is located in conﬁguration word

2007h.

1. OSC (oscillator) selection

- Crystal/resonator

- Internal oscillator

10.1.1 INTERNAL OSCILLATOR CIRCUIT

PIC14000 includes an internal oscillator option that

offers additional cost and board-space savings. No

external components are required. The nominal

operating frequency is 4 MHz, with an absolute

frequency tolerance of +/- 20%. Frequency drift over

voltage and temperature must remain below 5%. The

frequency is measured and stored into the calibration

space in EPROM (address 0FD0h).

2. Reset options

- Power-on Reset

- Power-up Timer

- Oscillator Start-up Timer

3. Interrupts

4. Watchdog Timer

5. SLEEP and HIBERNATE modes

6. Code protection

By selecting IN mode (FOSC fuse bit = ’1’), OSC1/PBTN

becomes a digital input (with weak internal pull-up

resistor) and can be read via bit MISC<0>. Writes to

this location have no effect. The OSC1/PBTN input is

capable of generating an interrupt to the CPU if

enabled (Section 10.5). Also, OSC2 pin becomes a dig-

ital output for general purpose use and is accessed via

MISC <1>. Writes to bit7 directly affects the OSC2 pin.

Reading this bit returns the contents of the output latch.

The MISC register format is shown in Figure 10-5.

7. In-circuit serial programming

These features will be described in the following

sections.

The OSC2 pin also outputs the IN oscillator frequency,

divided-by-four, via INCLKEN (MISC <2>).

10.1.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATOR

In HS mode, a crystal or ceramic resonator is con-

nected to the OSC1 and OSC2 pins to establish oscil-

lation. A parallel cut crystal is required. Use of a series

cut crystal may give a frequency outside of the crystal

manufacturer’s speciﬁcations. When in HS mode, the

device can have an external clock source to drive the

OSC1 pin.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 73

PIC14000

FIGURE 10-1: CRYSTAL/CERAMIC

RESONATOR OPERATION

TABLE 10-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

(HS OSC CONFIGURATION)

Mode

Freq

OSC1

OSC2

OSC1

HS

4MHz

8MHz

20MHz

15 - 33 pF

15 - 47 pF

15 - 33 pF

15 - 47 pF

To internal

logic

C1

XTAL

OSC2

SLEEP

RF

Note: Higher capacitance increases the stability of

oscillator but also increases the start-up time.

These values are for design guidance only. Rs may

be required in HS mode to avoid overdriving

crystals with low drive level speciﬁcation. Since

each crystal has its own characteristics, the user

should consult the crystal manufacturer for

appropriate values of external components.

RS

C2

Note1

PIC14000

See Table 10-1 and Table 10-2 for recommended

values of C1 and C2.

Note 1: A series resistor may be required for AT

§

For VDD > 4.5V, C1 = C2 ≈ 30pf is recommended.

strip cut crystals.

10.1.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

FIGURE 10-2: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

Either a prepackaged oscillator can be used or a simple

oscillator circuit with TTL gates can be built.

Prepackaged oscillators provide a wide operating

range and better stability. A well-designed crystal

oscillator will provide good performance with TTL

gates. Two types of crystal oscillator circuits can be

used; one with series resonance, or one with parallel

resonance.

CONFIGURATION)

OSC1

OSC2

Clock from

ext. system

PIC14000

Open

Figure 10-3 shows implementation of

a parallel

TABLE 10-1: CERAMIC RESONATORS

resonant oscillator circuit. The circuit is designed to use

the fundamental frequency of the crystal. The 74AS04

inverter performs the 180-degree phase shift that a

parallel oscillator requires. The 4.7 kΩ resistor provides

the negative feedback for stability. The 10 kΩ

potentiometer biases the 74AS04 in the linear region.

This could be used for external oscillator designs.

Mode

HS

Freq

OSC1

OSC2

4.0MHz

8.0MHz

16.0MHz

15 - 68 pF

10 - 68 pF

10 - 22 pF

15 - 68 pF

10 - 68 pF

10 - 22 pF

Note: Recommended values of C1 and C2 are identical to

the ranges tested table.

Higher capacitance increases the stability of

oscillator but also increases the start-up time.

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

FIGURE 10-3: EXTERNAL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

+5V

To Other

Devices

10k

Resonators Used:

74AS04

4.7k

4.0MHz Murata Erie CSA4.00MG

8.0MHz Murata Erie CSA8.00MT

16.0MHz Murata Erie CSA16.00MX

+/-.5%

CLKIN

74AS04

All resonators used did not have built-in capacitors.

10k

XTAL

10k

20pF

Figure 10-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330 kΩ resistors provide the negative

feedback to bias the inverters in their linear region.

DS40122A-page 74

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 10-4: EXTERNAL SERIES

RESONANT CRYSTAL

10.2

Reset Operation

PIC14000 differentiates between various kinds of reset:

OSCILLATOR CIRCUIT

• Power-on/low-voltage detect reset (POR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

To Other

Devices

330kΩ

PIC14000

CLKIN

• WDT time-out during normal operation

• WDT time-out during SLEEP

74AS04

0.1µF

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a deﬁned

state on power-on reset (POR), on MCLR or WDT reset

during normal operation, and on MCLR reset during

SLEEP. They are not affected by a WDT reset during

SLEEP, since this reset is viewed as the resumption of

normal operation. TO and PD bits are set or cleared

differently in different reset situations as indicated in

Table 10-3. These bits are used in software to

determine the nature of reset.

XTAL

It is recommended that a checksum comparison at

POR to ensure integrity of the data space contents.

A simpliﬁed block diagram of the on-chip reset circuit is

shown in Figure 10-6.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 75

PIC14000

FIGURE 10-5: MISC REGISTER

9Eh

B7

B6

B5

B4

B3

B2

B1

OSC2

R/W

0

B0

OSC1

R

2

MISC

SMHOG SPGNDB SPGNDA I CSEL

SMBUS INCLKEN

Read/Write

POR value 00h

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

Bit

Name

Function

SMHOG enable

2

1 = Stretch I C CLK signal (hold low) when receive data buffer is full (refer to

Section 7.1.4). For pausing I C transfers while preventing interruptions of A/D

2

B7

SMHOG

conversions.

2

0 = Disable I C CLK stretch. (default)

Serial Port Ground Select

B6

B5

B4

SPGNDB

SPGNDA

1 = PORTD<1:0> ground reference is the RD5/AN5 pin.

0 = PORTD<1:0> ground reference is VSS.

Serial Port Ground Select

1 = PORTC<7:6> ground reference is the RA1/AN1 pin.

0 = PORTC<7:6> ground reference is VSS.

2

I C Port select Bit.

1 = PORTD<1:0> are used as the I C clock and data lines.

0 = PORTC<7:6> are used as the I C clock and data lines.

2

I CSEL

2

SMBus-Compatibility Select

1 = SMBus compatibility mode is enabled. PORTC<7:6> have SMBus-compatible input

B3

SMBus

thresholds.

0 = SMBus-compatibility is disabled (default). PORTC<7:6> have Schmitt trigger input

thresholds.

Oscillator Output Select

B2

B1

B0

INCLKEN

OSC2

1 = Output IN oscillator signal on OSC2 pin.

0 = Disconnect IN oscillator signal from OSC2 pin. (default)

OSC2 output port bit (available in IN mode only).

Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the

output latch.

OSC1 input port bit (available in IN mode only).

Reads from this location return the status of the OSC1 pin in IN mode. Writes have no

effect.

OSC1

DS40122A-page 76

Preliminary

1995 Microchip Technology Inc.

PIC14000

10.4.2 POWER-UP TIMER (PWRT)

TABLE 10-3: STATUS BITS AND THEIR

SIGNIFICANCE

The Power-up Timer provides a ﬁxed 72 ms (nominal)

time-out on power-up only, from POR. The power-up

timer operates from a local internal oscillator. The chip

is kept in reset as long as PWRT is active. The PWRT

delay allows the VDD to rise to an acceptable level. A

conﬁguration fuse, PWRTE, can disable (if set, or

unprogrammed) or enable (if cleared, or programmed)

the power-up timer.

POR

TO

PD

Meaning

Power-On Reset

0

1

0

X

0

1

X

0

1

Illegal, TO is set on POR

Illegal, PD is set on POR

WDT reset during normal

operation

The power-up timer delay will vary from chip to chip

and due to VDD and temperature.

1

0

1

0

1

0

WDT time-out wakeup from

sleep

10.4.3 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycles (from OSC1 input) delay after the

PWRT delay is over. This guarantees that the crystal

oscillator or resonator has started and stabilized.

MCLR reset during normal

operation

MCLR reset during SLEEP or

HIB, or interrupt wake-up

from SLEEP or HIB.

The OST time-out provides an 8-cycle delay with IN

mode only after a Power-on Reset (POR) or wake-up

from SLEEP.

10.3

Low-Voltage Detector

10.4.4 TIMEOUT SEQUENCE

PIC14000 contains an integrated low-voltage detector

that uses a precision voltage reference. The supply

voltage is divided by two and compared to the bandgap

reference output (approximately 1.23V). If the supply

voltage (VDD) falls below Vtrip- for greater than 1 us

(nominal), then the low-voltage detector will cause the

LVD bit in register PCON (8Eh) to be reset. This bit

must be read by software

On power-up the time-out sequence is as follows: First

the PWRT time-out is invoked after POR has expired.

Then OST is activated in HS (crystal oscillator) mode.

The total time-out will vary based on the oscillator

conﬁguration and PWRTE fuse status. For example, in

IN mode, with PWRTE fuse unprogrammed (PWRT

disabled), there will be no time-out delay at all.

Figure 13-4 depicts the power-on reset time-out

sequences.

The approximate values of the low-voltage detector trip

points are as follows:

Table 10-4 shows the reset conditions for some special

registers, while Table 10-5 shows the reset conditions

for all registers.

• Vtrip- = 2.55V +/- 0.1V

• Vtrip+ = 2.60V +/- 0.1V

• Hysteresis Vtrip-/Vtrip+ = 50 mV

10.4

Power-Up Timer (PWRT) and

Oscillator Start-up Timer (OST)

10.4.1 VDD RISE DETECTOR

A VDD rise detector is included to ensure a clean reset

under fast VDD ramps where the bandgap reference

(and low-voltage detector) may not have enough time

to start up and stabilize. A POR pulse is generated

on-chip when VDD rise is detected (in the range of

2.0-2.2V). To take advantage of the POR, tie MCLR

directly (or through a resistor) to VDD. This circuit has a

maximum VDD slew rate speciﬁcation (see electrical

speciﬁcations). However, this circuit, when used in

combination with the DC low-voltage detector,

effectively guarantee a proper reset regardless of the

VDD ramp time.

The VDD rise detector does not produce an internal

reset when VDD declines.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 77

PIC14000

TABLE 10-4: RESET CONDITION FOR

SPECIAL REGISTERS

FIGURE 10-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

PCL

STATUS

PCON

Addr: 02h Addr: 03h Addr: 8Eh

VDD

000h

0001 1xxx 0--- --0x

0001 1uuu u--- --ux

Power-on Reset

MCLR reset

during normal

operation

R

D

R1

MCLR

000h

0001 0uuu u--- --ux

0000 1uuu u--- --ux

MCLR reset

during SLEEP

C

PIC14000

WDT reset

during normal

operation

1. External power-on reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

PC + 1

uuu0 0uuu u--- --ux

WDT during

SLEEP

PC + 1 (1) uuu1 0uuu u--- --ux

Interrupt

wake-up from

SLEEP

2. R < 40 KΩ is recommended to make sure

that voltage drop across R does not exceed

0.2V (max leakage current spec on MCLR

pin is 5 µA). A larger voltage drop will

degrade VIH level on MCLR pin.

Legend: u = unchanged

x = unknown

3. R1 = 100 Ω to 1 KΩ will limit any current

ﬂowing into MCLR from external capacitor C

in the event of MCLR pin breakdown due to

ESD or EOS.

- = unimplemented, read as ’0’

(1) When the wake-up is due to an interrupt and the

GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

DS40122A-page 78

Preliminary

1995 Microchip Technology Inc.

PIC14000

TABLE 10-5: RESET CONDITION FOR REGISTERS

MCLR reset during

- normal operation

- SLEEP

Wake-up from SLEEP

through interrupt

Wake up from SLEEP

through WDT time-out

WDT time-out during normal

operation

Register

Address

-

Power-on Reset

xxxx xxxx

-

W

uuuu uuuu

-

uuuu uuuu

-

INDF

00h/80h

01h

TMR0

xxxx xxxx

0000h

uuuu uuuu

0000h

uuuu uuuu

PC + 1 (2)

uuu? ?uuu (3)

uuuu uuuu

---- uuuu

PCL

02h/82h

03h/83h

04h/84h

05h

STATUS

FSR

0001 1xxx

xxxx xxxx

---- xxxx

000? ?uuu (3)

uuuu uuuu

---- uuuu

PORTA

PORTC

PCLATH

INTCON

PIR1

07h

xxxx xxxx

---0 0000

0000 000x

0000 0000

xxxx xxxx

0000 0000

0000 0010

1111 1111

---- 1111

1111 1111

0000 0000

---- --00

uuuu uuuu

---0 0000

0000 000u

0000 0000

uuuu uuuu

0000 0000

0000 0010

1111 1111

---- 1111

1111 1111

0000 0000

---- --uu

uuuu uuuu

---u uuuu

0Ah/8Ah

0Bh/8Bh

0Ch

uuuu uuuu (1)

uuuu uuuu

---- uuuu

ADTMRL

ADTMRH

I2CBUF

I2CCON

ADCAPL

ADCAPH

ADCON0

OPTION

TRISA

0Eh

0Fh

13h

14h

15h

16h

1Fh

81h

85h

TRISC

87h

uuuu uuuu

---- --uu

PIE1

8Ch

PCON

8Eh

SLPCON

I2CADD

I2CSTAT

LDACA

LDACB

CHGCON

8Fh

0011 1111

0000 0000

--00 0000

0000 0000

0x00 0x00

0011 1111

0000 0000

--00 0000

0000 0000

0x00 0x00

uuuu uuuu

--uu uuuu

uuuu uuuu

93h

94h

9Bh

9Ch

9Dh

MISC

9Eh

9Fh

0000 000x

0000 0000

0000 000x

0000 0000

uuuu uuuu

ADCON1

Legend: u=unchanged, x =unknown, -– = unimplemented, reads as ’0’, ? = value depends on condition.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 79

PIC14000

can be determined by polling the interrupt ﬂag bits. The

interrupt ﬂag bit(s) must be cleared in software before

re-enabling interrupts to avoid inﬁnite interrupt

requests. Individual interrupt ﬂag bits are set

regardless of the status of their corresponding mask bit

or the GIE bit to allow polling.

10.5

Interrupts

PIC14000 has several sources of interrupt:

• External interrupt from OSC1/PBTN pin

2

• I C port interrupt

• PORTC change interrupt on change (pins

RC<7:4> only)

The return from interrupt instruction, RETFIE, exits the

interrupt routine as well as sets the GIE bit to re-enable

interrupts.

• Timer0 overﬂow

• A/D capture timer overﬂow

Note 1: The individual interrupt ﬂags will be set by

the speciﬁed condition even though the

corresponding interrupt enable bit is

cleared (interrupt disabled) or the GIE bit is

cleared (all interrupts disabled).

• A/D converter capture event (conversion-com-

plete)

• Wake-up on current detect

This section addresses the external and Timer0

interrupts only. Refer to the appropriate sections for

description of the serial port, wake-up and A/D

interrupts.

Note 2: If an interrupt occurs while the Global

Interrupt Enable (GIE) bit is being cleared,

the GIE bit may unintentionally be

re-enabled by the user’s Interrupt Service

Routine (the RETFIE instruction). The

events that would cause this to occur are:

The interrupt control register (INTCON, address 0Bh or

8Bh) records individual interrupt requests in ﬂag bits. It

also has individual and global enable bits. The

peripheral interrupt ﬂags reside in the PIR1 register

(0Ch). Peripheral interrupt enable interrupts are

contained in the PIE1 register (8Ch).

1. An instruction clears the GIE bit while an

interrupt is acknowledged.

2. The program branches to the interrupt vector

and executes the Interrupt Service Routine.

A global interrupt enable bit, GIE (INTCON <7>)

enables all un-masked interrupts (if set) or disables all

interrupts (if cleared). Individual interrupts can be

disabled through their corresponding mask bit in the

INTCON register. GIE is cleared on reset to mask

interrupts.

3. The interrupt service routine completes with the

execution of theRETFIEinstruction. This causes

the GIE bit to be set (enables interrupts), and the

program returns to the instruction after the one

which was meant to disable interrupts.

When an interrupt is serviced, the GIE is cleared to

disable any further interrupt, the return address is

pushed onto the stack and the PC is loaded with

0004h, the interrupt vector. For external interrupt

The method to ensure that interrupts are globally

disabled is:

1. Ensure that the GIE bit was cleared by the

instruction, as shown in the following code:

2

events, such as the I C interrupt, the interrupt latency

LOOP:BCF

INTCON,GIE ; Disable Global Interrupts

will be 3 or 4 instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for 1 or 2 cycle instructions. Once in the

interrupt service routine the source(s) of the interrupt

BTFSC INTCON,GIE ; Global Interrupts Disabled?

GOTO LOOP

:

; No, try again

; Yes, continue with program

;

flow

FIGURE 10-7: INTERRUPT LOGIC SCHEMATIC

PBIF

PBIE

ADIF

ADIE

Wake-up (If in SLEEP mode)

or terminate long write

T0IF

T0IE

I²CIF

I²CIE

PEIF

PEIE

Interrupt to CPU

GIE

OVFIF

OVFIE

WUIF

WUIE

RCIF

RCIE

DS40122A-page 80

Preliminary

1995 Microchip Technology Inc.

PIC14000

10.5.1 EXTERNAL INTERRUPT

whether or not the processor branches to the interrupt

vector following wake-up. The timing of the external

interrupt is shown in Figure 10-8.

An external interrupt can be generated via the

OSC1/PBTN pin if IN mode is enabled. A weak pull-up

is also enabled on this pin if IN mode is enabled. These

features are unavailable in HS (crystal/resonator)

mode. This interrupt is falling edge triggered. When a

valid edge appears on OSC1/PBTN pin, the PBIF bit is

set (PIR1<4>). This interrupt can be disabled by

clearing the PBIE control bit (PIE1 <4>). The PBIF bit

must be cleared in software in the interrupt service

routine before re-enabling the interrupt. The PBTN

interrupt can wake up the processor from SLEEP if the

PBIE bit is set (interrupt enabled) prior to going into

SLEEP mode. The status of the GIE bit determines

FIGURE 10-8: EXTERNAL (OSC1/PBTN) INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1 (int)

EPCLK(3)

4

PBIF pin

1

PBIFﬂag

(PIR<4>)

5

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC+1

—

0004h

0005h

Instruction

fetched

Inst (PC+1)

Inst (PC)

Inst (0004h)

Inst (PC)

Inst (0005h)

Inst (0004h)

Instruction

executed

Inst (PC-1)

Dummy Cycle

Notes:

1. INTF ﬂag is sampled here (every Q1)

2. Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3. Available only in IN oscillator mode on OSC2.

4. For minimum width spec of INT pulse, refer to AC specs.

5. INTF is enabled to be set anytime during the Q4-Q1 cycles.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 81

PIC14000

10.5.2 TIMER0 INTERRUPT

Note: If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RCIF

interrupt ﬂag may not be set.

An overﬂow (FFh -> 00h) in Timer0 will set the T0IF

(INTCON <2>) ﬂag. T0IE (INTCON <5>) controls the

interrupt.

10.5.4 CONTEXT SWITCHING DURING

INTERRUPTS

10.5.3 PORTC INTERRUPT ON CHANGE

An input change on PORTC <7:4> sets the RCIF

(PIR1<2>) bit. RCIE (PIE1 <2>) controls the interrupt.

For operation of PORTC, refer to Section 5.2.

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt for example, W register

and Status register. Example 10-1 is an example that

shows saving registers in RAM.

EXAMPLE 10-1: SAVING W REGISTER AND STATUS IN RAM

push:

MOVWF

SWAPF

BCF

TEMP_W

STATUS,W

STATUS,RP0

; Copy W to temp register

; Swap status to be saved into W

; Select bank 0

MOVWF

TEMP_STAT

; Save status to temp_stat regis-

ter

:

;

(ISR)

:

pop:

bank

SWAPF

TEMP_STAT, W

; Swap temp_stat reg into W (sets

; to original state)

; Move W into status register

; Do not want to

MOVWF

SWAPF

STATUS

TEMP_W, F

TEMP_W, W

; affect Z-bit

DS40122A-page 82

Preliminary

1995 Microchip Technology Inc.

PIC14000

The WDT can be permanently disabled by

programming the conﬁguration fuse WDTE as a ’0’. Its

oscillator can be shut down to conserve battery power

by entering HIBERNATE Mode. Refer to Section 10.7.3

for more information on HIBERNATE mode.

10.6

Watchdog Timer (WDT)

The watchdog timer is realized as a free running

on-chip RC oscillator which does not require any

external components. This RC oscillator is separate

from the IN oscillator used to generate the CPU and

A/D clocks. That means that the WDT will run even if

the clock has been stopped, for example, by execution

of a SLEEPinstruction. Refer to Section 10.7.1 for more

information.

CAUTION: Beware of disabling WDT if software

routines require exiting based on WDT

reset. For example, the MCU will not

exit HIBERNATE mode based on WDT

reset.

During normal operation, a WDT time-out generates a

device RESET. If the device is in SLEEP mode, a WDT

time-out causes the device to wake-up and continue

with normal operation.

A block diagram of the watchdog timer is shown in

Figure 10-9. It should be noted that a RESET

generated by the WDT time-out does not drive MCLR

low.

FIGURE 10-9: WATCHDOG TIMER BLOCK DIAGRAM (WITH TIMER0)

Timer0

Data bus

8

FOSC/4

0

1

PSout

1

0

Sync with

Internal

clocks

TMR0

RC3/T0CKI

PSout

Set T0IF

Interrupt on

Overﬂow

(2 cycle delay)

T0SE

PSA

T0CS

Prescaler/

Postscaler

Local

8-bit Counter

Oscillator

0

1

8

18 mS

Timer

3

8-to-1 MUX

PS2:PS0

PSA

Enable

1

0

PSA

WDT

Time-out

Watchdog Timer

WDT

Enable Bit

Note: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

Hibernate

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 83

PIC14000

10.6.1 WDT PERIOD

10.7

Power Management Options

The WDT has a nominal time-out period of 18 ms (with

no prescaler). The time-out periods vary with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION registers. Thus, time-out periods

up to 2.3 seconds can be realized. The CLRWDT and

SLEEPinstructions clear the WDT and the prescaler, if

assigned to the WDT, and prevent it from timing out and

generating a device RESET.

PIC14000 has several power management options to

prolong battery lifetime. TheSLEEPinstruction halts the

CPU and turn off the on-chip oscillator. The CPU can be

in SLEEP mode, yet the A/D converter can continue to

run. Several bits are included in the SLPCON register

(8Fh) to control power to analog modules, including the

current bias source, charge controller, temperature

sensor and A/D converter. For even lower power, a

HIBERNATE mode which halts all on-chip activity, can

be selected. A summary of the power management

options is contained in Table 10-6.

The TO bit in the status register will be cleared upon a

watchdog timer time-out.

10.6.2 WDT PROGRAMMING CONSIDERATIONS

It should also be taken into account that under

worst-case conditions (minimum VDD, maximum

temperature, maximum WDT prescaler) it may take

several seconds before a WDT time-out occurs.

TABLE 10-6: SUMMARY OF POWER MANAGEMENT OPTIONS

Estimated

Function

Current*

Summary

CPU clock

Frequency dependent OFF during SLEEP mode, ON otherwise.

Main Oscillator

Frequency dependent ON if NOT in SLEEP mode. In SLEEP mode,

controlled by OSCOFF bit, SLPCON<3>

Watchdog Timer

~ 5 µA

Controlled by WDTE, 2007h<2> and HIBEN,

SLPCON <7>

Temperature sensor

Low-voltage Detector

100 µA

Controlled by TEMPOFF, SLPCON<1>

Controlled by REFOFF, SLPCON<5>

Controlled by CWUOFF, SLPCON<2>

< 50 µA

50-100 µA

Charge Controller/Current Flow

Detector

A/D Comparator

A/D Current DAC

100 µA

Controlled by ADOFF, SLPCON<0>

Depends on

ADDAC<3:0>.

Anywhere from

0 - 40 µA.

Slope Reference Divider

Current Bias Network

A/D Capture Clock

~100 µA

Controlled by ADOFF, SLPCON<0>

Controlled by BIASOFF, SLPCON<4>.

~5 µA

< 500 µA at 4 MHz.

Automatically stops when overflow occurs. Requires

ADRST to restart. Also controlled by ADOFF,

SLPCON<0>

Bandgap Reference

~ 15 µA

Controlled by REFOFF, SLPCON< 5>

Controlled by REFOFF, SLPCON<5>

Bias Generator (for current sources) < 5 µA

Voltage Regulator Control

Depends on external

components.

Always ON. Does not consume power if

unconnected.

Power On Reset

< 5 µA

Always ON

Note:All circuits except voltage regulator and Power On Reset are OFF in HIBERNATE mode.

* Estimated current is preliminary information only.

DS40122A-page 84

Preliminary

1995 Microchip Technology Inc.

PIC14000

10.7.1 SLEEP MODE

An external reset on MCLR pin causes a device reset.

The other wake-up events are considered

a

The SLEEP mode is entered by executing a SLEEP

instruction.

continuation of program execution. The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused a

wake-up).

If SLEEP mode is enabled, the WDT will be cleared but

keep running. The PD bit in the STATUS register is

cleared, the TO bit is set, and on-chip oscillators are

shut off, except the WDT RC oscillator, which continues

to run. The I/O ports maintain the status they had

before the SLEEP command was executed (driving

high, low, or high-impedance). The IN or HS oscillator

will continue to run if bit OSCOFF in the SLPCON

register is cleared.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set. Wake-up occurs

regardless of the state of bit GIE. If bit GIE is clear, the

device continues execution at the instruction after the

SLEEPinstruction. If bit GIE is set, the device executes

the instruction after the SLEEP instruction and then

branches to the interrupt address (0004h). In cases

where the execution of the instruction following SLEEP

is not desirable, the user should have a NOP after the

SLEEPinstruction.

It is an option while in SLEEP mode to leave the

on-chip oscillator running. This option allows an A/D

conversion to continue while the CPU is in SLEEP

mode. The CPU clocks are stopped in this condition to

preserve power. The operation of the on-chip oscillator

during SLEEP is controlled by the OSCOFF bit in the

SLPCON <4>. Setting this bit to ’1’ allows the oscillator

to continue to run. This bit is only active in SLEEP

mode.

The WDT is cleared when the device wakes-up from

sleep, regardless of the source of wake-up.

For lowest power consumption in this mode, all I/O pins

should be either at VDD or VSS with no external circuitry

drawing current from the I/O pin. I/O pins that are

high-impedance inputs should be pulled high or low

externally to avoid leakage currents caused by ﬂoating

inputs. The MCLR pin must be at a logic high level

(VIH). The contribution from any on-chip pull-up

resistors should be considered.

Note: If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the

corresponding interrupt ﬂag bits set, the

device will immediately wake from SLEEP.

10.7.3 HIBERNATE MODE

HIBERNATE mode is identical to SLEEP mode with the

exception that the WDT (Watchdog Timer) is forced off.

10.7.2 WAKE-UP FROM SLEEP

The HIBERNATE mode is entered by executing a

SLEEP instruction with bit HIBEN in the SLPCON

register set.

The PIC14000 can wake up from SLEEP through one

of the following events:

1. External reset input on MCLR pin

2. Watchdog Timer time-out (if WDT is enabled)

3. Interrupt from OSC1/PBTN pin

4. RC<7:4> port change

Exiting HIBERNATE mode occurs in the same way as

exiting SLEEP mode, except that exiting due to a

watchdog reset cannot occur.

HIBERNATE mode allows power consumption to be

reduced to a minimum (typically a few microamps)

during periods of non-operation. This allows for

reduced current consumption in battery operated

systems that may undergo long storage periods (for

example, in warehouse after manufacture). This mode

may be desirable if a battery continues to be

discharged below the end-of-discharge voltage, to

minimize battery drain as much as possible, until a

recharge cycle can be performed.

5. TMR0 overﬂow.

The following peripheral interrupts can cause wake-up

from SLEEP:

2

1. I C (serial port) start/stop bit detect interrupt.

2. Wake-up on current ﬂow interrupt.

3. A/D conversion complete (capture event) interrupt.

4. A/D timer overﬂow interrupt.

Note: For an A/D interrupt to occur, bit OSCOFF

must be cleared to allow the on-chip

oscillator to continue to run during SLEEP

mode. Similarly, in order to use the wake-up

on current detect interrupt to exit SLEEP

mode, bit CWUOFF must be cleared to

keep the charge controller/current ﬂow

detector powered.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 85

PIC14000

FIGURE 10-10: SLPCON REGISTER

8Fh

B7

HIBEN

R/W

0

B6

-

B5

REFOFF

R/W

B4

BIASOFF

R/W

B3

B2

B1

B0

SLPCON

Read/Write

POR value 1Fh

OSCOFF CWUOFF TEMPOFF ADOFF

U

0

R/W

1

R/W

1

R/W

1

R/W

1

Bit

Name

Function

Hibernate Mode Select

B7

B6

B5

HIBEN

1 = Hibernate mode enable

0 = Normal operating mode

Unimplemented. Read as ’0’

References Power Control

-

REFOFF

1 = The Bandgap reference, Low voltage detect, and bias generator is off.

0 = The Bandgap reference is on.

Summing Junction Current Bias Source Power Control

1 = The current bias source is off. The AN1/BATI input can continue to function as

either an analog or digital input.

B4

B3

BIASOFF

0 = The current bias source is ON. The signal at the AN1/BATI input is level shifted

by approximately 0.5V.

Internal Oscillator ON/OFF bit during SLEEP mode.

1 = The internal IN or crystal oscillator is disabled during SLEEP mode.

OSCOFF

0 = The internal IN or crystal oscillator is running during SLEEP mode for A/D con-

versions to continue.

NOTE: This bit is effective only in SLEEP mode.

Charge Controller/Current Flow Detect Power Control

B2

B1

B0

CWUOFF

TEMPOFF

ADOFF

1 = The charge controller/current ﬂow detector circuits are OFF.

0 = The charge controller/current ﬂow detector circuits are ON.

On-chip Temperature Sensor Power Control

1 = The temperature sensor is OFF.

0 = The temperature sensor is ON.

A/D Module Power Control

1 = The A/D module power (comparator, current DAC, slope reference) is OFF

0 = The A/D module power is ON.

DS40122A-page 86

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 10-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

TOST(2)

CLKOUT(4)

INTERRUPT

Flag (5)

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(PC + 1)

Inst(0005h)

Inst(0004h)

Inst(PC) = SLEEP

Inst(PC - 1)

fetched

Instruction

executed

Dummy cycle

SLEEP

Note 1: HS oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay will be 8 TOSC for IN osc mode.

3: GIE = 1 assumed. In this case after wake up processor jumps to interrupt routine. If GIE = 0,

execution will continue in line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

5: Interrupt ﬂag can be from any source. Refer to Section 10.5 for sources.

10.8.1 CODE PROTECTION FUSES

10.8

Code Protection

Three separate code protect fuse bits are provided on

PIC14000. They are CPP (program space), CPU (user

space), and CPC (calibration space). The code

protection fuses are part of the conﬁguration fuse word

at location 2007h as deﬁned in Figure 10-12. The

contents of all segments can be read. Protected user

and program segments cannot be read or written

(programmed). Protected calibration space can be

read, but not written.

The code in the program memory can be protected by

programming the code protect fuses. When code

protected, the contents of the program memory cannot

be read out. In code-protected mode, the conﬁguration

word (2007h) will not be scrambled, allowing reading of

all conﬁguration bits (fuse(s)).

Note that address 2007h is beyond the user program

memory space. It resides in the special

test/conﬁguration memory space (2000h - 3FFFh),

which can be accessed only during programming. The

code protection fuses cannot be erased, once

programmed.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 87

PIC14000

FIGURE 10-12: CONFIGURATION FUSE WORD

2007h

B13-B8

CP<5:0>

R/W

B7

B6

B5

B4

B3

B2

B1

B0

FUSES

CPC

R/W

1

N/A

CPU

CPP

R/W

1

PWRTE

R/W

1

WDTE

R/W

1

N/A

FOSC

Read/Write

Erased value

Reserved R/W

1

Bit

B13-B8

B7

Name

Function

CP<5:0>

Alternate Code Protection Bits (Reserved).

Calibration Space Code Protection Bit

CPC

1 = Calibration space is readable and programmable.

0 = Calibration space is write protected (fuse is programmed).

B6

B5

N/A

Reserved

CPU

User Space Code Protection Bit

1 = User space is readable and programmable.

0 = User space is read/write protected (bit is programmed).

B4

B3

B2

CPP

Program Space Code Protection Bit

1 = Program space is readable and programmable.

0 = Program space is read/write protected (bit is programmed).

PWRTE

WDTE

Power-up Timer Enable Bit.

0 = Power-up timer is enabled.

1 = Power-up timer is disabled (unprogrammed).

Watchdog Timer Enable Bit

1 = WDT is enabled. (unprogrammed)

0 = WDT is disabled.

B1

B0

N/A

Reserved

FOSC

Oscillator Selection Bit

0 = HS oscillator (crystal/resonator)

1 = IN oscillator (default unprogrammed)

DS40122A-page 88

Preliminary

1995 Microchip Technology Inc.

PIC14000

10.9

In-Circuit Serial Programming

FIGURE 10-13: TYPICAL IN-SYSTEM SERIAL

PROGRAMMING

PIC14000 can be serially programmed while in the end

application circuit. This is simply done with two lines for

clock and data, and three other lines for power, ground

and the programming voltage. This allows customers to

manufacture boards with unprogrammed devices, and

then program the microcontroller just before shipping

the product. This allows the most recent ﬁrmware or a

custom ﬁrmware to be programmed.

CONNECTION

To Normal

Connections

External

Connector

Signals

PIC14000

+5V

0V

VDD

VSS

The device is placed into a program/verify mode by

holding the RC6/SCL and RC7/SDA pins low while

raising the MCLR (VPP) pin from VIL to VIH. RC6 then

becomes the programming clock and RC7 becomes

the programmed data. Both RC6 and RC7 are Schmitt

trigger inputs in this mode.

Vpp

MCLR/VPP

RC6

RC7

CLK

Data I/O

After reset, to place the device into programming/verify

mode, the program counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14-bits of program data

are then supplied to or from the device. For complete

details about serial programming, please refer to the

PIC16C6X/7X Programming Speciﬁcations (Literature

#DS30228).

VDD

To Normal

Connections

A typical in-system serial programming connection is

shown in Figure 10-13.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 89

PIC14000

NOTES:

DS40122A-page 90

Preliminary

1995 Microchip Technology Inc.

PIC14000

The instruction set is highly orthogonal and is grouped

into three basic categories:

11.0 INSTRUCTION SET SUMMARY

The PIC14000’s instruction set is the same as

PIC16CXX. Each instruction is a 14-bit word divided

into an OPCODE which speciﬁes the instruction type

and one or more operands which further specify the

operation of the instruction. The instruction set sum-

mary in Table 11-2 lists byte-oriented, bit-oriented, and

literal and control operations. Table 11-1 shows the

opcode ﬁeld descriptions.

• Byte oriented operations

• Bit oriented operations

• Literal and control operations

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles with the second cycle executed as a

NOP. One instruction cycle consists of four oscillator

periods. Thus, for an oscillator frequency of 4 MHz, the

normal instruction execution time is 1 µs. If a

conditional test is true or the program counter is

changed as a result of an instruction, the instruction

execution time is 2 µs.

For byte-oriented instructions, 'f' represents a ﬁle

register designator and 'd' represents a destination

designator. The ﬁle register designator speciﬁes which

ﬁle register is to be utilized by the instruction.

The destination designator speciﬁes where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W register. If 'd' is one, the result is placed

in the ﬁle register speciﬁed in the instruction.

Table 11-2 lists the instructions recognized by the

MPASM assembler.

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

Figure 11-1 shows the three general formats that the

instructions can have.

Note: To maintain upward compatibility with

future PIC16CXX products, do not use the

OPTION and TRIS instructions.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 11-1: OPCODE FIELD

DESCRIPTIONS

All examples use the following format to represent a

hexadecimal number:

0xhh

Field

Description

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

where h signiﬁes a hexadecimal digit.

f

w

b

k

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

Bit address within an 8 bit ﬁle register

Literal ﬁeld, constant data or label

Byte-oriented ﬁle register operations

Don't care location (= 0 or 1)

13

8

7

6

0

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

software tools.

x

OPCODE

d

f (FILE #)

d = 0 for destination W

d = 1 for destination f

Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f.

Default is d = 1

d

f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9

b (BIT #)

label

TOS

Label name

7

6

0

Top of Stack

OPCODE

f (FILE #)

PC

Program Counter

Program Counter High Latch

Global Interrupt Enable Bit

Watchdog Timer Counter

Time-out Bit

PCLATH

GIE

b = 3-bit address

f = 7-bit ﬁle register address

WDT

Literal and control operations

13

TO

8

7

PD

Power-down Bit

OPCODE

k (literal)

Destination either the W register or the speciﬁed

register ﬁle location

dest

k = 8-bit immediate value

[

(

]

)

Options

Contents

→

Assigned to

< >

Register bit ﬁeld

In the set of

italics

User deﬁned term (font is courier)

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 91

PIC14000

TABLE 11-2: PIC14000 INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

msb

lsb

ADDWF

ANDWF

CLRF

Add W and f

AND W and f

1

C,DC,Z

1,2

2

Z

f, d

00

0111 dfff ffff

0101 dfff ffff

0001 lfff ffff

0001 0xxx xxxx

1001 dfff ffff

0011 dfff ffff

1011 dfff ffff

1010 dfff ffff

1111 dfff ffff

0100 dfff ffff

1000 dfff ffff

0000 lfff ffff

0000 0xx0 0000

1101 dfff ffff

1100 dfff ffff

0010 dfff ffff

1110 dfff ffff

0110 dfff ffff

f, d Clear f

1

00

f

CLRW

COMF

DECF

Clear W

1

-

Complement f

1

1,2

f, d

f

Decrement f

1

1,2

DECFSZ

INCF

Decrement f, Skip if 0

Increment f

1(2)

1

1,2,3

1,2

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

Increment f, Skip if 0

Inclusive OR W and f

Move f

1(2)

1

1,2,3

1,2

Z

1

1,2

Move W to f

1

-

No Operation

1

f, d

RLF

Rotate left through carry

Rotate right f through carry

1

C

1,2

RRF

1

C

SUBWF

SWAPF

XORWF

f, d Subtract W from f

1

C,DC,Z

f, d

Swap nibbles in f

1

Exclusive OR W and f

1

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

f, b

Bit Clear f

1

01

00bb bfff ffff

01bb bfff ffff

1,2

3

BSF

Bit Set f

BTFSC

BTFSS

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2) 01

10bb bfff ffff

bfff

11bb

ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

k

-

Add literal to W

1

2

1

2

1

2

1

11

10

00

10

11

00

11

00

11

111x kkkk kkkk C,DC,Z

AND literal to W

1001 kkkk kkkk

0kkk kkkk kkkk

Z

Call subroutine

CLRWDT

GOTO

Clear watchdog timer

Go to address

0000 0110 0100 TO,PD

k

-

1kkk kkkk kkkk

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Inclusive OR literal to W

Move literal to W

1000 kkkk kkkk

00xx kkkk kkkk

0000 0000 1001

01xx kkkk kkkk

0000 0000 1000

Z

k

-

Return from interrupt

Return with literal in W

Return from subroutine

Go into standby mode

Subtract W from literal

Excl. OR literal to W

-

k

0000 0110 0011 TO,PD

110x kkkk kkkk C,DC,Z

1010 kkkk kkkk

Z

Note 1: When an I/O register is modiﬁed as a function of itself (e.g., MOVF PORTB, 1), the value used will be that

value present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is

driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d=1), the prescaler will be cleared

if assigned to the TMR0.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The

second cycle is executed as a NOP.

DS40122A-page 92

Preliminary

1995 Microchip Technology Inc.

PIC14000

11.1

Instruction Descriptions

Add Literal to W

ANDLW

And Literal and W

ADDLW

Syntax:

[label] ANDLW

k

Syntax:

[label] ADDLW

0 ≤ k ≤ 255

(W) + k → W

C, DC, Z

k

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Encoding:

Description:

(W).AND. (k) → W

Z

11

1001

kkkk

11

111x

kkkk

The contents of W register are

AND’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of the W register are

added to the eight bit literal 'k' and the

result is placed in the W register.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

ANDLW

0x5F

ADDLW

0x15

Before Instruction

W

=

0xA3

0x03

W

=

0x10

0x25

After Instruction

W

=

W

=

ADDWF

Syntax:

ADD W to f

ANDWF

Syntax:

AND W with f

[label] ADDWF f,d

[label] ANDWF f,d

Operands:

0 ≤ f ≤ 127

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected:

Encoding:

C, DC, Z

Status Affected:

Encoding:

Z

00

0111

dfff

ffff

00

0101

dfff

ffff

Add the contents of the W register to

register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

register. If 'd' is 1 the result is stored

back in register 'f'.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

ADDWF

FSR,

0

ANDWF

FSR, 1

Before Instruction

W

FSR =

=

0x17

0xC2

W

FSR =

=

0x17

0xC2

After Instruction

W

FSR =

=

0xD9

0xC2

W

FSR =

=

0x17

0x02

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 93

PIC14000

BCF

Bit Clear f

BTFSC

BIT Test, skip if Clear

Syntax:

Operands:

[label] BCF f,b

Syntax:

[label] BTFSC f,b

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation:

Status Affected:

Encoding:

Description:

Words:

0 → f <b>

Operation:

skip if (f<b>) = 0

None

Status Affected:

Encoding:

01

00bb

bfff

ffff

01

10bb

bfff

ffff

If bit 'b' in register 'f' is '0' then the next

instruction is skipped.

Bit 'b' in register 'f' is cleared.

Description:

1

If bit 'b' is '0' then the next instruction

fetched during the current instruction

execution is discarded, and a NOP is

executed instead, making this a 2 cycle

instruction.

Cycles:

BCF

FLAG_REG, 7

Example

Before Instruction

FLAG_REG = 0xC7

After Instruction

Words:

Cycles:

Example

1

1(2)

FLAG_REG = 0x47

HERE

FALSE

TRUE

BTFSC FLAG,1

GOTO

PROCESS_CODE

•

BSF

Bit Set f

Syntax:

Operands:

[label] BSF f,b

Before Instruction

0 ≤ f ≤ 127

0 ≤ b ≤ 7

PC

=

address HERE

After Instruction

Operation:

Status Affected:

Encoding:

Description:

Words:

1 → f<b>

if FLAG<1>=0,

PC=address

if FLAG<1>=1,

PC=address

TRUE

None

01

01bb

bfff

ffff

FALSE

Bit 'b' in register 'f' is set.

1

Cycles:

BSF

FLAG_REG,

7

Example

Before Instruction

FLAG_REG= 0x0A

After Instruction

FLAG_REG= 0x8A

DS40122A-page 94

Preliminary

1995 Microchip Technology Inc.

PIC14000

BTFSS

Bit Test, skip if Set

CLRF

Clear f

Syntax:

[label] BTFSS f,b

Syntax:

[label] CLRF

f

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

0 ≤ f ≤ 127

00h → f

1 → Z

Operation:

skip if (f<b>) = 1

None

Status Affected:

Encoding:

Status Affected:

Encoding:

Z

01

11bb

bfff

ffff

00

0001

1fff

ffff

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and a NOP is

executed instead, making this a 2 cycle

instruction.

The contents of register 'f' are cleared

and the Z bit is set.

Description:

Words:

Cycles:

Example

1

CLRF

FLAG_REG

Words:

Cycles:

Example

1

Before Instruction

FLAG_REG

After Instruction

FLAG_REG

Z

1(2)

=

0x5A

HERE

FALSE

TRUE

BTFSC FLAG,1

=

0x00

1

GOTO

PROCESS_CODE

•

Before Instruction

PC

=

address HERE

After Instruction

if FLAG<1>=0,

PC=address

if FLAG<1>=1,

PC=address

FALSE

TRUE

CLRW

Clear W Register

[label] CLRW

None

CALL

Subroutine Call

Syntax:

[label] CALL k

Operands:

Operation:

Operands:

Operation:

0 ≤ k ≤ 2047

00h → (W)

1 → Z

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

0001

0XXX

XXXX

10

0kkk

kkkk

W registered is cleared. Zero bit (Z) is

set.

Description:

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Description:

Words:

Cycles:

Example

1

CLRW

Words:

Cycles:

Example

1

2

Before Instruction

W

=

0x5A

After Instruction

HERE

CALL THERE

W

=

0x00

1

Before Instruction

Z

=

PC

=

Address

HERE

After Instruction

PC

THERE

TOS =

=

Address

HERE + 1

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 95

PIC14000

CLRWDT

Syntax:

Clear Watchdog Timer

DECF

Decrement f

[label] DECF f,d

0 ≤ f ≤ 127

[label] CLRWDT

None

Syntax:

Operands:

Operation:

d

[0,1]

00h → WDT

0 → WDT prescaler,

1 → TO

Operation:

(f)-1 → (dest)

Status Affected:

Encoding:

Z

1 → PD

00

0011

dfff

ffff

Status Affected:

Encoding:

TO, PD

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Description:

00

0000

0110

0100

CLRWDT instruction resets the

Description:

watchdog timer. It also resets the

prescaler of the WDT. Status bits TO

and PD are set.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

DECF

CNT, 1

1

Before Instruction

CLRWDT

CNT

Z

After Instruction

=

0x01

0

Before Instruction

WDT counter

After Instruction

=

?

CNT

Z

=

0x00

1

WDT counter

0x00

WDT prescale =

0

1

TO

PD

=

COMF

Complement f

[label] COMF f,d

0 ≤ f ≤ 127

DECFSZ

Syntax:

Decrement f, skip if 0

[label] DECFSZ f,d

0 ≤ f ≤ 127

Syntax:

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) - 1 → d; skip if result = 0

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

None

00

1001

dfff

ffff

00

1011

dfff

ffff

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'. If the result is

0, the next instruction, which is already

fetched, is discarded. A NOP is executed

instead making it a two cycle instruction.

The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

W. If 'd' is 1 the result is stored back in

register 'f'.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

COMF

REG1,0

1(2)

Before Instruction

HERE

DECFSZ

GOTO

CNT, 1

LOOP

REG1

After Instruction

REG1

=

0x13

CONTINUE •

=

0x13

0xEC

•

W

Before Instruction

PC

= addressHERE

After Instruction

CNT

= CNT - 1

if CNT = 0,

PC

if CNT ≠ 0,

PC = address HERE+1

= address CONTINUE

DS40122A-page 96

Preliminary

1995 Microchip Technology Inc.

PIC14000

GOTO

Unconditional Branch

[label] GOTO k

0 ≤ k ≤ 2047

INCFSZ

Syntax:

Increment f, skip if 0

Syntax:

[label] INCFSZ f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d

[0,1]

k → PC<10:0>

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) + 1 → (dest), skip if result = 0

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

10

1kkk

kkkk

00

1111

dfff

ffff

GOTO is an unconditional branch.

The eleven bit immediate value is

loaded into PC bits <10:0>. The upper

bits of PC are loaded from

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is decre-

mented. A NOP is executed instead

making it a two cycle instruction.

Description:

PCLATH<4:3>. GOTO is a two cycle

instruction.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

2

1(2)

GOTO THERE

HERE

INCFSZ

GOTO

CNT, 1

LOOP

After Instruction

PC

=

Address THERE

CONTINUE •

•

Before Instruction

PC

= addressHERE

After Instruction

CNT

if CNT

PC

if CNT

PC

= CNT + 1

0,

= addressCONTINUE

0,

= addressHERE +1

=

≠

IORLW

Inclusive OR Literal with W

[label] IORLW k

0 ≤ k ≤ 255

Syntax:

INCF

Increment f

Operands:

Operation:

Status Affected:

Encoding:

Description:

Syntax:

Operands:

[label] INCF f,d

(W) .OR. (k) → (W)

Z

0 ≤ f ≤ 127

d

[0,1]

11

1000

kkkk

Operation:

(f) + 1 → (dest)

The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Status Affected:

Encoding:

Z

00

1010

dfff

ffff

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

Cycles:

Example

1

IORLW

0x35

Words:

Cycles:

Example

1

Before Instruction

W

=

0x9A

0xBF

After Instruction

INCF

CNT, 1

W

=

Before Instruction

CNT

Z

=

0xFF

0

After Instruction

CNT

Z

=

0x00

1

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 97

PIC14000

IORWF

Inclusive OR W with f

MOVF

Move f

Syntax:

[label] IORWF f,d

Syntax:

Operands:

[label] MOVF f,d

Operands:

0 ≤ f ≤ 127

d

[0,1]

d

[0,1]

Operation:

(W) .OR. (f) → (W)

Operation:

(f) → (dest)

Status Affected:

Encoding:

Z

Status Affected:

Encoding:

Z

00

0100

dfff

ffff

00

1000

dfff

ffff

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

The contents of register f is moved to

destination d. If d=0, destination is W

register. If d=1, the destination is ﬁle

register f itself. d=1 is useful to test a

ﬁle register since status ﬂag Z is

affected.

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

IORWF

RESULT, 0

Before Instruction

MOVF

FSR, 0

RESULT =

0x13

0x91

W

=

After Instruction

W

= value in FSR register

RESULT =

0x13

0x93

W

=

MOVWF

Move W to f

[label] MOVWF

0 ≤ f ≤ 127

(W) → (f)

MOVLW

Move Literal to W

[label] MOVLW k

0 ≤ k ≤ 255

Syntax:

f

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

Operands:

Operation:

Status Affected:

Encoding:

Description:

k → (W)

None

00

0000

1fff

ffff

11

00XX

kkkk

Move data from W register to register

'f'.

The eight bit literal 'k' is loaded into W

register. The don’t cares will assemble

as 0’s.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

MOVWF

OPTION

Before Instruction

OPTION =

MOVLW

0x5A

0xFF

0x4F

After Instruction

W

=

W

=

0x5A

After Instruction

OPTION =

0x4F

W

=

DS40122A-page 98

Preliminary

1995 Microchip Technology Inc.

PIC14000

NOP

No Operation

[label] NOP

None

RETFIE

Return from Interrupt

Syntax:

[label] RETFIE

None

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

No operation

None

TOS → PC,

1 → GIE;

Status Affected:

Encoding:

None

00

0000

0XX0

0000

00

0000

1001

No operation.

Return from Interrupt. Stack is popped

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting the Global Interrupt Enable (GIE)

bit. GIE is the global interrupt enable

bit (INTCON<7>). This is a two cycle

instruction.

Description:

1

Cycles:

1

NOP

Example

Words:

Cycles:

Example

1

2

RETFIE

After Interrupt

PC

GIE =

=

TOS

1

RETLW

Return Literal to W

[label] RETLW k

0 ≤ k ≤ 255

OPTION

Syntax:

Load Option Register

[label] OPTION

None

Syntax:

Operands:

Operation:

Operands:

Operation:

Status Affected:

Encoding:

Description:

W → OPTION;

k → W; TOS → PC;

None

Status Affected: None

00

0000

0110

0010

Encoding:

11

01XX

kkkk

The contents of the W register are

loaded in the OPTION register. This

instruction is supported for code com-

patibility with PIC16C5X products.

Since OPTION is a readable/writable

register, the user can directly address

it.

Description:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words:

Cycles:

Example

1

2

Words:

Cycles:

Example

1

CALL TABLE ;W contains table

;offset value

•

;W now has table value

•

To maintain upward compatibility

with future PIC16CXX products,

do not use this instruction.

•

TABLE

ADDWF PC

;W = offset

;Begin table

;

RETLW k1

RETLW k2

•

RETLW kn

; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k7

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 99

PIC14000

RETURN

Return from Subroutine

RRF

Rotate Right f through Carry

[label] RRF f,d

Syntax:

[label] RETURN

None

Syntax:

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ f ≤ 127

d

[0,1]

TOS → PC;

None

Operation:

See description below

C

Status Affected:

Encoding:

00

0000

1000

00

1100

dfff

ffff

Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter.

This is a two cycle instruction.

Description:

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Words:

Cycles:

Example

1

2

register f

C

RETURN

After Interrupt

Words:

Cycles:

Example

1

PC

=

TOS

RRF

REG1,0

Before Instruction

REG1

C

=

11100110

0

After Instruction

REG1

W

C

=

11100110

01110011

1

SLEEP

RLF

Rotate Left f through Carry

Syntax:

[label]

Syntax:

[label]

None

SLEEP

RLF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d

[0,1]

00h → WDT,

0 → WDT prescaler

1 → TO,

0 → PD

Operation:

See description below

C

Status Affected:

Encoding:

00

1101

dfff

ffff

Status Affected:

Encoding:

TO, PD

Description:

The contents of register 'f' are

rotated one bit to the left through

the Carry Flag. If 'd' is 0 the result

is placed in the W register. If 'd' is

1 the result is stored back in reg-

ister 'f'.

00

0000

0110

0011

Description:

The power down status bit (PD)

is cleared. Time-out status bit

(TO) is set. Watchdog Timer and

its prescaler are cleared.

The processor is put into SLEEP

mode with the oscillator

register f

C

Words:

Cycles:

Example

1

stopped. See Section 10.7 for

more details.

RLF

REG1,0

Words:

1

Cycles:

Example:

1

Before Instruction

REG1

C

=

11100110

0

SLEEP

After Instruction

REG1

W

C

=

11100110

11001100

1

DS40122A-page 100

Preliminary

1995 Microchip Technology Inc.

PIC14000

SUBLW

Subtract W from Literal

[label] SUBLW k

SUBWF

Syntax:

Subtract W from f

Syntax:

[label]

SUBWF f,d

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

k - (W) → (W)

C, DC, Z

Operands:

0 ≤ f ≤ 127

d

[0,1]

Operation:

f - (W) → (dest)

Status Affected:

Encoding:

C, DC, Z

11

110x kkkk kkkk

00

0010 dfff ffff

The W register is subtracted (2’s

complement method) from the

eight bit literal 'k'. The result is

placed in the W register.

Description:

Subtract (2’s complement meth-

odize W register from register 'f'.

If 'd' is 0 the result is stored in

the W register. If 'd' is 1 the

result is stored back in register

'f'.

Words:

1

Cycles:

Example 1:

SUBLW

0x02

Words:

1

Cycles:

Before Instruction

Example 1:

SUBWF

W

C

=

1

?

REG1,1

Before Instruction

After Instruction

REG1

W

=

3

2

?

W

C

=

1

1; result is

C

positive

After Instruction

Example 2:

Before Instruction

REG1

W

=

1

2

W

C

=

2

?

C

1; result is

positive

After Instruction

Example 2:

Before Instruction

W

=

0

C

zero

=

1; result is

REG1

W

C

=

2

?

Example 3:

Before Instruction

After Instruction

REG1 = 0

W

C

=

3

?

W

C

= 2

= 1; result is zero

After Instruction

W

C

=

FF

0; result is

Example 3:

Before Instruction

REG1 = 1

negative

W

C

= 2

= ?

After Instruction

REG1 = FF

W

C

= 2

= 0; result is negative

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 101

PIC14000

SWAPF

Syntax:

Swap f

XORLW

Exclusive OR Literal with W

[label] XORLW k

[label] SWAPF f,d

Syntax:

Operands:

0 ≤ f ≤ 127

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ k ≤ 255

d

[0,1]

(W) .XOR. k → (W)

Operation:

f<0:3> → d<4:7>,

f<4:7> → d<0:3>

Z

11

1010 kkkk kkkk

Status Affected:

Encoding:

None

Description:

The contents of the W register

are XOR’ed with the eight bit lit-

eral 'k'. The result is placed in

the W register.

00

1110

dfff

ffff

Description:

The upper and lower nibbles of

register 'f' are exchanged. If 'd' is

0 the result is placed in W regis-

ter. If 'd' is 1 the result is placed in

register 'f'.

Words:

1

Cycles:

Example:

Words:

Cycles:

Example

1

XORLW

0xAF

Before Instruction

SWAP REG,

F

0

W

=

0xB5

0x1A

After Instruction

Before Instruction

REG1

W

=

0xA5

After Instruction

REG1

W

=

0xA5

0x5A

TRIS

Load TRIS Register

Syntax:

[label] TRIS

f

XORWF

Syntax:

Exclusive OR W with f

[label] XORWF f,d

0 ≤ f ≤ 127

Operands:

Operation:

5 ≤ f ≤ 7

W → TRIS register f;

Operands:

Status Affected: None

d

[0,1]

Encoding:

00

0000 0110

0fff

Operation:

(W) .XOR. (f) → (dest)

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Description:

Status Affected:

Encoding:

Z

00

0110

dfff

ffff

Description:

Exclusive OR the contents of the

W register with register 'f'. If 'd' is

0 the result is stored in the W reg-

ister. If 'd' is 1 the result is stored

back in register 'f'.

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

To maintain upward compatibility

with future PIC16CXX products,

do not use this instruction.

REG

1

XORWF

Before Instruction

REG

W

=

0xAF

0xB5

After Instruction

REG

W

=

0x1A

0xB5

DS40122A-page 102

Preliminary

1995 Microchip Technology Inc.

PIC14000

The PICMASTER has been designed as a real-time

emulation system with advanced features generally

found on more expensive development tools. The AT

platform and Windows 3.x environment was chosen to

best make these features available to you, the end

user.

12.0 DEVELOPMENT SUPPORT

12.1

Development Tools

The PIC14000 are supported with a full range of

hardware and software development tools:

• PICMASTER Real-Time In-Circuit Emulator

• PRO MATE Universal Programmer

• MPASM Assembler

The PICMASTER Emulator Universal System consists

primarily of four major components:

• Host-Interface Card

• MPSIM Software Simulator

• C Compiler (MP-C)

• Emulator Control Pod

• Target-Speciﬁc Emulator Probe

• PC Host Emulation Control Software

• Fuzzy logic development system

(fuzzyTECH −MP)

The Windows 3.x operating system allows the

developer to take full advantage of the many powerful

features and functions of the PICMASTER system.

12.2

PICMASTER: High Performance

Universal In-Circuit Emulator

PICMASTER emulation can operate in one window,

while a text editor is running in a second window.

The PICMASTER Universal In-Circuit Emulator

provides the product development engineer with a

complete microcontroller design tool set for all

microcontrollers in the PIC14000, PIC16C5X,

PIC16CXX, and PIC17CXX families. A PICMASTER

System conﬁguration is shown in Figure 12-1.

PC-Host emulation control software takes full

advantage of Dynamic Data Exchange (DDE), a

feature of Windows 3.x. DDE allows data to be

dynamically transferred between two or more Windows

programs. With this feature, data collected with

PICMASTER can be automatically transferred to a

spreadsheet or database program for further analysis.

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different

processors. The universal architecture of the

PICMASTER allows expansion to support all new

PIC14000, PIC16C5X, PIC16CXX and PIC17CXX

microcontrollers.

Under Windows 3.x, two or more PICMASTER

emulators can be run simultaneously on the same PC

making development of multi-microcontroller systems

possible (e.g., a system containing a PIC16CXX

processor and a PIC17CXX processor).

The Emulator System is designed to operate on PC

compatible 386 and better machines. The development

software runs in the Microsoft Windows

3.x

environment, allowing the operator access to a wide

range of supporting software and accessories.

FIGURE 12-1: PICMASTER SYSTEM CONFIGURATION

In-Line

5VDC

Power Supply

(Optional)

90 - 250VAC

Windows 3.x

Power Switch

Interchangeable

Emulator Probe

Power Connector

PC Bus

Aux.

Ext +5V

PC-Interface

PICMASTER Emulator Pod

Common Interface Card

PC Compatible Computer

Logic Probes

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 103

PIC14000

MPASM provides a full feature directive language

represented by four basic classes of directives:

12.3

PRO MATE: Universal Programmer

The PRO MATE Universal Programmer is

full-featured programmer capable of operating in

stand-alone mode as well as PC-hosted mode.

a

• Data Directives control the allocation of memory

and provide a way to refer to data items

symbolically, by meaningful names.

The PRO MATE has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE can read, verify or program

the PIC14000. It can also set fuse conﬁguration and

code-protect bits in this mode.

• Listing Directives control the MPASM listing

display. They allow the speciﬁcation of titles and

sub-titles, page ejects and other listing control.

• Control Directives permit sections of

conditionally assembled code.

• Macro Directives control the execution and data

allocation within macro body deﬁnitions.

12.5

Software Simulator (MPSIM)

In PC-hosted mode, the PRO MATE connects to the

PC via one of the COM (RS-232) ports. PC based

user-interface software makes using the programmer

simple and efﬁcient. The user interface is full-screen

and menu-based. Full screen display and editing of

data, easy selection of fuse conﬁguration and part type,

easy selection of VDD min, VDD max and VPP levels,

load and store to and from disk ﬁles (Intel hex format)

are some of the features of the software. Essential

commands such as read, verify, program and blank

check can be issued from the screen. Additionally,

serial programming support is possible where each

part is programmed with a different serial number,

sequential or random.

The MPSIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The

input/output radix can be set by the user and the

execution can be performed in single step, execute

until break or in a trace mode. MPSIM fully supports

symbolic debugging using MP-C and MPASM. The

Software Simulator offers the low cost ﬂexibility to

develop and debug code outside of the laboratory

environment making it an excellent multi-project

software development tool.

The PRO MATE has a modular “programming socket

module.” Different socket modules are required for

different processor types and/or package types.

12.6

C Compiler (MP-C)

The MP-C Code Development System is a complete 'C'

compiler and integrated development environment for

Microchip’s PIC16/17 family of microcontrollers. The

compiler provides powerful integration capabilities and

ease of use not found with other compilers.

12.4

Assembler (MPASM)

The MPASM Cross Assembler is a PC-hosted symbolic

assembler. It supports all microcontroller series

including the PIC14000, PIC16C5X, PIC16CXX, and

PIC17CXX families.

For easier source level debugging, the compiler

provides symbol information that is compatible with the

PICMASTER Universal Emulator memory display

(emulator software versions 1.13 and later).

MPASM offers full featured Macro capabilities,

conditional assembly, and several source and listing

formats. It generates various object code formats to

support Microchip's development tools as well as third

party programmers.

The MP-C Code Development System is supplied

directly by Byte Craft Limited of Waterloo, Ontario,

Canada. If you have any questions, please contact your

regional Microchip FAE (see Worldwide Sales & Ser-

vice at the end of data sheet ), or Microchip technical

support personnel at (602) 786-7627.

MPASM allows full symbolic debugging from

the Microchip Universal Emulator System

(PICMASTER).

MPASM has the following features to assist in

developing software for speciﬁc use applications.

12.7

Fuzzy Logic Development System

(fuzzyTECH-MP)

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

fuzzyTECH-MP fuzzy logic development tool comes in

two versions: low cost introductory version,

• Macro Assembly Capability

a

• Provides Object ﬁles, Listing ﬁles, Symbol ﬁles

and special ﬁles required for debugging with one

of the Microchip Emulator systems.

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design, and a

full-featured fuzzyTECH-MP Edition for implementing

more complex systems.

• Supports Hex (default), Decimal and Octal

source and listing formats.

Both versions include Microchip’s fuzzyLAB

demonstration board for hands-on experience with

fuzzy logic systems implementation.

DS40122A-page 104

Preliminary

1995 Microchip Technology Inc.

PIC14000

12.8

Development Systems

For convenience, the development tools are packaged

into comprehensive systems as listed in Table 12-1.

TABLE 12-1: DEVELOPMENT SYSTEM PACKAGES

Item

Name

System Description

1.

PICMASTER System

PICMASTER In-Circuit Emulator with PRO MATE Programmer, Assembler,

Software Simulator, Samples, and your choice of Target Probe,

2.

PRO MATE System

PRO MATE Universal Programmer, full featured stand-alone or PC-hosted

programmer, Assembler, Simulator

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 105

PIC14000

NOTES:

DS40122A-page 106

Preliminary

1995 Microchip Technology Inc.

PIC14000

13.0 ELECTRICAL CHARACTERISTICS FOR PIC14000

ABSOLUTE MAXIMUM RATINGS †

Ambient temperature under bias..............................................................................................................-55°C to+ 125°C

Storage Temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR) ....................................................... -0.5V to VDD +0.6V

Voltage on VDD with respect to VSS .............................................................................................................. 0 to +6.0 V

Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0 to +14 V

Total power Dissipation (Note 1)...............................................................................................................................1.0 W

Maximum Current out of VSS pin ............................................................................................................................300mA

Maximum Current into VDD pin ...............................................................................................................................250mA

Input clamp current, IIK (VI<0 or VI> VDD)...........................................................................................................................±20mA

Output clamp current, IOK (V0 <0 or V0>VDD)....................................................................................................................±20mA

Maximum Output Current sunk by any I/O pin..........................................................................................................25mA

Maximum Output Current sourced by any I/O pin.....................................................................................................25mA

Maximum Current sunk by PORTA, PORTC, and PORTD(combined)...................................................................200mA

Maximum Current sourced by PORTA, PORTC, and PORTE (combined).............................................................200mA

Maximum Current sunk by PORTC and PORTD (combined).................................................................................200mA

Maximum Current sourced by PORTC and PORTD (combined)............................................................................200mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus,

a series resistor of 50-100Ω should be used when applying a “low” level to the MCLRpin rather than pulling

this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage

to the device. This is a stress rating only and functional operation of the device at those or any other condi-

tions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maxi-

mum rating conditions for extended periods may affect device reliability.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 107

PIC14000

13.1

DC Characteristics:

PIC14000

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ + 125°C for automotive,

-40°C ≤ TA ≤ + 85°C for industrial and

DC CHARACTERISTICS

0°C

≤ TA ≤ +70°C for commercial

Operating voltage VDD = 2.7V to 6.0V

Characteristic

Sym

Min Typ† Max Units

Conditions

Supply Voltage

VDD

2.7

4.5

-

6.0

5.5

V

IN osc conﬁguration

HS osc conﬁguration

RAM Data Retention

Voltage (Note 1)

VDR

VPOR

SVDD

IDD

-

1.5

VSS

-

V

Device in SLEEP mode

VDD start voltage to

guarantee Power-On Reset

-

0.05*

-

V

See section on power-on reset for details

VDD rise rate to guarantee

Power-On Reset

V/ms See section on power-on reset for details

Supply Current (Note 2, 5)

TBD TBD

mA IN osc conﬁguration

FOSC = 4 MHz, VDD = 5.0V (Note 4)

TBD TBD

mA FOSC = 4MHz, VDD = 3.0V

mA HS osc conﬁguration

FOSC = 20 MHz, VDD = 5.5V

-

Power Down Current

(Note 3, 5)

IPD

-

TBD TBD

µA VDD=4.0V, WDT enabled,-40°C to +85°C

µA VDD=4.0V, WDT disabled,-0°C to +70°C

µA VDD=4.0V, WDT disabled,-40°C to +85°C

µA VDD=4.0V, WDT disabled,-40°C to +125°C

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD.

MCLR = VDD; WDT enabled/disabled as speciﬁed.

3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and V

.

SS

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2Rext (mA) with Rext in kΩ.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the speciﬁcation. This value is from

characterization and is for design guidance only. This is not tested.

DS40122A-page 108

Preliminary

1995 Microchip Technology Inc.

PIC14000

13.2

DC Characteristics:

PIC14000

Standard Operating Conditions (unless otherwise stated)

Operating temperature

-40°C ≤ TA ≤ + 125°C for automotive,

-40°C ≤ TA ≤ + 85°C for industrial and

DC CHARACTERISTICS

0°C

≤ TA ≤ +70°C for commercial

Operating voltage VDD range as described in DC speciﬁcations and

Table 13-1

Characteristic

Input Low Voltage

I/O ports

Sym

Min Typ† Max Units

Conditions

VIL

with Schmitt Trigger buffer

MCLR, OSC1 (in IN mode)

OSC1 (in HS)

VSS

Vss

-

0.2VDD

0.3VDD

V

Note1

Input High Voltage

I/O ports

VIH

-

with Schmitt Trigger buffer

0.85 VDD

VDD

V

For entire VDD range

PORTC weak pull-up current

IPURB

IIL

50

200

†400

µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2,3)

I/O ports

±1

±5

µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance

µA Vss ≤ VPIN ≤ VDD

MCLR

OSC1

µA Vss ≤ VPIN ≤ VDD

Output Low Voltage

I/O ports

VOL

-

0.6

TBD

0.6

V

IOL = 8.5mA, VDD-4.5V, -40°C to +85°C

TBD

CDAC

OSC2/CLKOUT (HS osc conﬁguration)

IN OSC

IOL = 1.6mA, VDD-4.5V, -40°C to +85°C

TBD

Output High Voltage

I/O ports (Note 3)

VOH

VDD-0.7

TBD

-

V

IOH = -3.0mA, VDD=4.5V, -40°C to +85°C

TBD

RC6, RC7, RD0

CDAC

TBD

OSC2/CLKOUT (HS osc conﬁguration)

IN OSC

VDD-0.7

TBD

IOH = -1.3mA, VDD=4.5V, -40°C to +85°C

Capacitive Loading Specs on Output

Pins

OSC2 pin

COSC2

15

pF In HS mode when external clock is used to

drive OSC1.

All I/O pins and OSC2 (in IN mode)

CIO

Cb

50

pF

2

SCL, SDA in I C mode

400

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In IN oscillator conﬁguration, the OSC1 pin is a Schmitt trigger input.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as coming out of the pin. All I/O ports except RC6, RC7, RD0.

4: The user may use better of the two specs.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 109

PIC14000

13.3

Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

2

1. TppS2ppS

3. TCC:ST

4. Ts

(I C speciﬁcations only)

2

2. TppS

(I C speciﬁcations only)

T

F

Frequency

T

Time

Lowercase subscripts (pp) and their meanings:

pp

ck

CLKOUT

SDI

osc

t0

OSC1

T0CKI

di

io

I/O port

MCLR

mc

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

2

I C only

AA

output access

Bus free

High

Low

High

Low

BUF

2

TCC:ST (I C speciﬁcations only)

CC

HD

ST

DAT

STA

Hold

SU

Setup

DATA input hold

START condition

STO

STOP condition

DS40122A-page 110

Preliminary

1995 Microchip Technology Inc.

PIC14000

13.4

Timing Diagrams and Speciﬁcations

FIGURE 13-1: EXTERNAL CLOCK TIMING

Q1

1

Q2

Q3

Q4

Q1

OSC1

3

4

2

CLKOUT

TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic

Min

Typ†

Max

Units Conditions

FOSC External CLKIN Frequency (Note 1)

DC

—

4

MHz HS osc mode (PIC14000-04)

MHz HS osc mode (PIC14000-20)

20

Oscillator Frequency (Note 1)

TOSC External CLKIN Period (Note 1)

Oscillator Period (Note 1)

4

—

4

MHz HS osc mode(PIC14000-04)

MHz HS osc mode (PIC14000-10)

MHz HS osc mode (PIC14000-20)

4

10

4

20

1

250

100

50

—

ns

HS osc mode (PIC14000-04)

HS osc mode (PIC14000-10)

HS osc mode (PIC14000-20)

HS osc mode (PIC14000-04)

HS osc mode (PIC14000-10)

HS osc mode (PIC14000-20)

TCY = 4/FOSC

—

250

100

50

250

DC

—

2

3

TCY

Instruction Cycle Time (Note 1)

200

10

TOSL, Clock in (OSC1) High or Low Time

TOSH

HS oscillator

4

TOSR, Clock in (OSC1) Rise or Fall Time

TOSF

—

15

ns

HS oscillator

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the

device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or

higher than expected current consumption. All devices are tested to operate at “min.” values with an external

clock applied to the OSC1 pin.

When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 111

PIC14000

FIGURE 13-2: LOAD CONDITIONS

Load condition 1

Load condition 2

VDD/2

RL

CL

VSS

RL = 464 Ω

CL = 50 pF for all pins except OSC2

25 pF for OSC2 output

DS40122A-page 112

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 13-3: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKOUT

13

12

16

19

18

14

I/O Pin

(input)

15

17

I/O Pin

(output)

new value

old value

20, 21

Note: Refer to Figure 13-2 for load conditions

TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ

†

Max

Unit

s

Condi-

tions

10

11

12

13

14

15

16

17

18

TosH2ckL

OSC1↑ to CLKOUT↓

—

15

5

30

ns

Note 1

TosH2ckH OSC1↑ to CLKOUT↑

30

TckR

CLKOUT rise time

15

TckF

CLKOUT fall time

5

15

0.5TCY+20

—

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

CLKOUT ↓ to Port out valid

Port in valid before CLKOUT ↑

Port in hold after CLKOUT ↑

OSC1↑ (Q1 cycle) to Port out valid

—

0.25 TCY+25

0

—

80 - 100

—

OSC1↑ (Q2 cycle) to Port input invalid

TBD

(I/O in hold time)

19

TioV2osH

Port input valid to OSC1↑ (I/O in setup

TBD

—

ns

time)

20

21

TioR

TioF

Tinp

Port output rise time

Port output fall time

—

20

10

—

25

—

ns

22††

PBTN pin high or low time

IN mode

only

23††

Trbp

RC<7:4> change INT high or low time

20

—

ns

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

††

These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in IN Mode where CLKOUT output is 4 x TOSC

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 113

PIC14000

FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER (HS MODE) AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Timeout

32

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O Pin

Note: Refer to Figure 13-2 for load conditions

TABLE 13-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Unit

s

Conditions

30

31

TmcL

Twdt

MCLR Pulse Width (low)

Watchdog Timer Timeout Period

(No Prescaler)

100

7*

—

ns

VDD = 5V, -40°C to +125°C

18

33*

ms VDD = 5V, -40°C to +125°C

32

Tost

Oscillation Start-up Timer Period

1024 TOSC

8 TOSC

ms

TOSC = OSC1 period

IN osc mode

33

34

Tpwrt

Power up Timer Period

28*

72

132*

100

ms VDD = 5V, -40°C to +125°C

TIOZ

I/O High Impedance from MCLR

Low

ns

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

DS40122A-page 114

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 13-5: TIMER0 CLOCK TIMINGS

T0CKI

41

40

42

Note: Refer to Figure 13-2 for load conditions.

TABLE 13-4: TIMER0 CLOCK REQUIREMENTS

Parame-

ter No.

Sym

Characteristic

Min

Typ Max Unit Conditions

†

s

40

41

42

Tt0H

T0CKI High Pulse Width

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20*

10*

—

ns

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

0.5 TCY + 20*

10*

TCY + 40*

N

ns N = prescale value

(1, 2, 4, ..., 256)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 115

PIC14000

2

FIGURE 13-6: I C BUS START/STOP BITS TIMING

SCL

91

81

93

83

92

82

90

80

SDA

START

STOP

Condition

Note: Refer to Figure 13-2 for load conditions

2

TABLE 13-5: I C BUS START/STOP BITS REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min Typ Max Units

Conditions

90

TSU:STA

START condition

Setup time

100 KHZ mode

400 KHz mode

100 KHz mode

400 KHz mode

100 KHZ mode

400 KHz mode

100 KHz mode

400 KHz mode

4700

600

—

Only relevant for repeated

START condition

ns

91

THD:STA

TSU:STO

THD:STO

START condition

Hold time

4000

600

After this period the ﬁrst clock

pulse is generated

92

93

STOP condition

Setup time

4700

600

STOP condition

Hold time

4000

600

DS40122A-page 116

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

FIGURE 13-7: I C BUS DATA TIMING

10933

91202

100

90

19011

SCL

90

80

106

96

107

97

8911

8922

SDA

IN

100

110

99

109

99

109

SDA

OUT

Note: Refer to Figure 13-2 for load conditions

TABLE 13-8: I²C BUS DATA REQUIREMENTS

Parame-

ter No.

Sym

Characteristic

Min

4.0

0.6

Max

—

Units

µs

Conditions

100

THIGH

Clock high time

100 kHz mode

400 kHz mode

PIC14000 must operate at a

minimum of 1.5 MHz

—

µs

PIC14000 must operate at a

minimum of 10 MHz

2

I C Module

1.5 TCY

4.7

—

101

TLOW

Clock low time

100 kHz mode

µs

PIC14000 must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

PIC14000 must operate at a

minimum of 10 MHz

2

I C Module

1.5 TCY

—

102

103

TR

TF

SDA and SCL rise

time

100 kHz mode

400 kHz mode

1000

300

ns

20+0.1 C

C is speciﬁed to be from

10-400 pF

b

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

300

ns

20+0.1 C

C is speciﬁed to be from

b

10-400 pF

90

91

TSU:STA

THD:STA

THD:DAT

TSU:DAT

TSU:STO

TAA

START condition

setup time

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

µs

ns

µs

ns

µs

ns

µs

Only relevant for repeated

START condition

START condition hold 100 kHz mode

time

—

After this period the ﬁrst clock

pulse is generated

400 kHz mode

—

106

107

92

Data input hold time

100 kHz mode

400 kHz mode

—

0

0.9

—

Data input setup time 100 kHz mode

400 kHz mode

250

100

4.7

0.6

—

Note 2

—

STOP condition

setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

—

109

110

Output valid from

clock

3500

—

Note 1

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

C

Bus capacitive loading

—

400

pF

b

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undeﬁned region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.

2

2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement

tSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW

period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the

2

next data bit to the SDA line TR max.+tSU:DAT=1000+250=1250 ns (according to the standard-mode I C bus

speciﬁcation) before the SCL line is released.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 117

PIC14000

14.0 ANALOG SPECIFICATIONS

The following parameters will be provided on the follow-

ing analog peripherals.

• Comparator

• 4-bit current DAC

• Bandgap voltage reference

• Digital-to-analog converter

• Thermistor

• Slope reference

High accuracy in analog-to-digital conversion can be

achieved through proper component and current DAC

selection. Please refer to the Section 8.0 "Analog Mod-

ules for A/D Conversion" for information on the analog

input channels.

DS40122A-page 118

Preliminary

1995 Microchip Technology Inc.

PIC14000

15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC14000

FIGURE 15-1: TYPICAL IPD VS VDD

WATCHDOG TIMER

FIGURE 15-2: TYPICAL IPD VS VDD

WATCHDOG TIMER ENABLED

DISABLED 25°C

25°C

NOT AVAILABLE AT THIS TIME

1995 Microchip Technology Inc.

DS40122A-page 119

PIC14000

FIGURE 15-3: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS VDD

NOT AVAILABLE AT THIS TIME

FIGURE 15-4: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN HS MODE) VS VDD

3.60

3.40

3.20

3.00

2.80

2.60

2.40

2.20

2.00

1.80

1.60

1.40

1.20

1.00

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

VDD (Volts)

DS40122A-page 120

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 15-5: TYPICAL IDD VS FREQ (EXT CLOCK, 25°C)

NOT AVAILABLE AT THIS TIME

FIGURE 15-6: MAXIMUM, IDD VS FREQ (EXT CLOCK, -40° TO +85°C)

NOT AVAILABLE AT THIS TIME

FIGURE 15-7: MAXIMUM IDD VS FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C)

NOT AVAILABLE AT THIS TIME

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 121

PIC14000

FIGURE 15-8: WDT TIMER TIME-OUT

PERIOD VS VDD

FIGURE 15-10: IOH VS VOH, VDD = 3V*

0

50.0

45.0

40.0

35.0

-5

Min @ +85˚C

-10

30.0

25.0

20.0

15.0

10.0

5.0

Max, 85˚C

Max, 70˚C

Typ @25˚C

-15

Typ, 25˚C

Min, 0˚C

-20

Max @ -40˚C

-25

Min, -40˚C

0

0.5

1

1.5

2

2.5

3

VOH (Volts)

2

3

4

5

6

7

V

DD (Volts)

FIGURE 15-11: IOH VS VOH, VDD = 5V*

FIGURE 15-9: TRANSCONDUCTANCE (GM)

OF HS OSCILLATOR VS VDD

0

-5

9000

8000

7000

-10

-15

-20

Min @ 85°C

6000

Max, -40˚C

-25

Typ @ 25°C

5000

4000

-30

-35

Typ, 25˚C

3000

-40

Max @ -40°C

Min, 85˚C

2000

-45

1000

0

-50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

VOH (Volts)

2

3

4

5

6

7

VDD (Volts)

*NOTE: All pins except RC6, RC7, RD0, RD1,OSC2

DS40122A-page 122

Preliminary

1995 Microchip Technology Inc.

PIC14000

FIGURE 15-12: IOL VS VOL, VDD = 3V*

FIGURE 15-13: IOL VS VOL, VDD = 5V*

35

90

80

70

60

Min @ -40°C

30

25

Typ @ 25°C

20

15

10

5

50

40

Min @ +85°C

30

20

10

0

1

0.5

1.5

2

2.5

3

0

0.5

2.5

VOL (Volts)

3.5

4

1.5

2

3

4.5 5

1

VOL (Volts)

*NOTE: All pins except OSC2

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 123

PIC14000

NOTES:

DS40122A-page 124

Preliminary

1995 Microchip Technology Inc.

PIC14000

APPENDIX A: DIFFERENCES

BETWEEN PIC14000

AND PIC16C74

The following is a list of differences between the

PIC14000 and the PIC16C74.

Package Size

Program and Data Memory

• The PIC14000 is a 28-pin device while the

PIC16C74 is in 40- and 44-pin packages. The

PIC14000 includes only Ports A, C and D. PORTB

is used by the PIC16C02 emulation master

device. This address is reserved for emulation

use.

• The PIC14000 program memory space has been

redeﬁned from the PIC16C74. The 4K of

implemented memory has been divided into a pro-

gram space and a 512 word user/calibration

space. Code protect can be enabled for each

space independently.

Clock Oscillator

Power Management

• PIC14000 provides support for HS and IN

oscillation options. The IN oscillator option on the

PIC14000 uses internal RC components with a

ﬁxed nominal frequency of 4 MHz.

• SLEEP/power-down modes have been enhanced

on the PIC14000. Control bits have been added to

the SLPCON register (1Fh) to enable power down

of various analog modules. A new mode "Hiber-

nate" has been added. Refer to Section 10.7 for

details.

Peripherals

• PIC14000 does not include the USART, CCP reg-

ister, Timer1 and Timer2. The registers associated

with these modules are eliminated.

• HIBERNATE mode disables the Watchdog Timer

allowing for software to disable the WDT. Please

refer to the section on the Watchdog Timer for

additional details.

2

• PIC14000 supports the I C protocol only. SPI

protocol is not supported. Registers associated

with SPI protocol exist but are not used. The

2

module should ONLY be programmed as an I C

interface.

2

• The I C interface pins are located on PORTC,

bits 7 and 6. These pins are also used as the

serial programming interface.

• The slope A/D converter on the PIC14000 is

completely different from the successive

approximation A/D on the PIC16C74. Refer to the

A/D Converter section for additional details.

• The PIC14000 includes a bandgap voltage

reference, low-voltage detector and other analog

modules not found on the PIC16C74. Refer to

Section 8.0 for a complete list of analog modules

on the PIC14000.

• PIC14000 provides hardware support for

controlling two external switching regulators for

battery charging. A logarithmic DAC and

comparator is required for each socket. This

circuit can also be used as a current ﬂow detector

to exit from SLEEP mode.

• The PORTB interrupt-on-change has been

relocated to RC<7:4>.

• The external interrupt feature has been moved

from RB0 to the OSC1/PBTN pin. This interrupt is

available only in IN mode.

• Timer0 external clock option (T0CKI) is moved to

RC3 pin.

• PORTC electrical characteristics are different

from the PIC16C74. Refer to Section 13.0 of the

PIC14000 data sheet and Section 18.0 in the

PIC16C74 data sheet for details.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 125

PIC14000

Differences between PIC14000 and PIC16C74

in the Register File Map

Differences in Special Registers between

PIC14000 and PIC16C74

This section details the differences in the register ﬁle

map between the PIC14000 and the PIC16C74. Port-

ing any code developed on the PIC16C74 to the

PIC14000 must take these differences into account.

Refer to Figure 4-2 for names of the speciﬁc PIC14000

registers. In some cases the PIC14000 register names

are different from the PIC16C74 registers. Note that all

memory locations speciﬁed at UNIMPLEMENTED are

read as 0’s. The differences between the PIC16C74

and PIC14000 register ﬁles are:

This section details the differences in the special regis-

ters between the PIC14000 and the PIC16C74. Porting

any code developed on the PIC16C74 to the PIC14000

must take these differences into account. In cases

where registers have the same name but the bits have

different functions, the differences in the individual bits

are detailed. In cases where the register name and

functionality has changed, only the register name is

detailed. Refer to Table 4-3 for the deﬁnitions of the

PIC14000 registers.

File

Address

Bit

PIC16C74

IRP

PIC14000

RESERVED

PIC16C74

PIC14000

03

BIT7

BIT6

06

PORTB

PORTE

PIR2

RESERVED

RP1

09

UNIMPLEMENTED

ADTMRL

0D

0E

0F

10

06

08

09

0B

PORTB

PORTD

PORTE

INTE

RESERVED

TMR1L

TMR1H

T1CON

TMR2

ADTMRH

UNIMPLEMENTED

I2CBUF

BIT4

11

12

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

TRIS B

BIT1

BIT0

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

INTF

RESERVED

WUIF

13

RBIF

14

I2CCON

0C

PSPIF

ADIF

15

ADCAPL

NOT USED

PBIF

16

ADCAPH

RCIF

17

UNIMPLEMENTED

RESERVED

TXIF

18

SSPIF

CCPIF

TMR2IF

TMR1IF

I2CIF

19

RCIF

1A

1B

1C

1D

1E

86

ADCIF

OVFIF

89

TRIS E

UNIMPLEMENTED

8D

8F

92

PIE2

UNIMPLEMENTED SLPCON

PR2

UNIMPLEMENTED

93

SSPADD

SSPSTAT

TXSTA

SPBRG

I2CADD

94

I2CSTAT

98

UNIMPLEMENTED

99

9B

9C

9D

9E

UNIMPLEMENTED LDACA

UNIMPLEMENTED LDACB

UNIMPLEMENTED CHGCON

UNIMPLEMENTED MISC

DS40122A-page 126

Preliminary

1995 Microchip Technology Inc.

PIC14000

2

Figure 7-16: Operation of the I C in Idle Mode,

RCV Mode or Xmit Mode ...............................55

LIST OF EXAMPLES

Example 3-1: Instruction Pipeline Flow ...................................11

Example 4-1: Call Of A Subroutine In Page 1 from

Figure 8-1: A/D Block Diagram ........................................59

Figure 8-2: Example A/D Conversion Cycle ....................60

Figure 8-3: A/D Capture Timer (Low Byte) ......................60

Figure 8-4: A/D Capture Timer (High Byte) .....................60

Figure 8-5: A/D Capture Register (Low Byte) ..................60

Figure 8-6: A/D Capture Register (High Byte) ................60

Figure 9-1: Current Bias and Zeroing Network ................66

Figure 9-2: Voltage Regulator (Example for a Battery

Pack Application) ...........................................67

Page 0 ..............................................................24

Example 4-2: Indirect Addressing............................................25

Example 5-1: Initializing PORTA .............................................27

Example 5-2: Initializing PORTC.............................................29

Example 5-3: Initializing PORTD ............................................36

Example 5-4: Read Modify Write Instructions on an

I/O Port .............................................................36

Example 6-1: Changing Prescaler (TMR0→WDT) .................42

Example 6-2: Changing Prescaler (WDT→TMR0) .................42

Example 10-1: Saving W Register and Status in RAM .............82

Figure 9-3: DAC Transfer Function ..................................69

Figure 9-4: Charge/Current Flow Detect Control

Register .........................................................70

LIST OF FIGURES

Figure 9-5: LDACA Register ............................................71

Figure 9-6: LDACB Register ............................................71

Figure 9-7: Charge Control/Current Flow Detect Block

Diagram (One of Two Shown) .......................72

Figure 10-1: Crystal/Ceramic Resonator Operation

(HS OSC Configuration) ................................74

Figure 10-2: External Clock Input Operation

(HS OSC Configuration) ................................74

Figure 10-3: External Parallel Resonant Crystal

Oscillator Circuit ............................................74

Figure 10-4: External Series Resonant Crystal

Oscillator Circuit ............................................75

Figure 10-5: MISC Register ...............................................76

Figure 10-6: External Power-on Reset Circuit

Figure 3-1: PIC14000 Simplified Block Diagram ............... 8

Figure 3-2: Clock/Instruction Cycle ................................. 11

Figure 4-1: PIC14000 Program Memory Map and Stack 13

Figure 4-2: Register File Map .......................................... 14

Figure 4-3: Status Register ............................................. 17

Figure 4-4: Events Affecting PD/TO Status Bits .............. 18

Figure 4-5: Option Register ............................................. 19

Figure 4-6: INTCON Register .......................................... 20

Figure 4-7: PIE1 Register ................................................ 21

Figure 4-8: PIR1 Register ................................................ 22

Figure 4-9: PCON Register ............................................. 23

Figure 4-10: Loading of PC in Different Situations ............ 24

Figure 4-11: Indirect/indirect Addressing ........................... 25

Figure 5-1: PORTA Block Diagram ................................. 27

Figure 5-2: PORTA Data Register ................................... 28

Figure 5-3: Summary of Porta Registers ......................... 28

Figure 5-4: Block Diagram of PORTC <7:4> Pins ........... 29

Figure 5-5: Block Diagram of PORTC <3:0> Pins ........... 30

Figure 5-6: PORTC Data Register .................................. 31

Figure 5-7: TRISC Register ............................................. 32

Figure 5-8: Block Diagram of PORTD <7:4> Pins ........... 33

Figure 5-9: Block Diagram of PORTD<3:0> Pins ............ 33

Figure 5-10: PORTD Data Register .................................. 34

Figure 5-11: TRISD Register ............................................. 35

Figure 5-12: Successive I/O Operation ............................. 37

Figure 6-1: Timer0 and Watchdog Timer Block

(for Slow VDD Power-up) ...............................78

Figure 10-7: Interrupt Logic Schematic ..............................80

Figure 10-8: External (Osc1/PBTN) Interrupt Timing .........81

Figure 10-9: Watchdog Timer Block Diagram

(with Timer0) ..................................................83

Figure 10-10:SLPCON Register .........................................86

Figure 10-11:Wake-up from Sleep Through Interrupt .........87

Figure 10-12: Configuration Fuse Word .............................88

Figure 10-13:Typical In-system Serial Programming

Connection ....................................................89

Figure 11-1: General Format for Instructions .....................91

Figure 12-1: PICMASTER System Configuration ............103

Figure 13-1: External Clock Timing ..................................111

Figure 13-2: Load Conditions ...........................................112

Figure 13-3: CLKOUT and I/O Timing .............................113

Figure 13-4: Reset, Watchdog Timer, Oscillator Start-up

Timer and Power-up Timer Timing ..............114

Diagram ........................................................ 39

Figure 6-2: Timer0 (TMR0) Timing:

Internal Clock/no Prescale............................. 40

Figure 6-3: Timer0 (TMR0) Timing:

Internal Clock/Prescale 1:2 ........................... 40

Figure 13-5: Timer0 Clock Timings ..................................115

Figure 6-4: Timer0 (TMR0) Interrupt Timing ................... 40

Figure 6-5: Timer0 Timing with External Clock ............... 41

2

Figure 13-6: I C Bus Start/Stop Bits Timing ....................116

2

Figure 13-7: I C Bus Data Timing ....................................117

2

Figure 7-1: I C Start and Stop Conditions ....................... 43

Figure 15-1: Typical IPD vs VDD Watchdog Timer

Disabled 25°C ..............................................119

Figure 15-2: Typical IPD vs VDD Watchdog Timer

Enabled 25°C ..............................................119

Figure 15-3: VTH (Input Threshold Voltage) of

I/O Pins vs VDD.............................................120

Figure 15-4: VTH (Input Threshold Voltage) of

OSC1 Input (in HS Mode) vs VDD ...............120

Figure 15-5: Typical IDD vs Freq. (Ext Clock, 25°C) ........121

Figure 15-6: Maximum, IDD vs Freq. (Ext Clock,

–40° to +85°C) .............................................121

Figure 15-7: Maximum IDD vs Freq. with A/D Off

(Ext Clock, –55° to +125°C) ........................121

Figure 15-8: WDT Timer Time-out Period vs VDD ...........122

Figure 15-9: Transconductance (gm) of HS Oscillator

vs VDD .......................................................122

2

Figure 7-2: I CSTAT: I C Port Status Register ............... 44

2

Figure 7-3: I CCON: I C Port Control Register ............... 45

2

Figure 7-4: I C 7-Bit Address Format .............................. 46

2

Figure 7-5: I C 10-bit Address Format ............................ 46

2

Figure 7-6: I C Slave-Receiver Acknowledge ................. 47

2

Figure 7-7: Sample I C Data Transfer ............................. 47

Figure 7-8: Master – Transmitter Sequence .................... 48

Figure 7-9: Master – Receiver Sequence ........................ 48

Figure 7-10: Combined Format ......................................... 48

Figure 7-11: Multi-master Arbitration (2 Masters) .............. 49

2

Figure 7-12: I C Clock Synchronization ............................ 49

2

Figure 7-13: I C Block Diagram ........................................ 50

2

Figure 7-14: I C Waveforms for Reception

(7-Bit Address) ............................................. 52

2

Figure 7-15: I C Waveforms for Transmission

(7-Bit Address) .............................................. 53

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 127

PIC14000

Figure 15-10: IOH vs VOH, VDD= 3.0 V ............................ 122

Figure 15-11: IOH vs VOH VDD = 5.0 V ............................ 122

Figure 15-12: VOL vs VOL, VDD = 3.0 V ............................ 123

Figure 15-13: IOL vs VOL, VDD = 5.0 V ............................. 123

Table 8-6: Ramp Capacitor Selection

(Examples for Full Scale of 3.5V & 1.5V) ..... 64

Table 9-1: Digital DAC Decode (Course Adjust)............ 68

Table 9-2: Digital DAC Decode (Fine Adjust) ................ 69

Table 10-1: Ceramic Resonators..................................... 74

Table 10-2: Capacitor Selection for Crystal Oscillator..... 74

Table 10-3: Status Bits and their Significance................. 77

Table 10-4: Reset Condition for Special Registers.......... 78

Table 10-5: Reset Condition for Registers....................... 79

Table 10-6: Summary of Power Management Options.... 84

Table 11-1: OPCODE Field Descriptions ........................ 91

Table 11-2: PIC14000 Instruction Set.............................. 92

Table 12-1: Development System Packages................. 105

Table 13-1: External Clock Timing Requirements ......... 111

Table 13-2: CLKOUT and I/O Timing Requirements..... 113

Table 13-3: Reset, Watchdog Timer, Oscillator

LIST OF TABLES

Table 3-1: Pin Descriptions.............................................. 9

Table 4-1: Calibration Data Formats.............................. 13

Table 4-2: Calibration Constant Addresses ................... 14

Table 4-3: Special Registers for the PIC14000.............. 15

Table 4-4: PD/TO Status after Reset ............................. 18

Table 5-1: Reset Condition for Registers....................... 35

Table 6-1: Summary of TMR0 Registers...................... 42

Table 6-2: Registers Associated with Timer0................. 42

2

Table 7-1: I C Bus Terminology..................................... 46

Table 7-2: Data Transfer Received Byte Actions........... 51

2

Start-up Timer and Power-up Timer

Requirements ............................................. 114

Table 7-3: Registers Associated with I C Operation...... 54

Table 8-1: A/D Channel Select Decode ......................... 61

Table 8-2: A/D CDAC Current DAC Output Decode...... 62

Table 8-3: A/D Control and Status Register 1................ 63

Table 8-4: A/D Control and Status Register 2................ 63

Table 8-5: PORTA and PORTD Configuration

Table 13-4: Timer0 Clock Requirements....................... 115

2

Table 13-5: I C Bus Start/Stop Bits Requirements........ 116

2

Table 13-8: I C Bus Data Requirements ....................... 117

Select Decode............................................... 63

DS40122A-page 128

Preliminary

1995 Microchip Technology Inc.

PIC14000

CONNECTING TO MICROCHIP BBS

Connect worldwide to the Microchip BBS using the

CompuServe communications network. In most

cases a local call is your only expense. The Microchip

BBS connection does not use CompuServe member-

ship services, therefore you do not need CompuServe

membership to join Microchip's BBS.

Trademarks:

PIC is a registered trademark of Microchip

Technology Incorporated in the U.S.A. The

Microchip logo and name are registered

trademarks of Microchip Technology Inc.

There is no charge for connecting to the BBS, except

for a toll charge to the CompuServe access number,

where applicable. You do not need to be a Com-

puServe member to take advantage of this connection

(you never actually log in to CompuServe).

PICMASTER, PICSTART, PRO MATE, and

fuzzyLAB are trademarks, and SQTP is a service

mark of Microchip Technology Incorporated.

fuzzyTECH is a registered trademark of Inform

Software Corporation.

The procedure to connect will vary slightly from country

to country. Please check with your local CompuServe

agent for details if you have a problem. CompuServe

service allows multiple users at baud rates up to 14400

bps.

2

I C is a trademark of Philips Corporation.

IBM, IBM PC-AT are registered trademarks of

International Business Machines Corp.

Pentium is a trademark of Intel Corporation.

The following connect procedure applies in most loca-

tions:

MS-DOS , MS Windows and Windows are

registered trademarks of Microsoft Corporation.

1. Set your modem to 8 bit, No parity, and One stop

(8N1). This is not the normal CompuServe set-

ting which is 7E1.

CompuServe is a registered trademark of

CompuServe Incorporated.

2. Dial your local CompuServe access number.

All other trademarks mentioned herein are the

property of their respective companies.

3. Depress <ENTER > and a garbage string will

appear because CompuServe is expecting a

7E1 setting.

4. Type +, depress <ENTER > and Host Name:

will appear.

5. Type MCHIPBBS, depress < ENTER > and

you will be connected to the Microchip BBS.

In the United States, to ﬁnd CompuServe's phone num-

ber closest to you, set your modem to 7E1 and dial

(800) 848-4480 for 300-2400 baud or (800) 331-7166

for 9600-14400 baud connection. After the system

responds with Host Name:, type

NETWORK, depress < ENTER

>

and follow CompuServe's directions.

For voice information (or calling from overseas), you

may call (614) 457-1550 for your local CompuServe

number.

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 129

PIC14000

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

To:

Technical Publications Manager

Reader Response

Total Pages Sent

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

Literature Number:

DS40122A

Device:

PIC14000

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefullness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

DS40122A-page 130

Preliminary

1995 Microchip Technology Inc.

PIC14000

NOTES:

1995 Microchip Technology Inc.

Preliminary

DS40122A-page 131

PIC14000

PIC14000 Product Identiﬁcation System

To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed

sales ofﬁces.

PART NO. -XX X /XX XXX

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Package:

SP

SO

SS

JW

=

300 mil PDIP

300 mil SOIC (Gull Wing, 300 mil body)

209 mil SSOP

Windowed CERDIP

Temperature

Range:

-

I

E

=

0˚C to +70˚C (T for tape/reel)

-40˚C to +85˚C (S for tape/reel)

-40˚C to +125˚C

Frequency

Range:

04

20

=

4 MHz

20 MHz

Device:

PIC14000

EUROPE

AMERICAS

AMERICAS (continued)

United Kingdom

Corporate Ofﬁce

New York

Arizona Microchip Technology Ltd.

Unit 6, The Courtyard

Meadow Bank, Furlong Road

Bourne End, Buckinghamshire SL8 5AJ

Tel: 44 0 1628 851077 Fax: 44 0 1628 850259

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 602 786-7200 Fax: 602 786-7277

Technical Support: 602 786-7627

Web: http://www.mchip.com/mIcrochip

Microchip Technology Inc.

150 Motor Parkway, Suite 416

Hauppauge, NY 11788

Tel: 516 273-5305 Fax: 516 273-5335

San Jose

France

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Arizona Microchip Technology SARL

2 Rue du Buisson aux Fraises

91300 Massy - France

Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 Muenchen, Germany

Tel: 49 89 627 144 0 Fax: 49 89 627 144 44

Atlanta

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770 640-0034 Fax: 770 640-0307

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 408 436-7950 Fax: 408 436-7955

ASIA/PACIFIC

Hong Kong

Microchip Technology

Unit No. 3002-3004, Tower 1

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T. Hong Kong

Tel: 852 2 401 1200 Fax: 852 2 401 3431

Italy

Tel: 508 480-9990

Fax: 508 480-8575

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Pegaso Ingresso No. 2

Via Paracelso 23, 20041

Agrate Brianza (MI) Italy

Tel: 39 039 689 9939 Fax: 39 039 689 9883

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 708 285-0071 Fax: 708 285-0075

Dallas

Microchip Technology Inc.

14651 Dallas Parkway, Suite 816

Dallas, TX 75240-8809

Tel: 214 991-7177 Fax: 214 991-8588

Dayton

Microchip Technology Inc.

35 Rockridge Road

Korea

Microchip Technology

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku,

Seoul, Korea

Tel: 82 2 554 7200 Fax: 82 2 558 5934

Singapore

Microchip Technology

200 Middle Road

#10-03 Prime Centre

Singapore 188980

Tel: 65 334 8870 Fax: 65 334 8850

Taiwan

JAPAN

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shin Yokohama

Kohoku-Ku, Yokohama

Kanagawa 222 Japan

Tel: 81 45 471 6166 Fax: 81 45 471 6122

Englewood, OH 45322

Tel: 513 832-2543 Fax: 513 832-2841

Los Angeles

9/22/95

Microchip Technology

10F-1C 207

Microchip Technology Inc.

18201 Von Karman, Suite 455

Irvine, CA 92715

Tung Hua North Road

Taipei, Taiwan, ROC

Tel: 886 2 717 7175 Fax: 886 2 545 0139

Tel: 714 263-1888 Fax: 714 263-1338

Printed in the USA, 9/95

1995, Microchip Technology Inc.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty

is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property

rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip.

No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights

reserved. All other trademarks mentioned herein are the property of their respective companies.

DS40122A-page 132

Preliminary

1995 Microchip Technology Inc.


型号：	PIC14000T-04E/SS
厂家：	MICROCHIP
描述：	8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28, 0.209 INCH, SSOP-28 可编程只读存储器光电二极管
文件：	总132页 (文件大小：832K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC14000T-04E/SS [MICROCHIP]

相关型号：

PIC14000T-04I/SO

PIC14000T-04I/SS

PIC14000T-04I/SSG

PIC14000T-20/SO

PIC14000T-20/SS

PIC14000T-20I/SO

PIC14000T-20I/SS

PIC1470-KTQ

PIC1470-KTW

PIC1470KT

PIC1471KT

PIC14R7-MTQ