PIC14000 [MICROCHIP]
28-Pin Programmable Mixed Signal Controller; 28引脚可编程的混合信号控制器
| 型号： | PIC14000 |
| 厂家： | 
MICROCHIP |
| 描述： | 28-Pin Programmable Mixed Signal Controller |
| 文件： | 总152页 (文件大小：943K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC14000
28-Pin Programmable Mixed Signal Controller
High-Performance RISC CPU:
Pin Diagram
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
PDIP, SOIC, SSOP, Windowed CERDIP
28
• Operating speed: DC - 20 MHz clock input
• 4096 x 14 on-chip EPROM program memory
• 192 x 8 general purpose registers (SRAM)
• 6 internal and 5 external interrupt sources
• 38 special function hardware registers
• Eight-level hardware stack
RA2/AN2
• 1
2
RA1/AN1
RA0/AN0
27
26
25
24
23
22
21
20
19
18
17
16
15
RA3/AN3
RD4/AN4
RD5/AN5
RD6/AN6
RD7/AN7
CDAC
3
RD3/REFB
RD2/CMPB
RD1/SDAB
RD0/SCLB
OSC2/CLKOUT
OSC1/PBTN
VDD
4
5
6
7
SUM
8
VSS
9
Analog Peripherals Features:
RC0/REFA
RC1/CMPA
RC2
10
11
12
13
14
VREG
RC7/SDAA
RC6/SCLA
RC5
• Slope Analog-to-Digital (A/D) converter
- Eight external input channels including two
channels with selectable level shift inputs
- Six internal input channels
RC3/T0CKI
RC4
MCLR/VPP
- 16-bit programmable timer with capture
register
Digital Peripherals Features:
- 16 ms maximum conversion time at maxi-
mum (16-bit) resolution and 4 MHz clock
- 4-bit programmable current source
• Internal bandgap voltage reference
• Factory calibrated with calibration constants
stored in EPROM
• 22 I/O pins with individual direction control
• High current sink/source for direct LED drive
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
• 16-bit A/D timer: can be used as a general
purpose timer
• On-chip temperature sensor
2
• I C serial port compatible with System
• Voltage regulator control output
• Two comparators with programmable references
• On-chip low voltage detector
Management Bus
CMOS Technology:
Special Microcontroller Features:
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide-operating voltage range (2.7V to 6.0V)
• Commercial and Industrial Temperature Range
• Low power dissipation (typical)
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
- < 3 mA @5V, 4 MHz operating mode
- < 300 µA @3V (Sleep mode: clocks stopped
with analog circuits active)
- < 5 µA @3V (Hibernate mode: clocks
stopped, analog inactive, and WDT disabled)
• Multi-segment programmable code-protection
• Selectable oscillator options
-
-
Internal 4 MHz oscillator
External crystal oscillator
•
Serial in-system programming (via two pins)
Applications:
• Battery Chargers
• Battery Capacity Monitoring
• Uninterruptable Power Supply Controllers
• Power Management Controllers
• HVAC Controllers
• Sensing and Data Acquisition
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 1
PIC14000
TABLE OF CONTENTS
1.0: General Description........................................................................................................................... 3
2.0: Device Varieties ................................................................................................................................ 5
3.0: Architectural Overview ...................................................................................................................... 7
4.0: Memory Organization...................................................................................................................... 13
5.0: I/O Ports .......................................................................................................................................... 25
6.0: Timer Modules................................................................................................................................. 37
2
7.0: Inter-integrated Circuit Serial Port (I C )........................................................................................ 41
8.0: Analog Modules for A/D Conversion ............................................................................................... 57
9.0: Other Analog Modules..................................................................................................................... 65
10.0: Special Features of the CPU........................................................................................................... 75
11.0: Instruction Set Summary................................................................................................................. 91
12.0: Development Support.................................................................................................................... 103
13.0: Electrical Characteristics for PIC14000..........................................................................................107
14.0: Analog Specifications: PIC14000-04 (Commercial, Industrial)...................................................... 123
Appendix A:PIC16/17 Microcontrollers ....................................................................................................133
Index.........................................................................................................................................................143
PIC14000 Product Identification System ..................................................................................................149
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted
to a new publishing software package which we believe will enhance our entire documentation process and product.
As in any conversion process, information may have accidently been altered or deleted. We have spent an excep-
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DS40122B-page 2
Preliminary
1996 Microchip Technology Inc.
PIC14000
The internal band-gap reference is used for calibrating
the measurements of the analog peripherals. The
calibration factors are stored in EPROM and can be
used to achieve high measurement accuracy.
1.0
GENERAL DESCRIPTION
The PIC14000 features include medium to high reso-
lutionA/D conversion (10 to 16 bits), temperature sens-
ing, closed loop charge control, serial communication,
and low power operation.
Power savings modes are available for portable appli-
cations. The SLEEP and HIBERNATE modes offer dif-
ferent levels of power savings. The PIC14000 can
wake up from these modes through interrupts or reset.
The PIC14000 uses a RISC Harvard architecture CPU
with separate 14-bit instruction and 8-bit data buses. A
two-stage instruction pipeline allows all instructions to
execute in a single cycle, except for program branches,
which require two cycles. A total of 35 instructions are
available. Additionally, a large register set is included.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
PIC16/17 microcontrollers typically achieve a 2:1 code
compression and a 4:1 speed improvement over other
8-bit microcontrollers.
The PIC14000 fits perfectly in applications for battery
charging, capacity monitoring, and data logging. The
EPROM technology makes customization of
application programs (battery characteristics, feature
sets, etc.) extremely fast and convenient. The small
footprint packages make this microcontroller based
mixed signal device perfect for all applications with
space limitations. Low-cost, low-power, high perfor-
mance, ease of use and I/O flexibility make the
PIC14000 very versatile in other applications such as
temperature monitors/controllers.
Features:
The PIC14000 is a 28-pin device with these features:
• 4K of EPROM
• 192 bytes of RAM
•
22 I/O pins
The analog peripherals include:
• 8 external analog input channels, two with level
shift inputs
1.1
Family and Upward Compatibility
• 6 internal analog input channels
• 2 comparators with programmable references
• A bandgap reference
Code written for PIC16C6X/7X can be easily ported to
the PIC14000 (see Appendix A).
1.2
Development Support
• An internal temperature sensor
• A programmable current source
The PIC14000 is supported by a full-featured macro
assembler, a software simulator, an in-circuit emulator,
a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
2
In addition, the I C serial port through a multiplexer
2
low-cost development programmer and
a
supports two separate I C channels.
A special oscillator option allows either an internal
4 MHz oscillator or an external crystal oscillator. Using
the internal 4 MHz oscillator requires no external com-
ponents.
The PIC14000 contains three timers, the Watchdog
Timer (WDT), Timer0 (TMR0), and A/D Timer
(ADTMR). The Watchdog Timer includes its own
on-chip RC oscillator providing protection against
software lock-up. TMR0 is a general purpose 8-bit
timer/counter with an 8-bit prescaler. It may be clocked
externally using the RC3/T0CKI pin. The ADTMR is
intended for use with the slope A/D converter, but can
also be used as a general purpose timer. It has an
associated capture register which can be used to mea-
sure the time between events.
An internal low-voltage detect circuit allows for tracking
of voltage levels. Upon detecting the low voltage con-
dition, the PIC14000 can be instructed to save its oper-
ating state then enter an idle state.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 3
PIC14000
NOTES:
DS40122B-page 4
Preliminary
1996 Microchip Technology Inc.
PIC14000
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. The PIC14000 Product Selection System
section at the end of this data sheet provides the
devices options to be selected for your specific applica-
tion and production requirements. When placing
orders, please use the “PIC14000 Product Identifica-
tion System” at the back of this data sheet to specify the
correct part number.
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and
fuse options already programmed by the factory.
Certain code and prototype verification procedures do
apply before production shipments are available.
Please contact your local Microchip Technology sales
office for more details.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
The UV erasable version can be erased and
reprogrammed to any of the configuration modes.
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Note: Please note that erasing the device will
also erase the pre-programmed calibration
factors. Please refer to AN621 for more
information.
Microchip's PICSTART , PICSTART-PLUS and
PRO MATE programmers all support programming of
the PIC14000. Third party programmers also are avail-
able; refer to the Microchip Third Party Guide for a list
of sources.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 5
PIC14000
NOTES:
DS40122B-page 6
Preliminary
1996 Microchip Technology Inc.
PIC14000
The ALU is capable of addition, subtraction, shift, and
logical operations. Unless otherwise mentioned,
arithmetic operations are two's complement. In
two-operand instructions, typically one operand is the
working register (W register). The other operand is a
file register or an immediate constant. In single
operand instructions, the operand is either the
W register or a file register.
3.0
ARCHITECTURAL OVERVIEW
The PIC14000 addresses 4K x 14 program memory.All
program memory is internal. The PIC14000 can directly
or indirectly address its register files or data memory.All
special function registers including the program counter
are mapped in the data memory. The PIC14000 has an
orthogonal instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC14000 simple yet efficient. In addition, the learning
curve is reduced significantly.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
The PIC14000 contains an 8-bit ALU and working
register. The ALU performs arithmetic and Boolean
functions between data in the working register and any
register file.
A simplified block diagram for the PIC14000 is shown
in Figure 3-1, its corresponding pin description is
shown in Table 3-1.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 7
PIC14000
FIGURE 3-1: PIC14000 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
4K x 14
192 x 8
Program
Bus
14
RAM Addr (1)
9
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
FSR reg
PORTC
RC0/REFA
RC1/CMPA
RC2
STATUS reg
8
RC3/T0CKI
RC4
RC5
RC6/SCLA
RC7/SDAA
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/PBTN
OSC2/CLKOUT
Low Voltage
Detector
PORTD
RD0/SCLB
RD1/SDAB
Internal
Oscillator
RD2/CMPB
RD3/REFB
RD4/AN4
RD5/AN5
MCLR/VPP VDD, VSS
RD6/AN6
RD7/AN7
Programmable
Reference A & B
with Comparators
Timer0
Voltage
Regulator
Support
I2C
Serial Port
Temp
Sensor
Bandgap
Reference
Slope A/D
VREG
SUM CDAC
Note 1: Higher order bits are from the STATUS register.
DS40122B-page 8
Preliminary
1996 Microchip Technology Inc.
PIC14000
TABLE 3-1:
PIN DESCRIPTIONS
Pin
I/O
Pin Type
Input Output
Pin Name
Description
No.
CDAC
22
O
—
AN
A/D ramp current source output. Normally connected to
external capacitor to generate a linear voltage ramp.
RA0/AN0
RA1/AN1
2
1
I/O
I/O
AN/ST
AN/ST
CMOS
CMOS
Analog input channel 0. This pin can also serve as a
general-purpose I/O.
Analog input channel 1. This pin can connect to a level
shift network. If enabled, a +0.5V offset is added to the
input voltage. This pin can also serve as a general-
purpose I/O.
RA2/AN2
RA3/AN3
SUM
28
27
21
I/O
I/O
O
AN/ST
AN/ST
—
CMOS
CMOS
AN
Analog input channel 2. This pin can also serve as a
general purpose digital I/O.
Analog input channel 3. This pin can also serve as a gen-
eral purpose digital I/O.
AN1 summing junction output. This pin can be connected
to an external capacitor for averaging small duration
pulses.
RC0/REFA
RC1/CMPA
RC2
19
18
17
16
15
I/O-PU
I/O-PU
I/O-PU
I/O-PU
I/O-PU
ST
ST
ST
ST
ST
CMOS
CMOS
CMOS
CMOS
CMOS
LED direct-drive output or programmable reference A out-
put. This pin can also serve as a GPIO. If enabled, this
pin has a weak internal pull-up to VDD.
LED direct-drive output or comparator A output. This pin
can also serve as a GPIO. If enabled, this pin has a weak
internal pull-up to VDD.
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, this pin has a weak internal pull-up to
VDD
RC3/T0CKI
RC4
LED direct-drive output. This pin can also serve as a
GPIO, or an external clock input for Timer0. If enabled,
this pin has a weak internal pull-up to VDD.
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to VDD.
RC5
13
12
I/O-PU
I/O
ST
CMOS
LED direct-drive output. This pin can also serve as a
GPIO. If enabled, a change on this pin can cause a CPU
interrupt. If enabled, this pin has a weak internal pull-up
to VDD.
RC6/SCLA
ST/SM
NPU/OD
General purpose I/O. If enabled, is multiplexed as
2
(No P-diode) synchronous serial clock for I C interface. Also is the
serial programming clock. If enabled, a change on this pin
can cause a CPU interrupt. This pin has an N-channel
2
pull-up device which is disabled in I C mode.
RC7/SDAA
11
I/O
ST/SM
NPU/OD
General purpose I/O. If enabled, is multiplexed as
2
(No P-diode) synchronous serial data I/O for I C interface. Also is the
serial programming data line. If enabled, a change on this
pin can cause a CPU interrupt. This pin has an N-channel
2
pull-up device which is disabled in I C mode.
RD0/SCLB
RD1/SDAB
6
5
I/O
I/O
ST/SM
ST/SM
NPU/OD
General purpose I/O. If enabled, is multiplexed as
2
(No P-diode) synchronous serial clock for I C interface. This pin has an
2
N-channel pull-up device which is disabled in I C mode.
NPU/OD
General purpose I/O. If enabled, is multiplexed as
2
(No P-diode) synchronous serial data I/O for I C interface. This pin has
2
an N-channel pull-up device which is disabled in I C
mode.
RD2/CMPB
4
I/O-PU AN/ST CMOS
General purpose I/O or comparator B output.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 9
PIC14000
TABLE 3-1:
PIN DESCRIPTIONS (CONTINUED)
Pin
No.
Pin Type
Input Output
Pin Name
I/O
Description
RD3/REFB
3
I/O-PU AN/ST CMOS
General purpose I/O or programmable reference B
output.
RD4/AN4
RD5/AN5
26
25
I/O
I/O
AN/ST CMOS
AN/ST CMOS
Analog input channel 4. This pin can also serve as a
GPIO.
Analog input channel 5. This pin can connect to a level
shift network. If enabled, a +0.5V offset is added to the
input voltage. This pin can also serve as a GPIO.
RD6/AN6
RD7/AN7
VREG
24
23
10
8
I/O
I/O
O
AN/ST CMOS
AN/ST CMOS
Analog input channel 6. This pin can also serve as a
GPIO.
Analog input channel 7. This pin can also serve as a
GPIO.
—
AN
—
This pin is an output to control the gate of an external
N-FET for voltage regulation.
OSC1/PBTN
I-PU
ST
IN Mode: Input with weak pull-up resistor, can be used to
generate an interrupt.
HS Mode: External oscillator input.
OSC2/
7
O
—
CMOS
IN Mode: General purpose output.
CLKOUT
HS Mode: External oscillator/clock output.
MCLR/VPP
14
I/PWR
ST
Master clear (reset) input / programming voltage input.
This pin is an active low reset to the device.
VDD
VSS
9
PWR
GND
Positive supply connection
Return supply connection
20
Legend:
Type:
Definition:
TTL
CMOS
ST
TTL-compatible input
CMOS-compatible input or output
Schmitt Trigger input, with CMOS levels
SMBus compatible input
SM
OD
Open-drain output. An external pull-up resistor is required if this pin is used as an output.
N-channel pull-up. This pin will pull-up to approximately VDD - 1.0V when outputting a logical ‘1’.
Weak internal pull-up (10K-50K ohms)
NPU
PU
No-P diode
No P-diode to VDD. This pin may be pulled above the supply rail (to 6.0V maximum).
Analog input or output
AN
DS40122B-page 10
Preliminary
1996 Microchip Technology Inc.
PIC14000
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1 or the internal oscillator) is
internally divided by four to generate four
non-overlapping quadrature clocks, namely Q1, Q2,
Q3 and Q4. The program counter (PC) is incremented
every Q1, the instruction is fetched from the program
memory and latched into the instruction register in Q4.
The instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
Phase
Clock
Q4
PC
PC
PC+1
PC+2
CLKOUT
(IN mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Execute 1
Fetch 2
Fetch 1
1. MOVLW
2. MOVWF
3. CALL
4. BSF
55h
PORTB
SUB_1
PORTA, BIT3
Execute 2
Fetch 3
Execute 3
Fetch 4
F
Flush
Fetch SUB_1
All instructions are single cycle, except for program branches. These take two cycles
since the fetched instruction is “flushed” from the pipeline while the new instruction is
being fetched and then executed.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 11
PIC14000
NOTES:
DS40122B-page 12
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.1.1
CALIBRATION SPACE
4.0
MEMORY ORGANIZATION
The calibration space is not used for instructions. This
section stores constants and factors for the arithmetic
calculations to calibrate the analog measurements.
4.1
Program Memory Organization
The PIC14000 has a 13-bit program counter capable of
addressing an 8K x 14 program memory space. Only
the first 4K x 14 (0000-0FFFh) are physically imple-
mented. Accessing a location above the physically
implemented address will cause a wraparound. The
reset vector is at 0000h and the interrupt vector is at
0004h (Figure 4-1).
TABLE 4-1:
CALIBRATION DATA
OVERVIEW*
Address
Parameter Symbol Units
Format
Slope
32-bit
KREF
0FC0h-0FC3h reference
ratio
N/A
floating
point**
The 4096 words of Program Memory space are divided
into:
Bandgap
0FC4h-0FC7h reference
voltage
32-bit
Volts floating
point
KBG
• Address Vectors (addr 0000h-0004h)
• Program Memory Page 0 (addr 0005h-07FFH)
• Program Memory Page 1 (addr 0800h-0FBFh)
• Calibration Space (64 words, addr 0FC0h-0FFFh)
Tempera-
0FC8h-0FCBh ture sensor
voltage
32-bit
Volts floating
point
VTHERM
Program code may reside in Page 0 and Page 1.
Tempera-
0FCCh-0FCFh ture sensor
coefficient
Volts/ 32-bit
degree floating
Celsius point
KTC
FIGURE 4-1: PIC14000 PROGRAM
MEMORY MAP AND STACK
Internal
oscillator
frequency
multiplier
FOSC
0FD0h
N/A
ms
byte
byte
PC<12:0>
13
CALL, RETURN,
RETFIE, RETLW
WDT
0FD2h
TWDT
time-out
Stack Level 1
* Refer to AN621 for details.
•
** Microchip modified IEEE754 32-bit floating point format.
Refer to application note AN575 for details.
•
Stack Level 8
0000h
Reset Vector
•
•
•
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FBFh
0FC0h
Calibration Space
(64 words)
0FFFh
1000h
20FFh
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 13
PIC14000
4.2.1
GENERAL PURPOSE REGISTER FILE
TABLE 4-2:
CALIBRATION CONSTANT
ADDRESSES
The register file is accessed either directly, or indirectly
through the file select register FSR (Section 4.4).
Address
0FC0h
0FC1h
0FC2h
0FC3h
0FC4h
0FC5h
0FC6h
0FC7h
0FC8h
0FC9h
0FCAh
0FCBh
0FCCh
0FCDh
0FCEh
0FCFh
0FD0h
0FD1h
0FD2h
Data
FIGURE 4-2: REGISTER FILE MAP
K
REF , exponent
KREF , mantissa high byte
REF , mantissa middle byte
File Address
00h Indirect add.(*)
Indirect addr.(*)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
TMR0
PCL
K
KREF , mantissa low byte
KBG , exponent
STATUS
FSR
STATUS
FSR
PORTA
RESERVED
PORTC
PORTD
TRISA
KBG , mantissa high byte
RESERVED
TRISC
KBG , mantissa middle byte
KBG , mantissa low byte
VTHERM , exponent
TRISD
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
V
THERM , mantissa high byte
VTHERM , mantissa middle byte
THERM , mantissa low byte
V
ADTMRL
ADTMRH
PCON
KTC , exponent
SLPCON
KTC , mantissa high byte
KTC , mantissa middle byte
KTC , mantissa low byte
2
2
I CBUF
I CADD
F
OSC, unsigned byte
2
2
14h
94h
I CCON
I CSTAT
reserved
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
ADCAPL
ADCAPH
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
TWDT, unsigned byte
0FD3h -
0FF8h
reserved
0FF9h-Fh
calibration space checksums
PREFA
PREFB
CMCON
MISC
4.2
Data Memory Organization
The data memory (Figure 4-2) is partitioned into two
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when
the RP0 bit in the STATUS register is cleared. Bank 1
is selected when the RP0 bit in the STATUS register is
set. Each bank extends up to 7Fh (128 bytes). The first
32 locations of each bank are reserved for the Special
Function Registers. Several Special Function
Registers are mapped in both Bank 0 and Bank 1. The
general purpose registers, implemented as static RAM,
are located from address 20h through 7Fh, and A0
through FF.
ADCON0
ADCON1
General
Purpose
Register
(96 Bytes)
General
Purpose
Register
(96 Bytes)
7F
FF
* Not a physical register.
Shaded areas are unimplemented memory locations,
read as ‘0’s.
DS40122B-page 14
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers are classified into two sets.
Special registers associated with the “core” functions
are described in this section. Those registers related to
the operation of the peripheral features are described
in the section specific to that peripheral.
The special function registers are registers used by the
CPU and peripheral functions for controlling the
desired operation of the device (Table 4-3). These reg-
isters are static RAM.
TABLE 4-3:
SPECIAL FUNCTION REGISTERS FOR THE PIC14000
Address
Bank0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INDF
(Indirect
Address)
Addressing this location uses contents of the FSR to address data memory (not a physical
register).
00h*
01h
02h*
03h*
04h*
05h
06h
07h
08h
09h
0Ah*
0Bh*
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
TMR0
Timer0 data
PCL
Program Counter’s (PC’s) least significant byte
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
PORTA data latch.
PORTA
Reserved
PORTC
PORTD
Reserved
PCLATH
INTCON
PIR1
Reserved for emulation.
PORTC data latch
PORTD data latch
Buffered register for the upper 5 bits of the Program Counter (PC)
GIE
PEIE
—
T0IE
—
r
r
T0IF
r
r
2
CMIF
PBIF
I CIF
RCIF
ADCIF
OVFIF
Reserved
ADTMRL
ADTMRH
Reserved
Reserved
Reserved
A/D capture timer data least significant byte
A/D capture timer data most significant byte
2
2
I CBUF
I C Serial Port Receive Buffer/Transmit Register
2
2
2
2
2
2
2
I CCON
WCOL
I COV
I CEN
CKP
I CM3
I CM2
I CM1
I CM0
ADCAPL
ADCAPH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ADCON0
A/D capture latch least significant byte
A/D capture latch most significant byte
1Fh
ADCS3
ADCS2
ADCS1
ADCS0
—
AMUXOE
ADRST ADZERO
Legend
— = unimplemented bits, read as ‘0’ but cannot be overwritten
= reserved bits, default is POR value and should not be overwritten with any value
r
Reserved indicates reserved register and should not be overwritten with any value
* indicates registers that can be addressed from either bank
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 15
PIC14000
TABLE 4-3:
SPECIAL FUNCTION REGISTERS FOR THE PIC14000 (CONTINUED)
Address
Bank1
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INDF
(Indirect Ad-
dress)
Addressing this location uses contents of FSR to address data memory (not a physical regis-
ter).
80h*
81h
82h*
83h*
84h*
85h
86h
87h
88h
89h
8Ah*
8Bh*
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
OPTION
PCL
RCPU
Program Counter’s (PC’s) least significant byte
IRP RP1 RP0 TO
r
TOCS
TOSE
PSA
PD
PS2
Z
PS1
DC
PS0
C
STATUS
FSR
Indirect data memory address pointer
PORTA Data Direction Register
Reserved for emulation
TRISA
Reserved
TRISC
PORTC Data Direction Register
PORTD Data Direction Register
TRISD
Reserved
PCLATH
INTCON
PIE1
Buffered register for the upper 5 bits of the Program Counter (PC)
GIE
PEIE
—
T0IE
—
r
r
T0IF
r
r
2
CMIE
PBIE
I CIE
RCIE
ADCIE
OVFIE
Reserved
PCON
r
—
—
—
—
—
—
POR
LVD
SLPCON
Reserved
Reserved
Reserved
HIBEN
REFOFF LSOFF OSCOFF CMOFF TEMPOFF ADOFF
2
2
I CADD
I C Synchronous Serial Port Address Register
2
I CSTAT
—
—
D/A
P
S
R/W
UA
BF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PREFA
PRA7
PRB7
—
PRA6
PRB6
PRA5
PRB5
PRA4
PRB4
PRA3
PRB3
—
PRA2
PRB2
PRA1
PRB1
PRA0
PRB0
PREFB
CMCON
MISC
CMBOUT CMBOE
CPOLB
2
CMAOUT CMAOE
CPOLA
OSC1
SMHOG SPGNDB SPGNDA I CSEL
SMBUS INCLKEN
PCFG2
OSC2
9Fh
ADCON1
ADDAC3 ADDAC2 ADDAC1 ADDAC0 PCFG3
PCFG1
PCFG0
Legend
— = unimplemented bits, read as ‘0’ but cannot be overwritten
= reserved bits, default is POR value and should not be overwritten with any value
r
Reserved indicates reserved register and should not be overwritten with any value
* indicates registers that can be addressed from either bank
DS40122B-page 16
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”
The STATUS register, shown in Figure 4-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The IRP and RP1 bits (STATUS<7:6>) are
not used by the PIC14000 and should be
programmed as cleared. Use of these bits
as general purpose R/W bits is NOT
recommended, since this may affect
upward compatibility with future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
FIGURE 4-3: STATUS REGISTER
83h
Bit 7
IRP
R/W
0
Bit 6
RP1
R/W
0
Bit 5
RP0
R/W
0
Bit 4
TO
R
Bit 3
PD
R
Bit 2
Z
Bit 1
DC
R/W
X
Bit 0
C
STATUS
Read/Write
POR value FFh
R/W
X
R/W
X
1
1
Bit
Name
Function
Not used. This bit should be programmed as ‘0’.
B7
IRP
Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
Not used. This bit should be programmed as ‘0’.
B6
B5
RP1
RP0
Use of this bit as a general purpose read/write bit is not recommended, since this may
affect upward compatibility with future products.
Register page select for direct addressing.
1 = Bank1 (80h - FFh)
0 = Bank0 (00h - 7Fh)
Each page is 128 bytes. Only the RP0 bit is used.
Time-out bit.
B4
B3
B2
TO
PD
Z
1 = After power-up and by the CLRWDTand SLEEPinstruction.
0 = A watchdog timer time-out has occurred.
Power down bit.
1 = After power-up or by a CLRWDTinstruction.
0 = By execution of the SLEEPinstruction.
Zero bit.
1 = The result of an arithmetic or logic operation is zero.
0 = The result of an arithmetic or logical operation is not zero.
Digit carry / borrow bit.
For ADDWFand ADDLWinstructions.
B1
B0
DC
1 = A carry-out from the 4th low order bit of the result.
0 = No carry-out from the 4th low order bit of the result.
Note: For Borrow, the polarity is reversed.
Carry / borrow bit.
For ADDWFand ADDLWinstructions.
1 = A carry-out from the most significant bit of the result occurred. Note that a
subtraction is executed by adding the two’s complement of the second operand. For
rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
C
0 = No carry-out from the most significant bit of the result.
Note: For Borrow the polarity is reversed.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 17
PIC14000
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment,
assign the prescaler to the WDT (PSA=1)
The OPTION register (Address 81h) is a readable and
writable register which contains various control bits to
configure the TMR0/WDT prescaler, TMR0, and the
weak pull-ups on PORTC<5:0>. Bit 6 is reserved.
FIGURE 4-4: OPTION REGISTER
R/W
R/W
r
R/W R/W R/W R/W R/W R/W
T0CS T0SE PSA PS2 PS1 PS0
W:
R:
U:
Writable
Readable
Unimplemented.
Read as '0'
Register:
Address:
POR value:
OPTION
81h
RCPU
FFh
bit7
bit0
PRESCALER VALUE
TMR0 RATE WDT RATE
PS2:PS0
PS2
0
PS1 PS0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 : 2
1 : 1
0
0
0
1
1
1
1
1 : 4
1 : 2
1 : 8
1 : 4
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to TMR0
T0SE: TMR0 source edge
1 = Increment on high-to-low transition on RC3/T0CKI pin
0 = Increment on low-to-high transition on RC3/T0CKI pin
T0CS: TMR0 clock source
1 = Transition on RC3/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
Reserved. This bit should be programmed as a ‘1’. Use of this bit as
general purpose read/write is not recommended since this may affect
upward compatibility with future products.
RCPU: PORTC pull-up enable
1 = PORTC pull-ups are disabled overriding any port latch value (RC<5:0> only)
0 = PORTC pull-ups are enabled by individual port-latch values (RC<5:0>)
DS40122B-page 18
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.2.2.3
INTCON REGISTER
Note: The T0IF will be set by the specified
condition even if the corresponding Inter-
rupt Enable Bit is cleared (interrupt
disabled) or the GIE bit is cleared (all
interrupts disabled). Before enabling
interrupt, clear the interrupt flag, to ensure
that the program does not immediately
branch to the peripheral interrupt service
routine
The INTCON Register is a readable and writable
register which contains the various enable and flag bits
for the Timer0 overflow and peripheral interrupts.
Figure 4-5 shows the bits for the INTCON register.
FIGURE 4-5: INTCON REGISTER
R/W R/W
R/W
R/W R/W R/W R/W R/W
W: Writable
Register:
Address:
INTCON
0Bh or 8Bh
R:
Readable
Unimplemented,
r
GIE PEIE T0IE
r
T0IF
r
r
POR value: 0000 000xb U:
read as '0'
bit0
bit7
Reserved. This bit should be programmed as ‘0’. Use of this bit
as a general purpose read/write bit is not recommended, since
this may affect upward compatibility with future products.
Reserved. This bit should be programmed as ‘0’. Use of this bit
as a general purpose read/write bit is not recommended, since
this may affect upward compatibility with future products.
T0IF: TMR0 overflow interrupt flag
1 = The TMR0 has overflowed
Must be cleared by software
0 = TMR0 did not overflow
Reserved. This bit should be programmed as ‘0’. Use of this bit
as a general purpose read/write bit is not recommended, since
this may affect upward compatibility with future products.
Reserved. This bit should be programmed as ‘0’. Use of this bit
as a general purpose read/write bit is not recommended, since
this may affect upward compatibility with future products.
T0IE: TMR0 interrupt enable bit
1 = Enables T0IF interrupt
0 = Disables T0IF interrupt
PEIE: Peripheral interrupt enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
GIE: Global interrupt enable
1 = Enables all un-masked interrupts
0 = Disables all interrupts
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 19
PIC14000
4.2.2.4
PIE1 REGISTER
Note: INTCON<6> must be enabled to enable
any interrupt in PIE1.
This register contains the individual enable bits for the
Peripheral interrupts including A/D capture event, I C
2
serial port, PORTC change and A/D capture timer
overflow, and external push button.
FIGURE 4-6: PIE1 REGISTER
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Register:
Address:
PIE1
W: Writable
PBIE I2CIE
RCIE
ADCIE
OVFIE
—
CMIE
—
8Ch R:
Readable
00h
U:
bit0
POR value:
Unimplemented,
read as '0'
bit7
OVFIE: A/D Counter Overflow Interrupt Enable
1 = Enables A/D counter overflow interrupt
0 = Disables A/D counter overflow interrupt
ADCIE: A/D Capture Interrupt Enable
1 = A/D capture interrupt is enabled
0 = A/D capture interrupt is disabled
RCIE:
PORTC Interrupt on change Enable
1 = Enables RCIF interrupt on pins, RC<7:4>
0 = Disables RCIF interrupt
I2CIE: I2C Port Interrupt Enable
1 = Enables I2CIF interrupt
0 = Disables I2CIF interrupt
PBIE: External Pushbutton Interrupt Enable
1 = Enable PBTN (pushbutton) interrupt on OSC1/PBTN.
(Note this interrupt not available in HS mode).
0 = Disable PBTN interrupt on OSC1/PBTN
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
CMIE: Programmable Reference Comparator Interrupt Enable
1 = Enable programmable reference comparator trip
0 = Disable programmable reference comparator trip
DS40122B-page 20
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.2.2.5
PIR1 REGISTER
Note: These bits will be set by the specified
condition, even if the corresponding
Interrupt Enable bit is cleared (interrupt
disabled) or the GIE bit is cleared (all
interrupts disabled). Before enabling an
interrupt, the user may wish to clear the
corresponding interrupt flag, to ensure that
the program does not immediately branch
to the Peripheral Interrupt service routine.
This register contains the individual flag bits for the
Peripheral interrupts (Figure 4-7).
FIGURE 4-7: PIR1 REGISTER
R/W
R
R
R/W
R/W
R/W
R/W
R/W
W: Writable
Register: PIR1
Address: 0Ch
POR value: 00h
2
CMIF
—
PBIF
OVFIF
—
I CIF
RCIF
ADCIF
R: Readable
U: Unimplemented,
read as ‘0’
bit7
bit0
OVFIF: A/D counter Overflow Interrupt Flag
1 =An A/D counter overflow has occurred.
Must be cleared in software.
0 = An A/D counter overflow has not occurred
ADCIF: A/D Capture Interrupt Flag
1 =An A/D capture has occurred.
Must be cleared in software.
0 = An A/D capture has not occurred
RCIF: PORTC Interrupt on Change Flag
1 =At least one RC<7:4> input changed.
Must be cleared in software.
0 =None of the RC<7:4> inputs have changed
2
I CIF: I2C Port Interrupt Flag
1 =A transmission/reception is completed.
Must be cleared in software.
0 =Waiting to transmit/receive
PBIF: External Pushbutton Interrupt Flag
1 =The external pushbutton interrupt has occurred
on OSC1/PBTN. Note: This interrupt is not available
in HS mode.
0 =The external pushbutton interrupt did not occur
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
CMIF: Programmable Reference Comparator Interrupt Flag
1 =The comparator output has tripped. This is a
level-sensitive interrupt.
0 = The interrupt did not occur
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 21
PIC14000
4.2.2.6
PCON REGISTER
These bits are cleared on POR. The user must set
these bits following POR. On a subsequent reset if
POR is cleared, this is an indication that the reset was
due to a power-on reset condition.
The Power Control (PCON) register status contains
2 flag bits to allow differentiation between a Power-on
Reset, an external MCLR reset, WDT reset, or low-volt-
age condition (Figure 4-8).
Note: LVD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if LVD is
cleared, indicating a low voltage condition
has occurred.
FIGURE 4-8: PCON REGISTER
R/W
r
U
U
U
U
U
R/W
POR
R/W
W: Writable
Register: PCON
—
—
—
—
—
LVD
bit0
R: Readable
U: Unimplemented,
read as ‘0’
Address:
8Eh
POR value:
bit7
0000_000xb
LVD: Low Voltage Detect Flag
1 = A low-voltage detect condition has not occurred.
0 = A low-voltage detect condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
POR: Power on Reset Flag
1 = A power on reset condition has not occurred.
Reset must be due to some other source
(WDT, MCLR).
0 = A power on reset condition has occurred.
Software must set this bit after a
power-on-reset condition has occurred.
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Unimplemented. Read as ‘0’
Reserved. Bit 7 is reserved. This bit should be
programmed as ‘0’ .
DS40122B-page 22
Preliminary
1996 Microchip Technology Inc.
PIC14000
4.3
PCL and PCLATH
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
The program counter (PC) is 13-bits wide. The low
byte, PCL, is a readable and writable register. The high
byte of the PC (PCH) is not directly readable or
writable. PCLATH is a holding register for PC<12:8>
where contents are transferred to the upper byte of the
program counter. When PC is loaded with a new value
during a CALL, GOTOor a write to PCL, the high bits of
PC are loaded from PCLATH as shown in Figure 4-9.
Note 2: There are no instruction mnemonics
called PUSH nor POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW,or RETFIEinstructions,
or the vectoring to an interrupt address
4.3.3
PROGRAM MEMORY PAGING
FIGURE 4-9: LOADING OF PC IN
DIFFERENT SITUATIONS
The PIC14000 has 4K of program memory, but the
CALLand GOTOinstructions only have a 11-bit address
range. This 11-bit address range allows a branch within
a 2K program memory page size. To allow CALLand
GOTO instructions to address the entire 4K program
memory address range, there must be another bit to
specify the program memory page. This paging bit
comes from the PCLATH<3> bit (Figure 4-9). When
doing a CALLor GOTOinstruction, the user must ensure
that this page bit (PCLATH<3>) is programmed to the
desired program memory page. If a CALLinstruction (or
interrupt) is executed, the entire 13-bit PC is pushed
onto the stack. Therefore, manipulation of the
PCLATH<3> is not required for the return instructions
(which pops the PC from the stack).
PCH
PCL
12
8
7
0
INST with PCL
as dest
PC
8
PCLATH<4:0>
PCLATH
ALU result
5
PCH
12 11 10
PCL
8
7
0
GOTO, CALL
PC
11
PCLATH<4:3>
PCLATH
Opcode <10:0>
2
Note: The PIC14000 ignores the PCLATH<4>
bit, which is used for program memory
pages 2 and 3 (1000h-1FFFh). The use of
PCLATH<4> as
a
general purpose
read/write bit is not recommended since
this may affect upward compatibility with
future products.
Note: On POR, the contents of the PCLATH
register are unknown. The PCLATH should
be initialized before a CALL, GOTO, or any
instruction that modifies the PCL register is
executed.
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
service routine (if interrupts are used).
4.3.1
COMPUTED GOTO
When doing a table read using a computed GOTO
method, care should be exercised if the table location
crosses a PCL memory boundary (each 256 byte
block). Refer to the application note “Table Read Using
the PIC16CXX”(AN556).
EXAMPLE 4-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0X500
BSF
PCLATH, 3 ; Select page 1 (800h-FFFh)
CALL
SUB1_P1
; Call subroutine in
; page 1 (800h-FFFh)
:
:
:
4.3.2
STACK
The PIC14000 has an 8 deep x 13-bit wide hardware
stack (Figure 4-1). The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed in the stack
when a CALLinstruction is executed or an interrupt is
acknowledged. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a “PUSH” or a “POP”
operation.
ORG 0X900
SUB1 P1 :
; called subroutine
; page 1 (800h-FFFh)
:
:
RETURN
; return to page 0
; (000h-7FFh)
The stack operates as a circular buffer. This means
that after the stack has been “PUSHed” eight times, the
ninth push overwrites the value that was stored from
the first push. The tenth push overwrites the second
push (and so on).
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 23
PIC14000
4.4
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw 0x20
;initialize pointer
;to RAM
movf
clrf
incf
FSR
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
INDF
FSR
;clear INDF register
;inc pointer
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the file select
register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no-operation (although status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-10. However, IRP
is not used in the PIC14000.
btfss FSR,4
;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.
FIGURE 4-10: INDIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
6
RP1
0
RP0
from opcode
IRP
7
FSR
00
location select
bank select
bank select
00
location select
00
01
10
11
00
Data
Memory
not used
7F
7F
Bank 0
Bank 1 Bank 2
Bank 3
Note: For memory map detail see Figure 4-1.
DS40122B-page 24
Preliminary
1996 Microchip Technology Inc.
PIC14000
5.0
I/O PORTS
Note: On Reset, PORTA is configured as analog
inputs
The PIC14000 has three ports, PORTA, PORTC and
PORTD, described in the following paragraphs.
Generally, PORTA is used as the analog input port.
PORTC is used for general purpose I/O and for host
communication. PORTD provides additional I/O lines.
Four lines of PORTD may function as analog inputs.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured
as inputs when using them as analog inputs. A ‘1’ in
each location configures the corresponding port pin as
an input. This register resets to all ‘1’s, meaning all
PORTA pins are initially inputs. The data register
should be initialized prior to configuring the port as out-
puts. See Figure 5-2 and Figure 5-3.
5.1
PORTA and TRISA
PORTA is a 4-bit wide port with data register located at
location 05h and corresponding data direction register
(TRISA) at 85h. PORTA can operate as either
analog inputs for the internal A/D converter or as
general purpose digital I/O ports. These inputs are
Schmitt Triggers when used as digital inputs, and have
CMOS drivers as outputs.
PORTA inputs go through a Schmitt Trigger AND gate
that is disabled when the input is in analog mode. Refer
to Figure 5-1.
Note that bits RA<7:4> are unimplemented and always
read as ‘0’. Unused inputs should not be left floating to
avoid leakage currents. All pins have input protection
diodes to VDD and VSS.
PORTA pins are multiplexed with analog inputs.
ADCON1<1:0> bits control whether these pins are
analog or digital as shown in Section 8.7. When config-
ured to the digital mode, reading the PORTA register
reads the status of the pins whereas writing to it will
write to the port latch. When selected as an analog
input, these pins will read as ‘0’s.
EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA
;Initialize PORTA by setting
;output data latches
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x0F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<3:0> as inputs
FIGURE 5-1: PORTA BLOCK DIAGRAM
VDD
Data
D
Q
Q
Bus
P
N
I/O
Pin
Write
PORTA
CK
D
Q
Write
TRISA
VSS
CK
Q
Analog Input Mode
Read
TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
Read
PORTA
To A/D Converter
Note: I/O pins have protection diodes to VDD and VSS.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 25
PIC14000
FIGURE 5-2: PORTA DATA REGISTER
05h
Bit 7
—
Bit 6
—
Bit 5
—
Bit 4
—
Bit 3
RA3/AN3
R/W
Bit 2
RA2/AN2
R/W
Bit 1
RA1/AN1
R/W
Bit 0
RA0/AN0
R/W
PORTA
Read/Write
POR value 0xh
U
U
U
U
0
0
0
0
X
X
X
X
Bit
Name
Function
B7-B4
B3
Unimplemented. Reads as‘0’.
—
RA3/AN3
RA2/AN2
RA1/AN1
GPIO or analog input. Returns value on pin RA3/AN3 when used as a digital
input. When configured as an analog input, reads as ‘0’.
B2
B1
GPIO or analog input. Returns value on pin RA2/AN2 when used as a digital
input. When configured as an analog input, reads as ‘0’.
GPIO or analog input. Returns value on RA1/AN1 when used as a digital input.
This pin can connect to a level shift network. If enabled, a +0.5V offset is added
to the input voltage. When configured as an analog input, reads as ‘0’.
B0
RA0/AN0
GPIO or analog input. Returns value on pin RA0/AN0 when used as a digital
input. When configured as an analog input, reads as ‘0’.
When using PORTC<0> as an analog output
(CMCON<1> bit is set), the TRISC<0> bit should be
cleared to disable the weak pull-up on this pin. Refer to
Table 5-1.
5.2
PORTC and TRISC
PORTC is a 8-bit wide bidirectional port, with Schmitt
Trigger inputs, that serves the following functions
depending on programming:
Four of the PORTC pins, RC<7:4> have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur. In other words, any pin
RC<7:4> configured as an output is excluded from the
interrupt on change comparison. The input pins of
RC<7:4> are compared with the old value latched on
the last read of PORTC. The “mismatch” outputs of
RC<7:4> are OR’ed together to assert the RCIF flag
(PIR1 register<2>) and cause a CPU interrupt, if
enabled.
• Direct LED drive (PORTC<7:0>).
2
• I C communication lines (PORTC<7:6>), refer to
2
Section 7.0 I C Serial Port.
• Interrupt on change function (PORTC<7:4>),
discussed below and in Section 10.3 Interrupts.
• Programmable reference and comparator
outputs.
• Timer0 clock source on RC3
The PORTC data register is located at location 07h and
its data direction register (TRISC) is at 87h.
2
Note: If the I C function is enabled,
2
(I CCON<5>, address 14h), RC<7:6> are
PORTC<5:0> have weak internal pull-ups (~100 uA
typical). A single control bit can turn on all the pull-ups.
This is done by clearing bit RCPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on power-on reset and in hibernate mode.
automatically
interrupt-on-change comparison.
excluded
from
the
DS40122B-page 26
Preliminary
1996 Microchip Technology Inc.
PIC14000
This interrupt can wake the device up from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in one of two ways:
The TRISC register controls the direction of the
PORTC pin. A ‘1’ in each location configures the
corresponding port pin as an input. Upon reset, this
register sets to FFh, meaning all PORTC pins are ini-
tially inputs. The data register should be initialized prior
to configuring the port as outputs.
• Disable the interrupt by clearing the RCIE
(PIE1<2>) bit
• Read PORTC. This will end mismatch condition.
Then, clear the RCIF (PIR1<2>) bit.
Unused inputs should not be left floating to avoid
leakage currents. All pins have input protection diodes
to VDD and VSS.
A mismatch condition will continue to set the RCIF bit.
Reading PORTC will end the mismatch condition, and
allow the RCIF bit to be cleared.
EXAMPLE 5-2: INITIALIZING PORTC
If bit CMAOE (CMCON<1>) is set, the RC0/REFA pin
becomes the programmable reference A and analog
output. Pin RC1/CMPA becomes the comparator A out-
put.
CLRF PORTC
;Initialize PORTC data
;
;
;
latches before setting
the data direction
register
BSF
MOVLW 0xCF
STATUS, RPO ;Select Bank1
Note: Setting CMAOE changes the definition of
RC0/REFA and RC1/CMPA, bypassing
the PORTC data and TRISC register set-
tings.
;Value used to initialize
;data direction
;Set RC<3:0> as inputs
MOVWF TRISC
;
RC<5:4> as outputs
RC<7:6> as inputs
PORTC<7:6> also serves multiple functions. These
;
2
2
pins act as the I C data and clock lines when the I C
module is enabled. They also serve as the serial pro-
gramming interface data and clock line for in-circuit
programming of the EPROM.
FIGURE 5-3: BLOCK DIAGRAM OF PORTC<7:6> PINS
2
I CCON<5>
VDD
N
Data
Bus
D
Q
Q
I/O
Pin
Write
PORTC
CK
N
D
Q
Q
VSS
Write
CK
TRISC
Schmitt Trigger
Input Buffer
Read
TRISC
Q
Q
D
Read
PORTC
EN
Set
RCIF
D
From other
PORTC pins
Read PORTC
EN
Note: I/O pins have protection diodes to VDD and VSS. These pins do not have a P-channel pull-up.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 27
PIC14000
TABLE 5-1:
PORT RC0 PIN CONFIGURATION SUMMARY
RC0 Pin
RCPU
CMAOE
TRISC<0>
Comment
Configuration
Digital Input (weak pull-up)
Digital Input (no pull-up)
Digital Output
OPTION<7> CMCON<1>
1
1
0
0
0
1
0
0
0
1
X
X
Analog Output
Must clear TRISC<0> to disable pull-up when
used as an analog output.
FIGURE 5-4: BLOCK DIAGRAM OF PORTC<5:4> PINS
RCPU
VDD
HIBERNATE
Data
Bus
D
Q
Q
P
I/O
Write
PORTC
Pin
CK
D
Q
Q
Schmitt Trigger
Input Buffer
Write
TRISC
CK
Read
TRISC
Q
Q
D
Read
PORTC
EN
Set
RCIF
D
From other
PORTC pins
Read PORTC
EN
1. I/O pins have protection diodes to VDD and VSS.
2. Port Latch = ‘1’ and TRISC = ‘1’ enables weak pull-up if RCPU = ‘0’ in OPTION register.
DS40122B-page 28
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 5-5: BLOCK DIAGRAM OF PORTC<3:0> PINS
RCPU
VDD
P
Data
D
Q
Q
Bus
I/O
Pin
Write
PORTC
CK
D
Q
Q
Write
TRISC
HIBERNATE
CK
Schmitt Trigger
Input Buffer
Read
TRISC
Q
D
Read
PORTC
EN
Read PORTC
1. I/O pins have protection diodes to VDD and VSS.
2. Port Latch =‘1’ and TRISC =‘1’ enables weak pull-up if RCPU =‘0’ in OPTION register.
3. If the CMAOE bit (CMCON<1>) is set to‘1’, RC0 becomes REFA, RC1 becomes CMPA,
ignoring the PORTC<1:0> data and TRISC<1:0> register settings.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 29
PIC14000
FIGURE 5-6:
PORTC DATA REGISTER
07h
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RC0/REFA
R/W
PORTC
RC7/SDAA RC6/SCLA
RC5
R/W
x
RC4 RC3/T0CKI RC2 RC1/CMPA
Read/Write
POR value xxh
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
x
Bit
Name
Function
2
Synchronous serial data I/O for I C interface. Also is the serial programming data line.
This pin can also serve as a general purpose I/O. If enabled, a change on this pin can
cause a CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in
B7
RC7/SDAA
2
I C mode.
2
Synchronous serial clock for I C interface. Also is the serial programming clock. This pin
B6
B5
B4
B3
B2
B1
B0
RC6/SCLA
RC5
can also serve as a general purpose I/O. If enabled, a change on this pin can cause a
CPU interrupt. This pin has an N-channel pull-up to VDD which is disabled in I C mode.
2
LED direct-drive output. This pin can also serve as a GPIO. If enabled, a change on this
pin can cause a CPU interrupt. If enabled, this pin has a weak internal pull-up to VDD.
RC4
LED direct-drive output. This pin can also serve as a GPIO. If enabled, a change on this
pin can cause a CPU interrupt. If enabled, this pin has a weak internal pull-up to VDD.
RC3/T0CKI
RC2
LED direct-drive output. This pin can also serve as a GPIO. If enabled, this pin has a
weak internal pull-up to VDD. T0CKI is enabled as TMR0 clock via the OPTION register.
LED direct-drive output. This pin can also serve as a GPIO. If enabled, this pin has a
weak internal pull-up to VDD.
RC1/CMPA
RC0/REFA
LED direct-drive output. This pin can also serve as a GPIO, or comparator A output. If
enabled, this pin has a weak internal pull-up to VDD.
LED direct-drive output. This pin can also serve as a GPIO, or programmable reference
A output. If enabled, this pin has a weak internal pull-up to VDD.
U= unimplemented, X = unknown.
DS40122B-page 30
Preliminary
1996 Microchip Technology Inc.
PIC14000
5.2.1
TRISC PORTC DATA DIRECTION
REGISTER
This register defines each pin of PORTC as either an
input or output under software control. A ‘1’ in each
location configures the corresponding port pin as an
input. This register resets to all ‘1’s, meaning all
PORTC pins are initially inputs. The data register
should be initialized prior to configuring the port as
outputs.
FIGURE 5-7: TRISC REGISTER
87h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TRISC3
R/W
Bit 2
TRISC2
R/W
Bit 1
TRISC1
R/W
Bit 0
TRISC0
R/W
TRISC
TRISC7 TRISC6 TRISC5 TRISC4
Read/Write
POR value FFh
R/W
1
R/W
1
R/W
1
R/W
1
1
1
1
1
Bit
Name
Function
2
B7
TRISC7
Control direction on pin RC7/SDAA (has no effect if I C is enabled):
0 = pin is an output
1 = pin is an input
2
B6
TRISC6
Control direction on pin RC6/SCLA (has no effect if I C is enabled):
0 = pin is an output
1 = pin is an input
B5
B4
B3
B2
B1
B0
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
Control direction on pin RC5:
0 = pin is an output
1 = pin is an input
Control direction on pin RC4:
0 = pin is an output
1 = pin is an input
Control direction on pin RC3:
0 = pin is an output
1 = pin is an input
Control direction on pin RC2:
0 = pin is an output
1 = pin is an input
Control direction on pin RC1/CMPA (has no effect if the CMAOE bit is set):
0 = pin is an output
1 = pin is an input
Control direction on pin RC0/REFA (has no effect if the CMAOE bit is set):
0 = pin is an output
1 = pin is an input
U= unimplemented, X = unknown.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 31
PIC14000
5.3
PORTD and TRISD
PORTD is an 8-bit port that may be used for general
purpose I/O. Four pins can be configured as analog
inputs.
FIGURE 5-8: BLOCK DIAGRAM OF PORTD<7:4> PINS
VDD
P
Data
Bus
D
Q
Q
Write
PORTD
I/O
Pin
CK
N
D
Q
Q
Write
TRISD
VSS
CK
Analog Input Mode
Read
TRISD
Schmitt Trigger
Input Buffer
D
Q
EN
Read
PortD
To A/D Converter
Note: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-9: BLOCK DIAGRAM OF PORTD<3:2> PINS
Data
Bus
D
Q
Q
I/O
Pin
Write
PORTD
CK
D
Q
Q
Write
TRISD
Schmitt Trigger
Input Buffer
CK
Read
TRISD
Q
D
Read
PORTD
EN
Read PORTD
1. I/O pins have protection diodes to VDD and VSS.
2. If CMBOE (CMCON<5>) is set to ‘1’, RD2 becomes CMPB,
RD3 becomes REFB, ignoring the PORTD<3:2> data and
TRISD<3:2> register settings.
DS40122B-page 32
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 5-10: BLOCK DIAGRAM OF PORTD<1:0> PINS
I2CCON<5>
Data
VDD
N
Bus
D
Q
I/O
Pin
Write
PORTD
CK
Q
N
D
Q
Q
Write
TRISD
VSS
CK
Read
TRISD
Schmitt Trigger
Input Buffer
D
Q
EN
Read
PortD
Note: I/O pins have protection diodes to VDD and VSS. These pins do not have a P-channel pull-up.
FIGURE 5-11: PORTD DATA REGISTER
08h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
RD7/AN7 RD6/AN6 RD5/AN5 RD4/AN4 RD3/REFB RD2/CMPB RD1/SDAB RD0/SCLB
Read/Write
POR value xxh
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Bit
Name
Function
GPIO or analog input. Returns value on pin RD7/AN7 when used as a digital
input. When configured as an analog input, reads as ‘0’.
B7
B6
RD7/AN7
RD6/AN6
GPIO or analog input. Returns value on pin RD6/AN6 when used as a digital
input. When configured as an analog input, reads as ‘0’.
GPIO or analog input. This pin can connect to a level shift network. If
enabled, a +0.5V offset is added to the input voltage. When configured as
an analog input, reads as ‘0’.
B5
B4
RD5/AN5
RD4/AN4
GPIO or analog input. Returns value on pin RD4/AN4 when used as a digital
input. When configured as an analog input, reads as ‘0’.
B3
B2
RD3/REFB
RD2/CMPB
This pin can serve as a GPIO, or programmable reference B output.
This pin can serve as a GPIO, or comparator B output.
2
Alternate synchronous serial data I/O for I C interface enabled by setting
2
the I CSEL bit in the MISC register. This pin can also serve as a general
B1
B0
RD1/SDAB
RD0/SCLB
purpose I/O. This pin has an N-channel pull-up to VDD which is disabled in
2
I C mode.
2
Alternate synchronous serial clock for I C interface, enabled by setting the
2
I CSEL bit in the MISC register. This pin can also serve as a general pur-
2
pose I/O. This pin has an N-Channel pull-up to VDD which is disabled in I C
mode.
Legend: U = unimplemented, read as ‘0’, x = unknown.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 33
PIC14000
FIGURE 5-12: TRISD REGISTER
88h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
TRISD3
R/W
Bit 2
TRISD2
R/W
Bit 1
TRISD1
R/W
Bit 0
TRISD0
R/W
TRISD
TRISD7 TRISD6 TRISD5 TRISD4
Read/Write
POR value FFh
R/W
1
R/W
1
R/W
1
R/W
1
1
1
1
1
Bit
Name
Function
Control direction on pin RD7/AN7:
0 = pin is an output
1 = pin is an input
B7
B6
B5
B4
B3
B2
B1
B0
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Control direction on pin RD6/AN6:
0 = pin is an output
1 = pin is an input
Control direction on pin RD5/AN5:
0 = pin is an output
1 = pin is an input
Control direction on pin RD4/AN4:
0 = pin is an output
1 = pin is an input
Control direction on pin RD3/REFB (has no effect if the CMBOE bit is set):
0 = pin is an output
1 = pin is an input
Control direction on pin RD2/CMPB (has no effect if the CMBOE bit is set):
0 = pin is an output
1 = pin is an input
Control direction on pin RD1/SDAB:
0 = pin is an output
1 = pin is an input
Control direction on pin RD0/SCLB:
0 = pin is an output
1 = pin is an input
DS40122B-page 34
Preliminary
1996 Microchip Technology Inc.
PIC14000
If the CMBOE bit (CMCON<5>) is set, the RD3/REFB
pin becomes the programmable reference B output
and pin RD2/CMPB becomes the comparator B output.
5.4
I/O Programming Considerations
5.4.1
BI-DIRECTIONAL I/O PORTS
Reading the port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. Some instructions operate internally as
read-modify-write. The BCF and BSF instructions, for
example, read the register into the CPU, execute the bit
operation, and write the result back to the register.
Caution must be used when these instructions are
applied to a port with both inputs and outputs defined.
For example, a BSF operation on bit5 of PORTC will
cause all eight bits of PORTC to be read into the CPU.
Then the BSF operation takes place on bit5 and
PORTC is written to the output latches. If another bit of
PORTC is used as a bi-directional I/O pin (say bit0) and
it is defined as an input at this time, the input signal
present on the pin itself would be read into the CPU
and re-written to the data latch of this particular pin,
overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However,
if bit0 is switched into output mode later on, the content
of the data latch may now be unknown.
Note: Setting CMBOE changes the definition of
RD3/REFB and RD2/CMPB, bypassing
the PORTD data and TRISD register set-
tings.
PORTD<1:0> also serve multiple functions. These pins
2
2
act as the I C data and clock lines when the I C module
is enabled.
The TRISD register controls the direction of the Port D
pins.
A
‘1’ in each location configures the
corresponding port pin as an input. Upon reset, this
register sets to FFh, meaning all PORTD pins are ini-
tially inputs. The data register should be initialized prior
to configuring the port as outputs.
Unused inputs should not be left floating to avoid
leakage currents. All pins have input protection diodes
to VDD and VSS.
EXAMPLE 5-3: INITIALIZING PORTD
CLRF PORTD
;Initialize PORTD data
A pin actively outputting a LOW or HIGH should not be
driven from external devices at the same time in order
to change the level on this pin (“wire-or”, “wire-and”).
The resulting high output currents may damage the
chip.
;
;
;
latches before setting
the data direction
register
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0xFF
;Value used to initialize
;data direction
Example 5-4 shows the effect of two sequential read
modify write instructions (ex. BCF, BSF, etc.) on an I/O
Port.
MOVWF TRISD
;Set RD<7:0> as inputs
EXAMPLE 5-4: READ MODIFY WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings:
PORTC<7:4> Inputs
;
;
PORTC<3:0> Outputs
;PORTC<7:6> have external pull-up and are not
;connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BCF PORTC, 7
BCF PORTC, 6
BSF STATUS,RP0
BCF TRISC, 7
BCF TRISC, 6
;01pp pppp 11pp pppp
;10pp pppp 11pp pppp
;
;10pp pppp 11pp pppp
;10pp pppp 10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RC7 to be latched as the pin value (High).
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 35
PIC14000
5.4.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The sequence of instructions should be such to allow
the pin voltage to stabilize before the next instruction
which causes that port to be read into the CPU is
executed. Otherwise, the previous state of that pin may
be read into the CPU rather than the new state. When
in doubt, it is better to separate these instructions with
a NOP or another instruction not accessing this I/O
port.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle.
Therefore, care must be exercised if a write operation
is followed by a read operation on the same I/O port.
FIGURE 5-13: SUCCESSIVE I/O OPERATION
Example showing write to PORTC followed by immediate read. Some delays in settling may cause “old”
Port data to be read, especially at higher clock frequencies. Data setup time = (0.25 Tcyc- Tpd), where
Tcyc = instruction cycle time.
Q1 | Q2 | Q3 | Q4
PC
Q1 | Q2 | Q3 | Q4 Q1 | Q2
|
Q3
|
Q4 Q1 | Q2 | Q3 | Q4
PC + 3
PC + 1
PC + 2
NOP
MOVWF PORTC
Write to PORTC
MOVF PORTC, W
Read PORTC
NOP
Pin values
RC<x>
Port pin sampled
here
Execute NOP
Execute MOVF
PORTC, W
Execute MOVWF
PORTC
DS40122B-page 36
Preliminary
1996 Microchip Technology Inc.
PIC14000
• 8-bit timer
6.0
TIMER MODULES
• Readable and writable (file address 01h)
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
The PIC14000 contains two general purpose timer
modules, Timer0 (TMR0) and the Watchdog Timer
(WDT). The ADTMR is described in the A/D section.
Figure 6-1 is a simplified block diagram of the Timer0
module.
The Timer0 module is identical to the Timer0 module of
the PIC16C7X enhanced core products. It is an 8-bit
overflow counter.
The Timer0 module will increment every instruction
cycle (without prescaler). If TMR0 is written, increment
is inhibited for the following two cycles (Figure 6-2 and
Figure 6-3). The user can compensate by writing an
adjusted value to TMR0.
The Timer0 module has a programmable prescaler
option. This prescaler can be assigned to either the
Timer0 module or the Watchdog Timer (WDT). PSA
(OPTION<3>) assigns the prescaler, and PS2:PS0
(OPTION<2:0>) determines the prescaler value.
Timer0 can increment at the following rates: 1:1 (when
prescaler assigned to Watchdog Timer), 1:2, 1:4, 1:8,
1:16, 1:32, 1:64, 1:128, 1:256.
The Timer0 module has the following features:
FIGURE 6-1: TIMER0 AND WATCHDOG TIMER BLOCK DIAGRAM
Timer0
Data bus
8
FOSC/4
0
1
PSout
1
0
Sync with
Internal
clocks
TMR0
RC3/T0CKI
pin
PSout
Set T0IF
Interrupt on
Overflow
(2 cycle delay)
T0SE
PSA
T0CS
Prescaler/
Postscaler
Local
8-bit Counter
Oscillator
0
1
8
18 mS
Timer
3
8-to-1 MUX
PS2:PS0
PSA
Enable
1
0
PSA
WDT
Time-out
Watchdog Timer
WDT
Enable Bit
Note: T0CS, T0SE, PSA, PS2:PS0 correspond to (OPTION<5:0>).
HIBERNATE
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 37
PIC14000
vice routine before re-enabling this interrupt. The
Timer0 module interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
The timing of the Timer0 interrupt is shown in
Figure 6-4.
6.1
Timer0 Interrupt
The TMR0 interrupt is generated when the Timer0
overflows from FFh to 00h. This overflow sets the T0IF
bit. The interrupt can be masked by clearing bit T0IE
(INTCON<5>). Flag bit T0IF (INTCON<2>) must be
cleared in software by the TMR0 module interrupt ser-
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 6-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
1
FFh
1
00h
01h
02h
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in HS oscillator mode.
DS40122B-page 38
Preliminary
1996 Microchip Technology Inc.
PIC14000
6.2.2
TIMER0 INCREMENT DELAY
6.2
Using Timer0 with External Clock
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
When the external clock input (pin RC3/T0CKI) is used
for Timer0, it must meet certain requirements. The
external clock requirement is due to internal phase
clock (TOSC) synchronization. Also, there is a delay in
the actual incrementing of TMR0 after synchronization.
6.2.1
EXTERNAL CLOCK SYNCHRONIZATION
6.3
Prescaler
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2Tosc (and a small RC delay of 20 ns)
and low for at least 2Tosc (and a small RC delay of
20 ns).
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a post-scaler for the Watchdog
Timer (Figure 6-1). For simplicity, this counter is being
referred to as “prescaler” throughout this data sheet.
Note that there is only one prescaler available which is
mutually exclusive between the Timer0 module and the
Watchdog Timer. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4Tosc (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns.
Bit PSA and PS2:PS0 (OPTION<3:0>) determine the
prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the Timer0 module (e.g., CLRF 1, MOVWF 1,
BSF 1,x) will clear the prescaler. When assigned to
WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
EXT CLOCK INPUT OR
misses sampling
PRESCALER OUT (NOTE 2)
EXT CLOCK/PRESCALER
OUTPUT AFTER SAMPLING
(note 3)
INCREMENT TMR0 (Q4)
T0
T0 + 1
T0 + 2
TMR0
Notes:
1. Delay from clock input change to TMR0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on TMR0 input = ± 4 tosc max.
2. External clock if no prescaler selected, Prescaler output otherwise.
3. The arrows indicate the points in time where sampling occurs.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 39
PIC14000
6.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0
module use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control, i.e., it can be changed “on the fly” during
program execution. To avoid an unintended device
EXAMPLE 6-2: CHANGING PRESCALER
RESET,
the
following
instruction
sequence
(WDT→TIMER0)
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
CLRWDT
;Clear WDT and
;prescaler
BSF
STATUS, RP0
EXAMPLE 6-1: CHANGING PRESCALER
MOVLW
B'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
OPTION
STATUS, RP0
(TIMER0→WDT)
1.BCF
STATUS,RP0 ;Skip if already in
MOVWF
BCF
; Bank 0
2.CLRWDT
;Clear WDT
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
3.CLRF TMR0
4.BSF
5.MOVLW '00101111'b;These 3 lines (5, 6, 7)
6.MOVWF OPTION
7.CLRWDT
; are required only
; if desired PS<2:0>
; are 000 or 001
8.MOVLW '00101xxx'b ;Set Postscaler to
9.MOVWF OPTION ; desired WDT rate
10.BCF STATUS, RP0 ;Return to Bank 0
TABLE 6-1:
SUMMARY OF TIMER0 REGISTERS
Register Name
Function
Address
Power-on Reset Value
TMR0
Timer/counter register
01h
81h
xxxx xxxx
1111 1111
OPTION
Configuration and prescaler assign-
ment bits for TMR0.
INTCON
TMR0 overflow interrupt flag and
mask bits.
0Bh
0000 000x
Legend: x = unknown,
Note 1: For reset values of registers in other reset situations refer to Table 10-4.
TABLE 6-2:
Address
REGISTERS ASSOCIATED WITH TIMER0
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
TIMER0 TIMER/COUNTER
0Bh/8Bh
81h
INTCON
OPTION
TRISC
GIE
PEIE
r
T0IE
T0CS
r
r
T0IF
PS2
r
r
RCPU
T0SE
TRISC4
PSA
PS1
PS0
87h
TRISC7 TRISC6
TRISC5
TRISC3
TRISC2
TRISC1
TRISC0
Legend: r = Reserved locations
Shaded boxes are not used by Timer0 module
DS40122B-page 40
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
In the I C interface protocol each device has an
address. When a master wishes to initiate a data
transfer, it first transmits the address of the device that
it wishes to talk to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read from or write to the slave device.
The master and slave are always in opposite modes
7.0
INTER-INTEGRATED CIRCUIT
SERIAL PORT (I C )
2
2
The I C module is a serial interface useful for
communicating with other peripheral or microcontroller
devices. These peripheral devices may be serial
EEPROMs, shift registers, display drivers, A/D
2
converters, etc. The I C module is compatible with the
(transmitter/receiver) of operation during
a data
following interface specifications:
transfer. They may operate in either of these two
states:
2
• Inter-Integrated Circuit (I C)
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
• System Management Bus (SMBus)
2
Note: The I C module on PIC14000 only
2
supports I C mode. This is different from
In both cases the master generates the clock signal.
the standard module used on the
PIC16C7X family, which supports both
I C and SPI modes. Caution should be
exercised to avoid enabling SPI mode on
the PIC14000.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The
number of devices that may be attached to the I C bus
is limited only by the maximum bus loading specifica-
tion of 400 pF.
2
2
2
This section provides an overview of the Inter-IC(I C)
2
bus. The I C bus is a two-wire serial interface
developed by the Philips Corporation. The original
specification, or standard mode, was for data transfers
of up to 100 Kbps. An enhanced specification, or fast
mode, supports data transmission up to 400 Kbps.
Both standard mode and fast mode devices will
inter-operate if attached to the same bus.
7.1
Initiating and Terminating Data
Transfer
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP determine the start and stop of data
transmission. The START is defined as a high to low
transition of SDA when SCL is high. The STOP is
defined as a low to high transition of SDA when SCL is
high. Figure 7-1 shows the START and STOP. The
master generates these conditions for starting and ter-
minating data transfer. Due to the definition of the
START and STOP, when data is being transmitted the
SDA line can only change state when the SCL line is
low.
2
The I C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
(generates the clock) while the other device(s) acts as
the “slave”. All portions of the slave protocol are
2
implemented in the I C module’s hardware, except
general call support, while portions of the master proto-
col will need to be addressed in the PIC14000 soft-
2
ware. Table 7-1 defines some of the I C bus
2
terminology. For additional information on the I C inter-
face specification, please refer to the Philips Corpora-
2
tion document “The I C-bus and How to Use It”.
2
FIGURE 7-1: I C START AND STOP CONDITIONS
SDA
SCL
S
P
Start
Condition
Stop
Condition
Change
of Data
Allowed
Change
of Data
Allowed
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 41
PIC14000
2
2
FIGURE 7-2: I CSTAT: I C PORT STATUS REGISTER
U
_
U
_
R
R
P
R
S
R
R
R
2
Register:
Address:
POR value:
I CSTAT
94h
W: Writable bit
R: Readable bit
D/A
R/W
UA
BF
00h U: Unimplemented, read as ‘0’
bit0
bit7
BF: Buffer full
Receive
1 = Receive complete, I CBUF is full
2
2
0 = Receive not complete, I CBUF is empty
Transmit
2
1 = Transmit in progress, I CBUF is full
0 = Transmit complete, I CBUF is empty
2
2
UA: Update Address (10-bit I C slave mode only)
1 = Indicate that the user needs to update the address in the I CADD
register.
2
0 = Address does not need to be updated
R/W: Read/write bit information
This bit holds the R/W bit information received following the last address
match. This bit is only valid during the transmission.
The user may use this bit in software to determine whether transmission
or reception is in progress.
1 = Read
0 = Write
S: Start bit
2
2
This bit is cleared when the I C module is disabled (I CEN is cleared)
1 = Indicates that a start bit has been detected last. This bit is 0 on
reset.
0 = Start bit was not detected last
P: Stop bit
2
2
This bit is cleared when the I C module is disabled (I CEN is cleared)
1 = Indicates that a stop bit has been detected last.
0 = Stop bit was not detected last
D/A: Data/Address bit
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was address
Unimplemented: read as ‘0’
DS40122B-page 42
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
2
FIGURE 7-3: I CCON: I C PORT CONTROL REGISTER
R/W
R/W
R/W R/W R/W
R/W
R/W
R/W
2
WCOL I2COV I2CEN CKP I2CM3 I2CM2 I2CM1 I2CM0
Register:
Address:
POR value:
I CCON
14h
00h
W: Writable bit
R: Readable bit
U: Unimplemented, read as ‘0’
bit7
bit0
I2CM<3:0>: I2C mode select
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts
enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts
enabled
Any other combinations of I2CM<3:0>
are illegal and should NEVER be used.
CKP: Clock polarity select
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch)
Note: Used to ensure data setup time
I2CEN: I2C enable
1 = Enables the serial port and configures SDA and SCL pins as serial
port pins. When enabled, these pins must be configured as input
or output.
0 = Disables serial port and configures these pins as I/O port pins
I2COV: Receive overflow flag
1 = A byte is received while the I2CBUF is still holding the previous
byte. I2COV is a don't care in transmit mode.
I2COV must be cleared in software.
0 = No overflow
WCOL: Write collision detect
1 = the I2CBUF register is written while it is still transmitting the previ-
ous word.
Must be cleared in software.
0 = No collision
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 43
PIC14000
2
TABLE 7-1:
I C BUS TERMINOLOGY
Term
Description
Transmitter
Receiver
Master
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock, and terminates the transfer.
The device addressed by a master.
Slave
Multi-master
More than one master device in a system. These masters can attempt to control the bus
at the same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This
ensures that the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
2
2
FIGURE 7-4: I C 7-BIT ADDRESS FORMAT
7.2
Addressing I C Devices
MSb
LSb
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 7-4). The
address is the most significant seven bits of the byte.
R/W ACK
S
2
For example when loading the I CADD register, the
slave address
Sent by
Slave
S
R/W
ACK
Start Condition
Read/Write pulse
Acknowledge
least significant bit is a “don’t care”. The more complex
is the 10-bit address with a R/W bit (Figure 7-5). For
10-bit address format, two bytes must be transmitted
with the first five bits specifying this to be a 10-bit
address.
2
FIGURE 7-5: I C 10-BIT ADDRESS
FORMAT
S 1 111 0 A9 A8 RW ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
= 0 for write
S
- Start Condition
R/W - Read/Write Pulse
ACK - Acknowledge
DS40122B-page 44
Preliminary
1996 Microchip Technology Inc.
PIC14000
accomplished by setting SMHOG (MISC<7>) high.
Clearing MISC<7> will resume the data transfer.
Figure 7-7 shows a data transfer waveform.
7.3
Transfer Acknowledge
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an
acknowledge bit (ACK). This is shown in Figure 7-6.
When a slave-receiver doesn’t acknowledge the slave
address or received data, the master must abort the
transfer. The slave must leave SDA high so that the
master can generate the STOP (Figure 7-1).
Figure 7-8 and Figure 7-9 show master-transmitter and
master-receiver data transfer sequences.
2
FIGURE 7-6: I C SLAVE-RECEIVER
ACKNOWLEDGE
Data
Output by
Transmitter
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge. The slave then releases the
SDA line so the master can generate the STOP. The
master can also generate the STOP during the
acknowledge pulse for valid termination of data
transfer.
not acknowledge
Data
Output by
Receiver
acknowledge
SCL from
Master
1
2
8
9
S
Start
Clock pulse for
acknowledgement
Condition
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state can be
2
FIGURE 7-7: SAMPLE I C DATA TRANSFER
SDA
MSB
acknowledgement
signal from receiver
acknowledgement
signal from receiver
byte complete.
interrupt with receiver
clock line held low while
interrupts are serviced
SCL
S
9
8
9
1
2
2
7
3 • 8
1
P
Stop
Condition
Start
Condition
ACK
Address
R/W
Wait
Data
ACK
State
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 45
PIC14000
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START (Sr)
must be generated. This condition is identical to the
START (SDA goes high-to-low while SCL is high), but
occurs after a data transfer acknowledge pulse (not the
bus-free state). This allows a master to send
“commands” to the slave and then receive the
requested information or to address a different slave
device. This sequence is shown in Figure 7-10.
FIGURE 7-8: MASTER - TRANSMITTER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
S Slave Address R/W A DATA A DATA A/A
P
first 7 bits
second byte
"0" (write)
data transferred
(n bytes - acknowledge)
(write)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
Data A
Data A/A P
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
P = STOP condition
From master to slave
From slave to master
A master transmitter addresses a slave receiver with a
10-bit address.
FIGURE 7-9: MASTER - RECEIVER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
S Slave Address R/W A DATA A DATA
A
P
first 7 bits
second byte
(read)
data transferred
(n bytes - acknowledge)
(write)
A master reads a slave immediately after the first byte.
Sr
Slave Address R/W A3 Data A
first 7 bits
Data A P
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
(read)
From master to slave
From slave to master
A master transmitter addresses a slave receiver with a
10-bit address.
P = STOP condition
FIGURE 7-10: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
Sr
S Slave Address R/W A DATA A/A
Slave Address R/W A DATA A/A P
Direction of transfer
may change at this point
(write)
Sr = repeated
START condition
(read)
Transfer direction of data and acknowledgement bits depends on R/W bits.
Combined Format:
S Slave Address R/W A Slave Address A Data A
first 7 bits second byte
Data A/A Sr Slave Address R/W A Data A
Data A P
first 7 bits
(write)
(read)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = START condition
P = STOP condition
From master to slave
From slave to master
DS40122B-page 46
Preliminary
1996 Microchip Technology Inc.
PIC14000
7.4
Multi-Master Operation
FIGURE 7-11: MULTI-MASTER
ARBITRATION (2 MASTERS)
2
The I C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time,
arbitration and synchronization occur.
transmitter 1 loses arbitration
DATA 1- SDA
DATA 1
DATA 2
SDA
7.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 7-11) and turns off its data output stage. A
master which lost arbitrating can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
SCL
2
FIGURE 7-12: I C CLOCK
SYNCHRONIZATION
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning
master-transmitter may be addressing it.
start counting
HIGH period
wait
state
CLK
1
Arbitration is not allowed between:
• A repeated START
counter
reset
CLK
2
• A STOP and a data bit
• A repeated START and a STOP
Care needs to be taken to ensure that these conditions
do not occur.
SCL
7.4.2
CLOCK SYNCHRONIZATION
Clock synchronization occurs after the devices have
started arbitration. This is performed using
a
wired-AND connection to the SCL line. A high to low
transition on the SCL line causes the concerned
devices to start counting off their low period. Once a
device clock has gone low, it will hold the SCL line low
until its SCL high state is reached. The low to high
transition of this clock may not change the state of the
SCL line, if another device clock is still within its low
period. The SCL line is held low by the device with the
longest low period. Devices with shorter low periods
enter a high wait-state, until the SCL line comes high.
When the SCL line comes high, all devices start
counting off their high periods. The first device to
complete its high period will pull the SCL line low. The
SCA line high time is determined by the device with the
shortest high period. This is shown in the Figure 7-12.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 47
PIC14000
2
FIGURE 7-13: I C BLOCK DIAGRAM
Internal
data bus
MISC<4>
Read
Write
RC6/SCLA
2
I CBUF
SCK
SDA
RC7/SDAA
Shift
4:2
MUX
clock
2
I CSR
RD0/SCLB
RD1/SDAB
MSB
Match Detect
Addr_Match
2
I CADD
Set, Reset
S, P bits
(I CSTAT Reg)
Start and
Stop bit detect
2
2
2
• I C Slave mode (7-bit address), with start and
stop bit interrupts enabled
7.5
I C Operation
2
2
The I C module in I C mode fully implements all slave
functions, and provides support in hardware to facilitate
software implementations of the master functions. The
2
• I C Slave mode (10-bit address), with start and
stop bit interrupts enabled
2
• I C Firmware Controlled Master mode, slave is
2
I C module implements the standard and fast mode
specifications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RC6/SCLA pin, which is the I C clock, and the
RC7/SDAA pin which acts as the I C data. The I C
module can also be accessed via the RD0/SCLB and
RD1/SDAB pins by setting I CSEL (MISC<4>).The
user must configure these pins as inputs or outputs
through the TRISC<7:6> or TRISD<1:0> bits. A block
diagram of the I C module in I C mode is shown in
Figure 7-13. The I C module functions are enabled by
idle
2
2
Selection of any I C mode with the I CEN bit set, forces
the SCL and SDA pins to be open collector, provided
these pins are set to inputs through the TRISC bits.
2
2
2
2
The I CSTAT register gives the status of the data
2
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address, if the next byte is the completion of
10-bit address, and if this will be a read or write data
2
2
2
2
transfer. The I CSTAT register is read only.
2
setting the I CCON<5> bit.
2
The I CBUF is the register to which transfer data is
2
2
2
The I C module has five registers for I C operation.
These are the:
written to or read from. The I CSR register shifts the
data in or out of the device. In receive operations, the
2
2
2
2
I CBUF and I CSR create a double buffered receiver.
This allows reception of the next byte before reading
the last byte of received data. When the complete byte
• I C Control Register (I CCON)
2
2
• I C Status Register (I CSTAT)
2
• Serial Receive/Transmit Buffer (I CBUF)
2
is received, it is transferred to the I CBUF and PIR1<3>
2
2
• I C Shift Register (I CSR) - Not directly
accessible
is set. If another complete byte is received before the
2
I CBUF is read, a receiver overflow has occurred and
2
2
• Address Register (I CADD)
the I CCON<6> is set.
2
2
2
The I CCON register (14h) allows control of the I C
The I CADD register holds the slave address. In 10-bit
2
operation. Four mode selection bits (I CCON<3:0>)
allow one of the following I C modes to be selected:
mode, the user needs to write the high byte of the
address (1 1 1 1 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7-A0).
2
2
• I C Slave mode (7-bit address)
2
• I C Slave mode (10-bit address)
DS40122B-page 48
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
7.5.1
SLAVE MODE
In this case, the I CSR value is not loaded into the
2
2
I CBUF, but the I CIF bit is set. Table 7-2 shows what
happens when a data transfer byte is received, given
the status of the BF and I COV bits. The shaded boxes
show the conditions where user software did not
properly clear the overflow condition. The BF flag is
cleared by reading the I CBUF register while the
In slave mode, the SCLx and SDAx pins must be
configured as inputs (TRISC<7:6> or TRISD<1:0> are
set). The I C module will override the input state with
2
2
the output data when required (slave-transmitter).
2
When an address is matched or the data transfer from
an address match is received, the hardware
automatically will generate the acknowledge (ACK)
pulse, and then load the I CBUF with the received
value in the I CSR.
2
I COV bit is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I C specification as well as the requirement of the I C
module is shown in the AC timing specifications.
2
2
2
2
2
There are two conditions that will cause the I C module
not to give this ACK pulse. These are if either (or both)
occur:
2
• the Buffer Full (BF), I CSTAT<0>, bit was set
before the transfer was received, or
2
2
• the Overflow (I COV), I CCON<6> bit was set
before the transfer was received.
TABLE 7-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as DataTransfer
2
is Received
Set I CIF bit
2
2
2
2
Generate ACK Pulse
BF
I COV
I CSR-> I CBUF
(I C interrupt if enabled)
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 49
PIC14000
2
7.5.1.1
ADDRESSING
4. Receive second (low) byte of address (I CIF, BF
and UA are set).
2
2
Once the I C module has been enabled, the I C waits
for a START to occur. Following the START, the 8-bits
2
5. Update I CADD with first (high) byte of address
(clears UA, if match releases SCL line).
2
are shifted into the I CSR. All incoming bits are
sampled with the rising edge of the clock (SCL) line.
The I CSR<7:1> is compared to the I CADD register.
The address is compared on the falling edge of the
eighth clock (SCL) pulse. If the addresses match, and
2
2
6. Read I CBUF (clears BF) and clear I CIF
7. Receive Repeated START.
2
2
2
8. Receive first (high) byte of address (I CIF and
BF are set).
2
2
2
the BF and I COV bits are clear, the following things
9. Read I CBUF (clears BF) and clear I CIF.
happen:
7.5.1.2 RECEPTION
2
2
•
I CSR loaded into I CBUF
• Buffer Full (BF) bit is set
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the I CSTAT
2
• ACK pulse is generated
2
2
register is cleared. The received address is loaded into
•
I C Interrupt Flag (I CIF) is set (interrupt is
2
2
the I CBUF.
generated if enabled (I CIE set) on falling edge of
ninth SCL pulse.
When the address byte overflow condition exists then
no acknowledge (ACK) pulse is given. An overflow
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 7-5). The five most
significant bits (MSbs) of the first address byte specify
if this is a 10-bit address. The R/W bit (bit 0) must
specify a write, so the slave device will received the
second address byte. For a 10-bit address the first byte
would equal ‘1 1 1 1 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7-9 for
slave-transmitter:
2
condition is defined as either the BF bit (I CSTAT<0>)
2
2
is set or the I COV bit (I CCON<6>) is set
(Figure 7-14).
2
An I CIF interrupt is generated for each data transfer
2
byte. The I CIF bit must be cleared in software, and the
2
I CSTAT register is used to determine the status of the
byte. In master mode with slave enabled, three inter-
rupt sources are possible. Reading BF, P and S will
indicate the source of the interrupt.
2
1. Receive first (high) byte of address (I CIF, BF
Caution: BF is set after receipt of eight bits and auto-
2
and UA are set).
matically cleared after the I CBUF is read.
2
However, the flag is not actually cleared
until receipt of the acknowledge pulse. Oth-
erwise extra reads appear to be valid.
2. Update I CADD with second (low) byte of
address (clears UA and releases SCL line).
2
2
3. Read I CBUF (clears BF) and clear I CIF.
2
FIGURE 7-14: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
R/W=0
Receiving Address
Receiving Data
Receiving Data
ACK
ACK
9
ACK
9
A7 A6 A5 A4
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
7
1
2
4
9
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
Bus Master
terminates
transfer
Cleared in software
I2CBUF is read
I2COV (I2CCON<6>)
I2COV is set
because I2CBUF is
still full. ACK is not sent.
DS40122B-page 50
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
7.5.1.3
TRANSMISSION
A I CIF interrupt is generated for each data transfer
2
byte. The I CIF bit must be cleared in software, and the
I CSTAT register is used to determine the status of the
byte. The I CIF bit is set on the falling edge of the ninth
clock pulse.
2
When the R/W bit of the address byte is set and an
address match occurs, the R/W bit of the I CSTAT
2
2
register is set. The received address is loaded into the
2
I CBUF TheACK pulse will be sent on the ninth bit, and
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. The slave
then monitors for another occurrence of the START bit.
If the SDA line was low (ACK), the transmit data must
the SCL pin is held low. The transmit data must be
2
loaded into the I CBUF register, which also loads the
2
I CSR register. Then the SCL pin should be enabled by
2
setting the CKP bit (I CCON<4>). The eight data bits
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 7-15).
2
be loaded into the I CBUF register, which also loads
2
the I CSR register. Then the SCL pin should be
2
enabled by setting the CKP bit (I CCON<4>).
2
FIGURE 7-15: I C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SCL held low
while CPU
responds to I2CIF
Data in
sampled
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
From I2CIF interrupt
service routine
cleared in software
I2CBUF is written in software
CKP (I2CCON<4>)
Set bit after writing to I2CBUF
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 51
PIC14000
7.5.2
MASTER MODE
7.5.3
MULTI-MASTER MODE
Master mode operation is supported by interrupt
generation on the detection of the START and STOP.
The STOP(P) and START(S) bits are cleared from a
In multi-master mode, the interrupt generation on the
detection of the START and STOP allows the
determination of when the bus is free. The STOP (P)
and START (S) bits are cleared from a reset or when
2
reset or when the I C module is disabled. Control of the
2
2
2
I C bus may be taken when the P bit is set, or the bus
the I C module is disabled. Control of the I C bus may
be taken when the P bit is set, or the bus is idle and
both the S and P bits are cleared. When the bus is
is idle and both the S and P bits are cleared.
In master mode, the SCL and SDA lines are
manipulated by changing the corresponding
TRISC<7:6> or TRISD<1:0> bits to an output (cleared).
The output level is always low, regardless of the
value(s) in PORTC<7:6> or PORTD<1:0>. So when
transmitting data, a “1” data bit must have the
TRISC<7> or TRISD<1> bit set (input) and a “0” data
bit must have the TRISC<7> or TRISD<1> bit cleared
(output). The same scenario is true for the SCL line
with the TRISC<6> or TRISD<0> bit.
2
busy, enabling the I C interrupt will generate the
interrupt when the STOP occurs.
In multi-master operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<7:6>). There are two stages
where this arbitration can be lost, these are:
2
The following events will cause the I C interrupt Flag
• Address Transfer
• Data Transfer
2
2
(I CIF) to be set (I C interrupt if enabled):
• START
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, the device may being addressed. If
addressed an ACK pulse will be generated. If
arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
• STOP
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
2
2
slave mode idle (I CM3...I CM0 = 1011b) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
2
TABLE 7-3:
REGISTERS ASSOCIATED WITH I C OPERATION
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0B/8Bh
0Ch
8Ch
13h
INTCON
GIE
PEIE
—
T0IE
—
r
r
T0IF
RCIF
RCIE
r
r
2
PIR1
CMIF
CMIE
PBIF
PBIE
I CIF
ADCIF
ADCIE
OVFIF
OVFIE
2
PIE1
2
—
—
I CIE
2
I CBUF I C Serial Port Receive Buffer/Transmit Register
2
2
2
93h
I CADD I C mode Synchronous Serial Port (I C mode) Address Register
2
2
2
2
2
2
2
14h
I CCON
WCOL
—
I CON
I CEN
CKP
P
I CM3
I CM2
I CM1
I CM0
2
94h
I CSTAT
—
D/A
S
R/W
UA
BF
2
9Eh
87h
MISC
SMHOG SPGNDB
SPGNDA I CSEL SMBUS INCLKEN
OSC2
OSC1
TRISC
TRISD
TRISC7
TRISD7
TRISC6
TRISD6
TRISC5
TRISD5
TRISC4 TRISC3
TRISD4 TRISD3
TRISC2
TRISD2
TRISC1 TRISC0
TRISD1 TRISD0
88h
Legend: — = Unimplemented location, read as ‘0’
r
= reserved locations, default is POR value and should not be overwritten with any value
2
Note: Shaded boxes are not used by the I C module.
DS40122B-page 52
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 7-16: MISC REGISTER
9Eh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
OSC2
R/W
0
Bit 0
OSC1
R
2
MISC
SMHOG SPGNDB SPGNDA I CSEL
SMBUS INCLKEN
Read/Write
POR value 00h
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
X
Bit
Name
Function
SMHOG enable
2
1 = Stretch I C CLK signal (hold low) when receive data buffer is full (refer to
Section 7.5.4). For pausing I C transfers while preventing interruptions of A/D
2
B7
SMHOG
conversions.
2
0 = Disable I C CLK stretch.
Serial Port Ground Select
B6
B5
B4
SPGNDB
SPGNDA
1 = PORTD<1:0> ground reference is the RD5/AN5 pin.
0 = PORTD<1:0> ground reference is VSS.
Serial Port Ground Select
1 = PORTC<7:6> ground reference is the RA1/AN1 pin.
0 = PORTC<7:6> ground reference is VSS.
2
I C Port select Bit.
1 = PORTD<1:0> are used as the I C clock and data lines.
0 = PORTC<7:6> are used as the I C clock and data lines.
2
2
I CSEL
2
SMBus-Compatibility Select
1 = SMBus compatibility mode is enabled. PORTC<7:6> and PORTD<1:0> have
SMBus-compatible input thresholds.
B3
SMBus
0 = SMBus-compatibility is disabled. PORTC<7:6> and PORTD<1:0> have Schmitt Trig-
ger input thresholds.
Oscillator Output Select (available in IN mode only).
1 = Output IN oscillator signal divided by four on OSC2 pin.
0 = Disconnect IN oscillator signal from OSC2 pin.
B2
B1
B0
INCLKEN
OSC2
OSC2 output port bit (available in IN mode only).
Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the
output latch.
OSC1 input port bit (available in IN mode only).
Reads from this location return the status of the OSC1 pin in IN mode. Writes have no
effect.
OSC1
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 53
PIC14000
2
FIGURE 7-17: OPERATION OF THE I C IN IDLE_MODE, RCV_MODE OR XMIT_MODE
IDLE_MODE (7-bit):
if (Addr_match)
{
Set interrupt;
if (R/W = 1)
{
}
Send ACK = 0;
set XMIT_MODE;
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((I2CBUF=Full) OR (I2COV = 1))
{
Set I2COV;
Do not acknowledge;
}
{
else
transfer I2CSR → I2CBUF;
send ACK = 0;
}
Receive 8-bits in I2CSR;
Set interrupt;
XMIT_MODE:
While ((I2CBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if (ACK Received = 1)
{
}
End of transmission;
Go back to IDLE_MODE;
else if (ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{
PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((I2CBUF = Full) OR ((I2COV = 1))
{
Set I2COV;
Do not acknowledge;
}
{
else
Set UA = 1;
Send ACK = 0;
While (I2CADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{
PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (I2CADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
if (PRIOR_ADDR_MATCH)
{
{
send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
DS40122B-page 54
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
7.5.4
SMBus AND ACCESS.bus
CONSIDERATIONS
• A mechanism to stretch the I C clock time has
been implemented to support SMBus slave
transactions. The SMHOG bit (MISC<7>) allows
hardware to automatically force and hold the I C
clock line low when a data byte has been
2
PIC14000 is compliant with the SMBus specification
published by Intel. Some key points to note regarding
the bus specifications and how it pertains to the
PIC14000 hardware are listed below:
received. This prevents the SMBus master from
overflowing the receive buffer in instances where
the microcontroller may be to busy servicing
• SMBus has fixed input voltage thresholds.
PIC14000 I/O buffers have programmable levels
that can be selected to be compatible with both
SMBus threshold levels via the SMBus and
SPGND bits in the MISC register.
2
higher priority tasks to respond to a I C module
interrupt. Or, if the microcontroller is in SLEEP
mode and needs time to wake-up and respond to
2
the I C interrupt.
FIGURE 7-18: SMHOG STATE MACHINE
SMHOG = 0
A
2
I CIF = 1
2
I CIF = 1
E/DRIVE
SCL
B
LOW
2
I CIF = 0
SCL = 0
2
I CIF = 0
C
D
2
I CIF = 1
2
I CIF = 0
SCL = 1
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 55
PIC14000
NOTES:
DS40122B-page 56
Preliminary
1996 Microchip Technology Inc.
PIC14000
The maximum A/D timer count is 65,536. It can be
clocked by the on-chip or external oscillator. At a 4 MHz
oscillation frequency, the maximum conversion time is
16.38 ms for a full count. A typical conversion should
complete before full-count is reached. A timer overflow
flag is set once the timer rolls over (FFFFh to 0000h),
and an interrupt is sent to the CPU, if enabled.
8.0
ANALOG MODULES FOR A/D
CONVERSION
8.1
Overview
The PIC14000 includes analog components to create a
slope A/D converter including:
• Comparator
End-user calibration is simplified or eliminated by mak-
ing use of the on-chip EPROM. Internal component val-
ues are measured at factory final test and stored in the
memory for use by the application firmware.
• 4-bit programmable current source
• 16-channel analog mux
• 16-bit timer with capture register
Periodic conversion cycles should be performed on the
bandgap and slope references (described in
Section 9.0) to compensate for A/D component drift.
Measurements for the reference voltage count are
equated to the voltage value stored into EPROM during
calibration. All other channel measurements are
compensated for by ratioing the actual count with the
bandgap count and multiplying by the bandgap voltage
value stored in EPROM. Since all measurements are
relative to the reference, offset voltages inherent in the
comparator are cancelled out. See AN624, “PIC14000
A/D Theory and Implementation” for further details of
A/D operation.
Each channel is converted independently by means of
a slope conversion method using a single precision
comparator. The programmable current source feeds
an external 0.1 µF (nominal) capacitor to generate the
ramp voltage used in the conversion.
8.2
Conversion Process
These are the steps to perform data conversion:
• Clear REFOFF (SLPCON<5>) and ADOFF
(SLPCON<0>) bits to enable the A/D module.
• Initialize ADCON1<7:4> to initialize the program-
mable current source.
• Set ADRST (ADCON0<1>), for a minimum of 200
µs to stop the timer and fully discharge the ramp
capacitor to ground.
The analog components used in the conversion and
the A/D timer can be disabled during idle periods for
maximum power savings. Power-saving can be
achieved via software and/or hardware control
(Section 10.8).
• The A/D timer (ADTMR) increments from 0000h
to FFFFh and must be initialized before each con-
version.
8.3
A/D Timer (ADTMR) Module
• To start a conversion, clear ADRST through soft-
ware, it will allow the timer to begin counting and
the ramp capacitor to begin charging.
The A/D timer (ADTMR) is comprised of a 16-bit up
timer, which is incremented every oscillator cycle.
ADTMR is reset to 0000h by a power-up reset; other-
wise the software must initialize it after each conver-
sion. A separate 16-bit capture register (ADCAP) is
used to capture the ADTMR count if an A/D capture
event occurs (see below). Both the A/D timer and cap-
ture register are readable and writable. The low byte of
the A/D timer (ADTMRL) is accessed at location 0Eh
while the high byte (ADTMRH) is accessed at location
0Fh. Similarly, the low byte of the A/D capture register
(ADCAP) is accessed at location 15h, and the high byte
is located at 16h.
• When the ramp voltage exceeds the analog input,
the comparator output changes from high to low.
• This transition causes a capture event and copies
the current A/D timer value into the 16-bit capture
register.
• An interrupt is generated to the CPU if enabled.
Note: The A/D timer continues to run following a
capture event.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 57
PIC14000
Caution: Reading or writing the ADTMR register
during an A/D conversion cycle can pro-
duce unpredictable results and is not
recommended.
A CPU interrupt will be generated if bit ADCIE
(PIE1<1>) is set to ‘1’ (interrupt enabled). In addition,
the Global Interrupt Enable and Peripheral Interrupt
Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
conversion cycle. Note that this interrupt can only occur
once per conversion cycle.
Note: The correct sequence for writing the
ADTMR register is HI byte followed by LO
byte. Reversing this order will prevent the
A/D timer from running.
In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
is asserted (PIR1<0>). The timer continues to incre-
ment following a timer overflow. A CPU interrupt can be
generated if bit OVFIE (PIE1<0>) is set (interrupt
enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
be set. Software is responsible for clearing the OVFIF
flag prior to the next conversion cycle.
During conversion one or both of the following events
will occur:
1. capture event
2. timer overflow
In a capture event, the comparator trips when the slope
voltage on the CDAC output exceeds the input voltage,
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
FIGURE 8-1: A/D BLOCK DIAGRAM
OSC1
0
1
ADOFF
WRITE_TMR
ADRST
Internal
Oscillator
Clock
Stop
Logic
FOSC
(Configuration Bit)
AMUXOE
(ADCON0<2>)
RA0/AN0
15
14
13
12
11
RESERVED
RESERVED
RD7/AN7
RD6/AN6
RD5/AN5
RD4/AN4
Prog. Ref. B
Prog. Ref. A
Temp sensor
SREFLO
ADOFF
Note 2
10
ADTMRH
A/D Capture
ADCAPH
ADTMRL
ADCAPL
Timer
Overflow
(OVFIF, PIR1<0>)
9
Analog
Mux
8
~ 1 kohm
7
6
5
4
3
2
1
0
SREFHI
Bandgap Ref.
RA3/AN3
Internal
Data
Bus
RA2/AN2
RA1/AN1
A/D
RA0/AN0
Capture Interrupt
(ADCIF, PIR1<1>)
4
ADCON0<7:4>
~2.5uA~5uA~10uA~20uA
ADOFF
(SLPCON<0>)
CDAC
ADCON1<7:4>
0.1µF
(nominal)
~100 Ω
ADRST (ADCON0<1>)
Note 1
Note 1:
Note 2:
All current sources are disabled if ADRST = ‘1’
Approximately 3.5 microsecond time constant
4-Bit Current DAC
DS40122B-page 58
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 8-2: EXAMPLE A/D CONVERSION CYCLE
CAPTURE
CLK
ADTMR INCREMENTS
ADRST
ADCON0<1>
ADTMR
COUNT
XX+1 XX+2 XX+3
XX
XX+8 XX+9
COMPARE
CDAC
ADCIF,
PIR1<1>
(must be cleared by software)
Capture
Register
XX
XX+8
FIGURE 8-3: A/D CAPTURE TIMER (LOW BYTE)
0Eh
Bit 7
b7
Bit 6
b6
Bit 5
b5
Bit 4
b4
Bit 3
b3
Bit 2
Bit 1
b1
Bit 0
b0
ADTMRL
Read/Write
POR value 00h
b2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
FIGURE 8-4: A/D CAPTURE TIMER (HIGH BYTE)
0Fh
Bit 7
b15
R/W
0
Bit 6
b14
R/W
0
Bit 5
b13
R/W
0
Bit 4
b12
R/W
0
Bit 3
b11
R/W
0
Bit 2
b10
R/W
0
Bit 1
b9
Bit 0
b8
ADTMRH
Read/Write
POR value 00h
R/W
0
R/W
0
FIGURE 8-5: A/D CAPTURE REGISTER (LOW BYTE)
15h
Bit 7
b7
Bit 6
b6
Bit 5
b5
Bit 4
b4
Bit 3
b3
Bit 2
b2
Bit 1
b1
Bit 0
b0
ADCAPL
Read/Write
POR value 00h
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
FIGURE 8-6: A/D CAPTURE REGISTER (HIGH BYTE)
16h
Bit 7
b15
R/W
0
Bit 6
b14
R/W
0
Bit 5
b13
R/W
0
Bit 4
b12
R/W
0
Bit 3
b11
R/W
0
Bit 2
b10
R/W
0
Bit 1
b9
Bit 0
b8
ADCAPH
Read/Write
POR value 00h
R/W
0
R/W
0
Legend: U= unimplemented, X = unknown.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 59
PIC14000
8.4
A/D Comparator
8.5
Analog Mux
The PIC14000 includes a high gain comparator for
A/D conversions. Thepositive input terminal of theA/D
comparator is connected to the output of an analog
mux through an RC low-pass filter. The nominal
time-constant for the RC filter is 3.5 µs. The negative
input terminal is connected to the external 0.1 µF (nom-
inal) ramp capacitor.
A total of 16 channels are internally multiplexed to the
single A/D comparator positive input. Four
configuration bits (ADCON0<7:4>) select the channel
to be converted. Refer to Table 8-1 for channel assign-
ments.
TABLE 8-1:
A/D CHANNEL ASSIGNMENT
ADCON0(7:4)
A/D Channel
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
RA0/AN0 pin
RA1/AN1 pin
RA2/AN2 pin
RA3/AN3 pin
Bandgap reference voltage
Slope reference SREFHI
Slope reference SREFLO
Internal temperature sensor
Programmable reference A output
Programmable reference B output
RD4/AN4 pin
RD5/AN5 pin
RD6/AN6 pin
RD7/AN7 pin
Reserved
Reserved
DS40122B-page 60
Preliminary
1996 Microchip Technology Inc.
PIC14000
The programmable current source output is tied to the
CDAC pin and is used to charge an external capacitor
to generate the ramp voltage for the A/D comparator.
(Refer to Figure 8-1.) This capacitor should have a low
voltage-coefficient as found in teflon, polypropylene, or
polystyrene capacitors, for optimum results. The
capacitor must be discharged at the beginning of each
conversion cycle by asserting ADRST (ADCON0<1>)
for at least 200 µs to allow a complete discharge.
Asserting ADRST disables the current sources inter-
nally. Current flow begins when ADRST is cleared.
8.6
Programmable Current Source
Four configuration bits (ADCON1<7:4>) are used to
control a programmable current source for generating
the ramp voltage to the A/D comparator. It allows com-
pensation for full-scale input voltage, clock frequency
and CDAC capacitor tolerance variations. The current
values range from 0 to 33.75 µA (nominal) in 2.25 µA
increments. The intermediate values of the current
source are as follows:
TABLE 8-2:
PROGRAMMABLE CURRENT
SOURCE SELECTION
Current Source
ADCON1<7:4>
Output
0
0
0
0
OFF - all current
sources disabled
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.25 µA
4.5 µA
6.75 µA
9 µA
11.25 µA
13.5 µA
15.75 µA
18 µA
20.25 µA
22.5 µA
24.75 µA
27 µA
29.25 µA
31.5 µA
33.75 µA
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 61
PIC14000
8.7
A/D Control Registers
Two A/D control registers are provided on the
PIC14000 to control the conversion process. These are
ADCON0 (1Fh) and ADCON1 (9Fh). Both registers are
readable and writable.
TABLE 8-3:
A/D CONTROL AND STATUS REGISTER 0
1Fh
Bit 7
Bit 6
Bit 5
Bit 4
ADCS0
R/W
Bit 3
—
Bit 2
AMUXOE
R/W
Bit 1
ADRST
R/W
Bit 0
ADZERO
R/W
ADCON0
Read/Write
POR value 02h
ADCS3 ADCS2 ADCS1
R/W
0
R/W
0
R/W
0
U
0
0
0
1
0
Bit
Name
ADCS3
Function
ADCS2
ADCS1
ADCS0
A/D Channel Selects. Refer to Table 8-1.
B7-B4
B3
B2
—
Unimplemented. Read as ‘0’.
Analog Mux Output Enable
1 = Connect AMUX Output to RA0/AN0 pin (overrides TRISA<0> setting)
0 = RA0/AN0 pin normal
AMUXOE
A/D Reset Control Bit
B1
B0
ADRST
1 = Stop the A/D Timer, discharge CDAC capacitor
0 = Normal operation (A/D running)
A/D Zero Select Control. (Refer to Section 9.2)
1 = Enable zeroing operation on RA1/AN1 and RD5/AN5
0 = Normal operation (sample RA1/AN1 and RD5/AN5 pins)
ADZERO
DS40122B-page 62
Preliminary
1996 Microchip Technology Inc.
PIC14000
TABLE 8-4:
A/D CONTROL AND STATUS REGISTER 1
9Fh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PCFG1
R/W
Bit 0
PCFG0
R/W
ADCON1
Read/Write
POR value 00h
ADDAC3 ADDAC2 ADDAC1 ADDAC0 PCFG3 PCFG2
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
0
Bit
Name
Function
ADDAC3
ADDAC2
ADDAC1
ADDAC0
B7-B4
A/D Current Source Selects. Refer to Table 8-2.
PCFG3
PCFG2
PORTD Configuration Selects
(See Table 8-5)
B3-B2
PCFG1
PCFG0
PORTA Configuration Selects
(See Table 8-5)
B1-B0
TABLE 8-5:
PORTA AND PORTD CONFIGURATION
ADCON1<1:0>
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3
ADCON1<3:2>
RD4/AN4
RD5/AN5
RD6/AN6
RD7/AN7
0 0
0 1
1 0
1 1
A
A
A
D
A
A
A
D
A
A
D
D
A
D
D
D
Legend: A = Analog input, D = Digital I/O
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 63
PIC14000
Choosing the correct ramp capacitor for the CDAC pin
is required to achieve the desired resolution, conver-
sion time and full scale input voltage. The equation for
selecting the ramp capacitor value is:
8.8
A/D Speed, Resolution and Capacitor
Selection
The conversion time for the A/D converter on the
PIC14000 can be calculated using the equation:
Capacitor = (conversion time in seconds) X
(current source output in amps) / (full scale in volts)
N
Conversion Time = (1/Fosc) x 2
Table 8-6 provides example capacitor values for the
desired A/D resolution, conversion time, and full scale
voltage measurement.
Where Fosc is the oscillator frequency and N is the
number of bits of resolution desired.
Therefore at 4MHz, the conversion time for 16 bits is
16.384 msec. Conversely, it is 256 µsec for 10 bits.
TABLE 8-6:
CDAC CAPACITOR SELECTION (EXAMPLES FOR FULL SCALE OF 3.5V AND 1.5V)
Calculated
A/D
Resolution
(Bits)
A/D Current
Source Output
(µamps)
CDAC
Capacitor
(Farads)
CDAC Capacitor
Nearest Standard
Value
Conversion Time
Full Scale
(Volts)
(Seconds)
16
14
12
0.016384
0.004096
0.001024
3.5
3.5
3.5
24.75
24.75
24.75
1.17E-07
2.93E-08
7.31E-09
.1uF
.022uF
6800pF
16
14
12
0.016384
0.004096
0.001024
1.5
1.5
1.5
24.75
24.75
24.75
2.73E-07
6.83E-08
1.71E-08
0.22µF
68nF
15nF
Note: Assumes FOSC of 4 MHz.
DS40122B-page 64
Preliminary
1996 Microchip Technology Inc.
PIC14000
9.2.1
ZEROING/FILTERING SWITCHES
9.0
OTHER ANALOG MODULES
The PIC14000 has additional analog modules for
mixed signal applications. These include:
The RA1/AN1 and RA5/AN5 inputs also have a
matched pair of pass gates useful for current-measure-
ment applications. One gate is connected between the
pin and the level-shift network. The second pass gate
is connected to ground as shown in Figure 9-1. By set-
ting the ADZERO bit (ADCON0<0>), a zero-current
condition is simulated. Subsequent A/D readings are
calculated relative to this zero count from the A/D. This
zeroing of the current provides very high accuracies at
low current values where it is most needed.
• bandgap voltage reference
• comparators with programmable references
• internal temperature sensor
• voltage regulator control
9.1
Bandgap Voltage Reference
The bandgap reference circuit is used to generate a
1.2V nominal stable voltage reference for the A/D and
the low-voltage detector. The bandgap reference is
channel 4 of the analog mux. The bandgap reference
voltage is stored in the calibration space EPROM
(See Table 4-2). To enable the bandgap reference
REFOFF (SLPCON<5>) must be cleared.
For additional noise filtering or for capturing short dura-
tion periodic pulses, an optional filter capacitor may be
connected from the SUM pin to ground (this feature is
available for RA1/AN1 only). This forms an RC network
with the internal 100 kohm (nominal) bias resistor to act
as a low pass filter. The capacitor size can be adjusted
for the desired time constant.
9.2
Level-Shift Networks
A switch is included between the output from the
RA1/AN1 level-shift network and the SUM pin. This
switch is closed during A/D sampling periods and is
automatically opened during a zeroing operation (if
ADZERO = '1'). If not required in the system, this pin
should be left floating (not connected).
The RA1/AN1 and RA5/AN5 pins have an internal
level-shift network. A current source and resistor are
used to bias the pin voltage by about +0.5V into a range
usable by the A/D converter. The nominal value of bias
current source is 5 µA and the resistor is 100 kohms.
Setting the LSOFF bit (SLPCON<4>) disables the
level-shift networks, so the RA1/AN1 and RA5/AN5
pins can continue to be used as general-purpose ana-
log inputs.
The level-shift function can be turned on by clearing the
LSOFF bit (SLPCON<4>) to '0'.
Note: The minimum voltage permissible at the
RA1/AN1 and RA5/AN5 pins is -0.3V. The
input protection diodes will begin to turn
on beyond -0.3V, introducing significant
errors in the A/D readings. Under no con-
ditions should the pin voltage fall below
-0.5V.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 65
PIC14000
FIGURE 9-1: LEVEL-SHIFT NETWORKS
VDD
RA1/AN1 only
5 µA (nominal)
LSOFF
(SLPCON<4>)
SUM
VDD
Input Protection
Diodes
External
Capacitor
(Optional)
RA1/AN1
RD5/AN5
*
To A/D mux,
programmable
reference
100 kΩ
(nominal)
*
comparators
ADZERO
(ADCON<0>)
LSOFF
(SLPCON<4>)
*These switches are a matched pair
9.3
Slope Reference Voltage Divider
9.4
Internal Temperature Sensor
The slope reference voltage divider circuit, consisting
of a buffer amplifier and resistor divider, is connected to
the internal bandgap reference producing two other
voltage references called SREFHI and SREFLO (see
Figure 9-2). SREFHI is nominally the same as the
bandgap voltage, 1.2V, and SREFLO is nominally
0.13V. These reference voltages are available on two
of the analog multiplexer channels. The A/D module
and firmware can measure the SREFHI and SREFLO
voltages, and in conjunction with the KREF and KBG cal-
ibration data correct for the A/D's offset and slope
errors. See AN624 for further details.
The internal temperature sensor is connected to the
channel 7 input of the A/D converter. The sensor volt-
age is 1.05V nominal at 25°C and its temperature coef-
ficient is approximately 3.7mV/°C. The sensor voltage
at 25°C and the temperature coefficient values are
stored in the calibration space EPROM (See
Table 4-2). To enable the temperature sensor, the
TEMPOFF bit (SLPCON<1>) must be cleared.
DS40122B-page 66
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 9-2: SLOPE REFERENCE DIVIDER
ADOFF (SLPCON<0>)
VREF
+
_
SREFHI
Bandgap
Reference
To A/D
MUX
REFOFF (SLPCON<5>)
SREFLO
SREFHI
~
=
SREFLO
KREF
9
SREFLO
SREFHI - SREFLO
The comparator outputs are visible at either
RC1/CMPA or RD2/CMPB pins by setting the CMAOE
(CMCON<1>) or CMBOE (CMCON<5>) bits. Setting
CMxOE does not affect the comparator operation. It
only enables the pin function regardless of the port
TRIS register setting.
9.5
Comparator and Programmable
Reference Modules
9.5.1
COMPARATORS
The PIC14000 includes two independent low-power
comparators for comparing the programmable refer-
ence outputs to either the RA1/AN1 or RA5/AN5 pins.
The negative input of each comparator is tied to one of
the reference outputs as shown in Figure 9-3. The
comparator positive inputs are connected to the output
of the RA1/AN1 and RA5/AN5 level-shift networks.
Both the references and the comparators are enabled
by clearing the CMOFF (SLPCON<2>) bit.
9.5.2
PROGRAMMABLE REFERENCES
The PIC14000 includes two independent, programma-
ble voltage references. Each reference is built using
two resistor ladders, bandgap-referenced current
source, and analog multiplexers. The first ladder con-
tains 32 taps, and is divided into three ranges (upper,
middle, and lower) to provide a coarse voltage adjust-
ment. The coarse ladder includes 1k and 10k resistors
yielding a step size of either 5 or 50 mV (nominal)
depending on the selected range. Figure 9-8 shows the
comparator and reference architecture.
At reset, the RA1/AN1 level-shift output is connected to
the positive inputs of both comparators. This allows a
window comparison of the RA1/AN1 voltage using the
two programmable references and comparators. Set-
ting CMBOE (CMCON<5>) changes the configuration
so that RA1/AN1 and RA5/AN5 may be independently
monitored.
The comparator outputs can be read by the CMAOUT
(CMCON<2>) and CMBOUT (CMCON<6>) bits. These
are read-only bits and writes to these locations have no
effect.
A second ladder contains eight taps, and is connected
across the selected coarse ladder resistor to increase
resolution. This subdivides the coarse ladder step by
approximately 1/8. Thus, resolutions approaching 5/8
mV are obtainable.
Either a rising or falling comparator output can gener-
ate an interrupt to the CPU as controlled by the polarity
bits CPOLA (CMCON<0>) and CPOLB (CMCON<4>).
The CMIF bit (PIR1<7>) interrupt flag is set whenever
the exclusive-OR of the comparator output CMxOUT
and the CPOLx bits equal a logic one. As with other
peripheral interrupts, the corresponding enable bit
CMIE (PIE1<7>) must also be set to enable the com-
parator interrupt. In addition, the global interrupt enable
and peripheral interrupt enable bits INTCON<7:6>
must also be set. This comparator interrupt is level sen-
sitive.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 67
PIC14000
Two registers PREFA (9Bh) and PREFB (9Ch) are
used to select the reference output voltages. The
PREFx<7:3> bits select the output from the coarse lad-
der, while PREFx<2:0> bits are for the fine-tune adjust-
ment. Table 9-1 and Table 9-2 show the reference
decoding.
The reference outputs are also connected to two inde-
pendent comparators, COMPA and COMPB. Thus, the
references can be used to set the comparator trip-
points. The A/D converter can also monitor the refer-
ence outputs via A/D channels 8 and 9. Refer to
Section 8 for the description of the A/D operation.
These voltages are visible at either RC0/REFA or
RD3/REFB pins by setting the CMAOE (CMCON<1>)
or CMBOE (CMCON<5>) bits. Setting CMxOE does
not affect the reference voltages. It only enables the pin
function regardless of the port TRIS register setting.
These outputs are not buffered, so they cannot directly
drive any DC loads.
The programmable reference output is designed to
track the output from the level shift network. However,
there will always be some mismatch due to component
drift. For best accuracy, the A/D should be used to peri-
odically calibrate the references to the desired
set-point.
FIGURE 9-3: COMPARATOR AND PROGRAMMABLE REFERENCE BLOCK DIAGRAM
(ONE OF TWO SHOWN)
CMOFF
~5 µA
PREFx<7:3>
Coarse Adjust
Fine Tune Adjust
~0.85V
Analog
Mux
(1 of 32)
RC0/REFA or
RD3/REFB
Analog
Mux
(1-of-8)
Analog
Mux
(1 of 32)
PREFx<2:0>
CMxOE
~0.15V
To A/D
Converter
PREFx<7:3>
Programmable
Reference
To CMxOUT bit,
CMCON register
RC1/CMPA or
RD2/CMPB
_
From AN1 Level
Shift Network
+
CMBOE
CPOLx
CMIF bit
PIR1<7>
From Other
Comparator
From AN5 Level
Shift Network
Channel B only
DS40122B-page 68
Preliminary
1996 Microchip Technology Inc.
PIC14000
TABLE 9-1:
PROGRAMMABLE REFERENCE COARSE RANGE SELECTION
Nominal
Output Voltage
PREFx<7:3>
Range (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.8000 - 0.8500
0.7500 - 0.8000
0.7000 - 0.7500
0.6500 - 0.7000
0.6000 - 0.6500
0.5500 - 0.6000
0.5450 - 0.5500
0.5400 - 0.5450
0.5350 - 0.5400
0.5300 - 0.5350
0.5250 - 0.5300
0.5200 - 0.5250
0.5150 - 0.5200
0.5100 - 0.5150
0.5050 - 0.5100
0.5000 - 0.5050
0.4950 - 0.5000
0.4900 - 0.4950
0.4850 - 0.4900
0.4800 - 0.4850
0.4750 - 0.4800
0.4700 - 0.4750
0.4650 - 0.4700
0.4600 - 0.4650
0.4550 - 0.4600
0.4500 - 0.4550
0.4000 - 0.4500
0.3500 - 0.4000
0.3000 - 0.3500
0.2500 - 0.3000
0.2000 - 0.2500
0.1500 - 0.2000
Upper
Middle
Lower
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 69
PIC14000
TABLE 9-2:
PROGRAMMABLE
REFERENCE FINE RANGE
SELECTION
Fractional Value Of The
PREFx<2:0>
Coarse Range
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1/8
1/4
3/8
1/2
5/8
3/4
7/8
1
0
1
1
0
0
1
1
FIGURE 9-4: PROGRAMMABLE REFERENCE TRANSFER FUNCTION
Upper Range
Middle Range
Lower Range
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
7F
50 4F
00
C8 D7
F8
PREFx Value (hex)
DS40122B-page 70
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 9-5: COMPARATOR CONTROL REGISTER
9Dh
Bit 7
U
Bit 6
Bit 5
Bit 4
CPOLB
R/W
Bit 3
U
Bit 2
Bit 1
CMAOE
R/W
Bit 0
CPOLA
R/W
CMCON
CMBOUT CMBOE
CMAOUT
Read/Write
POR value 00h
—
R
0
R/W
0
—
R
0
0
0
0
0
0
Bit
Name
Function
B7
—
Unimplemented. Read as ‘0’.
Comparator B Output
B6
B5
CMBOUT
CMBOE
Reading this bit returns the status of the comparator B output. Writes to this bit have no
effect.
Comparator B Output Enable
1 = Comparator B output is available on RD2/CMPB pin and Reference B output is
available on RD3/REFB pin.
0 = RD2/CMPB and RD3/REFB assume normal PORTD function.
Comparator B Polarity Bit
B4
B3
B2
CPOLB
—
1 = Invert the output of comparator B.
0 = Do not invert the output of comparator B.
Unimplemented. Read as ‘0’.
Comparator A Output
CMAOUT
Reading this bit returns the status of the comparator A output. Writes to this bit have no
effect.
Comparator A Output Enable
1 = Comparator A output is available on RC1/CMPA pin and Reference A output is
available on RC0/REFA pin.
0 = RC0/REFA and RC1/CMPA assume normal PORTC function.
B1
B0
CMAOE
CPOLA
Comparator A Polarity Bit
1 = Invert the output of comparator A.
0 = Do not invert the output of comparator A.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 71
PIC14000
FIGURE 9-6:
PREFA REGISTER
9Bh
Bit 7
PRA7
R/W
0
Bit 6
PRA6
R/W
0
Bit 5
PRA5
R/W
0
Bit 4
PRA4
R/W
0
Bit 3
PRA3
R/W
0
Bit 2
PRA2
R/W
0
Bit 1
PRA1
R/W
0
Bit 0
PRA0
R/W
0
PREFA
Read/Write
POR value 00h
Bit
Name
Function
PRA7
PRA6
PRA5
PRA4
PRA3
PRA2
PRA1
PRA0
B7-B0
Programmable Reference A Voltage Select Bits.
See Table 9-1 and Table 9-2 for decoding.
FIGURE 9-7:
PREFB REGISTER
9Ch
Bit 7
PRB7
R/W
0
Bit 6
PRB6
R/W
0
Bit 5
PRB5
R/W
0
Bit 4
PRB4
R/W
0
Bit 3
PRB3
R/W
0
Bit 2
PRB2
R/W
0
Bit 1
PRB1
R/W
0
Bit 0
PRB0
R/W
0
PREFB
Read/Write
POR value 00h
Bit
Name
Function
PRB7
PRB6
PRB5
PRB4
PRB3
PRB2
PRB1
PRB0
B7-B0
Programmable Reference B Voltage Select Bits.
See Table 9-1 and Table 9-2 for decoding.
DS40122B-page 72
Preliminary
1996 Microchip Technology Inc.
PIC14000
9.6
Voltage Regulator Output
For systems with a main supply voltage above 6V, an
inexpensive, low quiescent current voltage regulator
can be formed by connecting the VREG pin to an exter-
nal resistor and FET as shown in Figure 9-8. This cir-
cuit will provide a VDD of about 5V, after the voltage
drop across the FET.
FIGURE 9-8: VOLTAGE REGULATOR CIRCUIT
PIC14000
Main
Supply
1-10 µA recommended
VREG
N-FET
(enhancement)
6V
Typical
VDD
Optional External
Voltage Regulator
(Not required for supply voltages
below 6.0 V)
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 73
PIC14000
NOTES:
DS40122B-page 74
Preliminary
1996 Microchip Technology Inc.
PIC14000
• Interrupts
10.0 SPECIAL FEATURES OF THE
CPU
• Watchdog Timer (WDT)
• SLEEP and HIBERNATE modes
• Code protection
What sets apart
a
microcontroller from other
processors are special circuits to deal with the needs of
real time applications. The PIC14000 has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
• In-circuit serial programming
These features will be described in the following
sections.
10.1
Configuration Bits
• OSC (oscillator) selection
- Crystal/resonator
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
- Internal oscillator
• Reset options
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
FIGURE 10-1: CONFIGURATION WORD
2007h
Bit 13-8 Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BITS
r
R/W
1
CPC
r
CPP1 CPP0 PWRTE WDTE
r
FOSC
Read/Write
Erased value
R/W Reserved R/W
R/W
1
R/W
1
R/W
1
Reserved R/W
1
1
1
1
1
Bit
Name
Function
B13-B8
r
Reserved
Calibration Space Code Protection Bit
B7
B6
B5
CPC
r
1 = Calibration space is readable and programmable
0 = Calibration space is write protected
Reserved
Program Space Code Protection Bit
1 = Program space is readable and programmable
0 = Program space is read/write protected
CPP1
Program Space Code Protection Bit
B4
B3
CPP0
1 = Program space is readable and programmable
0 = Program space is read/write protected
Power-up Timer Enable Bit
1 = Power-up timer is disabled
0 = Power-up timer is enabled
PWRTE
Watchdog Timer Enable Bit
1 = WDT is enabled
0 = WDT is disabled
B2
B1
B0
WDTE
r
Reserved
Oscillator Selection Bit
1 = IN oscillator (internal)
FOSC
0 = HS oscillator (crystal/resonator)
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 75
PIC14000
By selecting IN mode OSC1/PBTN becomes a digital
input (with weak internal pull-up resistor) and can be
read via bit MISC<0>. Writes to this location have no
effect. The OSC1/PBTN input is capable of generating
an interrupt to the CPU if enabled (Section 10.6). Also,
the OSC2 pin becomes a digital output for general pur-
pose use and is accessed via MISC<1>. Writes to this bit
directly affect the OSC2 pin. Reading this bit returns the
contents of the output latch. The MISC register format is
shown in Figure 10-2.
10.2
Oscillator Configurations
The PIC14000 can be operated with two different oscil-
lator options. The user can program a configuration
word (CONFIG<0>) to select one of these:
• HS
High Speed Crystal/Ceramic Resonator
(CONFIG<0> =‘0’)
• IN
Internal oscillator (CONFIG<0> =‘1’)
(Default)
10.2.1 INTERNAL OSCILLATOR CIRCUIT
The OSC2 pin can also output the IN oscillator fre-
quency, divided-by-four, by setting INCLKEN
(MISC<2>).
The PIC14000 includes an internal oscillator option
that offers additional cost and board-space savings. No
external components are required. The nominal
operating frequency is 4 MHz. The frequency is mea-
sured and stored into the calibration space in EPROM.
Note: The OSC2 output buffer provides less drive
than standard I/O.
FIGURE 10-2: MISC REGISTER
9Eh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
OSC2
R/W
0
Bit 0
OSC1
R
2
MISC
SMHOG SPGNDB SPGNDA I CSEL
SMBUS INCLKEN
Read/Write
POR value 00h
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
X
Bit
Name
Function
SMHOG enable
2
1 = Stretch I C CLK signal (hold low) when receive data buffer is full (refer to
Section 7.5.4). For pausing I C transfers while preventing interruptions of A/D
2
B7
SMHOG
conversions.
2
0 = Disable I C CLK stretch.
Serial Port Ground Select
B6
B5
B4
SPGNDB
SPGNDA
1 = PORTD<1:0> ground reference is the RD5/AN5 pin.
0 = PORTD<1:0> ground reference is VSS.
Serial Port Ground Select
1 = PORTC<7:6> ground reference is the RA1/AN1 pin.
0 = PORTC<7:6> ground reference is VSS.
2
I C Port select Bit.
1 = PORTD<1:0> are used as the I C clock and data lines.
0 = PORTC<7:6> are used as the I C clock and data lines.
2
2
I CSEL
2
SMBus-Compatibility Select
1 = SMBus compatibility mode is enabled. PORTC<7:6> and PORTD<1:0> have
SMBus-compatible input thresholds.
B3
SMBus
0 = SMBus-compatibility is disabled. PORTC<7:6> and PORTD<1:0> have Schmitt Trig-
ger input thresholds.
Oscillator Output Select (available in IN mode only).
1 = Output IN oscillator signal divided by four on OSC2 pin.
0 = Disconnect IN oscillator signal from OSC2 pin.
B2
B1
B0
INCLKEN
OSC2
OSC2 output port bit (available in IN mode only).
Writes to this location affect the OSC2 pin in IN mode. Reads return the value of the
output latch.
OSC1 input port bit (available in IN mode only).
Reads from this location return the status of the OSC1 pin in IN mode. Writes have no
effect.
OSC1
DS40122B-page 76
Preliminary
1996 Microchip Technology Inc.
PIC14000
10.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATOR
TABLE 10-2: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
In HS mode, a crystal or ceramic resonator is con-
nected to the OSC1 and OSC2 pins to establish oscil-
lation. A parallel cut crystal is required. Use of a series
cut crystal may give a frequency outside of the crystal
manufacturer’s specifications. When in HS mode, the
device can have an external clock source to drive the
OSC1 pin.
Mode
Freq
C1
C2
HS
4 MHz
8 MHz
20 MHz
15 - 33 pF
15 - 47 pF
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 47 pF
Note: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
These values are for design guidance only. Rs may
be required in HS mode to avoid overdriving
crystals with low drive level specification. Since
each crystal has its own characteristics, the user
should consult the crystal manufacturer for
FIGURE 10-3: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OSC CONFIGURATION)
appropriate values of external components.
For VDD > 4.5V, C1 = C2 ≈ 30pf is recommended.
OSC1
To internal
logic
C1
C2
10.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
XTAL
OSC2
SLEEP
SLPCON<3>
RF
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
RS
Note1
PIC14000
See Table 10-1 and Table 10-2 for recommended
values of C1 and C2.
Note 1: A series resistor may be required for AT
strip cut crystals.
FIGURE 10-4: EXTERNAL CLOCK INPUT
OPERATION (HS OSC
Figure 10-5 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to use
the fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a
parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ
potentiometer biases the 74AS04 in the linear region.
This could be used for external oscillator designs.
CONFIGURATION)
OSC1
Clock from
ext. system
PIC14000
Open
OSC2
FIGURE 10-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
TABLE 10-1: CERAMIC RESONATORS
OSCILLATOR CIRCUIT
Mode
HS
Freq
C1
C2
+5V
To Other
Devices
10k
4 MHz
8 MHz
16 MHz
15 - 68 pF
10 - 68 pF
10 - 22 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
74AS04
4.7k
OSC1
74AS04
Note: Recommended values of C1 and C2 are identical to
the ranges tested table.
Higher capacitance increases the stability of
oscillator but also increases the start-up time.
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
10k
XTAL
10k
20pF
20pF
Resonators Used:
4 MHz
8 MHz
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
+/-.5%
+/-.5%
+/-.5%
16 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 77
PIC14000
Figure 10-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 kΩ resistors provide the negative
feedback to bias the inverters in their linear region.
10.3
Reset
The PIC14000 differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (normal operation)
FIGURE 10-6: EXTERNAL SERIES
RESONANT CRYSTAL
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, and on MCLR Reset during SLEEP. They
are not affected by a WDT Wake-up, which is viewed
as the resumption of normal operation. The TO and PD
bits are set or cleared differently in different reset situ-
ations as indicated in Table 10-3. These bits are used
in software to determine the nature of the reset. See
Table 10-5 for a full description of reset states of all reg-
isters.
OSCILLATOR CIRCUIT
To Other
Devices
330kΩ
330kΩ
PIC14000
OSC1
74AS04
74AS04
74AS04
0.1µF
XTAL
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-7.
The devices all have a MCLR noise filter in the MCLR
reset path. The filter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
VDD rise
detect
Power-on Reset
VDD
S
R
OST/PWRT
OST
Chip_Reset
Q
10-bit Ripple counter
OSC1
PWRT
(1)
On-chip
RC OSC
10-bit Ripple counter
Note 1: This is a separate oscillator from the RC
oscillator of the CLKIN pin.
Enable PWRT
Enable OST
DS40122B-page 78
Preliminary
1996 Microchip Technology Inc.
PIC14000
TABLE 10-3: STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
Meaning
0
0
0
1
1
1
1
1
0
X
0
0
1
1
1
X
0
1
0
1
0
Power-On Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT reset during normal operation
WDT time-out wakeup from sleep
MCLR reset during normal operation
MCLR reset during SLEEP or HIBERNATE, or interrupt wake-up from
SLEEP or HIBERNATE.
10.5.2 POWER-UP TIMER (PWRT)
10.4
Low-Voltage Detector
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR. The power-up
timer operates from a local internal oscillator. The chip
is kept in reset as long as PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
configuration bit, PWRTE, can disable (if set, or unpro-
grammed) or enable (if cleared, or programmed) the
power-up timer.
The PIC14000 contains an integrated low-voltage
detector. The supply voltage is divided and compared
to the bandgap reference output. If the supply voltage
(VDD) falls below VTRIP-, then the low-voltage detector
will cause LVD (PCON<0>) to be reset. This bit can be
read by software to determine if a low voltage condition
occurred. This bit must be set by software.
The nominal values of the low-voltage detector trip
points are as follows:
The power-up timer delay will vary from chip to chip
and due to VDD and temperature.
• VTRIP- = 2.55V
• VTRIP+ = 2.60V
10.5.3 OSCILLATOR START-UP TIMER (OST)
• Hysteresis (VTRIP+ – VTRIP-) = 55 mV
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over. This guarantees that the crystal
oscillator or resonator has started and stabilized.
10.5
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST)
10.5.4 IN OSCILLATOR START-UP
10.5.1 POWER-ON RESET (POR)
There is an 8-cycle delay in IN mode to ensure stability
only after a Power-on Reset (POR) or wake-up from
SLEEP.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 79
PIC14000
10.5.5 TIMEOUT SEQUENCE
FIGURE 10-8: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
On power-up the time-out sequence is as follows: First
the PWRT time-out is invoked after POR has expired.
The OST is activated only in HS (crystal oscillator)
mode. The total time-out will vary based on the oscilla-
tor configuration and PWRTE status. For example, in
IN mode, with PWRTE unprogrammed (PWRT dis-
abled), there will be no time-out delay at all.
Figure 13-4 depicts the power-on reset time-out
sequences.
VDD
VDD
R
D
R1
MCLR
C
Table 10-4 shows the reset conditions for some special
registers, while Table 10-5 shows the reset conditions
for all registers.
PIC14000
1. External power-on reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2. R < 40 KΩ is recommended to make sure
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 µA). A larger voltage drop will
degrade VIH level on MCLR pin.
3. R1 = 100 Ω to 1 KΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
ESD or EOS.
TABLE 10-4: RESET CONDITION FOR SPECIAL REGISTERS
PCL
Addr: 02h
STATUS
Addr: 03h
PCON
Addr: 8Eh
Condition
000h
000h
0001 1xxx
0001 1uuu
0001 0uuu
0000 1uuu
uuu0 0uuu
uuu1 0uuu
0--- --0x
u--- --ux
u--- --ux
u--- --ux
u--- --ux
u--- --ux
Power-on Reset
MCLR reset during normal operation
MCLR reset during SLEEP
000h
000h
WDT reset during normal operation
WDT during SLEEP
PC + 1
(1)
PC + 1
Interrupt wake-up from SLEEP
Legend: u = unchanged
x = unknown
- = unimplemented, read as ‘0’
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
DS40122B-page 80
Preliminary
1996 Microchip Technology Inc.
PIC14000
TABLE 10-5: RESET CONDITIONS FOR REGISTERS
MCLR reset during
- normal operation
- SLEEP
WDT time-out during
normal operation
Wake-up from SLEEP
through interrupt
Wake up from SLEEP
through WDT time-out
Register
Address
-
Power-on Reset
xxxx xxxx
-
W
uuuu uuuu
-
uuuu uuuu
-
INDF
00h/80h
01h
TMR0
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
(2)
PCL
02h/82h
03h/83h
04h/84h
05h
PC + 1
(3)
(3)
STATUS
FSR
0001 1xxx
xxxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
---0 0000
0000 000x
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0010
1111 1111
---- 1111
1111 1111
1111 1111
0000 0000
---- --0x
0011 1111
0000 0000
--00 0000
0000 0000
0000 0000
0x00 0x00
0000 000x
0000 0000
000? ?uuu
uuu? ?uuu
uuuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
---0 0000
0000 000u
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
0000 0000
0000 0010
1111 1111
---- 1111
1111 1111
1111 1111
0000 0000
---- --uu
0011 1111
0000 0000
--00 0000
0000 0000
0000 0000
0x00 0x00
0000 000x
0000 0000
uuuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
---u uuuu
PORTA
PORTC
PORTD
PCLATH
INTCON
PIR1
07h
08h
0Ah/8Ah
0Bh/8Bh
0Ch
(1)
uuuu uuuu
(1)
uuuu uuuu
ADTMRL
ADTMRH
I2CBUF
I2CCON
ADCAPL
ADCAPH
ADCON0
OPTION
TRISA
0Eh
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- --uu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0Fh
13h
14h
15h
16h
1Fh
81h
85h
TRISC
87h
TRISD
88h
PIE1
8Ch
PCON
8Eh
SLPCON
I2CADD
I2CSTAT
PREFA
PREFB
CMCON
MISC
8Fh
93h
94h
9Bh
9Ch
9Dh
9Eh
ADCON1
9Fh
Legend: u=unchanged, x=unknown, -= unimplemented, reads as ‘0’, ?= value depends on condition.
Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 10-4 for reset value for specific condition.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 81
PIC14000
The return from interrupt instruction, RETFIE, exits the
interrupt routine as well as sets the GIE bit to re-enable
interrupts.
10.6
Interrupts
The PIC14000 has several sources of interrupt:
• External interrupt from OSC1/PBTN pin
Note 1: The individual interrupt flags will be set by
the specified condition even though the
corresponding interrupt enable bit is
cleared (interrupt disabled) or the GIE bit is
cleared (all interrupts disabled).
2
• I C port interrupt
• PORTC interrupt on change (pins RC<7:4> only)
• Timer0 overflow
• A/D timer overflow
Note 2: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be
re-enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
• A/D converter capture event
• Programmable reference comparator interrupt
This section addresses the external and Timer0
interrupts only. Refer to the appropriate sections for
description of the serial port, programmable reference
and A/D interrupts.
1. An instruction clears the GIE bit while an
interrupt is acknowledged.
INTCON records individual interrupt requests in flag
bits. It also has individual and global enable bits. The
peripheral interrupt flags reside in the PIR1 register.
Peripheral interrupt enable interrupts are contained in
the PIE1 register.
2. The program branches to the interrupt vector
and executes the Interrupt Service Routine.
3. The interrupt service routine completes with the
execution of the RETFIEinstruction. This causes
the GIE bit to be set (enables interrupts), and the
program returns to the instruction after the one
which was meant to disable interrupts.
Global interrupt masking is controlled by GIE
(INTCON<7>). Individual interrupts can be disabled
through their corresponding mask bit in the INTCON
register. GIE is cleared on reset to mask interrupts.
The method to ensure that interrupts are globally
disabled is:
When an interrupt is serviced, the GIE is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with
0004h, the interrupt vector. For external interrupt
1. Ensure that the GIE bit was cleared by the
instruction, as shown in the following code:
LOOP: BCF
INTCON,GIE ; Disable Global Interrupts
2
events, such as the I C interrupt, the interrupt latency
BTFSC INTCON,GIE ; Global Interrupts Disabled?
GOTO LOOP
:
; No, try again
; Yes, continue with program
will be 3 or 4 instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for 1 or 2 cycle instructions. Once in the
interrupt service routine the source(s) of the interrupt
can be determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid infinite interrupt
requests. Individual interrupt flag bits are set
regardless of the status of their corresponding mask bit
or the GIE bit to allow polling.
;
flow
FIGURE 10-9: INTERRUPT LOGIC SCHEMATIC
PBIF
PBIE
ADCIF
ADCIE
Wake-up (If in SLEEP mode)
or terminate long write
T0IF
T0IE
I2CIF
I2CIE
PEIF
PEIE
Interrupt to CPU
GIE
OVFIF
OVFIE
CMIF
CMIE
RCIF
RCIE
DS40122B-page 82
Preliminary
1996 Microchip Technology Inc.
PIC14000
10.6.1 EXTERNAL INTERRUPT
ware in the interrupt service routine before re-enabling
the interrupt. This interrupt can wake up the processor
from SLEEP if PBIE bit is set (interrupt enabled) prior
to going into SLEEP mode. The status of the GIE bit
determines whether or not the processor branches to
the interrupt vector following wake-up. The timing of the
external interrupt is shown in Figure 10-10.
An external interrupt can be generated via the
OSC1/PBTN pin if IN (internal oscillator) mode is
enabled. This interrupt is falling edge triggered. When
a valid edge appears on OSC1/PBTN pin, PBIF
(PIR1<4>) is set. This interrupt can be disabled by
clearing PBIE (PIE1<4>). PBIF must be cleared in soft-
FIGURE 10-10: EXTERNAL (OSC1/PBTN) INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTERNAL
OSC
CLKOUT(3)
PBTN pin
4
1
1
PBIF flag
(PIR<4>)
5
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+1
—
0004h
0005h
Instruction
fetched
Inst (PC+1)
Inst (PC)
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
Instruction
executed
Inst (PC-1)
Dummy Cycle
Dummy Cycle
Notes:
1. PBIF flag is sampled here (every Q1)
2. Interrupt latency = 3-4Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3. Available only in IN oscillator mode on OSC2.
4. For minimum width spec of PBTN pulse, refer to AC specs.
5. PBIF is enabled to be set anytime during the Q4-Q1 cycles.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 83
PIC14000
10.6.2 TIMER0 INTERRUPT
10.6.4 CONTEXT SWITCHING DURING
INTERRUPTS
An overflow (FFh → 00h) in Timer0 will set the T0IF
(INTCON<2>) flag. Setting T0IE (INTCON<5>)
enables the interrupt.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, for example, W register
and Status register. Example 10-1 is an example that
shows saving registers in RAM.
10.6.3 PORTC INTERRUPT ON CHANGE
An input change on PORTC<7:4> sets RCIF
(PIR1<2>). Setting RCIE (PIE1<2>) enables the inter-
rupt. For operation of PORTC, refer to Section 5.2.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RCIF
interrupt flag may not be set.
EXAMPLE 10-1: SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
BCF
BCF
MOVWF
:
W_TEMP
STATUS,W
STATUS,RP1
STATUS,RP0
STATUS_TEMP
;Copy W to TEMP register, could be any bank
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;
;Save status to bank zero STATUS_TEMP register
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS40122B-page 84
Preliminary
1996 Microchip Technology Inc.
PIC14000
The WDT can be permanently disabled by
programming the configuration bit WDTE as a ‘0’. Its
oscillator can be shut down to conserve battery power
10.7
Watchdog Timer (WDT)
The watchdog timer is realized as a free running
on-chip RC oscillator which does not require any
external components. This RC oscillator is separate
from the IN oscillator used to generate the CPU and
A/D clocks. That means that the WDT will run even if
the clock has been stopped, for example, by execution
of a SLEEPinstruction. Refer to Section 10.8.1 for more
information.
by
entering
HIBERNATE
Mode.
Refer
to
Section 10.8.3 for more information on HIBERNATE
mode.
CAUTION: Beware of disabling WDT if software
routines require exiting based on WDT
reset. For example, the MCU will not
exit HIBERNATE mode based on WDT
reset.
During normal operation, a WDT time-out generates a
device RESET. If the device is in SLEEP mode, a WDT
time-out causes the device to wake-up and continue
with normal operation.
A block diagram of the watchdog timer is shown in
Figure 10-11. It should be noted that a RESET
generated by the WDT time-out does not drive MCLR
low.
FIGURE 10-11: WATCHDOG TIMER BLOCK DIAGRAM (WITH TIMER0)
Timer0
Data bus
8
FOSC/4
0
1
PSout
1
0
Sync with
Internal
clocks
TMR0
RC3/T0CKI
pin
PSout
Set T0IF
Interrupt on
Overflow
(2 cycle delay)
T0SE
PSA
T0CS
Prescaler/
Postscaler
Local
8-bit Counter
Oscillator
0
1
8
18 mS
Timer
3
8-to-1 MUX
PS2:PS0
PSA
Enable
1
0
PSA
WDT
Time-out
Watchdog Timer
WDT
Enable Bit
Note: T0CS, T0SE, PSA, PS2:PS0 correspond to (OPTION<5:0>).
HIBERNATE
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 85
PIC14000
10.7.1 WDT PERIOD
10.7.2 WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, VDD and process variations (see DC
specs). If longer time-out periods are desired, a pres-
caler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION registers. Thus, time-out periods up to
2.3 seconds can be realized. The CLRWDTand SLEEP
instructions clear the WDT and the prescaler, if
assigned to the WDT, and prevent it from timing out and
generating a device RESET.
It should also be taken into account that under
worst-case conditions (minimum VDD, maximum
temperature, maximum WDT prescaler) it may take
several seconds before a WDT time-out occurs. Refer
to Section 6.3 for prescaler switching considerations.
10.8
Power Management Options
The PIC14000 has several power management
options to prolong battery lifetime. The SLEEPinstruc-
tion halts the CPU and can turn off the on-chip oscilla-
tors. The CPU can be in SLEEP mode, yet the A/D
converter can continue to run. Several bits are included
in the SLPCON register (8Fh) to control power to ana-
log modules.
The TO bit in the status register will be cleared upon a
watchdog timer time-out. The WDT time-out period (no
prescaler) is measured and stored in calibration space
at location 0FD2h.
TABLE 10-6: SUMMARY OF POWER MANAGEMENT OPTIONS
Function
Summary
CPU Clock
OFF during SLEEP/HIBERNATE mode, ON otherwise
Main Oscillator
ON if NOT in SLEEP mode. In SLEEP mode, controlled by OSCOFF
bit, SLPCON<3>.
Watchdog Timer
Controlled by WDTE, 2007h<2> and HIBEN, SLPCON<7>
Controlled by TEMPOFF, SLPCON<1>
Controlled by REFOFF, SLPCON<5>
Temperature Sensor
Low-voltage Detector
Comparator and
Controlled by CMOFF, SLPCON<2>
Programmable References
A/D Comparator
Controlled by ADOFF, SLPCON<0>
Programmable Current Source
Slope Reference Voltage Divider
Level Shift Networks
Controlled by ADOFF, SLPCON<0> and ADCON1<7:4>
Controlled by ADOFF, SLPCON<0>
Controlled by LSOFF, SLPCON<4>
Bandgap Reference
Controlled by REFOFF, SLPCON<5>
Voltage Regulator Control
Power On Reset
Always ON. Does not consume power if unconnected.
Always ON, except in SLEEP/HIBERNATE mode
Note: Refer to analog specs for individual peripheral operating currents.
DS40122B-page 86
Preliminary
1996 Microchip Technology Inc.
PIC14000
10.8.1 SLEEP MODE
An external reset on MCLR pin causes a device reset.
The other wake-up events are considered
a
The SLEEP mode is entered by executing a SLEEP
instruction.
continuation of program execution. The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
a wake-up).
If SLEEP mode is enabled, the WDT will be cleared but
keep running. The PD bit in the STATUS register is
cleared, the TO bit is set, and on-chip oscillators are
shut off, except the WDT RC oscillator, which continues
to run. The I/O ports maintain the status they had
before the SLEEP command was executed (driving
high, low, or high-impedance).
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set. Wake-up occurs
regardless of the state of bit GIE. If bit GIE is clear, the
device continues execution at the instruction after the
SLEEPinstruction. If bit GIE is set, the device executes
the instruction after the SLEEP instruction and then
branches to the interrupt address (0004h). In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEPinstruction.
It is an option while in SLEEP mode to leave the
on-chip oscillator running. This option allows an A/D
conversion to continue while the CPU is in SLEEP
mode. The CPU clocks are stopped in this condition to
preserve power. The operation of the on-chip oscillator
during
SLEEP
is
controlled
by
OSCOFF
(SLPCON<3>). Clearing this bit to ‘0’ allows the oscil-
lator to continue to run. This bit is only active in SLEEP
mode.
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
For lowest power consumption in this mode, all I/O pins
should be either at VDD or VSS with no external circuitry
drawing current from the I/O pin. I/O pins that are
high-impedance inputs should be pulled high or low
externally to avoid leakage currents caused by floating
inputs. The MCLR pin must be at a logic high level
(VIH). The contribution from any on-chip pull-up
resistors should be considered.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the
corresponding interrupt flag bits set, the
device will immediately wake from SLEEP.
10.8.3 HIBERNATE MODE
10.8.2 WAKE-UP FROM SLEEP
HIBERNATE mode is an extension of SLEEP mode
with the following additions.
The PIC14000 can wake up from SLEEP through one
of the following events:
• WDT is forced off
1. External reset input on MCLR pin
2. Watchdog Timer time-out (if WDT is enabled)
3. Interrupt from OSC1/PBTN pin
4. RC<7:4> port change
• Weak pull-ups on RC<5:0> are disabled
• Some input buffers are gated-off (refer to
Section 5.0)
The HIBERNATE mode is entered by executing a
SLEEPinstruction with HIBEN (SLPCON<7>) bit set.
2
5. I C (serial port) start/stop bit detect interrupt.
6. Wake-up on programmable reference compara-
tor interrupt.
The PIC14000 wakes up from HIBERNATE mode via
all the same mechanisms as SLEEP mode, except for
WDT time-out. HIBERNATE mode allows power con-
sumption to be reduced to a minimum.
7. A/D conversion complete (comparator trip) inter-
rupt.
8. A/D timer overflow interrupt.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 87
PIC14000
FIGURE 10-12: SLPCON REGISTER
8Fh
Bit 7
HIBEN
R/W
0
Bit 6
—
Bit 5
Bit 4
Bit 3
OSCOFF
R/W
Bit 2
Bit 1
Bit 0
SLPCON
Read/Write
POR value 3Fh
REFOFF LSOFF
CMOFF TEMPOFF ADOFF
U
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
0
1
Bit
Name
Function
Hibernate Mode Select
B7
B6
HIBEN
1 = Hibernate mode enable
0 = Normal operating mode
–
Unimplemented. Read as ‘0’
References Power Control (bandgap reference, low voltage detector,
bias generator)
1 = The references are off
B5
B4
B3
REFOFF
0 = The references are on
Level Shift Network Power Control
1 = The level shift network is off. The RA1/AN1, RD5/AN5 inputs can continue to
function as either analog or digital.
0 = The level shift network is on. The signals at the RA1/AN1, RD5/AN5 inputs are
level shifted by approximately 0.5V.
LSOFF
Main Oscillator Power Control
1 = The main oscillator is disabled during SLEEP mode
0 = The main oscillator is running during SLEEP mode for A/D conversions to
continue
OSCOFF
Programmable Reference and Comparator Power Control
1 = The programmable reference and comparator circuits are off
0 = The programmable reference and comparator circuits are on
B2
B1
CMOFF
On-chip Temperature Sensor Power Control
1 = The temperature sensor is off
TEMPOFF
0 = The temperature sensor is on
A/D Module Power Control (comparator, programmable current source,
slope reference voltage divider)
1 = The A/D module power is off
B0
ADOFF
0 = The A/D module power is on
DS40122B-page 88
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 10-13: WAKE-UP FROM SLEEP AND HIBERNATE THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INTERRUPT
Flag (5)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(PC + 1)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(0004h)
Note 1: HS oscillator mode assumed.
2: TOST = 1024 TOSC (drawing not to scale). This delay will be 8 TOSC for IN osc mode.
3: GIE = 1 assumed. In this case after wake up processor jumps to interrupt routine. If GIE = 0, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
5: Refer to Section 10.8 for sources.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device. For complete
details about serial programming, please refer to the
PIC16C6X/7X Programming Specifications (Literature
#DS30228).
10.9
Code Protection
The code in the program memory can be protected by
programming the code protect bits. When code
protected, the contents of the program memory cannot
be read out. In code-protected mode, the configuration
word (2007h) will not be scrambled, allowing reading of
all configuration bits.
A typical in-system serial programming connection is
shown in Figure 10-14.
10.10 In-Circuit Serial Programming
PIC14000 can be serially programmed while in the end
application circuit. This is simply done with two lines for
clock and data, and three other lines for power, ground
and the programming voltage. This allows customers to
manufacture boards with unprogrammed devices, and
then program the microcontroller just before shipping
the product. This allows the most recent firmware or a
custom firmware to be programmed.
FIGURE 10-14: TYPICAL IN-SYSTEM SERIAL
PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC14000
The device is placed into a program/verify mode by
holding the RC6/SCL and RC7/SDA pins low while
raising the MCLR (VPP) pin from VIL to VIH. RC6 then
becomes the programming clock and RC7 becomes
the programmed data. Both RC6 and RC7 are Schmitt
trigger inputs in this mode.
+5V
0V
VDD
VSS
Vpp
MCLR/VPP
RC6
RC7
CLK
Data I/O
VDD
To Normal
Connections
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 89
PIC14000
NOTES:
DS40122B-page 90
Preliminary
1996 Microchip Technology Inc.
PIC14000
The instruction set is highly orthogonal and is grouped
into three basic categories:
11.0 INSTRUCTION SET SUMMARY
The PIC14000’s instruction set is the same as
PIC16CXX. Each instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The instruction set sum-
mary in Table 11-2 lists byte-oriented, bit-oriented, and
literal and control operations. Table 11-1 shows the
opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table 11-2 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure 11-1 shows the three general formats that the
instructions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
All examples use the following format to represent a
hexadecimal number:
TABLE 11-1: OPCODE FIELD
DESCRIPTIONS
0xhh
where h signifies a hexadecimal digit.
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 11-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
8
7
6
0
0
Don't care location (= 0 or 1)
OPCODE
d
f (FILE #)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
b (BIT #)
label Label name
TOS Top of Stack
PC Program Counter
7
6
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
General
PD Power-down bit
dest Destination either the W register or the specified
13
8
7
0
0
register file location
OPCODE
k (literal)
[ ] Options
k = 8-bit immediate value
Contents
( )
→
Assigned to
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
Register bit field
In the set of
< >
k (literal)
User defined term (font is courier)
italics
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 91
PIC14000
TABLE 11-2: PIC14000 INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
0000 0110 0100
1kkk kkkk kkkk
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40122B-page 92
Preliminary
1996 Microchip Technology Inc.
PIC14000
11.1
Instruction Descriptions
ANDLW
And Literal with W
ADDLW
Add Literal and W
Syntax:
[ label ] ANDLW
k
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Operation:
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR, 1
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 93
PIC14000
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
Bit 'b' in register 'f' is cleared.
Description:
1
1
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
After Instruction
Words:
Cycles:
Example
1
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS40122B-page 94
Preliminary
1996 Microchip Technology Inc.
PIC14000
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
0 ≤ f ≤ 127
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Words:
Cycles:
Example
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
1(2)
=
0x5A
HERE
FALSE
TRUE
BTFSC FLAG,1
=
=
0x00
1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRW
None
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → (W)
1 → Z
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
0001
0xxx
xxxx
10
0kkk
kkkk
kkkk
W register is cleared. Zero bit (Z) is
set.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two cycle instruction.
Description:
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
2
Before Instruction
W
=
0x5A
After Instruction
HERE
CALL THERE
W
=
0x00
1
Before Instruction
Z
=
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 95
PIC14000
CLRWDT
Syntax:
Clear Watchdog Timer
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT,
1
1
Before Instruction
CLRWDT
CNT
Z
=
=
0x01
0
Before Instruction
After Instruction
WDT counter
After Instruction
=
=
?
CNT
Z
=
=
0x00
1
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Words:
Cycles:
Example
1
Before Instruction
1(2)
REG1
After Instruction
REG1
=
0x13
HERE
DECFSZ
GOTO
CNT, 1
LOOP
=
=
0x13
0xEC
CONTINUE •
W
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
=
=
DS40122B-page 96
Preliminary
1996 Microchip Technology Inc.
PIC14000
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
INCFSZ
Syntax:
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two cycle instruction.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
two cycle instruction.
Description:
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
GOTO THERE
1(2)
After Instruction
HERE
INCFSZ
GOTO
CNT,
LOOP
1
PC
=
Address THERE
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. k → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
11
1000
kkkk
kkkk
00
1010
dfff
ffff
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
Before Instruction
INCF
CNT, 1
W
=
0x9A
Before Instruction
After Instruction
CNT
Z
=
=
0xFF
0
W
=
0xBF
1
Z
=
After Instruction
CNT
Z
=
=
0x00
1
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 97
PIC14000
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register f is moved to
a destination dependant upon the sta-
tus of d. If d = 0, destination is W reg-
ister. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Description:
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
1
Before Instruction
RESULT =
0x13
0x91
MOVF
FSR, 0
W
=
After Instruction
After Instruction
RESULT =
W
Z
0x13
0x93
1
W = value in FSR register
=
=
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Syntax:
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
11
00xx
kkkk
kkkk
00
0000
1fff
ffff
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Move data from W register to register
'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
MOVLW
0x5A
Before Instruction
OPTION =
After Instruction
0xFF
0x4F
W
=
0x5A
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
DS40122B-page 98
Preliminary
1996 Microchip Technology Inc.
PIC14000
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
Syntax:
Syntax:
[ label ] RETFIE
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Description:
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
k → (W);
TOS → PC
Status Affected: None
00
0000
0110
0010
Encoding:
Status Affected:
Encoding:
None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Description:
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE
;W contains table
;offset value
•
;W now has table value
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
•
•
TABLE
ADDWF PC
;W = offset
;Begin table
;
RETLW k1
RETLW k2
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 99
PIC14000
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
None
Operation:
See description below
C
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
Cycles:
Example
1
2
C
Register f
RETURN
After Interrupt
Words:
Cycles:
Example
1
1
PC
=
TOS
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ] SLEEP
None
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1101
dfff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
Description:
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 10.8 for more details.
Words:
Cycles:
Example
1
1
Words:
1
RLF
REG1,0
Cycles:
Example:
1
Before Instruction
SLEEP
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
DS40122B-page 100
Preliminary
1996 Microchip Technology Inc.
PIC14000
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ]
SUBLW k
[ label ]
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d
[0,1]
k - (W) → (W)
Operation:
(f) - (W) → (dest)
Status
C, DC, Z
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Subtract (2’s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
=
=
=
2
2
?
1; result is zero
C
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is nega-
Example 3:
Before Instruction
tive
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 101
PIC14000
SWAPF
Syntax:
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
11
1010 kkkk kkkk
Status Affected:
Encoding:
None
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Description:
00
1110
dfff
ffff
The upper and lower nibbles of regis-
ter 'f' are exchanged. If 'd' is 0 the
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
Words:
Cycles:
Example
1
1
XORLW
0xAF
Before Instruction
SWAPF REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] TRIS
f
Operands:
Operation:
5 ≤ f ≤ 7
Operands:
d
[0,1]
(W) → TRIS register f;
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
00
Encoding:
0000 0110
0fff
Status Affected:
Encoding:
Z
The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Description:
00
0110
dfff
ffff
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
REG
1
XORWF
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS40122B-page 102
Preliminary
1996 Microchip Technology Inc.
PIC14000
12.3
ICEPIC:Low-cost PIC16CXX In-Circuit
Emulator
12.0 DEVELOPMENT SUPPORT
12.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXX families of 8-bit
OTP microcontrollers.
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
12.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
gram PIC16C5X, PIC16CXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH −MP)
12.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
12.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX and PIC17CXX devices with up
to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 103
PIC14000
include an RS-232 interface, push-button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the PIC-
DEM-3 board is an LCD panel, with 4 commons and 12
segments, that is capable of displaying time, tempera-
ture and day of the week. The PICDEM-3 provides an
additional RS-232 interface and Windows 3.1 software
for showing the demultiplexed LCD signals on a PC. A
simple serial interface allows the user to construct a
hardware demultiplexer for the LCD signals. PICDEM-
3 will be available in the 3rd quarter of 1996.
12.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
12.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
12.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
12.8
PICDEM-3 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features
12.10 Assembler (MPASM)
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
DS40122B-page 104
Preliminary
1996 Microchip Technology Inc.
PIC14000
MPASM allows full symbolic debugging from
the Microchip Universal Emulator System
(PICMASTER).
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
MPASM has the following features to assist in develop-
ing software for specific use applications.
12.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal
source and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
12.15 SEEVAL Evaluation and
Programming System
12.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break,
or in a trace mode.
12.16 TrueGauge Intelligent Battery
Management
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelli-
gent Battery Management IC. System design verifica-
tion can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
12.12 C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a com-
plete ‘C’ compiler and integrated development environ-
ment
for
Microchip’s
PIC16/17
family
of
12.17 KEELOQ Evaluation and
Programming Tools
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
12.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 105
PIC14000
TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 106
PIC14000
13.0 ELECTRICAL CHARACTERISTICS FOR PIC14000
ABSOLUTE MAXIMUM RATINGS †
Ambient temperature under bias.............................................................................................................-55°C to+ 125°C
Storage Temperature ............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................... -0.5V to VDD +0.6V
Voltage on VDD with respect to VSS .............................................................................................................. 0 to +6.0 V
Voltage on MCLR with respect to VSS (Note 2) ...............................................................................................0 to +14 V
Total power Dissipation (Note 1) ..............................................................................................................................1.0 W
Maximum Current out of VSS pin ...........................................................................................................................300mA
Maximum Current into VDD pin ..............................................................................................................................250mA
Input clamp current, IIK (VI <0 or VI> VDD) .........................................................................................................................±20mA
Output clamp current, IOK (VO <0 or VO>VDD)...................................................................................................................±20mA
Maximum Output Current sunk by any I/O pin.........................................................................................................25mA
Maximum Output Current sourced by any I/O pin....................................................................................................25mA
Maximum Current sunk by PORTA, PORTC, and PORTD(combined)..................................................................200mA
Maximum Current sourced by PORTA, PORTC, and PORTE (combined)............................................................200mA
Maximum Current sunk by PORTC and PORTD (combined)................................................................................200mA
Maximum Current sourced by PORTC and PORTD (combined)...........................................................................200mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 107
PIC14000
13.1
DC Characteristics:
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ + 85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD = 2.7V to 6.0V
Characteristic
Sym
Min Typ† Max Units
Conditions
Supply Voltage
VDD
2.7
4.5
—
—
6.0
5.5
V
V
IN or HS at Fosc ≤ 4 MHz
HS at Fosc > 4 MHz
RAM Data Retention
Voltage (Note 1)
VDR
—
1.5
VSS
—
—
—
—
V
Device in SLEEP mode
VDD start voltage to
guarantee Power-On Reset
VPOR
SVDD
—
V
See section on power-on reset for details
VDD rise rate to guarantee
Power-On Reset
0.05*
V/ms See section on power-on reset for details
Operating Current in SLEEP Mode (Note 2)
During A/D conversion:
all analog on and internal
oscillator active
IPD1
IPD1
—
—
TBD 900
TBD 1250
µA VDD = 3.0V
µA VDD = 4.0V
Comparator interrupt enabled:
level-shift, programmable
reference, and comparator active
IPD2
IPD2
—
—
75
95
100
125
µA VDD = 3.0V, CMOFF = 0, LSOFF = 0, REFOFF = 0
µA VDD = 4.0V, CMOFF = 0, LSOFF = 0, REFOFF = 0
All analog off, WDT on (Note 5)
IPD3
IPD3
—
—
7.5
10.5
20
28
µA VDD = 3.0V
µA VDD = 4.0V
All analog off, WDT off
(Hibernate mode) (Note 5)
IPD4
IPD4
—
—
0.9
1.5
12
16
µA VDD = 3.0V
µA VDD = 4.0V
Operating Supply Current (Note 2, 4)
Internal oscillator mode
HS oscillator mode
IDD
—
—
2.2
1.1
TBD
TBD
mA Fosc = 4 MHz, VDD = 5.5V
mA Fosc = 4 MHz, VDD = 3.0V
—
—
—
2.4
1.2
10
TBD
TBD
TBD
mA Fosc = 4 MHz, VDD = 5.5V
mA Fosc = 4 MHz, VDD = 3.0V
mA Fosc = 20 MHz, VDD = 5.5V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1=external square wave, from rail to rail; all I/O pins tristated, pulled to VDD.
MCLR = VDD; WDT enabled/disabled as specified.
3: Measured with all inputs at rails, no DC loads. IPD1 measured with internal oscillator active.
4: IDD values of individual analog module cannot be tested independently but are characterized.
5: Worst-case IPD conditions with all configuration bits unprogrammed. Programming configuration bits
may reduce IPD.
DS40122B-page 108
Preliminary
1996 Microchip Technology Inc.
PIC14000
13.2
DC Characteristics:
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ + 85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in Section 13.1.
Characteristic
Input Low Voltage
I/O ports
Sym Min Typ† Max Units Conditions
VIL
Schmitt Trigger mode
SMBus mode (RC7, RC6, RD0, RD1)
MCLR, OSC1 (in IN mode)
OSC1 (in HS mode)
Input High Voltage
I/O ports
VSS
VSS
Vss
Vss
—
—
—
—
0.2VDD
0.6
V
V
V
V
SMBus bit, MISC<3> = 1
0.2VDD
0.3VDD
VIH
—
Schmitt Trigger mode
0.85 VDD
1.4V
—
—
VDD
VDD
V
V
SMBus mode (RC7, RC6, RD0, RD1)
SMBus bit, MISC<3> = 1
PORTC<5:0> weak pull-up current
Input Leakage Current (Notes 1,2)
I/O ports, CDAC
MCLR
IPURC
IIL
50
200
†400
µA VDD = 5V, VPIN = VSS
±1
±5
±5
µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD
OSC1
µA Vss ≤ VPIN ≤ VDD
Output Low Voltage
I/O ports
VOL
VOH
—
—
—
—
0.6
0.6
V
V
IOL = 8.5mA, VDD-4.5V, -40°C to +85°C
IOL = 1.6mA, VDD-4.5V, -40°C to +85°C
OSC2
Output High Voltage
I/O ports (Note 2)
VDD-0.7
2.4
—
—
—
—
—
—
V
V
V
IOH = -3.0mA, VDD=4.5V, -40°C to +85°C
IOH = -2.0mA, VDD=4.5V, -40°C to +85°C
IOH = -1.3mA, VDD=4.5V, -40°C to +85°C
2
RC6, RC7, RD0, RD1 (except I C mode)
OSC2
VDD-0.7
Capacitive Loading Specs on Output
Pins
OSC2 pin
COSC2
CIO
15
50
pF
pF
pF
All I/O pins except OSC2 (in IN mode)
2
SCL, SDA in I C mode
Cb
400
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
2: Negative current is defined as coming out of the pin.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 109
PIC14000
13.3
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
3. TCC:ST
4. Ts
(I C specifications only)
2
2. TppS
(I C specifications only)
T
F
Frequency
T
Time
Lowercase subscripts (pp) and their meanings:
pp
ck
CLKOUT
SDI
osc
t0
OSC1
T0CKI
di
io
I/O port
MCLR
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
DS40122B-page 110
Preliminary
1996 Microchip Technology Inc.
PIC14000
13.4
Timing Diagrams and Specifications
FIGURE 13-1: EXTERNAL CLOCK TIMING
Q1
1
Q2
Q3
Q4
Q4
Q1
OSC1
3
3
4
4
2
CLKOUT
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
FOSC External CLKIN Frequency (Note 1)
Oscillator Frequency (Note 1)
TOSC External CLKIN Period (Note 1)
Oscillator Period (Note 1)
DC
DC
—
—
4
20
MHz HS osc mode (PIC14000-04)
MHz HS osc mode (PIC14000-20)
4
4
—
—
4
20
MHz HS osc mode (PIC14000-04)
MHz HS osc mode (PIC14000-20)
1
250
50
—
—
—
—
ns
ns
HS osc mode (PIC14000-04)
HS osc mode (PIC14000-20)
250
50
—
—
250
250
ns
ns
HS osc mode (PIC14000-04)
HS osc mode (PIC14000-20)
2
3
TCY
Instruction Cycle Time (Note 1)
200
10
—
—
DC
—
ns
ns
TCY = 4/FOSC
HS oscillator
TOSL, Clock in (OSC1) High or Low Time
TOSH
4
TOSR, Clock in (OSC1) Rise or Fall Time
TOSF
—
—
15
ns
HS oscillator
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an external
clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 111
PIC14000
FIGURE 13-2: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464 Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
DS40122B-page 112
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 13-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
16
19
18
14
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 13-2 for load conditions
TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10
11
12
13
14
15
16
17
18
TosH2ckL
TosH2ckH
TckR
OSC1↑ to CLKOUT↓
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
OSC1↑ to CLKOUT↑
30
CLKOUT rise time
15
TckF
CLKOUT fall time
5
15
0.5TCY+20
—
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
CLKOUT ↓ to Port out valid
Port in valid before CLKOUT ↑
Port in hold after CLKOUT ↑
OSC1↑ (Q1 cycle) to Port out valid
—
—
—
—
—
0.25 TCY+25
0
—
—
80 - 100
—
OSC1↑ (Q2 cycle) to Port input invalid
100
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑ (I/O in setup
0
—
—
ns
time)
20
21
TioR
TioF
Tinp
Port output rise time
Port output fall time
—
—
20
10
10
—
25
25
—
ns
ns
ns
22††
PBTN pin high or low time
IN mode
only
23††
Trbp
RC<7:4> change INT high or low time
20
—
—
ns
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
††
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in IN Mode where CLKOUT output is 4 x TOSC
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 113
PIC14000
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER (HS MODE) AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
I/O Pin
Note: Refer to Figure 13-2 for load conditions
TABLE 13-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL
TWDT
MCLR Pulse Width (low)
100
7*
—
—
ns
VDD = 5V, -40°C to +85°C
VDD = 5V, -40°C to +85°C
Watchdog Timer Timeout Period
(No Prescaler)
18
33*
ms
ss(WDT) Supply Sensitivity
—
—
-12.6
0.5
—
—
%/V TA = 25°C
%/°C VDD = 5V
tc(WDT) Temperature Coefficient
32
TOST
Oscillation Start-up Timer Period
1024 TOSC
8 TOSC
ms
ms
TOSC = OSC1 period
IN osc mode
33
34
TPWRT
TIOZ
Power up Timer Period
28*
72
132*
100
ms
ns
VDD = 5V, -40°C to +85°C
I/O High Impedance from MCLR
Low
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS40122B-page 114
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 13-5: TIMER0 CLOCK TIMINGS
T0CKI
41
40
42
Note: Refer to Figure 13-2 for load conditions.
TABLE 13-4: TIMER0 CLOCK REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ† Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20*
10*
TCY + 40*
N
N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 115
PIC14000
2
FIGURE 13-6: I C BUS START/STOP BITS TIMING
SCL
91
93
92
90
SDA
START
STOP
Condition
Condition
Note: Refer to Figure 13-2 for load conditions
2
TABLE 13-5: I C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90
TSU:STA
START condition
Setup time
100 KHZ mode
400 KHz mode
100 KHz mode
400 KHz mode
100 KHZ mode
400 KHz mode
100 KHz mode
400 KHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated
START condition
ns
ns
ns
ns
91
THD:STA
TSU:STO
THD:STO
START condition
Hold time
4000
600
After this period the first clock
pulse is generated
92
93
STOP condition
Setup time
4700
600
STOP condition
Hold time
4000
600
DS40122B-page 116
Preliminary
1996 Microchip Technology Inc.
PIC14000
2
FIGURE 13-7: I C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
IN
110
109
109
SDA
OUT
Note: Refer to Figure 13-2 for load conditions
TABLE 13-8: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
4.0
0.6
Max Units
Conditions
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
—
—
µs
µs
PIC14000 must operate at a
minimum of 1.5 MHz
PIC14000 must operate at a
minimum of 10 MHz
2
I C Module
1.5 TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC14000 must operate at a
minimum of 10 MHz
2
I C Module
1.5 TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20+0.1 C
C is specified to be from
10-400 pF
b
b
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
300
ns
ns
20+0.1 C
C is specified to be from
b
b
10-400 pF
90
91
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
START condition hold 100 kHz mode
time
—
After this period the first clock
pulse is generated
400 kHz mode
—
106
107
92
Data input hold time
100 kHz mode
400 kHz mode
—
0
0.9
—
Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
STOPcondition setup 100 kHz mode
time
—
400 kHz mode
—
109
110
Output valid from
clock
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
C
Bus capacitive loading
—
400
pF
b
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement
tSU:DAT≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
2
next data bit to the SDA line TR max.+tSU:DAT=1000+250=1250 ns (according to the standard-mode I C
bus specification) before the SCL line is released.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 117
PIC14000
13.5
DC and AC Characteristics Graphs
and Tables for PIC14000
FIGURE 13-10: TYPICAL IPD3 vs VDD AT 25°C
FIGURE 13-9: TYPICAL IPD4 VS VDD AT 25°C
TO BE DETERMINED.
TO BE DETERMINED.
FIGURE 13-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN HS MODE) vs VDD
3.60
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS40122B-page 118
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 13-12: TYPICAL OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, 25°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
100
10
1
100,000,000
1,000,000
10,000
10,000,000
100,000
Frequency (Hz)
FIGURE 13-13: MAXIMUM OPERATING SUPPLY CURRENT VS FREQ (EXT CLOCK, -40° TO +85°C)
TO BE DETERMINED.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 119
PIC14000
FIGURE 13-14: MAXIMUM IPD1 VS FREQ (EXT CLOCK, -40° TO +85°C)
TO BE DETERMINED.
FIGURE 13-15: WATCHDOG TIMER TIME-OUT PERIOD (TWDT) VS.TEMPERATURE (TYPICAL)
VDD=5V
24
22
20
18
16
14
12
10
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90 100
Temperature (°C)
DS40122B-page 120
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 13-16: WDT TIMER TIME-OUT
PERIOD VS VDD
FIGURE 13-18: IOH VS VOH, VDD = 3V*
0
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
-5
-10
-15
-20
-25
10.0
Min, -40˚C
0
0.5
1
1.5
2
2.5
3
5.0
VOH (Volts)
2
3
4
5
6
7
VDD(Volts)
FIGURE 13-19: IOH VS VOH, VDD = 5V*
FIGURE 13-17: TRANSCONDUCTANCE (GM)
OF HS OSCILLATOR VS VDD
0
-5
9000
8000
7000
6000
5000
4000
3000
-10
-15
-20
Min @ 85°C
-25
Typ @ 25°C
-30
-35
-40
Max @ -40°C
2000
1000
0
-45
-50
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOH (Volts)
2
3
4
5
6
7
VDD (Volts)
*NOTE: All pins except RC6, RC7, RD0, RD1,OSC2
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 121
PIC14000
FIGURE 13-20: IOL VS VOL, VDD = 3V*
FIGURE 13-21: IOL VS VOL, VDD = 5V*
35
90
Min @ -40°C
80
Min @ -40°C
30
25
20
70
60
Typ @ 25°C
Typ @ 25°C
50
40
Min @ +85°C
15
10
5
Min @ +85°C
30
20
10
0
0
0
1
0.5
1.5
2
2.5
3
0
0.5
2.5
VOL (Volts)
3.5
4
1.5
2
3
4.5 5
1
VOL (Volts)
*NOTE: All pins except OSC2
DS40122B-page 122
Preliminary
1996 Microchip Technology Inc.
PIC14000
14.0 ANALOG SPECIFICATIONS: PIC14000-04 (COMMERCIAL, INDUSTRIAL)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature:
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic
Sym.
Min.
Typ. Max.
Units
Conditions
Notes
Bandgap Voltage Reference
Output Voltage
vo(vref)
1.14
—
1.19
1
1.24
10
V
Turn-on Settling Time to < 0.1% ton(vref)
ms REFOFF bit in SLPCON
1
1
1
register → 0
Temperature Coefficient
Temperature Coefficient
tc(vref)
tc(vref)
—
—
±50
±20
—
—
ppm/°C Measured from 25°C to
-40°C, +85°C
ppm/°C Measured from 25°C to
0°C, +70°C
Supply Sensitivity
ss(vref)
idd(vref)
idd(vref)
—
—
—
0.04
20
0
—
30
—
%/V From VDDmin to VDDmax
µA REFOFF = 0
1
2
2
Operating Current (on)
Operating Current (off)
µA REFOFF = 1
Programmable Current Source
Output Current
io(cdac)
CDAC pin = 0V
3
18.75
1.25
-0.5
33.75 48.75
µA ADCON1<7:4> = 1111b
(full-scale)
2.25
0
3.25
0.5
µA ADCON1<7:4> = 0001b
(1 LSB)
µA ADCON1<7:4> = 0000b
(zero-scale)
Resolution
res(cdac)
1.25
-1/2
2.25
3.25
+1/2
µA 1 LSB
Relative accuracy (linearity
error)
racc(cdac)
lsb CDAC = 0V
Turn-on Settling Time to < 0.1% ton(cdac)
(reference start-up)
—
—
1
1
10
10
ms Bias generator (reference) turn-on
1
1
time
(REFOFF 1 → 0)
Turn-on Settling Time to < 0.1% ton(cdac)
(reference already on and
stable)
µs REFOFF = 0 (constant),
ADCON1<7:4> 0000b → 1111b
Temperature Coefficient
Supply Sensitivity
tc(cdac)
ss(cdac)
vs(cdac)
—
—
±0.1
0.2
—
—
–
%/°C Measured from 25°C to Tmin, Tmax
%/V From VDDmin to VDDmax
1
1
Output Voltage Sensitivity
-0.1
-0.01
%/V CDAC pin voltage = 0V to VDD -
1.4V
Output Voltage Range
vo(cdac)
idd(cdac)
idd(cdac)
0
—
50
0
VDD-1.4
V
Operating Current (A/D on)
Operating Current (A/D off)
—
—
70
—
µA ADCON1<7:4> = 1111b
µA REFOFF = 1, ADOFF = 1
2
2
Temperature Sensor
Output Voltage
vo(temp)
ss(temp)
KTC
0.92
—
1.05
0.2
1.18
—
V
TA = 25°C
Supply Sensitivity
%/V From VDDmin to VDDmax
1
Temperature Coefficient
3.2
3.65
4.1
mV/°C Measured from 25°C to Tmax.
Includes ± 2°C temperature
calibration tolerance
DS40122B-page 123
Preliminary
1996 Microchip Technology Inc.
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating Temperature:
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic
Sym.
Min.
Typ. Max.
Units
Conditions
Notes
Temperature Sensor (continued)
Output Linearity
lin(temp)
—
—
—
TBD
150
0
—
250
—
1
2
2
Operating Current (sensor on) idd(temp)
Operating Current (sensor off) idd(temp)
µA TEMPOFF = 0
µA TEMPOFF = 1
Slope Reference Voltage Divider
Output Voltage (SREFHI)
Output Voltage (SREFLO)
voh(sref)
vol(sref)
KREF
1.14
0.10
0.09
1.19
0.13
1.24
0.16
V
V
Slope Reference Calibration
Factor
0.126 0.16
TA = 25°C, VDD = 5V
KREF Supply Sensitivity
ss(KREF)
tc(KREF)
idd(sref)
idd(sref)
—
—
—
—
0.02
20
55
0
—
—
85
—
%/V From VDDmin to VDDmax
ppm/°C From Tmin to Tmax
µA ADOFF = 0
1
1
2
2
KREF Temperature Coefficient
Operating Current (A/D on)
Operating Current (A/D off)
µA ADOFF = 1
A/D Comparator
Input Offset Voltage
ioff(adc)
cmr(adc)
gain(adc)
-10
0
2
10
mV Measured over common-mode
range
Input Common Mode Voltage
Range
—
VDD-1.4
V
Differential Voltage Gain
—
—
100
80
—
—
dB
1
1
Common Mode Rejection Ratio cmrr(adc)
dB VDD = 5V, TA = 25°C, over
common-mode range
Power Supply Rejection Ratio
Operating Current (A/D on)
Operating Current (A/D off)
psrr(adc)
idd(adc)
—
—
—
70
40
0
—
65
—
dB TA = 25°C, VDDmin to VDDmax
µA ADOFF = 0
1
2
2
µA ADOFF = 1
Programmable Reference(s)
Upper Range
TA = 25°C
Output Voltage
vo(pref)
0.627
0.418
0.792 0.957
0.528 0.638
V
V
PREFx<7:0> = 7Fh
(127 decimal), max
PREFx<7:0> = 50h
(80 decimal), min
Coarse Resolution
Fine Resolution
resc(pref)
resf(pref)
38.0
4.0
48.0
5.0
58.0
6.0
mV PREFx<2:0> = constant
mV PREFx<7:3> = constant
Middle Range
Output Voltage
TA = 25°C
vo(pref)
0.414
0.380
0.342
0.523 0.632
0.480 0.580
0.432 0.522
V
V
V
PREFx<7:0> = 4F
(79 decimal), max
PREFx<7:0> = 00h
(default), mid-point
PREFx<7:0> = C8h
(200 decimal), min
Coarse Resolution
Fine Resolution
resc(pref)
resf(pref)
3.8
0.38
4.8
0.46
5.8
0.54
mV PREFx<2:0> = constant
mV PREFx<7:3> = constant
1
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 124
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating Temperature:
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic
Sym.
Min.
Typ. Max.
Units
Conditions
Notes
Programmable Reference(s) (continued)
Lower Range
TA = 25°C
Output Voltage
vo(pref)
0.304
0.114
0.384 0.464
0.144 0.174
V
V
PREFx<7:0> = D7h
(215 decimal), max
PREFx<7:0> = F8h
(248 decimal), min
Coarse Resolution
Fine Resolution
resc(pref)
resf(pref)
38.0
4.0
48.0
5.0
58.0
6.0
mV PREFx<2:0> = constant
mV PREFx<7:3> = constant
Relative accuracy (linearity
error)
racc(pref)
−1/2
—
+1/2
lsb lsb = resolution within selected
range
Settling Time to < ±1/2 LSB
ts(pref)
—
1
10
µS PREFx<7:0> transition from 7Fh to
1
FFh
Temperature Coefficient
Supply Sensitivity
tc(pref)
ss(pref)
idd(pref)
idd(pref)
—
—
—
—
0.39
0.2
5
—
—
10
—
%/°C From Tmin to Tmax
%/V From VDDmin to VDDmax
µA CMOFF = 0
1
1
2
2
Operating Current (on)
Operating Current (off)
0
µA CMOFF = 1
Low-Voltage Detector
Detect Voltage
v-(lvd)
v+(lvd)
2.43
2.48
35
2.55
2.60
55
2.67
2.72
75
V
V
Decreasing VDD
Increasing VDD
Release Voltage
Hysteresis
vhys(lvd)
mV Between detect and release trip
points
Operating Current (on)
Operating Current (off)
idd(lvd)
idd(lvd)
—
—
15
0
25
—
µA REFOFF = 0
µA REFOFF = 1
2
2
Internal Oscillator
Frequency Range
Temperature Coefficient
Supply Sensitivity
Jitter
fosc(in)
tc(in)
3.0
—
—
—
—
4.0
-0.04
0.8
5.0
—
—
—
—
MHz
%/°C From Tmin to Tmax
%/V From VDDmin to VDDmax
ppm ±3 sigma from mean
1
1
1
4
ss(in)
jit(in)
100
8
Start-up Time
tsu(in)
Tcycs At Power-On Reset and exit from
SLEEP
Operating Current
(oscillator on)
idd(in)
idd(in)
—
—
300
0
500
—
µA
2
2
Operating Current
(oscillator off)
µA SLEEP mode, OSCOFF = 1
Voltage Regulator Control Output
Regulation Voltage
vo(reg)
5.2
5.9
6.6
V
Measured with Ivreg = 10µA at TA =
25°C
Temperature Coefficient
tc(vreg)
—
1
-0.2
–
—
%/°C From Tmin to Tmax
1
Operating Current
(Recommended)
idd(vreg)
10
µA Determined by external
components
Operating Current
—
0
—
If VREG pin is open
DS40122B-page 125
Preliminary
1996 Microchip Technology Inc.
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating Temperature:
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic
Sym.
Min.
Typ. Max.
Units
Conditions
Notes
Programmable Reference Comparator(s)
Input Offset Voltage ioff(comp)
-10
0
3
10
mV Tested at 0.5V common-mode
voltage
Input Common Mode Voltage cmr(comp)
Range
—
VDD-1.4
V
1
Differential Voltage Gain
gain(comp)
—
—
80
60
—
—
dB
1
1
Common Mode Rejection Ratio cmrr(comp)
dB VDD = 5V, TA = 25°C, over
common-mode range
Power Supply Rejection Ratio psrr(comp)
—
—
—
55
10
0
—
20
—
dB TA = 25°C, VDDmin to VDDmax
µA CMOFF = 0
1
2
2
Operating Current (on)
Operating Current (off)
idd(comp)
idd(comp)
µA CMOFF = 1
Level-Shift Network(s)
Input Current (RA1/RD5 pin)
iin(lvs)
vo(lvs)
-3.4
-4.8
-6.2
µA TA = 25°C, RA1/RD5 = 0V (SUM
pin is open)
Output Voltage
0.37
0.46
0.55
V
TA = 25°C, RA1/RD5 = 0V, (SUM
pin is open)
Zeroing Mismatch Error
zm(lvs)
tc(lvs)
—
—
0.02
0.39
—
—
%
1
1
Output Voltage Temperature
Coefficient
%/°C From Tmin to Tmax
Output Voltage Supply
Sensitivity
ss(lvs)
—
0.2
—
%/V From VDDmin to VDDmax
1
Operating Current (network on) idd(lvs)
Operating Current (network off) idd(lvs)
—
—
5
0
15
—
µA LSOFF = 0
µA LSOFF = 1
2
2
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 126
PIC14000
Standard Operating Conditions (unless otherwise stated)
Operating Temperature:
-40°C ≤ TA ≤ +85°C for industrial
0°C ≤ TA ≤ +70°C for commercial
VDD range: 2.7V (min) to 6.0V (max) unless otherwise stated.
Characteristic
Sym.
Min.
Typ. Max.
Units
Conditions
Notes
Calibration Accuracy
All parameters calibrated at VDD = 3, 5
5V, TA = 25°C unless noted.
Accuracy
Parameter
Sym.
KREF
Resolution Units Typ
Max
—
Conditions
Notes
Slope Reference Ratio
Bandgap Reference Voltage
0.015%
10
—
µV
µV
.02%
.01%
.02%
KBG
—
Temperature Sensor Output
Voltage
VTHERM
20
—
Temperature Sensor Slope
Coefficient
KTC
0.33
µV/°C 6.7%
—
Calibrated at 25°C and Tmax
Internal Oscillator Frequency
FOSC
TWDT
10.0
1
kHz 0.14%
ms 0.5 ms
—
—
Watchdog Timer Time-out
Period
Notes for the analog specifications:
Note 1: This parameter is characterized but not tested.
Note 2: IDD values of individual analog module cannot be tested independently but are characterized.
Note 3: Calibration temp accuracy is ± 1°C typical, ± 2°C max.
Note 4: Guaranteed by design.
Note 5: Refer to AN621 for further information on calibration parameters and accuracy.
Calculations:
Temperature coefficients are calculated as:
tc = (value @TMAX - value @TMIN) / ((TMAX-TMIN) * Average(value @TMAX,value @TMIN))
Temperature coefficient for the internal temperature sensor is calculated as:
tc sensor = (sensor voltage @ TMAX - sensor voltage @ 25°C) / (TMAX - 25°C)
Temperature coefficients for the bandgap reference and programmable current source are calculated as
the larger TC from 25°C to either TMIN or TMAX
Supply sensitivities are calculated as:
ss = (value@VDDMAX - value@VDDMIN)/((VDDMAX - VDDMIN)*
Average(value@VDDMAX, value@VDDMIN))
Programmable current source output sensitivity is calculated as:
vs = (value@(VDD - 1.4V) - value @ 0V)/(VDD - 1.4V) *
Average(value@(VDD - 1.4V), value @ 0V)
DS40122B-page 127
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 14-1: BANDGAP REFERENCE OUTPUT VOLTAGE vs.TEMPERATURE
(TYPICAL DEVICES SHOWN)
1.194
1.192
1.190
1.188
1.186
1.184
1.182
1.180
1.178
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature (°C)
FIGURE 14-2: PROGRAMMABLE CURRENT SOURCE vs.TEMPERATURE
(TYPICAL DEVICES SHOWN)
2.7
2.5
2.3
2.1
1.9
1.7
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature (°C)
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 128
PIC14000
FIGURE 14-3: TEMPERATURE SENSOR OUTPUT VOLTAGE vs.TEMPERATURE
(TYPICAL DEVICES SHOWN)
1.4
1.3
1.2
1.1
1.0
0.9
0.8
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature (°C)
FIGURE 14-4: SLOPE REFERENCE RATIO (KREF) vs. SUPPLY VOLTAGE
(TYPICAL DEVICES SHOWN)
0.1260
0.1258
0.1256
0.1254
0.1252
0.1250
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply Voltage (Volts)
DS40122B-page 129
Preliminary
1996 Microchip Technology Inc.
PIC14000
FIGURE 14-5: SLOPE REFERENCE RATIO (KREF) vs.TEMPERATURE
(TYPICAL DEVICES SHOWN)
0.1260
0.1258
0.1256
0.1254
0.1252
0.1250
0.1248
0.1246
-40
-20
0
20
Temperature (°C)
Fixed Bandgap Reference Voltage
40
60
80
100
FIGURE 14-6: PROGRAMMABLE REFERENCE OUTPUT vs.TEMPERATURE (TYPICAL)
0.7
0.6
0.5
0.4
0.3
-40 -30 -20 -10
0
10 20 30 40
50 60 70 80 90
Temperature (°C)
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 130
PIC14000
FIGURE 14-7: INTERNAL RC OSCILLATOR FREQUENCY vs. SUPPLY VOLTAGE
(TYPICAL DEVICES SHOWN)
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Supply Voltage (Volts)
FIGURE 14-8: INTERNAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
(TYPICAL DEVICES SHOWN)
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90 100
Temperature (°C)
DS40122B-page 131
Preliminary
1996 Microchip Technology Inc.
PIC14000
NOTES:
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 132
PIC14000
APPENDIX A:PIC16/17 MICROCONTROLLERS
A.1
PIC14000 Devices
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 133
PIC14000
A.2
PIC16C5X Family of Devices
DS40122B-page 134
Preliminary
1996 Microchip Technology Inc.
PIC14000
A.3
PIC16CXXX Family of Devices
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 135
PIC14000
A.4
PIC16C6X Family of Devices
DS40122B-page 136
Preliminary
1996 Microchip Technology Inc.
PIC14000
A.5
PIC16C7X Family of Devices
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 137
PIC14000
A.6
PIC16C8X Family of Devices
DS40122B-page 138
Preliminary
1996 Microchip Technology Inc.
PIC14000
A.7
PIC16C9XX Family Of Devices
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 139
PIC14000
A.8
PIC17CXX Family of Devices
DS40122B-page 140
Preliminary
1996 Microchip Technology Inc.
PIC14000
A.9
Pin Compatibility
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE A-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509
8-pin
PIC16C54, PIC16C54A,
PIC16CR54A,
18-pin
20-pin
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622,
PIC16C710, PIC16C71, PIC16C711,
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
PIC16C55,
PIC16C57, PIC16CR57B
28-pin
28-pin
40-pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17C43, PIC17C44
40-pin
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 141
PIC14000
NOTES:
DS40122B-page 142
Preliminary
1996 Microchip Technology Inc.
PIC14000
ADDWF ...................................................................... 93
ANDLW....................................................................... 93
ANDWF ...................................................................... 93
BCF ............................................................................ 94
BSF............................................................................. 94
BTFSC........................................................................ 94
BTFSS........................................................................ 95
CALL........................................................................... 95
CLRF .......................................................................... 95
CLRW......................................................................... 95
CLRWDT .................................................................... 96
COMF......................................................................... 96
DECF.......................................................................... 96
DECFSZ ..................................................................... 96
GOTO......................................................................... 97
INCF ........................................................................... 97
INCFSZ....................................................................... 97
IORLW........................................................................ 97
IORWF........................................................................ 98
MOVF ......................................................................... 98
MOVLW...................................................................... 98
MOVWF...................................................................... 98
NOP............................................................................ 99
OPTION...................................................................... 99
RETFIE....................................................................... 99
RETLW....................................................................... 99
RETURN................................................................... 100
RLF........................................................................... 100
RRF .......................................................................... 100
SLEEP...................................................................... 100
SUBLW..................................................................... 101
SUBWF..................................................................... 101
SWAPF..................................................................... 102
TRIS ......................................................................... 102
XORLW .................................................................... 102
XORWF .................................................................... 102
Section........................................................................ 91
Summary Table .......................................................... 92
INTCON.............................................................................. 19
IORLW Instruction .............................................................. 97
IORWF Instruction.............................................................. 98
INDEX
A
Absolute Maximum Ratings ............................................. 107
ADDLW Instruction ............................................................ 93
ADDWF Instruction ............................................................ 93
ALU...................................................................................... 7
ANDLW Instruction ............................................................ 93
ANDWF Instruction ............................................................ 93
Application Notes
AN607........................................................................ 80
Assembler........................................................................ 104
B
BCF Instruction .................................................................. 94
Block Diagram
PIC16C74 .................................................................... 8
Block Diagrams
On-Chip Reset Circuit ................................................ 79
BSF Instruction .................................................................. 94
BTFSC Instruction.............................................................. 94
BTFSS Instruction.............................................................. 95
C
C Compiler (MP-C) .......................................................... 105
CALL Instruction ................................................................ 95
Carry bit ............................................................................... 7
Clocking Scheme............................................................... 11
CLRF Instruction................................................................ 95
CLRW Instruction............................................................... 95
CLRWDT Instruction.......................................................... 96
Code Examples
Saving STATUS and W registers in RAM.................. 85
COMF Instruction............................................................... 96
Compatibility, upward........................................................... 3
computed goto ................................................................... 23
D
DC Characteristics........................................................... 108
DECF Instruction................................................................ 96
DECFSZ Instruction........................................................... 96
Development Support ...................................................... 103
Development Tools.......................................................... 103
Digit Carry bit ....................................................................... 7
L
E
Loading of PC..................................................................... 23
Electrical Characteristics.................................................. 107
M
F
MCLR ................................................................................. 79
Family of Devices
Memory Organization
PIC14XXX................................................................ 133
PIC16C5X................................................................ 134
PIC16C62X.............................................................. 134
PIC16C6X................................................................ 136
PIC16C7X................................................................ 137
PIC16C8X................................................................ 138
PIC17CXX................................................................ 140
FSR.................................................................................... 24
Fuzzy Logic Dev. System (fuzzyTECH“-MP)........... 103, 105
Data Memory.............................................................. 14
Memory Organization ................................................. 13
Program Memory........................................................ 13
MOVF Instruction................................................................ 98
MOVLW Instruction ............................................................ 98
MOVWF Instruction ............................................................ 98
MPASM Assembler .................................................. 103, 104
MP-C C Compiler ............................................................. 105
MPSIM Software Simulator ...................................... 103, 105
G
N
GOTO Instruction............................................................... 97
NOP Instruction .................................................................. 99
I
O
IDLE_MODE ...................................................................... 54
INCF Instruction................................................................. 97
INCFSZ Instruction ............................................................ 97
Instruction Cycle ................................................................ 11
Instruction Flow/Pipelining ................................................. 11
Instruction Format.............................................................. 91
Instruction Set
Opcode............................................................................... 91
OPTION.............................................................................. 18
OPTION Instruction ............................................................ 99
P
Paging, Program Memory................................................... 23
PCL..................................................................................... 23
PCLATH ............................................................................. 23
ADDLW...................................................................... 93
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 143
PIC14000
PCON................................................................................. 22
PD ...................................................................................... 79
PICDEM-1 Low-Cost PIC16/17 Demo Board........... 103, 104
PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 103, 104
PICDEM-3 Low-Cost PIC16C9XXX Demo Board............ 104
PICMASTER RT In-Circuit Emulator............................. 103
PICSTART Low-Cost Development System ................. 103
PIE1 ................................................................................... 20
Pin Compatible Devices................................................... 141
PIR1 ................................................................................... 21
POR
Oscillator Start-up Timer (OST) ................................. 80
Power-on Reset (POR).............................................. 80
Power-up Timer (PWRT) ........................................... 80
TO .............................................................................. 79
Prescaler ............................................................................ 39
PRO MATE Universal Programmer............................... 103
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow ........................... 11
Example 4-1: Call Of A Subroutine In Page 1
from Page 0............................................... 23
Example 4-2: Indirect Addressing .................................... 24
Example 5-1: Initializing PORTA ..................................... 25
Example 5-2: Initializing PORTC ..................................... 27
Example 5-3: Initializing PORTD ..................................... 35
Example 5-4: Read Modify Write Instructions
On An I/O Port ........................................... 35
Example 6-1: Changing Prescaler (TIMER0→WDT) ....... 40
Example 6-2: Changing Prescaler (WDT→TIMER0) ....... 40
Example 10-1: Saving STATUS and W Registers
in RAM........................................................ 84
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 4-1:
PIC14000 Block Diagram ............................ 8
Clock/Instruction Cycle .............................. 11
PIC14000 Program Memory Map
R
RCV_MODE....................................................................... 54
Read Modify Write.............................................................. 35
Register File....................................................................... 14
Reset.................................................................................. 79
RETFIE Instruction............................................................. 99
RETLW Instruction............................................................. 99
RETURN Instruction......................................................... 100
RLF Instruction................................................................. 100
RRF Instruction ................................................................ 100
and Stack .................................................. 13
Register File Map ...................................... 14
Status Register .......................................... 17
Option Register ......................................... 18
INTCON Register ...................................... 19
PIE1 Register ............................................ 20
PIR1 Register ............................................ 21
PCON Register .......................................... 22
Loading of PC In Different Situations ........ 23
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
S
Saving W register and STATUS in RAM............................ 85
SLEEP................................................................................ 79
SLEEP Instruction............................................................ 100
Software Simulator (MPSIM)............................................ 105
Special FUNCTION Registers............................................ 15
SSP
SSPCON.................................................................... 43
SSPSTAT................................................................... 42
Stack .................................................................................. 23
overflows.................................................................... 23
underflow ................................................................... 23
SUBLW Instruction........................................................... 101
SUBWF Instruction ........................................................... 101
SWAPF Instruction........................................................... 102
Figure 4-10: Indirect/indirect Addressing ....................... 24
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
PORTA Block Diagram .............................. 25
PORTA Data Register ............................... 26
Block Diagram of PORTC<7:6> Pins ........ 27
Block Diagram of PORTC<5:4> Pins ........ 28
Block Diagram of PORTC<3:0> Pins ........ 29
PORTC Data Register ............................... 30
TRISC Register ......................................... 31
Block Diagram of PORTD<7:4> Pins ........ 32
Block Diagram oF PORTD<3:2> Pins ....... 32
Figure 5-10: Block Diagram of PORTD<1:0> Pins ........ 33
Figure 5-11: PORTD Data Register ............................... 33
Figure 5-12: TRISD Register ......................................... 34
Figure 5-13: Successive I/O OperatioN ......................... 36
T
Figure 6-1:
Figure 6-2:
Figure 6-3:
TIMER0 and Watchdog Timer
Block Diagram ........................................... 37
TIMER0 Timing: Internal Clock/
No Prescale ............................................... 38
TIMER0 Timing: Internal Clock/
Timer0
TMR0 with External Clock.......................................... 39
Timer1
Switching Prescaler Assignment................................ 40
Timing Diagrams and Specifications................................ 111
TRIS Instruction ............................................................... 102
Prescale 1:2 .............................................. 38
TIMER0 Interrupt Timing ........................... 38
TIMER0 Timing with External Clock .......... 39
Figure 6-4:
Figure 6-5:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 7-7:
Figure 7-8:
Figure 7-9:
W
2
I C Start And Stop Conditions ................... 41
Watchdog Timer (WDT) ..................................................... 79
2
2
I CSTAT: I C Port Status Register ............ 42
X
2
2
I CCON: I C Port Control Register ........... 43
XMIT_MODE...................................................................... 54
XORLW Instruction .......................................................... 102
XORWF Instruction .......................................................... 102
2
I C 7-bit Address Format ........................... 44
2
I C 10-bit Address Format ......................... 44
2
I C Slave-Receiver Acknowledge ............. 45
Z
2
Sample I C Data Transfer ......................... 45
Zero bit................................................................................. 7
Master - Transmitter Sequence ................. 46
Master - Receiver Sequence ..................... 46
Figure 7-10: Combined Format ...................................... 46
Figure 7-11: Multi-master Arbitration (2 Masters) .......... 47
2
Figure 7-12: I C Clock Synchronization ......................... 47
2
Figure 7-13: I C Block Diagram ..................................... 48
2
Figure 7-14: I C Waveforms For Reception
(7-bit Address) ........................................... 50
DS40122B-page 144
Preliminary
1996 Microchip Technology Inc.
PIC14000
2C
Figure 7-15:
I
Waveforms For Transmission
Figure 13-16: WDT Timer Time-out Period vs VDD .........121
Figure 13-17: Transconductance (gm) of HS Oscillator
vs VDD ......................................................121
Figure 13-18: IOH vs VOH, VDD = 3V* ............................121
Figure 13-19: IOH vs VOH, VDD = 5V* ............................121
Figure 13-20: IOL vs VOL, VDD = 3V* .............................122
Figure 13-21: IOL vs VOL, VDD = 5V* .............................122
Figure 14-1: Bandgap Reference Output
Voltage vs. Temperature
(Typical Devices Shown) ..........................128
Figure 14-2: Programmable Current Source
vs. Temperature
(Typical Devices Shown) ..........................128
Figure 14-3: Temperature Sensor
(7-bit Address) ........................................... 51
Figure 7-16: MISC Register ........................................... 53
Figure 7-17: Operation Of The I C in Idle_Mode,
RCV_Mode or Xmit_Mode ......................... 54
Figure 7-18: SMHOG State Machine ............................. 55
2
Figure 8-1:
Figure 8-2:
Figure 8-3:
Figure 8-4:
Figure 8-5:
Figure 8-6:
Figure 9-1:
Figure 9-2:
Figure 9-3:
A/D Block Diagram .................................... 58
Example A/d Conversion Cycle ................. 59
A/D Capture Timer (Low Byte) ................... 59
A/D Capture Timer (High Byte) .................. 59
A/D Capture Register (Low Byte) .............. 59
A/D Capture Register (High Byte) .............. 59
Level-shift Networks .................................. 66
Slope Reference Divider ............................ 67
Comparator and Programmable
Output Voltage vs. Temperature
Reference Block Diagram .......................... 68
Programmable Reference Transfer
(Typical Devices Shown) ..........................129
Figure 14-4: Slope Reference Ratio
Figure 9-4:
Function ..................................................... 70
Comparator CONTROL Register ............... 71
PREFA Register ........................................ 72
PREFB Register ........................................ 72
Voltage Regulator Circuit ........................... 73
(KREF) vs. Supply Voltage
(Typical Devices Shown) ..........................129
Figure 14-5: Slope Reference Ratio
Figure 9-5:
Figure 9-6:
Figure 9-7:
Figure 9-8:
(KREF) vs. Temperature
(Typical Devices Shown) ..........................130
Figure 14-6: Programmable Reference
Output vs. Temperature (Typical) .............130
Figure 14-7: Internal RC Oscillator Frequency
vs. Supply Voltage
Figure 10-1: Configuration Word..................................... 75
Figure 10-2: MISC Register ........................................... 76
Figure 10-3: Crystal/Ceramic Resonator Operation
(HS OSC Configuration) ............................ 77
Figure 10-4: External Clock Input Operation
(Typical Devices Shown) ..........................131
Figure 14-8: Internal RC Oscillator Frequency
vs. Temperature
(HS OSC Configuration) ............................ 77
Figure 10-5: External Parallel Resonant Crystal
Oscillator Circuit ......................................... 77
(Typical Devices Shown) ..........................131
Figure 10-6: External Series Resonant Crystal
Oscillator Circuit ......................................... 78
LIST OF TABLES
Figure 10-7: Simplified Block Diagram of On-chip
Reset Circuit .............................................. 78
Figure 10-8: External Power-on Reset Circuit
(For Slow VDD Power-up) .......................... 80
Table 3-1:
Table 4-1:
Table 4-2:
Table 4-3:
Pin Descriptions ........................................... 9
Calibration Data Overview.......................... 13
Calibration Constant Addresses................. 14
Special Function Registers for the
Figure 10-9: Interrupt Logic Schematic .......................... 82
Figure 10-10: External (OSC1/PBTN) Interrupt Timing .... 83
Figure 10-11: Watchdog Timer Block Diagram
PIC14000 ................................................... 15
Port RC0 Pin Configuration Summary........ 28
Summary of TIMER0 Registers.................. 40
Registers Associated with Timer0.............. 40
Table 5-1:
Table 6-1:
Table 6-2:
Table 7-1:
Table 7-2:
Table 7-3:
Table 8-1:
Table 8-2:
Table 8-3:
Table 8-4:
Table 8-5:
Table 8-6:
(with Timer0) .............................................. 85
2
Figure 10-12: SLPCON Register ...................................... 88
Figure 10-13: Wake-up From Sleep and Hibernate
Through Interrupt ....................................... 88
Figure 10-14: Typical In-system Serial Programming
Connection ................................................. 90
Figure 11-1: General Format for Instructions ................. 91
Figure 13-1: External Clock Timing .............................. 111
Figure 13-2: Load Conditions ....................................... 112
Figure 13-3: CLKOUT and I/O Timing .......................... 113
Figure 13-4: Reset, Watchdog Timer, Oscillator Start-up
Timer (HS Mode) And Power-up Timer
I C Bus Terminology .................................. 44
Data Transfer Received Byte Actions ........ 49
2
Registers Associated With I C Operation .. 52
A/D Channel Assignment ........................... 60
Programmable Current Source Selection... 61
A/D Control and Status Register 0 ............. 62
A/D Control and Status Register 1 ............. 63
PORTA and PORTD Configuration............ 63
CDAC Capacitor Selection (Examples
for Full Scale of 3.5V and 1.5V) ................. 64
Programmable Reference Coarse
Range Selection......................................... 69
Programmable Reference Fine
Range Selection......................................... 70
Ceramic Resonators................................... 77
Capacitor Selection For Crystal
Oscillator .................................................... 77
Status Bits And Their Significance ............. 79
Reset Condition For Special Registers ...... 80
Reset Conditions For Registers ................. 81
Summary of Power Management
Options....................................................... 86
Opcode Field Descriptions ......................... 91
PIC14000 Instruction Set ........................... 92
Development Tools From Microchip......... 106
External Clock Timing Requirements....... 111
Table 9-1:
Table 9-2:
Timing ...................................................... 114
Figure 13-5: TIMER0 Clock Timings ............................ 115
2
Figure 13-6: I C Bus Start/Stop Bits Timing ................. 116
2
Figure 13-7: I C Bus Data Timing ................................ 117
Table 10-1:
Table 10-2:
Figure 13-9: Typical IPD4 vs VDD ................................ 118
Figure 13-10: Typical IPD3 vs VDD ................................ 118
Figure 13-11: VTH (Input Threshold Voltage)
Table 10-3:
Table 10-4:
Table 10-5:
Table 10-6:
of OSC1 Input (in HS Mode) vs VDD ........ 118
Figure 13-12: Typical IDD vs Freq (Ext clock, 25°C) ...... 119
Figure 13-13: Maximum, IDD vs Freq (Ext clock,
-40° to +85°C) .......................................... 119
Figure 13-14: Maximum IPD1 vs Freq (Ext clock,
-40° to +85°C) .......................................... 120
Table 11-1:
Table 11-2:
Table 12-1:
Table 13-1:
Figure 13-15: PIC14000 Watchdog Timer Time-Out
Period (TWDT) vs. Temperature (Typical) 120
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 145
PIC14000
Table 13-2:
Table 13-3:
CLKOUT and I/O Timing Requirements .. 113
Reset, Watchdog Timer, Oscillator
Start-up Timer And Power-up Timer
Requirements .......................................... 114
Timer0 Clock Requirements .................... 115
Table 13-4:
Table 13-5:
Table 13-8:
Table A-1:
2
I C Bus Start/stop Bits Requirements...... 116
2
I C Bus Data Requirements .................... 117
Pin Compatible Devices ........................... 141
DS40122B-page 146
Preliminary
1996 Microchip Technology Inc.
PIC14000
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel for
you to use in extending your technical staff with micro-
controller and memory experts.
The following connect procedure applies in most loca-
tions.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products pro-
vide project solutions.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
The file transfer site is available by using an FTP ser-
vice to connect to:
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
errata sheets, bug reports, and interim patches for
Microchip systems software products. For each SIG, a
moderator monitors, scans, and approves or disap-
proves files submitted to the SIG. No executable files
are accepted from the user community in general to
limit the spread of computer viruses.
ftp.mchip.com/biz/mchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
960513
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications net-
work.
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER, and are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other coun-
tries. FlexROM, MPLAB, PRO MATE, and fuzzyLAB, are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
Internet:
You can telnet or ftp to the Microchip BBS at the
address:
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trade-
marks of Microsoft Corporation. CompuServe is a regis-
tered trademark of CompuServe Incorporated.
mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense.
The Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
All other trademarks mentioned herein are the property of
their respective companies.
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 147
PIC14000
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS40122B
Device:
PIC14000
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40122B-page 148
Preliminary
1996 Microchip Technology Inc.
PIC14000
PIC14000 PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information (e.g., on pricing or delivery), please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO. -XX X /XX XXX
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
Package:
SP
SO
SS
JW
=
=
=
=
300 mil PDIP
300 mil SOIC (Gull Wing, 300 mil body)
209 mil SSOP
Windowed CERDIP
Temperature
Range:
-
I
=
=
0˚C to +70˚C
-40˚C to +85˚C
Frequency
Range:
04
20
=
=
4 MHz
20 MHz
Device:
PIC14000: VDD range 2.7V to 6.0V
PIC14000T: VDD range 2.7V to 6.0V (Tape & Reel)
1996 Microchip Technology Inc.
Preliminary
DS30444C-page 149
PIC14000
NOTES:
DS30444C-page 150
Preliminary
1996 Microchip Technology Inc.
PIC14000
NOTES:
1996 Microchip Technology Inc.
Preliminary
DS30444C-page 151
WORLDWIDE SALES & SERVICE
AMERICAS
ASIA/PACIFIC
EUROPE
Corporate Office
China
United Kingdom
Microchip Technology Inc.
Microchip Technology
Unit 406 of Shanghai Golden Bridge
Mansion
2077 Yan’an Road West, Hongiao District
Shanghai, Peoples Republic of China
Tel: 86 21 6275 6060 x 406
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 1628 850303 Fax: 44 1628 850178
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
France
Hong Kong
Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Atlanta
Microchip Technology
RM 3801B, Tower Two
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
India
Microchip Technology
No. 6, Legacy, Convent Road
Bangalore 560 025 India
Tel: 91 80 526 3148 Fax: 91 80 558 6606
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Fax: 508 480-8575
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Tel: 39 39 6899939 Fax: 39 39 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
7/30/96
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
Toronto
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905 405-6279
Fax: 905 405-6253
All rights reserved. 1996, Microchip Technology Incorporated, USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre-
sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
DS40122B - page 152
1996 Microchip Technology Inc.
相关型号：
PIC14000-04E/SP
8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28, 0.300 INCH, PLASTIC, DIP-28
MICROCHIP
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