PIC16C432-E/SS [MICROCHIP]
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO20, 0.209 INCH, PLASTIC, SSOP-20;
| 型号： | PIC16C432-E/SS |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO20, 0.209 INCH, PLASTIC, SSOP-20 可编程只读存储器 光电二极管 |
| 文件： | 总106页 (文件大小：1536K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C432
OTP 8-Bit CMOS MCU with LIN Transceiver
Devices included in this Data Sheet:
PIN DIAGRAM
Ceramic DIP, SSOP, PDIP
• PIC16C432
High Performance RISC CPU:
LIN
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR/VPP
VSS
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
VBAT
BACT
• Only 35 instructions to learn
RA0/AN0
• All single cycle instructions (200 ns), except for
program branches which are two-cycle
OSC1/CLKIN
OSC2/CLKOUT
VDD
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
RB0/INT
RB1
RB7
RB6
RB5
RB2
Program
Memory
RAM Data
Memory
Device
RB3
RB4
PIC16C432
2K x 14
128 x 8
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
(via two pins)
• Direct, Indirect and Relative Addressing modes
• Power-on Reset (POR)
Peripheral Features:
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• 12 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
- Two analog comparators
• Programmable code protection
• Power saving SLEEP mode
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
• Selectable oscillator options
• Four user programmable ID locations
- Comparator outputs can be output signals
CMOS Technology:
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Low power, high speed CMOS EPROM/HV-CMOS
technology
• Integrated LIN Transceiver
• Wake-up on bus activity
• Fully static design
• 12V battery operation for Transceiver
• Thermal shutdown for Transceiver
• Ground loss protection
• Operating voltage range
- 4.5V to 5.5V
• Industrial and extended temperature range
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 1
PIC16C432
Table of Contents
1.0 General Description...................................................................................................................................................................... 3
2.0 PIC16C432 Device Varieties........................................................................................................................................................ 5
3.0 Memory Organization................................................................................................................................................................... 7
4.0 I/O Ports ..................................................................................................................................................................................... 17
5.0 LIN Transceiver.......................................................................................................................................................................... 23
6.0 Timer0 Module ........................................................................................................................................................................... 27
7.0 Comparator Module.................................................................................................................................................................... 33
8.0 Voltage Reference Module......................................................................................................................................................... 41
9.0 Special Features of the CPU...................................................................................................................................................... 43
10.0 Instruction Set Summary............................................................................................................................................................ 59
11.0 Development Support................................................................................................................................................................. 73
12.0 Electrical Specifications.............................................................................................................................................................. 79
13.0 DC and AC Characteristics Graphs and Tables......................................................................................................................... 91
14.0 Packaging Information................................................................................................................................................................ 93
Appendix A: Code for LIN Communication ...................................................................................................................................... 97
Index: .................................................................................................................................................................................................. 99
On-Line Support................................................................................................................................................................................. 101
Systems Information and Upgrade Hot Line ...................................................................................................................................... 101
Reader Response .............................................................................................................................................................................. 102
Product Identification System............................................................................................................................................................. 103
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS41140C-page 2
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
1.0
GENERAL DESCRIPTION
The PIC16C432 is a 20-pin EPROM-based member of
the versatile PIC® family of low cost, high performance,
CMOS, fully-static, 8-bit microcontrollers with an inte-
grated LIN transceiver.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
The LIN physical layer is implemented in hardware with
a voltage range from 0V to 18V, with a 40V transient
capability. The LIN protocol is to be implemented in
firmware, which enables flexibility with future revisions
of the LIN protocol.
A simplified block diagram of the PIC16C432 is shown
in Figure 4-1.
The PIC16C432 series fits perfectly in automotive and
industrial applications, which require LIN as a commu-
nication platform. The EPROM technology makes
customization of application programs (detection
levels, pulse generation, timers, etc.) extremely fast
and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high per-
formance, ease of use and I/O flexibility make the
PIC16C432 very versatile.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16C432 device has enhanced
core features, eight-level deep stack, and multiple
internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with separate 8-bit
wide data. The two stage instruction pipeline allows all
instructions to execute in a single cycle, except for pro-
gram branches (which require two cycles). A total of 35
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
1.1
Development Support
The PIC16C432 family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer. A “C” compiler is also
available.
PIC16C432 microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C432 has 12 I/O pins and an 8-bit timer/
counter with an 8-bit programmable prescaler. In addi-
tion, the PIC16C432 adds two analog comparators with
a programmable on-chip voltage reference module.
The comparator module is ideally suited for applica-
tions requiring a low cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc.).
PIC16C432 devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are four oscillator options, of which the
single pin RC oscillator provides a low cost solution, the
LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 3
PIC16C432
NOTES:
DS41140C-page 4
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
2.3
Quick-Turn-Programming (QTP)
Devices
2.0
PIC16C432 DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C432 Product
Identification System section at the end of this data
sheet.
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code pat-
terns have stabilized. The devices are identical to the
OTP devices, but with all EPROM locations and config-
uration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.1
UV Erasable Devices
The UV erasable version, offered in the CERDIP pack-
age is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PRO MATE® programmers support pro-
gramming of the PIC16C432.
2.4
SerializedQuick-Turn-Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 5
PIC16C432
NOTES:
DS41140C-page 6
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
3.2
Data Memory Organization
3.0
3.1
MEMORY ORGANIZATION
Program Memory Organization
The data memory (Figure 3-2) is partitioned into two
Banks, which contain the General Purpose Registers
and the Special Function Registers. Bank 0 is selected
when the RP0 bit is cleared. Bank 1 is selected when
the RP0 bit (STATUS <5>) is set. The Special Function
Registers are located in the first 32 locations of each
Bank. Register locations 20-7Fh (Bank 0) and A0-BFh
(Bank 1) are General Purpose Registers implemented
as static RAM. Some special purpose registers are
mapped in Bank 1. In the microcontroller, address
space F0h-FFh (Bank 1) is mapped to 70-7Fh (Bank 0)
as common RAM.
The PIC16C432 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. Only
the first 2K x 14 (0000h - 07FFh) are implemented for
the PIC16C432. Accessing a location above these
boundaries will cause a wrap-around within the first 2K
x 14 space. The RESET Vector is at 0000h and the
Interrupt Vector is at 0004h (Figure 3-1).
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C432
3.2.1
GENERAL PURPOSE REGISTER
FILE
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
The register file is organized as 128 x 8 in the
PIC16C432. Each is accessed either directly or indi-
rectly through the File Select Register FSR
(Section 3.4).
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
07FFh
0800h
1FFFh
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 7
PIC16C432
FIGURE 3-2:
DATA MEMORY MAP FOR
3.2.2
SPECIAL FUNCTION REGISTERS
THE PIC16C432
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 3-1). These
registers are static RAM.
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
The special registers can be classified into two sets
(core and peripheral). The Special Function Registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
LININTF
CMCON
VRCON
A0h
General
Purpose
Register
General
Purpose
Register
BFh
C0h
F0h
FFh
Accesses
70h-7Fh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations,read
as '0'.
Note 1: Not a physical register.
DS41140C-page 8
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
TABLE 3-1:
Address
SPECIAL REGISTERS FOR THE PIC16C432
Value on all
Value on
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
POR Reset
RESETS(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
16
01h
02h
TMR0
PCL
Timer0 Module’s Register
xxxx xxxx
0000 0000
27
15
Program Counter's (PC) Least Significant Byte
03h
STATUS
FSR
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---x 0000
xxxx xxxx
—
10
16
17
20
—
—
—
15
12
13
—
33
04h
Indirect data memory address pointer
05h
PORTA
PORTB
—
—
—
—
RA4
RB4
RA3
RB3
RA2
RB2
LINRX
RB1
RA0
RB0
06h
RB7
RB6
RB5
07h
Unimplemented
Unimplemented
Unimplemented
08h
—
—
09h
—
—
0Ah
PCLATH
INTCON
PIR1
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
0Bh
PEIE
CMIF
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
0Ch
0Dh-1Eh
1Fh
—
Unimplemented
C2OUT C1OUT
CMCON
—
—
CIS
CM2
CM1
CM0
00-- 0000
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
16
81h
82h
OPTION_REG
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
11
15
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
STATUS
FSR
PD
Z
DC
C
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
10
16
17
20
—
—
—
15
12
13
—
TRISA
TRISB
—
—
—
—
TRISA4 TRISA3
TRISA2 TLINRX(3) TRISA0
TRISB2 TRISB1 TRISB0
TRISB7
TRISB6 TRISB5 TRISB4 TRISB3
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
PCLATH
INTCON
PIE1
—
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
PEIE
CMIE
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
Unimplemented
8Eh
PCON
—
—
—
—
—
—
—
POR
BOD
---- --0x
—
14
—
23
41
8Fh-9Eh
90h
Unimplemented
LININTF
VRCON
—
—
—
—
—
—
LINTX
VR2
—
LINVDD
VR0
---- -1-1
000- 0000
9Fh
VREN
VROE
VRR
VR3
VR1
Legend:
— = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented
Note 1: Other (non power-up) RESETS include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
2: IRP & RPI bits are reserved; always maintain these bits clear.
3: TLINRX must set to ‘1’ at all times.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 9
PIC16C432
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
3.2.2.1
STATUS Register
The STATUS register, shown in Register 3-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16C432 and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu(where u= unchanged).
REGISTER 3-1:
STATUS REGISTER (ADDRESS 03h OR 83h)
Reserved Reserved
IRP RP1
bit7
R/W-0
R-1
R-1
R/W-x
Z
R/W-x
DC
R/W-x
C
RP0
TO
PD
bit0
bit 7
IRP:
The IRP bit is reserved on the PIC16C432, always maintain this bit clear
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4
bit 3
bit 2
bit 1
TO: Timeout bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT timeout occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions) (for borrow the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of
the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or
low order bit of the source register.
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS41140C-page 10
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
3.2.2.2
OPTION Register
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 3-2:
OPTION REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit7
bit0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 11
PIC16C432
3.2.2.3
INTCON Register
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources, except the comparator module.
See Section 3.2.2.4 and Section 3.2.2.5 for
description of the comparator enable and flag bits.
a
REGISTER 3-3:
INTCON REGISTER (ADDRESS 0Bh OR 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit7
bit0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= When at least one of the RB<7:4> pins changed state (must be cleared in software)
0= None of the RB<7:4> pins have changed state
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS41140C-page 12
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
3.2.2.4
PIE1 Register
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 3-4:
PIE1 REGISTER (ADDRESS 8CH)
U-0
—
R/W-0
CMIE
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit7
bit0
bit 7
bit 6
Unimplemented: Read as '0'
CMIE: Comparator Interrupt Flag bit
1= Enables the Comparator interrupt
0= Disables the Comparator interrupt
bit 5-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
3.2.2.5
PIR1 Register
This register contains the individual flag bit for the com-
parator interrupt.
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 3-5:
PIR1 REGISTER (ADDRESS 0Ch)
U-0
—
R/W-0
CMIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit7
bit0
bit 7
bit 6
Unimplemented: Read as '0'
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed
0= Comparator input has not changed
bit 5-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 13
PIC16C432
3.2.2.6
PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.
Note: BOD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOD is
cleared, indicating
a
brown-out has
occurred. The BOD status bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BODEN
bit
in
the
configuration word).
REGISTER 3-6:
PCON REGISTER (ADDRESS 8Eh))
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-0
BOD
bit7
bit0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
DS41140C-page 14
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
3.3.2
STACK
3.3
PCL and PCLATH
The PIC16C432 family has an 8 level deep x 13-bit
wide hardware stack (Figure 3-1 and Figure 3-1). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALLinstruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLWor a RET-
FIEinstruction execution. PCLATH is not affected by a
PUSH or POP operation.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 3-3 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> PCH). The lower exam-
ple in the figure shows how the PC is loaded during a
CALLor GOTOinstruction (PCLATH<4:3> PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).
FIGURE 3-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
12
8
7
0
Instruction with
PCL as
Destination
PC
8
2: There are no instruction/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
PCLATH<4:0>
PCLATH
5
ALU result
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
3.3.1
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
Application Note, “Implementing
a Table Read”
(AN556).
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 15
PIC16C432
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 3-1.
3.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 3-1:
INDIRECT ADDRESSING
movlw 0x20
movwf FSR
clrf INDF
incf FSR
;initialize pointer
;to RAM
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 3-4. However, IRP is not used in the
PIC16C432.
NEXT
;clear INDF register
;inc pointer
btfss FSR,4 ;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
FIGURE 3-4:
DIRECT/INDIRECT ADDRESSING PIC16C432
Direct Addressing
Indirect Addressing
(1)
(1)
RP1 RP0
from opcode
7
6
0
0
IRP
FSR Register
bank select
180h
location select
bank select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
For memory map detail see Figure 3-2 and Figure 3-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
DS41140C-page 16
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
4.0
I/O PORTS
Note: On RESET, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to
ground, to reduce excess current con-
sumption.
The PIC16C432 parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
4.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output driv-
ers. All pins have data direction bits (TRIS registers),
which can configure these pins as input or output.
The RA2 pin will also function as the output for the volt-
age reference. When in this mode, the VREF pin is a very
high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
A '1' in the TRISA register puts the corresponding out-
put driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
EXAMPLE 4-1:
INITIALIZING PORTA
CLRF
PORTA
;Initialize PORTA by setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
MOVLW 0X07
MOVWF CMCON
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control Register) register and the
VRCON (Voltage Reference Control Register) register.
When selected as a comparator input, these pins will
read as '0's.
BSF
STATUS,
RP0
;Select Bank1
MOVLW 0x1F
MOVWF TRISA
;Value used to initialize
;data direction
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as '0'.
FIGURE 4-1:
BLOCK DIAGRAM OF RA0
PINS
Note 1: BACT pin is an output and must be left
Data
open if unused.
Bus
D
Q
Q
VDD VDD
P
WR
PORTA
CK
Data Latch
D
Q
I/O Pin
N
WR
TRISA
CK
Q
TRIS Latch
Vss
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 17
PIC16C432
FIGURE 4-2:
BLOCK DIAGRAM OF RA2
PIN
Data
Bus
D
Q
Q
VDD
P
VDD
WR
PORTA
CK
Data Latch
D
Q
RA2 Pin
N
WR
TRISA
Q
CK
TRIS Latch
Vss
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
VROE
VREF
FIGURE 4-3:
BLOCK DIAGRAM OF RA3 PIN
Data
Comparator Mode = 110
Comparator Output
Bus
D
Q
VDD
P
VDD
WR
PORTA
Q
CK
Data Latch
D
Q
RA3 Pin
N
WR
TRISA
CK
Q
Vss
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
DS41140C-page 18
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
FIGURE 4-4:
BLOCK DIAGRAM OF RA4 PIN
Data
Bus
Comparator Mode = 110
Comparator Output
D
Q
Q
WR
PORTA
CK
Data Latch
D
Q
RA4 Pin
N
WR
TRISA
CK
Q
Vss
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
TABLE 4-1:
Name
PORTA FUNCTIONS
Buffer
Bit #
Type
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Input/output or comparator input.
LIN receive pin.
LINRX
RA2/AN2/VREF
RA3/AN3
Input/output or comparator input or VREF output.
Input/output or comparator input/output.
RA4/T0CKI
Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 4-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
All Other
RESETS
Value on:
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
1Fh
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA4
RA3
RA2
LINRX
RA0
---x 0000 ---u 0000
(2)
TRISA4 TRISA3 TRISA2 TLINRX
TRISA0 ---1 1111 ---1 1111
CMCON C2OUT C1OUT
VRCON VREN VROE
—
—
—
CIS
CM2
VR2
CM1
VR1
CM0
VR0
00-- 0000 00-- 0000
000- 0000 000- 0000
VRR
VR3
Legend: — = Unimplemented locations, read as ‘0’, x= unknown, u= unchanged
Note 1: Shaded bits are not used by PORTA.
2: TLINRX must be set to ‘1’ at all times.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 19
PIC16C432
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
4.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a High Impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
This interrupt-on-mismatch feature, together with
software configurable pull-ups on these four pins, allow
easy interface to a key pad and make it possible for
wake-up on key depression. (See AN552, “Implement-
ing Wake-up on Key Strokes”.)
Each of the PORTB pins has a weak internal pull-up
(200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins of RB<7:4> are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 4-6:
BLOCK DIAGRAM OF
RB<3:0> PINS
VDD
RBPU(1)
FIGURE 4-5:
BLOCK DIAGRAM OF
RB<7:4> PINS
P
Weak
Pull-up
I/O pin
Data Latch
Data Bus
VDD
D
Q
RBPU(1)
P
WR PORTB
CK
TRIS Latch
Weak
I/O pin
Data Latch
Pull-up
Data Bus
D
Q
D
Q
TTL
WR PORTB
WR TRISB(1)
Input
Buffer
CK
TRIS Latch
CK
D
Q
WR TRISB(1)
TTL
Input
Buffer
CK
RD TRISB
ST
Buffer
Q
D
EN
RD PORTB
RD TRISB
Latch
Q
Q
D
RB0/INT
EN
RD PORTB
ST
RD Port
Set RBIF
Buffer
Note 1: TRISB = 1 enables weak pull-up if RBPU = 0
From other
(OPTION<7>).
D
RB<7:4> pins
EN
RD Port
RB<7:6> in Serial Programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = 0
(OPTION<7>).
DS41140C-page 20
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
TABLE 4-3:
Name
PORTB FUNCTIONS
Bit #
Buffer Type
Function
RB0/INT
bit0
TTL/ST(1)
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock pin.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 4-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
All Other
RESETS
Value on:
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h
OPTION
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Legend: u= unchanged, x= unknown
Note 1: Shaded bits are not used by PORTB.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 21
PIC16C432
EXAMPLE 4-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
4.3
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
4.3.1
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit0 is switched into Output mode later on,
the content of the data latch may now be unknown.
; Initial PORT settings:
PORTB<7:4> Inputs
PORTB<3:0> Outputs
; PORTB<7:6> have external pull-up and are not connected
; to other circuitry
;
;
;
PORT latch
PORT pins
------------------ ----------------
BCF PORTB, 7
BCF PORTB, 6
; 01pp pppp
11pp pppp
11pp pppp
;10pp pppp
;
BSF STATUS,
RP0
BCF TRISB, 7
BCF TRISB, 6
; 10pp pppp
; 10pp pppp
11pp pppp
10pp pppp
;
; NOTE: that the user may have expected the pin values to
; be 00pp pppp. The 2nd BCF caused RB7 to be latched as
; the pin value (High).
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port
pins is read, the desired operation is done to this value,
and this value is then written to the port latch.
4.3.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
Example 4-2 shows the effect of two sequential read-
modify-write instructions (i.e., BCF, BSF, etc.) on an
I/O port.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 4-
7). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should allow the pin volt-
age to stabilize (load dependent) before the next
instruction causes that file to be read into the CPU.
Otherwise, the previous state of that pin may be read
into the CPU, rather than the new state. When in doubt,
it is better to separate these instructions with a NOP,or
another instruction not accessing this I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time, in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
FIGURE 4-7:
SUCCESSIVE I/O OPERATION
Note:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
This example shows write to PORTB
followed by a read from PORTB.
PC
PC + 1
PC + 2
PC + 3
PC
Instruction
MOVWF PORTB
MOVF PORTB, W
NOP
NOP
Note that:
Fetched
Write to
PORTB
Read PORTB
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
RB<7:0>
Port pin
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
sampled here
T
PD
Execute
Execute
Execute
NOP
M
O
V
WF
MOVF
PORTB
PORTB, W
DS41140C-page 22
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
5.4
Thermal Shutdown
5.0
LIN TRANSCEIVER
In thermal shutdown, the LIN output is disabled instan-
taneously. The output transistor is turned off, regard-
less of the input level at pin LINTX bit and only a limited
current can flow into the receiver connected to the LIN
pin.
The PIC16C432 has an integrated LIN transceiver
which allows the microcontroller to communicate via
LIN. The LIN protocol is handled by the microcontroller.
The conversion from 5V signal to LIN signals is han-
dled by the transceiver.
5.5
Wake-up From SLEEP Upon Bus
Activity
5.1
The LIN Protocol
The LIN protocol is not described within this document.
For further information regarding the LIN protocol,
please refer to www.lin-subbus.org.
The PIC16C432 can wake-up from SLEEP upon bus
activity in two ways:
1. With the use of the comparators.
5.2
LIN Interfacing
2. Connecting BACT to one of PORTB<0,4:7>
pins.
The LIN protocol is implemented and programmed by
the user, using the LINTX and LINRX bits, which are
used to interface to the transceiver. The LIN firmware
transmits by toggling the LINTX bit in the LININTF reg-
ister and is read by reading the LINRX bit in the PORTA
register. All aspects of the protocol are handled by soft-
ware (i.e., bit-banged), where the transceiver is used
as the physical interface to the LIN network.
In case the comparators are used to wake-up the
device upon bus activity, a reference to the LIN signal
has to be supplied. This is usually VDD/2. The refer-
ence can either be an external reference or the internal
voltage reference. Once the device is in SLEEP mode,
the comparator interrupt will wake-up the device. On
RESET, LINRX is configured as an analog comparator
input (Section 8.1 of Data Sheet) which can be used to
generate an interrupt to wake-up the device from
SLEEP on bus activity. The LINRX bit will not receive
data from the bus configured as an analog input, there-
fore, after wake-up from comparator interrupt or
RESET, LINRX must be configured as a digital input to
read the bus.
For LIN software implementation, please refer to Micro-
chip's website (www.microchip.com).
Note: The LINTX is bit 2 of the LININTF register.
If the LINTX bit is left cleared, no other nodes on the
network will be able to communicate on the LIN for this
is the dominate state for the protocol. The transceiver
can be powered down by clearing the LINVDD bit in the
LININTF register. This can be useful to reduce current
consumption but does not allow the microcontroller to
wake-up on LIN activity because the transceiver will be
disabled. It is recommended that the firmware verify
each bit transmitted, by comparing the LINTX and
LINRX bits, to ensure no bus contention or hardware
failure has occurred. The LINTX bit has no associated
TRIS bit and is always an output. The LINRX bit has an
associated TRIS bit, TLINRX, in the TRISA register.
The BACT output is a CMOS-levels representation of
the LIN pin. This signal can be routed to one of the
PORTB<0,4:7> pins. The RB0/INT external interrupt or
PORTB<4:7> interrupt-on-change wakes up the device
from SLEEP. Any one of the five PORTB pins can be
used for wake-up where PORTB<0> offers multiple
configuration options (Section 10.5.1 of Data Sheet)
and PORTB<4:7> are interrupt-on-change (Section
10.5.3 of Data Sheet).
Note: BACT pin is an output and must be left
Note: TLINRX, bit 1 of TRISA register, must be
open if unused.
set to '1' at all times.
5.3
LIN Hardware Interface
Figure 6-1 shows how to implement a hardware LIN
interface in a master configuration and Figure 6-2 in a
slave configuration using the PIC16C432. Figure 6-3
shows how to implement the hardware for a master
configuration using BACT pin to generate a wake-up
interrupt using RB0. The transceiver has an internal
series resistor and diode, as defined in the LIN 1.2
specification, connecting VBAT and LIN.
Note: No resistor is required between VBAT pin
and 12V supply and for slave configura-
tion, no resistor is required between VBAT
and LIN.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 23
PIC16C432
FIGURE 5-1:
TYPICAL LIN BUS MASTER APPLICATION
+5V
+12V
VDD
VBAT
BACT
Note 2
1 k
LIN
To LIN Bus
Note 1
VSS
Note 1: Refer to LIN Bus Specification.
2: BACT pin should be left open if not used.
FIGURE 5-2:
TYPICAL LIN BUS SLAVE APPLICATION
+5V
+12V
VDD
VBAT
Note 2
BACT
LIN
To LIN Bus
Note 1
VSS
Note 1: May not be required.
2: BACT pin should be left open if not used.
DS41140C-page 24
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
FIGURE 5-3:
LIN BUS APPLICATION USING WAKE-UP INTERRUPT
+5V
+12V
VDD
VBAT
Note 1
BACT
RB0
1k
LIN
To LIN Bus
Note 2
VSS
Note 1: May not be required.
2: For master configuration only.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 25
PIC16C432
REGISTER 5-1:
LININTF REGISTER (ADDRESS: 90h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
LINTX
U-0
—
R/W-1
LINVDD
bit 0
bit 7
bit 7-3
bit 2
Unimplemented: Read as '0'
LINTX: LIN Bus Transmit bit
1= LIN Bus line is high
0= LIN Bus line is low
bit 1
bit 0
Unimplemented: Read as '0'
LINVDD: LIN Bus Transceiver VDD Supply bit
1= VDD is supplied to the LIN Bus transceiver via microcontroller
0= VDD is not supplied to the LIN Bus transceiver
Note 1: Transceiver VDD is same as microcontroller VDD.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
TABLE 5-1:
SUMMARY OF REGISTERS ASSOCIATED WITH LIN TRANSCEIVER
Value on
All Other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
90h
PORTA
TRISA
—
—
—
—
—
—
—
—
—
RA4
RA3
RA2
LINRX
RA0
---x 0000 ---u 0000
(2)
TRISA4 TRISA3 TRISA2 TLINRX
LINTX
TRISA0 ---1 1111 ---1 1111
LINVDD ---- -1-1 ---- -1-1
LININTF
—
—
—
Legend: x = unknown, u = unchanged, — = Unimplemented locations read as ‘0’.
Note 1: Shaded bits are not used by LIN transceiver
2: TLINRX must be set to ‘1’ at all times.
DS41140C-page 26
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 6-1 is a simplified block diagram of the Timer0
module.
6.1
Timer0 Interrupt
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 6-2 and Figure 6-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine, before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP, since the timer is
shut-off during SLEEP. See Figure 6-4 for Timer0 inter-
rupt timing.
Counter mode is selected by setting the T0CS bit. In
this mode, Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 6-1:
TIMER0 BLOCK DIAGRAM
Data Bus
RA4/T0CKI
pin
FOSC/4
0
1
PSOUT
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
PSOUT
(2 TCY delay)
T0SE
Set Flag bit T0IF
on Overflow
PSA
PS<2:0>
T0CS
Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6).
FIGURE 6-2:
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVF TMR0,W
MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0 Read TMR0
Read TMR0
reads NT0 reads NT0 + 1 reads NT0 + 2
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 27
PIC16C432
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVF TMR0,W
MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 6-4:
TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
(3)
CLKOUT
TMR0 Timer
FEh
1
FFh
1
00h
01h
02h
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
Interrupt Latency Time
PC +1
INSTRUCTION FLOW
PC
PC
PC +1
0004h
0005h
Instruction
Fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Instruction
Executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (0004h)
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3Tcy, where Tcy = instruction cycle time.
3: CLKOUT is available only in RC Oscillator mode.
DS41140C-page 28
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PIC16C432
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns), divided by the prescaler value. The only
requirement on T0CKI high and low time is that they do
not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
6.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 6-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 6-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
Prescaler Output
(2)
(1)
(3)
External Clock/Prescaler
Output after Sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC (Duration of Q = TOSC). There-
fore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
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Preliminary
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PIC16C432
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
6.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 6-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
FIGURE 6-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
8
M
U
X
1
0
0
1
M
U
X
T0CKI
pin
SYNC
TMR0 reg
2
Cycles
T0SE
T0CS
Set Flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8-to-1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
DS41140C-page 30
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
EXAMPLE 6-2:
CHANGING PRESCALER
(WDTTIMER0)
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
CLRWDT
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
RESET,
the
following
instruction
sequence
;Select TMR0, new
;prescale value and
;clock source
(Example 6-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
MOVWF
BCF
OPTION_REG
STATUS, RP0
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0WDT)
1.BCF
STATUS, RP0 ;Skip if already in
; Bank 0
2.CLRWDT
3.CLRF
;Clear WDT
;Clear TMR0 & Prescaler
TMR0
4.BSF
STATUS, RP0 ;Bank 1
5.MOVLW
6.MOVWF
'00101111’b ;These 3 lines (5, 6, 7)
OPTION
; are required only
; if desired PS<2:0>
; are
7.CLRWDT
8.MOVLW
9.MOVWF
10.BCF
; 000 or 001
'00101xxx’b ;Set Postscaler to
OPTION ; desired WDT rate
STATUS, RP0 ;Return to Bank 0
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 6-2. This
precaution must be taken, even if the WDT is disabled.
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on:
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
POR
RESETS
01h
TMR0
Timer0 module register
GIE PEIE T0IE
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
0Bh/8Bh
81h
INTCON
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF
PS0
OPTION RBPU INTEDG T0CS
TRISA
(2)
85h
—
—
—
TRISA4 TRISA3 TRISA2 TLINRX
TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’, x= unknown, u= unchanged
Note 1: Shaded bits are not used by TMR0 module.
2: TLINRX must be set to ‘1’ at all times.
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Preliminary
DS41140C-page 31
PIC16C432
NOTES:
DS41140C-page 32
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
7.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The on-
chip voltage reference (Section 8.0) can also be an
input to the comparators.
The CMCON register, shown in Register 7-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 7-1.
REGISTER 7-1:
CMCON REGISTER (ADDRESS 1Fh)
R-0
R-0
U-0
—
U-0
—
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
C2OUT
C1OUT
bit7
bit0
bit 7
bit 6
C2OUT: Comparator 2 Output bit
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
C1OUT: Comparator 1 Output bit
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
bit 5-4
bit 3
Unimplemented: Read as '0'
CIS: Comparator Input Switch bit
When CM<2:0> = 001:
1= C1 VIN- connects to RA3
0= C1 VIN- connects to RA0
When CM<2:0> = 010:
1= C1 VIN- connects to RA3
C2 VIN- connects to RA2
0= C1 VIN- connects to RA0
C2 VIN- connects to LINRX
bit 2-0
CM<2:0>: Comparator Mode bits
(See Figure 7-1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset ’1’ = Bit is set
7.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 7-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the Comparator
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 12-1.
Note: Comparator interrupts should be disabled
during a Comparator mode change, other-
wise a false interrupt may occur.
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Preliminary
DS41140C-page 33
PIC16C432
FIGURE 7-1:
COMPARATOR I/O OPERATING MODES
A
A
A
A
VIN-
VIN+
VIN-
D
D
D
D
VIN-
VIN+
VIN-
-
-
RA0/AN0
RA3/AN3
LINRX
RA0/AN0
RA3/AN3
LINRX
Off
Off
C1
C2
C1
C2
(Read as ‘0’)
(Read as ‘0’)
+
-
+
-
Off
Off
(Read as ‘0’)
(Read as ‘0’)
VIN+
VIN+
+
+
RA2/AN2
RA2/AN2
CM<2:0> = 000
CM<2:0> = 111
Comparators Reset
Comparators Off
A
RA0/AN0
CIS=0
CIS=1
CIS=0
VIN-
A
VIN-
VIN+
VIN-
-
-
RA0/AN0
C1
C2
C1OUT
C2OUT
C1
C2
A
C1OUT
RA3/AN3
VIN+
A
+
-
+
-
RA3/AN3
A
LINRX
VIN-
A
LINRX
C2OUT
A
CIS=1
RA2/AN2
VIN+
A
VIN+
+
+
RA2/AN2
From VREF Module
CM<2:0> = 011
Four Inputs Multiplexed to
Two Comparators
CM<2:0> = 010
Two Common Reference Comparators
A
D
VIN-
-
A
D
VIN-
VIN+
VIN-
-
RA0/AN0
RA3/AN3
Off
RA0/AN0
RA3/AN3
LINRX
C1
C1
C2
C1OUT
(Read as ‘0’)
VIN+
+
+
-
A
A
VIN-
A
A
-
C2OUT
LINRX
Off
C2
VIN+
+
(Read as ‘0’)
VIN+
RA2/AN2
+
RA2/AN2
CM<2:0> = 011
RA4 Open Drain
CM<2:0> = 110
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
A
A
CIS=0
VIN-
D
D
VIN-
RA0/AN0
-
-
RA0/AN0
RA3/AN3
Off
C1
C2
CIS=1
VIN+
C1
C2
C1OUT
C2OUT
VIN+
(Read as ‘0’)
RA3/AN3
LINRX
+
+
-
A
A
VIN-
A
A
VIN-
-
LINRX
C2OUT
VIN+
VIN+
+
+
RA2/AN2
RA2/AN2
CM<2:0> = 101
Three Inputs Multiplexed to
Two Comparators
CM<2:0> = 001
One Independent Comparators
Legend: A = Analog Input, Port Reads ‘0’ Always
D = Digital Input
CIS = CMCON<3>, Comparator Input Switch
DS41140C-page 34
Preliminary
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PIC16C432
The code example in Example 7-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 7-1:
INITIALIZING
COMPARATOR MODULE
FLAG_REGEQU
0X20
CLRF
CLRF
FLAG_REG
PORTA
;Init flag register
;Init PORTA
MOVF
CMCON,W
0xC0
;Move comparator contents to W
;Mask comparator bits
ANDLW
IORWF
MOVLW
MOVWF
BSF
FLAG_REG,F ;Store bits in flag register
0x03
CMCON
;Init comparator mode
;CM<2:0> = 011
STATUS,RP0 ;Select Bank1
MOVLW
MOVWF
0x07
TRISA
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
STATUS,RP0 ;Select Bank 0
DELAY 10
CMCON,F
PIR1,CMIF
;10ms delay
;Read CMCONtoendchangecondition
;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
7.2
Comparator Operation
A single comparator is shown in Figure 7-2, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 7-2 represent
the uncertainty due to input offsets and response time.
7.3
Comparator Reference
An external or internal reference signal may be used,
depending on the Comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 7-2).
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 35
PIC16C432
FIGURE 7-2:
SINGLE COMPARATOR
VIN+
VIN-
+
-
Output
VIN-
VIN+
Output
7.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same, or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
7.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 8.0, Voltage Reference Module,
contains a detailed description of the Voltage Refer-
ence Module that provides this signal. The internal ref-
erence signal is used when the comparators are in
mode CM<2:0> = 010 (Figure 7-1). In this mode, the
internal voltage reference is applied to the VIN+ pin of
both comparators.
7.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal ref-
erence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs, otherwise the maximum delay of
the comparators should be used (Table 12.1).
DS41140C-page 36
Preliminary
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PIC16C432
7.5
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications. Figure 7-
3 shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4 pins while in this mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is speci-
fied.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 37
PIC16C432
FIGURE 7-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
To RA3 or
RA4 Pin
Data
Bus
Q
D
RD CMCON
EN
Set
CMIF
bit
Q
D
From
Other
Comparator
EN
CL
RD CMCON
NRESET
DS41140C-page 38
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
7.6
Comparator Interrupts
7.9
Analog Input Connection
Considerations
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
A simplified circuit for an analog input is shown in
Figure 7-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
7.7
Comparator Operation During
SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode when enabled.
While the comparator is powered up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering SLEEP.
If the device wakes up from SLEEP, the contents of the
CMCON register are not affected.
7.8
Effects of a RESET
A device RESET forces the CMCON register to its
RESET state. This forces the comparator module to be
in the Comparator RESET mode, CM<2:0> = 000. This
ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered down during the RESET interval.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 39
PIC16C432
FIGURE 7-4:
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10 K
RIC
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend
CPIN
VT
= Input capacitance
= Threshold voltage
ILEAKAGE
RIC
= Leakage current at the pin due to various junctions
= Interconnect resistance
RS
= Source impedance
VA
= Analog voltage
TABLE 7-1:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
RESETS
Value on:
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1Fh
9Fh
0Bh
0Ch
8Ch
85h
CMCON C2OUT C1OUT
—
VRR
T0IE
—
—
—
CIS
VR3
RBIE
—
CM2
VR2
T0IF
—
CM1
VR1
INTF
—
CM0
VR0
RBIF
—
00-- 0000 00-- 0000
000- 0000 000- 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
-0-- ---- -0-- ----
VRCON
INTCON
PIR1
VREN
GIE
—
VROE
PEIE
CMIF
CMIE
—
INTE
—
PIE1
—
—
—
—
—
—
—
(1)
TRISA
—
—
TRISA4 TRISA3 TRISA2 TLINRX
TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented, read as ‘0’, x = unknown, u = unchanged
Note 1: TLINRX must be set to ‘1’ at all times.
DS41140C-page 40
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
8.1
Configuring the Voltage Reference
8.0
VOLTAGE REFERENCE
MODULE
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Register 8-1. The block diagram
is given in Figure 8-1.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 12.1). Example 8-1 shows an example of how
to configure the Voltage Reference for an output volt-
age of 1.25V with VDD = 5.0V.
REGISTER 8-1:
VRCON REGISTER (ADDRESS 9Fh)
R/W-0
R/W-0
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
VREN
VROE
bit7
bit0
bit 7
bit 6
bit 5
VREN: VREF Enable bit
1= VREF circuit powered on
0= VREF circuit powered down, no IDD drain
VROE: VREF Output Enable bit
1= VREF is output on RA2 pin
0= VREF is disconnected from RA2 pin
VRR: VREF Range Selection bit
1= Low Range
0= High Range
bit 4
Unimplemented: Read as '0'
bit 3-0
VR<3:0>: VREF Value Selection 0 VR [3:0] 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’0’ = Bit is cleared
x = Bit is unknown
FIGURE 8-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
R
R
R
8R
R
8R
VRR
VR3
VREF
(From VRCON<3:0>)
16-1 Analog Mux
VR0
Note 1: R is defined in Table 12-2.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 41
PIC16C432
EXAMPLE 8-1:
VOLTAGE REFERENCE
CONFIGURATION
8.4
Effects of a RESET
A device RESET disables the Voltage Reference by
clearing bit VREN (VRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
MOVLW
MOVWF
BSF
0x02
; 4 Inputs Muxed
; to 2 comps.
CMCON
STATUS,RP0
0x07
; go to Bank 1
; RA3-RA0 are
; outputs
MOVLW
MOVWF
MOVLW
MOVWF
TRISA
0xA6
; enable VREF
; low range
8.5
Connection Considerations
VRCON
The
Voltage
Reference
Module
operates
; set VR<3:0>=6
; go to Bank 0
; 10s delay
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin, with an input signal present,
will increase current consumption. Connecting RA2 as
a digital output with VREF enabled will also increase
current consumption.
BCF
STATUS,RP0
DELAY10
CALL
8.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network (Figure 8-
1) keep VREF from approaching VSS or VDD. The Volt-
age Reference is VDD derived and therefore, the VREF
output changes with fluctuations in VDD. The absolute
accuracy of the Voltage Reference can be found in
Table 12-2.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 8-2 shows an example buffering
technique.
8.3
Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer timeout, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 8-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
R
RA2
VREF
Module
+
–
•
VREF Output
•
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 8-2:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Value On
All Other
RESETS
Value On
POR/BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Fh
1Fh
85h
VRCON
VREN
VROE VRR
—
—
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
000- 0000 000- 0000
00-- 0000 00-- 0000
CMCON C2OUT C1OUT
TRISA
—
—
(1)
—
—
TRISA4 TRISA3 TRISA2 TLINRX
TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented, read as ‘0’
Note 1: TLINRX must be set to ‘1’ at all times.
DS41140C-page 42
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
The PIC16C432 has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only, and is
designed to keep the part in RESET while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which provides at least a
72 ms RESET. With these three functions on-chip,
most applications need no external RESET circuitry.
9.0
SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC16C432 device has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection.
These are:
1. OSC Selection
2. RESET
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up, or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOD)
3. Interrupts
4. Watchdog Timer (WDT)
5. SLEEP
6. Code Protection
7. ID Locations
9.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in
program memory location 2007h.
8. In-circuit Serial Programming
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 43
PIC16C432
REGISTER 9-1:
CONFIGURATION WORD
(2)
(2)
(2)
(1)
(2)
(1)
CP1 CP0
CP1 CP0
CP1 CP0
—
BODEN
CP1 CP0 PWRTE WDTE F0SC1 F0SC0
bit 0
bit 13
(2)
bit 13-8
bit 5-4
CP1:CP0 Pairs: Code protection bit pairs
Code protection for 2K program memory bits
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
bit 7
bit 6
Unimplemented: Read as '1'
(1)
BODEN: Brown-out Reset Enable bit
1= BOD enabled
0= BOD disabled
(1)
bit 3
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit
PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset in enabled.
2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS41140C-page 44
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
TABLE 9-1:
Mode
CERAMIC RESONATORS,
PIC16C432
9.2
Oscillator Configurations
9.2.1
OSCILLATOR TYPES
Ranges Tested:
The PIC16C432 can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
• LP - Low Power Crystal
HS
8.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
• XT - Crystal/Resonator
16.0 MHz
• HS - High Speed Crystal/Resonator
• RC - Resistor/Capacitor
These values are for design guidance only. See
notes at bottom of page.
9.2.2
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
TABLE 9-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR,
PIC16C432
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 9-1). The PIC16C432 oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 9-2).
Crystal Cap. Range
Cap.
Osc Type
Freq
C1
Range C2
LP
32 kHz
33 pF
33 pF
200 kHz 15 pF
200 kHz 47-68 pF
15 pF
XT
HS
47-68 pF
15 pF
1 MHz
4 MHz
4 MHz
8 MHz
15 pF
15 pF
15 pF
FIGURE 9-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
15 pF
15 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz 15-33 pF
CONFIGURATION)
These values are for design guidance only. See
notes at bottom of page.
OSC1
C1
To Internal Logic
SLEEP
XTAL
OSC2
Note 1: Recommended values of C1 and C2 are
RF
indentical to the ranges tested table.
R
S
2: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
Note 2
C2
PIC16C432
Note 1: See Table 9-1 and Table 9-2 for recom-
mended values of C1 and C2.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
2: A series resistor may be required for AT strip
cut crystals.
FIGURE 9-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
4: Rs may be required in HS mode, as well
as XT mode, to avoid over driving crystals
with low drive level specification.
CONFIGURATION)
Clock from
ext. system
OSC1
PIC16C432
OSC2
Open
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 45
PIC16C432
9.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
9.2.4
RC OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 9-5 shows how the
R/C combination is connected to the PIC16C432. For
REXT values below 2.2 k, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (i.e., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, it is
recommended to keep REXT between 3 k and 100 k.
Either a prepackaged oscillator can be used, or a sim-
ple oscillator circuit with TTL gates can be built. Pre-
packaged oscillators provide a wide operating range
and better stability. A well designed crystal oscillator
will provide good performance with TTL gates. Two
types of crystal oscillator circuits can be used: one with
series resonance, or one with parallel resonance.
Figure 9-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180 phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 9-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance, or
package lead frame capacitance.
+5V
10k
To Other
Devices
74AS04
4.7k
PIC16C432
CLKIN
74AS04
The variation is larger for larger R (since leakage cur-
rent variation will affect RC frequency more for large R)
and for smaller C (since variation of input capacitance
will affect RC frequency more).
10k
XTAL
See Section 2.0 for variation of oscillator frequency due
to VDD for given REXT/CEXT values, as well as
frequency variation due to operating temperature for
given R, C, and VDD values.
10k
20 pF
20 pF
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin and can be used for test pur-
poses, or to synchronize other logic (see Figure 4-2 for
waveform).
Figure 9-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180
phase shift in a series resonant oscillator circuit. The
330 k resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 9-5:
RC OSCILLATOR MODE
VDD
FIGURE 9-4:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
PIC16C432
REXT
OSC1
Internal Clock
CEXT
VDD
To other
Devices
330
330
OSC2/CLKOUT
74AS04
74AS04
74AS04
PIC16C432
FOSC/4
CLKIN
0.1 mF
XTAL
DS41140C-page 46
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
WDT Reset and MCLR Reset during SLEEP. They are
not affected by a WDT wake-up, since this is viewed as
the resumption of normal operation. TO and PD bits are
set or cleared differently in different RESET situations,
as indicated in Table 9-4. These bits are used in soft-
ware to determine the nature of the RESET. See
Table 9-6 for a full description of RESET states of all
registers.
9.3
RESET
The PIC16C432 differentiates between various kinds of
RESET:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) WDT Reset (normal operation)
e) WDT wake-up (SLEEP)
A simplified block diagram of the On-chip Reset Circuit
is shown in Figure 9-6.
f) Brown-out Reset (BOD)
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 12-6 for pulse width
specification.
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are RESET to
a “RESET state” on Power-on Reset, MCLR Reset,
FIGURE 9-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP pin
SLEEP
WDT
WDT
Module
Timeout
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
10-bit Ripple-counter
Chip_Reset
Q
R
OSC1/
CLKIN
pin
PWRT
10-bit Ripple-counter
(1)
On-chip
RC OSC
Enable PWRT
Enable OST
See Table 9-3 for timeout situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 47
PIC16C432
The Power-Up time delay will vary from chip-to-chip
and due to VDD, temperature and process variation.
See DC parameters for details.
9.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOD)
9.4.3
OSCILLATOR START-UP TIMER
(OST)
9.4.1
POWER-ON RESET (POR)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
electrical specifications for details.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
The POR circuit does not produce an internal RESET
when VDD declines.
9.4.4
BROWN-OUT RESET (BOD)
The PIC16C432 has an on-chip Brown-out Reset cir-
cuitry. A configuration bit, BOREN, can disable (if clear/
programmed), or enable (if set) the Brown-out Reset
circuitry. If VDD falls below 4.0V (refer to BVDD param-
eter D005) for greater than parameter (TBOR) in
Table 12-6, the brown-out situation will reset the chip.
A RESET won’t occur if VDD falls below 4.0V for less
than parameter (TBOR).
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating condi-
tions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until VDD rises
above BVDD. The Power-up Timer will then be invoked
and will keep the chip in RESET an additional 72 ms.
9.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
timeout on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in RESET as long as PWRT
is active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE, can
disable (if set), or enable (if cleared or programmed)
the Power-up Timer. The Power-up Timer should
always be enabled when Brown-out Reset is enabled.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset and
the Power-up Timer will be re-initialized. Once VDD rises
above BVDD, the Power-up Timer will execute a 72 ms
RESET. The Power-up Timer should always be enabled
when Brown-out Reset is enabled. Figure 9-7 shows
typical Brown-out situations.
FIGURE 9-7:
BROWN-OUT SITUATIONS
VDD
BVDD
Internal
Reset
72 ms
VDD
BVDD
Internal
Reset
<72 ms
72 ms
VDD
BVDD
Internal
Reset
72 ms
DS41140C-page 48
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
9.4.5
TIMEOUT SEQUENCE
9.4.6
POWER CONTROL (PCON)/STATUS
REGISTER
On power-up, the timeout sequence is as follows: First
PWRT timeout is invoked after POR has expired, then
OST is activated. The total timeout will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no timeout at all. Figure 9-8,
Figure 9-8 and Figure 9-9 depict timeout sequences.
The power control/status register, PCON (address
8Eh), has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOR = 0, indicating
that a brown-out has occurred. The BOR status bit is a
“don’t care” and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Since the timeouts occur from the POR pulse, if MCLR
is kept low long enough, the timeouts will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-8). This is useful for testing purposes or
to synchronize more than one PIC® device operating in
parallel.
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subse-
quent RESET, if POR is ‘0’, it will indicate that a Power-
on Reset must have occurred (VDD may have gone too
low).
Table 9-5 shows the RESET conditions for some spe-
cial registers, while Table 9-6 shows the RESET condi-
tions for all the registers.
TABLE 9-3:
TIMEOUT IN VARIOUS SITUATIONS
Power-up
Wake-up
Brown-out Reset
Oscillator Configuration
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
72 ms + 1024 TOSC
72 ms
1024 TOSC
—
TABLE 9-4:
POR
STATUS/PCON BITS AND THEIR SIGNIFICANCE
BOR
TO
1
PD
1
0
0
X
X
Power-on Reset
0
X
Illegal, TO is set on POR
0
1
1
1
X
0
1
1
X
X
0
0
0
X
u
0
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
1
1
1
1
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during SLEEP
Legend: x = unknown, u = unchanged
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 49
PIC16C432
TABLE 9-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
---- --0x
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
0001 0uuu
0000 uuuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
WDT Wake-up
PC + 1
000h
PC + 1(1)
Brown-out Reset
Interrupt Wake-up from SLEEP
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the inter-
rupt vector (0004h) after execution of PC+1.
TABLE 9-6:
Register
INITIALIZATION CONDITION FOR REGISTERS
MCLRResetduringNormal
Wake-up from SLEEP
through Interrupt
Wake-up from SLEEP
through WDT Timeout
Operation
MCLR Reset during SLEEP
WDT Reset
Address
Power-on Reset
Brown-out Reset(1)
W
—
xxxx xxxx
—
uuuu uuuu
-
uuuu uuuu
-
INDF
00h
01h
02h
03h
04h
05h
06h
1Fh
0Ah
0Bh
0Ch
81h
85h
86h
8Ch
8Eh
90h
9Fh
TMR0
PCL
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
00-- 0000
---0 0000
0000 000x
-0-- ----
1111 1111
---1 1111
1111 1111
-0-- ----
---- --0x
---- -111
000- 0000
uuuu uuuu
0000 0000
000q quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
00-- 0000
---0 0000
0000 000u
-0-- ----
1111 1111
---1 1111
1111 1111
-0-- ----
---- --uq(1,6)
---- -1-1
000- 0000
uuuu uuuu
PC + 1(3)
uuuq quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
uu-- uuuu
---u uuuu
uuuu uqqq(2)
-q-- ----(2,5)
uuuu uuuu
---u uuuu
uuuu uuuu
-u-- ----
---- --uu
---- -1-1
uuu- uuuu
STATUS
FSR
PORTA
PORTB
CMCON
PCLATH
INTCON
PIR1
OPTION
TRISA
TRISB
PIE1
PCON
LININTF
VRCON
Legend: u= unchanged, x= unknown, - = unimplemented bit, reads as ‘0’, q= value depends on condition
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 9-5 for RESET value for specific conditions.
5: If wake-up was due to comparator input changing , then bit 6 = 1. All other interrupts generating a wake-
up will cause bit 6 = u.
6: If RESET was due to brown-out, then PCON bit0 = 0. All other RESETS will cause bit0 = u.
DS41140C-page 50
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
FIGURE 9-8:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
FIGURE 9-9:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
FIGURE 9-10:
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
OST TIMEOUT
TOST
INTERNAL RESET
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 51
PIC16C432
FIGURE 9-11:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 9-13:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
R1
VDD
VDD
VDD
Q1
D
R
MCLR
R1
R2
40k
MCLR
PIC16C432
PIC16C432
C
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor quickly
when VDD powers down.
R1
= 0.7V
VDD x
R1 + R2
2: < 40 k is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100 to 1 k will limit any current flow-
ing into MCLR from external capacitor C, in
the event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
2: Internal brown-out detection should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the charac-
teristics of the transistor.
FIGURE 9-14:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
FIGURE 9-12:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
MCP809
VDD
Bypass
VSS
Capacitor
VDD
33k
VDD
VDD
RST
MCLR
10k
MCLR
PIC16C432
40k
PIC16C432
This brown-out protection circuit employs Microchip
Technology’s MCP809 microcontroller supervisor. The
MCP8XX and MCP1XX families of supervisors provide
push-pull and open collector outputs with both high and
low active RESET pins. There are 7 different trip point
selections to accommodate 5V and 3V systems.
Note 1: This circuit will activate RESET when VDD
goes below (Vz + 0.7V), where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.
DS41140C-page 52
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
9.5
Interrupts
The PIC16C432 has 4 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB<7:4>)
• Comparator interrupt
• LIN Bus wake-up can be wired to RB0, or compar-
ator
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs (Figure 9-
16). The latency is the same for one or two cycle
instructions. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
The interrupt control register (INTCON) and the Periph-
eral Interrupt Register (PIR1) record individual interrupt
requests in flag bits. INTCON and PIR1 have individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
Note 1: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which re-
enables all unmasked interrupts.
2: When an instruction that clears the GIE bit
is executed, any interrupts that were
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
pending for execution in the next cycle are
ignored. The CPU will execute a NOPin the
cycle immediately following the instruction
which clears the GIE bit. The interrupts
which were ignored are still pending to be
serviced when the GIE bit is set again.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
FIGURE 9-15:
INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
CMIF
CMIE
PEIE
GIE
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 53
PIC16C432
9.5.1
RB0/INT INTERRUPT
9.5.2
TMR0 INTERRUPT
External interrupt on RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the Interrupt Service Routine before re-
enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 9.8 for
details on SLEEP and Figure 9-18 for timing of wake-
up from SLEEP through RB0/INT interrupt.
An overflow (FFh 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
9.5.3
PORTB INTERRUPT
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 4.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
9.5.4
COMPARATOR INTERRUPT
See Section 7.6 for complete description of comparator
interrupts.
FIGURE 9-16:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC+1
PC+1
—
0005h
PC
Instruction
Fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 1-4 Tcy where Tcy = instruction cycle time. Latency is the same whether Inst (PC) is a single
cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
DS41140C-page 54
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
9.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
Example 9-7 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x70 in Bank 0 and it must also be defined at 0xF0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 9-7:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 9-7:
SAVING THE STATUS
AND W REGISTERS IN
RAM
MOVW
F
W_TEMP
;copy W to temp register,
;could be in either bank
SWAP
F
STATUS,W
STATUS,RP0
;swap status to be saved
into W
BCF
;change to bank 0 regard-
less
;of current bank
MOVW
F
STATUS_TEMP ;save status to bank 0
;register
:
:
:
(ISR)
SWAP
F
STATUS_TEMP ;swap STATUS_TEMP regis-
,W
ter
;into W, sets bank to
original
;state
MOVW
F
STATUS
;move W into STATUS regis-
ter
SWAP
F
W_TEMP,F
W_TEMP,W
;swap W_TEMP
SWAP
F
;swap W_TEMP into W
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 55
PIC16C432
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control, by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
9.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run even
if the clock on the OSC1 and OSC2 pins of the device
have been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 9.1).
The CLRWDTand SLEEPinstructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
9.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT timeout occurs.
9.7.1
WDT PERIOD
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with tempera-
ture, VDD and process variations from part to part (see
FIGURE 9-17:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-6)
0
M
U
X
Postscaler
8
1
Watchdog
Timer
•
PS<2:0>
To TMR0 (Figure 6-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
TABLE 9-8:
SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
OPTION
—
BOREN
INTEDG
CP1
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
RBPU
T0CS
T0SE
Legend: _ = Unimplemented location, read as “0”, + = Reserved for future use
Note 1: Shaded cells are not used by the Watchdog Timer.
DS41140C-page 56
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
9.8.1
WAKE-UP FROM SLEEP
9.8
Power-down Mode (SLEEP)
The device can wake-up from SLEEP through one of
the following events:
The Power-down mode is entered by executing a
SLEEPinstruction.
1. External RESET input on MCLR pin.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before SLEEPwas executed (driving high, low, or hi-
impedance).
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
4. LIN activity.
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin, and the com-
parators and VREF should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on-chip pull-ups on PORTB should be considered.
The first event will cause a device RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOPafter the SLEEPinstruction.
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEPinstruction is completely executed.
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 57
PIC16C432
FIGURE 9-18:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
Fetched
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay does not occur for RC Osc mode.
3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C6X/7X/9XX Programming Specifications (Liter-
ature #DS30228).
9.9
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note: Microchip does not recommend code
protecting windowed devices.
9.10 ID Locations
A typical in-circuit serial programming connection is
shown in Figure 9-19.
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during program/verify. Only the
Least Significant 4 bits of the ID locations are used.
FIGURE 9-19:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
9.11 In-Circuit Serial Programming
To Normal
Connections
The PIC16C432 microcontroller can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
External
Connector
Signals
PIC16C432
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
VDD
To Normal
Connections
DS41140C-page 58
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
The instruction set is highly orthogonal and is grouped
into three basic categories:
10.0 INSTRUCTION SET SUMMARY
Each PIC16C432 instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16C432 instruction
set summary in Table 10-2 lists byte-oriented, bit-
oriented, and literal and control operations.
Table 10-1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is 1 s. If
a
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 s.
Table 10-1 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure 10-1 shows the three general formats that the
instructions can have.
For literal and control operations, 'k' represents an
eight- or eleven-bit constant, or literal value.
Note: To maintain upward compatibility with
future PIC® products, do not use the
OPTIONand TRISinstructions.
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label
TOS
Label name
Top-of-Stack
PC
Program Counter
PCLATH Program Counter High Latch
GIE
WDT
TO
Global Interrupt Enable bit
Watchdog Timer/Counter
Timeout bit
PD
Power-down bit
dest
Destination, either the W register or the specified
register file location
[
]
)
Options
(
Contents
< >
Assigned to
Register bit field
In the set of
italics User defined term (font is courier)
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 59
PIC16C432
FIGURE 10-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
0
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
k (literal)
DS41140C-page 60
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
TABLE 10-2: PIC16C432 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0000 0011
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
DECFSZ f, d
INCF
f, d
f, d
f, d
f, d
f
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1) the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second is exe-
cuted as a NOP.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 61
PIC16C432
10.1 Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[ label ] ADDLW
0 k 255
k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Encoding:
(W) + k (W)
(W) .AND. (k) (W)
Z
Status Affected: C, DC, Z
Encoding:
11
111x
kkkk
kkkk
11
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and
the result is placed in the W regis-
ter.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDLW
0x15
ANDLW
0x5F
Before Instruction
Before Instruction
W
=
0x10
0x25
W
=
0xA3
0x03
After Instruction
After Instruction
W
=
W
=
ADDWF
Add W and f
ANDWF
AND W with f
Syntax:
[ label ] ADDWF f,d
Syntax:
[ label ] ANDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) (dest)
Operation:
(W) .AND. (f) (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
Encoding:
00
0111
dfff
ffff
00
0101
dfff
ffff
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result is
stored in the W register. If 'd' is 1, the
result is stored back in register 'f'.
Description:
AND the W register with register 'f'.
If 'd' is 0, the result is stored in the
W register. If 'd' is 1, the result is
stored back in register 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR,
1
Before Instruction
Before Instruction
W
=
0x17
W
=
0x17
0xC2
FSR = 0xC2
After Instruction
FSR =
After Instruction
W
=
0xD9
W
=
0x17
0x02
FSR = 0xC2
FSR =
DS41140C-page 62
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 (f<b>)
Operation:
skip if (f<b>) = 0
None
Status Affected: None
01
00bb
bfff
ffff
Encoding:
01
10bb
bfff
ffff
Bit 'b' in register 'f' is cleared.
Description:
If bit 'b' in register 'f' is '0', then the
next instruction is skipped.
1
1
If bit 'b' is '0', then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction.
Cycles:
Example
BCF
FLAG_REG, 7
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
0xC7
0x47
Words:
Cycles:
Example
1
(2)
1
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1>= 0,
PC = address TRUE
if FLAG<1>=1, PC = address
FALSE
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 (f<b>)
None
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
1
1
Cycles:
Example
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
=
=
0x0A
0x8A
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 63
PIC16C432
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL
0 k 2047
k
Operands:
0 f 127
0 b < 7
Operands:
Operation:
(PC) + 1 TOS,
k PC<10:0>,
Operation:
skip if (f<b>) = 1
(PCLATH<4:3>) PC<12:11>
Status Affected: None
Status Affected:
Encoding:
None
Encoding:
01
11bb
bfff
ffff
10
0kkk
kkkk
kkkk
Description:
If bit 'b' in register 'f' is '1' then the
next instruction is skipped.
Description:
Call Subroutine. First, return
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a two-
cycle instruction.
address (PC+1) is pushed onto the
stack. The eleven bit immediate
address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis a
two-cycle instruction.
Words:
Cycles:
Example
1
(2)
Words:
Cycles:
Example
1
2
1
HERE
FALSE
TRUE
BTFSS
GOTO
•
•
•
FLAG,1
PROCESS_CODE
HERE
Before Instruction
PC = Address HERE
After Instruction
CALL
THERE
Before Instruction
PC = address HERE
After Instruction
if FLAG<1> = 0,
PC = Address THERE
TOS = Address HERE+1
PC = address FALSE
CLRF
Clear f
if FLAG<1> = 1,
PC = address TRUE
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
Operation:
00h (f)
1 Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
Description:
The contents of register 'f' are
cleared and the Z bit is set.
Words:
Cycles:
Example
1
1
CLRF
Before Instruction
FLAG_REG = 0x5A
After Instruction
FLAG_REG = 0x00
FLAG_REG
Z = 1
DS41140C-page 64
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
COMF
Complement f
CLRW
Clear W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CLRW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
00h (W)
1 Z
Operation:
(f) (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
1001
dfff
ffff
00
0001
0000
0011
Description:
The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is 1, the
result is stored back in register 'f'.
Description:
W register is cleared. Zero bit (Z)
is set.
Words:
Cycles:
Example
1
Words:
Cycles:
Example
1
1
1
CLRW
COMF
Before Instruction
REG1 = 0x13
After Instruction
REG1 = 0x13
W = 0xEC
REG1,0
Before Instruction
W = 0x5A
After Instruction
W = 0x00
Z = 1
DECF
Decrement f
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRWDT
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
00h WDT
0 WDT prescaler,
1 TO
Operation:
(f) - 1 (dest)
Status Affected:
Encoding:
Z
1 PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
Decrement register 'f'. If 'd' is 0, the
result is stored in the W register. If
'd' is 1, the result is stored back in
register 'f'.
00
0000
0110
0100
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT,
1
1
Before Instruction
CLRWDT
CNT = 0x01
Z = 0
After Instruction
Before Instruction
WDT counter = ?
After Instruction
WDT counter = 0x00
WDT prescaler = 0
TO = 1
CNT = 0x00
Z = 1
PD = 1
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 65
PIC16C432
DECFSZ
Decrement f, Skip if 0
INCF
Increment f
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (dest); skip if result = 0
Operation:
(f) + 1 (dest)
Status Affected:
Encoding:
None
Status Affected:
Encoding:
Z
00
1011
dfff
ffff
00
1010
dfff
ffff
Description:
The contents of register 'f' are
decremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in register
'f'.
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in regis-
ter 'f'.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOP is executed
instead making it a two-cycle
instruction.
Words:
Cycles:
Example
1
1
INCF
CNT,
1
Before Instruction
Words:
Cycles:
Example
1
CNT = 0xFF
Z = 0
After Instruction
(2)
1
HERE
DECFSZ
GOTO
CNT, 1
LOOP
CNT = 0x00
Z = 1
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
CNT = CNT - 1
if CNT = 0,
PC = address CONTINUE
if CNT¼ 0,
PC = address HERE+1
GOTO
Unconditional Branch
Syntax:
[ label ] GOTO
0 k 2047
k
Operands:
Operation:
k PC<10:0>
PCLATH<4:3> PC<12:11>
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
Description:
GOTOis an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two-
cycle instruction.
Words:
Cycles:
Example
1
2
GOTO THERE
After Instruction
PC = Address THERE
DS41140C-page 66
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
IORLW
Inclusive OR Literal with W
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Syntax:
[ label ] INCFSZ f,d
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (dest), skip if result = 0
Status Affected:
Encoding:
None
11
1000
kkkk
kkkk
00
1111
dfff
ffff
Description:
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in regis-
ter 'f'.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOPis executed
instead making it a two-cycle
instruction.
Words:
Cycles:
Example
1
1
IORL
W
0x35
Before Instruction
W = 0x9A
Words:
Cycles:
Example
1
After Instruction
W = 0xBF
(2)
1
Z = 1
HERE
1
INCFSZ
GOTO
CNT,
LOOP
IORWF
Inclusive OR W with f
CONTINUE •
•
•
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Before Instruction
PC = address HERE
After Instruction
CNT = CNT + 1
if CNT = 0,
Operation:
(W) .OR. (f) (dest)
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
PC = address CONTINUE
if CNT0,
PC = address HERE +1
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in regis-
ter 'f'.
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Before Instruction
RESULT = 0x13
W = 0x91
After Instruction
RESULT = 0x13
W = 0x93
Z = 1
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 67
PIC16C432
MOVLW
Move Literal to W
MOVWF
Move W to f
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Syntax:
[ label ] MOVWF
0 f 127
(W) (f)
f
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
None
None
11
00xx kkkk
kkkk
00
0000
1fff
ffff
Description:
The eight bit literal 'k' is loaded into
W register. The don’t cares will
assemble as 0’s.
Description:
Move data from W register to regis-
ter 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
Before Instruction
OPTION = 0xFF
W = 0x4F
After Instruction
OPTION
MOVLW
0x5A
After Instruction
W = 0x5A
OPTION = 0x4F
W = 0x4F
MOVF
Move f
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
NOP
No Operation
Syntax:
[ label ] NOP
None
Operation:
(f) (dest)
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Status Affected:
Encoding:
Z
No operation
None
00
1000
dfff
ffff
Description:
The contents of register f are
00
0000
0xx0
0000
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
No operation.
1
Cycles:
1
Example
NOP
Words:
Cycles:
Example
1
1
MOVF
FSR,
0
After Instruction
W = value in FSR register
Z = 1
DS41140C-page 68
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
OPTION
Load Option Register
RETLW
Return with Literal in W
Syntax:
[ label ] OPTION
None
Syntax:
[ label ] RETLW
0 k 255
k
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
(W) OPTION
None
k (W);
TOS PC
00
0000
0110
0010
Status Affected:
Encoding:
None
Description:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code
compatibility with PIC16C5X prod-
ucts. Since OPTION is a readable/
writable register, the user can
directly address it.
11
01xx
kkkk
kkkk
Description:
The W register is loaded with the
eight bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE ;W contains table
;offset value
•
value
•
To maintain upward compatibil-
ity with future PIC products, do
not use this instruction.
;W now has table
®
TABLE
•
ADDWF PC ;W = offset
RETLW k1
RETLW k2
;Begin table
;
•
•
RETFIE
Return from Interrupt
Syntax:
[ label ] RETFIE
•
RETLW kn
; End of table
Operands:
Operation:
None
Before Instruction
W = 0x07
After Instruction
TOS PC,
1 GIE
Status Affected:
Encoding:
None
W = value of k8
00
0000
0000
1001
Description:
Return from Interrupt. Stack is
POPed and Top-of-Stack (TOS) is
loaded in the PC. Interrupts are
enabled by setting Global Inter-
rupt Enable bit, GIE
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Encoding:
(INTCON<7>). This is a two-cycle
instruction.
TOS PC
None
Words:
Cycles:
Example
1
00
0000
0000
1000
2
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
RETFIE
After Interrupt
PC = TOS
GIE = 1
Words:
Cycles:
Example
1
2
RETURN
After Interrupt
PC = TOS
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 69
PIC16C432
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
Syntax:
[ label ]
RLF f,d
Syntax:
[ label ] RRF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
See description below
C
Operation:
See description below
C
Status Affected:
Encoding:
Status Affected:
Encoding:
00
1101
dfff
ffff
00
1100
dfff
ffff
Description:
The contents of register 'f' are
Description:
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is stored back in regis-
ter 'f'.
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in register
'f'.
C
Register f
C
Register f
Words:
Cycles:
Example
1
Words:
Cycles:
Example
1
1
1
RLF
REG1,0
RRF
REG1,0
Before Instruction
REG1 = 1110 0110
Before Instruction
REG1 = 1110 0110
C = 0
C = 0
After Instruction
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1
REG1 = 1110 0110
W = 0111 0011
C = 0
SLEEP
Syntax:
[ label ]
SLEEP
Operands:
Operation:
None
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
Encoding:
TO, PD
00
0000
0110
0011
Description:
The power-down status bit, PD is
cleared. Timeout status bit, TO is
set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 9.8 for more details.
Words:
1
Cycles:
Example:
1
SLEEP
DS41140C-page 70
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
SUBLW
Subtract W from Literal
[ label ] SUBLW
SUBWF
Syntax:
Subtract W from f
Syntax:
k
[ label ]
SUBWF f,d
Operands:
Operation:
0 k 255
k - (W) (W)
C, DC, Z
Operands:
0 f 127
d [0,1]
Operation:
(f) - (W) (dest)
Status
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
Description:
The W register is subtracted (2’s
complement method) from the eight
bit literal 'k'. The result is placed in the
W register.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W register. If
'd' is 1, the result is stored back in reg-
ister 'f'.
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
C
=
=
=
2
2
?
1; result is zero
Example 3:
Before Instruction
W
C
=
=
3
?
After Instruction
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is negative
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 71
PIC16C432
SWAPF
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
SWAPF f,d
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) .XOR. k (W)
Z
Operation:
(f<3:0>) (dest<7:4>),
(f<7:4>) (dest<3:0>)
11
1010
kkkk
kkkk
Status Affected:
Encoding:
None
Description:
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the
W register.
00
1110
dfff
ffff
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is 0,
the result is placed in W register. If
'd' is 1, the result is placed in regis-
ter 'f'.
Words:
1
1
Cycles:
Example:
XORL
W
0xAF
Words:
Cycles:
Example
1
1
Before Instruction
W = 0xB5
SWAPF
Before Instruction
REG1 = 0xA5
After Instruction
REG,
0
After Instruction
W = 0x1A
REG1 = 0xA5
W = 0x5A
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register
Syntax:
[ label ]
XORWF f,d
Syntax:
[ label ] TRIS
5 f 7
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Encoding:
(W) TRIS register f;
Operation:
(W) .XOR. (f) (dest)
None
Status Affected:
Encoding:
Z
00
0000
0110
0fff
00
0110
dfff
ffff
Description:
The instruction is supported for
code compatibility with the
PIC16C5X products. Since TRIS
registers are readable and writable,
the user can directly address them.
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibil-
ity with future PIC products, do
not use this instruction.
XORW
F
REG
1
®
Before Instruction
REG = 0xAF
W = 0xB5
After Instruction
REG = 0x1A
W = 0xB5
DS41140C-page 72
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
The MPLAB IDE allows you to:
11.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PIC® microcontrollers are supported with a full
range of hardware and software development tools:
• One touch assemble (or compile) and download
to PIC MCU emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
MPLIBTM Object Librarian
• Simulators
- MPLAB SIM Software Simulator
• Emulators
11.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PIC MCUs.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
11.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
11.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 73
PIC16C432
11.4 MPLINK Object Linker/
11.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
MPLIB Object Librarian
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PIC micro-
controllers (MCUs). Software control of the MPLAB ICE
in-circuit emulator is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
building, downloading and source debugging from a
single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PIC microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
11.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
11.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PIC series microcontrollers on an instruction level. On
any given instruction, the data areas can be examined
or modified and stimuli can be applied from a file, or
user-defined key press, to any of the pins. The execu-
tion can be performed in single step, execute until
break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS41140C-page 74
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
11.8 MPLAB ICD In-Circuit Debugger
11.11 PICDEM 1 Low Cost PIC MCU
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PIC MCUs and can be used to
develop for this and other PIC microcontrollers. The
MPLAB ICD utilizes the in-circuit debugging capability
built into the FLASH devices. This feature, along with
Microchip's In-Circuit Serial ProgrammingTM protocol,
offers cost-effective in-circuit FLASH debugging from
the graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
11.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In Stand-alone mode, the PRO MATE II
device programmer can read, verify, or program PIC
devices. It can also set code protection in this mode.
11.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
11.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PIC devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 75
PIC16C432
11.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
11.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
11.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS41140C-page 76
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m r e g g u b D e s r e m m a o g P r r
s t K l a i E d v n a s d r a B o o m D e
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 77
PIC16C432
NOTES:
DS41140C-page 78
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
12.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias............................................................................................................-40 to +125C
Storage Temperature ..............................................................................................................................-65 to +150C
Voltage on any pin with respect to VSS (except VDD and MCLR) ....................................................-0.6V to VDD +0.6V
Voltage on VDD with respect to VSS ............................................................................................................. 0 to +7.0V
Voltage on RA4 with respect to VSS........................................................................................................................8.5V
Voltage on MCLR with respect to VSS (Note 2) ..............................................................................................0 to +14V
Voltage on RA4 with respect to VSS........................................................................................................................8.5V
Voltage on LIN with respect to VSS ..........................................................................................................................40V
Total power Dissipation (Note 1)...........................................................................................................................1.0 W
Maximum Current out of VSS pin .......................................................................................................................300 mA
Maximum Current into VDD pin ..........................................................................................................................250 mA
Input clamp current by LIN pin, IIK (VI <0 or VI > VBAT......................................................................................200 mA
Output clamp current by LIN pin, IOK (VO <0 or VO > VBAT) .............................................................................200 mA
Input Clamp Current, IIK (VI <0 or VI> VDD)20 mA
Output Clamp Current, IOK (VO <0 or VO>VDD)20 mA
Maximum Output Current sunk by any I/O pin (source by VDD) ..........................................................................25 mA
Maximum Current sourced by any I/O pin (source by VDD).................................................................................25 mA
Maximum Current sunk by PORTA and PORTB (source by VDD) .....................................................................200 mA
Maximum Current sourced by PORTA and PORTB (source by VDD)................................................................200 mA
Maximum Current sunk by LIN pin (source by VBAT).........................................................................................200 mA
Maximum Current sunk by BACT pin (source by VBAT)......................................................................................1.8 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions, above
those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 79
PIC16C432
FIGURE 12-1:
PIC16C432 VOLTAGE-FREQUENCY GRAPH, -40C TA +125C
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
FREQUENCY (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS41140C-page 80
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
12.1 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
-40C TA +85C for industrial and
-40C TA +125C for extended
Param
Sym
No.
Characteristic
Supply Voltage
Min Typ† Max Units
Conditions
D001
D001A
D002
VDD
VBAT
VDR
4.5
8.0
—
—
5.5
18
—
V
V
V
See Figure 12-1 through Figure 12-3
Battery Supply Voltage
RAM Data Retention
13.8
1.5*
Device in SLEEP mode
(1)
Voltage
D003
D004
D005
VPOR
SVDD
VDD Start Voltage
to ensure Power-on Reset
—
0.05*
3.7
VSS
—
—
—
V
See section on Power-on Reset for details
VDD Rise Rate
to ensure Power-on Reset
V/ms See section on Power-on Reset for details
BOREN configuration bit is cleared
mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled,
VBOR
IDD
Brown-out Detect Voltage
4.0 4.35
V
(2), (4)
Supply Current
D010
—
—
—
1.2
4.0
4.0
2.0
6.0
7.0
(4)
XT Osc mode,
*
mA FOSC = 20 MHz, VDD = 4.5V, WDT disabled,
HS Osc mode
mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled*,
HS Osc mode
(3)
IPD
Power-down Current
D020
—
—
—
—
—
—
5.0
9.0
15
A VDD = 4.5V*
A VDD = 5.5V
A VDD = 5.5V Extended
(5)
D313
D022
IDD-LIN
IWDT
LIN Transceiver Current
1
mA LIN XCVR enabled
(5)
WDT Current
—
6.0
10
12
A VDD = 4.0V
A (125C)
(5)
D022A
D023
IBOR
Brown-out Reset Current
—
—
75
30
125
60
A BOD enabled, VDD = 5.0V
A VDD = 4.0V
ICOMP
Comparator Current for each
(5)
Comparator
(5)
D023A
IVREF
VREF Current
—
80
135
A VDD = 4.0V
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25C, unless otherwise stated. These parameters are for design guidance only and are not tested.
†
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switch-
ing rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2REXT (mA) with REXT in k.
5: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 81
PIC16C432
12.2 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial and
-40°C TA +125°C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Table 12.3
Parm
Sym
No.
Characteristic
Min
Typ†
Max
Unit
Conditions
VIL
Input Low Voltage
I/O ports
with TTL buffer
D030
VSS
—
—
0.8V
V
VDD = 4.5V to 5.5V, Otherwise
0.15 VDD
0.2 VDD
0.2 VDD
D031
D032
with Schmitt Trigger input
MCLR, RA4/T0CKI,OSC1
(in RC mode)
VSS
VSS
V
V
(Note 1)
D033
D034
OSC1 (in XT and HS)
OSC1 (in LP)
VSS
VSS
-8
—
—
—
0.3 VDD
0.6 VDD - 1.0
0.4 VBAT
V
V
V
VIL_LIN Low level input voltage
VIH Input High Voltage
I/O ports
Dominant State
D040
with TTL buffer
2.0V
.25 VDD + 0.8V
0.8 VDD
0.8 VDD
0.7 VDD
0.9 VDD
0.6 VBAT
50
—
VDD
VDD
VDD
VDD
VDD
V
VDD = 4.5V to 5.5V
D041
D042
D043
D043A
with Schmitt Trigger input
MCLR RA4/T0CKI
—
—
V
V
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
(Note 1)
D044 VIH_LIN High level input voltage
—
18
V
Recessive State
D070
IPURB PORTB weak pull-up current
200
400
A VDD = 5.0V, VPIN = VSS
(2), (3)
IIL
Input Leakage Current
I/O ports (Except PORTA)
PORTA
±1.0
±0.5
±1.0
±5.0
A VSS VPIN VDD, pin at hi-impedance
A Vss VPIN VDD, pin at hi-impedance
A Vss VPIN VDD
A Vss VPIN VDD, XT, HS and LP osc
configuration
D060
D061
D063
—
—
—
—
—
—
RA4/T0CKI
OSC1, MCLR
D064 IOH_LIN High level output leakage current
—
—
±20
A VBUS VBAT; VBUS < 40V
VOL Output Low Voltage
D080
D083
D084
I/O ports
—
—
—
—
—
—
—
—
—
—
—
0.6
0.6
V
V
V
V
IOL=8.5 mA, VDD=4.5V, -40 to +85C
IOL=7.0 mA, VDD=4.5V, +125C
IOL=1.6 mA, VDD=4.5V, -40 to +85C
IOL=1.2 mA, VDD=4.5V, +125C
TBD
OSC2/CLKOUT (RC only)
BACT
0.6
0.6
TBD
0.2 VBAT
D085 VOL_LIN Low level output voltage
V
IOL = 200 mA
VBUS = 12V
(3)
VOH Output High Voltage
D090
D092
D093
I/O ports (Except RA4)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
4.0V
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
V
IOH=-3.0 mA, VDD=4.5V, -40 to +85C
IOH=-2.5 mA, VDD=4.5V, +125C
IOH=-1.3 mA, VDD=4.5V, -40 to +85C
IOH=-1.0 mA, VDD=4.5V, +125C
OSC2/CLKOUT (RC only)
VOH BACT
VBAT = 18V, VDD = 5.0V, IOH = 1.8 mA
D094 VOH_LIN High level output voltage
D150* VOD Open-Drain High Voltage
These parameters are characterized but not tested.
0.8 VBAT
8.5
RA4 pin
*
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C432 be driven
with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal
operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: LIN tested 4 MHz, 14.4V VBAT, 5.0V VDD.
DS41140C-page 82
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
12.2 DC CHARACTERISTICS: PIC16C432 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial and
-40°C TA +125°C for extended
Operating voltage VDD range as described in DC spec Table 12.3
DC CHARACTERISTICS
Parm
Sym
No.
Characteristic
Min
Typ†
Max
Unit
Conditions
Capacitive Loading Specs on
Output Pins
D100
COSC2 OSC2 pin
15*
pF In XT, HS and LP modes when external
clock used to drive OSC1
(4)
CLIN LIN
100A
100B
D101
10*
50*
50*
nF
pF
pF
CBACT BACT
CIO All I/O pins/OSC2 (in RC mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C432 be driven
with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal
operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: LIN tested 4 MHz, 14.4V VBAT, 5.0V VDD.
12.3 LIN Transceiver Bus Interface
Specifications
Operating Conditions: VDD range as described in Table 12-1, -40C <TA< +125C
Param
No.
Sym
Characteristics
Min
Typ
Max
Units
Comments
D315
D317
IOL_LIN_DOMINAT Low level output current
40
-1
—
—
200
1
mA
mA
VBUS = 12V
IOH_LIN_REVERS
Low level output
current, open ground
D320*
D321*
VHYS_LIN
ISC_LIN
Input hysteresis
0.05 VBAT
0.05
—
—
0.1VBAT
200
V
VIH_LIN - VIL_LIN
Short circuit current limit
mA
* These parameters are characterized but not tested.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 83
PIC16C432
12.4 Comparator Specifications
Operating Conditions: VDD range as described in Table 12-1, -40C <TA< +125C
Param No.
Sym
Characteristics
Input Offset Voltage
Input Common Mode Voltage
Min
Typ
Max
Units
Comments
D300
D301
D302
300
VIOFF
VICM
± 5.0
± 10
mV
V
0
VDD - 1.5
CMRR CMRR
TRESP Response Time(1)
+55*
db
ns
s
150*
400*
10*
301
TMC2OV Comparator Mode Change to
Output Valid
*
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
12.5 Voltage Reference Specifications.
Operating Conditions: VDD range as described in Table 12-1, -40C <TA< +125C
Param
No.
Sym
Characteristics
Resolution
Min
Typ
Max
Units
Comments
D310
VRES
VRAA
VDD/24
VDD/32
LSB
D311
Absolute Accuracy
+1/4
+1/2
LSB
LSB
Low Range (VRR=1)
High Range (VRR=0)
D312
310
VRUR
TSET
Unit Resistor Value (R)
Settling Time(1)
2K*
Figure 8.1
10*
ms
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000to 1111.
12.6 LIN Transceiver Operating Specifications.
Operating Conditions: VDD range as described in Table 12-1, -40C <TA< +125C
Param
No.
Characteristics
Sym
Min
Typ
Max
Units
Comments
D313
VDD Quiescent Operating
Current
IDD_LIN
—
—
1
mA
D314
VBAT Low Power Current
IBAT
—
—
50
A
*
These parameters are characterized but not tested.
DS41140C-page 84
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
12.7 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
T
Time
CLKOUT
I/O port
MCLR
osc
t0
OSC1
T0CKI
io
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-Impedance
FIGURE 12-2:
LOAD CONDITIONS
Load condition 1
VDD/2
Load condition 2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464
CL = 50 pF for all pins except OSC2 and LIN bus
15 pF for OSC2 output
10 nF for LIN
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 85
PIC16C432
12.8 Timing Diagrams and Specifications
FIGURE 12-3:
EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
(1)
1A
Fosc External CLKIN Frequency
DC
DC
DC
—
—
—
4
MHz XT and RC Osc mode, VDD=5.0V
MHz HS Osc mode
20
200
kHz LP Osc mode
(1)
Oscillator Frequency
DC
0.1
1
—
—
—
–
4
4
MHz RC Osc mode, VDD=5.0 OV
MHz XT Osc mode
20
200
MHz HS Osc mode
DC
kHz LP Osc mode
(1)
1
Tosc
External CLKIN Period
250
50
5
—
—
—
—
—
—
ns
ns
XT and RC Osc mode
HS Osc mode
ms LP Osc mode
(1)
Oscillator Period
250
250
50
—
—
—
—
—
10,000
1,000
—
ns
ns
ns
RC Osc mode
XT Osc mode
HS Osc mode
5
ms LP Osc mode
(1)
2
Tcy
Instruction Cycle Time
200
100*
2*
—
—
—
—
—
—
—
DC
—
—
—
—
—
—
ns
ns
TCY=FOSC/4
3*
TosL, External Clock in (OSC1) High or
TosH Low Time
XT oscillator, TOSC L/H duty cycle
ms LP oscillator, TOSC L/H duty cycle
20*
25*
50*
15*
ns
ns
ns
ns
HS oscillator, TOSC L/H duty cycle
XT oscillator
4*
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
LP oscillator
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type, under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
DS41140C-page 86
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
FIGURE 12-4:
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
14
12
16
18
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note 1: All tests must be done with specified capacitance loads (Figure 12-2) 50 pF on I/O pins and CLKOUT.
TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
Sym
Characteristic
Min
Typ†
Max
Units
No.
—
75
75
35
35
—
—
—
200
200
100
100
20
ns
ns
ns
ns
ns
ns
ns
10*
11*
12*
13*
14*
15*
TosH2ckL OSC1 to CLKOUT(1)
TosH2ckH OSC1 to CLKOUT (1)
—
CLKOUT rise time(1)
CLKOUT fall time(1)
—
TckR
—
TckF
TckL2ioV CLKOUT to Port out valid(1)
TioV2ckH Port in valid before CLKOUT (1)
TckH2ioI Port in hold after CLKOUT (1)
—
TOSC +200 ns
0
—
—
16*
17*
18*
TosH2ioV OSC1 (Q1 cycle) to Port out valid
—
50
—
150
—
ns
ns
TosH2ioI OSC1 (Q2 cycle) to Port input invalid (I/O in
100
hold time)
19*
20*
21*
22*
23
TioV2osH Port input valid to OSC1 (I/O in setup time)
0
—
—
10
10
—
—
—
40
40
—
—
ns
ns
ns
ns
ns
TioR
TioF
Tinp
Trbp
Port output rise time
Port output fall time
—
RB0/INT pin high or low time
RB<7:4> change interrupt high or low time
25
TCY
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 87
PIC16C432
FIGURE 12-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
FIGURE 12-6:
BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 12-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
31
TmcL
Twdt
MCLR Pulse Width (low)
2000
7*
—
—
ns
-40 to +85C
Watchdog Timer Timeout Period
(No Prescaler)
18
33*
ms
VDD = 5.0V, -40 to +85C
32
33
Tost
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024 TOSC
72
—
—
TOSC = OSC1 period
Tpwrt
28*
132*
ms
VDD = 5.0V, -40 to +85C
34
35
TIOZ
I/O hi-impedance from MCLR low
Brown-out Reset Pulse Width
—
—
2.0
—
ms
ms
TBOR
100*
3.7V VDD 4.3V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS41140C-page 88
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
FIGURE 12-7:
RA4/T0CKI
TIMER0 CLOCK TIMING
41
40
42
TMR0
TABLE 12-4: TIMER0 CLOCK REQUIREMENTS
Parameter
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
40
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
41
42
0.5 TCY + 20*
10*
TCY + 40*
N
N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
TABLE 12-5: LIN AC CHARACTERISTICS
Symbol
dV/dt
Parameter
Min.
Typ.
Max.
Unit
Note
Slope rising and falling edges
1
2
3
4
V/s (Note 1)
Ttrans_pd Propagation delay of transmitter
s
Ttrans_pd= max(Ttrans_pdr or
Ttrans_pdf
)
Trec_pd Propagation delay of receiver
6
2
s
s
Trec_pd = max (Trec_pdr or Trec_pdf
Trec_sym = Trec_pdf - Trec_pdr
)
Trec_sym Symmetry of receiver propaga-
tion delay rising edge w.r.t. fall-
ing edge
-2
-2
Ttrans_sym Symmetry of transmitter propa-
gation delay rising edge w.r.t.
falling edge
2
s
Ttrans_sym = Ttrans_pdf - Trans_pdr
Note 1: Rising edge is system dependent. Value is characterized but not tested.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 89
PIC16C432
TABLE 12-6: LIN THERMAL CHARACTERISTICS
Symbol
recovery
Parameter
Typ.
Max.
Unit
Note
Recovery Temperature
+135
°C
Information
Parameter
shutdown
Shutdown Temperature
Thermal Recovery Time
+155
°C
Information
Parameter
TTHERM
1.5
ms
Information
Parameter
FIGURE 12-8:
TIMING DIAGRAM
TxD (input of physical layer)
t
t
trans_pdr
trans_pdf
Bus Signal
rec. threshold
rec. threshold
t
rec_pdf
t
rec_pdr
RxD (physical layer output)
DS41140C-page 90
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
13.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs and tables, the data presented is outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. ‘Typical’ represents the mean of the distribution at 25C. ‘max’ or ‘min’ represents
(mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
FIGURE 13-1:
LIN TRANSCEIVER SHUTDOWN HYSTERESIS (V) VS. TEMPERATURE (C)
20
18
150.0
135.2
143.1
16
14
12
10
8
VBAT = 18.0V
VDD = 5.0V
TXD = 0V
Temp (Shutdown)
Temp (Recover)
6
4
2
120
120
135.2
135
143.1
145
0
115
125
130
140
150
155
TEMPERATURE (C)
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 91
PIC16C432
NOTES:
DS41140C-page 92
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
14.0 PACKAGING INFORMATION
14.1 Package Marking Information
20-Lead CERDIP Windowed
Example
PIC16C432/P301
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
0007CBP
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16C432
-I/218
0007CBP
20-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16C432/P301
0007CBP
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( )
e
3
*
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 93
PIC16C432
20-Lead Ceramic Dual In-Line with Window (JW) - 300 mil (CERDIP)
Package drawing not available at this time.
DS41140C-page 94
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
1
n
a
c
A2
A
f
L
A1
b
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
f
Lead Width
B
a
b
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 95
PIC16C432
20-Lead Plastic Dual In-Line (P) - 300 mil (PDIP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.295
.240
1.025
.120
.008
.055
.014
.310
5
.145
3.68
0.38
7.49
6.10
26.04
3.05
0.20
1.40
0.36
7.87
5
.310
.250
1.033
.130
.012
.060
.018
.370
10
.325
.260
1.040
.140
.015
.065
.022
.430
15
7.87
6.35
26.24
3.30
0.29
1.52
0.46
9.40
10
8.26
6.60
26.42
3.56
0.38
1.65
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-019
DS41140C-page 96
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
APPENDIX A: CODE FOR LIN
COMMUNICATION
Please check our web site at www.microchip.com for
code availability.
APPENDIX B: REVISION HISTORY
Revision C (January 2013)
Added a note to each package outline drawing.
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 97
PIC16C432
NOTES:
DS41140C-page 98
Preliminary
2000-2013 Microchip Technology Inc.
PIC16C432
BCF ............................................................................ 63
BSF............................................................................. 63
BTFSC........................................................................ 63
BTFSS........................................................................ 64
CALL........................................................................... 64
CLRF .......................................................................... 64
CLRW......................................................................... 65
CLRWDT .................................................................... 65
COMF......................................................................... 65
DECF.......................................................................... 65
DECFSZ ..................................................................... 66
GOTO......................................................................... 66
INCF ........................................................................... 66
INCFSZ....................................................................... 67
IORLW ........................................................................ 67
IORWF........................................................................ 67
MOVF ......................................................................... 68
MOVLW ...................................................................... 68
MOVWF...................................................................... 68
NOP............................................................................ 68
OPTION...................................................................... 69
RETFIE....................................................................... 69
RETLW ....................................................................... 69
RETURN..................................................................... 69
RLF............................................................................. 70
RRF ............................................................................ 70
SLEEP........................................................................ 70
SUBLW....................................................................... 71
SUBWF....................................................................... 71
SWAPF....................................................................... 72
TRIS ........................................................................... 72
XORLW....................................................................... 72
XORWF ...................................................................... 72
Instruction Set Summary .................................................... 59
INT Interrupt ....................................................................... 54
INTCON Register................................................................ 12
Interrupts ............................................................................ 53
IORLW Instruction .............................................................. 67
IORWF Instruction .............................................................. 67
INDEX
A
ADDLW Instruction ............................................................. 62
ADDWF Instruction ............................................................. 62
ANDLW Instruction ............................................................. 62
ANDWF Instruction ............................................................. 62
Assembler
MPASM Assembler ..................................................... 73
B
BCF Instruction ................................................................... 63
Block Diagram
TIMER0....................................................................... 27
TMR0/WDT PRESCALER .......................................... 30
Brown-out Detect (BOD) ..................................................... 48
BSF Instruction ................................................................... 63
BTFSC Instruction............................................................... 63
BTFSS Instruction............................................................... 64
C
CALL Instruction ................................................................. 64
CLRF Instruction................................................................. 64
CLRW Instruction................................................................ 65
CLRWDT Instruction ........................................................... 65
CMCON Register................................................................ 33
Code Protection .................................................................. 58
COMF Instruction................................................................ 65
Comparator Configuration................................................... 33
Comparator Interrupts......................................................... 39
Comparator Module ............................................................ 33
Comparator Operation ........................................................ 35
Comparator Reference ....................................................... 35
Configuration Bits................................................................ 43
Configuring the Voltage Reference..................................... 41
Crystal Operation ................................................................ 45
D
Data Memory Organization ................................................... 7
DECF Instruction................................................................. 65
DECFSZ Instruction ............................................................ 66
Development Support ......................................................... 73
K
KEELOQ Evaluation and Programming Tools...................... 76
L
E
LIN Hardware Interface....................................................... 23
LIN Interfacing .................................................................... 23
LIN Protocol........................................................................ 23
LIN Transceiver .................................................................. 23
Errata .................................................................................... 2
External Crystal Oscillator Circuit ....................................... 46
G
General Purpose Register File.............................................. 7
GOTO Instruction................................................................ 66
M
MOVF Instruction................................................................ 68
MOVLW Instruction............................................................. 68
MOVWF Instruction ............................................................ 68
MPLAB C17 and MPLAB C18 C Compilers ....................... 73
MPLAB ICD In-Circuit Debugger ........................................ 75
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE ................................................................. 74
MPLAB Integrated Development Environment Software.... 73
MPLINK Object Linker/MPLIB Object Librarian.................. 74
I
I/O Ports.............................................................................. 17
I/O Programming Considerations........................................ 22
ICEPIC In-Circuit Emulator ................................................. 74
ID Locations........................................................................ 58
INCF Instruction .................................................................. 66
INCFSZ Instruction ............................................................. 67
In-Circuit Serial Programming............................................. 58
Indirect Addressing, INDF and FSR Registers ................... 16
Instruction Set
N
NOP Instruction .................................................................. 68
ADDLW ....................................................................... 62
ADDWF....................................................................... 62
ANDLW ....................................................................... 62
ANDWF....................................................................... 62
O
One-Time-Programmable (OTP) Devices ............................ 5
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 99
PIC16C432
OPTION Instruction.............................................................69
OPTION Register................................................................11
Oscillator Configurations.....................................................45
Oscillator Start-up Timer (OST) ..........................................48
Switching Prescaler Assignment ................................ 31
Timing Diagrams and Specifications .................................. 86
TMR0 Interrupt.................................................................... 54
TRIS Instruction.................................................................. 72
TRISA ................................................................................. 17
TRISB ................................................................................. 20
P
Package Marking Information .............................................93
Packaging Information ........................................................93
PCL and PCLATH...............................................................15
PCON Register ...................................................................14
PICDEM 1 Low Cost PIC MCU Demonstration Board........75
PICDEM 17 Demonstration Board ......................................76
PICDEM 2 Low Cost PIC16CXX Demonstration Board......75
PICDEM 3 Low Cost PIC16CXXX Demonstration Board ...76
PICSTART Plus Entry Level Development Programmer ....75
PIE1 Register......................................................................13
PIR1 Register......................................................................13
Port RB Interrupt .................................................................54
PORTA................................................................................17
PORTB................................................................................20
Power Control/Status Register (PCON)..............................49
Power-down Mode (SLEEP) ...............................................57
Power-on Reset (POR) .......................................................48
Timeout (TO Bit)..........................................................10
Power-up Timer (PWRT).....................................................48
Prescaler.............................................................................30
Program Memory Organization.............................................7
V
Voltage Reference Module ................................................. 41
VRCON Register ................................................................ 41
W
Watchdog Timer (WDT)...................................................... 56
WWW, On-Line Support ....................................................... 2
X
XORLW Instruction............................................................. 72
XORWF Instruction............................................................. 72
Q
Quick-Turn-Programming (QTP) Devices.............................5
R
RC Oscillator.......................................................................46
RESET ................................................................................47
RETFIE Instruction..............................................................69
RETLW Instruction..............................................................69
RETURN Instruction............................................................69
RLF Instruction....................................................................70
RRF Instruction ...................................................................70
S
Serialized Quick-Turn-Programming (SQTP) Devices..........5
SLEEP Instruction...............................................................70
Software Simulator (MPLAB SIM).......................................74
Special Features of the CPU...............................................43
Special Function Registers ...................................................8
Stack ...................................................................................15
STATUS Register
DC Bit..........................................................................10
IRP Bit.........................................................................10
TO Bit..........................................................................10
Z Bit.............................................................................10
Status Register....................................................................10
SUBLW Instruction..............................................................71
SUBWF Instruction..............................................................71
SWAPF Instruction..............................................................72
T
Thermal Shutdown..............................................................23
Timer0
TIMER0.......................................................................27
TIMER0 (TMR0) Interrupt ...........................................27
TIMER0 (TMR0) Module.............................................27
TMR0 with External Clock...........................................29
Timer1
DS41140C-page 100
Preliminary
2000-2013 Microchip Technology Inc.
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the web site
at: http://microchip.com/support
• Business of Microchip – Product selector and
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listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2000-2013 Microchip Technology Inc.
DS41140C-page 101
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
RE:
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Reader Response
Total Pages Sent ________
From:
Name
Company
Address
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Literature Number: DS41140C
Application (optional):
Would you like a reply?
Y
N
Device:
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS41140C-page 102
2000-2013 Microchip Technology Inc.
PIC16C432
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC16C432-E/P301 = Extra Temp, PDIP pack-
age, 4 MHz, normal VDD limits, QTP pattern
#301
b)
PIC16C432-I/SS Industrial Temp., SSOP pack-
age, 4 MHz, industrial VDD limits
Device
PIC16C432: VDD range 4.0 V to 5.5 V
PIC16C432T: VDD range 4.0 V to 5.5 V (Tape and Reel)
Temperature Range
Package
I
E
=
=
-40C to +85C
-40C to
+125C
SS
=
SSOP
JW* =
Windowed CERDIP
Pattern
3-Digit Pattern Code for QTP (blank otherwise).
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Worldwide Site (www.microchip.com)
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page103
PIC16C432
DS41140C-page 104
Preliminary
2000-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2000-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769720
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2000-2013 Microchip Technology Inc.
Preliminary
DS41140C-page 105
Worldwide Sales and Service
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11/29/12
DS41140C-page 106
Preliminary
2000-2013 Microchip Technology Inc.
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