PIC16C505T-04I/P [MICROCHIP]
14-Pin, 8-Bit CMOS Microcontroller; 14引脚, 8位CMOS微控制器型号: | PIC16C505T-04I/P |
厂家: | MICROCHIP |
描述: | 14-Pin, 8-Bit CMOS Microcontroller |
文件: | 总80页 (文件大小:603K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16C505
14-Pin, 8-Bit CMOS Microcontroller
Device included in this Data Sheet:
PIC16C505
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
• Power-on Reset (POR)
High-Performance RISC CPU:
• Device Reset Timer (DRT)
• Only 33 instructions to learn
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
• Watchdog Timer (WDT) with dedicated on-chip
RC oscillator for reliable operation
• Programmable Code Protection
• Internal weak pull-ups on I/O pins
• Wake-up from Sleep on pin change
• Power-saving Sleep mode
Memory
Device
Program
Data
• Selectable oscillator options:
PIC16C505
1024 x 12
72 x 8
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
• Direct, indirect and relative addressing modes for
data and instructions
- XT:
- HS:
- LP:
Standard crystal/resonator
High speed crystal/resonator
• 12 bit wide instructions
• 8 bit wide data path
Power saving, low frequency
crystal
• 2-level deep hardware stack
• Eight special function hardware registers
CMOS Technology:
• Direct, indirect and relative addressing modes for
data and instructions
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• All single cycle instructions (200 ns) except for
program branches which are two-cycle
• Wide operating voltage range (2.5V to 5.5V)
Peripheral Features:
• Wide temperature ranges
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
• 11 I/O pins with individual direction control
• 1 input pin
• High current sink/source for direct LED drive
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
- Extended: -40˚C to +125˚C
- < 1.0 µA typical standby current @ 5V
• Low power consumption
- < 2.0 mA @ 5V, 4 MHz
- 15 µA typical @ 3.0V, 32 kHz for TMR0 run-
ning in SLEEP mode
FIGURE 1:
PIN DIAGRAM:
PDIP, SOIC, Ceramic Side Brazed
- < 1.0 µA typical standby current @ 5V
VDD
1
2
3
4
5
14
13
12
11
10
VSS
RB5/OSC1/CLKIN
RB0
RB1
RB2
RC0
RC1
RC2
RB4/OSC2/CLKOUT
RB3/MCLR/VPP
RC5/T0CKI
RC4
RC3
6
7
9
8
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 1
PIC16C505
TABLE OF CONTENTS
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
General Description..................................................................................................................................................................... 3
PIC16C505 Device Varieties....................................................................................................................................................... 5
Architectural Overview ................................................................................................................................................................ 7
Memory Organization................................................................................................................................................................ 11
I/O Port...................................................................................................................................................................................... 19
Timer0 Module and TMR0 Register .......................................................................................................................................... 23
Special Features of the CPU..................................................................................................................................................... 27
Instruction Set Summary........................................................................................................................................................... 39
Development Support................................................................................................................................................................ 51
10.0 Electrical Characteristics - PIC16C505 ..................................................................................................................................... 55
11.0 DC and AC Characteristics - PIC16C505.................................................................................................................................. 65
12.0 Packaging Information............................................................................................................................................................... 69
INDEX .................................................................................................................................................................................................. 73
PIC16C505 Product Identification System........................................................................................................................................... 77
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
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DS40192A-page 2
Preliminary
1998 Microchip Technology Inc.
PIC16C505
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC16C505 from Microchip Technology is a low-
cost, high performance, 8-bit, fully static, EPROM/
ROM-based CMOS microcontroller. It employs a RISC
architecture with only 33 single word/single cycle
instructions. All instructions are single cycle (1 µs)
except for program branches which take two cycles.
The PIC16C505 delivers performance an order of mag-
nitude higher than its competitors in the same price cat-
egory. The 12-bit wide instructions are highly
symmetrical resulting in 2:1 code compression over
other 8-bit microcontrollers in its class.The easy to use
and easy to remember instruction set reduces
development time significantly.
The PIC16C505 fits perfectly in applications ranging
from personal care appliances and security systems to
low-power remote transmitters/receivers. The EPROM
technology makes customizing application programs
(transmitter codes, appliance settings, receiver fre-
quencies, etc.) extremely fast and convenient. The
small footprint packages, for through hole or surface
mounting, make this microcontroller perfect for applica-
tions with space limitations. Low-cost, low-power, high
performance, ease of use and I/O flexibility make the
PIC16C505 very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic and PLD’s
in larger systems, coprocessor applications).
The PIC16C505 product is equipped with special fea-
tures that reduce system cost and power requirements.
The Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are five oscillator configurations to choose from,
including INTRC internal oscillator mode and the
power-saving LP (Low Power) oscillator. Power saving
SLEEP mode, Watchdog Timer and code protection
features improve system cost, power and reliability.
The PIC16C505 is available in the cost-effective One-
Time-Programmable (OTP) version, which is suitable
for production in any volume. The customer can take
full advantage of Microchip’s price leadership in OTP
microcontrollers while benefiting from the OTP’s
flexibility.
The PIC16C505 product is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a ‘C’ compiler, a low-cost development pro-
grammer, and a full featured programmer. All the tools
are supported on IBM PC and compatible machines.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 3
PIC16C505
TABLE 1-1:
PIC16C505 DEVICE
PIC16C505
Maximum Frequency
of Operation (MHz)
20
Clock
EPROM Program Memory
Data Memory (bytes)
Timer Module(s)
1024
72
Memory
TMR0
Yes
Peripherals
Features
Wake-up from SLEEP on
pin change
I/O Pins
11
Input Pins
1
Internal Pull-ups
In-Circuit Serial Programming
Number of Instructions
Packages
Yes
Yes
33
14-pin DIP, SOIC, JW
The PIC16C505 device has Power-on Reset, selectable Watchdog Timer, selectable code protect,
high I/O current capability and precision internal oscillator.
The PIC16C505 device uses serial programming with data pin RB0 and clock pin RB1.
DS40192A-page 4
Preliminary
1998 Microchip Technology Inc.
PIC16C505
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC16C505 DEVICE VARIETIES
A
variety of packaging options are available.
Depending on application and production
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and fuse
options already programmed by the factory. Certain
code and prototype verification procedures do apply
before production shipments are available. Please con-
tact your local Microchip Technology sales office for
more details.
requirements, the proper device option can be
selected using the information in this section. When
placing orders, please use the PIC16C505 Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in ceramic side
brazed package, is optimal for prototype development
and pilot programs.
The UV erasable version can be erased and
reprogrammed to any of the configuration modes.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be saved prior
to erasing the part.
Microchip offers a unique programming service where
few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
a
Microchip's PICSTART PLUS and PRO MATE pro-
grammers all support programming of the PIC16C505.
Third party programmers also are available; refer to the
Microchip Third Party Guide for a list of sources.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates or small volume applications.
The OTP devices, packaged in plastic packages permit
the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 5
PIC16C505
NOTES:
DS40192A-page 6
Preliminary
1998 Microchip Technology Inc.
PIC16C505
The PIC16C505 device contains an 8-bit ALU and
3.0
ARCHITECTURAL OVERVIEW
working register. The ALU is
a general purpose
The high performance of the PIC16C505 can be
attributed to number of architectural features
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
a
commonly found in RISC microprocessors. To begin
with, the PIC16C505 uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide, making it possible to have
all single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
execution of instructions. Consequently, all instructions
(33) execute in a single cycle (200ns @ 20MHz)
except for program branches.
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is either a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWFand ADDWF
instructions for examples.
The PIC16C505 addresses 1K x 12 of program
memory. All program memory is internal.
The PIC16C505 can directly or indirectly address its
register files and data memory. All special function
registers, including the program counter, are mapped
in the data memory. The PIC16C505 has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C505 simple yet efficient.
In addition, the learning curve is reduced significantly.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 7
PIC16C505
FIGURE 3-1: PIC16C505 BLOCK DIAGRAM
12
8
PORTB
PORTC
Data Bus
RAM
Program Counter
EPROM
1K x 12
Program
Memory
RB0
RB1
RB2
STACK1
RB3/MCLR/Vpp
RB4/OSC2/CLKOUT
RB5/OSC1/CLKIN
File
STACK2
Registers
Program
12
RAM Addr
Bus
9
Addr MUX
Instruction reg
RC0
RC1
RC2
Indirect
Addr
5
Direct Addr
5-7
RC3
RC4
FSR reg
RC5/T0CKI
STATUS reg
8
3
MUX
Device Reset
Timer
Power-on
Reset
ALU
Instruction
Decode &
Control
8
Watchdog
Timer
W reg
Timing
Generation
OSC1/CLKIN
OSC2
Internal RC
OSC
Timer0
MCLR
Vdd, Vss
DS40192A-page 8
Preliminary
1998 Microchip Technology Inc.
PIC16C505
TABLE 3-1:
Name
PIC16C505 PINOUT DESCRIPTION
DIP
SOIC
Pin #
I/O/P
Type
Buffer
Type
Description
Pin #
RB0
13
13
I/O
TTL/ST Bi-directional I/O port/ serial programming data. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
RB1
12
12
I/O
TTL/ST Bi-directional I/O port/ serial programming clock. Can
be software programmed for internal weak pull-up and
wake-up from SLEEP on pin change. This buffer is a
Schmitt Trigger input when used in serial programming
mode.
RB2
11
10
9
11
10
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
TTL
TTL
TTL
TTL
TTL
TTL
ST
Bi-directional I/O port.
RC0
Bi-directional I/O port.
RC1
Bi-directional I/O port.
RC2
8
8
Bi-directional I/O port.
RC3
7
7
Bi-directional I/O port.
RC4
6
6
Bi-directional I/O port.
RC5/T0CKI
RB3/MCLR/VPP
5
5
Bi-directional I/O port. Can be configured as T0CKI.
4
4
TTL
Input port/master clear (reset) input/programming volt-
age input. When configured as MCLR, this pin is an
active low reset to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. Weak pull-
up only when configured as RB3.
RB4/OSC2/CLKOUT
3
3
I/O
TTL
Bi-directional I/O port/oscillator crystal output. Con-
nections to crystal or resonator in crystal oscillator
mode (XT and LP modes only, RB4 in other modes).
Can be software programmed for internal weak pull-up
and wake-up from SLEEP on pin change. In EXTRC
and INTRC modes, the pin output can be configured to
CLKOUT, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
RB5/OSC1/CLKIN
2
2
I/O
TTL/ST Bidirectional IO port/oscillator crystal input/external
clock source input (RB5 in Internal RC mode only,
OSC1 in all other oscillator modes). TTL input when
RB5, ST input in external RC oscillator mode.
VDD
VSS
1
1
P
P
—
—
Positive supply for logic and I/O pins
Ground reference for logic and I/O pins
14
14
Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,
ST = Schmitt Trigger input
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 9
PIC16C505
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter is incremented every Q1, and the
instruction is fetched from program memory and
latched into instruction register in Q4. It is decoded
and executed during the following Q1 through Q4. The
clocks and instruction execution flow is shown in
Figure 3-2 and Example 3-1.
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 03H
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTB, BIT1
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40192A-page 10
Preliminary
1998 Microchip Technology Inc.
PIC16C505
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
4.0
MEMORY ORGANIZATION
PIC16C505 memory is organized into program mem-
ory and data memory. For the PIC16C505, a paging
scheme is used. Program memory pages are accessed
using one STATUS register bit. Data memory banks
are accessed using the File Select Register (FSR).
PIC16C505
PC<11:0>
12
CALL, RETLW
Stack Level 1
Stack Level 2
4.1
Program Memory Organization
The PIC16C505 devices have
Counter (PC).
a 12-bit Program
Reset Vector (note 1)
0000h
The 1K x 12 (0000h-03FFh) for the PIC16C505 are
physically implemented. Refer to Figure 4-1.
Accessing a location above this boundary will cause a
wrap-around within the first 1K x 12 space. The
effective reset vector is at 0000h, (see Figure 4-1).
Location 03FFh (PIC16C505) contains the internal
clock oscillator calibration value. This value should
never be overwritten.
01FFh
0200h
On-chip Program
Memory
1024 Word
03FFh
0400h
7FFh
Note 1: Address 0000h becomes the
effective reset vector. Location
03FFh (PIC16C505) contains the
MOVLW XXINTERNAL RC oscillator
calibration value.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 11
PIC16C505
For the PIC16C505, the register file is composed of 8
special function registers, 24 general purpose
registers, and 48 general purpose registers that may
be addressed using a banking scheme (Figure 4-2).
4.2
Data Memory Organization
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
4.2.1
GENERAL PURPOSE REGISTER FILE
The general purpose register file is accessed either
directly or indirectly through the file select register
FSR (Section 4.8).
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
The general purpose registers are used for data and
control information under command of the instructions.
FIGURE 4-2: PIC16C505 REGISTER FILE MAP
FSR<6:5>
00
01
10
11
File Address
00h
INDF(1)
TMR0
20h
40h
60h
01h
02h
03h
04h
05h
06h
PCL
Addresses map back to
addresses in Bank 0.
STATUS
FSR
OSCCAL
PORTB
PORTC
07h
08h
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
70h
10h
1Fh
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
5Fh
7Fh
Bank 1
Bank 2
Bank 3
Bank 0
Note 1: Not a physical register.
DS40192A-page 12
Preliminary
1998 Microchip Technology Inc.
PIC16C505
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral functions to control
the operation of the device (Table 4-1).
TABLE 4-1:
SPECIAL FUNCTION REGISTER (SFR) SUMMARY
Value on
Power-On
Reset
Value on
MCLR and Wake-up on
WDT Reset Pin Change
Value on
Address
Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2 Bit 1 Bit 0
xxxx xxxx uuuu uuuu uuuu uuuu
xxxx xxxx uuuu uuuu uuuu uuuu
00h
01h
INDF
TMR0
PCL
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
02h(1)
03h
04h
05h
N/A
N/A
N/A
06h
07h
Low order 8 bits of PC
1111 1111 1111 1111 1111 1111
0001 1xxx 000q quuu 100q quuu
110x xxxx 11uu uuuu 11uu uuuu
1000 00-- uuuu uu-- uuuu uu--
--11 1111 --11 1111 --11 1111
--11 1111 --11 1111 --11 1111
1111 1111 1111 1111 1111 1111
--xxxxxx --uu uuuu --uu uuuu
--xx xxxx --uu uuuu --uu uuuu
STATUS
FSR
RBWUF
—
PAO
TO
PD
Z
DC
—
C
Indirect data memory address pointer
OSCCAL
TRISB
CAL5
—
CAL4
—
CAL3
CAL2
CAL1
CAL0
—
I/O control registers
I/O control registers
TRISC
—
—
OPTION
PORTB
PORTC
RBWU RBPU TOCS TOSE
PSA
RB3
RC3
PS2
RB2
RC2
PS1 PS0
RB1 RB0
RC1 RC0
—
—
—
—
RB5
RC5
RB4
RC4
Legend: Shaded cellls not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 13
PIC16C505
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bit.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions, which do affect STATUS bits, see
Instruction Set Summary.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction with
the STATUS register as destination may be different
than intended.
FIGURE 4-3: STATUS REGISTER (ADDRESS:03h)
R/W-0
RBWUF
R/W-0
—
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
6
5
4
3
2
1
bit0
bit 7:
RBWUF: IO reset bit
1 = Reset due to wake-up from SLEEP on pin change
0 = After power up or other reset
bit 6:
bit 5:
Unimplemented
PA0: Program page preselect bits
1 = Page 1 (200h - 3FFh)
0 = Page 0 (000h - 1FFh)
Each page is 512 bytes.
Using the PA0 bit as a general purpose read/write bit in devices which do not use it for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF
SUBWF
RRF or RLF
1 = A carry occurred
0 = A carry did not occur
1 = A borrow did not occur
0 = A borrow occurred
Load bit with LSB or MSB, respectively
DS40192A-page 14
Preliminary
1998 Microchip Technology Inc.
PIC16C505
4.4
OPTION Register
Note: If TRIS bit is set to ‘0’, the wake-up on
change and pull-up functions are disabled
for that pin; i.e., note that TRIS overrides
OPTION control of RBPU and RBWU.
The OPTION register is
register which contains various control bits to
configure the Timer0/WDT prescaler and Timer0.
a
8-bit wide, write-only
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<7:0> bits.
FIGURE 4-4: OPTION REGISTER
W-1
W-1
RBPU
6
W-1
T0CS
5
W-1
T0SE
4
W-1
PSA
3
W-1
PS2
2
W-1
PS1
1
W-1
PS0
RBWU
W
U
= Writable bit
= Unimplemented bit
bit7
bit0
- n = Value at POR reset
Reference Table 4-1 for
other resets.
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
RBWU: Enable wake-up on pin change (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
RBPU: Enable weak pull-ups (RB0, RB1, RB3, RB4)
1 = Disabled
0 = Enabled
T0CS: Timer0 clock source select bit
1 = Transition on T0CKI pin
0 = Transition on internal instruction cycle clock, Fosc/4
T0SE: Timer0 source edge select bit
1 = Increment on high to low transition on the T0CKI pin
0 = Increment on low to high transition on the T0CKI pin
PSA: Prescaler assignment bit
1 = Prescaler assigned to the WDT
0 = Prescaler assigned to Timer0
bit 2-0: PS2:PS0: Prescaler rate select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 15
PIC16C505
4.5
OSCCAL Register
The Oscillator Calibration (OSCCAL) register is used to
calibrate the internal 4 MHz oscillator. It contains six
bits for fine calibration.
FIGURE 4-5: OSCCAL REGISTER (ADDRESS 05h)PIC16C505
R/W-1
CAL5
R/W-0
CAL4
R/W-0
CAL3
R/W-0
CAL2
R/W-0
CAL1
R/W-0
CAL0
U-0
—
U-0
—
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-4: CAL<5:0>: Fine calibration
DS40192A-page 16
Preliminary
1998 Microchip Technology Inc.
PIC16C505
4.6.1
EFFECTS OF RESET
4.6
Program Counter
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 4-
6).
Therefore, upon a RESET, a GOTO instruction will
automatically cause the program to jump to page 0
until the value of the page bits is altered.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-6).
4.7
Stack
PIC16C505 devices have a 12-bit wide hardware
push/pop stack.
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC,and BSF PC,5.
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
Note: Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
A RETLWinstruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
FIGURE 4-6: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C505
GOTO Instruction
11
10
9
8
7
0
PC
PCL
Instruction Word
0
PA0
7
STATUS
CALL or Modify PCL Instruction
11
10
9
8
7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA0
7
0
STATUS
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 17
PIC16C505
4.8
Indirect Data Addressing; INDF and
FSR Registers
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
The INDF register is not
a physical register.
movlw 0x10
;initialize pointer
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
movwf FSR
; to RAM
;clear INDF register
NEXT
clrf
incf
INDF
FSR,F ;inc pointer
btfsc FSR,4 ;all done?
goto
NEXT
;NO, clear next
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 07 contains the value 10h
• Register file 08 contains the value 0Ah
• Load the value 07 into the FSR register
• A read of the INDF register will return the value
of 10h
CONTINUE
:
;YES, continue
The FSR is
a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
• Increment the value of the FSR register by one
(FSR = 08)
• A read of the INDR register now will return the
value of 0Ah.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
The device uses FSR6:5 to select between banks
0:3.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING
Direct Addressing
(FSR)
Indirect Addressing
6
5
4
(opcode)
0
6
5
4
(FSR)
0
bank
location select
bank select
location select
00
01
10
11
00h
Addresses
map back to
addresses
in Bank 0.
0Fh
10h
Data
Memory(1)
1Fh
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 0
Bank 3
Note 1: For register map detail see Section 4.2.
DS40192A-page 18
Preliminary
1998 Microchip Technology Inc.
PIC16C505
5.4
I/O Interfacing
5.0
I/O PORT
As with any other register, the I/O register can be
written and read under program control. However,
read instructions (e.g., MOVF PORTB,W) always read
the I/O pins independent of the pin’s input/output
modes. On RESET, all I/O ports are defined as input
(inputs are at hi-impedance) since the I/O control
registers are all set.
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All port pins, except RB3 which is input
only, may be used for both input and output
operations. For input operations these ports are non-
latching. Any input must be present until read by an
input instruction (e.g., MOVF PORTB,W). The outputs
are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the
corresponding direction control bit in TRIS must be
cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin (except RB3) can be
programmed individually as input or output.
5.1
PORTB
PORTB is an 8-bit I/O register. Only the low order 6
bits are used (RB5:RB0). Bits and are
7
6
unimplemented and read as '0's. Please note that RB3
is an input only pin. The configuration word can set
several I/O’s to alternate functions. When acting as
alternate functions the pins will read as ‘0’ during port
read. Pins RB0, RB1, RB3 and RB4 can be configured
with weak pull-ups and also with wake-up on change.
The wake-up on change and weak pull-up functions
are not pin selectable. If pin 4 is configured as MCLR,
weak pull-up is always off and wake-up on change for
this pin is not enabled.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
Data
Bus
D
Q
Q
Data
Latch
VDD
P
WR
Port
CK
5.2
PORTC
N
I/O
pin(1)
W
Reg
PORTC is an 8-bit I/O register. Only the low order 6
bits are used (RC5:RC0). Bits 7 and 6 are unimple-
mented and read as ‘0’s.
D
Q
Q
TRIS
Latch
VSS
TRIS ‘f’
CK
5.3
TRIS Registers
The output driver control register is loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer. The
exceptions are RB3 which is input only and RC5 which
may be controlled by the option register, see Figure 4-
4.
Reset
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 19
PIC16C505
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR and Wake-up on
WDT Reset Pin Change
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
--11 1111 --11 1111 --11 1111
--11 1111 --11 1111 --11 1111
1111 1111 1111 1111 1111 1111
0001 1xxx 000q quuu 100q quuu
--xxxxxx --uu uuuu --uu uuuu
--xx xxxx --uu uuuu --uu uuuu
N/A
N/A
N/A
03h
06h
07h
TRISB
—
—
—
—
I/O control registers
I/O control registers
TRISC
OPTION
STATUS
PORTB
PORTC
RBWU
RBWUF
—
RBPU
—
TOCS
PAO
TOSE
TO
PSA
PD
PS2
Z
PS1
DC
PS0
C
—
RB5
RB4
RC4
RB3
RC3
RB2
RC2
RB1
RB0
—
—
RC5
RC1 RC0
Legend: Shaded cellls not used by Port Registers, read as ‘0’, — = unimplemented, read as ‘0’, x = unknown, u = unchanged.
5.5
I/O Programming Considerations
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORTB Settings
; PORTB<5:3> Inputs
; PORTB<2:0> Outputs
;
5.5.1
BI-DIRECTIONAL I/O PORTS
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bi-
directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
;
;
PORTB latch PORTB pins
---------- ----------
BCF
BCF
MOVLW 007h
TRIS PORTB
PORTB, 5
PORTB, 4
;--01 -ppp
;--10 -ppp
;
--11 pppp
--11 pppp
;--10 -ppp
--11 pppp
;
;Note that the user may have expected the pin
;values to be --00 pppp. The 2nd BCF caused
;RB5 to be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an I/
O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-
and”). The resulting high output currents may damage
the chip.
DS40192A-page 20
Preliminary
1998 Microchip Technology Inc.
PIC16C505
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
This example shows
a write to PORTB
Instruction
fetched
followed by a read from PORTB.
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
MOVWF PORTB MOVF PORTB,W
RB5:RB0
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
executed
MOVWF PORTB MOVF PORTB,W
NOP
(Write to
PORTB)
(Read
PORTB)
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 21
PIC16C505
NOTES:
DS40192A-page 22
Preliminary
1998 Microchip Technology Inc.
PIC16C505
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
T0SE bit (OPTION<4>) determines the source edge.
Clearing the T0SE bit selects the rising edge.
Restrictions on the external clock input are discussed
in detail in Section 6.1.
6.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler may be used by either the Timer0
module or the Watchdog Timer, but not both. The
prescaler assignment is controlled in software by the
control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is
not readable or writable. When the prescaler is
assigned to the Timer0 module, prescale values of 1:2,
1:4,..., 1:256 are selectable. Section 6.2 details the
operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-2 and Figure 6-3).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data bus
RC5/T0CKI
Pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
Programmable
PSout
Sync
(2)
Prescaler
(2 cycle delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-5).
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 23
PIC16C505
FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on
Value on
Power-On
Reset
MCLR and Wake-up on
WDT Reset Pin Change
Address Name
Bit 7
Timer0 - 8-bit real-time clock/counter
OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
N/A
N/A
N/A
TMR0
xxxx xxxx uuuu uuuu
uuuu uuuu
1111 1111
TRISB
TRISC
I/O control registers
I/O control registers
--11 1111 --11 1111 --11 1111
--11 1111 --11 1111 --11 1111
Legend: Shaded cells not used by Timer0, -= unimplemented, x = unknown, u= unchanged,
DS40192A-page 24
Preliminary
1998 Microchip Technology Inc.
PIC16C505
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
6.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-4). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-4 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-4: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or
misses sampling
Prescaler Output (2)
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 25
PIC16C505
6.2
Prescaler
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0→WDT)
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 7.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
1.CLRWDT
2.CLRF
;Clear WDT
TMR0
;Clear TMR0 & Prescaler
3.MOVLW '00xx1111’b;;These 3 lines (5, 6, 7)
4.OPTION
; are required only if
; desired
;PS<2:0> are 000 or 001
5.CLRWDT
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION ; desired WDT rate
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDTinstruction should be executed before switching
the prescaler.
The PSA and PS2:PS0 bits (OPTION<3:0>)
determine prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x,etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
;prescaler
MOVLW 'xxxx0xxx'
;Select TMR0, new
;prescale value and
;clock source
6.2.1
SWITCHING PRESCALER ASSIGNMENT
OPTION
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
FIGURE 6-5: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = Fosc/4)
Data Bus
8
0
RC5/T0CKI
M
U
X
1
Pin
M
U
X
Sync
2
Cycles
1
TMR0 reg
0
T0SE
T0CS
PSA
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS40192A-page 26
Preliminary
1998 Microchip Technology Inc.
PIC16C505
The PIC16C505 has a Watchdog Timer which can be
shut off only through configuration bit WDTE. It runs
off of its own RC oscillator for added reliability. If using
HS, XT or LP selectable oscillator options, there is
always an 18 ms (nominal) delay provided by the
Device Reset Timer (DRT), intended to keep the chip
in reset until the crystal oscillator is stable. If using
INTRC or EXTRC there is an 18 ms delay only on VDD
power-up. With this timer on-chip, most applications
need no external reset circuitry.
7.0
SPECIAL FEATURES OF THE
CPU
What sets
a
microcontroller apart from other
processors are special circuits to deal with the needs
of real-time applications. The PIC16C505 family of
microcontrollers has a host of such features intended
to maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up
from SLEEP through a change on input pins or
through a Watchdog Timer time-out. Several oscillator
options are also made available to allow the part to fit
the application, including an internal 4 MHz oscillator.
The EXTRC oscillator option saves system cost while
• Oscillator selection
• Reset
- Power-On Reset (POR)
- Device Reset Timer (DRT)
- Wake-up from SLEEP on pin change
• Watchdog Timer (WDT)
• SLEEP
the LP crystal option saves power.
A set of
configuration bits are used to select various options.
• Code protection
7.1
Configuration Bits
• ID locations
• In-circuit Serial Programming
• Clock Out
The PIC16C505 configuration word consists of 6 bits.
Configuration bits can be programmed to select
various device configurations. Three bits are for the
selection of the oscillator type, one bit is the Watchdog
Timer enable bit, and one bit is the MCLR enable bit.
One bit is the code protection bit (Figure 7-1).
FIGURE 7-1: CONFIGURATION WORD FOR PIC16C505
CP
CP
10
CP
9
CP
8
CP
7
CP MCLRE CP
WDTE FOSC2 FOSC1 FOSC0
bit0
Register: CONFIG
(2)
Address
:
0FFFh
bit11
6
5
4
3
2
1
(1)(2)
bit 11-6, 4: CP Code Protection bits
bit 5:
bit 3:
MCLRE: RB3/MCLR pin function select
1 = RB3/MCLR pin function is MCLR
0 = RB3/MCLR pin function is digital I/O, MCLR internally tied to VDD
WDTE: Watchdog timer enable bit
1 = WDT enabled
0 = WDT disabled
bit 2-0: FOSC1:FOSC0: Oscillator Selection bits
111 = external RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
110 = external RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
101 = internal RC oscillator/CLKOUT function on RB4/OSC2/CLKOUT pin
100 = internal RC oscillator/RB4 function on RB4/OSC2/CLKOUT pin
011 = invalid selection
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 1: 03FFh is always uncodeprtotected on the PIC16C505. This location contains the
MOVLWxx calibration instruction for the INTRC.
Note 2: Refer to the PIC16C505 Programming Specifications to determine how to access the con-
figuration word. This register is not user addressable during device operation.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 27
PIC16C505
7.2
Oscillator Configurations
OSCILLATOR TYPES
TABLE 7-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16C505
7.2.1
The PIC16C505 can be operated in four different
oscillator modes. The user can program three
configuration bits (FOSC2:FOSC0) to select one of
these four modes:
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
XT
HS
4.0 MHz
16 MHz
30 pF
30 pF
10-47 pF
10-47 pF
• LP:
• XT:
• HS:
Low Power Crystal
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
Crystal/Resonator
High Speed Crystal/Resonator
• INTRC: Internal 4 MHz Oscillator
• EXTRC: External Resistor/Capacitor
TABLE 7-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC16C505
7.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Osc
Resonator Cap.Range Cap. Range
In HS, XT or LP modes, a crystal or ceramic resonator
is connected to the RB5/OSC1/CLKIN and RB4/
OSC2/CLKOUT pins to establish oscillation (Figure 7-
2). The PIC16C505 oscillator design requires the use
of a parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in HS, XT or LP modes, the
device can have an external clock source drive the
RB5/OSC1/CLKIN pin (Figure 7-3).
Type
Freq
C1
C2
(1)
LP
XT
32 kHz
15 pF
15 pF
200 kHz
1 MHz
4 MHz
47-68 pF
15 pF
15 pF
47-68 pF
15 pF
15 pF
HS
20 MHz
15-47 pF
15-47 pF
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in XT mode to avoid overdriving crystals
with low drive level specification. Since each crystal
has its own characteristics, the user should consult
the crystal manufacturer for appropriate values of
external components.
FIGURE 7-2: CRYSTAL OPERATION (OR
CERAMIC RESONATOR) (HS,
XT OR LP OSC
CONFIGURATION)
(1)
C1
OSC1
PIC16C505
SLEEP
XTAL
(3)
RF
To internal
logic
OSC2
(2)
RS
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 7-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16C505
Open
DS40192A-page 28
Preliminary
1998 Microchip Technology Inc.
PIC16C505
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
7.2.4
EXTERNAL RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-4 shows implementation of
a
parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
Figure 7-6 shows how the R/C combination is
connected to the PIC16C505. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
FIGURE 7-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
PIC16C505
4.7k
74AS04
CLKIN
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC frequency
more).
10k
XTAL
10k
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
20 pF
20 pF
Figure 7-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 7-6: EXTERNAL RC OSCILLATOR
MODE
VDD
Rext
Internal
FIGURE 7-5: EXTERNAL SERIES
RESONANT CRYSTAL
clock
OSC1
N
OSCILLATOR CIRCUIT
To Other
Devices
Cext
VSS
PIC16C505
330
330
74AS04
74AS04
74AS04
PIC16C505
OSC2/CLKOUT
FOSC/4
CLKIN
0.1 µF
XTAL
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 29
PIC16C505
7.2.5
INTERNAL 4 MHz RC OSCILLATOR
The internal RC oscillator provides a fixed 4 MHz (nom-
inal) system clock at VDD = 5V and 25°C, see “Electri-
cal Specifications” section for information on variation
over voltage and temperature..
In addition, a calibration instruction is programmed into
the last address of memory which contains the calibra-
tion value for the internal RC oscillator. This location is
always uncode protected regardless of the code pro-
tect settings. This value is programmed as a MOVLW XX
instruction where XX is the calibration value, and is
placed at the reset vector. This will load the W register
with the calibration value upon reset and the PC will
then roll over to the users program at address 0x000.
The user then has the option of writing the value to the
OSCCAL Register (05h) or ignoring it.
OSCCAL, when written to with the calibration value, will
“trim” the internal oscillator to remove process variation
from the oscillator frequency. .
Note: Please note that erasing the device will
also erase the pre-programmed internal
calibration value for the internal oscillator.
The calibration value must be read prior to
erasing the part. so it can be repro-
grammed correctly later.
For the PIC16C505, only bits <7:2> of OSCCAL are
implemented.
7.3
RESET
The device differentiates between various kinds of
reset:
a) Power on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT time-out reset during normal operation
e) WDT time-out reset during SLEEP
f) Wake-up from SLEEP on pin change
Some registers are not reset in any way; they are
unknown on POR and unchanged in any other reset.
Most other registers are reset to “reset state” on power-
on reset (POR), on MCLR, WDT or wake-up on pin
change reset during normal operation. They are not
affected by a WDT reset during SLEEP or MCLR reset
during SLEEP, since these resets are viewed as
resumption of normal operation. The exceptions to this
are TO, PD, and RBWUF bits. They are set or cleared
differently in different reset situations. These bits are
used in software to determine the nature of reset. See
Table 7-3 for a full description of reset states of all
registers.
DS40192A-page 30
Preliminary
1998 Microchip Technology Inc.
PIC16C505
TABLE 7-3:
RESET CONDITIONS FOR REGISTERS
MCLR Reset
WDT time-out
Register
Address
Power-on Reset
Wake-up on Pin Change
W
—
qqqq xxxx (1)
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
110x xxxx
1000 00--
--xx xxxxx
--xx xxxxx
1111 1111
--11 1111
--11 1111
qqqq uuuu (1)
uuuu uuuu
uuuu uuuu
1111 1111
?00? ?uuu (2)
11uu uuuu
uuuu uu--
--uu uuuu
--uu uuuu
1111 1111
--11 1111
--11 1111
INDF
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
—
PC
STATUS
FSR
OSCCAL
PORTB
PORTC
OPTION
TRISB
TRISC
—
—
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’, ?= value depends on condition.
Note 1:
Note 2:
Bits <7:4> of W register contain oscillator calibration values due to MOVLW XXinstruction at top of memory.
See Table 7-7 for reset value for specific conditions
TABLE 7-4:
RESET CONDITION FOR SPECIAL REGISTERS
STATUS Addr: 03h
PCL Addr: 02h
Power on reset
0001 1xxx
000u uuuu
0001 0uuuu
0000 0uuu
0000 1uuu
1001 0uuu
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset during SLEEP
WDT reset normal operation
Wake-up from SLEEP on pin change
Legend: u= unchanged, x= unknown, -= unimplemented bit, read as ‘0’.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 31
PIC16C505
7.3.1
MCLR ENABLE
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
VDD, and the pin is assigned to be a I/O. See Figure 7-
7.
FIGURE 7-7: MCLR SELECT
A power-up example where MCLR is held low is
shown in Figure 7-9. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
RBWU
MCLRE
In Figure 7-10, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together or the
pin is programmed to be RB3.). The VDD is stable
before the start-up timer times out and there is no
problem in getting a proper reset. However, Figure 7-
11 depicts a problem situation where VDD rises too
slowly. The time between when the DRT senses that
MCLR is high and when MCLR (and VDD) actually
reach their full value, is too long. In this situation, when
the start-up timer times out, VDD has not reached the
VDD (min) value and the chip is, therefore, not
guaranteed to function correctly. For such situations,
we recommend that external RC circuits be used to
achieve longer POR delay times (Figure 7-10).
WEAK
PULL-UP
INTERNAL MCLR
RB3/MCLR/VPP
7.4
Power-On Reset (POR)
The PIC16C505 family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
reset for most power-up situations.
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 2.3V - 2.8V). To
take advantage of the internal POR, program the RB3/
MCLR/VPP pin as MCLR and tie directly to VDD or pro-
gram the pin as RB3. An internal weak pull-up resistor
is implemented using a transistor. Refer to Table 10-6
for the pull-up resistor ranges. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
Note: When the device starts normal operation
(exits the reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
For additional information refer to Application Notes
“Power-Up Considerations” - AN522 and “Power-up
Trouble Shooting” - AN607.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-8.
DS40192A-page 32
Preliminary
1998 Microchip Technology Inc.
PIC16C505
FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
Pin Change
SLEEP
POR (Power-On Reset)
VDD
Wake-up on
pin change
RB3/MCLR/VPP
WDT Time-out
MCLRE
RESET
S
R
Q
Q
8-bit Asynch
On-Chip
DRT OSC
Ripple Counter
(Start-Up Timer)
CHIP RESET
FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR PULLED LOW)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 33
PIC16C505
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
7.5
Device Reset Timer (DRT)
7.6
Watchdog Timer (WDT)
In the PIC16C505, the DRT runs any time the device is
powered up. DRT runs from RESET and varies based
on oscillator selection (see Table 7-5.)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the RB5/OSC1/CLKIN pin
and the internal 4 MHz oscillator. That means that the
WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or SLEEP, a WDT
reset or wake-up reset generates a device RESET.
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer reset.
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET condition for approximately 18
ms after MCLR has reached a logic high (VIHMCLR)
level. Thus, programming RB3/MCLR/VPP as MCLR
and using an external RC network connected to the
MCLR input is not required in most cases, allowing for
savings in cost-sensitive and/or space restricted
applications, as well as allowing the use of the RB3/
MCLR/VPP pin as a general purpose input.
The WDT can be permanently disabled by
programming the configuration bit WDTE as a '0'
(Section 7.1). Refer to the PIC16C505 Programming
Specifications to determine how to access the
configuration word.
TABLE 7-5:
DRT (DEVICE RESET TIMER
PERIOD)
Oscillator
Configuration
Subsequent
POR Reset
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
Resets
IntRC &
ExtRC
18 ms (typical)
300 µs (typi-
cal)
The DRT will also be triggered upon a Watchdog Timer
time-out (only in HS, XT and LP modes). This is
particularly important for applications using the WDT
to wake from SLEEP mode automatically.
HS, XT & LP
18 ms (typical) 18 ms (typical)
DS40192A-page 34
Preliminary
1998 Microchip Technology Inc.
PIC16C505
7.6.1
WDT PERIOD
7.6.2
WDT PROGRAMMING CONSIDERATIONS
The WDT has a nominal time-out period of 18 ms,
(with no prescaler). If a longer time-out period is
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT (under software control)
by writing to the OPTION register. Thus, a time-out
period of a nominal 2.3 seconds can be realized.
These periods vary with temperature, VDD and part-to-
part process variations (see DC specs).
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it
from timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the
maximum SLEEP time before a WDT wake-up reset.
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
0
M
Postscaler
1
Watchdog
Timer
U
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
Configuration Bit
To Timer0 (Figure 6-4)
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
WDT
Time-out
TABLE 7-6:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset Pin Change
Value on
Wake-up on
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1111 1111
N/A
OPTION RBWU RBPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, —= unimplemented, read as '0', u= unchanged
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 35
PIC16C505
7.7
Time-Out Sequence, Power Down,
7.8
Reset on Brown-Out
and Wake-up from SLEEP Status Bits
(TO/PD/RBWUF)
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
The TO, PD, and RBWUF bits in the STATUS register
can be tested to determine if a RESET condition has
been caused by a power-up condition, a MCLR or
Watchdog Timer (WDT) reset, or a MCLR or WDT
reset.
To reset PIC16C505 devices when
a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 7-13 and Figure 7-14.
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 1
TABLE 7-7:
TO/PD/RBWUF STATUS
AFTER RESET
RBWUF TO PD
RESET caused by
WDT wake-up from
SLEEP
VDD
0
0
0
0
0
1
0
1
0
VDD
WDT time-out (not from
SLEEP)
33k
Q1
MCLR wake-up from
SLEEP
10k
MCLR
40k*
0
0
1
1
u
1
1
u
0
PIC16C505
Power-up
MCLR not during SLEEP
Wake-up from SLEEP on
pin change
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
Legend: Legend: u = unchanged
Note 1: The TO, PD, and RBWUF bits main-
*Refer to Figure 7-7 and Table 10-6 for internal weak pull-
up on MCLR.
tain their status (u) until a reset
occurs. A low-pulse on the MCLR
input does not change the TO, PD,
and RBWUF status bits.
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 2
These STATUS bits are only affected by events listed
in Table 7-8.
VDD
TABLE 7-8:
EVENTS AFFECTING TO/PD
STATUS BITS
VDD
R1
Event
RBWUF TO
PD Remarks
Q1
MCLR
0
0
1
0
1
Power-up
R2
u
WDT Time-out
No effect
on PD
40k
PIC16C505
u
u
1
1
0
1
SLEEP instruction
CLRWDT
instruction
1
1
0
Wake-up from
SLEEP on pin
change
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
Legend: u = unchanged
R1
A WDT time-out will occur regardless of the status of the
TO bit. A SLEEP instruction will be executed, regardless of
the status of the PD bit. Table 7-7 reflects the status of TO
and PD after the corresponding event.
= 0.7V
VDD •
R1 + R2
*Refer to Figure 7-7 and Table 10-6 for internal weak
pull-up on MCLR.
Table 7-4 lists the reset conditions for the special
function registers, while Table 7-3 lists the reset
conditions for all the registers.
DS40192A-page 36
Preliminary
1998 Microchip Technology Inc.
PIC16C505
7.9
Power-Down Mode (SLEEP)
7.10
Program Verification/Code Protection
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
If the code protection bit has not been programmed,
the on-chip program memory can be read out for
verification purposes.
7.9.1
SLEEP
The first 64 locations and the last location (OSCCAL)
can be read regardless of the code protection bit
setting.
The Power-Down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
7.11
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code-
identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR pin low.
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '0's.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the RB3/
MCLR/VPP pin must be at a logic high level (VIHMC) if
MCLR is enabled.
7.9.2
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. An external reset input on RB3/MCLR/VPP pin,
when configured as MCLR.
2. A Watchdog Timer time-out reset (if WDT was
enabled).
3. A change on input pin RB0, RB1, RB3 or RB4
when wake-up on change is enabled.
These events cause a device reset. The TO, PD, and
RBWUF bits can be used to determine the cause of
device reset. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEP is invoked.
The RBWUF bit indicates a change in state while in
SLEEP at pins RB0, RB1, RB3 or RB4 (since the last
file or bit operation on RB port).
Caution: Right before entering SLEEP, read the
input pins. When in SLEEP, wake up
occurs when the values at the pins change
from the state they were in at the last
reading. If a wake-up on change occurs
and the pins are not read before
reentering SLEEP, a wake up will occur
immediately even if no pins change while
in SLEEP mode.
The WDT is cleared when the device wakes from
sleep, regardless of the wake-up source.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 37
PIC16C505
7.12
In-Circuit Serial Programming
FIGURE 7-15: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
The PIC16C505 microcontrollers can be serially
programmed while in the end application circuit.This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16C505
+5V
0V
VDD
VSS
The device is placed into a program/verify mode by
holding the RB1 and RB0 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB1 becomes the programming clock
and RB0 becomes the programming data. Both RB1
and RB0 are Schmitt Trigger inputs in this mode.
VPP
MCLR/VPP
RB1
RB0
CLK
Data I/O
VDD
After reset, a 6-bit command is then supplied to the
device. Depending on the command, 14-bits of pro-
gram data are then supplied to or from the device,
depending if the command was a load or a read. For
complete details of serial programming, please refer to
the PIC16C505 Programming Specifications.
To Normal
Connections
A typical in-circuit serial programming connection is
shown in Figure 7-15.
DS40192A-page 38
Preliminary
1998 Microchip Technology Inc.
PIC16C505
All instructions are executed within a single instruction
cycle, unless a conditional test is true or the program
counter is changed as a result of an instruction. In this
case, the execution takes two instruction cycles. One
instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 µs. If a conditional test
is true or the program counter is changed as a result of
an instruction, the instruction execution time is 2 µs.
8.0
INSTRUCTION SET SUMMARY
Each PIC16C505 instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC16C505
instruction set summary in Table 8-2 groups the
instructions into byte-oriented, bit-oriented, and literal
and control operations. Table 8-1 shows the opcode
field descriptions.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
0xhhh
where 'h' signifies a hexadecimal digit.
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
FIGURE 8-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
11
6
5
4
0
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
5
4
0
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
OPCODE
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Field
Description
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
Literal and control operations (except GOTO)
11
8
7
0
Bit address within an 8-bit file register
Literal field, constant data or label
OPCODE
k (literal)
k = 8-bit immediate value
Literal and control operations - GOTOinstruction
11 0
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
x
d
9
8
OPCODE
k (literal)
Destination select;
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
k = 9-bit immediate value
label Label name
TOS
PC
Top of Stack
Program Counter
Watchdog Timer Counter
Time-Out bit
WDT
TO
PD
Power-Down bit
Destination, either the W register or the specified
register file location
dest
[ ]
( )
→
Options
Contents
Assigned to
< >
Register bit field
In the set of
italics
User defined term (font is courier)
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 39
PIC16C505
TABLE 8-2:
INSTRUCTION SET SUMMARY
12-Bit Opcode
Mnemonic,
Operands
Status
Description
Cycles MSb
LSb Affected Notes
1
1
1
1
1
1
0001 11df ffff
C,DC,Z 1,2,4
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f,d
f,d
f
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
Z
Z
Z
2,4
4
–
Z
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
Z
None
Z
None
Z
Z
None
None
C
2,4
2,4
2,4
2,4
2,4
2,4
1,4
1(2) 0010 11df ffff
0010 10df ffff
1(2) 0011 11df ffff
1
1
1
1
1
1
1
1
1
1
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
0000 10df ffff
0011 10df ffff
0001 10df ffff
–
2,4
2,4
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
C
C,DC,Z 1,2,4
None
Z
2,4
2,4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
0100 bbbf ffff
0101 bbbf ffff
None
None
None
None
2,4
2,4
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
1 (2) 0110 bbbf ffff
1 (2) 0111 bbbf ffff
LITERAL AND CONTROL OPERATIONS
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
0000 0000 0011
0000 0000 0fff
1111 kkkk kkkk
Z
None
AND literal with W
Call subroutine
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
–
k
–
f
1
3
T
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
O, PD
None
Z
None
None
None
TO, PD
None
Z
Exclusive OR Literal to W
XORLW
k
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.
(Section 4.6)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 6 causes the contents of the W register to be written to the tristate latches of
PORTB. A '1' forces the pin to a hi-impedance state and disables the output buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
DS40192A-page 40
Preliminary
1998 Microchip Technology Inc.
PIC16C505
ADDWF
Syntax:
Add W and f
[ label ] ADDWF f,d
0 ≤ f ≤ 31
ANDWF
Syntax:
AND W with f
[ label ] ANDWF f,d
Operands:
Operands:
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
0001
11df
ffff
0001
01df
ffff
Encoding:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Description:
Description:
Words:
1
Words:
1
1
Cycles:
Example:
1
Cycles:
Example:
ADDWF FSR, 0
ANDWF FSR,
1
Before Instruction
Before Instruction
0x17
W
=
0x17
W
=
FSR = 0xC2
FSR = 0xC2
After Instruction
After Instruction
W
=
0xD9
W
=
0x17
FSR = 0xC2
FSR = 0x02
ANDLW
And literal with W
BCF
Bit Clear f
Syntax:
[ label ] ANDLW
k
Syntax:
Operands:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
0 → (f<b>)
Z
Status Affected: None
1110
kkkk
kkkk
0100
bbbf
ffff
Encoding:
Description:
Words:
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Bit 'b' in register 'f' is cleared.
1
1
Words:
1
Cycles:
Cycles:
Example:
1
BCF
FLAG_REG,
7
Example:
ANDLW 0x5F
Before Instruction
FLAG_REG = 0xC7
Before Instruction
0xA3
W
=
After Instruction
FLAG_REG = 0x47
After Instruction
0x03
W
=
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 41
PIC16C505
BSF
Bit Set f
BTFSS
Bit Test f, Skip if Set
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected: None
0101
bbbf
ffff
0111
bbbf
ffff
Encoding:
Description:
Words:
Encoding:
Bit 'b' in register 'f' is set.
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
Description:
1
1
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BSF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0x0A
Words:
1
After Instruction
FLAG_REG = 0x8A
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSS FLAG,1
PROCESS_CODE
•
BTFSC
Bit Test f, Skip if Clear
•
•
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
Operation:
skip if (f<b>) = 0
=
=
=
=
0,
Status Affected: None
address (FALSE);
1,
address (TRUE)
bbbf
ffff
if FLAG<1>
PC
Encoding:
0110
If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
Description:
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSC
FLAG,1
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
if FLAG<1>
PC
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
if FLAG<1>
PC
DS40192A-page 42
Preliminary
1998 Microchip Technology Inc.
PIC16C505
CALL
Subroutine Call
[ label ] CALL
0 ≤ k ≤ 255
CLRW
Clear W
Syntax:
k
Syntax:
[ label ] CLRW
None
Operands:
Operation:
Operands:
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
00h → (W);
1 → Z
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected:
Encoding:
Z
0000
0100
0000
Status Affected: None
The W register is cleared. Zero bit (Z)
is set.
Description:
1001
kkkk
kkkk
Encoding:
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STA-
TUS<6:5>, PC<8> is cleared.CALLis a
two cycle instruction.
Description:
Words:
1
Cycles:
Example:
1
CLRW
Before Instruction
0x5A
W
=
After Instruction
Words:
1
2
W
=
0x00
Cycles:
Example:
Z
=
1
HERE
CALL
THERE
Before Instruction
PC address (HERE)
CLRWDT
Clear Watchdog Timer
[ label ] CLRWDT
None
=
Syntax:
After Instruction
PC address (THERE)
TOS =
=
Operands:
Operation:
address (HERE + 1)
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
CLRF
Clear f
Syntax:
[ label ] CLRF
f
Status Affected: TO, PD
Operands:
Operation:
0 ≤ f ≤ 31
0000
0000
0100
Encoding:
00h → (f);
1 → Z
The CLRWDTinstruction resets the
WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.
Description:
Status Affected:
Encoding:
Z
0000
011f
ffff
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
CLRWDT
Cycles:
Example:
Before Instruction
CLRF
FLAG_REG
WDT counter
=
=
?
Before Instruction
FLAG_REG
After Instruction
WDT counter
=
0x5A
0x00
After Instruction
WDT prescale =
0
1
1
FLAG_REG
Z
=
=
0x00
1
TO
PD
=
=
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 43
PIC16C505
COMF
Complement f
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] COMF f,d
0 ≤ f ≤ 31
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d; skip if result = 0
Status Affected:
Encoding:
Z
Status Affected: None
0010
01df
ffff
0010
11df
ffff
Encoding:
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead mak-
ing it a two cycle instruction.
Words:
1
1
Cycles:
Example:
COMF
REG1,0
Words:
1
Before Instruction
REG1
=
0x13
0x13
Cycles:
Example:
1(2)
After Instruction
HERE
DECFSZ
GOTO
CONTINUE •
CNT, 1
LOOP
REG1
=
W
=
0xEC
•
•
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 31
Before Instruction
PC
=
address (HERE)
Syntax:
After Instruction
Operands:
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
d
[0,1]
Operation:
(f) – 1 → (dest)
Status Affected:
Encoding:
Z
address (HERE+1)
0000
11df
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
GOTO
Unconditional Branch
Syntax:
[ label ] GOTO
0 ≤ k ≤ 511
k
Words:
1
1
Operands:
Cycles:
Example:
Operation:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
DECF
CNT,
1
Before Instruction
Status Affected: None
CNT
=
0x01
0
101k
kkkk
kkkk
Encoding:
Z
=
GOTOis an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTOis a
two cycle instruction.
Description:
After Instruction
CNT
=
0x00
1
Z
=
Words:
1
Cycles:
Example:
2
GOTO THERE
After Instruction
PC
=
address (THERE)
DS40192A-page 44
Preliminary
1998 Microchip Technology Inc.
PIC16C505
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
[ label ] IORLW k
0 ≤ f ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
d
[0,1]
(W) .OR. (k) → (W)
Operation:
(f) + 1 → (dest)
Z
Status Affected:
Encoding:
Z
1101
kkkk
kkkk
0010
10df
ffff
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
IORLW 0x35
Cycles:
Example:
Before Instruction
0x9A
INCF
CNT,
1
W
=
Before Instruction
After Instruction
CNT
=
0xFF
0
W
=
0xBF
Z
=
Z
=
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
INCFSZ
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 31
d
[0,1]
Syntax:
Operation:
(W).OR. (f) → (dest)
Operands:
Status Affected:
Encoding:
Z
d
[0,1]
0001
00df
ffff
Operation:
(f) + 1 → (dest), skip if result = 0
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Status Affected: None
0011
11df
ffff
Encoding:
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
If the result is 0, then the next instruc-
tion, which is already fetched, is dis-
carded and an NOP is executed
instead making it a two cycle instruc-
tion.
IORWF
RESULT, 0
Before Instruction
RESULT
W
=
0x13
=
0x91
After Instruction
Words:
1
RESULT
=
=
=
0x13
0x93
0
Cycles:
Example:
1(2)
W
Z
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 45
PIC16C505
MOVF
Move f
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] MOVF f,d
f
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Encoding:
Z
0000
001f
ffff
Encoding:
0010
00df
ffff
Move data from the W register to regis-
ter 'f'.
Description:
The contents of register 'f' is moved to
destination 'd'. If 'd' is 0, destination is
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test
a file register since status flag Z is
affected.
Description:
Words:
1
Cycles:
Example:
1
MOVWF TEMP_REG
Before Instruction
Words:
1
1
TEMP_REG
W
=
=
0xFF
0x4F
Cycles:
Example:
MOVF
FSR,
0
After Instruction
TEMP_REG
W
=
=
0x4F
0x4F
After Instruction
W
=
value in FSR register
NOP
No Operation
[ label ] NOP
None
MOVLW
Move Literal to W
[ label ] MOVLW
0 ≤ k ≤ 255
Syntax:
Syntax:
k
Operands:
Operation:
Operands:
Operation:
No operation
k → (W)
Status Affected: None
0000
0000
0000
Status Affected: None
Encoding:
Description:
Words:
1100
kkkk
kkkk
Encoding:
No operation.
The eight bit literal 'k' is loaded into the
W register. The don’t cares will assem-
ble as 0s.
Description:
1
Cycles:
1
NOP
Example:
Words:
1
Cycles:
Example:
1
MOVLW 0x5A
After Instruction
W
=
0x5A
DS40192A-page 46
Preliminary
1998 Microchip Technology Inc.
PIC16C505
OPTION
Syntax:
Load OPTION Register
[ label ] OPTION
None
RLF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLF f,d
Operands:
Operation:
0 ≤ f ≤ 31
d
[0,1]
(W) → OPTION
Status Affected: None
Operation:
See description below
C
0000
0000
0010
Encoding:
Status Affected:
Encoding:
The content of the W register is loaded
into the OPTION register.
Description:
0011
01df
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
OPTION
Before Instruction
register 'f'
C
W
=
0x07
0x07
After Instruction
OPTION
Words:
1
=
Cycles:
Example:
1
RLF
REG1,0
RETLW
Return with Literal in W
Before Instruction
Syntax:
[ label ] RETLW
k
REG1
C
=
=
1110 0110
0
Operands:
Operation:
0 ≤ k ≤ 255
After Instruction
k → (W);
TOS → PC
REG1
W
C
=
=
=
1110 0110
1100 1100
1
Status Affected: None
1000
kkkk
kkkk
Encoding:
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
d
[0,1]
Words:
1
2
Operation:
See description below
C
Cycles:
Example:
Status Affected:
Encoding:
CALL TABLE ;W contains
;table offset
;value.
0011
00df
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Description:
•
•
;W now has table
;value.
•
TABLE
ADDWF PC
RETLW k1
RETLW k2
;W = offset
;Begin table
;
register 'f'
C
•
•
Words:
1
•
Cycles:
Example:
1
RETLW kn
; End of table
RRF
REG1,0
Before Instruction
W
=
0x07
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
value of k8
W
=
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 47
PIC16C505
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
Syntax:
[label]
None
[label] SUBWF f,d
SLEEP
Operands:
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
00h → WDT;
0 → WDT prescaler;
1 → TO;
Operation:
(f) – (W) → (dest)
Status Affected: C, DC, Z
0 → PD
0000
10df
ffff
Encoding:
Status Affected: TO, PD, RBWUF
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0011
Encoding:
Time-out status bit (TO) is set. The
power down status bit (PD) is cleared.
Description:
Words:
1
1
RBWUF is unaffected.
The WDT and its prescaler are
cleared.
Cycles:
SUBWF
REG1, 1
Example 1:
The processor is put into SLEEP mode
with the oscillator stopped. See sec-
tion on SLEEP for more details.
Before Instruction
REG1
W
C
=
=
=
3
2
?
Words:
1
Cycles:
Example:
1
After Instruction
SLEEP
REG1
=
=
=
1
2
1
W
C
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
FF
2
0
; result is negative
DS40192A-page 48
Preliminary
1998 Microchip Technology Inc.
PIC16C505
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 31
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW
0 ≤ k ≤ 255
k
Operands:
Operands:
d
[0,1]
Operation:
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Encoding:
1111
kkkk
kkkk
Status Affected: None
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
0011
10df
ffff
Encoding:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
0xB5
W
=
SWAPF
REG1,
0
After Instruction
Before Instruction
REG1
W
=
0x1A
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
TRIS
Load TRIS Register
d
[0,1]
Syntax:
[ label ] TRIS
f = 6
f
Operation:
(W) .XOR. (f) → (dest)
Operands:
Operation:
Status Affected:
Encoding:
Z
(W) → TRIS register f
0001
10df
ffff
Status Affected: None
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0fff
Encoding:
TRIS register 'f' (f = 6 or 7) is loaded
with the contents of the W register
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
TRIS
PORTB
REG,1
XORWF
Before Instruction
Before Instruction
W
=
0XA5
0XA5
REG
=
0xAF
0xB5
W
=
After Instruction
TRIS
=
After Instruction
REG
W
=
=
0x1A
0xB5
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 49
PIC16C505
NOTES:
DS40192A-page 50
Preliminary
1998 Microchip Technology Inc.
PIC16C505
9.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER /PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
9.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
9.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
9.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
The PICMASTER Emulator System has been
designed as
a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 51
PIC16C505
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
9.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
9.9
MPLAB™ Integrated Development
Environment Software
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
9.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
9.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
9.10
Assembler (MPASM)
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
The MPASM Universal Macro Assembler is a PC-
hosted symbolic assembler. It supports all microcon-
troller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
DS40192A-page 52
Preliminary
1998 Microchip Technology Inc.
PIC16C505
MPASM has the following features to assist in develop-
ing software for specific use applications.
9.14
MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
9.15
SEEVAL Evaluation and
Programming System
9.11
Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
9.16
KEELOQ Evaluation and
Programming Tools
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
9.12
C Compiler (MPLAB-C17)
The MPLAB-C Code Development System is
a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
9.13
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 53
24CXX HCS200
PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X 25CXX HCS300
93CXX HCS301
PIC12C5XX
PIC16C505
EMULATOR PRODUCTS
PICMASTER
/
PICMASTER-CE
In-Circuit Emulator
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ICEPIC Low-Cost
In-Circuit Emulator
SOFTWARE PRODUCTS
MPLAB
Integrated
Development
Environment
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MPLAB C17
Compiler
fuzzyTECH -MP
Explorer/Edition
Fuzzy Logic Dev. Tool
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
MP-DriveWay
Applications
Code Generator
Total Endurance
Software Model
ü
PROGRAMMERS
PICSTART Plus
Low-Cost
Universal Dev. Kit
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
ü
PRO MATE II
Universal Programmer
ü
ü
ü
ü
KEELOQ Programmer
DEMO BOARDS
SEEVAL Designers Kit
PICDEM-1
ü
ü
ü
ü
PICDEM-2
ü
ü
PICDEM-3
ü
KEELOQ Evaluation Kit
ü
PIC16C505
10.0 ELECTRICAL CHARACTERISTICS - PIC16C505
Absolute Maximum Ratings†
Ambient Temperature under bias ........................................................................................................... –40˚C to +125˚C
Storage Temperature.............................................................................................................................. –65˚C to +150˚C
Voltage on VDD with respect to VSS .................................................................................................................0 to +7.5 V
Voltage on MCLR with respect to VSS...............................................................................................................0 to +14 V
Voltage on all other pins with respect to VSS ................................................................................–0.6 V to (VDD + 0.6 V)
(1)
Total Power Dissipation ....................................................................................................................................700 mW
Max. Current out of VSS pin...................................................................................................................................200 mA
Max. Current into VDD pin......................................................................................................................................150 mA
Input Clamp Current, IIK (VI < 0 or VI > VDD) ....................................................................................................................±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................25 mA
Max. Output Current sourced by I/O port .............................................................................................................100 mA
Max. Output Current sunk by I/O port ..................................................................................................................100 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
†
NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 55
PIC16C505
10.1
DC CHARACTERISTICS:
PIC16C505-04 (Commercial, Industrial, Extended)
PIC16C505-20(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
(1)
Characteristic
Sym
Min
Max
Units
Conditions
Typ
Supply Voltage
VDD
3.0
5.5
V
XT, EXTRC, INTRC and LP OSC configura-
tion
4.5
5.5
V
V
HS OSC configuration
RAM Data Retention
VDR
1.5*
Device in SLEEP mode
(2)
Voltage
VDD Start Voltage to ensure VPOR
VSS
V
See section on Power-on Reset for details
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
(3)
IDD
—
—
—
1.8
1.8
15
2.4
2.4
27
35
35
16
mA
mA
µA
XT and EXTRC options (Note 4)
FOSC = 4 MHz, VDD = 5.5V
INTRC Option
Supply Current
FOSC = 4 MHz, VDD = 5.5V
LP OPTION, Commercial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Industrial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Extended Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
HS OPTION, Industrial Temperature
FOSC = 20 MHz, VDD = 5.5V
—
—
—
19
µA
19
µA
4.5
mA
(5)
IPD
Power-Down Current
—
—
—
—
—
—
4
4
5
0.25
0.25
2
12
14
22
4
5
18
µA
µA
µA
µA
µA
µA
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 3.0V, Extended
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 3.0V, Extended
WDT Enabled
WDT Disabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
DS40192A-page 56
Preliminary
1998 Microchip Technology Inc.
PIC16C505
10.2
DC CHARACTERISTICS:
PIC16LC505-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
(1)
Characteristic
Sym
Min
Max
Units
Conditions
Typ
Supply Voltage
VDD
3.0
5.5
V
XT, EXTRC, INTRC OSC configuration
2.5
5.5
V
V
LP OSC configuration
Device in SLEEP mode
RAM Data Retention
VDR
1.5*
(2)
Voltage
VDD Start Voltage to ensure VPOR
VSS
V
See section on Power-on Reset for details
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
(3)
IDD
—
—
—
1.8
1.8
15
2.4
2.4
27
35
35
16
mA
mA
µA
XT and EXTRC options (Note 4)
FOSC = 4 MHz, VDD = 5.5V
INTRC Option
Supply Current
FOSC = 4 MHz, VDD = 5.5V
LP OPTION, Commercial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Industrial Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP OPTION, Extended Temperature
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
HS OPTION, Industrial Temperature
FOSC = 20 MHz, VDD = 5.5V
—
—
—
19
µA
19
µA
4.5
mA
(5)
IPD
Power-Down Current
—
—
—
—
—
—
4
4
5
0.25
0.25
2
12
14
22
4
5
18
µA
µA
µA
µA
µA
µA
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 3.0V, Extended
VDD = 3.0V, Commercial
VDD = 3.0V, Industrial
VDD = 3.0V, Extended
WDT Enabled
WDT Disabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through Rext. The current through the resistor can be estimated by the
formula: IR = VDD/2Rext (mA) with Rext in kOhm.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is mea-
sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 57
PIC16C505
10.3
DC CHARACTERISTICS:
PIC16C505-04 (Commercial, Industrial, Extended)
PIC16C505-20(Commercial, Industrial, Extended)
PIC16LC505-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
All Pins Except
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1.
(1)
Characteristic
Sym
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL
I/O ports
VSS
VSS
0.8
V
V
Pin at hi-impedance
4.5V < VDD ≤ 5.5V
Pin at hi-impedance
3.0V < VDD ≤ 4.5V
0.15 VDD
MCLR and RC5 (Schmitt Trigger)
VSS
VSS
VSS
VSS
0.20 VDD
0.20 VDD
0.3 VDD
V
V
V
V
(4)
OSC1
OSC1
OSC1
EXTRC option only
XT and HS options
LP option
0.6 VDD -1.0
Input High Voltage
VIH
I/O ports
0.25VDD+0.8V
2.0
0.2VDD+1V
0.8 VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
2.5V < VDD ≤ 4.5V
(5)
4.5V < VDD ≤ 5.5V
(5)
Full VDD range
MCLR and RC5 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
Full VDD range
EXTRC option only
HS, XT and LP options
(4)
0.9 VDD
0.7 VDD
IPUR
(2,3)
Input Leakage Current
IIL
For VDD ≤ 5.5V
I/O ports
–1
20
–3
0.5
+1
µA
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD,
XT and LP options
(2)
MCLR
130
0.5
0.5
250
+5
+3
µA
µA
µA
OSC1
Output Low Voltage
Vol
I/O ports
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOH = –5.4 mA, VDD = 4.5V
(3,4)
Output High Voltage
I/O ports
VoH
VDD –0.7
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
2: The leakage current on the MCLR/VPP/RB3 pin is strongly dependent on the applied voltage level.The spec-
ified levels represent normal operating conditions. Higher leakage current may be measured at different
input voltage.
3: Negative current is defined as coming out of the pin.
4: For PIC16C505 devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C505 be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
DS40192A-page 58
Preliminary
1998 Microchip Technology Inc.
PIC16C505
10.4
Timing Parameter Symbology and Load Conditions - PIC16C505
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC16C505
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
VSS
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 59
PIC16C505
10.5
Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C505
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
Sym
(1)
Characteristic
Min
Max Units
Conditions
Typ
No.
(2)
FOSC
DC
DC
—
—
4
4
MHz XT osc mode
External CLKIN Frequency
MHz HS osc mode
(PIC16C505-04)
DC
DC
0.1
4
—
—
—
—
200
4
kHz LP osc mode
MHz EXTRC osc mode
MHz XT osc mode
(2)
Oscillator Frequency
4
4
MHz HS osc mode
(PIC16C505-04)
4
—
20
MHz HS osc mode
(PIC16C505-20)
DC
250
5
—
—
—
—
—
—
200
—
kHz LP osc mode
ns XT osc mode
µs LP osc mode
ns EXTRC osc mode
ns XT osc mode
(2)
1
TOSC
External CLKIN Period
—
(2)
250
250
250
—
Oscillator Period
10,000
250
ns HS ocs mode
(PIC16C505-04)
50
—
250
ns HS ocs mode
(PIC16C505-20)
5
—
—
µs LP osc mode
(3)
2
Tcy
—
4/FOSC
DC
ns
Instruction Cycle Time
200
—
ns TC4 = 4/FOSC
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS40192A-page 60
Preliminary
1998 Microchip Technology Inc.
PIC16C505
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C505 (CONTINUED)
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
Sym
(1)
Characteristic
Min
Max Units
Conditions
Typ
No.
3
TosL, TosH Clock in (OSC1) Low or High Time
50*
2*
—
—
—
—
ns XT oscillator
µs LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
10
—
—
—
4
TosR, TosF Clock in (OSC1) Rise or Fall Time
—
—
—
25*
50*
15
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 61
PIC16C505
FIGURE 10-3: I/O TIMING - PIC16C505
Q1
Q2
Q3
Q4
OSC1
I/O Pin
(input)
17
18
19
I/O Pin
(output)
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-2: TIMING REQUIREMENTS - PIC16C505
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
(1)
No.
Sym
TosH2ioV
TosH2ioI
Characteristic
Min
—
Typ
Max
100*
—
Units
ns
(3)
—
—
17
OSC1↑ (Q1 cycle) to Port out valid
OSC1↑ (Q2 cycle) to Port input invalid
TBD
ns
18
(I/O in hold time)
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
19
(I/O in setup time)
(3)
TioR
TioF
—
—
10
10
25**
25**
ns
ns
20
21
Port output rise time
(3)
Port output fall time
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in EXTRC mode.
3: See Figure 10-1 for loading conditions.
DS40192A-page 62
Preliminary
1998 Microchip Technology Inc.
PIC16C505
FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C505
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Timeout
(Note 2)
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
2: Runs in MCLR or WDT reset only in XT, LP and HS modes.
TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1
Parameter
No.
(1)
Sym Characteristic
Min Typ
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
2000*
9*
—
—
ns VDD = 5 V
Twdt Watchdog Timer Time-out Period
(No Prescaler)
18*
30*
ms VDD = 5 V (Commercial)
(2)
32
34
TDRT Device Reset Timer Period
9*
—
18*
—
30*
ms VDD = 5 V (Commercial)
ns
TioZ I/O Hi-impedance from MCLR Low
2000*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
TABLE 10-4: DRT (DEVICE RESET TIMER PERIOD - PIC16C505
Oscillator Configuration
POR Reset
Subsequent Resets
IntRC & ExtRC
XT, HS & LP
18 ms (typical)
18 ms (typical)
300 µs (typical)
18 ms (typical)
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 63
PIC16C505
FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C505
T0CKI
40
41
42
TABLE 10-5: TIMER0 CLOCK REQUIREMENTS - PIC16C505
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1.
Parameter
(1)
Sym Characteristic
Min
Typ
Max Units Conditions
No.
40
Tt0H T0CKI High Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TABLE 10-6: PULL-UP RESISTOR RANGES - PIC16C505
VDD (Volts)
Temperature (°C)
Min
Typ
Max
Units
RB0/RB1/RB4
3.0
-40
25
27K
33K
33K
37K
15K
18K
19K
22K
32K
38K
39K
42K
17K
20K
22K
24K
35K
43K
43K
60K
20K
23K
25K
28K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
5.5
85
125
RB3
3.0
5.5
-40
25
271K
327K
348K
400K
247K
288K
306K
351K
326K
390K
427K
472K
292K
341K
371K
407K
395K
492K
500K
567K
360K
437K
448K
500K
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
85
125
-40
25
85
125
*
These parameters are characterized but not tested.
DS40192A-page 64
Preliminary
1998 Microchip Technology Inc.
PIC16C505
11.0 DC AND AC CHARACTERISTICS - PIC16C505
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 11-1: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 5.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
Not available at this time.
FIGURE 11-2: CALIBRATED INTERNAL RC FREQUENCY RANGE VS.TEMPERATURE (VDD = 3.0V)
(INTERNAL RC IS CALIBRATED TO 25°C, 5.0V)
Not available at this time.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 65
PIC16C505
FIGURE 11-3: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 5.5V)
Not available at this time.
FIGURE 11-4: INTERNAL RC FREQUENCY VS. CALIBRATION VALUE (VDD = 3.5V)
Not available at this time.
TABLE 11-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C
VDD = 3.0V(1)
Oscillator
Frequency
VDD = 5.5V
250 µA(2)
420 µA
251 µA
7 µA
620 µA(2)
1.1 mA
775 µA
37 µA
External RC
4 MHz
4 MHz
4 MHz
32 KHz
20 MHz
Internal RC
XT
LP
HS
N/A
4.5 mA
Note 1: LP oscilator based on VDD = 2.5V
Note 2: Does not include current through external R&C.
DS40192A-page 66
Preliminary
1998 Microchip Technology Inc.
PIC16C505
FIGURE 11-5: WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 11-6: SHORT DRT PERIOD VS. VDD
1000
50
45
40
900
800
700
600
35
30
Max +125°C
Max +125°C
500
25
Max +85°C
Max +85°C
400
20
Typ +25°C
300
Typ +25°C
15
200
10
MIn –40°C
MIn –40°C
100
2
3
4
5
6
7
5
2
3
4
5
6
7
VDD (Volts)
VDD (Volts)
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 67
PIC16C505
FIGURE 11-7: IOH vs. VOH, VDD = 2.5 V
FIGURE 11-9: IOL vs. VOL, VDD = 2.5 V
25
0
-1
-2
20
Max –40°C
15
10
-3
-4
Typ +25°C
Min +85°C
-5
Min +125°C
5
0
-6
-7
500m
1.0
1.5
2.0
2.5
VOH (Volts)
0
250.0m
500.0m
1.0
VOL (Volts)
FIGURE 11-8: IOH vs. VOH, VDD = 5.5 V
FIGURE 11-10: IOL vs. VOL, VDD = 5.5 V
0
50
-5
Max –40°C
40
30
20
10
-10
Typ +25°C
Min +85°C
-15
-20
Min +125°C
-25
-30
3.5
4.0
4.5
5.0
5.5
0
VOH (Volts)
250.0m
500.0m
750.0m
1.0
VOL (Volts)
DS40192A-page 68
Preliminary
1998 Microchip Technology Inc.
PIC16C505
12.0 PACKAGING INFORMATION
12.1
Package Marking Information
14-Lead PDIP (300 mil)
Example
16C505-04I/P
BUILT 4 SPEED
MMMMMMMMMMMMMM
XXXXXXXXXXXXXX
AABBCDE
9804SAZ
14-Lead SOIC (150 mil)
Example
16C505-04I
9804SAZ
MMMMMMMMMM
AABBCDE
Example
14-Lead Windowed Ceramic Side Brazed (300 mil)
JW
MM
16C505
MMMMMMM
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP
price.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 69
PIC16C505
Package Type: K04-005 14-Lead Plastic Dual In-line (P) – 300 mil
E
D
2
1
n
α
E1
A
A1
R
L
c
A2
B1
β
eB
p
B
Units
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
INCHES*
NOM
0.300
MILLIMETERS
MIN
MAX
MIN
NOM
7.62
14
MAX
n
p
B
B1
R
c
14
0.100
0.018
0.060
0.005
0.010
0.145
0.085
0.015
0.130
0.750
0.245
0.280
0.368
10
2.54
0.013
0.023
0.33
1.40
0.46
1.52
0.13
0.25
3.68
2.16
0.38
3.30
19.05
6.22
7.11
9.33
10
0.58
†
0.055
0.000
0.006
0.120
0.065
0.000
0.125
0.740
0.240
0.260
0.310
5
0.065
0.010
0.012
0.170
0.105
0.035
0.135
0.760
0.250
0.300
0.425
15
1.65
0.25
0.30
4.32
2.67
0.89
3.43
19.30
6.35
7.62
10.80
15
0.00
0.20
3.05
1.65
0.00
3.18
18.80
6.10
6.60
7.87
5
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A1
A2
L
D
E
E1
eB
α
‡
‡
β
5
10
15
5
10
15
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010”(0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS40192A-page 70
Preliminary
1998 Microchip Technology Inc.
PIC16C505
Package Type: K04-065 14-Lead Plastic Small Outline (SL) – Narrow, 150 mil
E1
E
p
D
2
1
B
n
α
X
45°
L
R2
c
A
A1
φ
R1
A2
L1
β
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
14
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
14
MAX
p
n
A
A1
A2
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
0.058
0.063
0.036
0.006
0.341
0.153
0.236
0.014
0.005
0.005
0.016
4
0.068
1.47
0.69
1.60
0.90
0.15
8.66
3.89
5.99
0.36
0.13
0.13
0.41
4
1.73
0.027
0.004
0.338
0.150
0.230
0.010
0.005
0.005
0.011
0
0.044
0.008
0.344
0.156
0.242
0.018
0.010
0.010
0.021
8
1.12
0.20
8.74
3.96
6.15
0.46
0.25
0.25
0.53
8
0.10
8.59
3.81
5.84
0.25
0.13
0.13
0.28
0
‡
D
E
‡
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.000
0.008
0.014
0
0.005
0.009
0.017
12
0.010
0.010
0.019
15
0.00
0.19
0.36
0
0.13
0.22
0.42
12
0.25
0.25
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 71
PIC16C505
Package Type: 14-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil
E
W
T
D
2
1
n
U
A
A1
L
A2
c
B1
p
eB
B
Units
INCHES*
NOM
0.300
14
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Lead Thickness
Top to Seating Plane
Top of Body to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
MIN
MAX
MIN
NOM
7.62
14
MAX
n
p
B
B1
c
0.098
0.016
0.050
0.008
0.145
0.103
0.025
0.130
0.680
0.280
0.310
0.161
0.440
0.260
0.100
0.018
0.055
0.010
0.165
0.123
0.035
0.140
0.700
0.290
0.338
0.166
0.450
0.270
0.102
2.49
0.41
2.54
0.46
1.40
0.25
4.19
3.12
0.89
3.56
17.78
7.37
8.57
4.22
11.43
6.86
2.59
0.020
0.060
0.012
0.185
0.143
0.045
0.150
0.720
0.300
0.365
0.171
0.460
0.280
0.51
1.52
0.30
4.70
3.63
1.14
3.81
18.29
7.62
9.27
4.34
11.68
7.11
1.27
0.20
3.68
2.62
0.64
3.30
17.27
7.11
7.87
4.09
11.18
6.60
A
A1
A2
L
D
E
eB
W
T
Package Width
Overall Row Spacing
Window Diameter
Lid Length
Lid Width
U
*
Controlling Parameter.
DS40192A-page 72
Preliminary
1998 Microchip Technology Inc.
PIC16C505
INDEX
A
O
OPTION Register ............................................................... 15
OSC selection..................................................................... 27
OSCCAL Register .............................................................. 16
Oscillator Configurations .................................................... 28
Oscillator Types
ALU....................................................................................... 7
Applications........................................................................... 3
Architectural Overview.......................................................... 7
Assembler
HS............................................................................... 28
LP ............................................................................... 28
RC .............................................................................. 28
XT............................................................................... 28
MPASM Assembler..................................................... 52
B
Block Diagram
On-Chip Reset Circuit................................................. 33
Timer0......................................................................... 23
TMR0/WDT Prescaler................................................. 26
Watchdog Timer.......................................................... 35
Brown-Out Protection Circuit .............................................. 36
P
Package Marking Information............................................. 69
Packaging Information........................................................ 69
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 52
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 52
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 52
PICMASTER In-Circuit Emulator..................................... 51
PICSTART Plus Entry Level Development System......... 51
POR
Device Reset Timer (DRT) ................................... 27, 34
PD............................................................................... 36
Power-On Reset (POR).............................................. 27
TO............................................................................... 36
PORTB ............................................................................... 19
Power-Down Mode............................................................. 37
Prescaler ............................................................................ 26
PRO MATE II Universal Programmer.............................. 51
Program Counter................................................................ 17
C
CAL0 bit .............................................................................. 16
CAL1 bit .............................................................................. 16
CAL2 bit .............................................................................. 16
CAL3 bit .............................................................................. 16
CALFST bit ......................................................................... 16
CALSLW bit ........................................................................ 16
Carry ..................................................................................... 7
Clocking Scheme................................................................ 10
Code Protection ............................................................ 27, 37
Configuration Bits................................................................ 27
Configuration Word............................................................. 27
D
Q
DC and AC Characteristics................................................. 65
Development Support ......................................................... 51
Development Tools............................................................. 51
Device Varieties.................................................................... 5
Digit Carry............................................................................. 7
Q cycles.............................................................................. 10
R
RC Oscillator ...................................................................... 29
Read Modify Write.............................................................. 20
Register File Map ............................................................... 12
Registers
F
Family of Devices
PIC16C505 ................................................................... 4
FSR..................................................................................... 18
Fuzzy Logic Dev. System (fuzzyTECH -MP) .................... 53
Special Function......................................................... 13
Reset .................................................................................. 27
Reset on Brown-Out........................................................... 36
I
S
I/O Interfacing ..................................................................... 19
I/O Ports.............................................................................. 19
I/O Programming Considerations........................................ 20
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ............ 51
ID Locations.................................................................. 27, 37
INDF.................................................................................... 18
Indirect Data Addressing..................................................... 18
Instruction Cycle ................................................................. 10
Instruction Flow/Pipelining .................................................. 10
Instruction Set Summary..................................................... 40
SEEVAL Evaluation and Programming System .............. 53
SLEEP.......................................................................... 27, 37
Software Simulator (MPLAB-SIM)...................................... 53
Special Features of the CPU.............................................. 27
Special Function Registers................................................. 13
Stack................................................................................... 17
STATUS ................................................................................7
STATUS Register............................................................... 14
T
Timer0
K
Switching Prescaler Assignment ................................ 26
Timer0 ........................................................................ 23
Timer0 (TMR0) Module .............................................. 23
TMR0 with External Clock .......................................... 25
Timing Diagrams and Specifications .................................. 60
Timing Parameter Symbology and Load Conditions .......... 59
TRIS Registers ................................................................... 19
KeeLoq Evaluation and Programming Tools.................... 53
L
Loading of PC ..................................................................... 17
M
Memory Organization.......................................................... 11
Data Memory .............................................................. 12
Program Memory ........................................................ 11
MP-DriveWay™ - Application Code Generator................... 53
MPLAB C ............................................................................ 53
MPLAB Integrated Development Environment Software.... 52
W
Wake-up from SLEEP ........................................................ 37
Watchdog Timer (WDT)................................................ 27, 34
Period ......................................................................... 35
Programming Considerations..................................... 35
Z
Zero bit ..................................................................................7
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 73
PIC16C505
NOTES:
DS40192A-page 74
Preliminary
1998 Microchip Technology Inc.
PIC16C505
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. PICmicro, FlexROM, MPLAB and fuzzy-
LAB are trademarks and SQTP is a service mark of Micro-
chip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 75
PIC16C505
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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RE:
From:
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Address
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Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS40192A
Device:
PIC16C505
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40192A-page 76
Preliminary
1998 Microchip Technology Inc.
PIC16C505
PIC16C505 Product Identification System
Examples
PART NO. -XX X /XX XXX
Pattern:
Special Requirements
a)
b)
c)
PIC16C505-04/P
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits
Package:
SL
P
JW
=
=
=
150 mil SOIC
300 mil PDIP
300 mil Windowed Ceramic Side Brazed
PIC16C505-04I/SL
Industrial Temp., SOIC
package,4 MHz,normal
VDD limits
Temperature
Range:
-
=
=
=
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
I
E
Frequency
Range:
04
04
20
=
=
=
4 MHz (XT, INTRC, EXTRC OSC)
200 KHz (LP OSC)
20 MHz (HS OSC)
PIC16C505-04I/P
Industrial Temp.,
PDIP package, 4 MHz,
normal VDD limits
Device
PIC16C505
PIC16LC505
PIC16C505T (Tape & reel for SOIC only)
PIC16LC505T (Tape & reel for SOIC only)
Please contact your local sales office for exact ordering procedures.
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 77
PIC16C505
NOTES:
DS40192A-page 78
Preliminary
1998 Microchip Technology Inc.
PIC16C505
NOTES:
1998 Microchip Technology Inc.
Preliminary
DS40192A-page 79
M
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
Microchip Technology Inc.
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Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
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Tel: 852-2-401-1200 Fax: 852-2-401-3431
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Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
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Arizona Microchip Technology Ltd.
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Tel: 770-640-0034 Fax: 770-640-0307
India
Microchip Technology Inc.
India Liaison Office
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Tel: 91-80-229-0061 Fax: 91-80-229-0062
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Microchip Technology Inc.
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Singapore
Microchip Technology Singapore Pte Ltd.
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4/3/98
Tel: 714-263-1888 Fax: 714-263-1338
NewYork
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Microchip Technology Inc.
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Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
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Tel: 905-405-6279 Fax: 905-405-6253
Organization (ISO).
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 4/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS40192A-page 80
1998 Microchip Technology Inc.
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