PIC16C52T-04I/P [MICROCHIP]
8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP18, 0.300 INCH, PLASTIC, DIP-18;型号: | PIC16C52T-04I/P |
厂家: | MICROCHIP |
描述: | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP18, 0.300 INCH, PLASTIC, DIP-18 可编程只读存储器 时钟 光电二极管 外围集成电路 |
文件: | 总88页 (文件大小:526K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16C52
EPROM-Based 8-Bit CMOS Microcontroller
Pin Diagrams
Feature Highlights
Program Memory
384
Data Memory
I/O
PDIP, SOIC
25
12
18
17
16
15
14
13
12
11
10
RA1
• 1
2
RA2
RA3
High-Performance RISC CPU
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
3
T0CKI
MCLR/VPP
VSS
• Only 33 single word instructions to learn
• All single cycle instructions (1 µs) except for
program branches which are two-cycle
• Operating speed:
4
5
RB7
6
RB0
RB6
7
RB1
RB5
8
RB2
- DC to 4 MHz clock input
RB4
9
RB3
- DC to 1 µs instruction cycle
• 384 x 12 on-chip EPROM program memory
• 25 x 8 general purpose registers (SRAM)
• Special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes
Peripheral Features
• 12 I/O pins with individual direction control
• Sink/source current of 10 mA (max)
• TMR0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
- RC:
- XT:
Low-cost RC oscillator
Standard crystal/resonator
CMOS Technology
• Low-power, high-speed CMOS EPROM technology
• Fully static design
• Wide-operating voltage range (3.0 V to 6.25 V)
• Commercial and Industrial temperature ranges
• Low-power consumption
- <2.0 mA @ 5.0 V, 4 MHz
- 15 µA typical @ 3.0 V, 32 kHz
- <3.0 µA typical standby current @ 3.0 V
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 1
PIC16C52
Table of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
General Description.............................................................................................................................................3
PIC16C52 Device Varieties .................................................................................................................................5
Architectural Overview.........................................................................................................................................7
Memory Organization ........................................................................................................................................11
I/O Ports.............................................................................................................................................................17
Timer0 Module and TMR0 Register...................................................................................................................19
Special Features of the CPU .............................................................................................................................23
Instruction Set Summary ...................................................................................................................................33
Development Support........................................................................................................................................45
10.0 Electrical Characteristics ...................................................................................................................................51
11.0 DC and AC Characteristics................................................................................................................................59
12.0 Packaging Information.......................................................................................................................................67
Appendix A: Compatibility..................................................................................................................................71
Appendix B: What’s New ...................................................................................................................................71
Appendix C:PIC16/17 Microcontrollers..............................................................................................................73
Index..................................................................................................................................................................81
List of Examples ................................................................................................................................................82
List of Figures ....................................................................................................................................................83
List of Tables .....................................................................................................................................................84
Connecting to Microchip BBS............................................................................................................................85
Access to the Internet........................................................................................................................................85
Reader Response..............................................................................................................................................86
PIC16C52 Product Identification System...........................................................................................................87
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
To assist you in the use of this document, Appendix B contains a list of new information in this data sheet, while
Appendix C contains information that has changed
DS30254B-page 2
Advance Information
1995 Microchip Technology Inc.
PIC16C52
1.0
GENERAL DESCRIPTION
The PIC16C52 from Microchip Technology is a
low-cost, high performance, 8-bit, fully static,
EPROM-based CMOS microcontroller. It employs a
RISC architecture with only 33 single word/single
cycle instructions. All instructions are single cycle
except for program branches which take two cycles.
The PIC16C52 delivers performance an order of
magnitude higher than its competitors in the same
price category. The 12-bit wide instructions are highly
symmetrical resulting in 2:1 code compression over
other 8-bit microcontrollers in its class. The easy to
use and easy to remember instruction set reduces
development time significantly.
The PIC16C52 is equipped with special features that
reduce system cost and power requirements. The
Power-On Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are two oscillator configurations to choose from:
the cost-saving RC oscillator and the standard XT
crystal/resonator. Power-saving SLEEP mode and
code protection features improve system cost, power
and reliability.
This cost-effective, One Time Programmable (OTP)
device is suitable for production in any volume. The
customer can take full advantage of Microchip’s price
leadership in OTP microcontrollers while benefiting
from the OTP’s flexibility.
The PIC16C52 is supported by a full-featured macro
assembler, a software simulator, an in-circuit emulator,
a ‘C’ compiler, fuzzy logic support tools, a low-cost
development programmer, and
a
full featured
programmer. All the tools are supported on IBM
PC-AT and compatible machines.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 3
PIC16C52
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
Clock
Memory
Peripherals
Features
PIC16C52
PIC16C54
PIC16C54A
4
384
—
—
—
25
25
25
TMR0
TMR0
TMR0
TMR0
12 3.0-6.25 33 18-pin DIP, SOIC
20 512
20 512
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
(2)
20
—
512 25
PIC16CR54
PIC16CR54A
20
20
—
—
512 25
512 25
TMR0
TMR0
12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
(1)
PIC16CR54B
PIC16C55
20 512
—
—
24
25
25
TMR0
TMR0
TMR0
20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
PIC16C56
20
20
1K
—
(1)
1K
PIC16CR56
PIC16C57
20
20
2K
—
—
72
72
TMR0
TMR0
20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
(2)
2K
PIC16CR57A
20
—
2K
72
TMR0
20 2.5-6.25 33 28-pin DIP, SOIC, SSOP
PIC16CR57B
PIC16C58A
PIC16CR58A
20
20
20
2K
—
—
—
2K
2K
73
73
73
TMR0
TMR0
TMR0
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP
(1)
PIC16CR58B
All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer (except PIC16C52),
selectable code protect and high I/O current capability (except PIC16C52).
Note 1: Please contact your local sales office for availability of these devices.
2: Not recommended for new designs.
DS30254B-page 4
Advance Information
1995 Microchip Technology Inc.
PIC16C52
2.0
PIC16C52 DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and
production requirements, the proper device option can
be selected using the information in this section. When
placing orders, please use the PIC16C52 Product
Identification System at the back of this data sheet to
specify the correct part number.
2.1
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages,
permit the user to program them once. In addition to
the program memory, the configuration bits must be
programmed.
2.2
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium to high quantity of units and whose code
patterns have stabilized. The devices are identical to
the OTP devices but with all EPROM locations and
configuration bit options already programmed by the
factory. Certain code and prototype verification
procedures apply before production shipments are
available. Please contact your Microchip Technology
sales office for more details.
2.3
Serialized
Quick-Turnaround-Production
(SQTP) Devices
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 5
PIC16C52
NOTES:
DS30254B-page 6
Advance Information
1995 Microchip Technology Inc.
PIC16C52
The PIC16C52 device contains an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C52 can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C52 uses a Harvard architecture in
which program and data are accessed on separate
buses. This improves bandwidth over traditional von
Neumann architecture where program and data are
fetched on the same bus. Separating program and
data memory further allows instructions to be sized
differently than the 8-bit wide data word. Instruction
opcodes are 12-bits wide making it possible to have all
single word instructions. A 12-bit wide program
memory access bus fetches a 12-bit instruction in a
single cycle. A two-stage pipeline overlaps fetch and
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the W (working) register. The
other operand is a file register or an immediate
constant. In single operand instructions, the operand
is either the W register or a file register.
The W register is an 8-bit working register used for
ALU operations. It is not an addressable register.
execution
of
instructions.
Consequently,
all
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC),
and Zero (Z) bits in the STATUS register. The C and
DC bits operate as a borrow and digit borrow out bit,
respectively, in subtraction. See the SUBWFand ADDWF
instructions for examples.
instructions (33) execute in a single cycle except for
program branches.
The PIC16C52 addresses 384 x 12 program memory.
All program memory is internal.
The PIC16C52 can directly or indirectly address its
register files and data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16C52 has a highly
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make
programming with the PIC16C52 simple yet efficient.
In addition, the learning curve is reduced significantly.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 7
PIC16C52
FIGURE 3-1: PIC16C52 BLOCK DIAGRAM
9-11
T0CKI
PIN
OSC1 OSC2 MCLR
CONFIGURATION WORD
9-11
STACK 1
STACK2
EPROM
384 X 12
“DISABLE” “OSC
PC
SELECT”
12
2
“CODE
OSCILLATOR/
TIMING &
CONTROL
PROTECT”
INSTRUCTION
REGISTER
CLKOUT
TIMER0
PRESCALER
9
12
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
FROM W
DIRECT ADDRESS
DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE
5
5-7
8
(SRAM)
25 Bytes
STATUS
TMR0
FSR
8
8
DATA BUS
W
ALU
FROM W
8
FROM W
4
8
4
“TRIS 5”
“TRIS 6”
TRISB PORTB
TRISA PORTA
4
8
RA3:RA0
RB7:RB0
DS30254B-page 8
Advance Information
1995 Microchip Technology Inc.
PIC16C52
TABLE 3-1:
Name
PIC16C52 PINOUT DESCRIPTION
PDIP, SOIC I/O/P
Input
No.
Type Levels
Description
RA0
RA1
RA2
RA3
17
18
1
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
6
7
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
TTL
TTL
TTL
TTL
9
10
11
12
13
T0CKI
3
I
ST
Clock input to Timer0. Must be tied to VSS or VDD, if not in use, to
reduce current consumption.
MCLR/VPP
4
I
ST
Master clear (reset) input/programming voltage input. This pin is
an active low reset to the device. Voltage on MCLR/VPP must not
exceed VDD to avoid unintended entering of programming mode.
OSC1/CLKIN
16
15
I
ST
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator in crys-
tal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and denotes the instruction
cycle rate.
VDD
VSS
14
5
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output,
P = power, — = Not Used,
TTL = TTL input, ST = Schmitt Trigger input
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 9
PIC16C52
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, and
the instruction is fetched from program memory and
latched into the instruction register in Q4. It is
decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-2 and Example 3-1.
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the
instruction (Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is
latched into the Instruction Register (IR) in cycle Q1.
This instruction is then decoded and executed during
the Q2, Q3, and Q4 cycles. Data memory is read
during Q2 (operand read) and written during Q4
(destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
Internal
phase
clock
PC
PC+1
PC+2
PC
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30254B-page 10
Advance Information
1995 Microchip Technology Inc.
PIC16C52
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: special function registers and
general purpose registers.
4.1
Program Memory Organization
The PIC16C52 has a 9-bit Program Counter (PC)
capable of addressing a 384 x 12 program memory
space (Figure 4-1).
The reset vector for the PIC16C52 is at 17Fh. A NOPat
the reset vector location will cause a restart at
location 000h.
The special function registers include the TMR0
register, the Program Counter (PC), the Status
Register, the I/O registers (ports), and the File Select
Register (FSR). In addition, special purpose registers
are used to control the I/O port configuration and
prescaler options.
FIGURE 4-1: PIC16C52 PROGRAM
MEMORY MAP AND STACK
The general purpose registers are used for data and
control information under command of the instructions.
PC<8:0>
9
CALL, RETLW
For the PIC16C52, the register file is composed of
seven special function registers and 25 general
purpose registers (Figure 4-2).
Stack Level 1
Stack Level 2
000h
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly
through the file select register FSR (Section 4.7).
On-chip
Program
Memory
FIGURE 4-2: PIC16C52 REGISTER FILE
MAP
File Address
INDF(1)
00h
TMR0
PCL
01h
02h
03h
04h
05h
06h
07h
17Fh
Reset Vector
STATUS
FSR
PORTA
PORTB
General
Purpose
Registers
0Fh
10h
1Fh
Note 1: Not a physical register. See Section 4.7
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 11
PIC16C52
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets.
The special function registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
The Special Function Registers are registers used by
the CPU and peripheral functions to control the
operation of the device (Table 4-1).
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-On
Reset
Value on
MCLR
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
00h
01h
TRIS
I/O control registers (TRISA and TRISB)
Contains control bits to configure Timer0 and Timer0 prescaler
1111 1111 1111 1111
--11 1111 --11 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
OPTION
INDF
Uses contents of FSR to address data memory (not a physical register)
8-bit real-time clock/counter
TMR0
(1)
02h
03h
04h
05h
06h
PCL
Low order 8 bits of PC
1111 1111 1111 1111
0001 1xxx 000q quuu
1xxx xxxx 1uuu uuuu
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
STATUS
FSR
PA2
PA1
PA0
TO
PD
Z
DC
C
Indirect data memory address pointer
PORTA
PORTB
—
—
—
—
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB7
RB6
RB5
RB4
Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)
x= unknown, u= unchanged, q= see the tables in Section 7.6 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5
for an explanation of how to access these bits.
DS30254B-page 12
Advance Information
1995 Microchip Technology Inc.
PIC16C52
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
and the RESET status.
It is recommended, therefore, that only BCF, BSF and
MOVWF instructions be used to alter the STATUS
register because these instructions do not affect the Z,
DC or C bits from the STATUS register. For other
instructions which do affect STATUS bits, see
Table 8-2, Instruction Set Summary.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to
the device logic. Furthermore, the TO and PD bits are
not writable. Therefore, the result of an instruction
with the STATUS register as destination may be
different than intended.
FIGURE 4-3: STATUS REGISTER (ADDRESS:03h)
R/W-0
PA2
R/W-0
PA1
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
6
5
4
3
2
1
bit0
bit 7-5: PA2:PA0: Page select bits - unused.
Use of the PA2:PA0 bits as a general purpose read/write bit is not recommended,
since this may affect upward compatibility.
bit 4:
bit 3:
TO: Time-out bit
This bit always set on the PIC16C52.
PD: Power-down bit
1 = After power-up
0 = After SLEEPinstruction
bit 2:
bit 1:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF
1 = A carry from the 4th low order bit of the result occurred
0 = A carry from the 4th low order bit of the result did not occur
SUBWF
1 = A borrow from the 4th low order bit of the result did not occur
0 = A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF
1 = A carry occurred
0 = A carry did not occur
SUBWF
1 = A borrow did not occur
0 = A borrow occurred
RRF or RLF
Load bit with LSb or MSb
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 13
PIC16C52
4.4
OPTION Register
The OPTION register is a 6-bit wide, write-only
register which contains various control bits to
configure the Timer0 prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W register will be transferred to the OPTION
register. A RESET sets the OPTION<5:0> bits.
FIGURE 4-4: OPTION REGISTER
U-0
—
U-0
—
6
W-1
T0CS
5
W-1
T0SE
4
W-1
PSA
3
W-1
PS2
2
W-1
PS1
1
W-1
PS0
W = Writable bit
= Unimplemented bit
- n = Value at POR reset
U
bit7
bit0
bit 7-6: Unimplemented.
bit 5:
bit 4:
bit 3:
T0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler rate = 1:1
0 = Prescaler rate defined by PS2:PS0
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
DS30254B-page 14
Advance Information
1995 Microchip Technology Inc.
PIC16C52
4.5
Program Counter
4.6
Stack
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
The PIC16C52 device has a 9-bit wide, two-level
hardware push/pop stack (Figure 4-1).
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1.
If more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 4-5).
A RETLW instruction will pop the contents of stack
level 1 into the program counter and then copy stack
level 2 contents into level 1. If more than two
sequential RETLW’s are executed, the stack will be
filled with the address previously stored in level 2.
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC are provided
by the instruction word. However, PC<8> does not
come from the instruction word, but is always cleared.
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC,and BSF PC,5.
Note: The W register will be loaded with the
literal value specified in the instruction.
This is particularly useful for the
implementation of data look-up tables
within the program memory.
For the RETLW instruction, the PC is loaded with the
Top Of Stack (TOS) contents. All of the devices
covered in this data sheet have only two stacks. Each
stack has the same bit width as the device PC.
FIGURE 4-5: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C52
GOTO Instruction
8
7
0
PCL
PC
Instruction Word
CALL or Modify PCL Instruction
8
7
0
PCL
PC
Reset to '0'
Instruction Word
4.5.1
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (i.e., the reset vector).
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 15
PIC16C52
4.7
Indirect Data Addressing; INDF and
FSR Registers
FIGURE 4-6: DIRECT/INDIRECT
ADDRESSING
The INDF register is not
a physical register.
Direct Addressing
Addressing INDF actually addresses the register
whose address is contained in the FSR register (FSR
is a pointer). This is indirect addressing.
4
(opcode)
0
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value
of 10h
Indirect Addressing
(FSR)
0
4
• Increment the value of the FSR register by one
(FSR = 06)
location select
• A read of the INDR register now will return the
value of 0Ah.
00h
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
Data Memory
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
For register
map detail see
Section 4.2.
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x10 ;initialize pointer
movwf FSR
;
to RAM
1Fh
NEXT
clrf
incf
INDF ;clear INDF register
FSR,F ;inc pointer
btfsc FSR,4 ;all done?
goto
NEXT ;NO, clear next
CONTINUE
:
;YES, continue
The FSR is a 5-bit wide register. It is used in
conjunction with the INDF register to indirectly address
the data memory area.
DS30254B-page 16
Advance Information
1995 Microchip Technology Inc.
PIC16C52
5.4
I/O Interfacing
5.0
I/O PORTS
As with any other register, the I/O registers can be
written and read under program control. However,
read instructions (e.g., MOVF PORTB,W) always read
the I/O pins independent of the pin’s input/output
modes. On RESET, all I/O ports are defined as input
(inputs are at hi-impedance) since the I/O control
registers (TRISA, TRISB) are all set.
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operations. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The
outputs are latched and remain unchanged until the
output latch is rewritten. To use a port pin as output,
the corresponding direction control bit (in TRISA,
TRISB) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can
be programmed individually as input or output.
5.1
PORTA
PORTA is a 4-bit I/O register. Only the low order 4 bits
are used (RA3:RA0). Bits 7-4 are unimplemented and
read as '0's.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
5.2
PORTB
Data
Bus
PORTB is an 8-bit I/O register (PORTB<7:0>).
D
Q
Q
Data
Latch
5.3
TRIS Registers
VDD
P
WR
Port
CK
The output driver control registers are loaded with the
contents of the W register by executing the TRIS f
instruction. A '1' from a TRIS register bit puts the
corresponding output driver in a hi-impedance mode.
A '0' puts the contents of the output data latch on the
selected pins, enabling the output buffer.
N
I/O
pin(1)
W
Reg
D
Q
Q
TRIS
Latch
VSS
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin
is low.
TRIS ‘f’
CK
Reset
The TRIS registers are “write-only” and are set (output
drivers disabled) upon RESET.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR
Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
05h
06h
TRIS
PORTA
PORTB
I/O control registers (TRISA and TRISB)
1111 1111 1111 1111
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
—
—
—
—
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB7
RB6
RB5
RB4
Legend: Shaded boxes = unimplemented, read as ‘0’,
–= unimplemented, read as '0', x= unknown, u= unchanged
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 17
PIC16C52
5.5
I/O Programming Considerations
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.5.1
BI-DIRECTIONAL I/O PORTS
;Initial PORT Settings
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute
the bit operation and re-write the result. Caution must
be used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a
bi-directional I/O pin (say bit0) and it is defined as an
input at this time, the input signal present on the pin
itself would be read into the CPU and rewritten to the
data latch of this particular pin, overwriting the
previous content. As long as the pin stays in the input
mode, no problem occurs. However, if bit0 is switched
into output mode later on, the content of the data latch
may now be unknown.
;
;
PORTB<7:4> Inputs
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BCF
BCF
MOVLW 03Fh
TRIS PORTB
PORTB, 7
PORTB, 6
;01pp pppp
;10pp pppp
;
11pp pppp
11pp pppp
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.5.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of
an instruction cycle, whereas for reading, the data
must be valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”,
“wired-and”). The resulting high output currents may
damage the chip.
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Instruction
fetched
MOVWF PORTB MOVF PORTB,W
Data setup time = (0.25 TCY – TPD)
where: TCY = instruction cycle.
TPD = propagation delay
RB7:RB0
Port pin
written here
Port pin
sampled here
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
Instruction
executed
MOVWF PORTB MOVF PORTB,W
NOP
(Write to
PORTB)
(Read
PORTB)
DS30254B-page 18
Advance Information
1995 Microchip Technology Inc.
PIC16C52
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.1.
6.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). When the PSA bit is
set, the prescaler is not used (prescaler = 1:1). When
the PSA bit is cleared, prescale values of 1:2, 1:4,...,
1:256 are selectable by the PS2:PS0 bits. Section 6.2
details the operation of the prescaler.
Figure 6-1 is a simplified block diagram of the Timer0
module, while Figure 6-2 shows the electrical structure
of the Timer0 input.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-3 and Figure 6-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
T0CKI
pin
Programmable
Prescaler
PSout
Sync
(1)
(2 cycle delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
Schmitt Trigger
Input Buffer
N
(1)
VSS
VSS
Note 1: ESD protection circuits
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 19
PIC16C52
FIGURE 6-3: TIMER0 TIMING:
INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-4: TIMER0 TIMING:
INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
0
NT0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 6-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-On
Reset
Value on
MCLR
Reset
Name
Bit 7
Timer0 - 8-bit real-time clock/counter
T0CS T0SE PSA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01
TMR0
xxxx xxxx uuuu uuuu
N/A
OPTION
—
—
PS2
PS1
PS0 --11 1111 --11 1111
Legend: Shaded cells: Unimplemented bits,
-= unimplemented, x = unknown, u= unchanged,
DS30254B-page 20
Advance Information
1995 Microchip Technology Inc.
PIC16C52
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of
40 ns) divided by the prescaler value. The only
requirement on T0CKI high and low time is that they
do not violate the minimum pulse width requirement of
10 ns. Refer to parameters 40, 41 and 42 in the
electrical specification of the desired device.
6.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it
must meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0
module is actually incremented. Figure 6-5 shows the
delay from the external clock edge to the timer
incrementing.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or
misses sampling
Prescaler Output (2)
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 21
PIC16C52
When assigned, all instructions writing to the TMR0
register (e.g., CLRF 1, MOVWF 1, BSF 1,x,etc.) will
clear the prescaler. The prescaler is neither readable
nor writable. On a RESET, the prescaler contains all
'0's.
6.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module. The PSA and PS2:PS0 bits
(OPTION<3:0>) determine prescaler assignment and
prescale ratio.
FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0 PRESCALER
TCY ( = Fosc/4)
Data Bus
8
0
M
U
X
1
M
U
X
T0CKI
pin
1
Sync
2
Cycles
TMR0 reg
0
T0SE
T0CS
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
DS30254B-page 22
Advance Information
1995 Microchip Technology Inc.
PIC16C52
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake up
from SLEEP through external reset. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost. A set of configuration bits are used to select
various options.
7.0
SPECIAL FEATURES OF THE
CPU
What sets
processors are special circuits to deal with the needs
of real-time applications. The PIC16C52
microcontroller has a host of such features intended to
maximize system reliability, minimize cost through
elimination of external components, provide power
saving operating modes and offer code protection.
These features are:
a
microcontroller apart from other
7.1
Configuration Bits
The PIC16C52 configuration word consists of 12 bits,
4 of which are implemented. Configuration bits can be
programmed to select various device configurations.
Two bits are for the selection of the oscillator type and
two are unused on this device (Figure 7-1).
• Oscillator selection
• Reset
• Power-On Reset (POR)
• Device Reset Timer (DRT)
• SLEEP
OTP or QTP devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System" on
the inside back cover).
• Code protection
• ID locations
For the PIC16C52, there is an 18 ms delay provided
by the Device Reset Timer (DRT), intended to keep
the chip in reset until the crystal oscillator is stable.
With this timer on-chip, most applications need no
external reset circuitry.
FIGURE 7-1: CONFIGURATION WORD FOR PIC16C52
—
—
—
9
—
8
—
7
—
6
—
5
—
4
CP
3
—
2
FOSC1 FOSC0
bit0
Register: CONFIG
(1)
Address
:
FFFh
bit11
10
1
bit 11-4: Unimplemented: Read as ’0’.
bit 3:
CP: Code protection bit
1 = Code protection off
0 = Code protection on
bit 2:
Unimplemented: Read as ’0’.
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11 = RC oscillator
01 = XT oscillator
10 = Unused on PIC16C52
00 = Unused on PIC16C52
Note 1: Refer to the PIC16C5X Programming Specifications (literature number DS30190) to
determine how to access the configuration word.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 23
PIC16C52
7.2
Oscillator Configurations
TABLE 7-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16C52
7.2.1
OSCILLATOR TYPES
The PIC16C52 can be operated in two different
oscillator modes. The user can program two
configuration bits (FOSC1:FOSC0) to select one of
these modes:
Osc
Type
Resonator Cap. Range Cap. Range
Freq
C1
C2
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-33 pF
10-22 pF
68-100 pF
15-33 pF
10-22 pF
• RC:
• XT:
Resistor/Capacitor
Crystal/Resonator
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
7.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
TABLE 7-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC16C52
In XT mode, a crystal or ceramic resonator is
connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 7-2). The
PIC16C52 oscillator design requires the use of a
parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications. When in XT mode, the device can have
an external clock source drive the OSC1/CLKIN pin
(Figure 7-3).
Osc
Resonator Cap.Range Cap. Range
Type
Freq
C1
C2
XT
100 kHz
200 kHz
455 kHz
1 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15 pF
FIGURE 7-2: CRYSTAL OPERATION OR
CERAMIC RESONATOR (XT
2 MHz
4 MHz
15 pF
15 pF
OSC CONFIGURATION)
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
(1)
C1
OSC1
PIC16C52
SLEEP
XTAL
(3)
RF
To internal
logic
OSC2
(2)
RS
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
FIGURE 7-3: EXTERNAL CLOCK INPUT
OPERATION (XT OSC
CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16C52
Open
DS30254B-page 24
Advance Information
1995 Microchip Technology Inc.
PIC16C52
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
7.2.4
RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used.
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external
crystal oscillator circuit. Prepackaged oscillators
provide a wide operating range and better stability. A
well-designed crystal oscillator will provide good
performance with TTL gates. Two types of crystal
oscillator circuits can be used: one with parallel
resonance, or one with series resonance.
Figure 7-4 shows implementation of
a
parallel
resonant oscillator circuit. The circuit is designed to
use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
Figure 7-6 shows how the R/C combination is
connected to the PIC16C5X. For Rext values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high Rext values (e.g.,
1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
This
circuit
could
be
used
for
external
oscillator designs.
FIGURE 7-4: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
PIC16C52
10k
74AS04
4.7k
CLKIN
74AS04
The Electrical Specifications sections show RC
frequency variation from part to part due to normal
process variation. The variation is larger for larger R
(since leakage current variation will affect RC
frequency more for large R) and for smaller C (since
variation of input capacitance will affect RC
frequency more).
10k
XTAL
10k
Also, see the Electrical Specifications sections for
variation of oscillator frequency due to VDD for given
Rext/Cext values as well as frequency variation due to
operating temperature for given R, C, and VDD values.
20 pF
20 pF
Figure 7-5 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330Ω resistors provide the negative
feedback to bias the inverters in their linear region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic.
FIGURE 7-6: RC OSCILLATOR MODE
VDD
FIGURE 7-5: EXTERNAL SERIES
RESONANT CRYSTAL
Rext
OSCILLATOR CIRCUIT
Internal
clock
OSC1
N
To Other
Devices
330
330
PIC16C52
PIC16C52
74AS04
74AS04
74AS04
Cext
VSS
CLKIN
0.1 µF
Fosc/4
OSC2/CLKOUT
XTAL
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 25
PIC16C52
The TO and PD bits (STATUS <4:3>) are set or
cleared depending on the different reset conditions
(Section 7.6). These bits may be used to determine
the nature of the reset.
7.3
Reset
The PIC16C52 device may be reset in one of the
following ways:
• Power-On Reset (POR)
Table 7-4 lists a full description of reset states of all
registers. Figure 7-7 shows a simplified block diagram
of the on-chip reset circuit.
• MCLR reset (normal operation)
• MCLR wake-up reset (from SLEEP)
Table 7-3 shows these reset conditions for the PCL
and STATUS registers.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in
any other reset. Most other registers are reset to a
“reset state” on Power-On Reset (POR) or MCLR. A
MCLR wake-up from SLEEP also results in a device
reset, and not
before SLEEP.
a
continuation of operation
TABLE 7-3:
RESET CONDITIONS FOR SPECIAL REGISTERS
PCL
Addr: 02h
STATUS
Addr: 03h
Condition
1111 1111
1111 1111
1111 1111
0001 1xxx
Power-On Reset
(1)
000u uuuu
0001 0uuu
MCLR reset (normal operation)
MCLR wake-up (from SLEEP)
Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.
Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.
TABLE 7-4:
RESET CONDITIONS FOR ALL REGISTERS
Register
W
Address
N/A
Power-On Reset
xxxx xxxx
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
1111 1111
MCLR Reset
uuuu uuuu
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
1111 1111
TRIS
N/A
OPTION
INDF
N/A
00h
TMR0
PCL(1)
01h
02h
STATUS(1)
0001 1xxx
000q quuu
03h
1xxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
FSR
04h
05h
PORTA
PORTB
06h
General Purpose
register files
08-7Fh
Legend: u= unchanged, x= unknown, -= unimplemented, read as '0',
q= see tables in Section 7.6 for possible values.
Note 1: See Table 7-3 for reset value for specific conditions.
DS30254B-page 26
Advance Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
RESET
S
R
Q
Q
8-bit Asynch
On-Chip
RC OSC
Ripple Counter
(Start-Up Timer)
CHIP RESET
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 27
PIC16C52
7.4
Power-On Reset (POR)
FIGURE 7-8: ELECTRICAL STRUCTURE OF
MCLR/VPP PIN
The PIC16C5X family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
reset for most power-up situations. To use this feature,
the user merely ties the MCLR/VPP pin (Figure 7-8) to
VDD. A simplified block diagram of the on-chip
Power-On Reset circuit is shown in Figure 7-7.
RIN
(1)
MCLR
pin
Schmitt Trigger
Input Buffer
N
(1)
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the
on-chip reset signal.
VSS
VSS
Note 1: ESD protection circuits
FIGURE 7-9: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
A power-up example where MCLR is not tied to VDD is
shown in Figure 7-10. VDD is allowed to rise and
stabilize before bringing MCLR high. The chip will
actually come out of reset TDRT msec after MCLR
goes high.
VDD
VDD
In Figure 7-11, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The
VDD is stable before the start-up timer times out and
there is no problem in getting a proper reset. However,
Figure 7-12 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the
MCLR/VPP pin (and VDD) actually reach their full
value, is too long. In this situation, when the start-up
timer times out, VDD has not reached the VDD (min)
value and the chip is, therefore, not guaranteed to
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-9).
D
R
R1
MCLR
PIC16C52
C
• External Power-On Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
• R < 40 kΩ is recommended to make sure that
voltage drop across R does not exceed 0.2V
(max leakage current spec on MCLR/VPP pin
is 5 µA). A larger voltage drop will degrade
VIH level on MCLR/VPP pin.
Note: When the device starts normal operation
(exits the reset condition), device operat-
ing parameters (voltage, frequency, tem-
perature, etc.) must be meet to ensure
operation. If these conditions are not met,
the device must be held in reset until the
operating conditions are met.
• R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor C
in the event of MCLR pin breakdown due to
ESD or EOS.
For more information on PIC16C52 POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal reset
when VDD declines.
DS30254B-page 28
Advance Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will reset properly if, and only if, V1 ≥ VDD min.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 29
PIC16C52
7.5
Device Reset Timer (DRT)
7.6
Time-Out Sequence and Power Down
Status Bits (TO/PD)
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on reset. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows
VDD to rise above VDD min., and for the oscillator to
stabilize.
The TO and PD bits in the STATUS register can be
tested to determine if a RESET condition has been
caused by a power-up condition or MCLR reset, or a
MCLR wake-up reset.
TABLE 7-5:
TO/PD STATUS AFTER
RESET
Oscillator circuits based on crystals or ceramic
resonators require a certain time after power-up to
establish a stable oscillation. The on-chip DRT keeps
the device in a RESET for approximately 18 ms after
the voltage on the MCLR/VPP pin has reached a logic
high (VIHMC) level. Thus, external RC networks
connected to the MCLR input are not required in most
cases, allowing for savings in cost-sensitive and/or
space restricted applications.
TO
PD
RESET was caused by
Power-up (POR)
1
u
1
u
(1)
MCLR reset (normal operation)
1
0
MCLR wake-up reset (from SLEEP)
Legend: u= unchanged
Note 1: The TO and PD bits maintain their status (u) until
a reset occurs. A low-pulse on the MCLR input
does not change the TO and PD status bits.
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
These STATUS bits are only affected by events listed
in Table 7-6.
TABLE 7-6:
EVENTS AFFECTING TO/PD
STATUS BITS
Event
TO PD
Remarks
1
1
1
0
Power-up
SLEEPinstruction
Legend: u= unchanged
A SLEEPinstruction will be executed, regardless of the sta-
tus of the PD bit. Table 7-5 reflects the status of TO and
PD after the corresponding event.
Table 7-3 lists the reset conditions for the special
function registers, while Table 7-4 lists the reset
conditions for all the registers.
DS30254B-page 30
Advance Information
1995 Microchip Technology Inc.
PIC16C52
7.7
Reset on Brown-Out
7.8
Power-Down Mode (SLEEP)
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and
then recovers. The device should be reset in the event
of a brown-out.
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
7.8.1
SLEEP
To reset PIC16C52 devices when a brown-out occurs,
external brown-out protection circuits may be built
(Figure 7-13 and Figure 7-14).
The Power-Down mode is entered by executing a
SLEEPinstruction.
The TO bit (STATUS<4>) is set, the PD bit
(STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
FIGURE 7-13: BROWN-OUT PROTECTION
CIRCUIT 1
VDD
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level (VIHMC).
VDD
33k
7.8.2
WAKE-UP FROM SLEEP
10k
MCLR
The device can wake-up from SLEEP through an
external reset input on MCLR/VPP pin. The PD bit,
which is set on power-up, is cleared when SLEEP is
invoked.
40k
PIC16C52
7.9
Program Verification/Code Protection
This circuit will activate reset when VDD goes below Vz +
0.7V (where Vz = Zener voltage).
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note: Microchip does not recommend code pro-
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 2
tecting windowed devices.
VDD
7.10
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other
code-identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
VDD
R1
Q1
MCLR
R2
40k
Use only the lower 4 bits of the ID locations and
always program the upper 8 bits as '1's.
PIC16C52
Note: Microchip will assign a unique pattern
number for QTP and SQTP requests. This
pattern number will be unique and trace-
able to the submitted code.
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
R1
= 0.7V
VDD •
R1 + R2
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 31
PIC16C52
NOTES:
DS30254B-page 32
Advance Information
1995 Microchip Technology Inc.
PIC16C52
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles. One instruction cycle consists of
four oscillator periods. Thus, for an oscillator
frequency of 4 MHz, the normal instruction execution
time is 1 µs. If a conditional test is true or the program
counter is changed as a result of an instruction, the
instruction execution time is 2 µs.
8.0
INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided
into an OPCODE, which specifies the instruction type,
and one or more operands which further specify the
operation of the instruction. The PIC16C5X instruction
set summary in Table 8-2 groups the instructions into
byte-oriented, bit-oriented, and literal and control
operations. Table 8-1 shows the opcode field
descriptions.
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator is used to
specify which one of the 32 file registers is to be used
by the instruction.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:
0xhhh
where 'h' signifies a hexadecimal digit.
The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.
FIGURE 8-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
11
6
5
d
4
0
OPCODE
f (FILE #)
d = 0 for destination W
d = 1 for destination f
For literal and control operations, 'k' represents an
8 or 9-bit constant or literal value.
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
5
4
0
OPCODE
f (FILE #)
Field
Description
b = 3-bit bit address
f = 5-bit file register address
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
Literal and control operations (except GOTO)
11
Bit address within an 8-bit file register
Literal field, constant data or label
8
7
0
OPCODE
k (literal)
Don't care location (= 0 or 1)
k = 8-bit immediate value
Literal and control operations - GOTOinstruction
11 0
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
x
d
9
8
Destination select;
OPCODE
k (literal)
d = 0 (store result in W)
d = 1 (store result in file register 'f')
Default is d = 1
k = 9-bit immediate value
label Label name
TOS
PC
Top of Stack
Program Counter
Time-Out bit
TO
PD
Power-Down bit
Destination, either the W register or the specified
register file location
dest
Options
[ ]
( )
→
Contents
Assigned to
Register bit field
In the set of
< >
User defined term (font is courier)
italics
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 33
PIC16C52
TABLE 8-2:
INSTRUCTION SET SUMMARY
12-Bit Opcode
Cycles MSb LSb Affected Notes
Mnemonic,
Operands
Status
Description
0001 11df ffff
C,DC,Z
1,2,4
2,4
4
1
1
1
1
1
1
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f,d
f,d
f
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
2,4
2,4
2,4
2,4
2,4
2,4
1,4
1(2) 0010 11df ffff
0010 10df ffff
1(2) 0011 11df ffff
1
1
1
1
1
1
1
1
1
1
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
0000 10df ffff
0011 10df ffff
0001 10df ffff
Z
None
None
C
–
2,4
2,4
1,2,4
2,4
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
C
C,DC,Z
None
Z
2,4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
0100 bbbf ffff
0101 bbbf ffff
None
None
None
None
2,4
2,4
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
1 (2) 0110 bbbf ffff
1 (2) 0111 bbbf ffff
LITERAL AND CONTROL OPERATIONS
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
0000 0000 0011
0000 0000 0fff
1111 kkkk kkkk
Z
None
O, PD
None
Z
None
None
None
TO, PD
None
Z
AND literal with W
Call subroutine
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
k
k
–
f
1
5
T
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
3
Exclusive OR Literal to W
XORLW
k
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except forGOTO.
(Section 4.5)
2: When an I/O register is modified as a function of itself (e.g.MOVF PORTB, 1), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5, 6, or 7 causes the contents of the W register to be written to the tristate
latches of PORTA, B or C, respectively. A '1' forces the pin to a hi-impedance state and disables the output
buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared
(if assigned to TMR0).
5: Do not use in PIC16C52 code.
DS30254B-page 34
Advance Information
1995 Microchip Technology Inc.
PIC16C52
ADDWF
Syntax:
Add W and f
[ label ] ADDWF f,d
0 ≤ f ≤ 31
ANDWF
Syntax:
AND W with f
[ label ] ANDWF f,d
Operands:
Operands:
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
0001
11df
ffff
0001
01df
ffff
Encoding:
Add the contents of the W register and
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is '1' the result is
stored back in register 'f'.
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Description:
Description:
Words:
1
Words:
1
1
Cycles:
Example:
1
Cycles:
Example:
ADDWF FSR, 0
ANDWF FSR,
1
Before Instruction
Before Instruction
W
=
0x17
W
=
0x17
FSR = 0xC2
FSR = 0xC2
After Instruction
After Instruction
W
=
0xD9
W
=
0x17
FSR = 0xC2
FSR = 0x02
ANDLW
And literal with W
BCF
Bit Clear f
Syntax:
[ label ] ANDLW
k
Syntax:
Operands:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
0 → (f<b>)
Z
Status Affected: None
1110
kkkk
kkkk
0100
bbbf
ffff
Encoding:
Description:
Words:
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Bit 'b' in register 'f' is cleared.
1
1
Words:
1
Cycles:
Cycles:
Example:
1
BCF
FLAG_REG,
7
Example:
ANDLW 0x5F
Before Instruction
Before Instruction
FLAG_REG = 0xC7
W
=
0xA3
After Instruction
After Instruction
FLAG_REG = 0x47
W
=
0x03
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 35
PIC16C52
BSF
Bit Set f
BTFSS
Bit Test f, Skip if Set
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected: None
0101
bbbf
ffff
0111
bbbf
ffff
Encoding:
Description:
Words:
Encoding:
Bit 'b' in register 'f' is set.
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
Description:
1
1
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and an NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BSF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0x0A
Words:
1
After Instruction
Cycles:
Example:
1(2)
FLAG_REG = 0x8A
HERE
FALSE GOTO
TRUE
BTFSS FLAG,1
PROCESS_CODE
•
BTFSC
Bit Test f, Skip if Clear
•
•
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
Operation:
skip if (f<b>) = 0
=
=
=
=
0,
Status Affected: None
address (FALSE);
1,
address (TRUE)
bbbf
ffff
if FLAG<1>
PC
Encoding:
0110
If bit 'b' in register 'f' is 0 then the next
instruction is skipped.
Description:
If bit 'b' is 0 then the next instruction
fetched during the current instruction
execution is discarded, and an NOP is
executed instead, making this a 2 cycle
instruction.
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSC
FLAG,1
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
if FLAG<1>
PC
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
if FLAG<1>
PC
DS30254B-page 36
Advance Information
1995 Microchip Technology Inc.
PIC16C52
CALL
Subroutine Call
[ label ] CALL k
0 ≤ k ≤ 255
CLRW
Clear W
Syntax:
Syntax:
[ label ] CLRW
None
Operands:
Operation:
Operands:
Operation:
(PC) + 1→ Top of Stack;
k → PC<7:0>;
00h → (W);
1 → Z
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected:
Encoding:
Z
0000
0100
0000
Status Affected: None
The W register is cleared. Zero bit (Z)
is set.
Description:
1001
kkkk
kkkk
Encoding:
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from STA-
TUS<6:5>, PC<8> is cleared. CALLis
a two cycle instruction.
Description:
Words:
1
Cycles:
Example:
1
CLRW
Before Instruction
W
=
0x5A
After Instruction
Words:
1
2
W
=
0x00
Cycles:
Example:
Z
=
1
HERE
CALL
THERE
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
address (THERE)
TOS =
address (HERE + 1)
CLRF
Clear f
CLRWDT
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
[ label ] CLRF
f
Syntax:
Operands:
Operation:
0 ≤ f ≤ 31
Operands:
Operation:
00h → (f);
1 → Z
1 → TO;
1 → PD
Status Affected:
Encoding:
Z
Status Affected: TO, PD
0000
011f
ffff
0000
0000
0100
Encoding:
The contents of register 'f' are cleared
and the Z bit is set.
Since WDT is not available on the
PIC16C52, the CLRWDTinstruction will
execute as a NOP. Status bits TO and
PD are set.
Description:
Description:
Words:
1
1
Cycles:
Example:
Words:
1
CLRF
FLAG_REG
Cycles:
Example:
1
Before Instruction
FLAG_REG
CLRWDT
=
0x5A
After Instruction
After Instruction
TO
PD
=
=
1
1
FLAG_REG
Z
=
=
0x00
1
Do not use in PIC16C52 code.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 37
PIC16C52
COMF
Complement f
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] COMF f,d
0 ≤ f ≤ 31
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d; skip if result = 0
Status Affected:
Encoding:
Z
Status Affected: None
0010
01df
ffff
0010
11df
ffff
Encoding:
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded
and an NOP is executed instead mak-
ing it a two cycle instruction.
Words:
1
1
Cycles:
Example:
COMF
REG1,0
Words:
1
Before Instruction
REG1
=
0x13
0x13
Cycles:
Example:
1(2)
After Instruction
HERE
DECFSZ
GOTO
CONTINUE •
CNT, 1
LOOP
REG1
=
W
=
0xEC
•
•
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 31
Before Instruction
PC
=
address (HERE)
Syntax:
After Instruction
Operands:
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
d
[0,1]
Operation:
(f) – 1 → (dest)
Status Affected:
Encoding:
Z
address (HERE+1)
0000
11df
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 511
Syntax:
Words:
1
1
Operands:
Operation:
Cycles:
Example:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
DECF
CNT,
1
Before Instruction
Status Affected: None
CNT
=
0x01
0
101k
kkkk
kkkk
Encoding:
Z
=
GOTOis an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTOis a
two cycle instruction.
Description:
After Instruction
CNT
=
0x00
1
Z
=
Words:
1
Cycles:
Example:
2
GOTO THERE
After Instruction
PC
=
address (THERE)
DS30254B-page 38
Advance Information
1995 Microchip Technology Inc.
PIC16C52
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
0 ≤ f ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. (k) → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
1101
kkkk
kkkk
0010
10df
ffff
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
IORLW 0x35
Cycles:
Example:
Before Instruction
INCF
CNT,
1
W
=
0x9A
Before Instruction
After Instruction
CNT
=
0xFF
0
W
=
0xBF
Z
=
Z
=
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
INCFSZ
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 31
d
[0,1]
Syntax:
Operation:
(W).OR. (f) → (dest)
Operands:
Status Affected:
Encoding:
Z
d
[0,1]
0001
00df
ffff
Operation:
(f) + 1 → (dest), skip if result = 0
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Status Affected: None
0011
11df
ffff
Encoding:
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
If the result is 0, then the next instruc-
tion, which is already fetched, is dis-
carded and an NOP is executed
instead making it a two cycle instruc-
tion.
IORWF
RESULT, 0
Before Instruction
RESULT =
0x13
0x91
W
=
After Instruction
RESULT =
Words:
1
0x13
0x93
0
Cycles:
Example:
1(2)
W
Z
=
=
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 39
PIC16C52
MOVF
Move f
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] MOVF f,d
f
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Encoding:
Z
0000
001f
ffff
Encoding:
0010
00df
ffff
Move data from the W register to regis-
ter 'f'.
Description:
The contents of register 'f' is moved to
destination 'd'. If 'd' is 0, destination is
the W register. If 'd' is 1, the destination
is file register 'f'. 'd' is 1 is useful to test
a file register since status flag Z is
affected.
Description:
Words:
1
Cycles:
Example:
1
MOVWF TEMP_REG
Before Instruction
Words:
1
1
TEMP_REG
W
=
=
0xFF
0x4F
Cycles:
Example:
MOVF
FSR,
0
After Instruction
TEMP_REG
W
=
=
0x4F
0x4F
After Instruction
W
=
value in FSR register
NOP
No Operation
[ label ] NOP
None
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
No operation
k → (W)
Status Affected: None
0000
0000
0000
Status Affected: None
Encoding:
Description:
Words:
1100
kkkk
kkkk
Encoding:
No operation.
The eight bit literal 'k' is loaded into the
W register. The don’t cares will assem-
ble as 0s.
Description:
1
Cycles:
1
NOP
Example:
Words:
1
Cycles:
Example:
1
MOVLW 0x5A
After Instruction
W
=
0x5A
DS30254B-page 40
Advance Information
1995 Microchip Technology Inc.
PIC16C52
OPTION
Syntax:
Load OPTION Register
[ label ] OPTION
None
RLF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLF f,d
Operands:
Operation:
0 ≤ f ≤ 31
d
[0,1]
(W) → OPTION
Status Affected: None
Operation:
See description below
C
0000
0000
0010
Encoding:
Status Affected:
Encoding:
The content of the W register is loaded
into the OPTION register.
Description:
0011
01df
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
OPTION
Before Instruction
register 'f'
C
W
=
0x07
0x07
After Instruction
OPTION =
Words:
1
Cycles:
Example:
1
RLF
REG1,0
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
Before Instruction
Syntax:
REG1
C
=
=
1110 0110
0
Operands:
Operation:
After Instruction
k → (W);
TOS → PC
REG1
W
C
=
=
=
1110 0110
1100 1100
1
Status Affected: None
1000
kkkk
kkkk
Encoding:
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
d
[0,1]
Words:
1
2
Operation:
See description below
C
Cycles:
Example:
Status Affected:
Encoding:
CALL TABLE ;W contains
;table offset
;value.
0011
00df
ffff
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Description:
•
•
;W now has table
;value.
•
TABLE
ADDWF PC
RETLW k1
RETLW k2
;W = offset
;Begin table
;
register 'f'
C
•
•
Words:
1
•
Cycles:
Example:
1
RETLW kn
; End of table
RRF
REG1,0
Before Instruction
W
=
0x07
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
W
=
value of k8
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 41
PIC16C52
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
Syntax:
[label]
None
[label] SUBWF f,d
SLEEP
Operands:
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
1 → TO;
0 → PD
Operation:
(f) – (W) → (dest)
Status Affected: C, DC, Z
Status Affected: TO, PD
0000
10df
ffff
Encoding:
0000
0000
0011
Encoding:
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
Time-out status bit (TO) is set. The
power down status bit (PD) is cleared.
Description:
The processor is put into SLEEP mode
with the oscillator stopped. See sec-
tion on SLEEP for more details.
Words:
1
1
Words:
1
Cycles:
Cycles:
Example:
1
SUBWF
REG1, 1
Example 1:
SLEEP
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
FF
2
0
; result is negative
DS30254B-page 42
Advance Information
1995 Microchip Technology Inc.
PIC16C52
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 31
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Operands:
Operands:
d
[0,1]
Operation:
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Encoding:
1111
kkkk
kkkk
Status Affected: None
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
0011
10df
ffff
Encoding:
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
Description:
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
W
=
0xB5
SWAPF
REG1,
0
After Instruction
Before Instruction
W
=
0x1A
REG1
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
TRIS
Load TRIS Register
d
[0,1]
Syntax:
[ label ] TRIS
f = 5, 6 or 7
f
Operation:
(W) .XOR. (f) → (dest)
Operands:
Operation:
Status Affected:
Encoding:
Z
(W) → TRIS register f
0001
10df
ffff
Status Affected: None
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0fff
Encoding:
TRIS register 'f' (f = 5, 6, or 7) is loaded
with the contents of the W register
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
TRIS
PORTA
REG,1
XORWF
Before Instruction
Before Instruction
W
=
0XA5
0XA5
REG
=
0xAF
0xB5
W
=
After Instruction
TRISA
=
After Instruction
REG
W
=
=
0x1A
0xB5
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 43
PIC16C52
NOTES:
DS30254B-page 44
Advance Information
1995 Microchip Technology Inc.
PIC16C52
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
9.0
DEVELOPMENT SUPPORT
9.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
(and
better)
machine
platform
and
Microsoft Windows 3.x environment was chosen to
best make these features available to you, the
end user.
• PICMASTER Real-Time In-Circuit Emulator
• PRO MATE Universal Programmer
• PICSTART Low-Cost Prototype Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• MPASM Assembler
The PICMASTER Universal Emulator System consists
primarily of four major components:
• Host-Interface Card
• Emulator Control Pod
• Target-Specific Emulator Probe
• PC-Host Emulation Control Software
• MPSIM Software Simulator
• C Compiler (MP-C)
• Fuzzy logic development system
(fuzzyTECH −MP)
The Windows operating system allows the developer to
take full advantage of the many powerful features and
functions of the PICMASTER system.
9.2
PICMASTER High Performance
Universal In-Circuit Emulator with
MPLAB IDE
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
PC-Host Emulation Control software takes full advan-
tage of Dynamic Data Exchange (DDE), a feature of
Windows. DDE allows data to be dynamically trans-
ferred between two or more Windows programs. With
this feature, data collected with PICMASTER can be
automatically transferred to a spreadsheet or database
program for further analysis.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16C5X, PIC16CXX and
PIC17CXX families. PICMASTER is supplied with the
MPLAB Integrated Development Environment (IDE),
which allows editing, "make" and download, and
source debugging from a single environment. A
PICMASTER System configuration is shown in
Figure 9-1.
Under Windows, as many as four PICMASTER emula-
tors can be run simultaneously from the same PC mak-
ing development of multi-microcontroller systems
possible (e.g., a system containing a PIC16CXX
processor and a PIC17CXX processor).
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new PIC16C5X,
PIC16CXX and PIC17CXX microcontrollers.
The PICMASTER probes specifications are shown in
Table 9-1.
FIGURE 9-1: PICMASTER SYSTEM CONFIGURATION
In-Line
5 VDC
Power Supply
(Optional)
90 - 250 VAC
Windows 3.x
Power Switch
Interchangeable
Emulator Probe
Power Connector
PC Bus
PC-Interface
PICMASTER Emulator Pod
Common Interface Card
PC Compatible Computer
Logic Probes
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 45
PIC16C52
TABLE 9-1:
PICMASTER PROBE
TABLE 9-1:
PICMASTER PROBE
SPECIFICATION
SPECIFICATION (CON’T)
PROBE
PROBE
PICMASTER
PROBE
PICMASTER
Devices
Devices
Maximum Operating
Maximum Operating
PROBE
Frequency
4 MHz
Voltage
Frequency
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
20 MHz
20 MHz
20 MHz
Voltage
(1)
PIC16C52
PROBE-16D
PROBE-16D
PROBE-16D
PROBE-16D
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
PIC16CR64
PIC16C65
PIC16C65A
PIC16C620
PIC16C621
PIC16C622
PIC16C70
PIC16C71
PIC16C71A
PIC16C72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C83
PIC16C84
PIC17C42
PIC17C43
PIC17C44
PROBE-16E
PROBE-16F
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
PIC16C54
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
(1)
PIC16C54A
PIC16CR54
PIC16CR54A
PIC16CR54B
PIC16C55
PROBE-16F
PROBE-16H
PROBE-16H
PROBE-16H
(1)
PROBE-16D
PROBE-16D
(1)
(1)
PROBE-16D
PROBE-16B
PROBE-16B
(1)
PIC16CR55
PIC16C56
PROBE-16D
PROBE-16D
(1)
PROBE-16B
PROBE-16F
(1)
(1)
PIC16CR56
PIC16C57
PROBE-16D
PROBE-16D
PROBE-16D
PROBE-16F
(1)
PIC16CR57A
PIC16CR57B
PIC16C58A
PIC16CR58A
PIC16CR58B
PIC16C61
PROBE-16F
PROBE-16F
(1)
PROBE-16D
PROBE-16D
PROBE-16D
(1)
PROBE-16F
PROBE-16C
PROBE-16C
PROBE-17B
PROBE-17B
PROBE-17B
(1)
PROBE-16D
PROBE-16G
PROBE-16E
PIC16C62
(1)
PIC16C62A
PIC16CR62
PIC16C63
PROBE-16E
PROBE-16E
PROBE-16F
(1)
(1)
Note 1: This PICMASTER probe can be used to
functionally emulate the device listed in the
previous column. Contact your Microchip sales
office for details.
PIC16C64
PROBE-16E
(1)
PIC16C64A
PROBE-16E
DS30254B-page 46
Advance Information
1995 Microchip Technology Inc.
PIC16C52
9.3
PRO MATE Universal Programmer
9.5
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PRO MATE Universal Programmer is
a
full-featured programmer capable of operating in
stand-alone mode as well as PC-hosted mode.
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s
microcontrollers. The microcontrollers supported are:
PIC16C5X (PIC16C52 to PIC16C58A), PIC16C61,
PIC16C62X, PIC16C71, PIC16C8X, PIC17C42,
PIC17C43 and PIC17C44. All necessary hardware and
software is included to run basic demo programs. The
users can program the sample microcontrollers
The PRO MATE has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE can read, verify or program
PIC16C5X, PIC16CXX and PIC17CXX devices. It can
also set configuration and code-protect bits in
this mode.
provided with the PICDEM-1 board, on
a
PRO MATE or PICSTART-16B programmer, and
easily test firmware. The user can also connect the
PICDEM-1 board to the PICMASTER emulator and
download the firmware to the emulator for testing.
Additional prototype area is available for the user to
build some additional hardware and connect it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, a potentiometer for simulated
analog input, push-button switches and eight LEDs
connected to PORTB.
In PC-hosted mode, the PRO MATE connects to the
PC via one of the COM (RS-232) ports. PC based
user-interface software makes using the programmer
simple and efficient. The user interface is full-screen
and menu-based. Full screen display and editing of
data, easy selection of bit configuration and part type,
easy selection of VDD min, VDD max and VPP levels,
load and store to and from disk files (Intel hex format)
are some of the features of the software. Essential
commands such as read, verify, program and blank
check can be issued from the screen. Additionally,
serial programming support is possible where each
part is programmed with a different serial number,
sequential or random.
9.6
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C64, PIC16C65, PIC16C73 and
PIC16C74 microcontrollers. All the necessary
hardware and software is included to run the basic
demonstration programs. The user can program
the sample microcontrollers provided with the
PICDEM-2 board, on a PRO MATE programmer or
PICSTART-16C, and easily test firmware. The
PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding
additional hardware and connecting it to the
microcontroller socket(s). Some of the features include
The PRO MATE has a modular “programming socket
module”. Different socket modules are required for
different processor types and/or package types.
PRO MATE supports all PIC16C5X, PIC16CXX and
PIC17CXX processors.
9.4
PICSTART Low-Cost Development
System
a
RS-232 interface, push-button switches,
a
The PICSTART programmer is an easy to use, very
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. A PC-based user
interface software makes using the programmer simple
and efficient. The user interface is full-screen and
menu-based. PICSTART is not recommended for
production programming.
potentiometer for simulated analog input, a Serial
EEPROM to demonstrate usage of the I C bus and
separate headers for connection to an LCD module
and a keypad.
2
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 47
PIC16C52
9.7
MPLAB Integrated Development
Environment Software
9.8
MPASM Assembler
The MPASM CrossAssembler is a PC-hosted symbolic
assembler. It supports all microcontroller series
including the PIC16C5X, PIC16CXX, and PIC17CXX
families.
The MPLAB Software brings an ease of software
development previously unseen in the 8-bit
microcontroller market. MPLAB is a windows based
application which contains:
MPASM offers full featured Macro capabilities,
conditional assembly, and several source and listing
formats. It generates various object code formats to
support Microchip's development tools as well as third
party programmers.
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator (available soon)
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
MPASM allows full symbolic debugging from
the
Microchip Universal Emulator System
(PICMASTER).
MPASM has the following features to assist in
developing software for specific use applications.
• Extensive on-line help
MPLAB allows you to:
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• edit your source files (either assembly or "C")
• one touch assemble (or compile) and download to
PIC16/17 tools (automatically updates all project
information)
• debug using:
- source files
- absolute listing file
• transfer data dynamically via DDE (soon to be
replaced by OLE)
• Macro assembly capability
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal
source and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source
code shorter and more maintainable.
• run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
(available soon) allows a consistent platform and the
ability to easily switch from the low cost simulator to the
full featured emulator with minimal retraining due to
development tools.
• Data Directives are those that control the
allocation of memory and provide a way to refer to
data items symbolically (i.e., by meaningful
names).
• Control Directives control the MPASM listing
display. They allow the specification of titles and
sub-titles, page ejects and other listing control.
This eases the readability of the printed
output file.
• Conditional Directives permit sections of
conditionally assembled code. This is most useful
where additional functionality may wished to be
added depending on the product (less
functionality for the low end product, then for the
high end product). Also this is very helpful in the
debugging of a program.
• Macro Directives control the execution and data
allocation within macro body definitions. This
makes very simple the re-use of functions in a
program as well as between programs.
DS30254B-page 48
Advance Information
1995 Microchip Technology Inc.
PIC16C52
9.9
MPSIM Software Simulator
9.11
fuzzyTECH-MP Fuzzy Logic
Development System
The MPSIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The
input/output radix can be set by the user and the
execution can be performed in; single step, execute
until break, or in a trace mode. MPSIM fully supports
symbolic debugging using MP-C and MPASM. The
Software Simulator offers the low cost flexibility to
develop and debug code outside of the laboratory
environment making it an excellent multi-project
software development tool.
fuzzyTECH-MP fuzzy logic development tool is
available in two versions - a low cost introductory
version, MP Explorer, for designers to gain
comprehensive working knowledge of fuzzy logic
system design; and full-featured version,
a
a
fuzzyTECH-MP, edition for implementing more
complex systems.
Both versions include Microchip’s fuzzyLAB
demonstration board for hands-on experience with
fuzzy logic systems implementation.
9.12
Development Systems
For convenience, the development tools are packaged
into comprehensive systems as listed in Table 9-2.
9.10
MP-C C Compiler
The MP-C Code Development System is a complete 'C'
compiler and integrated development environment for
Microchip’s PIC16/17 family of microcontrollers. The
compiler provides powerful integration capabilities and
ease of use not found with other compilers.
For easier source level debugging, the compiler
provides symbol information that is compatible with the
PICMASTER Universal Emulator memory display
(PICMASTER emulator software versions 1.13
and later).
The MP-C Code Development System is supplied
directly by Byte Craft Limited of Waterloo, Ontario,
Canada. If you have any questions, please contact
your regional Microchip FAE or Microchip technical
support personnel at (602) 786-7627.
TABLE 9-2:
Item
DEVELOPMENT SYSTEM PACKAGES
Name
System Description
1.
2.
3.
PICMASTER System
PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler,
Software Simulator, Samples and your choice of Target Probe.
PICSTART System
PRO MATE System
PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator
and Samples.
PRO MATE Universal Programmer, full featured stand-alone or PC-hosted
programmer, Assembler, Simulator
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 49
PIC16C52
NOTES:
DS30254B-page 50
Advance Information
1995 Microchip Technology Inc.
PIC16C52
10.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Ambient Temperature under bias...........................................................................................................–55°C to +125°C
Storage Temperature .............................................................................................................................–65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................. 0 V to +7.5 V
(2)
Voltage on MCLR with respect to VSS ....................................................................................................... 0 V to +14 V
Voltage on all other pins with respect to VSS ............................................................................... –0.6 V to (VDD + 0.6 V)
(1)
Total Power Dissipation ....................................................................................................................................800 mW
Max. Current out of VSS pin ..................................................................................................................................150 mA
Max. Current into VDD pin .......................................................................................................................................50 mA
Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA
Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................10 mA
Max. Output Current sourced by any I/O pin...........................................................................................................10 mA
Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................10 mA
Max. Output Current sunk by a single I/O port (PORTA, B or C)............................................................................10 mA
Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS
†
NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 51
PIC16C52
10.1
DC Characteristics: PIC16C52-04 (Commercial)
PIC16C52-I04 (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
(1)
Characteristic
Sym Min
Typ
Max Units
Conditions
Supply Voltage
VDD
VDR
IDD
3.0
6.25
V
V
FOSC = DC to 4 MHz
(2)
RAM Data Retention Voltage
1.5*
Device in SLEEP Mode
FOSC = 4 MHz, VDD = 5.5 V
(3,4)
Supply Current
1.8
3.3
mA
(5)
Power Down Current
IPD
Commercial
Industrial
0.6
0.6
9*
12*
µA
µA
VDD = 3.0 V
VDD = 3.0 V
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
Vss, T0CKI = VDD, MCLR = VDD.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: For RC option, does not include current through Rext. The current through the resistor can be estimated by
the formula: IR = VDD/2Rext (mA) with Rext in kΩ.
5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30254B-page 52
Advance Information
1995 Microchip Technology Inc.
PIC16C52
10.2
DC Characteristics: PIC16C52-04 (Commercial)
PIC16C52-I04 (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
DC Characteristics
All Pins Except
Power Supply Pins
Operating Voltage VDD range is described in Section 10.1.
(1)
Characteristic
Sym
Min
Typ
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
VIL
VSS
VSS
VSS
VSS
VSS
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
(4)
RC option only
XT option
Input High Voltage
I/O ports
VIH
(5)
0.45 VDD
2.0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
(5)
4.0 V < VDD ≤ 5.5 V
VDD > 5.5 V
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
(4)
RC option only
XT option
Hysteresis of Schmitt
Trigger inputs
VHYS
IIL
0.15VDD*
V
(2,3)
Input Leakage Current
For VDD ≤ 5.5 V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25 V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT option
I/O ports
–1
–5
0.5
+1
µA
MCLR
µA
µA
µA
µA
0.5
0.5
0.5
+5
+3
+3
T0CKI
OSC1
–3
–3
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
VOH
0.6
0.6
V
V
IOL = 2.0 mA, VDD = 4.5 V
IOL = 1.6 mA, VDD = 4.5 V,
RC option
Output High Voltage
(3)
I/O ports
VDD – 0.7
VDD – 0.7
V
V
IOH = –2.0 mA, VDD = 4.5 V
IOH = –1.0 mA, VDD = 4.5 V,
RC option
OSC2/CLKOUT
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C52 be
driven with external clock in RC mode.
5: The user may use the better of the two specifications.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 53
PIC16C52
10.3
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
oscillator
OSC1
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
t0
T0CKI
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC16C52
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT mode when
external clock is used to
drive OSC1
VSS
DS30254B-page 54
Advance Information
1995 Microchip Technology Inc.
PIC16C52
10.4
Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C52
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C52
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1.
Parameter
(1)
No.
Sym
Characteristic
Min Typ
Max Units
Conditions
(2)
FOSC
External CLKIN Frequency
DC
DC
DC
0.1
250
250
250
250
—
—
—
4
4
MHz RC osc mode
MHz XT osc mode
(2)
Oscillator Frequency
—
4
MHz RC osc mode
MHz XT osc mode
—
4
(2)
1
TOSC
External CLKIN Period
—
—
ns
ns
ns
ns
—
ns
ns
RC osc mode
XT osc mode
RC osc mode
XT osc mode
—
—
(2)
Oscillator Period
—
—
—
10,000
—
(3)
2
3
4
TCY
Instruction Cycle Time
4/FOSC
—
TosL, TosH Clock in (OSC1) Low or High Time
TosR, TosF Clock in (OSC1) Rise or Fall Time
50*
—
—
XT oscillator
XT oscillator
—
25*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard operating condi-
tions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 55
PIC16C52
FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C52
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
18
14
19
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C52
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1.
Parameter
(1)
No.
Sym
Characteristic
(2)
Min
Typ
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL
TosH2ckH
TckR
OSC1↑ to CLKOUT↓
—
15
15
5
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
OSC1↑ to CLKOUT↑
—
(2)
CLKOUT rise time
—
(2)
TckF
CLKOUT fall time
—
5
(2)
CLKOUT↓ to Port out valid
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
—
—
—
—
—
—
(2)
Port in valid before CLKOUT↑
(2)
0.25 TCY+30*
Port in hold after CLKOUT↑
OSC1↑ (Q1 cycle) to Port out valid
0*
—
—
(3)
100*
—
OSC1↑ (Q2 cycle) to Port input invalid (I/O in
TBD
hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
(3)
20
21
TioR
TioF
Port output rise time
—
—
10
10
25**
25**
ns
ns
(3)
Port output fall time
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 10-1 for loading conditions.
DS30254B-page 56
Advance Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 10-4: RESET AND DEVICE RESET TIMER TIMING - PIC16C52
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 10-3: RESET AND DEVICE RESET TIMER - PIC16C52
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1.
Parameter
No.
(1)
Sym Characteristic
Min Typ
Max Units
Conditions
30
32
34
TmcL MCLR Pulse Width (low)
100*
9*
—
18*
—
—
ns VDD = 5 V
TDRT Device Reset Timer Period
TioZ I/O Hi-impedance from MCLR Low
30*
ms VDD = 5 V (Commercial)
ns
—
100*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design
guidance only and are not tested.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 57
PIC16C52
FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C52
T0CKI
40
41
42
TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16C52
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial),
–40°C ≤ TA ≤ +85°C (industrial),
Operating Voltage VDD range is described in Section 10.1.
Parameter
(1)
Sym Characteristic
Min
Typ
Max Units Conditions
No.
40
Tt0H T0CKI High Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS30254B-page 58
Advance Information
1995 Microchip Technology Inc.
PIC16C52
11.0 DC AND AC CHARACTERISTICS
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some
graphs or tables the data presented are outside specified operating range (e.g., outside specified VDD range). This is
for information only and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
Rext ≥ 10 kΩ
Cext = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
VDD = 5.5 V
VDD = 3.5 V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 11-1: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5 V, 25°C
Cext
Rext
20 pF
3.3 k
5 k
4.973 MHz
3.82 MHz
2.22 MHz
262.15 kHz
1.63 MHz
1.19 MHz
684.64 kHz
71.56 kHz
660 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10 k
100 k
3.3 k
5 k
100 pF
300 pF
10 k
100 k
3.3 k
5.0 k
10 k
160 k
484.1 kHz
267.63 kHz
29.44 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5 V.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 59
PIC16C52
FIGURE 11-2: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
FIGURE 11-3: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
CEXT = 20PF
CEXT = 100 PF
5.5
1.8
R = 3.3k
R = 3.3k
5.0
1.6
4.5
1.4
R = 5k
R = 5k
4.0
1.2
1.0
3.5
3.0
0.8
R = 10k
R = 10k
2.5
0.6
Measured on DIP Packages, T = 25°C
2.0
0.4
Measured on DIP Packages, T = 25°C
0.2
1.5
R = 100k
0.0
1.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
R = 100k
0.5
FIGURE 11-4: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
0.0
CEXT = 300 PF
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
800
700
R = 3.3k
600
R = 5k
500
400
300
200
100
0
R = 10k
Measured on DIP Packages, T = 25°C
R = 100k
5.5 6.0
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
DS30254B-page 60
Advanced Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 11-5: TYPICAL IPD vs. VDD
FIGURE 11-6: MAXIMUM IPD vs. VDD
100
2.5
2.0
+125˚C
+85˚C
T = 25°C
1.5
10
+70˚C
0˚C
1.0
0.5
–40˚C
–55˚C
1
0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 61
PIC16C52
FIGURE 11-7: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 11-8: VIH, VIL OF MCLR,T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note: These input pins have Schmitt Trigger input buffers.
FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30254B-page 62
Advance Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 11-10: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25°C)
10
1.0
0.1
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 11-11: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)
10
1.0
7.0
6.5
6.0
0.1
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 63
PIC16C52
FIGURE 11-12: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55°C TO +125°C)
10
1.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.1
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 11-13: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR vs. VDD
TABLE 11-2: INPUT CAPACITANCE FOR
PIC16C52
Typical Capacitance (pF)
Pin
2500
18L PDIP
18L SOIC
RA port
RB port
5.0
4.3
Max –40°C
2000
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
1500
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
Typ +25°C
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
1000
Min +85°C
500
0
2
3
4
5
6
7
VDD (Volts)
DS30254B-page 64
Advance Information
1995 Microchip Technology Inc.
PIC16C52
FIGURE 11-14: IOH vs. VOH, VDD = 3 V
FIGURE 11-16: IOL vs. VOL, VDD = 3 V
0
45
40
35
Max –40°C
–5
Min +85°C
30
25
–10
Typ +25°C
Typ +25°C
Min +85°C
–15
20
Max –40°C
15
10
–20
5
0
–25
0
0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
0.0
0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 11-17: IOL vs. VOL, VDD = 5 V
FIGURE 11-15: IOH vs. VOH, VDD = 5 V
90
0
Max –40°C
80
70
Min +85°C
–10
60
50
Typ +25°C
–20
Typ +25°C
40
Min +85°C
30
20
–30
Max –40°C
10
0
–40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 65
PIC16C52
NOTES:
DS30254B-page 66
Advanced Information
1995 Microchip Technology Inc.
PIC16C52
12.0 PACKAGING INFORMATION
12.1
Package Marking Information
18-Lead PDIP
Example
MMMMMMMMMMMMXXX
MMMMMMMMXXXXXXX
PIC16C52-
04I/P456
9523 CBA
AABB CDE
18-Lead SOIC
Example
MMMMMMMMM
XXXXXXXXX
PIC16C52-
04I/S0218
AABB CDE
9518 CDK
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
S = Tempe, Arizona, U.S.A.
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev#, and assembly code. For OTP marking
beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in
QTP price.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 67
PIC16C52
12.2
18-Lead Plastic Dual In-Line (PDIP) - 300 mil
N
α
C
E1
E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A2
A1
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
10°
4.064
–
0°
10°
0.160
–
A
–
–
A1
A2
B
0.381
3.048
0.355
1.524
0.203
22.479
20.320
7.620
6.096
2.489
7.620
7.874
3.048
18
0.015
0.120
0.014
0.060
0.008
0.885
0.800
0.300
0.240
0.098
0.300
0.310
0.120
18
3.810
0.559
1.524
0.381
23.495
20.320
8.255
7.112
2.591
7.620
9.906
3.556
18
0.150
0.022
0.060
0.015
0.925
0.800
0.325
0.280
0.102
0.300
0.390
0.140
18
B1
C
Reference
Typical
Reference
Typical
D
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
0.889
0.127
–
0.035
0.005
–
S1
–
–
DS30254B-page 68
Advance Information
1995 Microchip Technology Inc.
PIC16C52
12.3
18-Lead Plastic Surface Mount (SOIC) - 300 mil
e
B
h x 45°
N
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Base
Plane
CP
Seating
Plane
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Max
Inches
Symbol
Min
0°
Notes
Min
Max
Notes
α
A
8°
0°
8°
2.362
0.101
0.355
0.241
11.353
7.416
1.270
10.007
0.381
0.406
18
2.642
0.300
0.483
0.318
11.735
7.595
1.270
10.643
0.762
1.143
18
0.093
0.004
0.014
0.009
0.447
0.292
0.050
0.394
0.015
0.016
18
0.104
0.012
0.019
0.013
0.462
0.299
0.050
0.419
0.030
0.045
18
A1
B
C
D
E
e
Reference
Reference
H
h
L
N
CP
–
0.102
–
0.004
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 69
PIC16C52
NOTES:
DS30254B-page 70
Advance Information
1995 Microchip Technology Inc.
PIC16C52
APPENDIX A: COMPATIBILITY
APPENDIX B: WHAT’S NEW
To convert code written for PIC16CXX to PIC16C5X,
the user should take the following steps:
This is the first version of the PIC16C52 data sheet. It
is based on the PIC16C5X data sheet.
1. Check any CALL, GOTO or instructions that
modify the PC to determine if any program
memory page select operations (PA2, PA1, PA0
bits) need to be made.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any special function register page
switching. Redefine data variables to reallocate
them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to proper value for
processor used.
6. Remove any use of the ADDLW and SUBLW
instructions.
7. Rewrite any code segments that use interrupts.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 71
PIC16C52
NOTES:
DS30254B-page 72
Advance Information
1995 Microchip Technology Inc.
PIC16C52
APPENDIX C:PIC16/17 MICROCONTROLLERS
TABLE C-1:
PIC16C5X FAMILY OF DEVICES
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 73
PIC16C52
TABLE C-2:
PIC16C62X FAMILY OF DEVICES
DS30254B-page 74
Advance Information
1995 Microchip Technology Inc.
PIC16C52
TABLE C-3:
PIC16C6X FAMILY OF DEVICES
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 75
PIC16C52
TABLE C-4:
PIC16C7X FAMILY OF DEVICES
DS30254B-page 76
Advance Information
1995 Microchip Technology Inc.
PIC16C52
TABLE C-5:
PIC16C8X FAMILY OF DEVICES
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 77
PIC16C52
TABLE C-6:
PIC17CXX FAMILY OF DEVICES
DS30254B-page 78
Advance Information
1995 Microchip Technology Inc.
PIC16C52
C.1
Pin Compatibility
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket (ex.,
PIC16C56 and PIC16C61 devices). Not all devices in
the same package size are pin compatible; for
example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE C-7:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC16C52, PIC16C54, PIC16C54A,
PIC16CR54, PIC16CR54A, PIC16CR54B,
PIC16C56, PIC16CR56,
18 pin
(20 pin)
PIC16C58A, PIC16CR58A, PIC16CR58B,
PIC16C61,
PIC16C620, PIC16C621, PIC16C622,
PIC16C70, PIC16C71, PIC16C71A
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
PIC16C55, PIC16CR55,
PIC16C57, PIC16CR57A, PIC16CR57B
28 pin
28 pin
40 pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17C43, PIC17C44
40 pin
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 79
PIC16C52
NOTES:
DS30254B-page 80
Advance Information
1995 Microchip Technology Inc.
PIC16C52
M
INDEX
MCLR ................................................................................ 26
Memory Organization ........................................................ 11
Data Memory ............................................................. 11
Program Memory ....................................................... 11
MPASM Assembler ..................................................... 45, 48
MP-C C Compiler .............................................................. 49
MPSIM Software Simulator ......................................... 45, 49
A
Absolute Maximum Ratings ............................................... 51
ALU ...................................................................................... 7
Architectural Overview ......................................................... 7
Assembler .......................................................................... 48
B
O
Block Diagram
One-Time-Programmable (OTP) Devices ............................5
OPTION Register .............................................................. 14
OSC selection .................................................................... 23
Oscillator Configurations ................................................... 24
Oscillator Types
On-Chip Reset Circuit ................................................ 27
PIC16C52 .................................................................... 8
Timer0 ........................................................................ 19
Timer0 Prescaler ........................................................ 22
Brown-Out Protection Circuit ............................................. 31
RC ............................................................................. 24
XT .............................................................................. 24
C
C Compiler (MP-C) ...................................................... 45, 49
Carry .................................................................................... 7
Clocking Scheme ............................................................... 10
Code Protection ........................................................... 23, 31
Configuration Bits ............................................................... 23
Configuration Word - PIC16C52 ........................................ 23
P
Packaging Information ....................................................... 67
18-Lead Plastic Dual In-Line (PDIP) - 300 mil ........... 68
18-Lead Plastic Surface Mount (SOIC) - 300 mil ...... 69
PCL .................................................................................... 26
PIC16C52 DC and AC Characteristics .............................. 59
PICDEM-1 Low-Cost PIC16/17 Demo Board .............. 45, 47
PICDEM-2 Low-Cost PIC16CXX Demo Board ............ 45, 47
PICMASTER Probes ......................................................... 46
PICMASTER System Configuration .................................. 45
PICMASTER RT In-Circuit Emulator .............................. 45
PICSTART Low-Cost Development System ............. 45, 47
Pin Compatible Devices .................................................... 79
Pinout Description ................................................................9
POR
Oscillator Start-Up Timer (OST) .................... 23, 28, 30
PD ........................................................................ 26, 30
Power-On Reset (POR) ................................. 23, 26, 28
TO ........................................................................ 26, 30
PORTA ........................................................................ 17, 26
PORTB ........................................................................ 17, 26
Power-Down Mode ............................................................ 31
Prescaler ........................................................................... 22
PRO MATE Universal Programmer .......................... 45, 47
D
DC Characteristics ....................................................... 52, 53
Development Support ........................................................ 45
Development Systems ....................................................... 49
Development Tools ............................................................ 45
Device Varieties ................................................................... 5
Digit Carry ............................................................................ 7
Dynamic Data Exchange (DDE) ........................................ 45
E
Electrical Characteristics .................................................... 51
External Power-On Reset Circuit ....................................... 28
F
Family of Devices ................................................................. 4
PIC16C5X .................................................................. 73
PIC16C62X ................................................................ 74
PIC16C6X .................................................................. 75
PIC16C7X .................................................................. 76
PIC16C8X .................................................................. 77
PIC17CXX .................................................................. 78
FSR .............................................................................. 16, 26
Fuzzy Logic Dev. System (fuzzyTECH -MP) ............. 45, 49
Q
Quick-Turnaround-Production (QTP) Devices ......................5
R
RC Oscillator ..................................................................... 25
Read Modify Write ............................................................. 18
Reset ........................................................................... 23, 26
Reset on Brown-Out .......................................................... 31
I
I/O Interfacing .................................................................... 17
I/O Ports ............................................................................. 17
I/O Programming Considerations ....................................... 18
ID Locations ................................................................. 23, 31
INDF ............................................................................. 16, 26
Indirect Data Addressing .................................................... 16
Instruction Cycle ................................................................ 10
Instruction Flow/Pipelining ................................................. 10
Instruction Set Summary .................................................... 34
Integrated ........................................................................... 48
S
Serialized Quick-Turnaround-Production (SQTP) Devices ..5
SLEEP ......................................................................... 23, 31
Software Simulator (MPSIM) ............................................. 49
Special Features of the CPU ............................................. 23
STATUS ........................................................................ 7, 26
STATUS Word Register .................................................... 13
Summary of Port Regiters ................................................. 17
L
Loading of PC .................................................................... 15
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 81
PIC16C52
T
LIST OF EXAMPLES
Timer0 ................................................................................19
Timer0 Module ...........................................................19
Timer0 with External Clock ........................................21
TMR0 Register ...........................................................19
Timing Diagrams and Specifications ..................................55
Timing Parameter Symbology and Load Conditions ..........54
TRIS Registers ...................................................................17
Example 3-1: Instruction Pipeline Flow ............................ 10
Example 4-1: Indirect Addressing..................................... 16
Example 4-2: How To Clear RAM Using Indirect Address-
ing............................................................... 16
Example 5-1: Read-Modify-Write Instructions on an
I/O Port....................................................... 18
W
W ........................................................................................26
Wake-up from SLEEP ........................................................31
Z
Zero bit .................................................................................7
DS30254B-page 82
Advance Information
1995 Microchip Technology Inc.
PIC16C52
Figure 11-8: VIH, VIL of MCLR, T0CKI and OSC1
LIST OF FIGURES
(in RC Mode) vs. VDD .................................... 62
Figure 11-9: VTH (Input Threshold Voltage) of OSC1 Input
(in XT, HS, and LP modes) vs. VDD .............. 62
Figure 11-10:Typical IDD vs. Frequency (External Clock,
25°C) ............................................................. 63
Figure 11-11:Maximum IDD vs. Frequency
(External Clock, –40°C to +85°C).................. 63
Figure 11-12:Maximum IDD vs. Frequency
Figure 3-1: PIC16C52 Block Diagram................................ 8
Figure 3-2: Clock/Instruction Cycle .................................. 10
Figure 4-1: PIC16C52 Program Memory Map and Stack. 11
Figure 4-2: PIC16C52 Register File Map ......................... 11
Figure 4-3: STATUS Register (Address:03h)................... 13
Figure 4-4: OPTION Register........................................... 14
Figure 4-5: Loading of PC
(External Clock –55°C to +125°C)................. 64
Branch Instructions -
Figure 11-13:Transconductance (gm) of XT Oscillator vs.
VDD ................................................................ 64
Figure 11-14:IOH vs. VOH, VDD = 3 V.................................. 65
Figure 11-15:IOH vs. VOH, VDD = 5 V.................................. 65
Figure 11-16:IOL vs. VOL, VDD = 3 V................................... 65
Figure 11-17:IOL vs. VOL, VDD = 5 V................................... 65
PIC16C52 ...................................................... 15
Figure 4-6: Direct/Indirect Addressing.............................. 16
Figure 5-1: Equivalent Circuit
for a Single I/O Pin......................................... 17
Figure 5-2: Successive I/O Operation .............................. 18
Figure 6-1: Timer0 Block Diagram ................................... 19
Figure 6-2: Electrical Structure of T0CKI Pin ................... 19
Figure 6-3: Timer0 Timing:
Internal Clock/No Prescale ............................ 20
Figure 6-4: Timer0 Timing:
Internal Clock/Prescale 1:2............................ 20
Figure 6-5: Timer0 Timing With External Clock................ 21
Figure 6-6: Block Diagram of the Timer0 Prescaler ......... 22
Figure 7-1: Configuration Word for PIC16C52 ................. 23
Figure 7-2: Crystal Operation or Ceramic Resonator
(XT OSC Configuration)................................ 24
Figure 7-3: External Clock Input Operation
(XT OSC Configuration)................................. 24
Figure 7-4: External Parallel Resonant Crystal Oscillator
Circuit............................................................. 25
Figure 7-5: External Series Resonant Crystal Oscillator
Circuit............................................................. 25
Figure 7-6: RC Oscillator Mode........................................ 25
Figure 7-7: Simplified Block Diagram of On-Chip Reset
Circuit............................................................. 27
Figure 7-8: ElectriCal Structure of MCLR/VPP Pin ........... 28
Figure 7-9: External Power-On Reset Circuit
(For Slow VDD Power-Up).............................. 28
Figure 7-10: Time-Out Sequence on Power-Up
(MCLR Not Tied to VDD) ................................ 29
Figure 7-11: Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Fast VDD Rise Time..... 29
Figure 7-12: Time-Out Sequence on Power-Up
(MCLR Tied to VDD): Slow VDD Rise Time .... 29
Figure 7-13: Brown-Out Protection Circuit 1 ...................... 31
Figure 7-14: Brown-Out Protection Circuit 2 ...................... 31
Figure 8-1: General Format for Instructions ..................... 33
Figure 9-1: PICMASTER System Configuration............... 45
Figure 10-1: Load Conditions - PIC16C52 ......................... 54
Figure 10-2: External Clock Timing - PIC16C52 ................ 55
Figure 10-3: CLKOUT and I/O Timing - PIC16C52............ 56
Figure 10-4: Reset and Device Reset Timer Timing -
PIC16C52 ...................................................... 57
Figure 10-5: Timer0 Clock Timings - PIC16C52 ................ 58
Figure 11-1: Typical RC Oscillator Frequency vs.
Temperature .................................................. 59
Figure 11-2: Typical RC Oscillator Frequency vs. VDD,
CEXT = 20PF................................................... 60
Figure 11-3: Typical RC Oscillator Frequency vs. VDD,
CEXT = 100 PF................................................ 60
Figure 11-4: Typical RC Oscillator Frequency vs. VDD,
CEXT = 300 PF................................................ 60
Figure 11-5: Typical IPD vs. VDD ........................................ 61
Figure 11-6: Maximum IPD vs. VDD .................................... 61
Figure 11-7: VTH (Input Threshold Voltage) of I/O Pins vs.
VDD ................................................................ 62
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 83
PIC16C52
LIST OF TABLES
Table 1-1: PIC16C5X Family of Devices...........................4
Table 3-1: PIC16C52 Pinout Description ..........................9
Table 4-1: Special Function Register Summary..............12
Table 5-1: Summary of Port Registers............................17
Table 6-1: Registers Associated With Timer0.................20
Table 7-1: Capacitor Selection
For Ceramic Resonators - PIC16C52............24
Table 7-2: Capacitor Selection
For Crystal Oscillator - PIC16C52..................24
Table 7-3: Reset Conditions for Special Registers .........26
Table 7-4: Reset Conditions for All Registers .................26
Table 7-5: TO/PD Status After Reset..............................30
Table 7-6: Events Affecting TO/PD Status Bits...............30
Table 8-1: OPCODE Field Descriptions..........................33
Table 8-2: Instruction Set Summary................................34
Table 9-1: PICMASTER Probe Specification..................46
Table 9-2: Development System Packages....................49
Table 10-1: External Clock Timing Requirements -
PIC16C52 ......................................................55
Table 10-2: CLKOUT and I/O Timing Requirements -
PIC16C52 ......................................................56
Table 10-3: Reset and Device Reset Timer - PIC16C52 ..57
Table 10-4: Timer0 Clock Requirements - PIC16C52.......58
Table 11-1: RC Oscillator Frequencies.............................59
Table 11-2: Input Capacitance for PIC16C52 ...................64
Table C-1: PIC16C5X Family of Devices.........................73
Table C-2: PIC16C62X Family of Devices.......................74
Table C-3: PIC16C6X Family of Devices.........................75
Table C-4: PIC16C7X Family of Devices.........................76
Table C-5: PIC16C8X Family of Devices.........................77
Table C-6: PIC17CXX Family of Devices ........................78
Table C-7: Pin Compatible Devices.................................79
DS30254B-page 84
Advance Information
1995 Microchip Technology Inc.
PIC16C52
CONNECTING TO MICROCHIP BBS
Trademarks:
Connect worldwide to the Microchip BBS using the
CompuServe communications network. In most
cases a local call is your only expense. The Microchip
BBS connection does not use CompuServe
membership services, therefore, you do not need
CompuServe membership to join Microchip's BBS.
PICMASTER and PICSTART are trademarks of
Microchip Technology Incorporated. PIC is a
registered trademark of Microchip Technology
Incorporated in the U.S.A.
PRO MATE, fuzzyLAB, the Microchip logo and
name are trademarks of Microchip Technology
Incorporated.
There is no charge for connecting to the BBS, except
toll charge to CompuServe access number, where
applicable. You do not need to be a CompuServe
member to take advantage of this connection (you
never actually log in to CompuServe).
fuzzyTECH is a registered trademark of Inform
Software Corporation.
2
I C is a trademark of Philips Corporation.
The procedure to connect will vary slightly from
country to country. Please check with your local
CompuServe agent for details if you have a problem.
CompuServe service allows multiple users at baud
rates up to 14,400 bps.
IBM, IBM PC-AT are registered trademarks of
International Business Machines Corporation.
Pentium is a trademark of Intel Corporation.
MS-DOS and Microsoft Windows are registered
trademarks of Microsoft Corporation. Windows is
a trademark of Microsoft Corporation.
The following connect procedure applies in most
locations:
CompuServe is a registered trademark of
CompuServe Incorporated.
1. Set your modem to 8 bit, No parity, and One stop
(8N1). This is not the normal CompuServe
setting which is 7E1.
All other trademarks mentioned herein are the
property of their respective companies.
2. Dial your local CompuServe access number.
3. Depress <ENTER > and a garbage string will
appear because CompuServe is expecting a
7E1 setting.
4. Type +, depress <ENTER > and Host Name:
will appear.
5. Type MCHIPBBS, depress < ENTER > and
you will be connected to the Microchip BBS.
In the United States, to find CompuServe's
phone number closest to you, set your modem to
7E1 and dial (800) 848-4480 for 300-2400 baud or
(800) 331-7166 for 9600-14400 baud connection. After
the system responds with Host Name:
Type, NETWORK, depress < ENTER > and follow
CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 457-1550 for your local CompuServe
number.
ACCESS TO THE INTERNET
Microchip’s current WWW address is listed on the
back page of this data sheet under Worldwide Sales &
Service - Americas - Corporate Office.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 85
PIC16C52
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product.
If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can
better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device:
Literature Number:
PIC16C52
Questions:
1. What are the best features of this document?
DS30254B
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30254B-page 86
Advance Information
1995 Microchip Technology Inc.
PIC16C52
PIC16C52 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Oscillator Temperature Package
Type Range
Pattern
(2)
Examples:
Device
PIC16C52, PIC16C52T
= 4 MHz
0°C to +70°C (Commerciall)
a) PIC16C52 - 04/PXXX = "RC" oscillator,
commercial temp., PDIP, QTP pattern.
Frequency Range 04
(1)
Temperature
Range
b
I
=
b) PIC16C52 - 04I/SO = "XT" oscillator,
industrial temp., SOIC (OTP device)
= -40°C to +85°C (Industrial)
Package
P
SO
= PDIP
Note 1: b = blank
= SOIC (Gull Wing, 300 mil body)
2: T = in tape and reel -
SOIC packages only.
Pattern
3-digit Pattern Code for QTP (blank otherwise)
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1995 Microchip Technology Inc.
Advance Information
DS30254B-page 87
WORLDWIDE SALES & SERVICE
AMERICAS
ASIA/PACIFIC
EUROPE
Corporate Office
Hong Kong
United Kingdom
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.mchip.com/microchip
Microchip Technology
Unit No. 3002-3004, Tower 1
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 0 1628 851077 Fax: 44 0 1628 850259
France
Korea
Arizona Microchip Technology SARL
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Atlanta
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508 480-9990
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
Dayton
Microchip Technology Inc.
Suite 150
Italy
Fax: 508 480-8575
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Pegaso Ingresso No. 2
Via Paracelso 23, 20041
Agrate Brianza (MI) Italy
Tel: 39 039 689 9939 Fax: 39 039 689 9883
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Two Prestige Place
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
12/04/95
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408 436-7950 Fax: 408 436-7955
All rights reserved. 1995, Microchip Technology Incorporated, USA.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or
otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise,
under any intellectual property rights.The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved.All other trademarks mentioned herein are the property of
their respective companies.
DS30254B-page 88
Advance Information
1995 Microchip Technology Inc.
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