PIC16C55-XTI/SOXXX [MICROCHIP]
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC;
| 型号： | PIC16C55-XTI/SOXXX |
| 厂家： | 
MICROCHIP |
| 描述： | IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总194页 (文件大小：2646K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C5X
Data Sheet
EPROM/ROM-Based 8-bit CMOS
Microcontroller Series
2002 Microchip Technology Inc.
Preliminary
DS30453D
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
DS30453D - page ii
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
EPROM/ROM-Based 8-bit CMOS Microcontroller Series
• 12-bit wide instructions
Devices Included in this Data Sheet:
• 8-bit wide data path
• PIC16C54
• Seven or eight special function hardware registers
• PIC16CR54
• Two-level deep hardware stack
• PIC16C55
• Direct, indirect and relative addressing modes for
• PIC16C56
data and instructions
• PIC16CR56
• PIC16C57
• PIC16CR57
• PIC16C58
• PIC16CR58
Peripheral Features:
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Power-on Reset (POR)
Note: PIC16C5X refers to all revisions of the part
(i.e., PIC16C54 refers to PIC16C54,
PIC16C54A, and PIC16C54C), unless
specifically called out otherwise.
• Device Reset Timer (DRT)
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• Programmable Code Protection
• Power saving SLEEP mode
• Selectable oscillator options:
High-Performance RISC CPU:
• Only 33 single word instructions to learn
- RC:
- XT:
- HS:
- LP:
Low cost RC oscillator
• All instructions are single cycle except for pro-
gram branches which are two-cycle
Standard crystal/resonator
High speed crystal/resonator
Power saving, low frequency crystal
• Operating speed: DC - 40 MHz clock input
DC - 100 ns instruction cycle
EPROM/
ROM
CMOS Technology:
Device
PIC16C54
Pins I/O
RAM
• Low power, high speed CMOS EPROM/ROM tech-
nology
18
18
18
18
18
28
28
18
18
18
28
28
28
18
18
12
12
12
12
12
20
20
12
12
12
20
20
20
12
12
512
512
512
512
512
512
512
1K
25
25
25
25
25
24
24
25
25
25
72
72
72
73
73
PIC16C54A
PIC16C54C
PIC16CR54A
PIC16CR54C
PIC16C55
• Fully static design
• Wide operating voltage and temperature range:
- EPROM Commercial/Industrial 2.0V to 6.25V
- ROM Commercial/Industrial 2.0V to 6.25V
- EPROM Extended 2.5V to 6.0V
- ROM Extended 2.5V to 6.0V
PIC16C55A
PIC16C56
• Low power consumption
PIC16C56A
PIC16CR56A
PIC16C57
1K
- < 2 mA typical @ 5V, 4 MHz
1K
- 15 µA typical @ 3V, 32 kHz
2K
- < 0.6 µA typical standby current
(with WDT disabled) @ 3V, 0°C to 70°C
PIC16C57C
PIC16CR57C
PIC16C58B
PIC16CR58B
2K
2K
2K
Note: In this document, figure and table titles
refer to all varieties of the part number indi-
cated, (i.e., The title “Figure 15-1: Load
Conditions For Device Timing Specifica-
2K
tions
-
PIC16C54A”, also refers to
PIC16LC54A and PIC16LV54A parts),
unless specifically called out otherwise.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 1
PIC16C5X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
PDIP, SOIC, Windowed CERDIP
18
17
16
15
14
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
T0CKI
•1
•1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
RA2
2
3
4
5
6
7
8
9
RA3
T0CKI
MCLR/VPP
VSS
VDD
N/C
VSS
N/C
RA0
RA1
RA2
RA3
RB0
OSC1/CLKIN
3
OSC2/CLKOUT
RC7
4
5
RC6
RB7
RB6
RB5
RB4
13
12
RB0
6
RC5
RC4
RC3
RB1
RB2
RB3
11
10
7
8
RC2
9
RC1
RC0
10
11
12
13
14
RB1
RB2
RB3
RB4
RB7
RB6
RB5
SSOP
SSOP
VSS
•1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RA2
RA3
T0CKI
MCLR/VPP
VSS
•1
2
3
4
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
T0CKI
VDD
VDD
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
VSS
5
6
7
8
VDD
VDD
RB7
RB6
RB5
RB4
VSS
RB0
RB1
9
10
11
12
13
14
RB2
RB3
9
10
RC0
RB7
RB6
RB5
Device Differences
Oscillator
Selection
(Program)
Process
Technology
(Microns)
Voltage
Range
ROM
Equivalent
MCLR
Filter
Device
Oscillator
PIC16C54
2.5-6.25
2.0-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
Factory
User
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
1.2
0.9
0.7
1.7
0.7
1.7
0.7
1.2
0.7
0.7
1.2
0.7
0.7
0.7
0.7
PIC16CR54A
No
No
PIC16C54A
PIC16C54C
PIC16C55
—
User
PIC16CR54C
Yes
No
Factory
User
—
PIC16C55A
PIC16C56
—
Yes
No
Factory
User
—
PIC16CR56A
—
PIC16C56A
PIC16C57
Yes
No
Factory
User
PIC16C57C
PIC16C58B
PIC16CR54A
PIC16CR54C
PIC16CR56A
PIC16CR57C
PIC16CR58B
PIC16CR57C
PIC16CR58B
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
User
Factory
Factory
Factory
Factory
Factory
N/A
N/A
N/A
N/A
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties, please
refer to Section 2.0.
DS30453D-page 2
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C5X Device Varieties ......................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................ 9
4.0 Oscillator Configurations ............................................................................................................................................................ 15
5.0 Reset.......................................................................................................................................................................................... 19
6.0 Memory Organization................................................................................................................................................................. 25
7.0 I/O Ports ..................................................................................................................................................................................... 35
8.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 37
9.0 Special Features of the CPU...................................................................................................................................................... 43
10.0 Instruction Set Summary............................................................................................................................................................ 49
11.0 Development Support................................................................................................................................................................. 61
12.0 Electrical Characteristics - PIC16C54/55/56/57 ......................................................................................................................... 67
13.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 79
14.0 Device Characterization - PIC16C54/55/56/57/CR54A.............................................................................................................. 91
15.0 Electrical Characteristics - PIC16C54A.................................................................................................................................... 103
16.0 Device Characterization - PIC16C54A..................................................................................................................................... 117
17.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ........................................ 131
18.0 Device Characterization - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B.......................................... 145
19.0 Electrical Characteristics - PIC16C54C/C55A/C56A/C57C/C58B 40MHz............................................................................... 155
20.0 Device Characterization - PIC16C54C/C55A/C56A/C57C/C58B 40MHz ................................................................................ 165
21.0 Packaging Information.............................................................................................................................................................. 171
Appendix A: Compatibility ............................................................................................................................................................. 183
On-Line Support................................................................................................................................................................................. 189
Reader Response.............................................................................................................................................................................. 190
Product Identification System ............................................................................................................................................................ 191
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
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2002 Microchip Technology Inc.
Preliminary
DS30453D-page 3
PIC16C5X
NOTES:
DS30453D-page 4
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
8-Bit EPROM/ROM-Based CMOS Microcontrollers
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC16C5X series fits perfectly in applications rang-
ing from high speed automotive and appliance motor
control to low power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequen-
cies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mount-
ing, make this microcontroller series perfect for applica-
tions with space limitations. Low cost, low power, high
performance ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, co-processor applications).
The PIC16C5X from Microchip Technology is a family
of low cost, high performance, 8-bit fully static,
EPROM/ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single word/
single cycle instructions. All instructions are single
cycle except for program branches which take two
cycles. The PIC16C5X delivers performance in an
order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C5X products are equipped with special fea-
tures that reduce system cost and power requirements.
The Power-on Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external RESET circuitry.
There are four oscillator configurations to choose from,
including the power saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and Code Protection features
improve system cost, power and reliability.
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers, while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by a full fea-
tured macro assembler, a software simulator, an in-cir-
cuit emulator, a low cost development programmer and
a full featured programmer. All the tools are supported
on IBM PC and compatible machines.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 5
PIC16C5X
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
Features
PIC16C54
PIC16CR54
PIC16C55
PIC16C56
PIC16CR56
Maximum Operation Frequency
EPROM Program Memory (x12 words)
ROM Program Memory (x12 words)
RAM Data Memory (bytes)
Timer Module(s)
40 MHz
512
—
20 MHz
—
40 MHz
512
—
40 MHz
1K
20 MHz
—
512
25
—
1K
25
24
25
25
TMR0
12
TMR0
12
TMR0
20
TMR0
12
TMR0
12
I/O Pins
Number of Instructions
Packages
33
33
33
33
33
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
28-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
20-pin SSOP 20-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high
I/O current capability.
Features
PIC16C57
PIC16CR57
PIC16C58
PIC16CR58
Maximum Operation Frequency
EPROM Program Memory (x12 words)
ROM Program Memory (x12 words)
RAM Data Memory (bytes)
Timer Module(s)
40 MHz
2K
20 MHz
—
40 MHz
2K
20 MHz
—
—
2K
—
2K
72
72
73
73
TMR0
20
TMR0
20
TMR0
12
TMR0
12
I/O Pins
Number of Instructions
Packages
33
33
33
33
28-pin DIP, SOIC; 28-pin DIP, SOIC; 18-pin DIP, SOIC; 18-pin DIP, SOIC;
28-pin SSOP 28-pin SSOP 20-pin SSOP 20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high
I/O current capability.
DS30453D-page 6
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
2.3
Quick-Turnaround-Production
(QTP) Devices
2.0
PIC16C5X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in this section. When placing
orders, please use the PIC16C5X Product Identifica-
tion System at the back of this data sheet to specify the
correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your
Microchip Technology sales office for more details.
For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:
1. C, as in PIC16C54C. These devices have
EPROM program memory and operate over the
standard voltage range.
2.4
Serialized Quick-Turnaround-
Production (SQTPSM) Devices
2. LC, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.
Microchip offers the unique programming service
where a few user defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequen-
tial. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory.
3. CR, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.
4. LCR, as in PIC16LCR54A. These devices have
ROM program memory and operate over an
extended voltage range.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
2.1
UV Erasable Devices (EPROM)
The UV erasable versions offered in CERDIP pack-
ages, are optimal for prototype development and pilot
programs.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.
UV erasable devices can be programmed for any of the
four oscillator configurations. Microchip’s
PICSTART Plus(1) and PRO MATE programmers
both support programming of the PIC16C5X. Third
party programmers also are available. Refer to the
Third Party Guide (DS00104) for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates, or small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must be pro-
grammed.
Note 1: PIC16C55A and PIC16C57C devices
require OSC2 not to be connected while
programming with PICSTART® Plus
programmer.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 7
PIC16C5X
NOTES:
DS30453D-page 8
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
The PIC16C5X device contains an 8-bit ALU and work-
ing register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16C5X uses a Harvard architecture in which
program and data are accessed on separate buses.
This improves bandwidth over traditional von Neumann
architecture where program and data are fetched on
the same bus. Separating program and data memory
further allows instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are 12
bits wide making it possible to have all single word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions. Consequently, all instructions (33) execute in a
single cycle except for program branches.
The ALU is 8 bits wide and capable of addition, subtrac-
tion, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the W (working) register. The other
operand is either a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
The PIC16C54/CR54 and PIC16C55 address 512 x 12
of program memory, the PIC16C56/CR56 address
1K x 12 of program memory, and the PIC16C57/CR57
and PIC16C58/CR58 address 2K x 12 of program
memory. All program memory is internal.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1
(for PIC16C54/56/58) and Table 3-2 (for PIC16C55/
57).
The PIC16C5X can directly or indirectly address its
register files and data memory. All special function reg-
isters including the program counter are mapped in the
data memory. The PIC16C5X has a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C5X simple yet efficient. In addition, the learning
curve is reduced significantly.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 9
PIC16C5X
FIGURE 3-1:
PIC16C5X SERIES BLOCK DIAGRAM
9-11
T0CKI
PIN
OSC1 OSC2 MCLR
CONFIGURATION WORD
9-11
EPROM/ROM
512 X 12 TO
2048 X 12
STACK 1
STACK2
“DISABLE” “OSC
PC
SELECT”
WATCHDOG
TIMER
12
2
“CODE
OSCILLATOR/
TIMING &
CONTROL
PROTECT”
INSTRUCTION
REGISTER
WDT TIME
OUT
CLKOUT
WDT/TMR0
PRESCALER
9
12
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
FROM W
DIRECT ADDRESS
DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE
5
5-7
8
(SRAM)
24, 25, 72 or
73 Bytes
STATUS
TMR0
FSR
8
DATA BUS
8
W
ALU
FROM W
8
FROM W
4
FROM W
8
8
4
8
“TRIS 5”
“TRIS 6”
“TRIS 7”
TRISB PORTB
TRISA PORTA
TRISC
PORTC
8
4
8
RC<7:0>
(28-Pin
RA<3:0>
RB<7:0>
Devices Only)
DS30453D-page 10
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
TABLE 3-1:
Pin Name
PINOUT DESCRIPTION - PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58,
PIC16CR58
Pin Number
SOIC SSOP
Pin Buffer
Type Type
Description
DIP
RA0
RA1
RA2
RA3
17
18
1
17
18
1
19
20
1
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
2
2
2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
6
7
8
6
7
8
7
8
9
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
TTL
TTL
TTL
TTL
9
9
10
11
12
13
10
11
12
13
T0CKI
3
3
3
I
ST
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
MCLR/VPP
4
4
4
I
ST
Master clear (RESET) input/programming voltage input.
This pin is an active low RESET to the device. Voltage on
the MCLR/VPP pin must not exceed VDD to avoid unin-
tended entering of Programming mode.
OSC1/CLKIN
16
15
16
15
18
17
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
VDD
VSS
14
5
14
5
15,16
5,6
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 11
PIC16C5X
TABLE 3-2:
Pin Name
PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57
Pin Number
Pin Buffer
Type Type
Description
DIP
SOIC SSOP
RA0
RA1
RA2
RA3
6
7
8
9
6
7
8
9
5
6
7
8
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
10
11
12
13
14
15
16
17
10
11
12
13
14
15
16
17
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
10
11
12
13
15
16
17
TTL
TTL
TTL
TTL
TTL
TTL
TTL
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
18
19
20
21
22
23
24
25
18
19
20
21
22
23
24
25
18
19
20
21
22
23
24
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
TTL
TTL
TTL
TTL
T0CKI
1
1
2
I
ST
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
MCLR
28
28
28
I
ST
Master clear (RESET) input. This pin is an active low
RESET to the device.
OSC1/CLKIN
27
26
27
26
27
26
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
VDD
VSS
N/C
2
4
2
4
3,4
1,14
—
P
P
—
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Unused, do not connect.
3,5
3,5
—
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger
input
DS30453D-page 12
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter is incremented every Q1 and the instruc-
tion is fetched from program memory and latched into
the instruction register in Q4. It is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow are shown in Figure 3-2
and Example 3-1.
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW H’55’
2. MOVWF PORTB
3. CALL SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 13
PIC16C5X
NOTES:
DS30453D-page 14
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 4-2:
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
4.0
4.1
OSCILLATOR
CONFIGURATIONS
CONFIGURATION)
Oscillator Types
PIC16C5Xs can be operated in four different oscillator
modes. The user can program two configuration bits
(FOSC1:FOSC0) to select one of these four modes:
Clock from
ext. system
OSC1
PIC16C5X
OSC2
1. LP:
2. XT:
3. HS:
4. RC:
Low Power Crystal
Open
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 4-1:
CAPACITOR SELECTION FOR
CERAMIC RESONATORS -
PIC16C5X, PIC16CR5X
Note: Not all oscillator selections available for all
parts. See Section 9.1.
Osc
Resonator Cap. Range Cap. Range
Type
Freq
C1
C2
4.2
Crystal Oscillator/Ceramic
Resonators
XT
455 kHz
2.0 MHz
4.0 MHz
68-100 pF
15-33 pF
10-22 pF
68-100 pF
15-33 pF
10-22 pF
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 4-1). The
PIC16C5X oscillator design requires the use of a paral-
lel cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source drive the OSC1/CLKIN pin
(Figure 4-2).
HS
8.0 MHz
16.0 MHz
10-22 pF
10 pF
10-22 pF
10 pF
These values are for design guidance only. Since
each resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
TABLE 4-2:
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR -
PIC16C5X, PIC16CR5X
FIGURE 4-1:
CRYSTAL/CERAMIC
RESONATOROPERATION
(HS, XT OR LP OSC
CONFIGURATION)
Osc
Type
Crystal
Freq
32 kHz(1)
Cap.Range Cap. Range
C1
C2
LP
XT
15 pF
15 pF
(1)
C1
OSC1
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15 pF
PIC16C5X
SLEEP
XTAL
OSC2
(3)
RF
To internal
logic
15 pF
15 pF
(2)
RS
(1)
HS
4 MHz
8 MHz
20 MHz
15 pF
15 pF
15 pF
15 pF
15 pF
15 pF
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required
for AT strip cut crystals.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
These values are for design guidance only. Rs may
be required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specification.
Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for
appropriate values of external components.
3: RF varies with the Oscillator mode cho-
sen (approx. value = 10 MΩ).
Note: If you change from this device to another
device, please verify oscillator characteris-
tics in your application.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 15
PIC16C5X
Figure 4-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator cir-
cuit. The 330 kΩ resistors provide the negative feed-
back to bias the inverters in their linear region.
4.3
External Crystal Oscillator Circuit
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external crys-
tal oscillator circuit. Prepackaged oscillators provide a
wide operating range and better stability. A well-
designed crystal oscillator will provide good perfor-
mance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance, or
one with series resonance.
FIGURE 4-4:
EXAMPLE OF EXTERNAL
SERIES RESONANT
CRYSTAL OSCILLATOR
CIRCUIT (USING XT, HS
OR LP OSCILLATOR
MODE)
Figure 4-3 shows an implementation example of a par-
allel resonant oscillator circuit. The circuit is designed
to use the fundamental frequency of the crystal. The
74AS04 inverter performs the 180-degree phase shift
that a parallel oscillator requires. The 4.7 kΩ resistor
provides the negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This circuit could be used for external oscillator
designs.
To Other
Devices
330K
330K
PIC16C5X
74AS04
74AS04
74AS04
CLKIN
0.1 µF
XTAL
Open
OSC2
FIGURE 4-3:
EXAMPLE OF EXTERNAL
PARALLEL RESONANT
CRYSTAL OSCILLATOR
CIRCUIT (USING XT, HS
OR LP OSCILLATOR
MODE)
+5V
To Other
Devices
10K
74AS04
PIC16C5X
4.7K
CLKIN
74AS04
Open
OSC2
10K
XTAL
10K
20 pF
20 pF
DS30453D-page 16
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 4-5:
RC OSCILLATOR MODE
4.4
RC Oscillator
VDD
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used.
REXT
Internal
clock
OSC1
N
CEXT
VSS
PIC16C5X
OSC2/CLKOUT
Fosc/4
Figure 4-5 shows how the R/C combination is con-
nected to the PIC16C5X. For REXT values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high REXT values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 3 kΩ and 100 kΩ.
Note: If you change from this device to another
device, please verify oscillator characteris-
tics in your application.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or pack-
age lead frame capacitance.
The Electrical Specifications sections show RC fre-
quency variation from part to part due to normal pro-
cess variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
Also, see the Electrical Specifications sections for vari-
ation of oscillator frequency due to VDD for given REXT/
CEXT values as well as frequency variation due to oper-
ating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 17
PIC16C5X
NOTES:
DS30453D-page 18
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different RESET conditions (Table 5-
1). These bits may be used to determine the nature of
the RESET.
5.0
RESET
PIC16C5X devices may be RESET in one of the follow-
ing ways:
• Power-On Reset (POR)
Table 5-3 lists a full description of RESET states of all
registers. Figure 5-1 shows a simplified block diagram
of the On-chip Reset circuit.
• MCLR Reset (normal operation)
• MCLR Wake-up Reset (from SLEEP)
• WDT Reset (normal operation)
• WDT Wake-up Reset (from SLEEP)
Table 5-1 shows these RESET conditions for the PCL
and STATUS registers.
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-On Reset (POR), MCLR or
WDT Reset. A MCLR or WDT wake-up from SLEEP
also results in a device RESET, and not a continuation
of operation before SLEEP.
TABLE 5-1:
STATUS BITS AND THEIR SIGNIFICANCE
Condition
TO
PD
Power-On Reset
1
u
1
u
MCLR Reset (normal operation)
1
0
MCLR Wake-up (from SLEEP)
WDT Reset (normal operation)
0
0
1
0
WDT Wake-up (from SLEEP)
Legend: u= unchanged, x= unknown, —= unimplemented read as ’0’.
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH RESET
Value on
MCLR and
WDT Reset
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
STATUS
PA2
PA1
PA0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
Legend: u = unchanged, x = unknown, q = see Table 5-1 for possible values.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 19
PIC16C5X
TABLE 5-3:
RESET CONDITIONS FOR ALL REGISTERS
Register
Address
Power-On Reset
MCLR or WDT Reset
W
N/A
N/A
xxxx xxxx
1111 1111
uuuu uuuu
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
1111 1111
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TRIS
OPTION
INDF
N/A
--11 1111
00h
xxxx xxxx
TMR0
PCL
01h
xxxx xxxx
02h
1111 1111
STATUS
FSR(1)
PORTA
PORTB
PORTC(2)
03h
0001 1xxx
04h
1xxx xxxx
05h
---- xxxx
06h
xxxx xxxx
07h
xxxx xxxx
General Purpose Register Files
07-7Fh
xxxx xxxx
Legend: x= unknown
u= unchanged
-= unimplemented, read as ’0’
q= see tables in Table 5-1 for possible values.
Note 1: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the
value on RESET is 111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.
2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-Up
Detect
POR (Power-On Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
8-bit Asynch
S
R
Q
Q
WDT
On-Chip
RC OSC
Ripple Counter
(Device Reset
Timer)
CHIP RESET
DS30453D-page 20
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 5-2:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
5.1
Power-On Reset (POR)
The PIC16C5X family incorporates on-chip Power-On
Reset (POR) circuitry which provides an internal chip
RESET for most power-up situations. To use this fea-
ture, the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 5-1.
VDD
D
VDD
R
R1
The Power-On Reset circuit and the Device Reset
Timer (Section 5.2) circuit are closely related. On
power-up, the RESET latch is set and the DRT is
RESET. The DRT timer begins counting once it detects
MCLR to be high. After the time-out period, which is
typically 18 ms, it will RESET the reset latch and thus
end the on-chip RESET signal.
MCLR
PIC16C5X
C
• External Power-On Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
A power-up example where MCLR is not tied to VDD is
shown in Figure 5-3. VDD is allowed to rise and stabilize
before bringing MCLR high. The chip will actually come
out of reset TDRT msec after MCLR goes high.
• R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
In Figure 5-4, the on-chip Power-On Reset feature is
being used (MCLR and VDD are tied together). The VDD
is stable before the start-up timer times out and there is
no problem in getting a proper RESET. However,
Figure 5-5 depicts a problem situation where VDD rises
too slowly. The time between when the DRT senses a
high on the MCLR/VPP pin, and when the MCLR/VPP
pin (and VDD) actually reach their full value, is too long.
In this situation, when the start-up timer times out, VDD
has not reached the VDD (min) value and the chip is,
therefore, not guaranteed to function correctly. For
such situations, we recommend that external RC cir-
cuits be used to achieve longer POR delay times
(Figure 5-2).
• R1 = 100Ω to 1 kΩ will limit any current flow-
ing into MCLR from external capacitor C in the
event of MCLR pin breakdown due to Electro-
static Discharge (ESD) or Electrical Over-
stress (EOS).
Note: When the device starts normal operation
(exits the RESET condition), device oper-
ating parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in RESET until the
operating conditions are met.
For more information on PIC16C5X POR, see Power-
Up Considerations - AN522 in the Embedded Control
Handbook.
The POR circuit does not produce an internal RESET
when VDD declines.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 21
PIC16C5X
FIGURE 5-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE
TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE
TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will RESET properly if, and only if, V1 ≥ VDD min
DS30453D-page 22
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 5-7:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
5.2
Device Reset Timer (DRT)
The Device Reset Timer (DRT) provides an 18 ms
nominal time-out on RESET regardless of Oscillator
mode used. The DRT operates on an internal RC oscil-
lator. The processor is kept in RESET as long as the
DRT is active. The DRT delay allows VDD to rise above
VDD min., and for the oscillator to stabilize.
VDD
VDD
R1
R2
Q1
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a RESET condition for approximately 18 ms after the
voltage on the MCLR/VPP pin has reached a logic high
(VIH) level. Thus, external RC networks connected to
the MCLR input are not required in most cases, allow-
ing for savings in cost-sensitive and/or space restricted
applications.
MCLR
40K
PIC16C5X
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD
is below a certain level such that:
The Device Reset time delay will vary from chip to chip
due to VDD, temperature, and process variation. See
AC parameters for details.
R1
= 0.7V
VDD •
R1 + R2
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16C5X from SLEEP
mode automatically.
FIGURE 5-8:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
5.3
Reset on Brown-Out
VDD
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be RESET in the event of
a brown-out.
VDD
bypass
capacitor
VDD
MCP809
To RESET PIC16C5X devices when a brown-out
occurs, external brown-out protection circuits may be
built, as shown in Figure 5-6, Figure 5-7 and Figure 5-
8.
RST
MCLR
Vss
PIC16C5X
This brown-out protection circuit employs Micro-
chip Technology’s MCP809 microcontroller
supervisor. The MCP8XX and MCP1XX families
of supervisors provide push-pull and open collec-
tor outputs with both "active high and active low"
RESET pins. There are 7 different trip point selec-
tions to accommodate 5V and 3V systems.
FIGURE 5-6:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
33K
VDD
Q1
10K
MCLR
40K
PIC16C5X
This circuit will activate RESET when VDD goes below Vz
+ 0.7V (where Vz = Zener voltage).
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 23
PIC16C5X
NOTES:
DS30453D-page 24
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 6-2:
PIC16C56/CR56
PROGRAM MEMORY MAP
AND STACK
6.0
MEMORY ORGANIZATION
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or two
STATUS Register bits. For devices with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Selection Register (FSR).
PC<9:0>
10
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip Program
0FFh
Memory (Page 0)
100h
6.1
Program Memory Organization
The PIC16C54, PIC16CR54 and PIC16C55 have a 9-
bit Program Counter (PC) capable of addressing a 512
1FFh
200h
x
12 program memory space (Figure 6-1). The
On-chip Program
Memory (Page 1)
2FFh
300h
PIC16C56 and PIC16CR56 have a 10-bit Program
Counter (PC) capable of addressing a 1K x 12 program
memory space (Figure 6-2). The PIC16CR57,
PIC16C58 and PIC16CR58 have an 11-bit Program
Counter capable of addressing a 2K x 12 program
memory space (Figure 6-3). Accessing a location
above the physically implemented address will cause a
wraparound.
RESET Vector
3FFh
FIGURE 6-3:
PIC16C57/CR57/C58/
CR58 PROGRAM
MEMORY MAP AND
STACK
A NOPat the RESET vector location will cause a restart
at location 000h. The RESET vector for the PIC16C54,
PIC16CR54 and PIC16C55 is at 1FFh. The RESET
vector for the PIC16C56 and PIC16CR56 is at 3FFh.
The RESET vector for the PIC16C57, PIC16CR57,
PIC16C58, and PIC16CR58 is at 7FFh. See
Section 6.5 for additional information using CALLand
GOTOinstructions.
PC<10:0>
11
CALL, RETLW
Stack Level 1
Stack Level 2
000h
FIGURE 6-1:
PIC16C54/CR54/C55
PROGRAM MEMORY MAP
AND STACK
On-chip Program
0FFh
Memory (Page 0)
100h
1FFh
200h
PC<8:0>
9
On-chip Program
2FFh
CALL, RETLW
Memory (Page 1)
300h
Stack Level 1
Stack Level 2
3FFh
400h
On-chip Program
4FFh
000h
Memory (Page 2)
500h
On-chip
Program
Memory
5FFh
600h
0FFh
100h
On-chip Program
6FFh
Memory (Page 3)
700h
RESET Vector
7FFh
RESET Vector
1FFh
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 25
PIC16C5X
FIGURE 6-4:
PIC16C54, PIC16CR54,
PIC16C55, PIC16C56,
PIC16CR56 REGISTER
FILE MAP
6.2
Data Memory Organization
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers and
General Purpose Registers.
File Address
INDF(1)
TMR0
PCL
00h
01h
02h
03h
04h
05h
06h
07h
The Special Function Registers include the TMR0 reg-
ister, the Program Counter (PC), the Status Register,
the I/O registers (ports) and the File Select Register
(FSR). In addition, Special Purpose Registers are used
to control the I/O port configuration and prescaler
options.
STATUS
FSR
PORTA
PORTB
The General Purpose Registers are used for data and
control information under command of the instructions.
For the PIC16C54, PIC16CR54, PIC16C56 and
PIC16CR56, the register file is composed of 7 Special
Function Registers and 25 General Purpose Registers
(Figure 6-4).
PORTC(2)
08h
General
Purpose
Registers
For the PIC16C55, the register file is composed of 8
Special Function Registers and 24 General Purpose
Registers.
For the PIC16C57 and PIC16CR57, the register file is
composed of 8 Special Function Registers, 24 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 6-5).
1Fh
Note 1: Not a physical register. See
Section 6.7.
2: PIC16C55 only, in all other devices this
is implemented as a a general purpose
register.
For the PIC16C58 and PIC16CR58, the register file is
composed of 7 Special Function Registers, 25 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 6-6).
6.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is accessed either directly or indirectly
through the File Select Register (FSR). The FSR Reg-
ister is described in Section 6.7.
DS30453D-page 26
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 6-5:
PIC16C57/CR57 REGISTER FILE MAP
FSR<6:5>
00
01
10
11
File Address
00h
INDF(1)
TMR0
PCL
20h
40h
60h
01h
02h
03h
04h
05h
06h
STATUS
FSR
Addresses map back to
addresses in Bank 0.
PORTA
PORTB
07h
08h
PORTC
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
10h
70h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
1Fh
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: Not a physical register. See Section 6.7.
FIGURE 6-6:
PIC16C58/CR58 REGISTER FILE MAP
FSR<6:5>
00
01
10
11
File Address
00h
INDF(1)
TMR0
PCL
20h
40h
60h
01h
02h
03h
04h
05h
STATUS
FSR
Addresses map back to
addresses in Bank 0.
PORTA
PORTB
06h
07h
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
10h
70h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
1Fh
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: Not a physical register. See Section 6.7.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 27
PIC16C5X
6.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions to control the opera-
tion of the device (Table 6-1).
The Special Registers can be classified into two sets.
The Special Function Registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
TABLE 6-1:
Address
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-on
Reset
Details
on Page
Name
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2 Bit 1 Bit 0
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
1xxx xxxx(3)
---- xxxx
N/A
N/A
00h
01h
02h
TRIS
I/O Control Registers (TRISA, TRISB, TRISC)
35
30
32
38
31
29
OPTION
INDF
Contains control bits to configure Timer0 and Timer0/WDT prescaler
Uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
TMR0
PCL
(1)
Low order 8 bits of PC
03h
04h
05h
06h
07h
STATUS
FSR
PA2
PA1
PA0
TO
PD
Z
DC
C
Indirect data memory address pointer
32
35
35
35
PORTA
PORTB
PORTC
—
—
—
—
RA3
RB3
RC3
RA2
RB2
RC2
RA1
RB1
RC1
RA0
RB0
RC0
RB7
RC7
RB6
RC6
RB5
RC5
RB4
RC4
xxxx xxxx
xxxx xxxx
(2)
Legend: x = unknown, u = unchanged, – = unimplemented, read as '0' (if applicable). Shaded cells = unimplemented or unused
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 6.5 for an explanation of how to access
these bits.
2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and
PIC16CR58.
3: These values are valid for PIC16C57/CR57/C58/CR58. For the PIC16C54/CR54/C55/C56/CR56, the value on RESET is
111x xxxx and for MCLR and WDT Reset, the value is 111u uuuu.
DS30453D-page 28
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
6.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status and the page preselect bits for pro-
gram memories larger than 512 words.
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as 000u u1uu(where u= unchanged).
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
It is recommended, therefore, that only BCF, BSFand
MOVWFinstructions be used to alter the STATUS Reg-
ister because these instructions do not affect the Z, DC
or C bits from the STATUS Register. For other instruc-
tions which do affect STATUS Bits, see Section 10.0,
Instruction Set Summary.
REGISTER 6-1:
R/W-0
PA2
bit 7
STATUS REGISTER (ADDRESS: 03h)
R/W-0
PA1
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 0
bit 7:
PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5:
PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58)
00= Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
01= Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
10= Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58
11= Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58
Each page is 512 words.
Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF
1= A carry from the 4th low order bit of the result occurred
0= A carry from the 4th low order bit of the result did not occur
SUBWF
1= A borrow from the 4th low order bit of the result did not occur
0= A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF
SUBWF
RRF or RLF
1= A carry occurred
0= A carry did not occur
1= A borrow did not occur
0= A borrow occurred
Loaded with LSb or MSb, respectively
Legend:
R = Readable bit
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at POR
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 29
PIC16C5X
6.4
OPTION Register
The OPTION Register is a 6-bit wide, write-only regis-
ter which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W Register will be transferred to the OPTION Reg-
ister. A RESET sets the OPTION<5:0> bits.
REGISTER 6-2:
U-0
OPTION REGISTER
U-0
W-1
T0CS
W-1
W-1
W-1
W-1
W-1
PS0
bit 0
—
—
TOSE
PSA
PS2
PS1
bit 7
bit 7-6:
bit 5:
Unimplemented: Read as ‘0’
T0CS: Timer0 clock source select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: Timer0 source edge select bit
1 = Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3:
PSA: Prescaler assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
bit 2-0:
PS<2:0>: Prescaler rate select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
DS30453D-page 30
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 6-8:
LOADING OF PC
6.5
Program Counter
BRANCH INSTRUCTIONS
- PIC16C56/PIC16CR56
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next pro-
gram instruction to be executed. The PC value is
increased by one, every instruction cycle, unless an
instruction changes the PC.
GOTO Instruction
10
9
8
7
0
0
PC
PCL
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTOinstruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 6-7, Figure 6-8 and
Figure 6-9).
Instruction Word
2
PA<1:0>
7
0
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page num-
ber must be supplied as well. Bit5 and bit6 of the STA-
TUS Register provide page information to bit9 and
bit10 of the PC (Figure 6-8 and Figure 6-9).
0
STATUS
CALL or Modify PCL Instruction
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are pro-
vided by the instruction word. However, PC<8> does
not come from the instruction word, but is always
cleared (Figure 6-7 and Figure 6-8).
10
9
8
7
0
0
PC
PCL
Instruction Word
Instructions where the PCL is the destination, or modify
PCL instructions, include MOVWF PCL, ADDWF PCL,
and BSF PCL,5.
Reset to ‘0’
PA<1:0>
2
7
0
0
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page num-
ber again must be supplied. Bit5 and bit6 of the STA-
TUS Register provide page information to bit9 and
bit10 of the PC (Figure 6-8 and Figure 6-9).
STATUS
FIGURE 6-9:
LOADING OF PC
BRANCH INSTRUCTIONS
- PIC16C57/PIC16CR57,
AND PIC16C58/
Note: Because PC<8> is cleared in the CALL
instruction, or any modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
PIC16CR58
GOTO Instruction
10
9
8
7
0
FIGURE 6-7:
LOADING OF PC
PC
PCL
BRANCH INSTRUCTIONS
- PIC16C54, PIC16CR54,
PIC16C55
Instruction Word
2
PA<1:0>
GOTO Instruction
7
0
8
7
0
PCL
PC
STATUS
CALL or Modify PCL Instruction
Instruction Word
10
9
8
7
0
CALL or Modify PCL Instruction
PC
PCL
8
7
0
PCL
PC
Instruction Word
Reset to ‘0’
PA<1:0>
Reset to ’0’
Instruction Word
2
7
0
STATUS
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 31
PIC16C5X
6.5.1
PAGING CONSIDERATIONS –
PIC16C56/CR56, PIC16C57/CR57
AND PIC16C58/CR58
If the Program Counter is pointing to the last address of
a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS Reg-
ister will not be updated. Therefore, the next GOTO,
CALLor modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0 or
PA<1:0>).
For example, a NOP at location 1FFh (page 0) incre-
ments the PC to 200h (page 1). A GOTO xxxat 200h
will return the program to address xxh on page 0
(assuming that PA<1:0> are clear).
To prevent this, the page preselect bits must be
updated under program control.
6.5.2
EFFECTS OF RESET
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (i.e., the RESET vector).
The STATUS Register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
Therefore, upon a RESET, a GOTO instruction at the
RESET vector location will automatically cause the pro-
gram to jump to page 0.
6.6
Stack
PIC16C5X devices have a 10-bit or 11-bit wide, two-
level hardware push/pop stack.
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLWinstruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W Register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
For the RETLW instruction, the PC is loaded with the
Top of Stack (TOS) contents. All of the devices covered
in this data sheet have a two-level stack. The stack has
the same bit width as the device PC, therefore, paging
is not an issue when returning from a subroutine.
DS30453D-page 32
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
EXAMPLE 6-2:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
6.7
Indirect Data Addressing; INDF
and FSR Registers
The INDF Register is not
a physical register.
MOVLW
H’10’
FSR
;initialize pointer
; to RAM
Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
MOVWF
CLRF
NEXT
INDF
FSR,F
FSR,4
NEXT
;clear INDF Register
;inc pointer
;all done?
INCF
BTFSC
GOTO
EXAMPLE 6-1:
INDIRECT ADDRESSING
;NO, clear next
CONTINUE
• Register file 08 contains the value 10h
• Register file 09 contains the value 0Ah
• Load the value 08 into the FSR Register
:
;YES, continue
The FSR is either a 5-bit (PIC16C54, PIC16CR54,
PIC16C55, PIC16C56, PIC16CR56) or 7-bit
(PIC16C57, PIC16CR57, PIC16C58, PIC16CR58)
wide register. It is used in conjunction with the INDF
Register to indirectly address the data memory area.
• A read of the INDF Register will return the value
of 10h
• Increment the value of the FSR Register by one
(FSR = 09h)
• A read of the INDF register now will return the
value of 0Ah.
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF Register indirectly results in a
no-operation (although STATUS bits may be affected).
PIC16C54, PIC16CR54, PIC16C55, PIC16C56,
PIC16CR56: These do not use banking. FSR<6:5> bits
are unimplemented and read as '1's.
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 6-2.
PIC16C57, PIC16CR57, PIC16C58, PIC16CR58:
FSR<6:5> are the bank select bits and are used to
select the bank to be addressed (00 = bank 0,
01= bank 1, 10= bank 2, 11= bank 3).
FIGURE 6-10:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(FSR)
(opcode)
(FSR)
3
2
1
4
0
5
3
2
1
0
6
4
5
6
location select
bank select
location select
bank
00
01
10
11
00h
Addresses map back to
addresses in Bank 0.
Data
Memory
0Fh
10h
(1)
1Fh
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 3
Bank 0
Note 1: For register map detail see Section 6.2.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 33
PIC16C5X
NOTES:
DS30453D-page 34
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
7.5
I/O Interfacing
7.0
I/O PORTS
The equivalent circuit for an I/O port pin is shown in
Figure 7-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The out-
puts are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corre-
sponding direction control bit (in TRISA, TRISB,
TRISC) must be cleared (= 0). For use as an input, the
corresponding TRIS bit must be set. Any I/O pin can be
programmed individually as input or output.
As with any other register, the I/O Registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
7.1
PORTA
PORTA is a 4-bit I/O Register. Only the low order 4 bits
are used (RA<3:0>). Bits 7-4 are unimplemented and
read as '0's.
FIGURE 7-1:
EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
7.2
PORTB
PORTB is an 8-bit I/O Register (PORTB<7:0>).
Data
Bus
D
7.3
PORTC
Q
Data
Latch
VDD
PORTC is an 8-bit I/O Register for PIC16C55,
PIC16C57 and PIC16CR57.
WR
Port
Q
CK
P
PORTC is a General Purpose Register for PIC16C54,
PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and
PIC16CR58.
N
I/O
W
pin(1)
Reg
7.4
TRIS Registers
D
Q
Q
TRIS
Latch
VSS
The Output Driver Control Registers are loaded with
the contents of the W Register by executing the
TRIS ‘f’
CK
TRISfinstruction. A '1' from a TRIS Register bit puts
the corresponding output driver in a hi-impedance
(input) mode. A '0' puts the contents of the output data
latch on the selected pins, enabling the output buffer.
RESET
Note: A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS Registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 7-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
05h
06h
07h
TRIS
I/O Control Registers (TRISA, TRISB, TRISC)
1111 1111 1111 1111
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PORTA
PORTB
PORTC
—
—
—
—
RA3
RB3
RC3
RA2
RB2
RC2
RA1
RB1
RC1
RA0
RB0
RC0
RB7
RC7
RB6
RC6
RB5
RC5
RB4
RC4
Legend: x= unknown, u= unchanged, — = unimplemented, read as '0', Shaded cells = unimplemented, read as ‘0’
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 35
PIC16C5X
EXAMPLE 7-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
7.6
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
7.6.1
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bi-direc-
tional I/O pin (say bit0) and it is defined as an input at
this time, the input signal present on the pin itself would
be read into the CPU and rewritten to the data latch of
this particular pin, overwriting the previous content. As
long as the pin stays in the Input mode, no problem
occurs. However, if bit0 is switched into Output mode
later on, the content of the data latch may now be
unknown.
;Initial PORT Settings
; PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BCF
BCF
MOVLW H’3F’
TRIS PORTB
PORTB, 7
PORTB, 6
;01pp pppp
;10pp pppp
;
11pp pppp
11pp pppp
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
7.6.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 7-
2). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should allow the pin volt-
age to stabilize (load dependent) before the next
instruction, which causes that file to be read into the
CPU, is executed. Otherwise, the previous state of that
pin may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instruc-
tions with a NOP or another instruction not accessing
this I/O port.
Example 7-1 shows the effect of two sequential read-
modify-write instructions (e.g., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 7-2:
SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
Instruction
fetched
MOVWF PORTB MOVF PORTB,W
This example shows a write
to PORTB followed by a read
from PORTB.
RB<7:0>
Port pin
written here
Port pin
sampled here
MOVWF PORTB MOVF PORTB,W
NOP
Instruction
executed
(Write to
PORTB)
(Read
PORTB)
DS30453D-page 36
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 8.1.
8.0
TIMER0 MODULE AND TMR0
REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Note: The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
Figure 8-1 is a simplified block diagram of the Timer0
module, while Figure 8-2 shows the electrical structure
of the Timer0 input.
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 8.2 details the operation
of the prescaler.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 8-3 and Figure 8-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 8-1.
FIGURE 8-1:
TIMER0 BLOCK DIAGRAM
Data Bus
F
OSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
T0CKI
pin
Programmable
Prescaler(2)
PSout
Sync
T0SE(1)
(2 cycle delay)
3
PSA(1)
PS2, PS1, PS0(1)
T0CS(1)
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register
(Section 6.4).
2: The prescaler is shared with the Watchdog Timer (Figure 8-6).
FIGURE 8-2:
ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
Schmitt Trigger
Input Buffer
N
(1)
VSS
VSS
Note 1: ESD protection circuits.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 37
PIC16C5X
FIGURE 8-3:
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 8-4:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALER 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 8-1:
Address
01h
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-on
Reset
Value on
MCLR and
WDT Reset
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR0
Timer0 - 8-bit real-time clock/counter
T0CS T0SE
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
N/A
OPTION
—
—
PSA
PS2
PS1
PS0
Legend: x = unknown, u= unchanged, -= unimplemented. Shaded cells not used by Timer0.
DS30453D-page 38
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
8.1
Using Timer0 with an External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
8.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 8-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer
to the electrical specification of the desired device.
8.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 8-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 8-5:
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or
misses sampling
Prescaler Output (1)
(3)
External Clock/Prescaler
Output After Sampling
(2)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: External clock if no prescaler selected, prescaler output otherwise.
2: The arrows indicate the points in time where sampling occurs.
3: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc (duration of Q = Tosc). Therefore,
the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 39
PIC16C5X
EXAMPLE 8-1:
CHANGING PRESCALER
(TIMER0→WDT)
8.2
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 9.2.1). For simplic-
ity, this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler may
be used by either the Timer0 module or the WDT, but
not both. Thus, a prescaler assignment for the Timer0
module means that there is no prescaler for the WDT,
and vice-versa.
CLRWDT
CLRF
;Clear WDT
;Clear TMR0 & Prescaler
TMR0
MOVLW B'00xx1111’ ;Last 3 instructions in
this example
;are required only if
;desired
;PS<2:0> are 000 or
;001
OPTION
CLRWDT
MOVLW B'00xx1xxx’ ;Set Prescaler to
OPTION ;desired WDT rate
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
To change prescaler from the WDT to the Timer0 mod-
ule, use the sequence shown in Example 8-2. This
sequence must be used even if the WDT is disabled. A
CLRWDTinstruction should be executed before switch-
ing the prescaler.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDTinstruction will clear
the prescaler along with the WDT. The prescaler is nei-
ther readable nor writable. On a RESET, the prescaler
contains all '0's.
EXAMPLE 8-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
8.2.1
SWITCHING PRESCALER
ASSIGNMENT
MOVLW
B'xxxx0xxx'
The prescaler assignment is fully under software con-
trol (i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 8-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT.
OPTION
DS30453D-page 40
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 8-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = FOSC/4)
Data Bus
8
0
1
M
U
X
1
0
M
U
X
T0CKI
pin
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
PSA
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 41
PIC16C5X
NOTES:
DS30453D-page 42
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
9.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of real-
time applications. The PIC16C5X family of microcon-
trollers have a host of such features intended to maxi-
mize system reliability, minimize cost through
elimination of external components, provide power sav-
ing operating modes and offer code protection. These
features are:
• Oscillator Selection (Section 4.0)
• RESET (Section 5.0)
• Power-On Reset (Section 5.1)
• Device Reset Timer (Section 5.2)
• Watchdog Timer (WDT) (Section 9.2)
• SLEEP (Section 9.3)
• Code protection (Section 9.4)
• ID locations (Section 9.5)
The PIC16C5X Family has a Watchdog Timer which
can be shut off only through configuration bit WDTE. It
runs off of its own RC oscillator for added reliability.
There is an 18 ms delay provided by the Device Reset
Timer (DRT), intended to keep the chip in RESET until
the crystal oscillator is stable. With this timer on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low cur-
rent Power-down mode. The user can wake up from
SLEEP through external RESET or through a Watch-
dog Timer time-out. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 43
PIC16C5X
PIC16C58B, and PIC16CR58B devices (Register 9-1).
One bit is for code protection for the PIC16C54,
PIC16C55, PIC16C56 and PIC16C57 devices
(Register 9-2).
9.1
Configuration Bits
Configuration bits can be programmed to select various
device configurations. Two bits are for the selection of
the oscillator type and one bit is the Watchdog Timer
enable bit. Nine bits are code protection bits for the
PIC16C54A,
PIC16CR54C,
PIC16CR56A,
QTP or ROM devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System" dia-
grams in the back of this data sheet).
PIC16CR54A,
PIC16C55A,
PIC16C57C,
PIC16C54C,
PIC16C56A,
PIC16CR57C,
REGISTER 9-1: CONFIGURATION WORD FOR PIC16C54A/CR54A/C54C/CR54C/C55A/C56A/
CR56A/C57C/CR57C/C58B/CR58B
CP
CP
CP
CP
CP
CP
CP
CP
CP
WDTE
FOSC1
FOSC0
bit 0
bit 11
bit 11-3: CP: Code Protection Bit
1= Code protection off
0= Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection Bit
00 = LP oscillator
01 = XT oscillator
10 = HS oscillator
11 = RC oscillator
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to
access the configuration word.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
-n = Value at POR
1 = bit is set
DS30453D-page 44
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
REGISTER 9-2: CONFIGURATION WORD FOR PIC16C54/C55/C56/C57
—
—
—
—
—
—
—
—
CP
WDTE
FOSC1
FOSC0
bit 11
bit 0
bit 11-4: Unimplemented: Read as ‘0’
bit 3:
CP: Code protection bit.
1 = Code protection off
0= Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits(2)
00 = LP oscillator
01 = XT oscillator
10 = HS oscillator
11 = RC oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to
access the configuration word.
2: PIC16LV54A supports XT, RC and LP oscillator only.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared x = bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 45
PIC16C5X
both. Thus, a prescaler assignment for the Timer0
module means that there is no prescaler for the WDT,
and vice-versa.
9.2
Watchdog Timer (WDT)
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation or SLEEP, a WDT Reset or Wake-up Reset
generates a device RESET.
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio (Section 6.4).
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, time-out a period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see Device Characterization).
The TO bit (STATUS<4>) will be cleared upon a Watch-
dog Timer Reset (Section 6.3).
The WDT can be permanently disabled by program-
ming the configuration bit WDTE as a ’0’ (Section 9.1).
Refer to the PIC16C5X Programming Specifications
(Literature Number DS30190) to determine how to
access the configuration word.
Under worst case conditions (VDD = Min., Temperature
= Max., WDT prescaler = 1:128), it may take several
seconds before a WDT time-out occurs.
9.2.2
WDT PROGRAMMING
CONSIDERATIONS
9.2.1
WDT PERIOD
The CLRWDTinstruction clears the WDT and the pres-
caler, if assigned to the WDT, and prevents it from tim-
ing out and generating a device RESET.
An 8-bit counter is available as a prescaler for the
Timer0 module (Section 8.2), or as a postscaler for the
Watchdog Timer (WDT), respectively. For simplicity,
this counter is being referred to as “prescaler” through-
out this data sheet. Note that the prescaler may be
used by either the Timer0 module or the WDT, but not
The SLEEPinstruction RESETS the WDT and the pres-
caler, if assigned to the WDT. This gives the maximum
SLEEP time before a WDT Wake-up Reset.
FIGURE 9-1:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
M
1
Prescaler
Watchdog
U
X
Timer
8 - to - 1 MUX
PS2:PS0
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
PSA
MUX
Note:
T0CS, T0SE, PSA, PS2:PS0 are bits in the
OPTION register.
WDT
Time-out
TABLE 9-1:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Value on
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-On MCLR and
Reset WDT Reset
N/A
OPTION
—
—
Tosc
Tose
PSA
PS2
PS1
PS0 --11 1111 --11 1111
Legend: u= unchanged, -= unimplemented, read as '0'. Shaded cells not used by Watchdog Timer.
DS30453D-page 46
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
9.3
Power-Down Mode (SLEEP)
9.4
Program Verification/Code
Protection
A device may be powered down (SLEEP) and later
powered up (Wake-up from SLEEP).
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
9.3.1
SLEEP
The Power-down mode is entered by executing a
SLEEPinstruction.
Note: Microchip does not recommend code pro-
tecting windowed devices.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
9.5
ID Locations
Four memory locations are designated as ID locations
where the user can store checksum or other code-iden-
tification numbers. These locations are not accessible
during normal execution but are readable and writable
during program/verify.
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ’1’s.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level
(MCLR = VIH).
Note: Microchip will assign a unique pattern
number for QTP and SQTP requests and
for ROM devices. This pattern number will
be unique and traceable to the submitted
code.
9.3.2
WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. An external RESET input on MCLR/VPP pin.
2. A Watchdog Timer Time-out Reset (if WDT was
enabled).
Both of these events cause a device RESET. The TO
and PD bits can be used to determine the cause of
device RESET. The TO bit is cleared if a WDT time-
out occurred (and caused wake-up). The PD bit, which
is set on power-up, is cleared when SLEEPis invoked.
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 47
PIC16C5X
NOTES:
DS30453D-page 48
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time would be 1 µs. If a condi-
tional test is true or the program counter is changed as
a result of an instruction, the instruction execution time
would be 2 µs.
10.0 INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided into
an OPCODE, which specifies the instruction type and
one or more operands which further specify the opera-
tion of the instruction. The PIC16C5X instruction set
summary in Table 10-2 groups the instructions into
byte-oriented, bit-oriented, and literal and control oper-
ations. Table 10-1 shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator is used to specify
which one of the 32 file registers in that bank is to be
used by the instruction.
Figure 10-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal num-
ber:
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is ’0’, the result is
placed in the W register. If ’d’ is ’1’, the result is placed
in the file register specified in the instruction.
0xhhh
where ’h’ signifies a hexadecimal digit.
FIGURE 10-1:
GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Byte-oriented file register operations
11
6
5
d
4
0
OPCODE
f (FILE #)
For literal and control operations, ’k’ represents an
8 or 9-bit constant or literal value.
d = 0 for destination W
d = 1 for destination f
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
TABLE 10-1: OPCODE FIELD
DESCRIPTIONS
5
4
0
Field
Description
OPCODE
f (FILE #)
f
W
b
k
x
Register file address (0x00 to 0x1F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1)
b = 3-bit bit address
f = 5-bit file register address
Literal and control operations (except GOTO)
11
8
7
0
The assembler will generate code with x = 0.
It is the recommended form of use for com-
patibility with all Microchip software tools.
Destination select;
OPCODE
k (literal)
k = 8-bit immediate value
d
d = 0 (store result in W)
d = 1 (store result in file register ’f’)
Default is d = 1
Literal and control operations - GOTO instruction
11
9
8
0
OPCODE
k (literal)
label Label name
TOS
PC
WDT
TO
Top of Stack
k = 9-bit immediate value
Program Counter
Watchdog Timer Counter
Time-out bit
PD
Power-down bit
dest
Destination, either the W register or the
specified register file location
Options
[
(
]
)
Contents
→
Assigned to
< >
Register bit field
In the set of
italics User defined term (font is courier)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 49
PIC16C5X
TABLE 10-2: INSTRUCTION SET SUMMARY
12-Bit Opcode
MSb LSb
Mnemonic,
Description
Operands
Status
Affected
Cycles
Notes
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f,d
f,d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
1
1
1
1
1
0001 11df ffff C,DC,Z
1,2,4
2,4
4
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
0010 11df ffff
0010 10df ffff
0011 11df ffff
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
Z
Z
Z
Z
Z
None
Z
None
Z
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1
2,4
2,4
2,4
2,4
2,4
2,4
1,4
DECFSZ
INCF
1(2)
1
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
1(2)
1
1
1
1
1
1
1
1
1
Z
None
None
C
–
f, d
f, d
f, d
f, d
f, d
2,4
2,4
1,2,4
2,4
C
0000 10df ffff C,DC,Z
0011 10df ffff
0001 10df ffff
None
Z
Exclusive OR W with f
2,4
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
0100 bbbf ffff
0101 bbbf ffff
0110 bbbf ffff
0111 bbbf ffff
None
None
None
None
2,4
2,4
1 (2)
1 (2)
LITERAL AND CONTROL OPERATIONS
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
k
k
–
f
AND literal with W
Call subroutine
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100 TO, PD
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
Z
None
1
3
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
None
Z
None
None
None
0000 0000 0011 TO, PD
0000 0000 0fff
1111 kkkk kkkk
None
Z
XORLW
k
Exclusive OR Literal to W
Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for
GOTO(see Section 6.5 for more on program counter).
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and
is driven low by an external device, the data will be written back with a '0'.
3: The instruction TRIS f, where f = 5, 6 or 7 causes the contents of the W register to be written to the tristate
latches of PORTA, B or C respectively. A '1' forces the pin to a hi-impedance state and disables the output
buffers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS30453D-page 50
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
ADDWF
Syntax:
Add W and f
[ label ] ADDWF f,d
0 ≤ f ≤ 31
ANDWF
Syntax:
AND W with f
[ label ] ANDWF f,d
Operands:
Operands:
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
Encoding:
0001
11df
ffff
0001
01df
ffff
Description:
Add the contents of the W register
and register ’f’. If ’d’ is 0 the result
is stored in the W register. If ’d’ is
’1’ the result is stored back in
register ’f’.
Description:
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0
the result is stored in the W regis-
ter. If 'd' is '1' the result is stored
back in register 'f'.
Words:
1
Words:
1
Cycles:
Example:
1
Cycles:
Example:
1
ADDWF TEMP_REG, 0
ANDWF TEMP_REG, 1
Before Instruction
Before Instruction
W
=
0x17
W
=
0x17
TEMP_REG = 0xC2
After Instruction
TEMP_REG = 0xC2
After Instruction
W
=
0xD9
W
=
0x17
TEMP_REG = 0xC2
TEMP_REG = 0x02
ANDLW
AND literal with W
BCF
Bit Clear f
Syntax:
[ label ] ANDLW
k
Syntax:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Encoding:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
0 → (f<b>)
Z
Status Affected: None
1110
kkkk
kkkk
Encoding:
Description:
Words:
0100
bbbf
ffff
Description:
The contents of the W register are
AND’ed with the eight-bit literal 'k'.
The result is placed in the W regis-
ter.
Bit 'b' in register 'f' is cleared.
1
1
Cycles:
Words:
1
Example:
BCF
FLAG_REG,
7
Cycles:
Example:
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
ANDLW H’5F’
=
=
0xC7
0x47
Before Instruction
W
=
0xA3
After Instruction
0x03
W
=
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 51
PIC16C5X
BSF
Bit Set f
BTFSS
Bit Test f, Skip if Set
Syntax:
[ label ] BSF f,b
Syntax:
[ label ] BTFSS f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected: None
Encoding:
Description:
Words:
0101
bbbf
ffff
Encoding:
0111
bbbf
ffff
Bit ’b’ in register ’f’ is set.
Description:
If bit ’b’ in register ’f’ is ’1’ then the
next instruction is skipped.
1
1
If bit ’b’ is ’1’, then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a 2-cycle instruction.
Cycles:
Example:
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE GOTO
TRUE
BTFSS FLAG,1
PROCESS_CODE
BTFSC
Bit Test f, Skip if Clear
•
•
•
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Before Instruction
PC
After Instruction
If FLAG<1>
PC
=
address (HERE)
Operation:
skip if (f<b>) = 0
Status Affected: None
=
=
=
=
0,
address (FALSE);
1,
address (TRUE)
Encoding:
0110
bbbf
ffff
if FLAG<1>
PC
Description:
If bit ’b’ in register ’f’ is 0 then the
next instruction is skipped.
If bit ’b’ is 0 then the next instruc-
tion fetched during the current
instruction execution is discarded,
and a NOPis executed instead,
making this a 2-cycle instruction.
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE GOTO
BTFSC FLAG,1
PROCESS_CODE
TRUE
•
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
if FLAG<1>
PC
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
if FLAG<1>
PC
DS30453D-page 52
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
CALL
Subroutine Call
CLRW
Clear W
Syntax:
[ label ] CALL
k
Syntax:
[ label ] CLRW
None
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
Operation:
(PC) + 1→ TOS;
k → PC<7:0>;
00h → (W);
1 → Z
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected:
Encoding:
Z
0000
0100
0000
Status Affected: None
Description:
The W register is cleared. Zero bit
(Z) is set.
Encoding:
1001
kkkk
kkkk
Description:
Subroutine call. First, return
address (PC+1) is pushed onto the
stack. The eight bit immediate
address is loaded into PC bits
<7:0>. The upper bits PC<10:9>
are loaded from STATUS<6:5>,
PC<8> is cleared. CALLis a two-
cycle instruction.
Words:
1
Cycles:
Example:
1
CLRW
Before Instruction
W
=
0x5A
After Instruction
W
Z
=
=
0x00
1
Words:
1
2
Cycles:
Example:
HERE
CALL
THERE
CLRWDT
Clear Watchdog Timer
Before Instruction
Syntax:
[ label ] CLRWDT
None
PC
=
address (HERE)
After Instruction
Operands:
Operation:
PC
TOS
=
=
address (THERE)
address (HERE + 1)
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
CLRF
Clear f
[ label ] CLRF
Status Affected: TO, PD
Syntax:
f
Encoding:
0000
0000
0100
Operands:
Operation:
0 ≤ f ≤ 31
Description:
The CLRWDTinstruction resets the
WDT. It also resets the prescaler, if
the prescaler is assigned to the
WDT and not Timer0. Status bits
TO and PD are set.
00h → (f);
1 → Z
Status Affected:
Encoding:
Z
0000
011f
ffff
Words:
1
Description:
The contents of register ’f’ are
cleared and the Z bit is set.
Cycles:
Example:
1
CLRWDT
Words:
1
1
Before Instruction
Cycles:
Example:
WDT counter
After Instruction
WDT counter
=
=
?
CLRF
FLAG_REG
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
0x00
=
0x5A
WDT prescaler =
TO
PD
0
1
1
=
=
=
=
0x00
1
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 53
PIC16C5X
COMF
Complement f
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Operands:
0 ≤ f ≤ 31
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d; skip if result = 0
Status Affected:
Encoding:
Z
Status Affected: None
0010
01df
ffff
Encoding:
0010
11df
ffff
Description:
The contents of register ’f’ are
complemented. If ’d’ is 0 the result
is stored in the W register. If ’d’ is 1
the result is stored back in
register ’f’.
Description:
The contents of register 'f' are dec-
remented. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in
register 'f'.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded and a NOPis executed
instead making it a two-cycle
instruction.
Words:
1
1
Cycles:
Example:
COMF
REG1,0
0x13
Before Instruction
Words:
1
REG1
=
After Instruction
Cycles:
Example:
1(2)
REG1
W
=
=
0x13
0xEC
HERE
DECFSZ
GOTO
CNT, 1
LOOP
CONTINUE •
•
•
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Before Instruction
PC
After Instruction
CNT
=
address(HERE)
Operands:
0 ≤ f ≤ 31
d
[0,1]
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
Operation:
(f) – 1 → (dest)
if CNT
PC
if CNT
PC
Status Affected:
Encoding:
Z
0000
11df
ffff
address (HERE+1)
Description:
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If
'd' is 1 the result is stored back in
register 'f'.
Words:
1
1
Cycles:
Example:
DECF
CNT, 1
0x01
Before Instruction
CNT
Z
=
=
0
After Instruction
CNT
Z
=
=
0x00
1
DS30453D-page 54
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
GOTO
Unconditional Branch
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] GOTO k
Syntax:
[ label ] INCFSZ f,d
Operands:
Operation:
0 ≤ k ≤ 511
Operands:
0 ≤ f ≤ 31
d
[0,1]
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected: None
Status Affected: None
Encoding:
101k
kkkk
kkkk
Encoding:
0011
11df
ffff
Description:
GOTOis an unconditional branch.
The 9-bit immediate value is
loaded into PC bits <8:0>. The
upper bits of PC are loaded from
STATUS<6:5>. GOTOis a two-
cycle instruction.
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1
the result is placed back in
register ’f’.
If the result is 0, then the next
instruction, which is already
fetched, is discarded and a NOPis
executed instead making it a two-
cycle instruction.
Words:
1
Cycles:
Example:
2
GOTO THERE
Words:
1
After Instruction
PC
=
address (THERE)
Cycles:
Example:
1(2)
HERE
INCFSZ
GOTO
CONTINUE •
CNT, 1
LOOP
INCF
Increment f
•
•
Syntax:
[ label ] INCF f,d
Operands:
0 ≤ f ≤ 31
Before Instruction
d
[0,1]
PC
After Instruction
CNT
=
address (HERE)
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
if CNT
PC
0010
10df
ffff
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1
the result is placed back in
register ’f’.
if CNT
PC
address (HERE +1)
Words:
1
1
Cycles:
Example:
INCF
CNT,
1
Before Instruction
CNT
Z
=
=
0xFF
0
After Instruction
CNT
Z
=
=
0x00
1
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 55
PIC16C5X
IORLW
Inclusive OR literal with W
MOVF
Move f
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] MOVF f,d
0 ≤ f ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Operands:
d
[0,1]
(W) .OR. (k) → (W)
Z
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
1101
kkkk
kkkk
0010
00df
ffff
Description:
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Description:
The contents of register 'f' is
moved to destination 'd'. If 'd' is 0,
destination is the W register. If 'd'
is 1, the destination is file
register 'f'. 'd' is 1 is useful to test a
file register since status flag Z is
affected.
Words:
1
Cycles:
Example:
1
IORLW 0x35
Words:
1
1
Before Instruction
0x9A
After Instruction
W
=
Cycles:
Example:
MOVF
FSR,
0
W
Z
=
=
0xBF
0
After Instruction
W
=
value in FSR register
IORWF
Inclusive OR W with f
Syntax:
[ label ] IORWF f,d
0 ≤ f ≤ 31
MOVLW
Move Literal to W
Operands:
Syntax:
[ label ] MOVLW
0 ≤ k ≤ 255
k
d
[0,1]
Operands:
Operation:
Operation:
(W).OR. (f) → (dest)
k → (W)
Status Affected:
Encoding:
Z
Status Affected: None
0001
00df
ffff
Encoding:
1100
kkkk
kkkk
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in
register 'f'.
Description:
The eight bit literal 'k' is loaded into
the W register.
Words:
1
Cycles:
Example:
1
Words:
1
1
MOVLW 0x5A
Cycles:
Example:
After Instruction
IORWF
RESULT, 0
W
=
0x5A
Before Instruction
RESULT
W
=
=
0x13
0x91
After Instruction
RESULT
W
Z
=
=
=
0x13
0x93
0
DS30453D-page 56
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
MOVWF
Move W to f
OPTION
Load OPTION Register
Syntax:
[ label ] OPTION
None
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 31
f
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
(W) → (f)
Status Affected: None
Status Affected: None
Encoding:
0000
0000
0010
Encoding:
0000
001f
ffff
Description:
The content of the W register is
loaded into the OPTION register.
Description:
Move data from the W register to
register ’f’.
Words:
Cycles:
Example
1
Words:
1
1
Cycles:
Example:
1
OPTION
MOVWF TEMP_REG
Before Instruction
Before Instruction
TEMP_REG = 0xFF
W
=
0x07
0x07
After Instruction
OPTION
W
=
0x4F
=
After Instruction
TEMP_REG = 0x4F
0x4F
W
=
RETLW
Return with Literal in W
Syntax:
[ label ] RETLW k
Operands:
Operation:
0 ≤ k ≤ 255
NOP
No Operation
k → (W);
TOS → PC
Syntax:
[ label ] NOP
None
Operands:
Operation:
Status Affected: None
No operation
Encoding:
1000
kkkk
kkkk
Status Affected: None
Description:
The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address). This
is a two-cycle instruction.
Encoding:
Description:
Words:
0000
0000
0000
No operation.
1
Cycles:
1
Words:
1
2
Example:
NOP
Cycles:
Example:
CALL TABLE ;W contains
;table offset
;value.
•
•
•
;W now has table
;value.
TABLE
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2
;
•
•
•
RETLW kn ; End of table
Before Instruction
W
=
=
0x07
After Instruction
W
value of k8
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 57
PIC16C5X
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
Syntax:
[ label ] RLF f,d
Syntax:
[ label ] RRF f,d
Operands:
0 ≤ f ≤ 31
Operands:
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
See description below
C
Operation:
See description below
C
Status Affected:
Encoding:
Status Affected:
Encoding:
0011
01df
ffff
0011
00df
ffff
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag (STATUS<0>). If ’d’
is 0 the result is placed in the W
register. If ’d’ is 1 the result is
stored back in
Description:
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag (STATUS<0>). If ’d’
is 0 the result is placed in the W
register. If ’d’ is 1 the result is
placed back in
register ’f’.
register ’f’.
register ’f’
C
register ’f’
C
Words:
1
Words:
1
1
Cycles:
Example:
1
Cycles:
Example:
RLF
REG1,0
RRF
REG1,0
Before Instruction
Before Instruction
REG1
C
=
=
1110 0110
0
REG1
C
=
=
1110 0110
0
After Instruction
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
REG1
W
C
=
=
=
1110 0110
0111 0011
0
SLEEP
Enter SLEEP Mode
Syntax:
[label] SLEEP
None
Operands:
Operation:
00h → WDT;
0 → WDT prescaler; if assigned
1 → TO;
0 → PD
Status Affected: TO, PD
Encoding:
0000
0000
0011
Description:
Time-out status bit (TO) is set. The
power-down status bit (PD) is
cleared. The WDT and its pres-
caler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See section on SLEEP for more
details.
Words:
1
Cycles:
Example:
1
SLEEP
DS30453D-page 58
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[label] SUBWF f,d
Syntax:
[ label ] SWAPF f,d
0 ≤ f ≤ 31
Operands:
0 ≤ f ≤ 31
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) – (W) → (dest)
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected: C, DC, Z
Status Affected: None
Encoding:
0000
10df
ffff
Encoding:
0011
10df
ffff
Description:
Subtract (2’s complement method)
the W register from register 'f'. If 'd'
is 0 the result is stored in the W
register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is 0
the result is placed in W register. If
'd' is 1 the result is placed in
register 'f'.
Words:
1
1
Words:
Cycles:
Example
1
1
Cycles:
Example 1:
SUBWF
REG1, 1
SWAPF REG1,
0
Before Instruction
REG1
W
C
=
=
=
3
2
?
Before Instruction
REG1
After Instruction
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0x5A
REG1
W
=
=
=
1
2
1
C
; result is positive
Example 2:
Before Instruction
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
f
REG1
W
C
=
=
=
2
2
?
Operands:
Operation:
f = 5, 6 or 7
(W) → TRIS register f
After Instruction
Status Affected: None
REG1
W
C
=
=
=
0
2
1
Encoding:
0000
0000
0fff
; result is zero
Description:
TRIS register 'f' (f = 5, 6, or 7) is
loaded with the contents of the W
register.
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
Words:
Cycles:
Example
1
1
After Instruction
TRIS
PORTB
REG1
W
C
=
=
=
0xFF
2
0
Before Instruction
W
=
0xA5
0xA5
; result is negative
After Instruction
TRISB
=
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 59
PIC16C5X
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) .XOR. k → (W)
Z
1111
kkkk
kkkk
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Words:
1
Cycles:
Example:
1
XORLW 0xAF
Before Instruction
W
=
0xB5
After Instruction
W
=
0x1A
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f,d
0 ≤ f ≤ 31
Operands:
d
[0,1]
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Encoding:
Z
0001
10df
ffff
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0
the result is stored in the W regis-
ter. If 'd' is 1 the result is stored
back in register 'f'.
Words:
Cycles:
Example
1
1
XORWF REG,1
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS30453D-page 60
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
The MPLAB IDE allows you to:
11.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
11.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
11.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
11.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 61
PIC16C5X
11.4 MPLINK Object Linker/
MPLIB Object Librarian
11.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
11.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
11.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C17 and the MPLAB C18 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS30453D-page 62
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
11.8 MPLAB ICD In-Circuit Debugger
11.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip’s In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip’s In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
11.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In Stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
11.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
11.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 63
PIC16C5X
11.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
11.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
11.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS30453D-page 64
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X X F 8 C 1 P I
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X X X C 2 C 1 P I
s o l T e o r a w f t S o s r o t a u l E m e r u b g e g D s m e a r m o g P r r
s t l K a i E d v n a s d r a B o o m D e
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 65
PIC16C5X
NOTES:
DS30453D-page 66
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
12.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57
Absolute Maximum Ratings(†)
Ambient Temperature under bias..................................................................................................... –55°C to +125°C
Storage Temperature ....................................................................................................................... –65°C to +150°C
Voltage on VDD with respect to VSS ..........................................................................................................0V to +7.5V
Voltage on MCLR with respect to VSS(1) ....................................................................................................0V to +14V
Voltage on all other pins with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)
Total power dissipation(2) ............................................................................................................................... 800 mW
Max. current out of VSS pin ............................................................................................................................. 150 mA
Max. current into VDD pin................................................................................................................................ 100 mA
Max. current into an input pin (T0CKI only)....................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................±20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA, B or C) .................................................................. 40 mA
Max. output current sunk by a single I/O port (PORTA, B or C)........................................................................50 mA
Note 1: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather
than pulling this pin directly to VSS.
2: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 67
PIC16C5X
12.1 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
PIC16C54/55/56/57-RC, XT, 10, HS, LP
Standard Operating Conditions (unless otherwise specified)
(Commercial)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
Param
No.
Symbol
Characteristic/Device
Min
Typ†
Max Units
Conditions
D001
VDD
Supply Voltage
PIC16C5X-RC
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-LP
3.0
3.0
4.5
4.5
2.5
—
—
—
—
—
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
D002
D003
VDR
RAM Data Retention Voltage(1)
1.5*
—
—
V
V
Device in SLEEP Mode
VPOR VDD Start Voltage to ensure
VSS
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD Rise Rate to ensure
0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
Supply Current(2)
PIC16C5X-RC(3)
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-HS
PIC16C5X-LP
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
32
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D020
IPD
Power-down Current(2)
—
—
4.0
0.6
12
9
µA
µA
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 68
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
12.2 DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI
Standard Operating Conditions (unless otherwise specified)
(Industrial)
Operating Temperature –40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Supply Voltage
Min
Typ†
Max Units
Conditions
D001
VDD
PIC16C5X-RCI
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-LPI
3.0
3.0
4.5
4.5
2.5
—
—
—
—
—
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
D002
D003
VDR
RAM Data Retention Voltage(1)
—
—
1.5*
—
—
V
V
Device in SLEEP mode
VPOR VDD Start Voltage to ensure
VSS
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD Rise Rate to ensure
0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
Supply Current(2)
PIC16C5X-RCI(3)
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-HSI
PIC16C5X-LPI
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
40
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
D020
IPD
Power-down Current(2)
—
—
4.0
0.6
14
12
µA
µA
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 69
PIC16C5X
12.3 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE
Standard Operating Conditions (unless otherwise specified)
(Extended)
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic/Device
Supply Voltage
Min
Typ†
Max Units
Conditions
D001
VDD
PIC16C5X-RCE
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-LPE
3.25
3.25
4.5
4.5
2.5
—
—
—
—
—
6.0
6.0
5.5
5.5
6.0
V
V
V
V
V
D002
D003
VDR
RAM Data Retention Voltage(1)
—
—
1.5*
—
—
V
V
Device in SLEEP mode
VPOR VDD Start Voltage to ensure
VSS
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD Rise Rate to ensure
0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
Supply Current(2)
PIC16C5X-RCE(3)
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-HSE
PIC16C5X-LPE
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
19
3.3
3.3
10
10
20
55
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.25V,
WDT disabled
D020
IPD
Power-down Current(2)
—
—
5.0
0.8
22
18
µA
µA
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and is
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT
enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 70
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
12.4 DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Param
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Symbol
Characteristic/Device
Min
Typ†
Max
Units
Conditions
No.
D030
VIL
Input Low Voltage
I/O ports
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
D040
VIH
Input High Voltage
I/O ports
I/O ports
(4)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(4)
VDD > 5.5V
I/O ports
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current(1,2)
For VDD ≤ 5.5V:
I/O ports
–1
0.5
+1
µA
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
MCLR
MCLR
T0CKI
OSC1
–5
—
–3
–3
—
—
+5
+3
+3
µA VPIN = VSS + 0.25V
0.5
0.5
0.5
µA
µA
µA
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
PIC16C5X-XT, 10, HS, LP
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 71
PIC16C5X
12.5 DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Operating Temperature
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
D030
VIL
Input Low Voltage
I/O ports
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
D040
VIH
Input High Voltage
I/O ports
I/O ports
(4)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(4)
VDD > 5.5 V
I/O ports
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(3)
PIC16C5X-XT, 10, HS, LP
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current (1,2)
For VDD ≤ 5.5 V:
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
PIC16C5X-XT, 10, HS, LP
I/O ports
–1
0.5
+1
µA
MCLR
MCLR
T0CKI
OSC1
–5
—
–3
–3
—
—
+5
+3
+3
µA
µA
µA
µA
0.5
0.5
0.5
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
DS30453D-page 72
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
12.6 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
mc MCLR
ck CLKOUT
osc oscillator
os OSC1
cy cycle time
drt device reset timer
io I/O port
t0 T0CKI
wdt watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 12-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54/55/56/57
Pin
CL =
50 pF
for all pins and OSC2 for RC mode
CL
0 - 15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 73
PIC16C5X
12.7
Timing Diagrams and Specifications
FIGURE 12-2:
EXTERNAL CLOCK TIMING - PIC16C54/55/56/57
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min Typ†
Max Units
Conditions
1A
FOSC
External CLKIN Frequency(1) DC
—
—
—
—
—
—
—
—
—
—
—
4.0
10
20
16
40
4.0
4.0
10
20
16
40
MHz XT OSC mode
MHz 10 MHz mode
DC
DC
DC
DC
MHz HS OSC mode (Comm/Ind)
MHz HS OSC mode (Ext)
kHz LP OSC mode
Oscillator Frequency(1)
DC
0.1
4.0
4.0
4.0
DC
MHz RC OSC mode
MHz XT OSC mode
MHz 10 MHz mode
MHz HS OSC mode (Comm/Ind)
MHz HS OSC mode (Ext)
kHz LP OSC mode
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 74
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min Typ†
Max Units
Conditions
1
TOSC
External CLKIN Period(1)
250
100
50
—
—
—
—
ns XT OSC mode
ns 10 MHz mode
—
—
ns HS OSC mode (Comm/Ind)
ns HS OSC mode (Ext)
µs LP OSC mode
ns RC OSC mode
ns XT OSC mode
ns 10 MHz mode
ns HS OSC mode (Comm/Ind)
ns HS OSC mode (Ext)
µs LP OSC mode
—
62.5
25
—
—
—
—
Oscillator Period(1)
250
250
100
50
—
—
—
10,000
250
250
250
—
—
—
62.5
25
—
—
2
3
Tcy
Instruction Cycle Time(2)
—
4/FOSC
—
—
TosL,
TosH
Clock in (OSC1) Low or High 85*
—
ns XT oscillator
Time
20*
—
—
ns HS oscillator
2.0*
—
—
µs LP oscillator
4
TosR,
TosF
Clock in (OSC1) Rise or Fall
Time
—
—
—
—
25*
25*
50*
ns XT oscillator
—
ns HS oscillator
—
ns LP oscillator
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 75
PIC16C5X
FIGURE 12-3:
CLKOUT AND I/O TIMING - PIC16C54/55/56/57
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
18
14
19
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
OSC1↑ to CLKOUT↓(1)
TosH2ckH OSC1↑ to CLKOUT↑(1)
Min
Typ†
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
TckR
CLKOUT rise time(1)
—
TckF
CLKOUT fall time(1)
—
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
CLKOUT↓ to Port out valid(1)
Port in valid before CLKOUT↑(1)
Port in hold after CLKOUT↑(1)
OSC1↑ (Q1 cycle) to Port out valid(2)
—
0.25 TCY+30*
—
0*
—
—
—
—
100*
—
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
TioR
TioF
Port output rise time(2)
—
—
10
10
25**
25**
ns
ns
Port output fall time(2)
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x Tosc.
2: Please refer to Figure 12-1 for load conditions.
DS30453D-page 76
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 12-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -
PIC16C54/55/56/57
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 12-1 for load conditions.
TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
30
TmcL
MCLR Pulse Width (low)
100*
—
—
ns VDD = 5.0V
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
9.0*
18*
30*
ms VDD = 5.0V (Comm)
32
TDRT
TioZ
Device Reset Timer Period
9.0*
—
18*
—
30*
ms VDD = 5.0V (Comm)
34
*
I/O Hi-impedance from MCLR Low
100*
ns
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 77
PIC16C5X
FIGURE 12-5:
TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57
T0CKI
40
41
42
Note: Please refer to Figure 12-1 for load conditions.
TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
40
Tt0H
T0CKI High Pulse Width
- No Prescaler
0.5 TCY + 20*
—
—
—
—
ns
ns
- With Prescaler
10*
41
Tt0L
Tt0P
T0CKI Low Pulse Width
- No Prescaler
0.5 TCY + 20*
—
—
—
—
—
—
ns
ns
- With Prescaler
10*
42
*
T0CKI Period
20 or TCY + 40*
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
N
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453D-page 78
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
13.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A
Absolute Maximum Ratings(†)
Ambient Temperature under bias..................................................................................................... –55°C to +125°C
Storage Temperature ....................................................................................................................... –65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS(1) ......................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)
Total power dissipation(2) ............................................................................................................................... 800 mW
Max. current out of VSS pin ............................................................................................................................. 150 mA
Max. current into VDD pin.................................................................................................................................. 50 mA
Max. current into an input pin (T0CKI only) .............................................................................................................. ±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD) ...............................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD) ........................................................................................................±20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA or B)....................................................................... 40 mA
Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA
Note 1: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus,
a series resistor of 50 to 100 Ω should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to Vss.
2: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 79
PIC16C5X
13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LCR54A-04
PIC16LCR54A-04I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16CR54A-04, 10, 20
PIC16CR54A-04I, 10I, 20I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Supply Voltage
Min
Typ†
Max
Units
Conditions
VDD
D001
PIC16LCR54A 2.0
—
6.25
V
D001
D001A
PIC16CR54A 2.5
4.5
—
—
6.25
5.5
V
V
RC and XT modes
HS mode
D002
D003
D004
VDR
VPOR
SVDD
IDD
RAM Data Retention
—
1.5*
VSS
—
—
—
—
V
Device in SLEEP mode
Voltage(1)
VDD Start Voltage to ensure
Power-on Reset
—
V
See Section 5.1 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
Supply Current(2)
0.05*
V/ms See Section 5.1 for details on
Power-on Reset
D005
PICLCR54A
—
—
10
—
20
70
µA
µA
Fosc = 32 kHz, VDD = 2.0V
Fosc = 32 kHz, VDD = 6.0V
D005A
RC(3) and XT modes:
PIC16CR54A
—
—
—
2.0
0.8
90
3.6
1.8
350
mA
mA
µA
FOSC = 4.0 MHz, VDD = 6.0V
FOSC = 4.0 MHz, VDD = 3.0V
FOSC = 200 kHz, VDD = 2.5V
HS mode:
—
—
4.8
9.0
10
20
mA
mA
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 80
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
13.1 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LCR54A-04
PIC16LCR54A-04I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16CR54A-04, 10, 20
PIC16CR54A-04I, 10I, 20I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Min
Typ†
Max
Units
Conditions
IPD
Power-down Current(2)
D006
PIC16LCR54A-Commercial
—
—
—
—
1.0
2.0
3.0
5.0
6.0
8.0*
15
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
25
D006A
D007
PIC16CR54A-Commercial
PIC16LCR54A-Industrial
—
—
—
—
1.0
2.0
3.0
5.0
6.0
8.0*
15
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
25
—
—
—
—
—
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
µA
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
45
D007A
PIC16CR54A-Industrial
—
—
—
—
—
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
µA
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
45
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 81
PIC16C5X
13.2 DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
PIC16CR54A-04E, 10E, 20E
(Extended)
Param
No.
Symbol
Characteristic
Min
Typ†
Max Units
Conditions
D001
VDD
Supply Voltage
RC, XT and LP modes
HS mode
3.25
4.5
—
—
6.0
5.5
V
V
D002
D003
VDR
RAM Data Retention Voltage(1)
—
—
1.5*
—
—
V
V
Device in SLEEP mode
VPOR VDD Start Voltage to ensure
VSS
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD Rise Rate to ensure Power- 0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
on Reset
IDD
Supply Current(2)
RC(3) and XT modes
HS mode
—
—
—
1.8
4.8
9.0
3.3
10
20
mA
mA
mA
FOSC = 4.0 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
HS mode
D020
IPD
Power-down Current(2)
—
—
5.0
0.8
22
18
µA
µA
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design
guidance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode.The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 82
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
13.3 DC Characteristics:PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC CHARACTERISTICS
Param
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
No.
D030
VIL
Input Low Voltage
I/O ports
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
V
V
V
V
V
Pin at hi-impedance
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC mode only(3)
XT, HS and LP modes
D040
VIH
Input High Voltage
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
2.0
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
VDD = 3.0V to 5.5V(4)
Full VDD range(4)
0.6 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.85 VDD
RC mode only(3)
XT, HS and LP modes
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current(1,2)
For VDD ≤ 5.5V:
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP modes
I/O ports
–1.0
—
+1.0
µA
MCLR
MCLR
T0CKI
OSC1
–5.0
—
–3.0
–3.0
—
—
µA
µA
µA
µA
0.5
0.5
0.5
+5.0
+3.0
+3.0
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.5
0.5
V
V
IOL = 10 mA, VDD = 6.0V
IOL = 1.9 mA, VDD = 6.0V,
RC mode only
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOH = –4.0 mA, VDD = 6.0V
IOH = –0.8 mA, VDD = 6.0V,
RC mode only
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 83
PIC16C5X
13.4 DC Characteristics:PIC16CR54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
D030
VIL
Input Low Voltage
I/O ports
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC mode only(3)
XT, HS and LP modes
D040
VIH
Input High Voltage
I/O ports
I/O ports
(4)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(4)
VDD > 5.5V
I/O ports
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC mode only(3)
XT, HS and LP modes
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current(1,2)
For VDD ≤ 5.5V:
I/O ports
–1.0
0.5
+1.0
µA
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP modes
MCLR
MCLR
T0CKI
OSC1
–5.0
—
–3.0
–3.0
—
—
µA
µA
µA
µA
0.5
0.5
0.5
+5.0
+3.0
+3.0
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC mode only
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
RC mode only
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
4: The user may use the better of the two specifications.
DS30453D-page 84
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
13.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
mc MCLR
ck CLKOUT
osc oscillator
os OSC1
cy cycle time
drt device reset timer
io I/O port
t0 T0CKI
wdt watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 13-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16CR54A
Pin
CL = 50 pF
for all pins and OSC2 for RC modes
CL
0 -15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 85
PIC16C5X
13.6 Timing Diagrams and Specifications
FIGURE 13-2:
EXTERNAL CLOCK TIMING - PIC16CR54A
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min
Typ†
Max Units
Conditions
FOSC
External CLKIN Frequency(1)
DC
DC
DC
DC
DC
DC
0.1
4.0
4.0
4.0
5.0
—
—
—
—
—
—
—
—
—
—
—
4.0
4.0
10
MHz XT OSC mode
MHz HS OSC mode (04)
MHz HS OSC mode (10)
MHz HS OSC mode (20)
kHz LP OSC mode
20
200
4.0
4.0
4.0
10
Oscillator Frequency(1)
MHz RC OSC mode
MHz XT OSC mode
MHz HS OSC mode (04)
MHz HS OSC mode (10)
MHz HS OSC mode (20)
kHz LP OSC mode
20
200
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 86
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min
Typ†
Max Units
Conditions
1
TOSC
External CLKIN Period(1)
250
250
100
50
—
—
—
—
—
—
—
—
ns XT OSC mode
ns HS OSC mode (04)
—
ns HS OSC mode (10)
ns HS OSC mode (20)
µs LP OSC mode
—
5.0
250
250
250
100
50
—
Oscillator Period(1)
—
ns RC OSC mode
—
10,000 ns XT OSC mode
—
250
250
250
200
—
ns HS OSC mode (04)
ns HS OSC mode (10)
ns HS OSC mode (20)
µs LP OSC mode
—
—
—
5.0
—
—
2
3
Tcy
Instruction Cycle Time(2)
4/FOSC
—
TosL, TosH Clock in (OSC1) Low or High
Time
50*
20*
2.0*
—
—
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
—
—
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
25*
25*
50*
—
—
—
—
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 87
PIC16C5X
FIGURE 13-3:
CLKOUT AND I/O TIMING - PIC16CR54A
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
12
13
18
19
16
14
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL
TosH2ckH
TckR
OSC1↑ to CLKOUT↓(1)
OSC1↑ to CLKOUT↑(1)
CLKOUT rise time(1)
CLKOUT fall time(1)
CLKOUT↓ to Port out valid(1)
Port in valid before CLKOUT↑(1)
Port in hold after CLKOUT↑(1)
OSC1↑ (Q1 cycle) to Port out valid(2)
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
TckF
—
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
—
0.25 TCY+30*
—
0*
—
—
—
—
100*
—
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
Port output rise time(2)
Port output fall time(2)
20
21
*
TioR
TioF
—
—
10
10
25**
25**
ns
ns
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Please refer to Figure 13.1 for load conditions.
DS30453D-page 88
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 13-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 13.1 for load conditions.
TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
1.0*
—
—
µs VDD = 5.0V
31
Twdt
Watchdog Timer Time-out Period
7.0*
18*
40*
ms VDD = 5.0V (Comm)
(No Prescaler)
32
34
TDRT
TioZ
Device Reset Timer Period
7.0*
—
18*
—
30*
ms VDD = 5.0V (Comm)
µs
I/O Hi-impedance from MCLR Low
1.0*
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 89
PIC16C5X
FIGURE 13-5:
TIMER0 CLOCK TIMINGS - PIC16CR54A
T0CKI
40
41
42
Note: Please refer to Figure 13.1 for load conditions.
TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse Width
- No Prescaler
- With Prescaler
Tt0L T0CKI Low Pulse Width
0.5 TCY + 20*
—
—
—
—
ns
ns
10*
- No Prescaler
0.5 TCY + 20*
—
—
—
—
—
—
ns
ns
- With Prescaler
10*
Tt0P T0CKI Period
20 or TCY + 40*
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
N
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453D-page 90
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
14.0 DEVICE CHARACTERIZATION - PIC16C54/55/56/57/CR54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-
teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean
– 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 14-1:
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
REXT ≥ 10 kΩ
1.08
1.06
1.04
1.02
1.00
CEXT = 100 pF
0.98
0.96
0.94
VDD = 5.5V
VDD = 3.5V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 14-1: RC OSCILLATOR FREQUENCIES
Average
FOSC @ 5 V, 25°C
CEXT
REXT
20 pF
3.3K
5K
5 MHz
3.8 MHz
2.2 MHz
262 kHz
1.6 MHz
1.2 MHz
684 kHz
71 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10K
100K
3.3K
5K
100 pF
300 pF
10K
100K
3.3K
5.0K
10K
100K
660 kHz
484 kHz
267 kHz
29 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviations from the average value for VDD = 5V.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 91
PIC16C5X
FIGURE 14-2:
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 20 PF
FIGURE 14-3:
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 100 PF
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
5.5
5.0
1.8
1.6
1.4
1.2
1.0
R = 3.3K
R = 3.3K
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
R = 5K
R = 5K
0.8
0.6
0.4
0.2
0.0
R = 10K
R = 10K
Measured on DIP Packages, T = 25°C
Measured on DIP Packages, T = 25°C
R = 100K
3.0
3.5
4.0
4.5
DD (Volts)
5.0
5.5
6.0
R = 100K
5.5
V
3.0
3.5
4.0
4.5
5.0
6.0
VDD (Volts)
DS30453D-page 92
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-4:
TYPICAL RC OSC
FREQUENCY vs. VDD,
CEXT = 300 PF
FIGURE 14-5:
TYPICAL IPD vs. VDD,
WATCHDOG DISABLED
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
2.0
1.5
800
700
600
500
400
300
200
100
0
R = 3.3K
R = 5K
T = 25°C
1.0
0.5
0.0
R = 10K
Measured on DIP Packages, T = 25°C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
R = 100K
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 93
PIC16C5X
FIGURE 14-6:
MAXIMUM IPD vs. VDD,
WATCHDOG DISABLED
FIGURE 14-8:
MAXIMUM IPD vs. VDD,
WATCHDOG ENABLED
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
60
100
50
40
+125°C
+85°C
10
–55°C
+70°C
0°C
+85°C
30
–40°C
–55°C
+125°C
–40°C
+70°C
1
0
20
10
0
0°C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
DD (Volts)
V
V
DD (Volts)
IPD, with WDT enabled, has two components:
The leakage current, which increases with higher temper-
ature, and the operating current of the WDT logic, which
increases with lower temperature. At –40°C, the latter
dominates explaining the apparently anomalous behav-
ior.
FIGURE 14-7:
TYPICAL IPD vs. VDD,
WATCHDOG ENABLED
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
20
18
16
14
12
T = 25°C
10
8
6
4
2
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
DS30453D-page 94
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-9:
VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.00
1.80
1.60
1.40
1.20
C)
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
C)
°
5
2
+
(
p
y
T
C)
°
5
8
+
to
1.00
0.80
C
°
0
4
–
(
in
M
0.60
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 14-10:
VIH, VIL OF MCLR, T0CKI AND OSC1 (RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0
3.5
C)
°
85
+
o
t
C
°
40
–
(
x
a
m
H
I
V
)
3.0
2.5
2.0
1.5
C
°
5
8
+
o
t
C
°
0
–4
(
n
i
m
H
I
V
IL
IH
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
These input pins have Schmitt Trigger input buffers.
5.0
5.5
6.0
Note:
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 95
PIC16C5X
FIGURE 14-11:
VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(XT, HS, AND LP MODES) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
)
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
1.8
1.6
1.4
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 14-12:
TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
1.0
0.1
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10K
100K
1M
10M
100M
External Clock Frequency (Hz)
DS30453D-page 96
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-13:
MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
1.0
7.0
6.5
6.0
5.5
5.0
0.1
4.5
4.0
3.5
3.0
2.5
0.01
10K
100K
1M
External Clock Frequency (Hz)
10M
100M
FIGURE 14-14:
MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55°C TO +125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10
1.0
0.1
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10K
100K
1M
10M
100M
External Clock Frequency (Hz)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 97
PIC16C5X
FIGURE 14-15:
WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 14-16:
TRANSCONDUCTANCE
(gm) OF HS OSCILLATOR
vs. VDD
(1)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
50
45
40
9000
8000
7000
Max –40°C
35
30
6000
5000
Max +85
°
C
C
Typ +25°C
25
4000
Max +70
°
20
15
Typ +25°C
3000
2000
Min +85°C
MIn 0°C
10
5
MIn –40°C
100
0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
2.0
3.0
4.0
5.0
6.0
7.0
Note 1: Prescaler set to 1:1.
VDD (Volts)
DS30453D-page 98
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-17:
TRANSCONDUCTANCE
(gm) OF LP OSCILLATOR
vs. VDD
FIGURE 14-18:
TRANSCONDUCTANCE
(gm) OF XT OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
40
35
2500
2000
1500
1000
Max –40°C
Max –40°C
30
25
Typ +25°C
Typ +25°C
20
15
10
Min +85°C
500
Min +85°C
5
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
VDD (Volts)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 99
PIC16C5X
FIGURE 14-19:
PORTA, B AND C IOH vs.
VOH, VDD = 3 V
FIGURE 14-20:
PORTA, B AND C IOH vs.
VOH, VDD = 5 V
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
–5
0
Min +85°C
–10
Min +85°C
–10
–15
–20
Typ +25°C
Typ +25°C
Max –40°C
–30
–40
Max –40°C
–20
–25
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0
0.5
1.0
1.5
2.0
2.5
3.0
VOH (Volts)
DS30453D-page 100
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 14-21:
PORTA, B AND C IOL vs.
VOL, VDD = 3 V
FIGURE 14-22:
PORTA, B AND C IOL vs.
VOL, VDD = 5 V
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
40
35
90
80
70
Max –40°C
Max –40°C
30
25
20
60
50
Typ +25°C
Typ +25°C
Min +85°C
40
Min +85°C
15
10
30
20
5
0
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
VOL (Volts)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 101
PIC16C5X
TABLE 14-2: INPUT CAPACITANCE FOR
PIC16C54/56
Typical Capacitance (pF)
Pin
18L PDIP
18L SOIC
RA port
RB port
5.0
4.3
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
TABLE 14-3: INPUT CAPACITANCE FOR
PIC16C55/57
Typical Capacitance (pF)
Pin
28L PDIP
(600 mil)
28L SOIC
RA port
RB port
5.2
5.6
5.0
17.0
6.6
4.6
4.5
4.8
4.7
4.1
17.0
3.5
3.5
3.5
RC port
MCLR
OSC1
OSC2/CLKOUT
T0CKI
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
DS30453D-page 102
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
15.0 ELECTRICAL CHARACTERISTICS - PIC16C54A
Absolute Maximum Ratings(†)
Ambient temperature under bias...................................................................................................... –55°C to +125°C
Storage temperature ....................................................................................................................... –65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS..........................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ............................................................................–0.6V to (VDD + 0.6V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Max. current out of VSS pin ............................................................................................................................. 150 mA
Max. current into VDD pin................................................................................................................................ 100 mA
Max. current into an input pin (T0CKI only) .............................................................................................................. ±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD)..............................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ........................................................................................................±20 mA
Max. output current sunk by any I/O pin ........................................................................................................... 25 mA
Max. output current sourced by any I/O pin...................................................................................................... 20 mA
Max. output current sourced by a single I/O port (PORTA or B)....................................................................... 50 mA
Max. output current sunk by a single I/O port (PORTA or B) ............................................................................ 50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 103
PIC16C5X
15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LC54A-04
PIC16LC54A-04I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16C54A-04, 10, 20
PIC16C54A-04I, 10I, 20I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Min Typ† Max Units
Conditions
VDD
Supply Voltage
PIC16LC54A 3.0
D001
D001A
D002
D003
D004
—
—
6.25
6.25
V
V
XT and RC modes
LP mode
2.5
PIC16C54A 3.0
4.5
—
—
6.25
5.5
V
V
RC, XT and LP modes
HS mode
VDR
RAM Data Retention
Voltage(1)
—
1.5*
Vss
—
—
—
—
V
Device in SLEEP mode
VPOR VDD Start Voltage to
—
V
See Section 5.1 for details on
Power-on Reset
ensure Power-on Reset
SVDD
IDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
V/ms See Section 5.1 for details on
Power-on Reset
Supply Current(2)
D005
PIC16LC5X
—
—
—
0.5
11
2.5 mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
27
35
µA FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Commercial
µA FOSC = 32 kHz, VDD = 2.5V,
WDT disabled, LP mode, Industrial
11
D005A
PIC16C5X
—
1.8
2.4 mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
—
—
—
2.4
4.5
14
8.0 mA FOSC = 10 MHz, VDD = 5.5V, HS mode
16
29
mA FOSC = 20 MHz, VDD = 5.5V, HS mode
µA FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Commercial
µA FOSC = 32 kHz, VDD = 3.0V,
WDT disabled, LP mode, Industrial
—
17
37
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 104
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
15.1 DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LC54A-04
PIC16LC54A-04I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16C54A-04, 10, 20
PIC16C54A-04I, 10I, 20I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Min Typ† Max Units
Conditions
IPD
Power-down Current(2)
PIC16LC5X
D006
—
—
—
—
2.5
0.25 4.0
2.5 14
0.25 5.0
4.0 12
0.25 4.0
12
µA VDD = 2.5V, WDT enabled, Commercial
µA VDD = 2.5V, WDT disabled, Commercial
µA VDD = 2.5V, WDT enabled, Industrial
µA VDD = 2.5V, WDT disabled, Industrial
D006A
PIC16C5X
—
—
—
—
µA VDD = 3.0V, WDT enabled, Commercial
µA VDD = 3.0V, WDT disabled, Commercial
µA VDD = 3.0V, WDT enabled, Industrial
µA VDD = 3.0V, WDT disabled, Industrial
5.0
0.3
14
5.0
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is based on characterization results at 25°C. This data is for design guidance only and
is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 105
PIC16C5X
15.2 DC Characteristics:
PIC16C54A-04E, 10E, 20E (Extended)
PIC16LC54A-04E (Extended)
PIC16LC54A-04E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise specified)
PIC16C54A-04E, 10E, 20E
(Extended)
Operating Temperature
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Supply Voltage
Min Typ† Max Units
Conditions
VDD
D001
PIC16LC54A 3.0
2.5
—
—
6.25
6.25
V
V
XT and RC modes
LP mode
D001A
PIC16C54A 3.5
4.5
—
—
5.5
5.5
V
V
RC and XT modes
HS mode
D002
D003
VDR
RAM Data Retention Voltage(1)
—
—
1.5*
Vss
—
—
V
V
Device in SLEEP mode
VPOR VDD Start Voltage to ensure
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD Rise Rate to ensure
0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
Supply Current(2)
PIC16LC54A
—
—
—
—
0.5
11
11
11
25
27
35
37
mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
µA FOSC = 32 kHz, VDD = 2.5V,
LP mode, Commercial
µA FOSC = 32 kHz, VDD = 2.5V,
LP mode, Industrial
µA FOSC = 32 kHz, VDD = 2.5V,
LP mode, Extended
D010A
PIC16C54A
—
—
—
1.8
4.8
9.0
3.3 mA FOSC = 4.0 MHz, VDD = 5.5V,
RC(3) and XT modes
10
20
mA FOSC = 10 MHz, VDD = 5.5V,
HS mode
mA FOSC = 20 MHz, VDD = 5.5V,
HS mode
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 106
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
15.2 DC Characteristics:
PIC16C54A-04E, 10E, 20E (Extended)
PIC16LC54A-04E (Extended)
PIC16LC54A-04E
(Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
Standard Operating Conditions (unless otherwise specified)
PIC16C54A-04E, 10E, 20E
(Extended)
Operating Temperature
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Power-down Current(2)
Min Typ† Max Units
Conditions
IPD
D020
PIC16LC54A
—
—
2.5
15
µA VDD = 2.5V, WDT enabled,
Extended
µA VDD = 2.5V, WDT disabled,
Extended
0.25 7.0
D020A
PIC16C54A
—
—
5.0
0.8
22
18*
µA VDD = 3.5V, WDT enabled
µA VDD = 3.5V, WDT disabled
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 107
PIC16C5X
15.3 DC Characteristics:PIC16LV54A-02 (Commercial)
PIC16LV54A-02I (Industrial)
PIC16LV54A-02
Standard Operating Conditions (unless otherwise specified)
PIC16LV54A-02I
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–20°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
D001
Supply Voltage
VDD
RC and XT modes
2.0
—
3.8
—
V
V
D002
D003
D004
D010
VDR
RAM Data Retention
Voltage(1)
—
1.5*
Device in SLEEP mode
VPOR VDD Start Voltage to ensure
—
Vss
—
—
—
V
See Section 5.1 for details on
Power-on Reset
Power-on Reset
SVDD VDD Rise Rate to ensure
0.05*
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
Supply Current(2)
RC(3) and XT modes
LP mode, Commercial
LP mode, Industrial
—
—
—
0.5
11
14
—
27
35
mA FOSC = 2.0 MHz, VDD = 3.0V
µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
D020
IPD
Power-down Current(2,4)
Commercial
—
—
—
—
2.5
0.25 4.0
3.5
0.3
12
µA VDD = 2.5V, WDT enabled
µA VDD = 2.5V, WDT disabled
µA VDD = 2.5V, WDT enabled
µA VDD = 2.5V, WDT disabled
Commercial
Industrial
Industrial
14
5.0
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
4: The oscillator start-up time can be as much as 8 seconds for XT and LP oscillator selection on wake-up from
SLEEP mode or during initial power-up.
DS30453D-page 108
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
15.4 DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)
PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)
PIC16C54A-04E, 10E, 20E, PIC16LC54A-04E (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
DC CHARACTERISTICS
Param
–40°C ≤ TA ≤ +85°C for industrial
–20°C ≤ TA ≤ +85°C for industrial-PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Symbol
Characteristic
Min
Typ†
Max
Units Conditions
No.
D030
VIL
Input Low Voltage
I/O ports
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
Pin at hi-impedance
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
(3)
RC mode only
XT, HS and LP modes
D040
VIH
Input High Voltage
I/O ports
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
(4)
0.2 VDD + 1
2.0
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
For all VDD
(4)
4.0V < VDD ≤ 5.5V
(3)
RC mode only
XT, HS and LP modes
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
(1,2)
IIL
Input Leakage Current
For VDD ≤ 5.5V:
I/O ports
-1.0
0.5
+1.0
µA
VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
MCLR
MCLR
T0CKI
OSC1
-5.0
—
-3.0
-3.0
—
+5.0
+3.0
+3.0
—
µA VPIN = VSS +0.25V
0.5
0.5
0.5
µA
µA
µA
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP modes
D080
VOL Output Low Voltage
I/O ports
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC mode only
OSC2/CLKOUT
(2)
VOH Output High Voltage
I/O ports
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC mode only
OSC2/CLKOUT
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only
and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be
driven with external clock in RC mode.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 109
PIC16C5X
15.5 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
mc MCLR
ck CLKOUT
osc oscillator
os OSC1
cy cycle time
drt device reset timer
io I/O port
t0 T0CKI
wdt watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 15-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS - PIC16C54A
Pin
CL = 50 pF
for all pins and OSC2 for RC modes
CL
0 -15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
VSS
DS30453D-page 110
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
15.6
Timing Diagrams and Specifications
FIGURE 15-2: EXTERNAL CLOCK TIMING - PIC16C54A
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
AC Characteristics
–20°C ≤ TA ≤ +85°C for industrial - PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Typ†
Max Units
Conditions
FOSC
External CLKIN Fre-
quency(1)
DC
DC
DC
DC
DC
DC
DC
DC
0.1
0.1
4.0
4.0
4.0
5.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0
2.0
4.0
10
MHz XT OSC mode
MHz XT OSC mode (PIC16LV54A)
MHz HS OSC mode (04)
MHz HS OSC mode (10)
MHz HS OSC mode (20)
kHz LP OSC mode
20
200
4.0
2.0
4.0
2.0
4.0
10
Oscillator Frequency(1)
MHz RC OSC mode
MHz RC OSC mode (PIC16LV54A)
MHz XT OSC mode
MHz XT OSC mode (PIC16LV54A)
MHz HS OSC mode (04)
MHz HS OSC mode (10)
MHz HS OSC mode (20)
kHz LP OSC mode
20
200
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 111
PIC16C5X
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
AC Characteristics
–20°C ≤ TA ≤ +85°C for industrial - PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Typ†
Max Units
Conditions
1
TOSC
External CLKIN Period(1) 250
—
—
—
—
—
—
—
—
—
—
ns XT OSC mode
500
250
100
50
ns XT OSC mode (PIC16LV54A)
ns HS OSC mode (04)
ns HS OSC mode (10)
ns HS OSC mode (20)
µs LP OSC mode
—
—
—
5.0
—
Oscillator Period(1)
250
500
250
500
250
100
50
—
ns RC OSC mode
—
ns RC OSC mode (PIC16LV54A)
—
10,000 ns XT OSC mode
—
—
250
250
250
200
—
ns XT OSC mode (PIC16LV54A)
—
ns HS OSC mode (04)
ns HS OSC mode (10)
ns HS OSC mode (20)
µs LP OSC mode
—
—
—
5.0
—
—
2
3
Tcy
Instruction Cycle Time(2)
4/FOSC
—
TosL, TosH Clock in (OSC1) Low or
High Time
85*
20*
2.0*
—
—
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
—
—
—
4
TosR, TosF Clock in (OSC1) Rise or
Fall Time
—
25*
25*
50*
—
—
—
—
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard
operating conditions with the device executing code. Exceeding these specified limits may result in an
unstable oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 112
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 15-3:
CLKOUT AND I/O TIMING - PIC16C54A
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
16
18
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
AC Characteristics
–20°C ≤ TA ≤ +85°C for industrial - PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL OSC1↑ to CLKOUT↓(1)
TosH2ckH OSC1↑ to CLKOUT↑(1)
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
TckR
CLKOUT rise time(1)
CLKOUT fall time(1)
—
TckF
—
TckL2ioV CLKOUT↓ to Port out valid(1)
TioV2ckH Port in valid before CLKOUT↑(1)
TckH2ioI Port in hold after CLKOUT↑(1)
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(2)
—
0.25 TCY+30*
—
0*
—
—
—
—
100*
—
TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
TioR
TioF
Port output rise time(2)
Port output fall time(2)
—
—
10
10
25**
25**
ns
ns
* These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Please refer to Figure 15-1 for load conditions.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 113
PIC16C5X
FIGURE 15-4:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 15-1 for load conditions.
TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
AC Characteristics
–20°C ≤ TA ≤ +85°C for industrial - PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
100*
1
—
—
—
—
ns VDD = 5.0V
µs VDD = 5.0V (PIC16LV54A only)
31
Twdt
Watchdog Timer Time-out
Period (No Prescaler)
9.0*
18*
30*
ms VDD = 5.0V (Comm)
32
34
TDRT
TioZ
Device Reset Timer Period
9.0*
18*
30*
ms VDD = 5.0V (Comm)
I/O Hi-impedance from MCLR
Low
—
—
—
—
100*
1µs
ns
—
(PIC16LV54A only)
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453D-page 114
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 15-5:
TIMER0 CLOCK TIMINGS - PIC16C54A
T0CKI
40
41
42
Note: Please refer to Figure 15-1 for load conditions.
TABLE 15-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
AC Characteristics
–20°C ≤ TA ≤ +85°C for industrial - PIC16LV54A-02I
–40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
Characteristic
Min
Typ† Max Units
Conditions
40
41
42
Tt0H T0CKI High Pulse Width
- No Prescaler
- With Prescaler
Tt0L T0CKI Low Pulse Width
0.5 TCY + 20*
—
—
—
—
ns
ns
10*
- No Prescaler
0.5 TCY + 20*
—
—
—
—
—
—
ns
ns
- With Prescaler
10*
Tt0P T0CKI Period
20 or TCY + 40*
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
N
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 115
PIC16C5X
NOTES:
DS30453D-page 116
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
16.0 DEVICE CHARACTERIZATION - PIC16C54A
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-
teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean
– 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 16-1:
Fosc
TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
Frequency normalized to +25°C
Fosc (25°C)
1.10
REXt ≥ 10 kW
1.08
1.06
1.04
1.02
1.00
CEXT = 100 pF
0.98
VDD = 5.5V
0.96
0.94
VDD = 3.5V
0.92
0.90
0.88
0
20
25
30
40
50
60
70
10
T(°C)
TABLE 16-1: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5 V, 25°C
CEXT
REXT
20 pF
3.3K
5K
5 MHz
3.8 MHz
2.2 MHz
262 kHz
1.6 MHz
1.2 MHz
684 kHz
71 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10K
100K
3.3K
5K
100 pF
300 pF
10K
100K
3.3K
5.0K
10K
100K
660 kHz
484 kHz
267 kHz
29 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5V.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 117
PIC16C5X
FIGURE 16-2:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
6
5
R=3.3K
R=5K
4
3
2
1
R=10K
R=100K
0
6.0
2.5
3.0
3.5
4.0
5.0
4.5
5.5
VDD (Volts)
FIGURE 16-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
R=3.3K
R=5K
6
5
4
3
2
1
R=10K
R=100K
0
5.0
5.5
6.0
2.5
3.5
4.0
3.0
4.5
VDD (Volts)
DS30453D-page 118
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-4:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
700
R=3.3K
R=5K
600
500
400
300
R=10K
200
100
R=100K
0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.5
6.0
5.0
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 119
PIC16C5X
FIGURE 16-5:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.5
2.0
1.5
1.0
0.5
0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 16-6:
TYPICAL IPD VS. VDD, WATCHDOG ENABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25.00
20.00
15.00
10.00
5.00
0.00
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volts)
DS30453D-page 120
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-7:
VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS - VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.0
1.8
1.6
1.4
1.2
C)
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
C)
°
5
2
+
(
p
y
T
C)
°
5
8
+
to
1.0
0.8
C
°
0
4
–
(
in
M
0.6
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 16-8:
VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP
MODES) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
)
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 121
PIC16C5X
FIGURE 16-9:
VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0
3.5
C)
°
5
8
+
o
t
C
°
40
–
(
x
a
m
H
I
V
3.0
2.5
2.0
1.5
C)
°
85
+
o
t
C
°
40
–
(
n
i
m
H
I
V
IL
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note:
These input pins have Schmitt Trigger input buffers.
DS30453D-page 122
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-10:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.1
1
10
Freq (MHz)
FIGURE 16-11:
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 20 PF, –40°C to +85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.1
1
10
Freq (MHz)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 123
PIC16C5X
FIGURE 16-12:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
1
10
0.1
Freq (MHz)
FIGURE 16-13:
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 100 PF, –40°C to +85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
0.1
10
1
Freq (MHz)
DS30453D-page 124
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-14:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
0.1
1
Freq (MHz)
FIGURE 16-15:
MAXIMUM IDD vs. FREQUENCY
(WDT DISABLED, RC MODE @ 300 PF, –40°C to +85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
100
10
0.01
0.1
1
Freq (MHz)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 125
PIC16C5X
FIGURE 16-16:
WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 16-17:
TRANSCONDUCTANCE
(gm) OF HS OSCILLATOR
vs. VDD
(1)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
50
45
40
9000
8000
7000
Max –40°C
35
30
6000
5000
Max +85°C
Typ +25°C
25
4000
Max +70°C
Typ +25°C
20
15
3000
2000
Min +85°C
MIn 0°C
10
5
100
0
MIn –40°C
2.0
3.0
5.0
VDD (Volts)
6.0
7.0
4.0
2.0
3.0
5.0
4.0
VDD (Volts)
6.0
7.0
Note 1: Prescaler set to 1:1.
DS30453D-page 126
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-18:
TRANSCONDUCTANCE
(gm) OF LP OSCILLATOR
vs. VDD
FIGURE 16-19:
TRANSCONDUCTANCE
(gm) OF XT OSCILLATOR
vs. VDD
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2500
2000
1500
1000
45
40
35
Max –40°C
Max –40°C
30
25
Typ +25°C
Min +85°C
Typ +25°C
20
15
10
500
Min +85°C
5
0
0
2.0
3.0
5.0
VDD (Volts)
6.0
7.0
4.0
2.0
3.0
5.0
VDD (Volts)
6.0
7.0
4.0
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 127
PIC16C5X
FIGURE 16-20:
PORTA, B AND C IOH vs.
VOH, VDD = 3V
FIGURE 16-21: PORTA, B AND C IOH vs. VOH,
VDD = 5V
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
–5
0
Min +85°C
–10
Min +85°C
–10
–15
–20
Typ +25°C
Typ +25°C
Max –40°C
–30
Max –40°C
–20
–25
–40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.5
1.0
1.5
2.0
2.5
3.0
VOH (Volts)
VOH (Volts)
DS30453D-page 128
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 16-22:
PORTA, B AND C IOL vs.
VOL, VDD = 3V
FIGURE 16-23:
PORTA, B AND C IOL vs.
VOL, VDD = 5V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
40
35
90
80
70
Max –40°C
Max –40°C
30
25
60
50
Typ +25°C
Typ +25°C
Min +85°C
20
40
Min +85°C
15
10
30
20
5
0
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
VOL (Volts)
TABLE 16-2: INPUT CAPACITANCE FOR
PIC16C54A/C58A
Typical Capacitance (pF)
Pin
18L PDIP
18L SOIC
RA port
RB port
5.0
5.0
4.3
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 129
PIC16C5X
NOTES:
DS30453D-page 130
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
17.0 ELECTRICAL CHARACTERISTICS - PIC16C54C/CR54C/C55A/C56A/CR56A/
C57C/CR57C/C58B/CR58B
Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................–55°C to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS................................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin............................................................................................................20 mA
Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA
Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 131
PIC16C5X
FIGURE 17-1:
PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,
0°C ≤ TA ≤ +70°C (COMMERCIAL TEMPS)
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(Volts)
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 17-2:
PIC16C54C/55A/56A/57C/58B-04, 20 VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA < 0°C, +70°C < TA ≤ +125°C (OUTSIDE OF COMMERCIAL TEMPS)
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30453D-page 132
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 17-3:
6.0
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH,
0°C ≤ TA ≤ +85°C
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 17-4:
PIC16LC54C/55A/56A/57C/58B VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ 0°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
VDD
(Volts)
2.7
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 133
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Supply Voltage
Min Typ† Max Units
Conditions
VDD
D001
2.5
2.7
2.5
—
—
—
5.5
5.5
5.5
V
V
V
–40°C ≤ TA ≤ + 85°C, 16LCR5X
–40°C ≤ TA ≤ 0°C, 16LC5X
0°C ≤ TA ≤ + 85°C 16LC5X
PIC16LC5X
PIC16C5X
RC, XT, LP and HS mode
from 0 - 10 MHz
from 10 - 20 MHz
D001A
D002
D003
D004
3.0
4.5
—
—
5.5
5.5
V
V
VDR
VPOR
SVDD
RAM Data Retention Volt-
age
—
1.5*
VSS
—
—
—
—
V
Device in SLEEP mode
(1)
VDD Start Voltage to ensure
Power-on Reset
—
V
See Section 5.1 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
0.05*
V/ms See Section 5.1 for details on
Power-on Reset
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 134
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Min Typ† Max Units
Conditions
(2,3)
IDD
Supply Current
D010
PIC16LC5X
—
—
0.5
11
2.4
27
mA FOSC = 4.0 MHz, VDD = 5.5V, XT and
µA
RC modes
FOSC = 32 kHz, VDD = 2.5V, LP mode,
Commercial
—
14
35
µA
FOSC = 32 kHz, VDD = 2.5V, LP mode,
Industrial
D010A
PIC16C5X
—
—
—
—
1.8
2.6
4.5
14
2.4
3.6*
16
mA FOSC = 4 MHz, VDD = 5.5V, XT and RC
mA modes
mA FOSC = 10 MHz, VDD = 3.0V, HS mode
32
µA
FOSC = 20 MHz, VDD = 5.5V, HS mode
FOSC = 32 kHz, VDD = 3.0V, LP mode,
Commercial
—
17
40
µA
FOSC = 32 kHz, VDD = 3.0V, LP mode,
Industrial
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 135
PIC16C5X
17.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
PIC16LC5X
PIC16LCR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Standard Operating Conditions (unless otherwise specified)
PIC16C5X
PIC16CR5X
(Commercial, Industrial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
Param
No.
Symbol
Characteristic/Device
Min Typ† Max Units
Conditions
(2)
IPD
Power-down Current
D020
PIC16LC5X
—
—
—
—
0.25
0.25
1
2
3
5
8
µA
µA
µA
µA
VDD = 2.5V, WDT disabled, Commercial
VDD = 2.5V, WDT disabled, Industrial
VDD = 2.5V, WDT enabled, Commercial
VDD = 2.5V, WDT enabled, Industrial
1.25
D020A
PIC16C5X
—
—
—
—
—
—
—
—
0.25
0.25
1.8
2.0
4
4
9.8
12
4.0
5.0
µA
µA
µA
µA
µA
µA
µA
µA
VDD = 3.0V, WDT disabled, Commercial
VDD = 3.0V, WDT disabled, Industrial
VDD = 5.5V, WDT disabled, Commercial
VDD = 5.5V, WDT disabled, Industrial
VDD = 3.0V, WDT enabled, Commercial
VDD = 3.0V, WDT enabled, Industrial
VDD = 5.5V, WDT enabled, Commercial
VDD = 5.5V, WDT enabled, Industrial
7.0*
8.0*
12*
14*
27*
30*
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only, and
are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus loading,
oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current con-
sumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,
from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled
as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.
The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
DS30453D-page 136
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
17.2 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended)
PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended)
PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E
Standard Operating Conditions (unless otherwise specified)
PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E
Operating Temperature –40°C ≤ TA ≤ +125°C for extended
(Extended)
Param
No.
Symbol
Characteristic
Supply Voltage
Min Typ† Max Units
Conditions
D001
VDD
RC, XT, LP, and HS mode
from 0 - 10 MHz
from 10 - 20 MHz
3.0
4.5
—
—
5.5
5.5
V
V
D002
D003
VDR
RAM Data Retention Voltage(1)
—
—
1.5*
Vss
—
—
V
V
Device in SLEEP mode
VPOR VDD start voltage to ensure
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
SVDD VDD rise rate to ensure
0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
Power-on Reset
IDD
IPD
Supply Current(2)
XT and RC(3) modes
HS mode
—
—
1.8
9.0
3.3 mA FOSC = 4.0 MHz, VDD = 5.5V
20
mA FOSC = 20 MHz, VDD = 5.5V
D020
Power-down Current(2)
—
—
—
—
—
—
0.3
10
12
4.8
18
26
17
µA VDD = 3.0V, WDT disabled
µA VDD = 4.5V, WDT disabled
µA VDD = 5.5V, WDT disabled
µA VDD = 3.0V, WDT enabled
µA VDD = 4.5V, WDT enabled
µA VDD = 5.5V, WDT enabled
50*
60*
31*
68*
90*
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C, unless otherwise stated. These parameters are for design guidance only,
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/
disabled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
3: Does not include current through REXT. The current through the resistor can be estimated by the formula:
IR = VDD/2REXT (mA) with REXT in kΩ.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 137
PIC16C5X
17.3 DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial, Extended)
PIC16LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended)
PIC16LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
No.
D030
VIL
Input Low Voltage
I/O Ports
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.8 V
V
V
V
V
V
V
4.5V <VDD ≤ 5.5V
Otherwise
I/O Ports
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC mode only(3)
XT, HS and LP modes
D040
VIH
Input High Voltage
I/O ports
2.0
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V < VDD ≤ 5.5V
Otherwise
I/O ports
0.25 VDD+0.8
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC mode only(3)
XT, HS and LP modes
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current(1,2)
For VDD ≤ 5.5V:
I/O ports
-1.0
-5.0
0.5
+1.0
µA VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
µA VPIN = VSS +0.25V
µA VPIN = VDD
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD,
XT, HS and LP modes
MCLR
MCLR
T0CKI
OSC1
—
+5.0
+3.0
+3.0
—
0.5
0.5
0.5
-3.0
-3.0
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
OSC2/CLKOUT
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC mode only
Output High Voltage(2)
I/O ports
OSC2/CLKOUT
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC mode only
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guid-
ance only and is not tested.
Note 1: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
2: Negative current is defined as coming out of the pin.
3: For the RC mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
DS30453D-page 138
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
17.4 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
mc MCLR
ck CLKOUT
osc oscillator
os OSC1
cy cycle time
drt device reset timer
io I/O port
t0 T0CKI
wdt watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 17-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS -
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B-04, 20
CL = 50 pF
for all pins and OSC2 for RC mode
Pin
0 -15 pF for OSC2 in XT, HS or LP modes when
external clock is used to drive OSC1
CL
VSS
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 139
PIC16C5X
17.5 Timing Diagrams and Specifications
FIGURE 17-6:
EXTERNAL CLOCK TIMING - PIC16C5X, PIC16CR5X
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min Typ† Max Units
Conditions
FOSC
External CLKIN Frequency(1)
DC
DC
DC
DC
DC
0.45
4.0
4.0
5.0
250
250
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0 MHz XT OSC mode
4.0 MHz HS OSC mode (04)
20 MHz HS OSC mode (20)
200 kHz LP OSC mode
4.0 MHz RC OSC mode
4.0 MHz XT OSC mode
4.0 MHz HS OSC mode (04)
Oscillator Frequency(1)
20
MHz HS OSC mode (20)
200 kHz LP OSC mode
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
—
—
—
—
—
ns XT OSC mode
ns HS OSC mode (04)
ns HS OSC mode (20)
µs LP OSC mode
5.0
250
250
250
50
ns RC OSC mode
2,200 ns XT OSC mode
250
250
200
ns HS OSC mode (04)
ns HS OSC mode (20)
µs LP OSC mode
5.0
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 140
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
TABLE 17-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min Typ† Max Units
Conditions
2
Tcy
Instruction Cycle Time(2)
—
50*
20*
2.0*
—
4/FOSC
—
—
—
—
3
TosL, TosH Clock in (OSC1) Low or High
Time
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
—
—
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
25*
25*
50*
—
—
—
—
*
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 141
PIC16C5X
FIGURE 17-7:
CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
18
14
19
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Refer to Figure 17-5 for load conditions.
Note:
TABLE 17-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL OSC1↑ to CLKOUT↓(1)
TosH2ckH OSC1↑ to CLKOUT↑(1)
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
TckR
CLKOUT rise time(1)
CLKOUT fall time(1)
—
TckF
—
TckL2ioV CLKOUT↓ to Port out valid(1)
TioV2ckH Port in valid before CLKOUT↑(1)
—
0.25 TCY+30*
—
TckH2ioI
Port in hold after CLKOUT↑(1)
0*
—
—
—
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(2)
—
100*
—
TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
*
TioR
TioF
Port output rise time(2)
Port output fall time(2)
—
—
10
10
25**
25**
ns
ns
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Refer to Figure 17-5 for load conditions.
DS30453D-page 142
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 17-8:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X,
PIC16CR5X
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: Please refer to Figure 17-5 for load conditions.
TABLE 17-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
1000*
—
—
ns VDD = 5.0V
31
Twdt Watchdog Timer Time-out Period
(No Prescaler)
9.0*
18*
30*
ms VDD = 5.0V (Comm)
32
TDRT Device Reset Timer Period
9.0*
18*
30*
ms VDD = 5.0V (Comm)
34
*
TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000*
ns
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 143
PIC16C5X
FIGURE 17-9:
TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X
T0CKI
40
41
42
Note: Please refer to Figure 17-5 for load conditions.
TABLE 17-4: TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
–40°C ≤ TA ≤ +85°C for industrial
–40°C ≤ TA ≤ +125°C for extended
AC Characteristics
Param
No.
Symbol Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
- No Prescaler
0.5 TCY + 20*
—
—
—
—
ns
ns
- With Prescaler
10*
41
Tt0L T0CKI Low Pulse Width
- No Prescaler
0.5 TCY + 20*
—
—
—
—
—
—
ns
ns
- With Prescaler
10*
42
*
Tt0P T0CKI Period
20 or TCY + 40*
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
N
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid-
ance only and are not tested.
DS30453D-page 144
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
18.0 DEVICE CHARACTERIZATION - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/
CR57C/C58B/CR58B
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-
teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean
– 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 18-1:
FOSC
TYPICAL RC OSCILLATOR FREQUENCY VS. TEMPERATURE
Frequency normalized to +25°C
FOSC (25°C)
1.10
REXT ≥ 10 kW
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
VDD = 5.5V
VDD = 3.5V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 18-1: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5V, 25°C
CEXT
REXT
20 pF
3.3K
5K
5 MHz
3.8 MHz
2.2 MHz
262 kHz
1.63 MHz
1.2 MHz
684 kHz
71 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10K
100K
3.3K
5K
100 pF
300 pF
10K
100K
3.3K
5.0K
10K
100K
660 kHz
484 kHz
267 kHz
29 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5V.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 145
PIC16C5X
FIGURE 18-2:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
6
5
4
R=3.3K
R=5K
3
2
R=10K
1
R=100K
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 18-3:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
1.8
1.6
R=3.3K
1.4
1.0
R=5K
R=10K
0.6
0.2
R=100K
0
2.5
3.0
3.5
5.0
5.5
6.0
4.0
4.5
DD (Volts)
V
DS30453D-page 146
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-4:
TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF, 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
700
600
R=3.3K
500
400
300
200
100
R=5K
R=10K
R=100K
0
2.5
3.0
3.5
5.0
5.5
6.0
4.0
4.5
VDD (Volts)
FIGURE 18-5:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25
20
15
10
5
0
2.5
3.0
3.5
5.0
5.5
6.0
4.0
4.5
DD (Volts)
V
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 147
PIC16C5X
FIGURE 18-6:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25
20
15
10
5.0
0
2.5
3.0
3.5
5.0
5.5
4.0
4.5
6.0
VDD (Volts)
FIGURE 18-7:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
35
30
25
20
15
10
5.0
0
2.5
3.0
3.5
5.0
5.5
4.0
4.5
6.0
VDD (Volts)
DS30453D-page 148
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-8:
VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.0
1.8
1.6
1.4
1.2
C)
°
5
2
+
(
p
y
T
1.0
0.8
0.6
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 18-9:
VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
4.5
4.0
3.5
C)
°
5
8
+
o
t
C
°
40
–
(
x
a
m
H
I
V
3.0
2.5
2.0
1.5
C)
°
85
+
o
t
C
°
40
–
(
n
i
m
H
I
V
IL
IL
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
These input pins have Schmitt Trigger input buffers.
5.0
5.5
6.0
Note:
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 149
PIC16C5X
FIGURE 18-10:
VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT (IN XT, HS
AND LP MODES) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 18-11:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 20 PF, 25°C)
TYPICAL IDD vs FREQ(RC MODE @ 20pF/25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
5.5V
4.5V
3.5V
2.5V
10
0.1
1
10
FREQ(MHz)
DS30453D-page 150
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-12:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 100 PF, 25°C)
TYPICAL IDD vs FREQ(RC MODE @ 100 pF/25C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
10000
1000
100
5.5V
4.5V
3.5V
2.5V
10
0.1
1
10
FREQ(MHz)
FIGURE 18-13:
TYPICAL IDD vs. FREQUENCY (WDT DISABLED, RC MODE @ 300 PF, 25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
TYPICAL IDD vs FREQ (RC MODE @ 300 pF/25C)
10000
1000
100
5.5V
4.5V
3.5V
2.5V
10
0.01
0.1
FREQ(MHz)
1
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 151
PIC16C5X
FIGURE 18-14:
WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 18-15:
PORTA, B AND C IOH vs.
VOH, VDD = 3 V
(1)
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
–5
50
45
40
Min +85°C
35
30
–10
–15
Typ +25°C
Typ +125°C
25
Typ +85°C
Max –40°C
20
15
Typ +25°C
Typ –40°C
–20
–25
10
0
0.5
1.0
VOH (Volts)
2.0
2.5
3.0
1.5
5.0
2.0
4.0
VDD (Volts)
3.0
5.0
6.0
7.0
Note 1: Prescaler set to 1:1.
DS30453D-page 152
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 18-16:
PORTA, B AND C IOH vs.
VOH, VDD = 5 V
FIGURE 18-17:
PORTA, B AND C IOL vs.
VOL, VDD = 3 V
Typical: statistical mean @ 25°C
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
45
40
35
0
Max –40°C
–10
30
25
Typ +125°C
Typ +85°C
–20
Typ +25°C
Min +85°C
20
Typ +25°C
Typ –40°C
15
–30
–40
10
5
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 153
PIC16C5X
FIGURE 18-18:
PORTA, B AND C IOL vs.
VOL, VDD = 5 V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
90
80
70
Max –40°C
60
50
Typ +25°C
Min +85°C
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
TABLE 18-2: INPUT CAPACITANCE
Typical Capacitance (pF)
Pin
18L PDIP
5.0
18L SOIC
4.3
RA port
RB port
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
DS30453D-page 154
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
19.0 ELECTRICAL CHARACTERISTICS - PIC16C54C/C55A/C56A/C57C/C58B
40MHz
Absolute Maximum Ratings(†)
Ambient temperature under bias............................................................................................................–55°C to +125°C
Storage temperature ............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS................................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin............................................................................................................20 mA
Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA
Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 155
PIC16C5X
FIGURE 19-1:
PIC16C54C/C55A/C56A/C57C/C58B-40 VOLTAGE-FREQUENCY GRAPH,
0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0
40
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
3: Operation between 20 to 40 MHz requires the following:
• VDD between 4.5V. and 5.5V
• OSC1 externally driven
• OSC2 not connected
• HS mode
• Commercial temperatures
Devices qualified for 40 MHz operation have -40 designation (ex: PIC16C54C-40/P).
4: For operation between DC and 20 MHz, see Section 17.1.
DS30453D-page 156
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
(1)
19.1
DC Characteristics:PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)
PIC16C54C/C55A/C56A/C57C/C58B-40
Standard Operating Conditions (unless otherwise specified)
(Commercial)
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
D001
D002
D003
VDD
Supply Voltage
RAM Data Retention Voltage(2)
4.5
—
—
5.5
—
V
V
V
HS mode from 20 - 40 MHz
Device in SLEEP mode
VDR
1.5*
Vss
VPOR VDD Start Voltage to ensure
—
—
See Section 5.1 for details on
Power-on Reset
Power-on Reset
D004
D010
D020
SVDD VDD Rise Rate to ensure Power- 0.05*
—
—
V/ms See Section 5.1 for details on
Power-on Reset
on Reset
IDD
IPD
Supply Current(3)
—
—
5.2 12.3 mA FOSC = 40 MHz, VDD = 4.5V, HS mode
6.8
16
mA FOSC = 40 MHz, VDD = 5.5V, HS mode
Power-down Current(3)
—
—
1.8
9.8
7.0
27*
µA VDD = 5.5V, WDT disabled, Commercial
µA VDD = 5.5V, WDT enabled, Commercial
* These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin
externally driven, OSC2 pin not connected, HS oscillator mode and commercial temperatures. For operation
between DC and 20 MHz, See Section 19.1.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus load-
ing, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the current
consumption.
a) The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square
wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/dis-
abled as specified.
b) For standby current measurements, the conditions are the same, except that the device is in SLEEP
mode. The power-down current in SLEEP mode does not depend on the oscillator type.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 157
PIC16C5X
(1)
19.2 DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-40 (Commercial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
Param
No.
Symbol
Characteristic
Min
Typ†
Max
Units
Conditions
D030
VIL
Input Low Voltage
I/O Ports
VSS
VSS
VSS
VSS
—
—
—
—
0.8
V
V
V
V
4.5V <VDD ≤ 5.5V
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1
0.15 VDD
0.15 VDD
0.2 VDD
HS, 20 MHz ≤ FOSC ≤ 40 MHz
4.5V < VDD ≤ 5.5V
D040
VIH
Input High Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1
2.0
—
—
—
—
VDD
VDD
VDD
VDD
V
V
V
V
0.85 VDD
0.85 VDD
0.8 VDD
HS, 20 MHz ≤ FOSC ≤ 40 MHz
D050
D060
VHYS Hysteresis of Schmitt
0.15 VDD*
—
—
V
Trigger inputs
IIL
Input Leakage Current(2,3)
For VDD ≤ 5.5V:
I/O ports
-1.0
0.5
+1.0
µA VSS ≤ VPIN ≤ VDD,
pin at hi-impedance
MCLR
MCLR
T0CKI
OSC1
-5.0
—
-3.0
-3.0
—
+5.0
+3.0
+3.0
—
µA VPIN = VSS +0.25V
µA VPIN = VDD
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD, HS
0.5
0.5
0.5
D080
D090
VOL
VOH
Output Low Voltage
I/O ports
Output High Voltage(3)
I/O ports
—
—
—
0.6
—
V
V
IOL = 8.7 mA, VDD = 4.5V
IOH = -5.4 mA, VDD = 4.5V
VDD - 0.7
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
Note 1: Device operation between 20 MHz to 40 MHz requires the following: VDD between 4.5V to 5.5V, OSC1 pin
externally driven, OSC2 pin not connected and HS oscillator mode and commercial temperatures. For opera-
tion between DC and 20 MHz, See Section 17.3.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
age.
3: Negative current is defined as coming out of the pin.
DS30453D-page 158
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
19.3 Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
2
to
mc MCLR
ck CLKOUT
osc oscillator
os OSC1
cy cycle time
drt device reset timer
io I/O port
t0 T0CKI
wdt watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 19-2:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS -
PIC16C54C/C55A/C56A/C57C/C58B-40
CL = 50 pF for all pins except OSC2
Pin
0 pF for OSC2 in HS mode for
CL
operation between
20 MHz to 40 MHz
VSS
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 159
PIC16C5X
19.4 Timing Diagrams and Specifications
FIGURE 19-3:
EXTERNAL CLOCK TIMING - PIC16C5X-40
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified)
AC Characteristics
Operating Temperature
0°C ≤ TA ≤ +70°C for commercial
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
FOSC
TOSC
Tcy
External CLKIN Frequency(1)
External CLKIN Period(1)
Instruction Cycle Time(2)
20
25
—
—
40
—
—
—
MHz HS OSC mode
ns HS OSC mode
—
1
2
3
—
4/FOSC
—
TosL, TosH Clock in (OSC1) Low or High
Time
6.0*
ns HS oscillator
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
—
6.5*
ns HS oscillator
*
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453D-page 160
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 19-4:
OSC1
CLKOUT AND I/O TIMING - PIC16C5X-40
Q1
Q2
Q3
Q4
10
11
CLKOUT
13
12
16
18
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Refer to Figure 19-2 for load conditions.
.
Note:
TABLE 19-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
AC Characteristics
Param
Symbol
No.
Characteristic
Min
Typ†
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL OSC1↑ to CLKOUT↓(1,2)
TosH2ckH OSC1↑ to CLKOUT↑(1,2)
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
TckR
CLKOUT rise time(1,2)
CLKOUT fall time(1,2)
—
TckF
—
TckL2ioV CLKOUT↓ to Port out valid(1,2)
TioV2ckH Port in valid before CLKOUT↑(1,2)
—
0.25 TCY+30*
—
TckH2ioI
Port in hold after CLKOUT↑(1,2)
0*
—
—
—
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid(2)
—
100
—
TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
*
TioR
TioF
Port output rise time(2)
Port output fall time(2)
—
—
10
10
25**
25**
ns
ns
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2: Refer to Figure 19-2 for load conditions.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 161
PIC16C5X
FIGURE 19-5:
RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16C5X-40
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
(1)
I/O pin
Note 1: Please refer to Figure 19-2 for load conditions.
.
TABLE 19-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X-40
Standard Operating Conditions (unless otherwise specified)
AC Characteristics Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
Operating Voltage VDD range is described in Section 19.1.
Param
No.
Symbol
Characteristic
Min Typ† Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
1000*
—
—
ns VDD = 5.0V
31
Twdt Watchdog Timer Time-out Period
(No Prescaler)
9.0*
18*
30*
ms VDD = 5.0V (Comm)
32
TDRT Device Reset Timer Period
9.0*
18*
30*
ms VDD = 5.0V (Comm)
34
*
TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000*
ns
These parameters are characterized but not tested.
†
Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453D-page 162
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 19-6:
TIMER0 CLOCK TIMINGS - PIC16C5X-40
T0CKI
40
41
42
Note:
Refer to Figure 19-2 for load conditions.
TABLE 19-4: TIMER0 CLOCK REQUIREMENTS PIC16C5X-40
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C for commercial
AC Characteristics
Param
No.
Symbol Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
- No Prescaler
0.5 TCY + 20*
—
—
ns
ns
- With Prescaler
Tt0L T0CKI Low Pulse Width
10*
—
—
41
- No Prescaler
0.5 TCY + 20*
—
—
—
—
—
—
ns
ns
- With Prescaler
10*
42
*
Tt0P T0CKI Period
20 or TCY + 40*
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
N
These parameters are characterized but not tested.
† Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 163
PIC16C5X
NOTES:
DS30453D-page 164
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
20.0 DEVICE CHARACTERIZATION - PIC16C54C/C55A/C56A/C57C/C58B 40MHz
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested or guaran-
teed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified
power supply range) and therefore outside the warranted range.
“Typical” represents the mean of the distribution at 25°C. “Maximum” or “minimum” represents (mean + 3σ) or (mean
– 3σ) respectively, where σ is a standard deviation, over the whole temperature range.
FIGURE 20-1:
TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25
20
15
10
5.0
0
2.5
3.0
3.5
5.0
5.5
4.0
4.5
6.0
VDD (Volts)
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 165
PIC16C5X
FIGURE 20-2:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
25
20
15
10
5.0
0
2.5
3.0
3.5
5.0
5.5
6.0
4.0
4.5
VDD (Volts)
FIGURE 20-3:
TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
35
30
25
20
15
10
5.0
0
6.0
2.5
3.5
5.0
5.5
3.0
4.0
4.5
VDD (Volts)
DS30453D-page 166
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 20-4:
VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
2.0
1.8
1.6
1.4
1.2
C)
°
5
2
+
(
p
y
T
1.0
0.8
0.6
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
FIGURE 20-5:
VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT
(HS MODE) vs. VDD
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 167
PIC16C5X
FIGURE 20-6:
TYPICAL IDD vs. VDD (40 MHZ, WDT DISABLED, HS MODE, 70°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
12
11
10
9.0
8.0
7.0
6.0
5.0
4.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30453D-page 168
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
FIGURE 20-7:
WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 20-8:
IOH vs. VOH, VDD = 5 V
(1)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
0
50
45
40
–10
Typ +125°C
Typ +85°C
35
30
–20
Typ +25°C
Typ –40°C
Typ +125°C
25
Typ +85°C
–30
–40
20
15
Typ +25°C
Typ –40°C
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
10
VOH (Volts)
5.0
2.0
3.0
4.0
5.0
6.0
7.0
VDD (Volts)
Note 1: Prescaler set to 1:1.
TABLE 20-1: INPUT CAPACITANCE
Typical Capacitance (pF)
Pin
18L PDIP
5.0
18L SOIC
4.3
RA port
RB port
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 169
PIC16C5X
FIGURE 20-9:
IOL vs. VOL, VDD = 5 V
Typical: statistical mean @ 25°C
Maximum: mean + 3s (-40°C to 125°C)
Minimum: mean – 3s (-40°C to 125°C)
90
80
70
Max –40°C
60
50
Typ +25°C
Min +85°C
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOL (Volts)
DS30453D-page 170
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
21.0 PACKAGING INFORMATION
21.1 Package Marketing Information
18-Lead PDIP
Example
PIC16C56A
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
-04I/P456
YYWWNNN
0023CBA
Example
Example
28-Lead Skinny PDIP (.300")
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16C55A
-04I/SP456
YYWWNNN
0023CBA
28-Lead PDIP (.600")
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
PIC16C55A
-04/P126
0042CDA
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C54C
-04/S0218
YYWWNNN
0018CDK
28-Lead SOIC
Example
PIC16C57C
-04/SO
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
0015CBK
Example
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C54C
-04/SS218
0020CBP
YYWWNNN
28-Lead SSOP
Example
PIC16C57C
-04/SS123
XXXXXXXXXXXX
XXXXXXXXXXXX
0025CBK
YYWWNNN
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 171
PIC16C5X
Package Marking Information (Cont’d)
18-Lead CERDIP Windowed
Example
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16C54C
/JW
0001CBA
28-Lead CERDIP Windowed
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C57C
/JW
0038CBA
YYWWNNN
Legend: XX...X Customer specific information*
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
DS30453D-page 172
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 173
PIC16C5X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS30453D-page 174
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
B1
β
A1
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.100
.175
.150
2.54
4.45
3.81
Top to Seating Plane
A
.160
.190
4.06
4.83
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.505
1.395
.120
.008
.030
.014
.620
5
.160
3.56
0.38
15.11
12.83
35.43
3.05
0.20
0.76
0.36
15.75
5
4.06
.600
.545
1.430
.130
.012
.050
.018
.650
10
.625
.560
1.465
.135
.015
.070
.022
.680
15
15.24
13.84
36.32
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
37.21
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-079
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 175
PIC16C5X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
DS30453D-page 176
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 177
PIC16C5X
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS30453D-page 178
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
NOM MAX
Dimension Limits
MIN
MAX
MIN
n
p
Number of Pins
Pitch
28
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
Overall Height
A
.068
.078
1.73
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.63
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 179
PIC16C5X
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
D
W2
2
1
n
W1
E
A2
A
c
L
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
22.86
3.49
0.25
1.40
0.47
9.78
3.56
5.08
4.95
A2
A1
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
0.38
7.62
7.24
22.35
3.18
0.20
1.27
0.41
8.76
3.30
4.83
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
§
eB
W1
W2
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-036
Drawing No. C04-010
DS30453D-page 180
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
E1
W
D
2
n
1
E
A2
A
L
c
B1
eB
A1
p
B
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.100
.210
.160
.038
.600
.520
1.460
.138
.010
.058
.020
.660
.280
2.54
5.33
Top to Seating Plane
Ceramic Package Height
Standoff
A
.195
.225
.165
.060
.625
.526
1.490
.150
.012
.065
.023
.710
.290
4.95
5.72
A2
A1
.155
.015
.595
.514
1.430
.125
.008
.050
.016
.610
.270
3.94
0.38
4.06
4.19
1.52
0.95
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.11
13.06
36.32
3.18
15.24
13.21
37.08
3.49
15.88
13.36
37.85
3.81
Tip to Seating Plane
Lead Thickness
c
0.20
0.25
0.30
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B1
B
1.27
1.46
1.65
0.41
0.51
0.58
§
eB
W
15.49
6.86
16.76
7.11
18.03
7.37
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-013
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 181
PIC16C5X
NOTES:
DS30453D-page 182
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
APPENDIX A: COMPATIBILITY
To convert code written for PIC16CXX to PIC16C5X,
the user should take the following steps:
1. Check any CALL, GOTO or instructions that
modify the PC to determine if any program
memory page select operations (PA2, PA1, PA0
bits) need to be made.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any special function register page
switching. Redefine data variables to reallocate
them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change RESET vector to proper value for
processor used.
6. Remove any use of the ADDLW, RETURN and
SUBLWinstructions.
7. Rewrite any code segments that use interrupts.
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 183
PIC16C5X
NOTES:
DS30453D-page 184
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
PIC16CR54A
INDEX
A
Commercial .................................................. 80, 83
Extended ...................................................... 82, 84
Industrial....................................................... 80, 83
Absolute Maximum Ratings
PIC16LV54A
PIC16C54/55/56/57 .................................................... 67
PIC16C54A............................................................... 103
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B ............................................................ 131
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B-40 ....................................................... 155
PIC16CR54A .............................................................. 79
ADDWF............................................................................... 51
ALU ....................................................................................... 9
ANDLW ............................................................................... 51
ANDWF............................................................................... 51
Applications........................................................................... 5
Architectural Overview .......................................................... 9
Assembler
Commercial .............................................. 108, 109
Industrial................................................... 108, 109
DECF.................................................................................. 54
DECFSZ ............................................................................. 54
Development Support......................................................... 61
Device Characterization
PIC16C54/55/56/57/CR54A ....................................... 91
PIC16C54A............................................................... 117
PIC16C54C/C55A/C56A/C57C/C58B-40................. 165
Device Reset Timer (DRT) ................................................. 23
Device Varieties.................................................................... 7
Digit Carry (DC) bit ......................................................... 9, 29
DRT .................................................................................... 23
MPASM Assembler ..................................................... 61
E
B
Electrical Specifications
PIC16C54/55/56/57.................................................... 67
PIC16C54A............................................................... 103
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B............................................................ 131
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B-40....................................................... 155
PIC16CR54A.............................................................. 79
Errata.................................................................................... 3
External Power-On Reset Circuit........................................ 21
Block Diagram
On-Chip Reset Circuit................................................. 20
PIC16C5X Series........................................................ 10
Timer0......................................................................... 37
TMR0/WDT Prescaler................................................. 41
Watchdog Timer.......................................................... 46
Brown-Out Protection Circuit .............................................. 23
BSF..................................................................................... 52
BTFSC ................................................................................ 52
BTFSS ................................................................................ 52
F
C
Family of Devices
PIC16C5X..................................................................... 6
FSR Register ...................................................................... 33
Value on reset............................................................. 20
CALL ............................................................................. 31, 53
Carry (C) bit .................................................................... 9, 29
Clocking Scheme ................................................................ 13
CLRF................................................................................... 53
CLRW ................................................................................. 53
CLRWDT............................................................................. 53
CMOS Technology................................................................ 1
Code Protection ............................................................ 43, 47
COMF ................................................................................. 54
Compatibility ..................................................................... 183
Configuration Bits................................................................ 44
G
General Purpose Registers
Value on reset............................................................. 20
GOTO ........................................................................... 31, 55
H
High-Performance RISC CPU .............................................. 1
I
D
I/O Interfacing ..................................................................... 35
I/O Ports ............................................................................. 35
I/O Programming Considerations ....................................... 36
ICEPIC In-Circuit Emulator................................................. 62
ID Locations.................................................................. 43, 47
INCF ................................................................................... 55
INCFSZ............................................................................... 55
INDF Register..................................................................... 33
Value on reset............................................................. 20
Indirect Data Addressing .................................................... 33
Instruction Cycle ................................................................. 13
Instruction Flow/Pipelining.................................................. 13
Instruction Set Summary .................................................... 49
IORLW................................................................................ 56
IORWF................................................................................ 56
Data Memory Organization ................................................. 26
DC Characteristics
PIC16C54/55/56/57
Commercial................................................... 68, 71
Extended....................................................... 70, 72
Industrial ....................................................... 69, 71
PIC16C54A
Commercial............................................... 104, 109
Extended................................................... 106, 109
Industrial ................................................... 104, 109
PIC16C54C/C55A/C56A/C57C/C58B-40
Commercial............................................... 157, 158
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B
Commercial............................................... 134, 138
Extended................................................... 137, 138
Industrial ................................................... 134, 138
K
KeeLoq Evaluation and Programming Tools ...................... 64
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 185
PIC16C5X
Program Memory Organization........................................... 25
Program Verification/Code Protection ................................ 47
L
Loading of PC .....................................................................31
Q
M
Q cycles.............................................................................. 13
Quick-Turnaround-Production (QTP) Devices...................... 7
MCLR Reset
Register values on ......................................................20
Memory Map
R
PIC16C54/CR54/C55..................................................25
PIC16C56/CR56 .........................................................25
PIC16C57/CR57/C58/CR58 .......................................25
Memory Organization..........................................................25
MOVF..................................................................................56
MOVLW...............................................................................56
MOVWF ..............................................................................57
MPLAB C17 and MPLAB C18 C Compilers........................61
MPLAB ICD In-Circuit Debugger.........................................63
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE..................................................................62
MPLAB Integrated Development Environment Software ....61
MPLINK Object Linker/MPLIB Object Librarian ..................62
RC Oscillator....................................................................... 17
Read Only Memory (ROM) Devices ..................................... 7
Read-Modify-Write.............................................................. 36
Register File Map
PIC16C54, PIC16CR54, PIC16C55, PIC16C56,
PIC16CR56 ................................................................ 26
PIC16C57/CR57......................................................... 27
PIC16C58/CR58......................................................... 27
Registers
Special Function ......................................................... 28
Value on reset............................................................. 20
Reset .................................................................................. 19
Reset on Brown-Out ........................................................... 23
RETLW ............................................................................... 57
RLF..................................................................................... 58
RRF .................................................................................... 58
N
NOP ....................................................................................57
O
S
One-Time-Programmable (OTP) Devices.............................7
OPTION ..............................................................................57
OPTION Register................................................................30
Value on reset .............................................................20
Oscillator Configurations.....................................................15
Oscillator Types
Serialized Quick-Turnaround-Production (SQTP) Devices... 7
SLEEP .................................................................... 43, 47, 58
Software Simulator (MPLAB SIM) ...................................... 62
Special Features of the CPU .............................................. 43
Special Function Registers................................................. 28
Stack................................................................................... 32
STATUS Register ........................................................... 9, 29
Value on reset............................................................. 20
SUBWF............................................................................... 59
SWAPF............................................................................... 59
HS...............................................................................15
LP................................................................................15
RC...............................................................................15
XT ...............................................................................15
P
T
PA0 bit.................................................................................29
PA1 bit.................................................................................29
Paging.................................................................................31
PC .......................................................................................31
Value on reset .............................................................20
PD bit ............................................................................ 19, 29
Peripheral Features...............................................................1
PICDEM 1 Low Cost PICmicro Demonstration Board ........63
PICDEM 17 Demonstration Board ......................................64
PICDEM 2 Low Cost PIC16CXX Demonstration Board......63
PICDEM 3 Low Cost PIC16CXXX Demonstration Board ...64
PICSTART Plus Entry Level Development Programmer ....63
Pin Configurations.................................................................2
Pinout Description - PIC16C54, PIC16CR54, PIC16C56,
PIC16CR56, PIC16C58, PIC16CR58 .................................11
Pinout Description - PIC16C55, PIC16C57, PIC16CR57 ...12
PORTA................................................................................35
Value on reset .............................................................20
PORTB................................................................................35
Value on reset .............................................................20
PORTC................................................................................35
Value on reset .............................................................20
Power-Down Mode..............................................................47
Power-On Reset (POR) ......................................................21
Register values on ......................................................20
Prescaler.............................................................................40
PRO MATE II Universal Device Programmer .....................63
Program Counter.................................................................31
Timer0
Switching Prescaler Assignment ................................ 40
Timer0 (TMR0) Module............................................... 37
TMR0 register - Value on reset................................... 20
TMR0 with External Clock .......................................... 39
Timing Diagrams and Specifications
PIC16C54/55/56/57 .................................................... 74
PIC16C54A............................................................... 111
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B ............................................................ 140
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B-40....................................................... 160
PIC16CR54A .............................................................. 86
Timing Parameter Symbology and Load Conditions
PIC16C54/55/56/57 .................................................... 73
PIC16C54A............................................................... 110
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B ............................................................ 139
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/
C58B/CR58B-40....................................................... 159
PIC16CR54A .............................................................. 85
TO bit............................................................................ 19, 29
TRIS.................................................................................... 59
TRIS Registers ................................................................... 35
Value on reset............................................................. 20
DS30453D-page 186
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
U
UV Erasable Devices ............................................................ 7
W
W Register
Value on reset............................................................. 20
Wake-up from SLEEP................................................... 19, 47
Watchdog Timer (WDT) ................................................ 43, 46
Period.......................................................................... 46
Programming Considerations ..................................... 46
Register values on reset ............................................. 20
WWW, On-Line Support ....................................................... 3
X
XORLW............................................................................... 60
XORWF............................................................................... 60
Z
Zero (Z) bit ...................................................................... 9, 29
2002 Microchip Technology Inc.
Preliminary
DS30453D-page 187
PIC16C5X
NOTES:
DS30453D-page 188
Preliminary
2002 Microchip Technology Inc.
PIC16C5X
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© 2002 Microchip Technology Inc.
Preliminary
DS30453D-page189
PIC16C5X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
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Literature Number:
DS30453D
Device:
PIC16C5X
Questions:
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4. What additions to the data sheet do you think would enhance the structure and subject?
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DS30453D-page190
Preliminary
© 2002 Microchip Technology Inc.
PIC16C5X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
-
PART NO.
Device
XX
X
/XX
XXX
Examples:
Frequency
Range/OSC
Type
Temperature Package Pattern
Range
a)
PIC16C55A - 04/P 301 = Commercial Temp.,
PDIP package, 4 MHz, standard VDD limits,
QTP pattern #301
b)
c)
PIC16LC54C - 04I/SO Industrial Temp., SOIC
package, 200 kHz, extended VDD limits
PIC16C57 - RC/SP = RC Oscillator, commer-
cial temp, skinny PDIP package, 4 MHz, stan-
dard VDD limits
Device
PIC16C54
PIC16C54T(2)
PIC16C54A
PIC16CR54A
PIC16C54C
PIC16CR54C
PIC16C55
PIC16C55A
PIC16C56
PIC16C56A
PIC16CR56A
PIC16C57
PIC16C54AT(2)
PIC16CR54AT(2)
PIC16C54CT(2)
PIC16CR54CT(2)
PIC16C55T(2)
d)
PIC16C58BT -40/SS 123 = commercial
temp, SSOP package in tape and reel, 4
MHz, extended VDD limits, ROM pattern
#123
PIC16C55AT(2)
PIC16C56T(2)
PIC16C56AT(2)
PIC16CR56AT(2)
PIC16C57T(2)
PIC16C57C
PIC16CR57C
PIC16C58B
PIC16CR58B
PIC16C57CT(2)
PIC16CR57CT(2)
PIC16C58BT(2)
PIC16CR58BT(2)
Note 1: C = normal voltage range
LC = extended
2: T = in tape and reel - SOIC and SSOP
packages only
Frequency Range/
Oscillator Type
RC Resistor Capacitor
LP Low Power Crystal
3: JW Devices are UV erasable and can be
programmed to any device configura-
tion. JW Devices meet the electrical
requirements of each oscillator type,
including LC devices.
XT Standard Crystal/Resonator
HS High Speed Crystal
02 200 KHz (LP) or 2 MHz (XT and RC)
04 200 KHz (LP) or 4 MHz (XT and RC)
10 10 MHz (HS only)
4: b = Blank
20 20 MHz (HS only)
40 40 MHz (HS only)
b(4) No oscillator type for JW packages(3)
*RC/LP/XT/HS are for 16C54/55/56/57 devices only
-02 is available for 16LV54A only
-04/10/20 options are available for all other devices
-40 is available for 16C54C/55A/56A/57C/58B devices only
Temperature Range
Package
b(4)
I
E
=
=
=
0°C to
-40°C to
-40°C to +125°C
+70°C
+85°C
S
JW
=
=
Die in Waffle Pack
28-pin 600 mil/18-pin 300 mil windowed CER-
DIP(3)
P
=
=
=
=
28-pin 600 mil/18-pin 300 mil PDIP
300 mil SOIC
209 mil SSOP
SO
SS
SP
28-pin 300 mil Skinny PDIP
*See Section 21 for additional package information.
Pattern
QTP, SQTP, ROM code (factory specified) or Special
Requirements. Blank for OTP and Windowed devices.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
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Preliminary
DS30453D-page191
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India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
03/01/02
DS30453D-page 192
2002 Microchip Technology Inc.
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