PIC16C61T-20E/SO [MICROCHIP]
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18, 0.300 INCH, PLASTIC, SO-18;
| 型号： | PIC16C61T-20E/SO |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18, 0.300 INCH, PLASTIC, SO-18 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总24页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C6XX/7XX/9XX
Programming Specifications for PIC16C6XX/7XX/9XX OTP MCUs
This document includes the programming
specifications for the following devices:
Pin Diagrams
PDIP, Windowed CERDIP
• PIC16C61
• PIC16C62
• PIC16C62A • PIC16C73A
• PIC16C62B • PIC16C73B
• PIC16C63
• PIC16C63A • PIC16C74A
• PIC16C64 • PIC16C74B
• PIC16C64A • PIC16C76
• PIC16C65 • PIC16C77
• PIC16C65A • PIC16C620
• PIC16C72A
• PIC16C73
• PIC16CE623
• PIC16CE624
• PIC16CE625
• PIC16C710
• PIC16C711
• PIC16C712
• PIC16C716
• PIC16C745
• PIC16C765
• PIC16C773
MCLR/VPP
RA0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
RA1
RA2
RA3
RA4/T0CKI
RA5
• PIC16C74
RE0
RE1
RE2
9
10
11
12
13
14
15
16
17
18
19
20
VSS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
RC1
RC2
RC3
• PIC16C65B • PIC16C620A • PIC16C774
RD0
RD1
• PIC16C66
• PIC16C67
• PIC16C71
• PIC16C72
• PIC16C621
• PIC16C621A • PIC16C924
• PIC16C622
• PIC16C923
PDIP, SOIC, Windowed CERDIP
(300 mil)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
MCLR/VPP
RA0
• 1
2
• PIC16C622A
3
RA1
RA2
4
1.0
PROGRAMMING THE
PIC16C6XX/7XX/9XX
RA3
5
6
RA4/T0CKI
RA5
7
VSS
8
The PIC16C6XX/7XX/9XX can be programmed using a
serial method. In serial mode the PIC16C6XX/7XX/
9XX can be programmed while in the users system.
This allows for increased design flexibility. This pro-
gramming specification applies to PIC16C6XX/7XX/
9XX devices in all packages.
9
OSC1/CLKIN
OSC2/CLKOUT
RC0
VSS
10
11
12
13
14
RC7
RC6
RC5
RC4
RC1
RC2
RC3
1.1
Hardware Requirements
The PIC16C6XX/7XX/9XX requires two programmable
power supplies, one for VDD (2.0V to 6.5V recom-
mended) and one for VPP (12V to 14V). Both supplies
should have a minimum resolution of 0.25V.
1.2
Programming Mode
The programming mode for the PIC16C6XX/7XX/9XX
allows programming of user program memory, special
locations used for ID, and the configuration word for the
PIC16C6XX/7XX/9XX.
2000 Microchip Technology Inc.
DS30228J-page 1
PIC16C6XX/7XX/9XX
Pin Diagrams (Con’t)
300 mil. SDIP, SOIC, Windowed CERDIP, SSOP
PDIP, SOIC, Windowed CERDIP
18
17
16
15
14
13
12
11
10
RA1
• 1
2
RA2
RA3
MCLR/VPP
RA0/AN0
• 1
2
28
27
26
25
24
RB7
RA0
RB6
OSC1/CLKIN
OSC2/CLKOUT
VDD
3
RA4/T0CKI
MCLR/VPP
VSS
RA1/AN1
3
RB5
4
RA2/AN2/VREF-/VRL
RA3/AN3/VREF+/VRH
4
RB4
5
5
RB3/AN9/LVDIN
RB7
RA4/T0CKI
6
7
8
23
22
21
RB2/AN8
RB1/SS
RB0/INT
6
RB0/INT
RB1
AVDD
AVSS
RB6
7
RB5
8
RB2
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
20
19
18
17
16
15
VDD
RB4
9
RB3
10
11
12
13
14
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
18 pin PDIP, SOIC, Windowed CERDIP
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RA2/AN2
RA3/AN3/VREF
• 1
2
18
17
16
15
14
RA4/T0CKI
MCLR/VPP
3
4
VSS
RB0/INT
RB1/T1OSO/T1CKI
5
RB7
RB6
6
7
8
9
13
12
11
RB5
RB4
RB2/T1OSI
RB3/CCP1
10
20 pin SSOP
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RA2/AN2
RA3/AN3/VREF
• 1
2
20
19
18
17
16
RA4/T0CKI
MCLR/VPP
3
4
VSS
VSS
5
VDD
6
15
RB7
RB6
RB0/INT
RB1/T1OSO/T1CKI
7
14
13
8
12
11
RB5
RB4
9
RB2/T1OSI
RB3/CCP1
10
PLCC
10
11
RA4/T0CKI
RA5/AN4/SS
RB1
RB0/INT
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
C1
60
RD5/SEG29/COM3
RG6/SEG26
RG5/SEG25
RG4/SEG24
RG3/SEG23
RG2/SEG22
RG1/SEG21
RG0/SEG20
RG7/SEG28
RF7/SEG19
RF6/SEG18
RF5/SEG17
RF4/SEG16
RF3/SEG15
RF2/SEG14
RF1/SEG13
RF0/SEG12
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PIC16C923
PIC16C924
C2
VLCD2
VLCD3
AVDD
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
DS30228J-page 2
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
A user may store identification information (ID) in four
ID locations. The ID locations are mapped in [0x2000 :
0x2003]. It is recommended that the user use only the
four least significant bits of each ID location. In some
devices, the ID locations read-out in a scrambled fash-
ion after code protection is enabled. For these devices,
it is recommended that ID location is written as “11
1111 1bbb bbbb” where 'bbbb' is ID information.
2.0
PROGRAM MODE ENTRY
2.1
User Program Memory Map
The user memory space extends from 0x0000 to
0x1FFF (8K). Table 2-1 shows actual implementation
of program memory in the PIC16C6XX/7XX/9XX fam-
ily.
Note: All other locations are reserved and should
TABLE 2-1:
IMPLEMENTATION OF
PROGRAM MEMORY IN THE
PIC16C6XX/7XX/9XX
not be programmed.
In other devices, the ID locations read out normally,
even after code protection. To understand how the
devices behave, refer to Table 4-1.
Program Memory
Size
Device
To understand the scrambling mechanism after code
protection, refer to Section 3.1.
PIC16C61
0x000 – 0x3FF (1K)
0x000 – 0x1FF (0.5K)
0x000 – 0x3FF (1K)
0x000 – 0x7FF (2K)
PIC16C620/620A
PIC16C621/621A
PIC16C622/622A
PIC16C62/62A/62B
PIC16C63/63A
PIC16C64/64A
PIC16C65/65A/65B
PIC16CE623
PIC16CE624
PIC16CE625
PIC16C71
0x000 – 0x7FF (2K)
0x000 – 0xFFF (4K)
0x000 – 0x7FF (2K)
0x000 – 0xFFF (4K)
0x000 – 0x1FF (0.5K)
0x000 – 0x3FF (1K)
0x000 – 0x7FF (2K)
0x000 – 0x3FF (1K)
0x000 – 0x1FF (0.5K)
0x000 – 0x3FF (1K)
0x000 – 0x3FF (1K)
0x000 – 0x7FF (2K)
0x000 – 0x7FF (2K)
0x000 – 0xFFF (4K)
0x000 – 0xFFF (4K)
0x000 – 0x1FFF (8K)
0x000 – 0x1FFF (8K)
0x000 – 0x1FFF (8K)
0x000 – 0x1FFF (8K)
0x000 – 0x1FFF (8K)
0x000 – 0x1FFF (8K)
0x000 – 0xFFF (4K)
0x000 – 0xFFF (4K)
0x000 – 0xFFF (4K)
PIC16C710
PIC16C711
PIC16C712
PIC16C716
PIC16C72/72A
PIC16C73/73A/73B
PIC16C74/74A/74B
PIC16C66
PIC16C67
PIC16C76
PIC16C77
PIC16C745
PIC16C765
PIC16C773
PIC16C774
PIC16C923/924
When the PC reaches the last location of the imple-
mented program memory, it will wrap around and
address a location within the physically implemented
memory (see Figure 2-1).
Once in configuration memory, the highest bit of the PC
stays a ’1’, thus always pointing to the configuration
memory. The only way to point to user program mem-
ory is to reset the part and reenter program/verify
mode, as described in Section 2.2.
2000 Microchip Technology Inc.
DS30228J-page 3
PIC16C6XX/7XX/9XX
FIGURE 2-1: PROGRAM MEMORY MAPPING
0.5K
1K
2K
4K
8K
words
words
words
words
words
0h
ID Location
ID Location
ID Location
ID Location
Reserved
2000h
2001h
2002h
2003h
2004h
2005h
2006h
2007h
Implemented
Reserved
1FFh
3FFh
400h
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
Implemented
7FFh
800h
BFFh
C00h
Reserved
FFFh
1000h
Reserved
Reserved
Reserved
Reserved
Configuration Word
1FFFh
2008h
2100h
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
3FFFh
DS30228J-page 4
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
have a minimum delay of 1 µs between the command
and the data. After this delay the clock pin is cycled 16
times with the first cycle being a start bit and the last
cycle being a stop bit. Data is also input and output LSb
first. Therefore, during a read operation the LSb will be
transmitted onto pin RB7 on the rising edge of the sec-
ond cycle, and during a load operation the LSb will be
latched on the falling edge of the second cycle. A min-
imum 1 µs delay is also specified between consecutive
commands.
2.2
Program/Verify Mode
The program/verify mode is entered by holding pins
RB6 and RB7 low while raising MCLR pin from VSS to
the appropriate VIHH (high voltage). Once in this mode
the user program memory and the configuration mem-
ory can be accessed and programmed in serial fash-
ion. The mode of operation is serial, and the memory
that is accessed is the user program memory. RB6 is a
Schmitt Trigger input in this mode.
The sequence that enters the device into the program-
ming/verify mode places all other logic into the reset
state (the MCLR pin was initially at VSS). This means
that all I/O are in the reset state (High impedance
inputs).
All commands are transmitted LSb first. Data words are
also transmitted LSb first. The data is transmitted on
the rising edge and latched on the falling edge of the
clock. To allow for decoding of commands and reversal
of data pin configuration, a time separation of at least
1 µs is required between a command and a data word
(or another command).
Note 1: The MCLR pin should be raised as quickly
as possible from VIL to VIHH. this is to
ensure that the device does not have the
PC incremented while in valid operation
range.
The commands that are available are listed
in Table 2-2.
2.2.1.1
LOAD CONFIGURATION
2: Do not power any pin before VDD is
applied.
After receiving this command, the program counter
(PC) will be set to 0x2000. By then applying 16 cycles
to the clock pin, the chip will load 14-bits a “data word”
as described above, to be programmed into the config-
uration memory. A description of the memory mapping
schemes for normal operation and configuration mode
operation is shown in Figure 2-1. After the configura-
tion memory is entered, the only way to get back to the
user program memory is to exit the program/verify test
mode by taking MCLR low (VIL).
2.2.1
PROGRAM/VERIFY OPERATION
The RB6 pin is used as a clock input pin, and the RB7
pin is used for entering command bits and data input/
output during serial operation. To input a command, the
clock pin (RB6) is cycled six times. Each command bit
is latched on the falling edge of the clock with the least
significant bit (LSb) of the command being input first.
The data on pin RB7 is required to have a minimum
setup and hold time (see AC/DC specs) with respect to
the falling edge of the clock. Commands that have data
associated with them (read and load) are specified to
TABLE 2-2:
COMMAND MAPPING
Command
Mapping (MSb ... LSb)
Data
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
Load Configuration
Load Data
0, data(14), 0
0, data(14), 0
0, data(14), 0
Read Data
Increment Address
Begin programming
End Programming
Note: The clock must be disabled during In-Circuit Serial Programming.
2000 Microchip Technology Inc.
DS30228J-page 5
PIC16C6XX/7XX/9XX
FIGURE 2-2: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX PROGRAM MEMORY
Start
Set VDD = VDDP*
Set VPP = VIHH1
N = 1
No
Report programming
Yes
Program Cycle
N > 25?
failure
Read Data
Command
N = N + 1 N = #
of Program Cycles
No
Increment Address
Command
Data correct?
Yes
Apply 3N Additional
Program Cycles
Program Cycle
Load Data
Command
No
All locations done?
Yes
Begin Programming
Command
Verify all locations
@ VDD min.*
VPP = VIHH2
Wait 100 µs
No
Report verify
Data correct?
Yes
@ VDD min. Error
End Programming
Command
Verify all locations
@ VDD max.*
VPP = VIHH2
Report verify
@ VDD max. Error
No
Data correct?
Yes
Done
* VDDP = VDD range for programming (typically 4.75V - 5.25V).
VDDmin = Minimum VDD for device operation.
VDDmax = Maximum VDD for device operation.
DS30228J-page 6
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
FIGURE 2-3: PROGRAM FLOW CHART - PIC16C6XX/7XX/9XX CONFIGURATION WORD & ID
LOCATIONS
Start
Set VDD = VDDP*
Set VPP = VIHH1
Load Configuration
Command
N = 1
No
Yes
Read Data
Command
Program ID Loc?
Program Cycle
Increment Address
No
Command
N = N + 1 N = #
of Program Cycles
Data Correct?
Yes
No
Address = 2004
Yes
No
N > 25
Yes
Increment Address
Command
Report ID
Configuration Error
Apply 3N
Program Cycles
Increment Address
Command
Program Cycle
100 Cycles
Read Data
Command
Increment Address
Command
No
Data Correct?
Yes
Set V = V min
Read Data Command
Set VPP = VIHH2
No
DD
DD
Report Program
ID/Config. Error
Data Correct?
Yes
No
Yes
Set VDD = VDDmax
Read Data Command
Set VPP = VIHH2
Data Correct?
Done
VDDP = VDD Range for programming (Typically 4.25V – 5.25V)
VDDMIN = minimum VDD for device operation
VDDMAX = maximum VDD for device operation
2000 Microchip Technology Inc.
DS30228J-page 7
PIC16C6XX/7XX/9XX
2.2.1.2
LOAD DATA
2.3
Programming Algorithm Requires
Variable VDD
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. A timing diagram for the load data
command is shown in Figure 4-1.
The PIC16C6XX/7XX/9XX uses an intelligent algo-
rithm. The algorithm calls for program verification at
VDDmin as well as VDDmax. Verification at VDDmin
guarantees good “erase margin”. Verification at
VDDmax guarantees good “program margin”.
2.2.1.3
READ DATA
After receiving this command, the chip will transmit
data bits out of the memory currently accessed starting
with the second rising edge of the clock input. The RB7
pin will go into output mode on the second rising clock
edge, and it will revert back to input mode (hi-imped-
ance) after the 16th rising edge. A timing diagram of
this command is shown in Figure 4-2.
The actual programming must be done with VDD in the
VDDP range (4.75 - 5.25V).
VDDP
= VCC range required during programming.
VDD min. = minimum operating VDD spec for the part.
VDDmax = maximum operating VDD spec for the part.
Programmers must verify the PIC16C6XX/7XX/9XX at
its specified VDDmax and VDDmin levels. Since
Microchip may introduce future versions of the
PIC16C6XX/7XX/9XX with a broader VDD range, it is
best that these levels are user selectable (defaults are
ok).
2.2.1.4
INCREMENT ADDRESS
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 4-3.
Note:
Any programmer not meeting these
requirements may only be classified as
“prototype” or “development” programmer
but not a “production” quality programmer.
2.2.1.5
BEGIN PROGRAMMING
A load command (load configuration or load data)
must be given before every begin programming
command. Programming of the appropriate memory
(test program memory or user program memory) will
begin after this command is received and decoded.
Programming should be performed with a series of
100µs programming pulses. A programming pulse is
defined as the time between the begin programming
command and the end programming command.
2.2.1.6
END PROGRAMMING
After receiving this command, the chip stops program-
ming the memory (configuration program memory or
user program memory) that it was programming at the
time.
DS30228J-page 8
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
3.0
CONFIGURATION WORD
The PIC16C6XX/7XX/9XX family members have sev-
eral configuration bits. These bits can be programmed
(reads ’0’) or left unprogrammed (reads ’1’) to select
various device configurations. Figure 3-1 and
Figure 3-2 provides an overview of configuration bits.
2000 Microchip Technology Inc.
DS30228J-page 9
PIC16C6XX/7XX/9XX
FIGURE 3-1: CONFIGURATION WORD BIT MAP
Bit
6
5
4
3
2
1
0
13
—
—
12
—
—
11
—
—
10
—
—
9
—
—
8
—
—
7
—
—
Number:
PIC16C61/71
—
0
—
CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C62/64/65/73/74
CP1 CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C62A/62B/63A/CR62/
63/
64A/CR64/65A/65B/66/67/
72/72A/73A/73B/74A/74B/76/
77/620/620A/621/621A/622/
622A/
712/716 CP1 CP0 CP1 CP0 CP1 CP0
—
—
BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
PIC16C9XX/745/765
CP1 CP0 CP1 CP0 CP1 CP0
—
CP1 CP0 PWRTE WDTE FOSC1 FOSC0
Reserved, '–' write as '1' for PIC16C6XX/7XX/9XX
CP <1:0>, Code Protect
Device
CP1
CP0
Code Protection
PIC16C622/622A
0
0
1
0
All memory protected
PIC16C62/62A/62B
PIC16C63/63A
0
1
Upper 3/4 memory protected
Upper 1/2 memory protected
PIC16C64/64A/712/716
PIC16C65/65A/65B
PIC16C66/67/72/72A
PIC16C73/73A/73B
PIC16C74/74A/74B/76/77
PIC16C745/765
1
1
Code protection off
PIC16C9XX
PIC16C61/71
PIC16C710/711
PIC16C620
—
—
0
0
1
1
0
1
1
0
1
0
1
0
1
0
0
1
All memory protected
Off
All memory protected
Do not use
Do not use
Code protection off
All memory protected
Upper 1/2 memory protected
Code protection off
PIC16C621
bit 6:
BODEN, Brown Out Enable Bit
1 = Enabled
2 = Disable
bit 4: PWRTE/PWRTE, Power Up Timer Enable Bit
PIC16C61/62/64/65/71/73/74:
1 = Power up timer enabled
0 = Power up timer disabled
PIC16C620/620A/621/621A/622/622A/62A/63/63A/65A/65B/66/67/72/72A/73A/73B/74A/74B/76/77/710/
711/923/924/745/765:
0 = Power up timer enabled
1 = Power up timer disabled
bit 3-2: WDTE, WDT Enable Bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC<1:0>, Oscillator Selection Bit
11: RC oscillator
10: HS oscillator
01: XT oscillator
00: LP oscillator
bit 1-0: FOSC<1:0>, PIC16C745/765
11: E external clock with 4k PLL
10: H HS oscillator with 4k PL enabled
01: EC exteranl clock, clkout on osc2
00: HS
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit
PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
DS30228J-page 10
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
FIGURE 3-2: CONFIGURATION WORD FOR PIC16C773/774 DEVICE
CP1 CP0 BORV1 BORV0 CP1 CP0
bit13 12 11 10
-
BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
bit0
Register: CONFIG
Address 2007h
9
8
7
6
5
4
3
2
1
CP <1:0> Code Protection bits (2)
Device
CP1
CP0
Code Protection
PIC16C773/774
0
0
1
1
0
1
0
1
All memory protected
Upper 3/4 memory protected
Upper 1/2 memory protected1
Code protection off
bit 11-10: BORV <1:0>: Brown-out Reset Voltage bits
11 = VBOR set to 2.5V
10 = VBOR set to 2.7V
01 = VBOR set to 4.2V
00 = VBOR set to 4.5V
bit 7:
bit 6:
Unimplemented, Read as ’1’
(1)
BODEN: Brown-out Reset Enable bit
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP <1:0> pairs have to be given the same value to enable the code protection scheme listed.
2000 Microchip Technology Inc.
DS30228J-page 11
PIC16C6XX/7XX/9XX
FIGURE 3-3: CONFIGURATION WORD, PIC16C710/711
CP0
CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0
CP0 PWRTE WDTE FOSC1 FOSC0
bit0
Register: CONFIG
Address 2007h
bit13
(2)
bit 13-7 CP0: Code protection bits
5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
(1)
bit 6:
bit 3:
bit 2:
BODEN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
(1)
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC <1:0>: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
DS30228J-page 12
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
3.1
Embedding Configuration Word and ID Information in the Hex File.
To allow portability of code, the programmer is required to read the configuration word and ID locations from the hex
file when loading the hex file. If configuration word information was not present in the hex file then a simple warning
message may be issued. Similarly, while saving a hex file, configuration word and ID information must be included.
An option to not include this information may be provided.
Microchip Technology Inc. feels strongly that this feature is beneficial to the end customer.
2000 Microchip Technology Inc.
DS30228J-page 13
PIC16C6XX/7XX/9XX
The following table describes how to calculate the
checksum for each device. Note that the checksum cal-
culation differs depending on the code protect setting.
Since the program memory locations read out differ-
ently depending on the code protect setting, the table
describes how to manipulate the actual program mem-
ory values to simulate the values that would be read
from a protected device. When calculating a checksum
by reading a device, the entire program memory can
simply be read and summed. The configuration word
and ID locations can always be read.
3.2
Checksum
3.2.1
CHECKSUM CALCULATIONS
Checksum is calculated by reading the contents of the
PIC16C6XX/7XX/9XX memory locations and adding
up the opcodes up to the maximum user addressable
location, e.g., 0x1FF for the PIC16C74. Any carry bits
exceeding 16-bits are neglected. Finally, the configura-
tion word (appropriately masked) is added to the check-
sum. Checksum computation for each member of the
PIC16C6XX/7XX/9XX devices is shown in Table 3-1.
Note that some older devices have an additional value
added in the checksum. This is to maintain compatibil-
ity with older device programmer checksums.
The checksum is calculated by summing the following:
• The contents of all program memory locations
• The configuration word, appropriately masked
• Masked ID locations (when applicable)
The least significant 16 bits of this sum is the check-
sum.
TABLE 3-1:
Device
CHECKSUM COMPUTATION
Code
0x25E6 at
Blank
Checksum*
0 and max
Value
Protect
address
PIC16C61
OFF
ON
SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0
SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060)
0x3BFF
0xFC6F
0x07CD
0xFC15
PIC16C620
PIC16C620A
PIC16C621
OFF
ON
SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F
0x3D7F
0x3DCE
0x094D
0x099C
OFF
ON
SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F
0x3D7F
0x3DCE
0x094D
0x099C
OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
PIC16C621A
PIC16C622
OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
PIC16C622A
PIC16CE623
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
ON
SUM[0x000:0x1FF] + CFGW & 0x3F7F
SUM_ID + CFGW & 0x3F7F
0x3D7F
0x3DCE
0x094D
0x099C
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
DS30228J-page 14
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
TABLE 3-1:
CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
0 and max
address
Code
Protect
Blank
Value
Device
Checksum*
PIC16CE624
OFF
1/2
ALL
SUM[0x000:0x3FF] + CFGW & 0x3F7F
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x3B7F
0x4EDE
0x3BCE
0x074D
0x0093
0x079C
PIC16CE625
PIC16C62
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F +
0x3F80
0x37BF
0x37AF
0x379F
0x378F
0x038D
0x1D69
0x1D59
0x3735
ALL
SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
PIC16C62A
PIC16C62B
PIC16C63
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
PIC16C63A
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
PIC16C64
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x3FF] + SUM_XNOR7[0x400:0x7FF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x1FF] + SUM_XNOR7[0x200:0x7FF] + CFGW & 0x003F +
0x3F80
0x37BF
0x37AF
0x379F
0x378F
0x038D
0x1D69
0x1D59
0x3735
ALL
SUM_XNOR7[0x000:0x7FF] + CFGW & 0x003F + 0x3F80
PIC16C64A
PIC16C65
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F +
0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
ALL
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
2000 Microchip Technology Inc.
DS30228J-page 15
PIC16C6XX/7XX/9XX
TABLE 3-1:
CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
0 and max
address
Code
Protect
Blank
Value
Device
Checksum*
PIC16C65A
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
PIC16C65B
PIC16C66
PIC16C67
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
OFF
1/2
3/4
SUM[0x000:0x1FFF] + CFGW & 0x3F7F
SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
ALL
OFF
1/2
3/4
SUM[0x000:0x1FFF] + CFGW & 0x3F7F
SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
ALL
PIC16C710
PIC16C71
PIC16C711
PIC16C712
OFF
ON
SUM[0x000:0x1FF] + CFGW & 0x3FFF
SUM[0x00:0x3F] + CFGW & 0x3FFF + SUM_ID
0x3DFF
0x3E0E
0x09CD
0xEFC3
OFF
ON
SUM[0x000:0x3FF] + CFGW & 0x001F + 0x3FE0
SUM_XNOR7[0x000:0x3FF] + (CFGW & 0x001F | 0x0060)
0x3BFF
0xFC6F
0x07CD
0xFC15
OFF
ON
SUM[0x000:0x03FF] + CFGW & 0x3FFF
SUM[0x00:0x3FF] + CFGW & 0x3FFF + SUM_ID
0x3BFF
0x3C0E
0x07CD
0xEDC3
OFF
1/2
ALL
SUM[0x000:0x07FF] + CFGW & 0x3F7F
SUM[0x000:0x03FF] + CFGW & 3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x37CE
0x034D
0xF58A
0x039C
PIC16C716
PIC16C72
PIC16C72A
PIC16C73
OFF
1/2
3/4
SUM[0x000:0x07FF] + CFGW & 0x3F7F
SUM[0x000:0x03FF] + CFGW & 0x3F7F + SUM_ID
SUM]0x000:0x01FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0x7FF] + CFGW & 0x3F7F
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x1FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x377F
0x5DEE
0x4ADE
0x37CE
0x034D
0x0FA3
0xFC93
0x039C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F +
0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
ALL
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
PIC16C73A
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
DS30228J-page 16
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
TABLE 3-1:
CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
0 and max
address
Code
Protect
Blank
Value
Device
Checksum*
PIC16C73B
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
PIC16C74
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
SUM[0x000:0x7FF] + SUM_XNOR7[0x800:FFF] + CFGW & 0x003F +
0x3F80
SUM[0x000:0x3FF] + SUM_XNOR7[0x400:FFF] + CFGW & 0x003F +
0x3F80
0x2FBF
0x2FAF
0x2F9F
0x2F8F
0xFB8D
0x1569
0x1559
0x2F35
ALL
SUM_XNOR7[0x000:0xFFF] + CFGW & 0x003F + 0x3F80
PIC16C74A
PIC16C74B
PIC16C76
PIC16C77
PIC16C773
PIC16C774
PIC16C923
PIC16C924
PIC16C745
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F7F
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x51EE
0x40DE
0x2FCE
0xFB4D
0x03A3
0xF293
0xFB9C
ALL
OFF
1/2
3/4
SUM[0x000:0x1FFF] + CFGW & 0x3F7F
SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
ALL
OFF
1/2
3/4
SUM[0x000:0x1FFF] + CFGW & 0x3F7F
SUM[0x000:0xFFF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:0x7FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x1F7F
0x39EE
0x2CDE
0x1FCE
0xEB4D
0xEBA3
0xDE93
0xEB9C
ALL
OFF
1/2
3/4
SUM[0x000:0x0FFF] + CFGW & 0x3F7F
SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0x55EE
0x48DE
0x3BCE
0xFB4D
0x07A3
0xFA93
0x079C
ALL
OFF
1/2
3/4
SU:M[0x000:0FFF] + CFGW & 0x3F7F
SUM[0x000:07FF] + CFGW & 0x3F7F + SUM_ID
SUM[0x000:03FF] + CFGW & 0x3F7F + SUM_ID
CFGW & 0x3F7F + SUM_ID
0x2F7F
0X55EE
0X48DE
0x3BCE
0xFB4D
0x07A3
0xFA93
0X079C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F3F
SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID
CFGW & 0x3F3F + SUM_ID
0x2F3F
0x516E
0x405E
0x2F4E
0xFB0D
0x0323
0xF213
0xFB1C
ALL
OFF
1/2
3/4
SUM[0x000:0xFFF] + CFGW & 0x3F3F
SUM[0x000:0x7FF] + CFGW & 0x3F3F + SUM_ID
SUM[0x000:0x3FF] + CFGW & 0x3F3F + SUM_ID
CFGW & 0x3F3F + SUM_ID
0x2F3F
0x516E
0x405E
0x2F4E
0xFB0D
0x0323
0xF213
0xFB1C
ALL
OFF
SUM(0000:1FFF) + CFGW & 0x3F3F
1F3F
396E
2C5E
1F4E
EB0D
EB23
DE13
EB1C
1000:1FFF SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID
800:1FFF SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID
ALL
CFGW * 0x3F3F + SUM_ID
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
2000 Microchip Technology Inc.
DS30228J-page 17
PIC16C6XX/7XX/9XX
TABLE 3-1:
CHECKSUM COMPUTATION (CONTINUED)
0x25E6 at
0 and max
address
Code
Protect
Blank
Value
Device
Checksum*
PIC16c765
OFF
SUM(0000:1FFF) + CFGW & 0x3F3F
1F3F
396E
2C5E
1F4E
EB0D
EB23
DE13
EB1C
1000:1FFF SUM(0000:0FFF) + CFGW & 0x3F3F+SUM_ID
800:1FFF SUM(0000:07FF) + CFGW & 0x3F3F + SUM_ID
ALL
CFGW * 0x3F3F + SUM_ID
Legend: CFGW = Configuration Word
SUM[a:b] = [Sum of locations a through b inclusive]
SUM_XNOR7[a:b] = XNOR of the seven high order bits of memory location with the seven low order bits summed over
locations a through b inclusive. For example, XNOR(0x3C31)=0x78 XNOR 0c31 = 0x0036.
SUM_ID = ID locations masked by 0xF then made into a 16-bit value with ID0 as the most significant nibble. For example,
ID0 = 0x12, ID1 = 0x37, ID2 = 0x4, ID3 = 0x26, then SUM_ID = 0x2746.
*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]
+ = Addition
& = Bitwise AND
| = Bitwise OR
DS30228J-page 18
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
4.0
PROGRAM/VERIFY MODE
TABLE 4-1:
AC/DC CHARACTERISTICS
TIMING REQUIREMENTS FOR PROGRAM/VERIFY TEST MODE
Standard Operating Conditions
Operating Temperature: +10°C ≤ TA ≤ +40°C, unless otherwise stated, (20°C recommended)
Operating Voltage:
4.5V ≤ VDD ≤ 5.5V, unless otherwise stated.
Parameter
Sym.
Characteristic
General
Min.
Typ.
Max.
Units
Conditions
No.
PD1
PD2
VDDP Supply voltage during programming
4.75
5.0
5.25
V
IDDP Supply current (from VDD)
during programming
–
–
20
mA
PD3
PD4
VDDV Supply voltage during verify
VDDmin
–
–
VDDmax
V
V
Note 1
VIHH1 Voltage on MCLR/VPP during
12.75
13.25
Note 2
programming
PD5
PD6
VIHH2 Voltage on MCLR/VPP during verify
VDD + 4.5
–
–
13.25
50
–
IPP
Programming supply current (from
–
mA
VPP)
PD9
PD8
VIH
VIL
(RB6, RB7) input high level
(RB6, RB7) input low level
0.8 VDD
0.2 VDD
–
–
–
–
V
V
Schmitt Trigger input
Schmitt Trigger input
Serial Program Verify
P1
TR
MCLR/VPP rise time (VSS to VHH)
–
–
8.0
µs
for test mode entry
P2
P3
P4
P5
Tf
MCLR Fall time
–
–
–
–
–
8.0
–
µs
ns
ns
µs
Tset1 Data in setup time before clock ↓
Thld1 Data in hold time after clock ↓
100
100
1.0
–
Tdly1 Data input not driven to next clock
input (delay required between com-
mand/data or command/command)
–
P6
P7
P8
Tdly2 Delay between clock ↓ to clock ↑ of
1.0
200
2
–
–
–
–
–
–
µs
ns
µs
next command or data
Tdly3 Clock ↑ to date out valid
(during read data)
Thld0 Hold time after MCLR ↑
Note 1: Program must be verified at the minimum and maximum VDD limits for the part.
2: VIHH must be greater than VDD + 4.5V to stay in programming/verify mode.
2000 Microchip Technology Inc.
DS30228J-page 19
PIC16C6XX/7XX/9XX
FIGURE 4-1: LOAD DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns
2
P6
P8
1
2
3
4
5
3
4
0
1
15
6
5
1µs min.
RB6
(CLOCK)
100ns
0
RB7
(DATA)
0
0
0
1
0
0
P5
P3
P4
P3
1µs min.
P4
100ns
min.
100ns
min.
Program/Verify Test Mode
Reset
FIGURE 4-2: READ DATA COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
100ns
2
P6
P8
1
2
3
4
5
3
4
0
1
15
6
5
1µs min.
RB6
(CLOCK)
100ns
1
P7
RB7
(DATA)
0
0
0
0
P5
P4
1µs min.
P3
100ns
min.
RB7
input
RB7 = output
Program/Verify Test Mode
Reset
FIGURE 4-3: INCREMENT ADDRESS COMMAND (PROGRAM/VERIFY)
VIHH
MCLR/VPP
P6
Next Command
2
1µs min.
2
1
3
6
0
1
1
4
5
0
RB6
(CLOCK)
RB7
(DATA)
0
0
0
1
0
P5
P3
P4
1µs min.
100ns
min
Program/Verify Test Mode
Reset
DS30228J-page 20
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
NOTES:
2000 Microchip Technology Inc.
DS30228J-page 21
PIC16C6XX/7XX/9XX
NOTES:
DS30228J-page 22
2000 Microchip Technology Inc.
PIC16C6XX/7XX/9XX
NOTES:
2000 Microchip Technology Inc.
DS30228J-page 23
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Microchip Technology Inc.
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
Beijing
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Tel: 86-10-85282100 Fax: 86-10-85282104
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
France
India
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 972-818-7423 Fax: 972-818-2924
Japan
Germany
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Italy
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 82-2-554-7200 Fax: 82-2-558-5934
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Los Angeles
Shanghai
Microchip Technology
Unit B701, Far East International Plaza,
No. 317, Xianxia Road
Shanghai, 200051 P.R.C
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
New York
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
01/21/00
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 2/1/00 Microchip Technology Incorporated. Printed in the USA. Tuesday, February 01, 2000
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.
It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights
arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property
rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS30228J-page 24
2000 Microchip Technology Inc.
相关型号：
PIC16C61T-20I/SO
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDSO18, 0.300 INCH, PLASTIC, SO-18
MICROCHIP
©2020 ICPDF网 联系我们和版权申明