PIC16C63AT-20E/SP [MICROCHIP]
8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28;
| 型号： | PIC16C63AT-20E/SP |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28 可编程只读存储器 时钟 光电二极管 外围集成电路 |
| 文件： | 总152页 (文件大小：1047K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M
PIC16C63A/65B/73B/74B
28/40-Pin 8-Bit CMOS Microcontrollers
Pin Diagram
Device
Pins
A/D
PSP
PDIP, Windowed CERDIP
PIC16C63A
PIC16C73B
PIC16C65B
PIC16C74B
28
28
40
40
NO
YES
NO
NO
NO
MCLR/VPP
RA0/AN0
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
YES
YES
2
3
4
5
6
7
8
9
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
YES
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB1
RB0/INT
VDD
Microcontroller Core Features:
• High-performance RISC CPU
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
• Only 35 single word instructions to learn
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
• 4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability (up to 12 internal/external
interrupt sources)
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
• Low-power, high-speed CMOS EPROM
technology
2
SPI and I C
• Fully static design
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• In-Circuit Serial Programming™ (ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Commercial, Industrial and Extended temperature
ranges
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
1998 Microchip Technology Inc.
DS30605A-page 1
PIC16C63A/65B/73B/74B
Pin Diagrams
SDIP, SOIC, SSOP, Windowed CERDIP
SDIP, SOIC, SSOP, Windowed CERDIP
MCLR/VPP
RA0/AN0
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
MCLR/VPP
RA0
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
RA1/AN1
3
RA1
3
RA2/AN2
4
RA2
4
RA3/AN3/VREF
5
RA3
5
RA4/T0CKI
RA5/SS/AN4
VSS
6
7
8
23
22
21
RB2
RA4/T0CKI
RA5/SS
VSS
6
7
8
23
22
21
RB2
RB1
RB1
RB0/INT
RB0/INT
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
20
19
18
17
16
15
VDD
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
20
19
18
17
16
15
VDD
10
11
12
13
14
VSS
10
11
12
13
14
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC3/SCK/SCL
PIC16C73B
PIC16C63A
PDIP, Windowed CERDIP
MQFP
TQFP
MCLR/VPP
RA0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
RB1
RB0/INT
VDD
NC
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
PIC16C65B
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
10
11
RB2
RB3
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
PIC16C65B
PLCC
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
RB3
RB2
RB1
RB0/INT
VDD
7
8
9
39
38
37
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
VDD
VSS
VSS
PIC16C65B
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
DS30605A-page 2
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Pin Diagrams (Cont.’d)
PLCC
MQFP
TQFP
RA4/T0CKI
RA5/SS/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB3
RB2
RB1
RB0/INT
VDD
7
8
9
39
38
37
36
35
34
33
32
31
30
29
NC
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
10
11
12
13
14
15
16
17
VSS
VDD
PIC16C74B
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
PIC16C74B
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/SS/AN4
RA4/T0CKI
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
9
10
11
RB2
RB3
Key Features
PICmicro Mid-Range Reference Manual
(DS33023)
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Operating Frequency
Resets (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
Program Memory (14-bit words)
Data Memory (bytes)
Interrupts
4K
4K
192
11
4K
192
11
4K
192
192
10
12
I/O Ports
Ports A,B,C
Ports A,B,C,D,E Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM modules
Serial Communications
Parallel Communications
8-bit Analog-to-Digital Module
Instruction Set
2
2
2
2
SSP, USART
SSP, USART
SSP, USART
—
SSP, USART
PSP
—
—
PSP
—
5 input channels 8 input channels
35 Instructions 35 Instructions 35 Instructions 35 Instructions
1998 Microchip Technology Inc.
DS30605A-page 3
PIC16C63A/65B/73B/74B
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................. 11
3.0 I/O Ports..................................................................................................................................................................................... 25
4.0 Timer0 Module ........................................................................................................................................................................... 37
5.0 Timer1 Module ........................................................................................................................................................................... 39
6.0 Timer2 Module ........................................................................................................................................................................... 43
7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................. 45
8.0 Synchronous Serial Port (SSP) Module..................................................................................................................................... 51
9.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) .................................................................................... 61
10.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 75
11.0 Special Features of the CPU...................................................................................................................................................... 81
12.0 Instruction Set Summary............................................................................................................................................................ 95
13.0 Development Support ................................................................................................................................................................ 97
14.0 Electrical Characteristics.......................................................................................................................................................... 101
15.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 123
16.0 Packaging Information ............................................................................................................................................................. 125
Appendix A: Revision History ........................................................................................................................................................... 137
Appendix B: Device Differences ....................................................................................................................................................... 137
Appendix C: Conversion Considerations .......................................................................................................................................... 137
Appendix D: Migration from Baseline to Midrange Devices.............................................................................................................. 138
Appendix E: Bit/Register Cross-Reference List................................................................................................................................ 139
Index .................................................................................................................................................................................................. 141
On-Line Support................................................................................................................................................................................. 147
Reader Response .............................................................................................................................................................................. 148
PIC16C63A/65B/73B/74B Product Identification System .................................................................................................................. 149
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our worldwide web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number, found on the bottom outside corner
of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of docu-
ment DS30000.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec-
ommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet.The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s worldwide web site at http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet
(include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation.We have spent a great deal of time
to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any
information that is missing or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet, or
• E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
DS30605A-page 4
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
There are four devices (PIC16C63A, PIC16C65B,
PIC16C73B, PIC16C74B) covered by this data sheet.
These devices come in 28- and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port imple-
mented. The PIC16C6X devices do not have the A/D
module implemented.
1.0
DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro
Mid-Range Reference Manual (DS33023) which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip web site. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2 respectively.
FIGURE 1-1: PIC16C63A/PIC16C73B BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
RA0/AN0(2)
EPROM
RA1/AN1(2)
4K x 14
RA2/AN2(2)
RAM
Program
Memory
(2)
8 Level Stack
(13-bit)
RA3/AN3/VREF
RA4/T0CKI
192 x 8
File
Registers
RA5/SS/AN4(2)
Program
Bus
14
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
MCLR VDD, VSS
Timer2
Timer0
CCP1
Timer1
CCP2
A/D(2)
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C63A.
1998 Microchip Technology Inc.
DS30605A-page 5
PIC16C63A/65B/73B/74B
FIGURE 1-2: PIC16C65B/PIC16C74B BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
RA0/AN0(2)
EPROM
RA1/AN1(2)
RA2/AN2(2)
4K x 14
RAM
(2)
RA3/AN3/VREF
RA4/T0CKI
8 Level Stack
(13-bit)
Program
Memory
192 x 8
File
Registers
RA5/SS/AN4(2)
Program
Bus
14
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
PORTD
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD7/PSP7:RD0/PSP0
PORTE
Parallel Slave Port
MCLR VDD, VSS
RE0/RD/AN5(2)
RE1/WR/AN6(2)
RE2/CS/AN7(2)
Timer0
CCP1
Timer1
CCP2
Timer2
A/D(2)
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C65B.
DS30605A-page 6
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-1:
PIC16C63A/PIC16C73B PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
Oscillator crystal input/external clock source input.
ST/CMOS
—
OSC2/CLKOUT
10
10
O
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
1
1
I/P
ST
Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
(4)
2
3
4
5
6
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA0/AN0
(4)
RA1 can also be analog input1
RA1/AN1
(4)
RA2 can also be analog input2
RA2/AN2
(4)
RA3 can also be analog input3 or analog reference voltage
RA3/AN3/VREF
RA4/T0CKI
RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
(4)
7
7
I/O
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
RA5/SS/AN4
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
RB2
TTL
RB3
TTL
RB4
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
(2)
RB7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
11
12
13
14
15
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output
2
for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5/SDO
16
17
16
17
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not available on the PIC16C63A.
1998 Microchip Technology Inc.
DS30605A-page 7
PIC16C63A/65B/73B/74B
TABLE 1-2:
PIC16C65B/PIC16C74B PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP I/O/P
Pin# Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
ST/CMOS
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0
RA1 can also be analog input1
RA2 can also be analog input2
(5)
RA0/AN0
2
3
4
5
3
4
5
6
19
20
21
22
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
(5)
RA1/AN1
(5)
RA2/AN2
(5)
RA3/AN3/VREF
RA3 can also be analog input3 or analog reference
voltage
RA4/T0CKI
6
7
7
8
23
24
I/O
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
(5)
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
33
34
35
36
37
38
39
40
36
37
38
39
41
42
43
44
8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0 can also be the external interrupt pin.
9
RB2
10
11
14
15
16
17
TTL
RB3
TTL
RB4
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
(2)
RB7
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: The A/D module is not available on the PIC16C65B.
DS30605A-page 8
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 1-2:
PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.’d)
DIP
Pin#
PLCC
Pin#
QFP I/O/P
Pin# Type
Buffer
Type
Pin Name
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
15
16
17
18
23
24
25
26
16
18
19
20
25
26
27
29
32
35
36
37
42
43
44
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3 can also be the synchronous serial clock input/
2
output for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
data I/O (I C mode).
RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
RC7/RX/DT
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
(5)
8
9
9
25
26
27
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
RE0 can also be read control for the parallel slave port,
or analog input5.
RE0/RD/AN5
(5)
10
11
RE1 can also be write control for the parallel slave port,
or analog input6.
RE1/WR/AN6
(5)
10
RE2 can also be select control for the parallel slave
port, or analog input7.
RE2/CS/AN7
VSS
VDD
NC
12,31
11,32
—
13,34
12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins should
be left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: The A/D module is not available on the PIC16C65B.
1998 Microchip Technology Inc.
DS30605A-page 9
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 10
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2
Data Memory Organization
2.0
MEMORY ORGANIZATION
There are two memory blocks in each of these PICmicro
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus so that concurrent
access can occur.
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
Additional information on device memory may be found
RP1(1)
RP0
(STATUS<6:5>)
in the PICmicro
(DS33023).
Mid-Range Reference Manual
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
2.1
Program Memory Organization
The PIC16C63A/65B/73B/74B microcontrollers have a
13-bit program counter capable of addressing an 8K x
14 program memory space. Each device has 4K x 14
words of program memory. Accessing a location above
the physically implemented address will cause a wrap-
around.
Note 1: Maintain this bit clear to ensure upward compati-
bility with future products.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
2.2.1
GENERAL PURPOSE REGISTER FILE
PC<12:0>
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 2.5).
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FFFh
1000h
1FFFh
1998 Microchip Technology Inc.
DS30605A-page 11
PIC16C63A/65B/73B/74B
2.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 2-2: REGISTER FILE MAP
File
File
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
Address
Address
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
INDF
INDF
80h
TMR0
PCL
OPTION_REG 81h
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers asso-
ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
STATUS
FSR
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
(2)
(2)
08h PORTD
09h PORTE
TRISD
(2)
(2)
TRISE
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
PCLATH
PCLATH
INTCON
PIE1
INTCON
PIR1
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
PR2
SSPADD
SSPSTAT
17h CCP1CON
18h
19h
1Ah
1Bh
1Ch
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
TXSTA
SPBRG
1Dh CCP2CON
(3)
1Eh ADRES
(3)
(3)
1Fh ADCON0
ADCON1
20h
General
Purpose
Register
General
Purpose
Register
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read
as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
DS30605A-page 12
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 2-1
SPECIAL FUNCTION REGISTER SUMMARY
Value on Value on all
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(5)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
TMR0
PCL(1)
Program Counter's (PC) Least Significant Byte
STATUS(1)
FSR(1)
IRP(6)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1(6)
RP0
TO
PD
Z
DC
C
PORTA(7)
PORTB(8)
PORTC(8)
PORTD(3,8)
PORTE(3,8)
PCLATH(1,2)
INTCON(1)
PIR1
—
—
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
—
—
—
—
—
—
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF(4)
—
T0IE
RCIF
—
INTE
TXIF
–
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(3)
—
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
PIR2
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
TMR1H
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
TMR2
Timer2 module’s register
0000 0000 0000 0000
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
USART Transmit Data Register
USART Receive Data Register
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES(4)
ADCON0(4)
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
1998 Microchip Technology Inc.
DS30605A-page 13
PIC16C63A/65B/73B/74B
TABLE 2-1
Addr Name
Bank 1
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on Value on all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(5)
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
OPTION_REG
PCL(1)
STATUS(1)
FSR(1)
TRISA
TRISB
TRISC
TRISD(3)
TRISE(3)
PCLATH(1,2)
INTCON(1)
PIE1
RBPU
Program Counter's (PC) Least Significant Byte
IRP(6) RP1(6)
RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
—
—
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIE(4)
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
SSPIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
PSPIE(3)
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PIE2
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
PR2
Timer2 Period Register
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
SSPADD
SSPSTAT
—
Synchronous Serial Port (I2C mode) Address Register
SMP
CKE
D/A
P
S
R/W
UA
BF
Unimplemented
Unimplemented
Unimplemented
CSRC
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1(4)
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
DS30605A-page 14
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
The STATUS register, shown in Figure 2-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled.These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear
0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh) - not implemented, maintain clear
10= Bank 2 (100h - 17Fh) - not implemented, maintain clear
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998 Microchip Technology Inc.
DS30605A-page 15
PIC16C63A/65B/73B/74B
2.2.2.2
OPTION_REG REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on PORTB.
FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
DS30605A-page 16
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
1998 Microchip Technology Inc.
DS30605A-page 17
PIC16C63A/65B/73B/74B
2.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
This register contains the individual enable bits for the
peripheral interrupts.
enable any peripheral interrupt.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
R/W-0
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
TMR2IE TMR1IE
bit0
R/W-0
(1)
(2)
PSPIE
bit7
ADIE
CCP1IE
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
(1)
bit 7:
PSPIE : Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
(2)
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
ADIE : A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module.This bit location is reserved on these devices. Always maintain
this bit clear.
DS30605A-page 18
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
TMR2IF TMR1IF
bit0
R/W-0
(1)
(2)
PSPIF
bit7
ADIF
RCIF
TXIF
CCP1IF
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
ADIF(2): A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module.This bit location is reserved on these devices. Always maintain
this bit clear.
1998 Microchip Technology Inc.
DS30605A-page 19
PIC16C63A/65B/73B/74B
2.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IE
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS30605A-page 20
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
.
2.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the CCP2 interrupt flag bit.
FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IF
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
1998 Microchip Technology Inc.
DS30605A-page 21
PIC16C63A/65B/73B/74B
2.2.2.8
PCON REGISTER
Note: If the BODEN configuration bit is set, BOR
is ’1’ on Power-on Reset. If the BODEN
configuration bit is clear, BOR is unknown
on Power-on Reset.
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con-
tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
The BOR status bit is a "don't care" and is
not necessarily predictable if the brown-out
circuit is disabled (the BODEN configura-
tion bit is clear). BOR must then be set by
the user and checked on subsequent
resets to see if it is clear, indicating a
brown-out has occurred.
FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-q
BOR
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
DS30605A-page 22
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2.3
PCL and PCLATH
2.4
Program Memory Paging
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg-
ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALLor GOTOinstruction
the upper bit of the address is provided by
PCLATH<3>. When doing a CALLor GOTOinstruction,
the user must ensure that the page select bit is pro-
grammed so that the desired program memory page is
addressed. If a return from a CALLinstruction (or inter-
rupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).
2.3.1
STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-Range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable.The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
1998 Microchip Technology Inc.
DS30605A-page 23
PIC16C63A/65B/73B/74B
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
2.5
Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Address-
ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer). This is indirect addressing.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR
clrf
incf
;
to RAM
INDF ;clear INDF register
FSR ;inc pointer
EXAMPLE 2-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
NEXT
btfss FSR,4 ;all done?
goto
NEXT ;NO, clear next
CONTINUE
:
;YES, continue
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-11. However, IRP is not used in the
PIC16C63A/65B/73B/74B.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
(2)
6
0
0
IRP
(2)
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
(3)
(3)
Data
Memory(1)
7Fh
Bank 0
Note 1: For register file map detail see Figure 2-2.
FFh
17Fh
1FFh
Bank 3
Bank 1 Bank 2
2: Maintain RP1 and IRP as clear for upward compatibility with future products.
3: Not implemented.
DS30605A-page 24
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
bus
D
Q
Q
VDD
P
WR
Port
Additional information on I/O ports may be found in the
PICmicro Mid-Range Reference Manual, (DS33023).
CK
Data Latch
3.1
PORTA and the TRISA Register
I/O pin(1)
N
D
Q
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
WR
TRIS
VSS
Q
CK
Analog
input
TRIS Latch
mode
(73B/74B
only)
Note: On a Power-on Reset, these pins are con-
TTL
input
buffer
RD TRIS
figured as inputs and read as '0'.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read.This value is modified and then written to the port
data latch.
Q
D
EN
RD PORT
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
To A/D Converter (73B/74B only)
Note 1: I/O pins have protection diodes to VDD and
VSS.
On PIC16C73B/74B devices, other PORTA pins are
multiplexed with analog inputs and analog VREF input.
The operation of each pin is selected by clearing/set-
ting the control bits in the ADCON1 register (A/D Con-
trol Register1).
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Data
bus
D
Q
Q
Note: On a Power-on Reset, these pins are con-
WR
PORT
figured as analog inputs and read as '0'.
CK
I/O pin(1)
N
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data Latch
D
Q
VSS
WR
TRIS
Schmitt
Trigger
input
Q
CK
EXAMPLE 3-1: INITIALIZING PORTA
TRIS Latch
buffer
BCF
STATUS, RP0
;
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
RD TRIS
BSF
MOVLW 0xCF
STATUS, RP0 ; Select Bank 1
Q
D
; Value used to
; initialize data
; direction
EN
MOVWF TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
1998 Microchip Technology Inc.
DS30605A-page 25
PIC16C63A/65B/73B/74B
TABLE 3-1:
PORTA FUNCTIONS
Name
Bit#
bit0
bit1
bit2
bit3
bit4
Buffer Function
(1)
(1)
(1)
(1)
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
TTL
TTL
TTL
TTL
ST
Input/output or analog input
Input/output or analog input
Input/output or analog input
(1)
Input/output or analog input or VREF
Input/output or external clock input for Timer0
Output is open drain type
(1)
RA5/SS/AN4
bit5
TTL
Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: On PIC16C73B/74B devices only.
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
POR,
BOR
Value on all
other resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
(1)
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: On PIC16C73B/74B devices only.
DS30605A-page 26
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
EXAMPLE 3-1: INITIALIZING PORTB
BCF
STATUS, RP0
;
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
a) Any read or write of PORTB. This will end the
mismatch condition.
BSF
STATUS, RP0 ; Select Bank 1
b) Clear flag bit RBIF.
MOVLW 0xCF
; Value used to
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
MOVWF TRISB
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups.This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
VDD
FIGURE 3-3: BLOCK DIAGRAM OF
RBPU(2)
weak
P
RB3:RB0 PINS
pull-up
VDD
Data Latch
Data bus
RBPU(2)
D
Q
weak
P
pull-up
I/O
pin(1)
WR Port
Data Latch
Data bus
CK
TRIS Latch
D
Q
I/O
pin(1)
D
Q
WR Port
CK
TRIS Latch
WR TRIS
TTL
CK
Input
Buffer
D
Q
ST
Buffer
TTL
Input
Buffer
WR TRIS
CK
RD TRIS
RD Port
Latch
Q
Q
D
RD TRIS
RD Port
EN
Q1
Set RBIF
Q
D
EN
D
From other
RB7:RB4 pins
RD Port
Q3
EN
RB0/INT
Schmitt Trigger
Buffer
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
1998 Microchip Technology Inc.
DS30605A-page 27
PIC16C63A/65B/73B/74B
TABLE 3-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
(1)
RB0/INT
bit0
TTL/ST
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
TTL/ST
TTL/ST
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
(2)
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
06h
86h
81h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
PS2
RB1
PS1
RB0
PS0
xxxx xxxx
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PORTB Data Direction Register
OPTION_ RBPU
REG
INTEDG
T0CS T0SE PSA
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30605A-page 28
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.3
PORTC and the TRISC Register
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORTC is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
PORT/PERIPHERAL Select(2)
Peripheral Data Out
VDD
0
Data bus
WR
PORT
D
Q
Q
P
1
CK
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
Data Latch
I/O
D
Q
Q
pin(1)
WR
TRIS
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided.The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
CK
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
PORT
Peripheral input
EXAMPLE 3-1: INITIALIZING PORTC
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
BCF
STATUS, RP0 ; Select Bank 0
CLRF
PORTC ; Initialize PORTC by
; clearing output
; data latches
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISC
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
1998 Microchip Technology Inc.
DS30605A-page 29
PIC16C63A/65B/73B/74B
TABLE 3-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
bit0
RC0/T1OSO/T1CKI
RC1/T1OSI
ST
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input
Input/output port pin or Timer1 oscillator input
bit1
bit2
RC2/CCP1
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
2
RC3/SCK/SCL
bit3
ST
RC3 can also be the synchronous serial clock for both SPI and I C
modes.
2
RC4/SDI/SDA
bit4
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I C mode).
RC5/SDO
RC6
bit5
bit6
bit7
ST
ST
ST
Input/output port pin or Synchronous Serial Port data output
Input/output port pin
RC7
Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on
POR,
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC
TRISC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PORTC Data Direction Register
Legend: x= unknown, u= unchanged.
DS30605A-page 30
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.4
PORTD and TRISD Registers
section is applicable
This
to
the
PIC16C65B/PIC16C74B devices only.
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
FIGURE 3-6: PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
Data
bus
D
Q
WR
PORT
I/O pin(1)
CK
Data Latch
D
Q
WR
TRIS
Schmitt
Trigger
input
CK
TRIS Latch
buffer
RD TRIS
Q
D
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
1998 Microchip Technology Inc.
DS30605A-page 31
PIC16C63A/65B/73B/74B
TABLE 3-7:
Name
PORTD FUNCTIONS
Bit#
Buffer Type
Function
(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on
POR,
BOR
Value on all
other resets
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD RD7 RD6 RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
TRISD PORTD Data Direction Register
TRISE IBF OBF IBOV PSPMODE
—
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30605A-page 32
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.5
PORTE and TRISE Register
section is applicable
Note: On a Power-on Reset these pins are con-
figured as analog inputs.
This
to
the
FIGURE 3-7: PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
PIC16C65B/PIC16C74B devices only. The A/D multi-
plexed functions are available on the PIC16C74B only.
Data
bus
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
D
Q
WR
PORT
I/O pin(1)
CK
Data Latch
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). For the PIC16C74B ensure ADCON1 is config-
ured for digital I/O. In this mode, the input buffers are
TTL.
D
Q
WR
TRIS
Schmitt
Trigger
input
CK
TRIS Latch
buffer
Figure 3-8 shows the TRISE register, which also con-
trols the parallel slave port operation.
RD TRIS
PORTE pins for the PIC16C74B only are multiplexed
with analog inputs. When selected as an analog input,
these pins will read as '0's.
Q
D
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 3-8: TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
R/W-0
U-0
—
R/W-1
R/W-1
TRISE1 TRISE0
bit0
R/W-1
OBF
IBOV PSPMODE
TRISE2
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as '0'
TRISE2: RE2 Direction Control bit
1 = Input
0 = Output
bit 1:
bit 0:
TRISE1: RE2 Direction Control bit
1 = Input
0 = Output
TRISE0: RE2 Direction Control bit
1 = Input
0 = Output
1998 Microchip Technology Inc.
DS30605A-page 33
PIC16C63A/65B/73B/74B
TABLE 3-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
(2)
(1)
RE0/RD/AN5
bit0
ST/TTL
Input/output port pin or read control input in parallel slave port mode or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
(2)
(1)
RE1/WR/AN6
bit1
bit2
ST/TTL
Input/output port pin or write control input in parallel slave port mode or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
(2)
(1)
RE2/CS/AN7
ST/TTL
Input/output port pin or chip select control input in parallel slave port
mode or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.
2: A/D Converter module multiplexing is implemented on the PIC16C74B only.
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on
POR,
BOR
Value on all
other resets
Addr Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
89h
9Fh
PORTE
TRISE
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
---- -000 ---- -000
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
PCFG2 PCFG1 PCFG0
(1)
ADCON1
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: A/D Converter module multiplexing is implemented on the PIC16C74B only.
DS30605A-page 34
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
3.6
Parallel Slave Port
FIGURE 3-9: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC16C65B and PIC16C74B).
SLAVE PORT)
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data bus
D
Q
WR
PORT
RDx
pin
CK
TTL
Q
D
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). For the
PIC16C74B, the A/D port configuration bits
PCFG2:PCFG0 (ADCON1<2:0>) must be set, which
will configure pins RE2:RE0 as digital I/O.
RD
PORT
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
RD
CS
WR
TTL
Chip Select
TTL
TTL
Write
Note: I/O pin has protection diodes to VDD and VSS.
FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
1998 Microchip Technology Inc.
DS30605A-page 35
PIC16C63A/65B/73B/74B
FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on
POR,
BOR
Value on all
other resets
Add. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h PORTD
09h PORTE
89h TRISE
0Ch PIR1
Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF
IBOV PSPMODE
—
PORTE Data Direction Bits
(1)
PSPIF ADIF
PSPIE ADIE
RCIF
RCIE
—
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
(1)
8Ch PIE1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
(1)
9Fh ADCON1
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: On PIC16C74B only.
DS30605A-page 36
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Additional information on external clock requirements
is available in the PICMicro Mid-Range Reference
Manual, (DS33023).
4.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
4.2
Prescaler
• 8-bit timer/counter
• Readable and writable
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available, which is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro
(DS33023).
Mid-Range Reference Manual,
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
4.1
Timer0 Operation
Timer0 can operate as a timer or as a counter.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Setting bit PSA will assign the prescaler to the Watch-
dog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed below.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler.When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the WDT.
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC).There is a delay in the actual incre-
menting of Timer0 after synchronization.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
PSout
(2 cycle delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
1998 Microchip Technology Inc.
DS30605A-page 37
PIC16C63A/65B/73B/74B
4.2.1
SWITCHING PRESCALER ASSIGNMENT
4.3
Timer0 Interrupt
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt.The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP.
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro Mid-Range Reference Manual,
(DS33023). must be executed when
changing the prescaler assignment from
Timer0 to the WDT.This sequence must be
followed even if the WDT is disabled.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 module’s register
GIE PEIE T0IE INTE
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
0Bh, 8Bh
81h
INTCON
RBIE
PSA
T0IF
PS2
INTF
PS1
OPTION_REG RBPU INTEDG T0CS T0SE
TRISA
PS0
1111 1111 1111 1111
--11 1111 --11 1111
85h
—
—
PORTA Data Direction Register
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS30605A-page 38
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.1
Timer1 Operation
5.0
TIMER1 MODULE
The Timer1 module timer/counter has the following fea-
tures:
Timer1 can operate in one of these modes:
• As a timer
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• As a synchronous counter
• As an asynchronous counter
• Readable and writable (Both registers)
• Internal or external clock select
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
Timer1 also has an internal “reset input”.This reset can
be generated by the CCP module (Section 7.0).
the PICmicro
(DS33023).
Mid-Range Reference Manual,
FIGURE 5-1: T1CON:TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
1998 Microchip Technology Inc.
DS30605A-page 39
PIC16C63A/65B/73B/74B
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
clock input
0
TMR1
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
RC0/T1OSO/T1CKI
RC1/T1OSI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FOSC/4
Internal
Clock
0
(1)
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
DS30605A-page 40
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
5.2
Timer1 Oscillator
5.3
Timer1 Interrupt
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>).The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 oscillator.
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clear-
ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4
Resetting Timer1 using a CCPTrigger
Output
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
TABLE 5-1:
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1, the write will take prece-
dence.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
In this mode of operation, the CCPR1H:CCPR1L regis-
ters pair effectively becomes the period register for
Timer1.
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
TABLE 5-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Bh,8Bh INTCON GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
(1)
(1)
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
(1)
(1)
(1)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: These bits are reserved, maintain as '0'.
1998 Microchip Technology Inc.
DS30605A-page 41
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 42
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
6.1
Timer2 Operation
6.0
TIMER2 MODULE
The Timer2 module timer has the following features:
Timer2 can be used as the PWM time-base for PWM
mode of the CCP module.
• 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
The TMR2 register is readable and writable, and is
cleared on any device reset.
• Readable and writable (Both registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match of PR2
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
• SSP module optional use of TMR2 output to gen-
erate clock shift
Timer2 has a control register, shown in Figure 6-1.
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
The prescaler and postscaler counters are cleared
when any of the following occurs:
Figure 6-2 is a simplified block diagram of the Timer2
module.
• a write to the TMR2 register
• a write to the T2CON register
Additional information on timer modules is available in
• any device reset (Power-on Reset, MCLR reset,
Watchdog Timer reset, or Brown-out Reset)
the PICmicro
(DS33023).
Mid-Range Reference Manual,
TMR2 is not cleared when T2CON is written.
FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
1998 Microchip Technology Inc.
DS30605A-page 43
PIC16C63A/65B/73B/74B
6.2
Timer2 Interrupt
FIGURE 6-2: TIMER2 BLOCK DIAGRAM
Sets flag
TMR2
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register.The PR2 register is ini-
tialized to FFh upon reset.
output (1)
bit TMR2IF
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
Postscaler
1:1 to 1:16
2
Comparator
6.3
Output ofTMR2
EQ
4
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate shift clock.
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
(1)
(1)
(1)
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
(1)
(1)
(1)
8Ch
PIE1
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2
module.
Note 1: These bits are reserved, maintain as '0'.
DS30605A-page 44
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
CCP2 Module
7.0
CAPTURE/COMPARE/PWM
(CCP) MODULE(S)
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 7-1 shows the
timer resources of the CCP module modes.
Additional information on the CCP module is available
in the PICmicro
(DS33023).
Mid-Range Reference Manual,
The operation of CCP1 is identical to that of CCP2, with
the exception of the special trigger. Therefore, opera-
tion of a CCP module in the following sections is
described with respect to CCP1.
TABLE 7-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Table 7-2 shows the interaction of the CCP modules.
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 7-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
Compare
None
None
PWM
FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit0
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx= PWM mode
1998 Microchip Technology Inc.
DS30605A-page 45
PIC16C63A/65B/73B/74B
7.1.4
CCP PRESCALER
7.1
Capture Mode
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• every falling edge
• every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 7-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
• every 4th rising edge
• every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
EXAMPLE 7-1: CHANGING BETWEEN
CAPTURE PRESCALERS
7.1.1
CCP PIN CONFIGURATION
CLRF
CCP1CON
;Turn CCP module off
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
MOVWF CCP1CON
FIGURE 7-2: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
RC2/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
Capture
Enable
and
edge detect
TMR1H
CCP1CON<3:0>
Q’s
7.1.2
TIMER1 MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
7.1.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
DS30605A-page 46
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.2.1
CCP PIN CONFIGURATION
7.2
Compare Mode
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
• driven High
• driven Low
• remains Unchanged
7.2.2
TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 7-3: COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.3
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Special event trigger will
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>),
which starts an A/D conversion
7.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
Special Event Trigger (CCP2 only)
Set flag bit CCP1IF
(PIR1<2>)
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Note: The special event trigger from the CCP2
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
TABLE 7-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
8Ch
87h
INTCON
GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(1)
(1)
PIR1
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1111 1111 1111 1111
(1)
(1)
(1)
PIE1
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
0Eh
0Fh
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON CCP1X CCP1Y
17h
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: These bits/registers are reserved, maintain as '0'.
1998 Microchip Technology Inc.
DS30605A-page 47
PIC16C63A/65B/73B/74B
7.3.1
PWM PERIOD
7.3
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] ¥ 4 ¥ TOSC ¥
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 7-4 shows a simplified block diagram of the CCP
module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 7.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 7-4: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 6.0) is
not used in the determination of the PWM
frequency.The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty cycle registers
CCPR1L
7.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1H (Slave)
Q
R
S
Comparator
TMR2
RC2/CCP1
(Note 1)
PWM DUTY CYCLE = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 PRESCALE VALUE)
TRISC<2>
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 7-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (1/
period).
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.=
FIGURE 7-5: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM fre-
quency:
Period
FOSC
---------------
log
FPWM
-----------------------------
=
bits
log(2)
Duty Cycle
TMR2 = PR2
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
For an example PWM period and duty cycle calcula-
tion, see the PICmicro Mid-Range Reference Manual
(DS33023).
DS30605A-page 48
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
7.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 7-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
TABLE 7-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
all other
resets
0Bh,8Bh
0Ch
8Ch
87h
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(1)
(1)
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
1111 1111 1111 1111
(1)
(1)
(1)
PIE1
TRISC
TMR2
PORTC Data Direction Register
Timer2 module’s register
11h
0000 0000 0000 0000
92h
PR2
Timer2 module’s period register
1111 1111 1111 1111
12h
T2CON
CCPR1L
CCPR1H
CCP1CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: These bits/registers are reserved, maintain as '0'.
1998 Microchip Technology Inc.
DS30605A-page 49
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 50
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.0
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
8.1
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
For more information on SSP operation (including an
2
I C Overview), refer to the PICmicro Mid-Range Ref-
erence Manual (DS33023). Also, refer to Application
2
Note AN578, “Use of the SSP Module in the I C Multi-
Master Environment.”
1998 Microchip Technology Inc.
DS30605A-page 51
PIC16C63A/65B/73B/74B
FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 R/W-0
SMP CKE
bit7
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
- n =Value at POR reset
bit 7:
bit 6:
SMP: SPI data input sample phase
SPI Master Operation
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
CKE: SPI Clock Edge Select
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
2
bit 5:
bit 4:
D/A: Data/Address bit (I C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
2
P: Stop bit (I C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
2
bit 3:
bit 2:
S: Start bit (I C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
2
bit 1:
bit 0:
UA: Update Address (10-bit I C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS30605A-page 52
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
WCOL SSPOV SSPEN
bit7
SSPM3 SSPM2 SSPM1 SSPM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode.The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since
each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
2
In I C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
2
In I C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI master operation, clock = FOSC/4
0001= SPI master operation, clock = FOSC/16
0010= SPI master operation, clock = FOSC/64
0011= SPI master operation, clock = TMR2 output/2
0100= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110= I C slave mode, 7-bit address
2
0111= I C slave mode, 10-bit address
2
1011= I C firmware controlled master operation (slave idle)
2
1110= I C slave mode, 7-bit address with start and stop bit interrupts enabled
2
1111= I C slave mode, 10-bit address with start and stop bit interrupts enabled
1998 Microchip Technology Inc.
DS30605A-page 53
PIC16C63A/65B/73B/74B
8.2
SPI Mode
Note: When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
This section contains register definitions and opera-
tional characteristics of the SPI module.
Additional information on SPI operation may be found
in the PICmicro
(DS33023).
Mid-Range Reference Manual
Note: If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
8.2.1
OPERATION OF SSP MODULE IN SPI
MODE
FIGURE 8-3: SSP BLOCK DIAGRAM
(SPI MODE)
A block diagram of the SSP Module in SPI Mode is
shown in Figure 8-3.
Internal
data bus
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
Read
Write
SSPBUF reg
SSPSR reg
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI)
• Serial Clock (SCK)
RC4/SDI/SDA
RC3/SCK/SCL
Additionally a fourth pin may be used when in a slave
mode of operation:
shift
clock
RC4/SDI/SDA
RC5/SDO
bit0
• Slave Select (SS)
RA5/SS/AN4
When initializing the SPI, several options need to be
specified.This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
Control
Enable
SS
RA5/SS/AN4
Edge
Select
• Master Operation (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
2
Clock Select
• Clock Edge (Output data on rising/falling edge of
SCK)
SSPM3:SSPM0
4
TMR2 output
2
• Clock Rate (master operation only)
• Slave Select Mode (Slave mode only)
Edge
Select
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set.To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister and then set bit SSPEN. This configures the SDI,
SDO, SCK and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (master operation) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
DS30605A-page 54
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 8-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
(1)
(1)
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
(1)
(1)
(1)
8Ch
87h
PIE1
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
13h
14h
85h
94h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
TRISA
—
—
PORTA Data Direction Register
D/A R/W
--11 1111 --11 1111
0000 0000 0000 0000
SSPSTAT
SMP
CKE
P
S
UA
BF
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Always maintain these bits clear.
1998 Microchip Technology Inc.
DS30605A-page 55
PIC16C63A/65B/73B/74B
2
2
The SSPCON register allows control of the I C opera-
8.3
SSP I C Operation
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I C modes to be selected:
2
2
The SSP module in I C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifica-
tions as well as 7-bit and 10-bit addressing.
2
• I C Slave mode (7-bit address)
2
• I C Slave mode (10-bit address)
2
• I C Slave mode (7-bit address), with start and
stop bit interrupts enabled
2
• I C Slave mode (10-bit address), with start and
Two pins are used for data transfer.These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
stop bit interrupts enabled
2
• I C Firmware controlled master operation, slave
is idle
2
Selection of any I C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
2
FIGURE 8-4: SSP BLOCK DIAGRAM
Additional information on SSP I C operation may be
2
(I C MODE)
found in the PICMicro Mid-Range Reference Manual
(DS33023).
8.3.1
SLAVE MODE
Internal
data bus
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
Read
Write
SSPBUF reg
SSPSR reg
RC3/SCK/SCL
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
shift
clock
RC4/
SDI/
MSb
LSb
SDA
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
Addr Match
Match detect
SSPADD reg
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 8-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
2
The SSP module has five registers for I C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
• SSP Address Register (SSPADD)
2
I C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
DS30605A-page 56
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.3.1.1
ADDRESSING
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows with steps 7- 9 for slave-transmit-
ter:
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
a) The SSPSR register value is loaded into the
SSPBUF register.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
5. Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
7. Receive repeated START condition.
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 8-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
Pulse
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
Yes
No
No
No
Yes
Yes
Yes
Yes
No
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
1998 Microchip Technology Inc.
DS30605A-page 57
PIC16C63A/65B/73B/74B
8.3.1.2
RECEPTION
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
2
FIGURE 8-5:
I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
9
ACK
9
ACK
9
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
7
1
2
4
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
DS30605A-page 58
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
8.3.1.3
TRANSMISSION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSP-
BUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input.This ensures that the SDA
signal is valid during the SCL high time (Figure 8-6).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT reg-
ister) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
2
FIGURE 8-6: I C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
From SSP interrupt
service routine
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
1998 Microchip Technology Inc.
DS30605A-page 59
PIC16C63A/65B/73B/74B
8.3.2
MASTER OPERATION
8.3.3
MULTI-MASTER OPERATION
Master operation is supported in firmware using inter-
rupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a reset or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
In multi-master operation, the interrupt generation on
the detection of the START and STOP conditions
allows the determination of when the bus is free. The
STOP (P) and START (S) bits are cleared from a reset
or when the SSP module is disabled. The STOP (P)
and START (S) bits will toggle based on the START and
2
2
the I C bus may be taken when the P bit is set, or the
STOP conditions. Control of the I C bus may be taken
bus is idle and both the S and P bits are clear.
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In master operation, the SCL and SDA lines are manip-
ulated in firmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So when
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
transmitting data,
a '1' data bit must have the
TRISC<4> bit set (input) and a '0' data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
• Data transfer byte transmitted/received
Master operation can be done with either the slave
mode idle (SSPM3:SSPM0 = 1011) or with the slave
active. When both master operation and slave modes
are used, the software needs to differentiate the
source(s) of the interrupt.
For more information on master operation, see AN554
For more information on master operation, see AN578
2
- Software Implementation of I C Bus Master.
2
- Use of the SSP Module in the of I C Multi-Master
Environment.
2
TABLE 8-3:
REGISTERS ASSOCIATED WITH I C OPERATION
Value on
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh, 8Bh
0Ch
8Ch
13h
INTCON
PIR1
GIE
PEIE
ADIF
T0IE
INTE
RBIE
T0IF
INTF
RBIF
(1)
(1)
(1)
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
(1)
(1)
PIE1
ADIE
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
2
93h
SSPADD Synchronous Serial Port (I C mode) Address Register
14h
SSPCON
SSPSTAT
TRISC
WCOL
SMP
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
CKE D/A R/W UA BF
94h
P
S
PORTC Data Direction register
87h
1111 1111 1111 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: These bits are unimplemented, read as '0'.
DS30605A-page 60
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The USART can be configured in the following modes:
9.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI).The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and RC7/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
FIGURE 9-1: TXSTA:TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n =Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
1998 Microchip Technology Inc.
DS30605A-page 61
PIC16C63A/65B/73B/74B
FIGURE 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
R-0
R-x
FERR
OERR
RX9D
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n =Value at POR reset
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS30605A-page 62
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.1
USART Baud Rate Generator (BRG)
EXAMPLE 9-1: CALCULATING BAUD
RATE ERROR
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 9-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Desired Baud rate
=Fosc / (64 (X + 1))
=16000000 /(64 (X + 1))
= 25.042 = 25
9600
X
Calculated Baud Rate =16000000 / (64 (25 + 1))
=
=
9615
Error
(Calculated Baud Rate-Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 9-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Example 9-1 shows the calculation of the baud rate
error for the following conditions:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
SYNC = 0
9.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
TABLE 9-1:
SYNC
BAUD RATE FORMULA
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
TABLE 9-2:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on
POR,
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
0000 -010 0000 -010
98h
18h
99h
TXSTA CSRC TX9
RCSTA SPEN RX9
TXEN SYNC
SREN CREN
—
—
BRGH TRMT TX9D
FERR OERR RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
1998 Microchip Technology Inc.
DS30605A-page 63
PIC16C63A/65B/73B/74B
TABLE 9-3:
BAUD RATES FOR SYNCHRONOUS MODE
BAUD FOSC = 20 MHz SPBRG
16 MHz
SPBRG
value
10 MHz
SPBRG 7.15909 MHz
value
SPBRG
value
RATE
(K)
value
KBAUD
NA
%
KBAUD
%
-
KBAUD
%
KBAUD
NA
%
-
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
NA
NA
NA
NA
-
-
NA
-
-
-
-
-
NA
-
-
NA
-
-
NA
-
2.4
NA
-
-
-
-
NA
-
NA
-
-
9.6
NA
-
+1.73
+0.16
+0.16
-1.96
0
-
-
-
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
9.622 +0.23
19.24 +0.23
77.82 +1.32
185
92
22
18
5
19.2
76.8
96
19.53
76.92
96.15
294.1
500
255
64
51
16
9
19.23 +0.16
76.92 +0.16
207
51
41
12
7
95.24
-0.79
94.20
298.3
NA
-1.88
300
500
HIGH
LOW
307.69 +2.56
-0.57
500
4000
0
-
4
-
-
-
-
5000
19.53
-
0
0
2500
9.766
-
0
1789.8
6.991
0
-
255
15.625
-
255
-
255
255
BAUD
RATE
(K)
FOSC = 5.0688 MHz
4 MHz
SPBRG 3.579545 MHz SPBRG
1 MHz
SPBRG
value
32.768 kHz
SPBRG
value
value
value
KBAUD
NA
%
SPBRG KBAUD
%
-
KBAUD
NA
%
KBAUD
NA
%
-
KBAUD
%
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
-
-
-
NA
NA
NA
-
-
-
-
-
-
207
103
25
12
2
0.303
1.170
NA
+1.14
26
NA
-
-
NA
-
1.202 +0.16
2.404 +0.16
9.615 +0.16
19.24 +0.16
83.34 +8.51
-2.48
6
2.4
NA
-
-
-
-
NA
-
-
-
-
-
-
-
-
-
-
-
-
9.6
9.6
0
131
65
15
12
3
9.615 +0.16
19.231 +0.16
76.923 +0.16
103
51
12
9
9.622
19.04
74.57
99.43
298.3
NA
+0.23
-0.83
-2.90
+3.57
-0.57
-
92
46
11
8
NA
-
19.2
76.8
96
19.2
79.2
97.48
316.8
NA
0
NA
-
+3.13
NA
-
+1.54
1000
NA
+4.17
NA
NA
-
-
-
-
-
-
NA
-
300
500
HIGH
LOW
+5.60
-
-
-
-
-
2
-
NA
-
-
-
-
-
-
NA
-
-
NA
-
NA
1267
4.950
0
100
0
894.9
3.496
-
0
250
0
8.192
0.032
0
255
3.906
255
-
255
0.9766
255
255
TABLE 9-4:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD FOSC = 20 MHz SPBRG
16 MHz
SPBRG
value
10 MHz
SPBRG 7.15909 MHz
value
SPBRG
value
RATE
(K)
value
%
-
%
%
%
(decimal)
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
-
255
129
32
15
3
NA
-
-
207
103
25
12
2
NA
1.202
2.404
9.766
19.53
78.13
NA
-
-
129
64
15
7
NA
-
-
92
46
11
5
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
1.202 +0.16
2.404 +0.16
9.615 +0.16
19.23 +0.16
83.33 +8.51
+0.16
1.203 +0.23
2.4
+0.16
2.380
9.322
18.64
NA
-0.83
9.6
+1.73
-2.90
19.2
76.8
96
+1.73
-2.90
+1.73
1
-
-
-
-
-
-
-
2
NA
NA
-
-
-
-
-
-
-
-
-
-
-
-
NA
-
300
500
HIGH
LOW
0
-
NA
-
NA
-
-
NA
-
NA
-
NA
-
312.5
1.221
-
0
250
0.977
0
156.3
0.6104
0
111.9
0.437
0
-
255
255
255
255
BAUD
RATE
(K)
FOSC = 5.0688 MHz
4 MHz
SPBRG 3.579545 MHz SPBRG
1 MHz
SPBRG
value
(decimal)
32.768 kHz
SPBRG
value
(decimal)
value
value
%
SPBRG
%
%
%
%
(decimal)
(decimal)
0.3
1.2
0.31
1.2
+3.13
255
65
32
7
0.3005 -0.17
1.202 +1.67
2.404 +1.67
207
0.301
1.190
2.432
9.322
18.64
NA
+0.23
185
46
22
5
0.300 +0.16
1.202 +0.16
51
0.256 -14.67
1
0
51
-0.83
12
NA
NA
-
-
-
-
-
-
-
-
-
-
-
2.4
2.4
0
25
+1.32
2.232
NA
-6.99
6
-
9.6
9.9
+3.13
NA
NA
-
-
-
-
-
-
-
-
-
-2.90
-
-
-
-
-
-
-
-
-
NA
-
19.2
76.8
96
19.8
79.2
NA
+3.13
3
-
-2.90
2
NA
-
NA
-
+3.13
0
NA
-
-
-
-
-
-
-
-
NA
-
NA
-
-
-
-
-
-
-
NA
-
NA
-
NA
-
NA
-
300
500
HIGH
NA
-
NA
-
-
NA
-
NA
-
-
NA
-
-
NA
-
NA
NA
-
NA
NA
79.2
0
62.500
3.906
0
55.93
0.2185
0
15.63
0.0610
0
0.512
0.0020
0
LOW 0.3094
255
255
255
255
255
DS30605A-page 64
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 9-5:
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD FOSC = 20 MHz SPBRG
16 MHz
SPBRG
value
10 MHz
SPBRG
value
7.16 MHz
SPBRG
value
RATE
(K)
value
%
+0.16
+0.16
-1.36
-1.36
-1.36
0
%
%
%
(decimal)
(deci-
(decimal)
(deci-
9.6
9.615
19.230
37.878
56.818
129
64
32
21
10
4
9.615 +0.16
19.230 +0.16
38.461 +0.16
58.823 +2.12
111.111 -3.55
103
51
25
16
8
9.615
18.939 -1.36
39.062 +1.7
56.818 -1.36
+0.16
64
32
15
10
4
9.520
-0.83
46
22
11
7
19.2
38.4
57.6
19.454 +1.32
37.286 -2.90
55.930 -2.90
111.860 -2.90
115.2 113.636
125
NA
+8.51
3
250
625
250
625
250
NA
NA
0
-
3
-
0
-
-
NA
NA
NA
-
-
-
-
0
1
-
625
NA
0
-
1250
1250
0
0
-
-
-
-
BAUD
RATE
(K)
FOSC = 5.068
%
SPBRG
value
4 MHz
SPBRG
value
3.579 MHz
%
SPBRG
value
1 MHz
SPBRG
value
32.768 kHz
%
SPBRG
value
%
-
%
(decimal)
(decimal)
(decimal)
(decimal)
(decimal)
9.6
19.2
38.4
57.6
115.2
250
9.6
18.645
39.6
52.8
105.6
NA
0
-2.94
+3.12
-8.33
-8.33
-
32
16
7
5
2
-
NA
-
207
103
25
12
-
9.727 +1.32
18.643 -2.90
37.286 -2.90
55.930 -2.90
111.860 -2.90
223.721 -10.51
22
11
5
8.928
-6.99
6
2
1
0
-
NA
NA
NA
NA
NA
NA
NA
NA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1.202 +0.17
2.403 +0.13
9.615 +0.16
19.231 +0.16
20.833 +8.51
31.25 -18.61
3
62.5
NA
NA
NA
NA
+8.51
1
-
-
-
-
NA
NA
NA
-
-
-
0
-
625
NA
-
-
-
NA
NA
-
-
-
-
1250
NA
-
-
-
-
-
1998 Microchip Technology Inc.
DS30605A-page 65
PIC16C63A/65B/73B/74B
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register.While flag bit TXIF indicated the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
9.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first.The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock, either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
is set.
Steps to follow when setting up an asynchronous trans-
mission:
The USART Asynchronous module consists of the fol-
lowing important elements:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1)
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
9.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 9-3. The heart of the transmitter is the transmit
(serial) shift register (TSR).The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts trans-
mission).
FIGURE 9-3: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30605A-page 66
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-4: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 9-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Start Bit
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
TXIF bit
(interrupt reg. flag)
WORD 1
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 9-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 0000 0000 0000
(1)
(2)
0Ch
PIR1
RCIF
SREN
TXREG USART Transmit Register
TXIF SSPIF CCP1IF TMR2IF TMR1IF
CREN FERR OERR RX9D
PSPIF
ADIF
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
18h
19h
8Ch
RCSTA SPEN
RX9
—
(1)
(2)
RCIE
PIE1
TXSTA CSRC
TXIE SSPIE CCP1IE TMR2IE TMR1IE
SYNC BRGH TRMT TX9D
PSPIE
ADIE
TX9
0000 -010 0000 -010
0000 0000 0000 0000
98h
99h
TXEN
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: PORTD and PORTE not implemented on the PIC16C63A/73B, maintain as ’0’.
2: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
1998 Microchip Technology Inc.
DS30605A-page 67
PIC16C63A/65B/73B/74B
9.2.2
USART ASYNCHRONOUS RECEIVER
3. If interrupts are desired, then set enable bit
RCIE.
The receiver block diagram is shown in Figure 9-6.The
data is received on the RC7/RX/DT pin and drives the
data recovery block.The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 9.1).
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR register
LSb
MSb
or
÷ 16
0
Baud Rate Generator
1
7
Stop (8)
Start
•
• •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 9-7: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS30605A-page 68
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 9-7:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(2)
0Ch
PIR1
RCIF
SREN
RCREG USART Receive Register
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PSPIF
ADIF
RX9
18h
1Ah
8Ch
RCSTA SPEN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
(1)
(2)
PIE1
TXSTA CSRC
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIE
ADIE
TX9
98h
99h
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
1998 Microchip Technology Inc.
DS30605A-page 69
PIC16C63A/65B/73B/74B
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register.While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
9.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
Steps to follow when setting up a Synchronous Master
Transmission:
9.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
1. Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
The USART transmitter block diagram is shown in
Figure 9-3. The heart of the transmitter is the transmit
(serial) shift register (TSR).The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
TABLE 9-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 0000
0000 0000
(1)
(2)
0Ch
PIR1
RCSTA SPEN
TXREG USART Transmit Register
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
— FERR OERR RX9D
PSPIF
ADIF
0000 -00x
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
18h
19h
8Ch
RX9
SREN CREN
(1)
(2)
PIE1
TXSTA CSRC
RCIE TXIE
TXEN SYNC
SSPIE CCP1IE TMR2IE TMR1IE
— BRGH TRMT TX9D
PSPIE
ADIE
TX9
0000 -010
0000 0000
0000 -010
0000 0000
98h
99h
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
DS30605A-page 70
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 9-8: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
WORD 2
Bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT bit
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
'1'
TXEN bit
FIGURE 9-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
1998 Microchip Technology Inc.
DS30605A-page 71
PIC16C63A/65B/73B/74B
9.3.2
USART SYNCHRONOUS MASTER
RECEPTION
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Master
Reception:
9. Read the 8-bit received data by reading the
RCREG register.
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 9.1)
10. If any error occurred, clear the error by clearing
bit CREN.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
TABLE 9-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 0000
0000 0000
(1)
(2)
0Ch
PIR1
RCSTA SPEN
RCREG USART Receive Register
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
— FERR OERR RX9D
PSPIF
ADIF
0000 -00x
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
18h
1Ah
8Ch
RX9
SREN CREN
(1)
(2)
PIE1
RCIE TXIE
TXEN SYNC
SSPIE CCP1IE TMR2IE TMR1IE
— BRGH TRMT TX9D
PSPIE
CSRC
ADIE
TX9
0000 -010
0000 0000
0000 -010
0000 0000
98h
99h
TXSTA
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Allways maintain these bits clear.
FIGURE 9-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
DS30605A-page 72
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
9.4.2
USART SYNCHRONOUS SLAVE
RECEPTION
9.4
USART Synchronous Slave Mode
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode and bit SREN, which is a "don't care" in slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
9.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a) The first word will immediately transfer to the
TSR register and transmit.
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, then set enable bit
RCIE.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
5. Flag bit RCIF will be set when reception is com-
plete. An interrupt will be generated if enable bit
RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
1998 Microchip Technology Inc.
DS30605A-page 73
PIC16C63A/65B/73B/74B
TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 0000
0000 0000
(1)
(2)
0Ch
PIR1
RCSTA SPEN
TXREG USART Transmit Register
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
— FERR OERR RX9D
PSPIF
ADIF
0000 -00x
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
18h
19h
8Ch
RX9
SREN CREN
(1)
(2)
PIE1
TXSTA CSRC
RCIE TXIE
TXEN SYNC
SSPIE CCP1IE TMR2IE TMR1IE
— BRGH TRMT TX9D
PSPIE
ADIE
TX9
0000 -010
0000 0000
0000 -010
0000 0000
98h
99h
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 0000
0000 0000
(1)
(2)
0Ch
PIR1
RCSTA SPEN
RCREG USART Receive Register
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
— FERR OERR RX9D
PSPIF
ADIF
0000 -00x
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
18h
1Ah
8Ch
RX9
SREN CREN
(1)
(2)
PIE1
RCIE TXIE
TXEN SYNC
SSPIE CCP1IE TMR2IE TMR1IE
— BRGH TRMT TX9D
PSPIE
CSRC
ADIE
TX9
0000 -010
0000 0000
0000 -010
0000 0000
98h
99h
TXSTA
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.
DS30605A-page 74
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Additional information on the A/D module is available in
10.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
the PICmicro
(DS33023).
Mid-Range Reference Manual,
This section applies to the PIC16C73B and
PIC16C74B only.The analog-to-digital (A/D) converter
module has five inputs for the PIC16C73B, and eight for
the PIC16C74B.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the device’s positive supply voltage (VDD)
or the voltage level on the RA3/AN3/VREF pin.
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off and any
conversion is aborted.
The ADCON0 register, shown in Figure 10-1, controls
the operation of the A/D module. The ADCON1 regis-
ter, shown in Figure 10-2, configures the functions of
the port pins. The port pins can be configured as ana-
log inputs (RA3 can also be a voltage reference) or as
digital I/O.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode.To oper-
ate in sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
FIGURE 10-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2
bit7
R/W-0
CHS1
R/W-0
R/W-0
U-0
—
R/W-0
ADON
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an internal RC oscillator)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion
is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
1998 Microchip Technology Inc.
DS30605A-page 75
PIC16C63A/65B/73B/74B
FIGURE 10-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
bit7
bit0
U =Unimplemented
bit, read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
RA0
RA1
RA2
RA5
RA3
VREF
VDD
000
001
010
011
100
101
11x
A
A
A
A
A
A
A
A
A
A
D
A
A
A
A
A
D
A
A
A
D
D
D
A
A
A
D
D
D
VREF
A
RA3
VDD
RA3
VDD
RA3
VDD
VREF
A
VREF
D
A = Analog input
D = Digital I/O
DS30605A-page 76
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 10-3.
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
4. Start conversion:
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 10.1.
After this acquisition time has elapsed the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
OR
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
FIGURE 10-3: A/D BLOCK DIAGRAM
CHS2:CHS0
111
(1)
RE2/AN7
110
(1)
RE1/AN6
101
(1)
RE0/AN5
100
RA5/AN4
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
100
VREF
(Reference
voltage)
001or
011or
101
PCFG2:PCFG0
Note 1: Available on the PIC16C74B only.
1998 Microchip Technology Inc.
DS30605A-page 77
PIC16C63A/65B/73B/74B
To calculate the minimum acquisition time, TACQ, see
the PICmicro Mid-Range Reference Manual,
(DS33023). This equation calculates the acquisition
time to within 1/2 LSb error (512 steps for the A/D).The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified accuracy.
10.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 10-4.The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD). The
source impedance affects the offset voltage at the ana-
log input (due to pin leakage current). The maximum
recommended impedance for analog sources is 10
kΩ. After the analog input channel is selected
(changed) this acquisition must be done before the
conversion can be started.
Note: When the conversion is started, the hold-
ing capacitor is disconnected from the
input pin.
FIGURE 10-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5
6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30605A-page 78
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
10.2
Selecting the A/D Conversion Clock
10.3
Configuring Analog Port Pins
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
The ADCON1, TRISA, and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
• 2TOSC
• 8TOSC
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 32TOSC
• Internal RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
Table 10-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins) may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 10-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Device Frequency
Operation ADCS1:ADCS0
20 MHz
5 MHz
1.25 MHz
1.6 µs
333.33 kHz
(2)
(2)
2TOSC
8TOSC
32TOSC
00
01
10
11
6 µs
100 ns
400 ns
(2)
(3)
1.6 µs
6.4 µs
400 ns
24 µs
(3)
(3)
1.6 µs
6.4 µs
25.6 µs
96 µs
(5)
(1,4)
(1,4)
(1,4)
(1)
RC
2 - 6 µs
2 - 6 µs
2 - 6 µs
2 - 6 µs
Legend: Shaded cells are outside of recommended range.
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for
sleep operation only.
5: For extended voltage devices (LC), please refer to Electrical Specifications section.
1998 Microchip Technology Inc.
DS30605A-page 79
PIC16C63A/65B/73B/74B
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
10.4
A/D Conversions
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10.5
Use of the CCPTrigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 10-2: SUMMARY OF A/D REGISTERS
Value on
POR,
Value on all
other
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
Resets
INTCON
PIR1
GIE
PEIE
ADIF
ADIE
—
T0IE
RCIF
RCIE
—
INTE
TXIF
TXIE
—
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Bh,8Bh
0Ch
(1)
PSPIF
PSPIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
PIE1
8Ch
PIR2
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
CCP2IE ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
0Dh
PIE2
—
—
—
—
8Dh
ADRES
A/D Result Register
1Eh
ADCON0 ADCS1 ADCS0 CHS2
CHS1
CHS0 GO/DON
E
—
ADON 0000 00-0 0000 00-0
1Fh
ADCON1
—
—
—
—
—
—
—
PCFG2
PCFG1 PCFG0 ---- -000 ---- -000
9Fh
05h
85h
09h
89h
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTA
TRISA
PORTE
TRISE
RA5
RA4
RA3
RA2
RA1
RA0
—
—
—
—
PORTA Data Direction Register
—
—
—
—
RE2
RE1
RE0
IBF
OBF
IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73B. Always maintain these bits clear.
DS30605A-page 80
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
other is the Power-up Timer (PWRT), which provides a
fixed delay on power-up only, designed to keep the part
in reset while the power supply stabilizes. With these
two timers on-chip, most applications need no external
reset circuitry.
11.0 SPECIAL FEATURES OF THE
CPU
The PIC16C63A/65B/73B/74B devices have a host of
features intended to maximize system reliability, mini-
mize cost through elimination of external components,
provide power saving operating modes and offer code
protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode.The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost, while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
• OSC Selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Additional information on special features is available in
the PICmicro
(DS33023).
Mid-Range Reference Manual,
• Watchdog Timer (WDT)
• SLEEP
11.1
Configuration Bits
• Code protection
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• ID locations
• In-circuit serial programming
These devices have a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable.The
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
FIGURE 11-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 CP1 CP0
bit13
—
BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0
bit0
Register:CONFIG
Address2007h
(2)
bit 13-8 CP1:CP0: Code Protection bits
5-4: 11= Code protection off
10= Upper half of program memory code protected
01= Upper 3/4th of program memory code protected
00= All memory is code protected
bit 7:
bit 6:
Unimplemented: Read as '1'
(1)
BODEN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
1998 Microchip Technology Inc.
DS30605A-page 81
PIC16C63A/65B/73B/74B
11.2
Oscillator Configurations
TABLE 11-1: CERAMIC RESONATORS
Ranges Tested:
11.2.1 OSCILLATOR TYPES
The PIC16CXXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
Mode
XT
Freq
OSC1
OSC2
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See
notes at bottom of page.
High Speed Crystal/Resonator
Resistor/Capacitor
Resonators Used:
11.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
± 0.5%
± 0.5%
± 0.5%
± 0.5%
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 11-2). The
PIC16CXXX oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 11-3).
All resonators used did not have built-in capacitors.
TABLE 11-2: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
Osc Type
FIGURE 11-2: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
OSC CONFIGURATION)
(1)
C1
4 MHz
15 pF
15 pF
OSC1
4 MHz
15 pF
15 pF
To
internal
logic
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
XTAL
(3)
RF
20 MHz
OSC2
These values are for design guidance only. See
notes at bottom of page.
SLEEP
PIC16CXXX
(2)
RS
(1)
C2
Crystals Used
32 kHz
200 kHz
1 MHz
Epson C-001R32.768K-A
STD XTL 200.000KHz
ECS ECS-10-13-1
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
± 30 PPM
Note1: See Table 11-1 and Table 11-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
3: RF varies with the crystal chosen.
4 MHz
ECS ECS-40-20-1
8 MHz
EPSON CA-301 8.000M-C
EPSON CA-301 20.000M-C
20 MHz
FIGURE 11-3: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 11-1).
2: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16CXXX
3: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
Open
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
DS30605A-page 82
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.2.3 RC OSCILLATOR
11.3
Reset
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 11-4 shows how the R/C combina-
tion is connected to the PIC16CXXX.
The PIC16CXXX differentiates between various kinds
of reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation.The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
Table 11-4. These bits are used in software to deter-
mine the nature of the reset. See Table 11-6 for a full
description of reset states of all registers.
FIGURE 11-4: RC OSCILLATOR MODE
VDD
Rext
Internal
OSC1
clock
Cext
VSS
PIC16CXXX
A simplified block diagram of the on-chip reset circuit is
shown in Figure 11-5.
OSC2/CLKOUT
Fosc/4
The PICmicros have a MCLR noise filter in the MCLR
reset path.The filter will detect and ignore small pulses.
Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ
Cext > 20pF
It should be noted that a WDT Reset does not drive
MCLR pin low.
1998 Microchip Technology Inc.
DS30605A-page 83
PIC16C63A/65B/73B/74B
FIGURE 11-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
10-bit Ripple counter
Chip_Reset
Q
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
DS30605A-page 84
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.4
Power-On Reset (POR)
11.5
Power-up Timer (PWRT)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD.This will eliminate
external RC components usually needed to create a
Power-on Reset. A maximum rise time for VDD is spec-
ified (parameter D004). For a slow rise time, see
Figure 11-6.
The Power-up Timer provides a fixed nominal time-out
(parameter #33) on power-up only, from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in reset as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/dis-
able the PWRT.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature,...) must be met to ensure oper-
ation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the start-up con-
ditions.
11.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32).This ensures that
the crystal oscillator or resonator has started and sta-
bilized.
FIGURE 11-6: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
VDD
11.7
Brown-Out Reset (BOR)
D
R
A configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A reset may not occur if VDD falls below
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
BVDD.The Power-up Timer will then be invoked and will
keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initial-
ized. Once VDD rises above BVDD, the Power-up Timer
will execute the additional time delay. The Power-up
Timer should always be enabled when Brown-out
Reset is enabled.
R1
MCLR
PIC16CXXX
C
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow.The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
1998 Microchip Technology Inc.
DS30605A-page 85
PIC16C63A/65B/73B/74B
11.8
Time-out Sequence
11.9
Power Control/Status Register
(PCON)
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay has
expired. Then OST is activated. The total time-out will
vary based on oscillator configuration and the status of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 11-7,
Figure 11-8, Figure 11-9 and Figure 11-10 depict time-
out sequences on power-up.
The Power Control/Status Register, PCON, has up to
two bits, depending upon the device.
Bit0 is Brown-out Reset Status bit, BOR. If the BODEN
configuration bit is set, BOR is ’1’ on Power-on Reset.
If the BODEN configuration bit is clear, BOR is
unknown on Power-on Reset.
The BOR status bit is a "don't care" and is not neces-
sarily predictable if the brown-out circuit is disabled (the
BODEN configuration bit is clear). BOR must then be
set by the user and checked on subsequent resets to
see if it is clear, indicating a brown-out has occurred.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 11-9). This is useful for testing purposes or to
synchronize more than one PIC16CXXX device operat-
ing in parallel.
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Table 11-5 shows the reset conditions for some special
function registers, while Table 11-6 shows the reset
conditions for all the registers.
TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up from
Oscillator Configuration
Brown-out
SLEEP
PWRTE = 0
72 ms + 1024TOSC
72 ms
PWRTE = 1
XT, HS, LP
RC
1024TOSC
—
72 ms + 1024TOSC
72 ms
1024TOSC
—
TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
000h
000h
PC + 1
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Brown-out Reset
(1)
Interrupt wake-up from SLEEP
PC + 1
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
DS30605A-page 86
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
W
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
(2)
PC + 1
(3)
(3)
STATUS
FSR
63A 65B 73B 74B
0001 1xxx
000q quuu
uuuq quuu
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
--0x 0000
uuuu uuuu
--0u 0000
uuuu uuuu
--uu uuuu
(4)
PORTA
PORTB
(5)
(5)
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
PORTC
PORTD
(5)
(5)
PORTE
PCLATH
INTCON
63A 65B 73B 74B
63A 65B 73B 74B
---0 0000
0000 000x
---0 0000
0000 000u
(1)
uuuu uuuu
(1)
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
--00 0000
-000 0000
0-00 0000
0000 0000
---- ---0
--00 0000
-000 0000
0-00 0000
0000 0000
---- ---0
--uu uuuu
(1)
-uuu uuuu
PIR1
PIR2
(1)
u-uu uuuu
(1)
uuuu uuuu
(1)
---- ---u
TMR1L
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
Legend: u = unchanged,
x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
1998 Microchip Technology Inc.
DS30605A-page 87
PIC16C63A/65B/73B/74B
TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
ADRES
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
63A 65B 73B 74B
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
0000 -000
--00 0000
0-00 0000
-000 0000
0000 0000
---- ---0
---- --0q
1111 1111
0000 0000
0000 0000
0000 -010
0000 0000
---- -000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
0000 -000
--00 0000
0-00 0000
-000 0000
0000 0000
---- ---0
---- --uq
1111 1111
0000 0000
0000 0000
0000 -010
0000 0000
---- -000
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu -uuu
--uu uuuu
u-uu uuuu
-uuu uuuu
uuuu uuuu
---- ---u
---- --uq
1111 1111
uuuu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- -uuu
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Legend: u = unchanged,
x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 11-5 for reset value for specific condition.
4: On any device reset, these pins are configured as inputs.
5: This is the value that will be in the port output latch.
FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30605A-page 88
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 11-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 11-10: SLOW RISE TIME (MCLRTIED TO VDD)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1998 Microchip Technology Inc.
DS30605A-page 89
PIC16C63A/65B/73B/74B
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
11.10 Interrupts
The PIC16CXX family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2.The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A
global interrupt enable bit, GIE (INTCON<7>)
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 11-11: INTERRUPT LOGIC
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
DS30605A-page 90
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
11.10.1 INT INTERRUPT
11.11 Context Saving During Interrupts
External interrupt on RB0/INT pin is edge triggered;
either rising if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP.The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 11.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack.Typically, users may wish to save key reg-
isters during an interrupt, i.e., W register and STATUS
register. This will have to be implemented in software.
Example 11-1 stores and restores the W and STATUS
registers. The register, W_TEMP, must be defined in
each bank and must be defined at the same offset from
the bank base address (i.e., if W_TEMP is defined at
0x20 in bank 0. It must also be defined at 0xA0 in bank
1).
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register.
11.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 4.0)
d) Executes the interrupt service routine code
(User-generated).
e) Restores the STATUS register (and bank select
bit).
f) Restores the W and PCLATH registers.
11.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
MOVF
MOVWF
:
FSR_TEMP
;Copy FSR from W to FSR_TEMP
:(ISR)
:
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
1998 Microchip Technology Inc.
DS30605A-page 91
PIC16C63A/65B/73B/74B
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
11.12 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEPinstruction.
Note: The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
During normal operation, a WDT time-out generates a
.
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up).The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 11.1).
FIGURE 11-12: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 4-2)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 4-2)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
FIGURE 11-13: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
(1)
(1)
Config. bits
OPTION_REG
CP1
CP0
BODEN
PWRTE
PSA
RBPU
INTEDG
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 11-1 for operation of these bits.
DS30605A-page 92
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
11.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
11.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
11.13.1 WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The device can wake up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will immedi-
ately wake up from sleep. The SLEEPinstruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked.The TO bit
is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes.To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEPinstruction was
executed as a NOP.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write.
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP capture mode interrupt.
4. Special event trigger (Timer1 in asynchronous
mode using an external clock).
5. SSP (Start/Stop) bit detect interrupt.
2
6. SSP transmit or receive in slave mode (SPI/I C).
7. USART RX or TX (synchronous slave mode).
8. A/D conversion (when A/D clock source is RC).
1998 Microchip Technology Inc.
DS30605A-page 93
PIC16C63A/65B/73B/74B
FIGURE 11-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
11.14 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip Technology does not recom-
mend code protecting windowed devices.
11.15 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
11.16 In-Circuit Serial Programming
PIC16CXXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming volt-
age.This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277B).
DS30605A-page 94
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Table 12-2 lists the instructions recognized by the
MPASM assembler.
12.0 INSTRUCTION SET SUMMARY
Each PIC16CXXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 12-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 12-1
shows the opcode field descriptions.
Figure 12-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXXX products, do not use
the OPTIONand TRISinstructions.
All examples use the following format to represent a
hexadecimal number:
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
0xhh
where h signifies a hexadecimal digit.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
FIGURE 12-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
0
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
OPCODE
d
f (FILE #)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
Bit-oriented file register operations
13 10 9
b (BIT #)
TABLE 12-1: OPCODE FIELD
DESCRIPTIONS
7
6
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Field
Description
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Literal and control operations
Bit address within an 8-bit file register
Literal field, constant data or label
General
Don't care location (= 0 or 1)
13
8
7
0
0
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip Technology software tools.
OPCODE
k (literal)
k = 8-bit immediate value
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
PC
TO
PD
Program Counter
Time-out bit
k (literal)
Power-down bit
The instruction set is highly orthogonal and is grouped
into three basic categories:
A description of each instruction is available in the
PICmicro
Mid-Range
Reference
Manual,
• Byte-oriented operations
• Bit-oriented operations
(DS33023).
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
1998 Microchip Technology Inc.
DS30605A-page 95
PIC16C63A/65B/73B/74B
TABLE 12-2: PIC16CXXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
Z
00 0000 0110 0100 TO,PD
10 1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
00 0000 0110 0011 TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30605A-page 96
1998 Microchip Technology Inc.
PIC16C62X(A)
13.3
ICEPIC: Low-Cost PICmicro™
In-Circuit Emulator
13.0 DEVELOPMENT SUPPORT
13.1
Development Tools
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC12CXXX, PIC16C5X and PIC16CXXX
families of 8-bit OTP microcontrollers.
The PICmicrο microcontrollers are supported with a
full range of hardware and software development tools:
• PICMASTER /PICMASTER CE Real-Time
In-Circuit Emulator
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
13.4
PRO MATE II: Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE II can read, verify or pro-
• MPLAB SIM Software Simulator
• MPLAB-C17 (C Compiler)
• Fuzzy Logic Development System
(fuzzyTECH −MP)
13.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
gram
PIC12CXXX,
PIC14C000,
PIC16C5X,
PIC16CXXX and PIC17CXX devices. It can also set
configuration and code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC14C000, PIC12CXXX,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
13.5
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use,
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip micro-
controllers.
PICSTART Plus supports all PIC12CXXX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923, PIC16C924 and PIC17C756 may be sup-
ported with an adapter socket. PICSTART Plus is CE
compliant.
The PICMASTER Emulator System has been
designed as
a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these fea-
tures available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
1998 Microchip Technology Inc.
DS30605A-page 97
PIC16C62X(A)
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
13.6
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
13.9
MPLAB™ Integrated Development
Environment Software
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
13.7
PICDEM-2 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
13.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
13.10 Assembler (MPASM)
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
The MPASM Universal Macro Assembler is
a
PC-hosted symbolic assembler. It supports all micro-
controller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator System.
DS30605A-page 98
1998 Microchip Technology Inc.
PIC16C62X(A)
MPASM has the following features to assist in develop-
ing software for specific use applications.
13.14 MP-DriveWay – Application Code
Generator
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
MP-DriveWay is an easy-to-use Windows-based Appli-
cation Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PICmicro
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Micro-
chip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PICmicro. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
13.15 SEEVAL Evaluation and
Programming System
13.11 Software Simulator (MPLAB-SIM)
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PICmicro series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The
input/output radix can be set by the user and the exe-
cution can be performed in; single step, execute until
break, or in a trace mode.
The Total Endurance
Disk is included to aid in
trade-off analysis and reliability calculations. The total
kit can significantly reduce time-to-market and result in
an optimized system.
13.16 KEELOQ Evaluation and
Programming Tools
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code out-
side of the laboratory environment making it an excel-
lent multi-project software development tool.
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products.The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
13.12 C Compiler (MPLAB-C17)
The MPLAB-C Code Development System is
a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC17CXXX family of
microcontrollers. The compiler provides powerful inte-
gration capabilities and ease of use not found with
other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
MPLAB IDE memory display.
13.13 Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, Edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
1998 Microchip Technology Inc.
DS30605A-page 99
PIC16C62X(A)
TABLE 13-1
DEVELOPMENT TOOLS FROM MICROCHIP
ufzy
DS30605A-page 100
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.0 ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Ambient temperature under bias............................................................................................................ .-55˚C to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V
Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) .............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE not available on the PIC16C63A/73B.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device.This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 14-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR MODES AND
FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C63A-04
PIC16C65B-04
PIC16C73B-04
PIC16C74B-04
PIC16C63A-20
PIC16C65B-20
PIC16C73B-20
PIC16C74B-20
PIC16LC63A-04
PIC16LC65B-04
PIC16LC73B-04
PIC16LC74B-04
OSC
Windowed (JW) Devices
RC
VDD: 4.0V to 5.5V
VDD: 4.5V to 5.5V
VDD: 2.5V to 5.5V
VDD: 2.5V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
XT
HS
VDD: 4.0V to 5.5V
VDD: 4.5V to 5.5V
VDD: 2.5V to 5.5V
VDD: 2.5V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
IDD: 20 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
VDD: 2.5V to 5.5V
Not recommended for use in
HS mode
LP
VDD: 4.0V to 5.5V
IDD: 52.5 µA typ.
at 32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
VDD: 2.5V to 5.5V
IDD: 48 µA max. at 32 kHz, IDD: 48 µA max. at 32 kHz,
Not recommended for use in
LP mode
3.0V
3.0V
IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom-
mended that the user select the device type that ensures the specifications required.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 101
PIC16C63A/65B/73B/74B
14.1
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
DC CHARACTERISTICS
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
D001A
VDD
Supply Voltage
4.0
4.5
VBOR*
-
-
-
5.5
5.5
5.5
V
V
V
XT, RC and LP osc mode
HS osc mode
BOR enabled (Note 7)
D002*
D003
VDR
RAM Data Retention
Voltage (Note 1)
-
1.5
-
V
VPOR VDD Start Voltage to
ensure internal
-
VSS
-
V
See section on Power-on Reset for details
Power-on Reset signal
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
0.05
TBD
-
-
-
-
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
Power-on Reset signal
See section on Power-on Reset for details
D005
D010
VBOR Brown-out Reset
3.65
-
-
4.35
5
V
BODEN bit set
voltage trip point
IDD
IPD
Supply Current
(Note 2, 5)
2.7
mA XT, RC osc modes
FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
D020
-
10
20
mA HS osc mode
FOSC = 20 MHz, VDD = 5.5V
Power-down Current
-
-
-
-
10.5
1.5
1.5
2.5
42
16
19
19
µA VDD = 4.0V, WDT enabled,-40°C to +85°C
µA VDD = 4.0V, WDT disabled, 0°C to +70°C
µA VDD = 4.0V, WDT disabled,-40°C to +85°C
µA VDD = 4.0V, WDT disabled,-40°C to +125°C
(Note 3, 5)
D021
D021B
Module Differential
Current (Note 6)
D022*
∆IWDT Watchdog Timer
-
-
6.0
350
20
425
µA WDTE bit set, VDD = 4.0V
µA BODEN bit set, VDD = 5.0V
D022A* ∆IBOR Brown-out Reset
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated.These parameters are for design guidance only
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included.The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30605A-page 102
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.2
DC Characteristics: PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
D002*
D003
VDD
Supply Voltage
2.5
VBOR*
-
-
5.5
5.5
V
V
LP, XT, RC osc modes (DC - 4 MHz)
BOR enabled (Note 7)
VDR
RAM Data Retention
Voltage (Note 1)
-
-
1.5
-
V
VPOR VDD Start Voltage to
ensure internal
VSS
-
V
See section on Power-on Reset for details
Power-on Reset signal
D004*
D004A*
SVDD VDD Rise Rate to
ensure internal
0.05
TBD
-
-
-
-
V/ms PWRT enabled (PWRTE bit clear)
PWRT disabled (PWRTE bit set)
Power-on Reset signal
See section on Power-on Reset for details
D005
D010
VBOR Brown-out Reset
3.65
-
-
4.35
3.8
V
BODEN bit set
voltage trip point
IDD
IPD
Supply Current
(Note 2, 5)
2.0
mA XT, RC osc modes
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
-
22.5
48
µA LP osc mode
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
Power-down Current
-
-
-
7.5
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
(Note 3, 5)
Module Differential
Current (Note 6)
D022*
∆IWDT Watchdog Timer
-
-
6.0
350
20
425
µA WDTE bit set, VDD = 4.0V
µA BODEN bit set, VDD = 5.0V
D022A* ∆IBOR Brown-out Reset
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated.These parameters are for design guidance only
and are not tested.
Note1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc mode, current through Rext is not included.The current through the resistor can be estimated by
the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached..
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 103
PIC16C63A/65B/73B/74B
14.3
DC Characteristics:
PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended)
PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended)
PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 14.1
and Section 14.2
Param Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
D030A
D031
D032
D033
with TTL buffer
VSS
VSS
VSS
Vss
Vss
-
-
-
-
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP
modes)
Note1
Input High Voltage
I/O ports
VIH
-
-
-
D040
D040A
with TTL buffer
2.0
0.25VDD
+ 0.8V
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
D041
D042
D042A
D043
with Schmitt Trigger buffer 0.8VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
For entire VDD range
Note1
MCLR
0.8VDD
OSC1 (XT, HS and LP modes) 0.7VDD
OSC1 (in RC mode)
Input Leakage Current (Notes
2, 3)
0.9VDD
D060
IIL
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD,
XT, HS and LP osc modes
µA VDD = 5V, VPIN = VSS
D070
D080
IPURB PORTB weak pull-up current
50
-
250
400
0.6
0.6
0.6
0.6
Output Low Voltage
I/O ports
VOL
-
-
-
-
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
-
D083
OSC2/CLKOUT (RC osc
mode)
-
-
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-
cro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
DS30605A-page 104
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 14.1
and Section 14.2
Param Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Output High Voltage
D090
VOH
I/O ports (Note 3)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
-
-
-
-
-
-
-
V
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
-
-
D092
OSC2/CLKOUT (RC osc
mode)
-
D150* VOD
Open-Drain High Voltage
Capacitive Loading Specs
on Output Pins
8.5
RA4 pin
D100
COSC2 OSC2 pin
-
-
15
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
D102
CIO
Cb
All I/O pins and OSC2 (in RC
mode)
-
-
-
-
50
pF
2
400
pF
SCL, SDA in I C mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-
cro be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
ages.
3: Negative current is defined as current sourced by the pin.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 105
PIC16C63A/65B/73B/74B
14.4
AC (Timing) Characteristics
14.4.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created fol-
lowing one of the following formats:
2
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
DS30605A-page 106
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
14.4.2 TIMING CONDITIONS
The temperature and voltages specified in Table 14-1
apply to all timing specifications unless otherwise
noted. Figure 14-1 specifies the load conditions for the
timing specifications.
TABLE 14-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0˚C ≤ TA ≤ +70˚C for commercial
-40˚C ≤ TA ≤ +85˚C for industrial
-40˚C ≤ TA ≤ +125˚C for extended
AC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2.
LC parts operate for commercial/industrial temp’s only.
FIGURE 14-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1 Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
but including D and E outputs as ports
VSS
Note1: PORTD and PORTE are not imple-
mented on the PIC16C63A/73B.
15 pF for OSC2 output
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 107
PIC16C63A/65B/73B/74B
14.4.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 14-2: EXTERNAL CLOCK TIMING
Q1
1
Q2
Q3
Q4
4
Q4
Q1
OSC1
3
3
4
2
CLKOUT
TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
1A
Fosc External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz RC and XT osc modes
MHz HS osc mode (-04)
MHz HS osc mode (-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
20
200
—
MHz HS osc mode
5
kHz LP osc mode
1
Tosc
External CLKIN Period
250
250
50
ns
ns
ns
µs
ns
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
RC and XT osc modes
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
(Note 1)
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
50
—
RC osc mode
XT osc mode
10,000
250
250
—
HS osc mode (-04)
HS osc mode (-20)
LP osc mode
5
2
TCY
Instruction Cycle Time (Note 1)
200
100
2.5
15
DC
—
TCY = 4/FOSC
3*
TosL,
TosH
External Clock in (OSC1) High or
Low Time
XT oscillator
—
LP oscillator
—
HS oscillator
4*
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
—
25
50
15
XT oscillator
—
LP oscillator
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30605A-page 108
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
—
—
200
200
100
100
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
—
12*
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
13*
—
14*
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
0.5TCY + 20 ns
15*
Tosc + 200
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
17*
TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
150
—
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input Standard
100
200
0
invalid (I/O in hold time)
18A*
19*
Extended (LC)
—
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
—
20*
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard
—
40
80
40
80
—
20A*
21*
Extended (LC)
Standard
—
TioF
—
21A*
Extended (LC)
—
22††* Tinp
23††* Trbp
TCY
TCY
RB7:RB4 change INT high or low time
—
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 109
PIC16C63A/65B/73B/74B
FIGURE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 14-1 for load conditions.
FIGURE 14-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2
7
—
—
µs VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
33*
34
Tost
Oscillation Start-up Timer Period
—
28
—
1024 TOSC
—
132
2.1
—
ms
µs
TOSC = OSC1 period
Tpwrt Power-up Timer Period
72
—
VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR
Low or WDT reset
35
TBOR
Brown-out Reset Pulse Width
100
—
—
VDD ≤ BVDD (D005)
µs
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 110
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
0.5TCY + 20
—
—
ns Must also meet
parameter 42
With Prescaler
No Prescaler
10
0.5TCY + 20
10
—
—
—
—
—
—
—
—
—
—
ns
41*
42*
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
With Prescaler
No Prescaler
With Prescaler
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4,..., 256)
N
0.5TCY + 20
15
45*
46*
47*
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, Prescaler = 1
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
ns
ns
Standard
25
Extended (LC)
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
Standard
50
Extended (LC)
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler =
2,4,8
15
25
ns
ns
Standard
Extended (LC)
Asynchronous
30
50
—
—
—
—
—
—
ns
ns
Standard
Extended (LC)
Standard
T1CKI input period Synchronous
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
Extended (LC)
Asynchronous
60
—
—
—
—
—
ns
ns
Standard
100
DC
Extended (LC)
Ft1
Timer1 oscillator input frequency range
200
kHz
(oscillator enabled by setting bit T1OSCEN)
48
*
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 111
PIC16C63A/65B/73B/74B
FIGURE 14-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
50*
TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
With Prescaler Standard
10
Extended (LC)
20
51*
TccH
No Prescaler
With Prescaler Standard
0.5TCY + 20
CCP1 and CCP2
input high time
10
20
Extended (LC)
52*
53*
TccP
3TCY + 40
N
ns N = prescale value
(1,4, or 16)
CCP1 and CCP2 input period
TccR CCP1 and CCP2 output rise time
TccF CCP1 and CCP2 output fall time
Standard
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
Extended (LC)
Standard
54*
Extended (LC)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 112
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-8: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
62*
63*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI WR↑ or CS↑ to data–in invalid Standard
20
20
35
—
10
—
—
—
—
—
—
—
—
80
30
ns
ns
ns
ns
ns
(hold time)
Extended (LC)
64
TrdL2dtV RD↓ and CS↓ to data–out valid
TrdH2dtI RD↑ or CS↑ to data–out invalid
65*
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 113
PIC16C63A/65B/73B/74B
FIGURE 14-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Refer to Figure 14-1 for load conditions.
TABLE 14-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71
71A
72
TscH
TscL
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
40
1.25TCY + 30
40
ns Note 1
SCK input low time
(slave mode)
ns
72A
73
ns Note 1
ns
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
100
—
—
—
—
ns Note 1
ns
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
75
TdoR
SDO data output rise time Standard
Extended (LC)
—
—
—
—
—
—
—
—
10
20
10
10
20
10
—
—
25
45
25
25
45
25
50
100
ns
ns
ns
ns
ns
ns
ns
ns
76
78
TdoF
TscR
SDO data output fall time
SCK output rise time
(master mode)
Standard
Extended (LC)
79
80
TscF
SCK output fall time (master mode)
TscH2doV, SDO data output valid
TscL2doV after SCK edge
Standard
Extended (LC)
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605A-page 114
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Refer to Figure 14-1 for load conditions.
TABLE 14-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
71
TscH
TscL
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
71A
72
40
1.25TCY + 30
40
ns Note 1
SCK input low time
(slave mode)
ns
72A
73
ns Note 1
ns
TdiV2scH, Setup time of SDI data input to SCK
100
TdiV2scL
edge
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns Note 1
ns
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise
time
Standard
10
20
10
10
20
10
—
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Extended (LC)
76
78
TdoF
TscR
SDO data output fall time
—
—
SCK output rise time
(master mode)
Standard
Extended (LC)
79
80
TscF
SCK output fall time (master mode)
—
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
Standard
Extended (LC)
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 115
PIC16C63A/65B/73B/74B
FIGURE 14-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Refer to Figure 14-1 for load conditions.
TABLE 14-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71
71A
72
TscH
TscL
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
40
1.25TCY + 30
40
ns Note 1
SCK input low time
(slave mode)
ns
72A
73
ns Note 1
ns
TdiV2scH, Setup time of SDI data input to SCK edge
TdiV2scL
100
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns Note 1
ns
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
TdoR
SDO data output rise time Standard
Extended (LC)
10
20
10
—
10
20
10
—
—
—
25
45
25
50
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
76
77
78
TdoF
SDO data output fall time
—
10
—
TssH2doZ SS↑ to SDO output hi-impedance
TscR
SCK output rise time
(master mode)
Standard
Extended (LC)
79
80
TscF
SCK output fall time (master mode)
—
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
Standard
Extended (LC)
83
†
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
DS30605A-page 116
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
FIGURE 14-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Refer to Figure 14-1 for load conditions.
TABLE 14-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param.
Symbol Characteristic
Min
Typ† Max Units Conditions
No.
70
TssL2scH, SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
TssL2scL
71
71A
72
TscH
TscL
TB2B
SCK input high time
(slave mode)
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
40
—
—
—
—
—
—
—
—
—
—
ns
ns Note 1
ns
SCK input low time
(slave mode)
1.25TCY + 30
40
72A
73A
ns Note 1
ns Note 1
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
74
75
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
—
—
ns
TdoR
SDO data output rise
time
Standard
10
20
10
—
10
20
10
—
—
—
—
—
25
45
25
50
25
45
25
50
100
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Extended (LC)
76
77
78
TdoF
SDO data output fall time
—
TssH2doZ SS↑ to SDO output hi-impedance
10
TscR
SCK output rise time
(master mode)
Standard
—
Extended (LC)
—
79
80
TscF
SCK output fall time (master mode)
—
TscH2doV, SDO data output valid
TscL2doV after SCK edge
Standard
—
Extended (LC)
Standard
—
82
TssL2doV SDO data output valid
—
—
after SS↓ edge
Extended (LC)
83
†
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5TCY + 40
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: Specification 73A is only required if specifications 71A and 72A are used.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 117
PIC16C63A/65B/73B/74B
2
FIGURE 14-13: I C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 14-1 for load conditions.
2
TABLE 14-12: I C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90*
91*
92*
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated START
condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
*
These parameters are characterized but not tested.
DS30605A-page 118
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
2
FIGURE 14-14: I C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 14-1 for load conditions.
2
TABLE 14-13: I C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100*
THIGH
Clock high time
100 kHz mode
400 kHz mode
4.0
0.6
—
—
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101*
TLOW
Clock low time
100 kHz mode
µs
µs
Device must operate at a mini-
mum of 1.5 MHz
400 kHz mode
1.3
—
Device must operate at a mini-
mum of 10 MHz
SSP Module
1.5TCY
—
—
102*
103*
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10-400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10-400 pF
90*
91*
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106*
107*
92*
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109*
110*
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode (400 kHz) I C-bus device can be used in a standard-mode (100 kHz) I C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
2
line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line
is released.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 119
PIC16C63A/65B/73B/74B
FIGURE 14-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 14-1 for load conditions.
122
TABLE 14-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Standard
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
120*
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
Extended (LC)
Standard
121*
Tckrf
Clock out rise time and fall time
(Master Mode)
Extended (LC)
Standard
50
122*
Tdtrf
Data out rise time and fall time
45
Extended (LC)
50
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 14-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 14-1 for load conditions.
TABLE 14-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125*
TdtV2ckL
TckL2dtl
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
15
—
—
—
—
ns
ns
126*
Data hold after CK ↓ (DT hold time)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30605A-page 120
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
TABLE 14-16: A/D CONVERTER CHARACTERISTICS:
PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED)
PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
A01
NR Resolution
—
—
—
—
—
—
—
—
—
—
—
—
8-bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A02 EABS Total Absolute error
< ± 1
< ± 1
< ± 1
< ± 1
< ± 1
LSb
LSb
LSb
LSb
LSb
A03
A04
A05
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06 EOFF Offset error
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity
—
2.5V
guaranteed
—
—
V
VSS ≤ VAIN ≤ VREF
A20 VREF Reference voltage
—
—
—
VDD + 0.3
VREF + 0.3
10.0
A25
A30
VAIN Analog input voltage
VSS - 0.3
—
V
ZAIN Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD A/D conversion current Standard
(VDD)
—
—
180
90
—
—
µA Average current consump-
tion when A/D is on.
(Note 1)
Extended (LC)
µA
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 10.1.
—
—
10
µA During A/D Conversion
cycle
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
1998 Microchip Technology Inc.
Preliminary
DS30605A-page 121
PIC16C63A/65B/73B/74B
FIGURE 14-17: A/D CONVERSION TIMING
BSF ADCON0, GO
1 Tcy
(TOSC/2) (1)
134
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This
allows the SLEEPinstruction to be executed.
TABLE 14-17: A/D CONVERSION REQUIREMENTS
Param Sym Characteristic
No.
Min
Typ†
Max
Units
Conditions
Standard
130
TAD A/D clock period
1.6
2.0
2.0
3.0
11
—
—
—
—
µs
TOSC based, VREF ≥ 3.0V
Extended (LC)
Standard
µs TOSC based, VREF full range
µs A/D RC Mode
µs A/D RC Mode
TAD
4.0
6.0
—
6.0
9.0
11
Extended (LC)
131
132
TCNV Conversion time (not including S/H time)
(Note 1)
TACQ Acquisition time
Note 2
5*
20
—
—
—
µs
µs The minimum time is the amplifier
settling time. This may be used if
the "new" input voltage has not
changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
134
135
TGO Q4 to A/D clock start
—
TOSC/2 §
—
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEPinstruction to be
executed.
TSWC Switching from convert → sample time
1.5 §
—
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
§
This specification ensured by design.
Note1: ADRES register may be read on the following TCY cycle.
2: See Section 10.1 for min conditions.
DS30605A-page 122
Preliminary
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
15.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs andTables not available at this
time.
1998 Microchip Technology Inc.
DS30605A-page 123
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 124
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.0 PACKAGING INFORMATION
16.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
AABBCDE
PIC16C73B-04/SP
9817HAT
28-Lead CERDIP Windowed
Example
XXXXXXXXXXX
PIC16C73B/JW
XXXXXXXXXXX
AABBCDE
9817CAT
28-Lead SOIC
Example
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
PIC16C73B-20/SO
9810/SAA
AABBCDE
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C73B
20I/SS025
9817SBP
AABBCAE
Legend: XX...X
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
AA
BB
C
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
1998 Microchip Technology Inc.
DS30605A-page 125
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
40-Lead PDIP
Example
PIC16C74B-04/P
9812SAA
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
AABBCDE
40-Lead CERDIP Windowed
Example
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C74B/JW
9805HAT
AABBCDE
Legend: XX...X
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
AA
BB
C
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30605A-page 126
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Package Marking Information (Cont’d)
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
PIC16C74B
-20/PT
AABBCDE
9811HAT
44-Lead MQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
PIC16C74B
-20/PQ
9804SAT
AABBCDE
44-Lead PLCC
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16C74B
-20/L
9803SAT
Legend: XX...X
Microchip part number & customer specific information*
Year code (last two digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
C = Chandler, Arizona, U.S.A.,
AA
BB
C
S = Tempe, Arizona, U.S.A. - 6”
H = Tempe, Arizona, U.S.A. - 8”
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line,
it will be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week
code, facility code, mask rev# and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
1998 Microchip Technology Inc.
DS30605A-page 127
PIC16C63A/65B/73B/74B
16.2
K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil
E
D
2
α
n
1
E1
A1
A
R
L
c
B1
β
A2
p
eB
B
Units
INCHES*
NOM
0.300
28
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
7.62
28
MAX
n
p
B
B1
R
c
0.100
0.019
0.053
0.005
0.010
0.150
0.090
0.020
0.130
1.365
0.288
0.283
0.350
10
2.54
0.016
0.022
0.41
1.02
0.48
1.33
0.13
0.25
3.81
2.29
0.51
3.30
34.67
7.30
7.18
8.89
10
0.56
†
0.040
0.000
0.008
0.140
0.070
0.015
0.125
1.345
0.280
0.270
0.320
5
0.065
0.010
0.012
0.160
0.110
0.025
0.135
1.385
0.295
0.295
0.380
15
1.65
0.25
0.30
4.06
2.79
0.64
3.43
35.18
7.49
7.49
9.65
15
0.00
0.20
3.56
1.78
0.38
3.18
34.16
7.11
6.86
8.13
5
A
A1
A2
L
D
E
E1
eB
α
‡
‡
β
5
10
15
5
10
15
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 128
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.3
K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil
E
D
W2
2
1
n
W1
E1
A
A1
R
L
c
B1
B
A2
eB
p
Units
INCHES*
NOM
0.300
28
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
MIN
MAX
MIN
NOM
7.62
28
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W1
W2
0.098
0.100
0.019
0.058
0.013
0.010
0.183
0.125
0.023
0.140
1.458
0.290
0.270
0.385
0.140
0.300
0.102
2.49
0.41
2.54
0.47
1.46
0.32
0.25
4.64
3.18
0.57
3.56
37.02
7.37
6.86
9.78
0.14
0.3
2.59
0.016
0.050
0.010
0.008
0.170
0.107
0.015
0.135
1.430
0.285
0.255
0.345
0.130
0.290
0.021
0.065
0.015
0.012
0.195
0.143
0.030
0.145
1.485
0.295
0.285
0.425
0.150
0.310
0.53
1.65
0.38
0.30
4.95
3.63
0.76
3.68
37.72
7.49
7.24
10.80
0.15
0.31
1.27
0.25
0.20
4.32
2.72
0.00
3.43
36.32
7.24
6.48
8.76
0.13
0.29
Package Width
Radius to Radius Width
Overall Row Spacing
Window Width
Window Length
*
Controlling Parameter.
1998 Microchip Technology Inc.
DS30605A-page 129
PIC16C63A/65B/73B/74B
16.4
K04-052 28-Lead Plastic Small Outline (SO) –Wide, 300 mil
E1
E
p
D
B
2
1
n
X
α
45°
L
R2
c
A
A1
φ
R1
β
L1
A2
Units
Dimension Limits
Pitch
INCHES*
NOM
0.050
28
MILLIMETERS
MIN
MAX
MIN
NOM
1.27
28
MAX
p
n
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Chamfer Distance
Shoulder Radius
Gull Wing Radius
Foot Length
A
A1
A2
0.093
0.099
0.058
0.008
0.706
0.296
0.407
0.020
0.005
0.005
0.016
4
0.104
2.36
1.22
2.50
1.47
0.19
17.93
7.51
10.33
0.50
0.13
0.13
0.41
4
2.64
0.048
0.004
0.700
0.292
0.394
0.010
0.005
0.005
0.011
0
0.068
0.011
0.712
0.299
0.419
0.029
0.010
0.010
0.021
8
1.73
0.28
18.08
7.59
10.64
0.74
0.25
0.25
0.53
8
0.10
17.78
7.42
10.01
0.25
0.13
0.13
0.28
0
‡
D
‡
E
E1
X
R1
R2
L
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.010
0.009
0.014
0
0.015
0.011
0.017
12
0.020
0.012
0.019
15
0.25
0.23
0.36
0
0.38
0.27
0.42
12
0.51
0.30
0.48
15
†
0
12
15
0
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 130
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.5
K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm
E1
E
p
D
B
2
1
n
α
L
A
R2
c
A1
R1
A2
φ
L1
β
Units
Dimension Limits
Pitch
INCHES
NOM
0.026
28
MILLIMETERS*
MIN
MAX
MIN
NOM
0.65
28
MAX
p
n
A
A1
A2
D
E
E1
R1
R2
L
Number of Pins
Overall Pack. Height
Shoulder Height
Standoff
Molded Package Length
Molded Package Width
Outside Dimension
Shoulder Radius
Gull Wing Radius
Foot Length
0.068
0.073
0.036
0.005
0.402
0.208
0.306
0.005
0.005
0.020
4
0.078
1.73
0.66
1.86
0.91
0.13
10.20
5.29
7.78
0.13
0.13
0.51
4
1.99
0.026
0.002
0.396
0.205
0.301
0.005
0.005
0.015
0
0.046
0.008
0.407
0.212
0.311
0.010
0.010
0.025
8
1.17
0.21
10.33
5.38
7.90
0.25
0.25
0.64
8
0.05
10.07
5.20
7.65
0.13
0.13
0.38
0
‡
‡
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
α
β
0.000
0.005
0.010
0
0.005
0.007
0.012
5
0.010
0.009
0.015
10
0.00
0.13
0.25
0
0.13
0.18
0.32
5
0.25
0.22
0.38
10
†
0
5
10
0
5
10
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
1998 Microchip Technology Inc.
DS30605A-page 131
PIC16C63A/65B/73B/74B
16.6
K04-016 40-Lead Plastic Dual In-line (P) – 600 mil
E
D
α
2
n
1
A1
L
E1
R
A
c
B1
B
β
A2
p
eB
Units
INCHES*
NOM
0.600
40
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
Molded Package Width
Radius to Radius Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
MAX
MIN
NOM
15.24
40
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
α
0.100
0.018
0.050
0.005
0.010
0.160
0.093
0.020
0.130
2.018
0.535
0.565
0.610
10
2.54
0.016
0.020
0.41
1.14
0.46
1.27
0.13
0.25
4.06
2.36
0.51
3.30
51.26
13.59
14.35
15.49
10
0.51
†
0.045
0.000
0.009
0.110
0.073
0.020
0.125
2.013
0.530
0.545
0.630
5
0.055
0.010
0.011
0.160
0.113
0.040
0.135
2.023
0.540
0.585
0.670
15
1.40
0.25
0.28
4.06
2.87
1.02
3.43
51.38
13.72
14.86
17.02
15
0.00
0.23
2.79
1.85
0.51
3.18
51.13
13.46
13.84
16.00
5
‡
‡
β
5
10
15
5
10
15
*
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
DS30605A-page 132
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.7
K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil
E
W
D
2
1
n
A1
L
E1
A
R
c
eB
B1
A2
p
B
Units
INCHES*
NOM
0.600
40
MILLIMETERS
Dimension Limits
PCB Row Spacing
Number of Pins
Pitch
Lower Lead Width
Upper Lead Width
Shoulder Radius
Lead Thickness
Top to Seating Plane
Top of Lead to Seating Plane
Base to Seating Plane
Tip to Seating Plane
Package Length
MIN
MAX
MIN
NOM
15.24
40
MAX
n
p
B
B1
R
c
A
A1
A2
L
D
E
E1
eB
W
0.098
0.100
0.020
0.053
0.005
0.011
0.205
0.135
0.045
0.140
2.050
0.520
0.580
0.660
0.350
0.102
2.49
0.41
2.54
0.50
2.59
0.58
1.40
0.25
0.36
5.59
3.89
1.52
3.68
52.32
13.36
15.24
18.03
9.14
0.016
0.050
0.000
0.008
0.190
0.117
0.030
0.135
2.040
0.514
0.560
0.610
0.340
0.023
0.055
0.010
0.014
0.220
0.153
0.060
0.145
2.060
0.526
0.600
0.710
0.360
1.27
0.00
1.33
0.13
0.20
0.28
4.83
5.21
2.97
3.43
0.00
1.14
3.43
3.56
51.82
13.06
14.22
15.49
8.64
52.07
13.21
14.73
16.76
8.89
Package Width
Radius to Radius Width
Overall Row Spacing
Window Diameter
*
Controlling Parameter.
1998 Microchip Technology Inc.
DS30605A-page 133
PIC16C63A/65B/73B/74B
16.8
K04-076 44-Lead PlasticThin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
α
L
A
R2
c
φ
R1
A1
β
A2
L1
Units
Dimension Limits
Pitch
INCHES
NOM
0.031
44
MILLIMETERS*
MIN
MAX
MIN
NOM
0.80
44
MAX
p
n
n1
A
A1
A2
R1
R2
L
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
11
11
0.039
0.015
0.002
0.003
0.003
0.005
0
0.043
0.025
0.004
0.003
0.006
0.010
3.5
0.047
1.00
0.38
1.10
0.64
0.10
0.08
0.14
0.25
3.5
1.20
0.035
0.006
0.010
0.008
0.015
7
0.89
0.15
0.25
0.20
0.38
7
0.05
0.08
0.08
0.13
0
Foot Angle
φ
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
*
L1
c
B
0.003
0.004
0.012
0.463
0.463
0.390
0.390
0.025
5
0.008
0.006
0.015
0.472
0.472
0.394
0.394
0.035
10
0.013
0.008
0.018
0.482
0.482
0.398
0.398
0.045
15
0.08
0.09
0.30
11.75
11.75
9.90
9.90
0.64
5
0.20
0.15
0.38
12.00
12.00
10.00
10.00
0.89
10
0.33
0.20
0.45
12.25
12.25
10.10
10.10
1.14
15
†
D1
E1
‡
D
E
‡
X
α
β
5
12
15
5
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-026 ACB
DS30605A-page 134
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
16.9
K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form
E1
E
# leads = n1
p
D
D1
2
1
B
n
X x 45°
α
L
R2
c
A
R1
φ
A1
β
L1
A2
Units
Dimension Limits
Pitch
INCHES
NOM
0.031
MILLIMETERS*
MIN
MAX
MIN
NOM
0.80
44
MAX
p
n
n1
A
A1
A2
R1
R2
L
Number of Pins
Pins along Width
Overall Pack. Height
Shoulder Height
Standoff
Shoulder Radius
Gull Wing Radius
Foot Length
44
11
11
0.079
0.086
0.044
0.006
0.005
0.012
0.020
3.5
0.093
2.00
0.81
2.18
1.11
0.15
0.13
0.30
0.51
3.5
2.35
0.032
0.002
0.005
0.005
0.015
0.056
0.010
0.010
0.015
0.025
1.41
0.25
0.25
0.38
0.64
7
0.05
0.13
0.13
0.38
0
Foot Angle
φ
0
7
Radius Centerline
Lead Thickness
Lower Lead Width
Outside Tip Length
Outside Tip Width
Molded Pack. Length
Molded Pack. Width
Pin 1 Corner Chamfer
Mold Draft Angle Top
L1
c
B
0.011
0.005
0.012
0.510
0.510
0.390
0.390
0.025
0.016
0.007
0.015
0.520
0.520
0.394
0.394
0.035
10
0.021
0.009
0.018
0.530
0.530
0.398
0.398
0.045
15
0.28
0.13
0.30
12.95
12.95
9.90
9.90
0.635
5
0.41
0.18
0.37
13.20
13.20
10.00
10.00
0.89
10
0.53
0.23
0.45
13.45
13.45
10.10
10.10
1.143
15
†
D1
E1
‡
D
E
‡
X
α
β
5
5
Mold Draft Angle Bottom
*
12
15
5
12
15
Controlling Parameter.
†
Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MS-022 AB
1998 Microchip Technology Inc.
DS30605A-page 135
PIC16C63A/65B/73B/74B
16.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square
E1
E
# leads = n1
D1
D
n 1 2
α
A3
CH2 x 45°
CH1 x 45°
R1
c
L
A
35°
A1
B1
B
R2
β
A2
p
E2
D2
Units
INCHES*
NOM
44
MILLIMETERS
Dimension Limits
Number of Pins
Pitch
Overall Pack. Height
Shoulder Height
Standoff
MIN
MAX
MIN
NOM
44
MAX
n
p
A
A1
A2
A3
CH1
CH2
E1
D1
E
D
E2
D2
n1
c
B1
B
L
0.050
0.173
0.103
0.023
0.029
0.045
0.005
0.690
0.690
0.653
0.653
0.620
0.620
11
0.010
0.029
0.018
0.058
0.005
0.025
5
1.27
0.165
0.180
4.19
2.41
0.38
0.61
1.02
0.00
17.40
17.40
16.51
16.51
15.49
15.49
4.38
2.60
0.57
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
11
4.57
2.79
0.76
0.86
1.27
0.095
0.015
0.024
0.040
0.000
0.685
0.685
0.650
0.650
0.610
0.610
0.110
0.030
0.034
0.050
0.010
0.695
0.695
0.656
0.656
0.630
0.630
Side 1 Chamfer Dim.
Corner Chamfer (1)
Corner Chamfer (other)
Overall Pack. Width
Overall Pack. Length
Molded Pack. Width
Molded Pack. Length
Footprint Width
Footprint Length
Pins along Width
Lead Thickness
Upper Lead Width
Lower Lead Width
Upper Lead Length
Shoulder Inside Radius
J-Bend Inside Radius
Mold Draft Angle Top
Mold Draft Angle Bottom
*
0.25
17.65
17.65
16.66
16.66
16.00
16.00
‡
‡
0.008
0.026
0.015
0.050
0.003
0.015
0
0.012
0.032
0.021
0.065
0.010
0.035
10
0.20
0.66
0.38
1.27
0.08
0.38
0
0.25
0.74
0.46
1.46
0.13
0.64
5
0.30
0.81
0.53
1.65
0.25
0.89
10
†
R1
R2
α
β
0
5
10
0
5
10
Controlling Parameter.
†
Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”
(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”
‡
Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”
JEDEC equivalent: MO-047 AC
DS30605A-page 136
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
7/98
This is a new data sheet. However, the devices described in this data sheet are
the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234D, and
the PIC16C7X Data Sheet, DS30390E.
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
Difference
DEVICE DIFFERENCES
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
A/D
no
no
5 channels, 8 bits
no
8 channels, 8 bits
yes
Parallel Slave Port
Packages
no
yes
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
SSOP
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
28-pin PDIP, 28-pin
windowed CERDIP,
28-pin SOIC, 28-pin
40-pin PDIP, 40-pin
windowed CERDIP,
44-pin TQFP, 44-pin
MQFP, 44-pin PLCC
MQFP, 44-pin PLCC SSOP
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of
devices to the ones listed in this data sheet are listed in
Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C63/65A/73A/74A
2.5V - 6.0V
Difference
PIC16C63A/65B/73B/74B
2.5V - 5.5V
Voltage Range
SSP module
SSP module
single mode SPI
4-mode SPI
N/A
Can only transmit one word in SPI mode
of enhanced SSP.
CCP module
CCP does not reset TMR1 when in special
event trigger mode.
N/A
USART module
Timer1 module
USART receiver errata in BRGH=1 mode.
N/A
Writing to TMR1L register can cause over- N/A
flow in TMR1H register.
1998 Microchip Technology Inc.
DS30605A-page 137
PIC16C63A/65B/73B/74B
18. Brown-out protection circuitry has been added.
Controlled by configuration word bit BODEN.
Brown-out reset ensures the device is placed in
a reset condition if VDD dips below a fixed set-
point.
APPENDIX D: MIGRATION FROM
BASELINE TO
MIDRANGE DEVICES
This section discusses how to migrate from a baseline
device (i.e., PIC16C5X) to a midrange device (i.e.,
PIC16CXXX).
To convert code written for PIC16C5X to PIC16CXXX,
the user should take the following steps:
The following are the list of modifications over the
PIC16C5X microcontroller family:
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change reset vector to 0000h.
3. Data memory paging is redefined slightly.
STATUS register is modified.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5X.
5. OPTION and TRIS registers are made address-
able.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Reg-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In-circuit serial programming” is made possible.
The user can program PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
DS30605A-page 138
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
T0IE ................................................... INTCON<5>
T0IF ................................................... INTCON<2>
T0SE .................................................. OPTION_REG<4>
T1CKPS1:T1CKPS0 .......................... T1CON<5:4>
T1OSCEN .......................................... T1CON<3>
T1SYNC ............................................ T1CON<2>
T2CKPS1:T2CKPS0 .......................... T2CON<1:0>
TMR1CS ............................................ T1CON<1>
TMR1IE ............................................. PIE1<0>
TMR1IF .............................................. PIR1<0>
TMR1ON ........................................... T1CON<0>
TMR2IE ............................................. PIE1<1>
TMR2IF .............................................. PIR1<1>
TMR2ON ........................................... T2CON<2>
TO ...................................................... STATUS<4>
TOUTPS3:TOUTPS0 ......................... T2CON<6:3>
TRMT ................................................. TXSTA<1>
TX9 .................................................... TXSTA<6>
TX9D ................................................. TXSTA<0>
TXEN ................................................. TXSTA<5>
TXIE ................................................... PIE1<4>
TXIF ................................................... PIR1<4>
UA ...................................................... SSPSTAT<1>
WCOL ................................................ SSPCON<7>
Z ........................................................ STATUS<2>
APPENDIX E: BIT/REGISTER CROSS-
REFERENCE LIST
ADCS1:ADCS0 ..................................ADCON0<7:6>
ADIE ...................................................PIE1<6>
ADIF ...................................................PIR1<6>
ADON .................................................ADCON0<0>
BF ......................................................SSPSTAT<0>
BOR ...................................................PCON<0>
BRGH .................................................TXSTA<2>
C ........................................................STATUS<0>
CCP1IE ..............................................PIE1<2>
CCP1IF ..............................................PIR1<2>
CCP1M3:CCP1M0 .............................CCP1CON<3:0>
CCP1X:CCP1Y ..................................CCP1CON<5:4>
CCP2IE ..............................................PIE2<0>
CCP2IF ..............................................PIR2<0>
CCP2M3:CCP2M0 .............................CCP2CON<3:0>
CCP2X:CCP2Y ..................................CCP2CON<5:4>
CHS2:CHS0 .......................................ADCON0<5:3>
CKE ....................................................SSPSTAT<6>
CKP ....................................................SSPCON<4>
CREN .................................................RCSTA<4>
CSRC .................................................TXSTA<7>
D/A .....................................................SSPSTAT<5>
DC ......................................................STATUS<1>
FERR .................................................RCSTA<2>
GIE .....................................................INTCON<7>
GO/DONE ..........................................ADCON0<2>
IBF .....................................................TRISE<7>
IBOV ...................................................TRISE<5>
INTE ...................................................INTCON<4>
INTEDG .............................................OPTION_REG<6>
INTF ...................................................INTCON<1>
IRP .....................................................STATUS<7>
OBF ....................................................TRISE<6>
OERR .................................................RCSTA<1>
P .........................................................SSPSTAT<4>
PCFG2:PCFG0 ..................................ADCON1<2:0>
PD ......................................................STATUS<3>
PEIE ...................................................INTCON<6>
POR ...................................................PCON<1>
PS2:PS0 ............................................OPTION_REG<2:0>
PSA ....................................................OPTION_REG<3>
PSPIE ................................................PIE1<7>
PSPIF .................................................PIR1<7>
PSPMODE .........................................TRISE<4>
R/W ....................................................SSPSTAT<2>
RBIE ...................................................INTCON<3>
RBIF ...................................................INTCON<0>
RBPU .................................................OPTION_REG<7>
RCIE ..................................................PIE1<5>
RCIF ...................................................PIR1<5>
RP1:RP0 ............................................STATUS<6:5>
RX9 ....................................................RCSTA<6>
RX9D .................................................RCSTA<0>
S .........................................................SSPSTAT<3>
SMP ...................................................SSPSTAT<7>
SPEN .................................................RCSTA<7>
SREN .................................................RCSTA<5>
SSPEN ...............................................SSPCON<5>
SSPIE ................................................PIE1<3>
SSPIF .................................................PIR1<3>
SSPM3:SSPM0 ..................................SSPCON<3:0>
SSPOV ...............................................SSPCON<6>
SYNC .................................................TXSTA<4>
T0CS ..................................................OPTION_REG<5>
1998 Microchip Technology Inc.
DS30605A-page 139
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 140
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Flag (CCP2IF Bit)............................................... 21
RC1/T1OSI/CCP2 Pin...................................... 7, 9
Interaction of Two CCP Modules................................ 45
Timer Resources ........................................................ 45
Timing Diagram ........................................................ 112
CCP1CON Register............................................................ 45
CCP1M3:CCP1M0 Bits .............................................. 45
CCP1X:CCP1Y Bits.................................................... 45
CCP2CON Register............................................................ 45
CCP2M3:CCP2M0 Bits .............................................. 45
CCP2X:CCP2Y Bits.................................................... 45
Code Protection............................................................ 81, 94
CP1:CP0 Bits.............................................................. 81
Compare (CCP Module)..................................................... 47
Block Diagram ............................................................ 47
CCP Pin Configuration ............................................... 47
CCPR1H:CCPR1L Registers ..................................... 47
Software Interrupt....................................................... 47
Special Event Trigger ..................................... 41, 47, 80
Timer1 Mode Selection............................................... 47
Configuration Bits ............................................................... 81
Conversion Considerations .............................................. 137
D
Data Memory...................................................................... 11
Bank Select (RP1:RP0 Bits)................................. 11, 15
General Purpose Registers ........................................ 11
Register File Map ....................................................... 12
Special Function Registers................................... 12, 13
DC Characteristics.................................................... 102, 104
Development Support......................................................... 97
Development Tools............................................................. 97
Device Differences ........................................................... 137
Direct Addressing ............................................................... 24
E
INDEX
A
A/D...................................................................................... 75
A/D Converter Enable (ADIE Bit)................................ 18
A/D Converter Flag (ADIF Bit) .............................. 19, 77
A/D Converter Interrupt, Configuring .......................... 77
ADCON0 Register................................................. 13, 75
ADCON1 Register........................................... 14, 75, 76
ADRES Register ............................................. 13, 75, 77
Analog Port Pins ....................................... 7, 8, 9, 34, 35
Analog Port Pins, Configuring..................................... 79
Block Diagram............................................................. 77
Block Diagram, Analog Input Model............................ 78
Channel Select (CHS2:CHS0 Bits)............................. 75
Clock Select (ADCS1:ADCS0 Bits)............................. 75
Configuring the Module............................................... 77
Conversion Clock (TAD) .............................................. 79
Conversion Status (GO/DONE Bit)....................... 75, 77
Conversions................................................................ 80
Converter Characteristics ......................................... 121
Module On/Off (ADON Bit).......................................... 75
Port Configuration Control (PCFG2:PCFG0 Bits)....... 76
Sampling Requirements.............................................. 78
Special Event Trigger (CCP)................................. 47, 80
Timing Diagram......................................................... 122
Absolute Maximum Ratings .............................................. 101
ADCON0 Register......................................................... 13, 75
ADCS1:ADCS0 Bits.................................................... 75
ADON Bit .................................................................... 75
CHS2:CHS0 Bits......................................................... 75
GO/DONE Bit........................................................ 75, 77
ADCON1 Register................................................... 14, 75, 76
PCFG2:PCFG0 Bits.................................................... 76
ADRES Register ..................................................... 13, 75, 77
Architecture
Electrical Characteristics .................................................. 101
Errata.....................................................................................4
External Power-on Reset Circuit ........................................ 85
F
PIC16C63A/PIC16C73B Block Diagram....................... 5
PIC16C65B/PIC16C74B Block Diagram....................... 6
Assembler
Firmware Instructions ......................................................... 95
ftp site............................................................................... 147
Fuzzy Logic Dev. System (fuzzyTECH -MP).................... 99
I
MPASM Assembler..................................................... 98
B
Banking, Data Memory ................................................. 11, 15
Brown-out Reset (BOR).............................. 81, 83, 85, 86, 87
BOR Enable (BODEN Bit)........................................... 81
BOR Status (BOR Bit)................................................. 22
Timing Diagram......................................................... 110
C
I/O Ports ............................................................................. 25
2
I C (SSP Module)............................................................... 56
ACK Pulse .......................................... 56, 57, 58, 59, 60
Addressing.................................................................. 57
Block Diagram ............................................................ 56
Buffer Full Status (BF Bit)........................................... 52
Clock Polarity Select (CKP Bit)................................... 53
Data/Address (D/A Bit) ............................................... 52
Master Mode............................................................... 60
Mode Select (SSPM3:SSPM0 Bits)............................ 53
Multi-Master Mode...................................................... 60
Read/Write Bit Information (R/W Bit)........ 52, 57, 58, 59
Receive Overflow Indicator (SSPOV Bit).................... 53
Reception ................................................................... 58
Reception Timing Diagram......................................... 58
Serial Clock (RC3/SCK/SCL) ..................................... 59
Slave Mode................................................................. 56
Start (S Bit)........................................................... 52, 60
Stop (P Bit) ........................................................... 52, 60
Synchronous Serial Port Enable (SSPEN Bit)............ 53
Timing Diagram, Data............................................... 119
Timing Diagram, Start/Stop Bits ............................... 118
Transmission .............................................................. 59
Update Address (UA Bit) ............................................ 52
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator............ 97
Capture (CCP Module) ....................................................... 46
Block Diagram............................................................. 46
CCP Pin Configuration................................................ 46
CCPR1H:CCPR1L Registers...................................... 46
Changing Between Capture Prescalers...................... 46
Software Interrupt ....................................................... 46
Timer1 Mode Selection............................................... 46
Capture/Compare/PWM (CCP)........................................... 45
CCP1 .......................................................................... 45
CCP1CON Register...................................... 13, 45
CCPR1H Register......................................... 13, 45
CCPR1L Register ......................................... 13, 45
Enable (CCP1IE Bit)........................................... 18
Flag (CCP1IF Bit) ............................................... 19
RC2/CCP1 Pin.................................................. 7, 9
CCP2 .......................................................................... 45
CCP2CON Register...................................... 13, 45
CCPR2H Register......................................... 13, 45
CCPR2L Register ......................................... 13, 45
Enable (CCP2IE Bit)........................................... 20
1998 Microchip Technology Inc.
DS30605A-page 141
PIC16C63A/65B/73B/74B
ID Locations ..................................................................81, 94
In-Circuit Serial Programming (ICSP) ...........................81, 94
Indirect Addressing .............................................................24
FSR Register ..................................................11, 13, 24
INDF Register .............................................................13
Instruction Format ...............................................................95
Instruction Set .....................................................................95
Summary Table...........................................................96
INTCON Register..........................................................13, 17
GIE Bit.........................................................................17
INTE Bit.......................................................................17
INTF Bit.......................................................................17
PEIE Bit.......................................................................17
RBIE Bit ......................................................................17
RBIF Bit.................................................................17, 27
T0IE Bit .......................................................................17
T0IF Bit .......................................................................17
Interrupt Sources...........................................................81, 90
A/D Conversion Complete ..........................................77
Block Diagram.............................................................90
Capture Complete (CCP)............................................46
Compare Complete (CCP)..........................................47
Interrupt on Change (RB7:RB4 ).................................27
RB0/INT Pin, External.........................................7, 8, 91
SSP Receive/Transmit Complete ...............................51
TMR0 Overflow.....................................................38, 91
TMR1 Overflow.....................................................39, 41
TMR2 to PR2 Match ...................................................44
TMR2 to PR2 Match (PWM) .................................43, 48
USART Receive/Transmit Complete ..........................61
Interrupts, Context Saving During.......................................91
Interrupts, Enable Bits
Memory Organization
Data Memory.............................................................. 11
Program Memory........................................................ 11
MP-DriveWay™ - Application Code Generator .................. 99
MPLAB C............................................................................ 99
MPLAB Integrated Development Environment
Software ..................................................................... 98
O
On-Line Support ............................................................... 147
OPCODE Field Descriptions............................................... 95
OPTION_REG Register................................................ 14, 16
INTEDG Bit................................................................. 16
PS2:PS0 Bits........................................................ 16, 37
PSA Bit ................................................................. 16, 37
RBPU Bit .................................................................... 16
T0CS Bit ............................................................... 16, 37
T0SE Bit ............................................................... 16, 37
OSC1/CLKIN Pin .............................................................. 7, 8
OSC2/CLKOUT Pin .......................................................... 7, 8
Oscillator Configuration ................................................ 81, 82
HS......................................................................... 82, 86
LP ......................................................................... 82, 86
RC .................................................................. 82, 83, 86
Selection (FOSC1:FOSC0 Bits) ................................. 81
XT......................................................................... 82, 86
Oscillator, Timer1.......................................................... 39, 41
Oscillator, WDT................................................................... 92
P
Packaging......................................................................... 125
Paging, Program Memory............................................. 11, 23
Parallel Slave Port (PSP).......................................... 9, 31, 35
Block Diagram ............................................................ 35
RE0/RD/AN5 Pin .............................................. 9, 34, 35
RE1/WR/AN6 Pin ............................................. 9, 34, 35
RE2/CS/AN7 Pin .............................................. 9, 34, 35
Read Waveforms........................................................ 36
Read/Write Enable (PSPIE Bit) .................................. 18
Read/Write Flag (PSPIF Bit)....................................... 19
Select (PSPMODE Bit)................................... 31, 33, 35
Timing Diagram ........................................................ 113
Write Waveforms........................................................ 35
PCON Register............................................................. 22, 86
BOR Bit....................................................................... 22
POR Bit....................................................................... 22
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 98
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 98
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 98
PICMASTER In-Circuit Emulator ..................................... 97
PICSTART Plus Entry Level Development System......... 97
PIE1 Register................................................................ 14, 18
ADIE Bit...................................................................... 18
CCP1IE Bit ................................................................. 18
PSPIE Bit.................................................................... 18
RCIE Bit...................................................................... 18
SSPIE Bit.................................................................... 18
TMR1IE Bit ................................................................. 18
TMR2IE Bit ................................................................. 18
TXIE Bit ...................................................................... 18
PIE2 Register................................................................ 14, 20
CCP2IE Bit ................................................................. 20
Pinout Descriptions
A/D Converter Enable (ADIE Bit)................................18
CCP1 Enable (CCP1IE Bit)...................................18, 46
CCP2 Enable (CCP2IE Bit).........................................20
Global Interrupt Enable (GIE Bit) ..........................17, 90
Interrupt on Change (RB7:RB4) Enable
(RBIE Bit)..............................................................17, 91
Peripheral Interrupt Enable (PEIE Bit) ........................17
PSP Read/Write Enable (PSPIE Bit) ..........................18
RB0/INT Enable (INTE Bit) .........................................17
SSP Enable (SSPIE Bit) .............................................18
TMR0 Overflow Enable (T0IE Bit)...............................17
TMR1 Overflow Enable (TMR1IE Bit).........................18
TMR2 to PR2 Match Enable (TMR2IE Bit) .................18
USART Receive Enable (RCIE Bit) ............................18
USART Transmit Enable (TXIE Bit)............................18
Interrupts, Flag Bits
A/D Converter Flag (ADIF Bit) ..............................19, 77
CCP1 Flag (CCP1IF Bit).................................19, 46, 47
CCP2 Flag (CCP2IF Bit).............................................21
Interrupt on Change (RB7:RB4) Flag
(RBIF Bit) ........................................................17, 27, 91
PSP Read/Write Flag (PSPIF Bit)...............................19
RB0/INT Flag (INTF Bit)..............................................17
SSP Flag (SSPIF Bit)..................................................19
TMR0 Overflow Flag (T0IF Bit).............................17, 91
TMR1 Overflow Flag (TMR1IF Bit) .............................19
TMR2 to PR2 Match Flag (TMR2IF Bit)......................19
USART Receive Flag (RCIF Bit).................................19
USART Transmit Flag (TXIE Bit) ................................19
K
KeeLoq Evaluation and Programming Tools....................99
M
Master Clear (MCLR)........................................................7, 8
MCLR Reset, Normal Operation.....................83, 86, 87
MCLR Reset, SLEEP......................................83, 86, 87
PIC16C63A/PIC16C73B............................................... 7
PIC16C65B/PIC16C74B............................................... 8
PIR1 Register ............................................................... 13, 19
ADIF Bit ...................................................................... 19
CCP1IF Bit.................................................................. 19
PSPIF Bit.................................................................... 19
DS30605A-page 142
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
RCIF Bit ...................................................................... 19
SSPIF Bit .................................................................... 19
TMR1IF Bit.................................................................. 19
TMR2IF Bit.................................................................. 19
TXIF Bit....................................................................... 19
PIR2 Register................................................................ 13, 21
CCP2IF Bit.................................................................. 21
Pointer, FSR ....................................................................... 24
PORTA.............................................................................. 7, 8
Analog Port Pins ....................................................... 7, 8
Initialization ................................................................. 25
PORTA Register ................................................... 13, 25
RA3:RA0 and RA5 Port Pins ...................................... 25
RA4/T0CKI Pin.................................................... 7, 8, 25
RA5/SS/AN4 Pin................................................. 7, 8, 54
TRISA Register..................................................... 14, 25
PORTB.............................................................................. 7, 8
Initialization ................................................................. 27
PORTB Register ................................................... 13, 27
Pull-up Enable (RBPU Bit).......................................... 16
RB0/INT Edge Select (INTEDG Bit)............................ 16
RB0/INT Pin, External......................................... 7, 8, 91
RB3:RB0 Port Pins ..................................................... 27
RB7:RB4 Interrupt on Change.................................... 91
RB7:RB4 Interrupt on Change Enable
Power-on Reset (POR)............................... 81, 83, 85, 86, 87
Oscillator Start-up Timer (OST)............................ 81, 85
POR Status (POR Bit) ................................................ 22
Power Control (PCON) Register................................. 86
Power-down (PD Bit)............................................ 15, 83
Power-on Reset Circuit, External ............................... 85
Power-up Timer (PWRT)...................................... 81, 85
PWRT Enable (PWRTE Bit) ....................................... 81
Time-out (TO Bit).................................................. 15, 83
Time-out Sequence .................................................... 86
Time-out Sequence on Power-up......................... 88, 89
Timing Diagram ........................................................ 110
Prescaler, Capture.............................................................. 46
Prescaler, Timer0 ............................................................... 37
Assignment (PSA Bit)........................................... 16, 37
Block Diagram ............................................................ 38
Rate Select (PS2:PS0 Bits).................................. 16, 37
Switching Between Timer0 and WDT......................... 38
Prescaler, Timer1 ............................................................... 40
Select (T1CKPS1:T1CKPS0 Bits) .............................. 39
Prescaler, Timer2 ............................................................... 48
Select (T2CKPS1:T2CKPS0 Bits) .............................. 43
PRO MATE II Universal Programmer.............................. 97
Product Identification System........................................... 149
Program Counter
(RBIE Bit).............................................................. 17, 91
RB7:RB4 Interrupt on Change Flag
PCL Register ........................................................ 13, 23
PCLATH Register........................................... 13, 23, 91
Reset Conditions ........................................................ 86
Program Memory................................................................ 11
Interrupt Vector........................................................... 11
Paging .................................................................. 11, 23
Program Memory Map................................................ 11
Reset Vector............................................................... 11
Program Verification........................................................... 94
Programming Pin (VPP) .................................................... 7, 8
Programming, Device Instructions...................................... 95
PWM (CCP Module)........................................................... 48
Block Diagram ............................................................ 48
CCPR1H:CCPR1L Registers ..................................... 48
Duty Cycle .................................................................. 48
Example Frequencies/Resolutions............................. 49
Output Diagram .......................................................... 48
Period ......................................................................... 48
Set-Up for PWM Operation......................................... 49
TMR2 to PR2 Match............................................. 43, 48
TMR2 to PR2 Match Enable (TMR2IE Bit)................. 18
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19
Q
(RBIF Bit) ........................................................ 17, 27, 91
RB7:RB4 Port Pins ..................................................... 27
TRISB Register..................................................... 14, 27
PORTC ............................................................................. 7, 9
Block Diagram............................................................. 29
Initialization ................................................................. 29
PORTC Register................................................... 13, 29
RC0/T1OSO/T1CKI Pin ............................................ 7, 9
RC1/T1OSI/CCP2 Pin............................................... 7, 9
RC2/CCP1 Pin.......................................................... 7, 9
RC3/SCK/SCL Pin ........................................ 7, 9, 54, 59
RC4/SDI/SDA Pin ............................................... 7, 9, 54
RC5/SDO Pin...................................................... 7, 9, 54
RC6/TX/CK Pin................................................... 7, 9, 62
RC7/RX/DT Pin............................................. 7, 9, 62, 63
TRISC Register............................................... 14, 29, 61
PORTD ........................................................................... 9, 35
Block Diagram............................................................. 31
Parallel Slave Port (PSP) Function............................. 31
PORTD Register................................................... 13, 31
TRISD Register..................................................... 14, 31
PORTE.................................................................................. 9
Analog Port Pins ............................................... 9, 34, 35
Block Diagram............................................................. 33
Input Buffer Full Status (IBF Bit) ................................. 33
Input Buffer Overflow (IBOV Bit)................................. 33
Output Buffer Full Status (OBF Bit)............................. 33
PORTE Register ................................................... 13, 33
PSP Mode Select (PSPMODE Bit) ................. 31, 33, 35
RE0/RD/AN5 Pin............................................... 9, 34, 35
RE1/WR/AN6 Pin.............................................. 9, 34, 35
RE2/CS/AN7 Pin............................................... 9, 34, 35
TRISE Register..................................................... 14, 33
Postscaler, Timer2
Q-Clock............................................................................... 48
R
RCSTA Register................................................................. 62
CREN Bit .................................................................... 62
FERR Bit..................................................................... 62
OERR Bit.................................................................... 62
RX9 Bit ....................................................................... 62
RX9D Bit..................................................................... 62
SPEN Bit............................................................... 61, 62
SREN Bit .................................................................... 62
Reader Response............................................................. 148
Register File ....................................................................... 11
Register File Map ............................................................... 12
Reset ............................................................................ 81, 83
Block Diagram ............................................................ 84
Reset Conditions for All Registers.............................. 87
Reset Conditions for PCON Register ......................... 86
Reset Conditions for Program Counter ...................... 86
Reset Conditions for STATUS Register ..................... 86
Select (TOUTPS3:TOUTPS0 Bits) ............................. 43
Postscaler, WDT................................................................. 37
Assignment (PSA Bit) ........................................... 16, 37
Block Diagram............................................................. 38
Rate Select (PS2:PS0 Bits) .................................. 16, 37
Switching Between Timer0 and WDT ......................... 38
1998 Microchip Technology Inc.
DS30605A-page 143
PIC16C63A/65B/73B/74B
Timing Diagram.........................................................110
Revision History ................................................................137
S
SEEVAL Evaluation and Programming System...............99
SLEEP.....................................................................81, 83, 93
Software Simulator (MPLAB-SIM).......................................99
Special Features of the CPU...............................................81
Special Function Registers ...........................................12, 13
Speed, Operating..........................................................1, 101
SPI (SSP Module)
TMR1CS Bit................................................................ 39
TMR1ON Bit ............................................................... 39
T2CON Register ........................................................... 13, 43
T2CKPS1:T2CKPS0 Bits............................................ 43
TMR2ON Bit ............................................................... 43
TOUTPS3:TOUTPS0 Bits .......................................... 43
Timer0................................................................................. 37
Block Diagram ............................................................ 37
Clock Source Edge Select (T0SE Bit) .................. 16, 37
Clock Source Select (T0CS Bit) ........................... 16, 37
Overflow Enable (T0IE Bit)......................................... 17
Overflow Flag (T0IF Bit) ....................................... 17, 91
Overflow Interrupt................................................. 38, 91
RA4/T0CKI Pin, External Clock................................ 7, 8
Timing Diagram ........................................................ 111
TMR0 Register ........................................................... 13
Timer1................................................................................. 39
Block Diagram ............................................................ 40
Capacitor Selection .................................................... 41
Clock Source Select (TMR1CS Bit)............................ 39
External Clock Input Sync (T1SYNC Bit).................... 39
Module On/Off (TMR1ON Bit) .................................... 39
Oscillator............................................................... 39, 41
Oscillator Enable (T1OSCEN Bit)............................... 39
Overflow Enable (TMR1IE Bit) ................................... 18
Overflow Flag (TMR1IF Bit)........................................ 19
Overflow Interrupt................................................. 39, 41
RC0/T1OSO/T1CKI Pin............................................ 7, 9
RC1/T1OSI/CCP2 Pin .............................................. 7, 9
Special Event Trigger (CCP) ................................ 41, 47
T1CON Register................................................... 13, 39
Timing Diagram ........................................................ 111
TMR1H Register................................................... 13, 39
TMR1L Register ................................................... 13, 39
Timer2
Block Diagram.............................................................54
Buffer Full Status (BF Bit) ...........................................52
Clock Edge Select (CKE Bit).......................................52
Clock Polarity Select (CKP Bit)...................................53
Data Input Sample Phase (SMP Bit)...........................52
Mode Select (SSPM3:SSPM0 Bits) ............................53
Receive Overflow Indicator (SSPOV Bit)....................53
Serial Clock (RC3/SCK/SCL)......................................54
Serial Data In (RC4/SDI/SDA) ....................................54
Serial Data Out (RC5/SDO)........................................54
Slave Select (RA5/SS/AN4)........................................54
Synchronous Serial Port Enable (SSPEN Bit) ............53
SSP.....................................................................................51
Enable (SSPIE Bit)......................................................18
Flag (SSPIF Bit)..........................................................19
RA5/SS/AN4 Pin.......................................................7, 8
RC3/SCK/SCL Pin ....................................................7, 9
RC4/SDI/SDA Pin .....................................................7, 9
RC5/SDO Pin............................................................7, 9
RCSTA Register .........................................................13
SPBRG Register.........................................................14
SSPADD Register.......................................................14
SSPBUF Register .......................................................13
SSPCON Register ................................................13, 53
SSPSTAT Register ...............................................14, 52
TMR2 Output for Clock Shift.................................43, 44
TXSTA Register..........................................................14
Write Collision Detect (WCOL Bit) ..............................53
SSPCON Register...............................................................53
CKP Bit .......................................................................53
SSPEN Bit...................................................................53
SSPM3:SSPM0 Bits....................................................53
SSPOV Bit ..................................................................53
WCOL Bit....................................................................53
SSPSTAT Register .............................................................52
BF Bit ..........................................................................52
CKE Bit .......................................................................52
D/A Bit.........................................................................52
P bit.......................................................................52, 60
R/W Bit......................................................52, 57, 58, 59
S Bit ......................................................................52, 60
SMP Bit.......................................................................52
UA Bit..........................................................................52
Stack ...................................................................................23
STATUS Register....................................................13, 15, 91
C Bit ............................................................................15
DC Bit..........................................................................15
IRP Bit.........................................................................15
PD Bit....................................................................15, 83
RP1:RP0 Bits..............................................................15
TO Bit....................................................................15, 83
Z Bit.............................................................................15
T
Block Diagram ............................................................ 44
PR2 Register .................................................. 14, 43, 48
SSP Clock Shift .................................................... 43, 44
T2CON Register................................................... 13, 43
TMR2 Register ..................................................... 13, 43
TMR2 to PR2 Match Enable (TMR2IE Bit)................. 18
TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 19
TMR2 to PR2 Match Interrupt......................... 43, 44, 48
Timing Diagrams
2
I C Reception (7-bit Address)..................................... 58
Time-out Sequence on Power-up......................... 88, 89
USART Asynchronous Master Transmission ............. 67
USART Asynchronous Reception .............................. 68
USART Synchronous Reception ................................ 72
USART Synchronous Transmission........................... 71
Wake-up from SLEEP via Interrupt ............................ 94
Timing Diagrams and Specifications ................................ 108
A/D Conversion ........................................................ 122
Brown-out Reset (BOR)............................................ 110
Capture/Compare/PWM (CCP) ................................ 112
CLKOUT and I/O ...................................................... 109
External Clock .......................................................... 108
2
I C Bus Data............................................................. 119
2
I C Bus Start/Stop Bits ............................................. 118
Oscillator Start-up Timer (OST)................................ 110
Parallel Slave Port (PSP) ......................................... 113
Power-up Timer (PWRT).......................................... 110
Reset ........................................................................ 110
Timer0 and Timer1 ................................................... 111
USART Synchronous Receive
T1CON Register............................................................13, 39
T1CKPS1:T1CKPS0 Bits............................................39
T1OSCEN Bit..............................................................39
T1SYNC Bit.................................................................39
( Master/Slave) ......................................................... 120
USART SynchronousTransmission
DS30605A-page 144
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
( Master/Slave).......................................................... 120
Watchdog Timer (WDT)............................................ 110
TRISE Register............................................................. 14, 33
IBF Bit ......................................................................... 33
IBOV Bit ...................................................................... 33
OBF Bit ....................................................................... 33
PSPMODE Bit................................................. 31, 33, 35
TXSTA Register.................................................................. 61
BRGH Bit .............................................................. 61, 63
CSRC Bit..................................................................... 61
SYNC Bit..................................................................... 61
TRMT Bit..................................................................... 61
TX9 Bit ........................................................................ 61
TX9D Bit...................................................................... 61
TXEN Bit ..................................................................... 61
U
Timing Diagram .......................................................... 94
WDT Reset................................................................. 87
Watchdog Timer (WDT)................................................ 81, 92
Block Diagram ............................................................ 92
Enable (WDTE Bit) ............................................... 81, 92
Programming Considerations..................................... 92
RC Oscillator .............................................................. 92
Time-out Period.......................................................... 92
Timing Diagram ........................................................ 110
WDT Reset, Normal Operation....................... 83, 86, 87
WDT Reset, SLEEP ....................................... 83, 86, 87
WWW, On-Line Support............................................... 4, 147
USART................................................................................ 61
Asynchronous Mode ................................................... 66
Master Transmission .......................................... 67
Receive Block Diagram ...................................... 68
Reception............................................................ 68
Transmit Block Diagram ..................................... 66
Baud Rate Generator (BRG)....................................... 63
Baud Rate Error, Calculating.............................. 63
Baud Rate Formula............................................. 63
Baud Rates, Asynchronous Mode
(BRGH=0)........................................................... 64
Baud Rates, Asynchronous Mode
(BRGH=1)........................................................... 65
Baud Rates, Synchronous Mode........................ 64
High Baud Rate Select (BRGH Bit) .............. 61, 63
Sampling............................................................. 63
Clock Source Select (CSRC Bit)................................. 61
Continuous Receive Enable (CREN Bit)..................... 62
Framing Error (FERR Bit) ........................................... 62
Mode Select (SYNC Bit) ............................................. 61
Overrun Error (OERR Bit)........................................... 62
RC6/TX/CK Pin......................................................... 7, 9
RC7/RX/DT Pin......................................................... 7, 9
RCREG Register......................................................... 13
RCSTA Register ......................................................... 62
Receive Data, 9th bit (RX9D Bit) ................................ 62
Receive Enable (RCIE Bit).......................................... 18
Receive Enable, 9-bit (RX9 Bit) .................................. 62
Receive Flag (RCIF Bit).............................................. 19
Serial Port Enable (SPEN Bit)............................... 61, 62
Single Receive Enable (SREN Bit) ............................. 62
Synchronous Master Mode......................................... 70
Reception............................................................ 72
Timing Diagram, Synchronous Receive ........... 120
Timing Diagram, Synchronous
Transmission .................................................... 120
Transmission ...................................................... 71
Synchronous Slave Mode........................................... 73
Transmit Data, 9th Bit (TX9D)..................................... 61
Transmit Enable (TXEN Bit)........................................ 61
Transmit Enable (TXIE Bit) ......................................... 18
Transmit Enable, Nine-bit (TX9 Bit) ............................ 61
Transmit Flag (TXIE Bit) ............................................. 19
Transmit Shift Register Status (TRMT Bit).................. 61
TXREG Register ......................................................... 13
TXSTA Register.......................................................... 61
W
W Register .......................................................................... 91
Wake-up from SLEEP................................................... 81, 93
Interrupts............................................................... 86, 87
MCLR Reset ............................................................... 87
1998 Microchip Technology Inc.
DS30605A-page 145
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 146
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
980106
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1998 Microchip Technology Inc.
DS30605A-page 147
PIC16C63A/65B/73B/74B
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
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Application (optional):
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Literature Number:
DS30605A
Device:
PIC16C63A/65B/73B/74B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30605A-page 148
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Examples:
Frequency Temperature Package
Range Range
Pattern
a) PIC16C74B -04/P 301 = Commercial temp.,
PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b)
PIC16LC63A - 04I/SO = Industrial temp., SOIC
package, 200 kHz, Extended VDD limits.
Device
PIC16C6X(1), PIC16C6XT(2);VDD range 4.0V to 5.5V
PIC16LC6X(1), PIC16LC6XT(2);VDD range 2.5V to 5.5V
PIC16C7X(1), PIC16C7XT(2);VDD range 4.0V to 5.5V
PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V to 5.5V
c)
PIC16C65B - 20I/P = Industrial temp., PDIP
package, 20MHz, normal VDD limits.
Frequency Range
04
20
= 4 MHz
= 20 MHz
Note 1:
2:
C
= CMOS
LC = Low Power CMOS
T
= in tape and reel - SOIC, SSOP,
PLCC, QFP, TQ and FP
packages only.
Temperature Range
blank
I
E
=
=
=
0°C to
70°C (Commercial)
-40°C to +85°C (Industrial)
-40°C to +125°C (Extended)
Package
JW
PQ
PT
SO
SP
P
=
=
=
=
=
=
=
=
Windowed CERDIP
MQFP (Metric PQFP)
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
L
PLCC
SSOP
SS
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
1998 Microchip Technology Inc.
DS30605A-page 149
PIC16C63A/65B/73B/74B
NOTES:
DS30605A-page 150
1998 Microchip Technology Inc.
PIC16C63A/65B/73B/74B
NOTES:
1998 Microchip Technology Inc.
DS30605A-page 151
M
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
AMERICAS (continued)
Toronto
ASIA/PACIFIC (continued)
Singapore
Microchip Technology Inc.
Microchip Technology Inc.
Microchip Technology Singapore Pte Ltd.
2355 West Chandler Blvd.
5925 Airport Road, Suite 200
200 Middle Road
Chandler, AZ 85224-6199
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Tel: 602-786-7200 Fax: 602-786-7277
Technical Support: 602 786-7627
Web: http://www.microchip.com
ASIA/PACIFIC
Hong Kong
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Atlanta
Microchip Technology Inc.
Microchip Asia Pacific
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tung Hua North Road
Taipei, Taiwan, ROC
RM 3801B, Tower Two
Metroplaza
Tel: 770-640-0034 Fax: 770-640-0307
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Boston
Microchip Technology Inc.
EUROPE
5 Mount Royal Avenue
Marlborough, MA 01752
India
Microchip Technology Inc.
United Kingdom
Arizona Microchip Technology Ltd.
Tel: 508-480-9990 Fax: 508-480-8575
India Liaison Office
505 Eskdale Road
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Winnersh Triangle
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Berkshire, England RG41 5TU
Tel: 44-1189-21-5858 Fax: 44-1189-21-5835
Chicago
Microchip Technology Inc.
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Itasca, IL 60143
Japan
Microchip Technology Intl. Inc.
Benex S-1 6F
Tel: 630-285-0071 Fax: 630-285-0075
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Zone Industrielle de la Bonde
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Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 972-991-7177 Fax: 972-991-8588
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Germany
Arizona Microchip Technology GmbH
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Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
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Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
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Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Italy
Detroit
Microchip Technology Inc.
42705 Grand River, Suite 201
Novi, MI 48375-1727
Tel: 248-374-1888 Fax: 248-374-2874
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-39-6899939 Fax: 39-39-6899883
Los Angeles
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
7/7/98
Tel: 714-263-1888 Fax: 714-263-1338
Microchip received ISO 9001 Quality
System certification for its worldwide
headquarters, design, and wafer
fabrication facilities in January, 1997.
Our field-programmable PICmicro™
8-bit MCUs, Serial EEPROMs,
related specialty memory products
and development systems conform
to the stringent quality standards of
the International Standard
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 516-273-5305 Fax: 516-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Organization (ISO).
All rights reserved. © 1998, Microchip Technology Incorporated, USA. 8/98
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no
liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use
or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or
otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS30605A-page 152
1998 Microchip Technology Inc.
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