PIC16C71A-10I/SS [MICROCHIP]
8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20, 0.209 INCH, PLASTIC, SSOP-20;
| 型号： | PIC16C71A-10I/SS |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, OTPROM, 10 MHz, RISC MICROCONTROLLER, PDSO20, 0.209 INCH, PLASTIC, SSOP-20 可编程只读存储器 时钟 光电二极管 外围集成电路 |
| 文件： | 总308页 (文件大小：2351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C7X
8-Bit CMOS Microcontrollers with A/D Converter
• Low-power, high-speed CMOS EPROM
technology
Devices included in this data sheet:
• PIC16C70
• PIC16C71
• PIC16C71A
• PIC16C72
• PIC16C73
• PIC16C73A
• PIC16C74
• PIC16C74A
• Fully static design
• Wide operating voltage range: 3.0V to 6.0V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Automotive Tempera-
ture Range
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
PIC16C7X Microcontroller Core Features:
PIC16C7X Peripheral Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• Timer0: 8-bit timer/counter with 8-bit prescaler
• All single cycle instructions (200 ns) except for
program branches which are two cycle
• Timer1: 16-bit timer/counter. TMR1 can be incre-
mented during sleep via external crystal/clock
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Timer2: 8-bit timer/counter with 8-bit period regis-
ter, prescaler and postscaler
• Interrupt capability
• Capture, Compare, PWM module(s)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Capture is 16-bit, max. resolution 12.5 ns, com-
pare is 16-bit, max. resolution 200 ns, max. PWM
resolution is 10-bit
• Synchronous Serial Port (SSP) with SPI
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
2
and I C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Parallel Slave Port (PSP) 8-bit wide, with external
RD, WR and CS controls
• Programmable code-protection
• Power saving SLEEP mode
• Brown-out detection circuitry for Brown-out Reset
(BOR)
• Selectable oscillator options
• 8-bit multichannel analog-to-digital converter
PIC16C7X Features
70
71
71A
72
73
73A
74
74A
Program Memory (EPROM)
Data Memory (Bytes)
I/O Pins
512
36
13
—
—
1
1K
36
13
—
—
1
1K
68
13
—
—
1
2K
128
22
—
1
4K
192
22
—
2
4K
192
22
—
2
4K
192
33
Yes
2
4K
192
33
Yes
2
Parallel Slave Port
Capture/Compare/PWM Modules
Timer Modules
3
3
3
3
3
A/D Channels
4
4
4
5
5
5
8
8
2
2
2
2
2
Serial Communication
—
—
—
SPI/I C SPI/I C,
USART
SPI/I C,
SPI/I C,
SPI/I C,
USART
USART
Yes
—
USART
In-Circuit Serial Programming
Brown-out Reset
Yes Yes Yes
Yes
Yes
8
Yes
—
Yes
Yes
Yes
4
—
4
Yes
4
Yes
Yes
Interrupt Sources
11
11
12
12
2
I C is a trademark of Philips Corporation. SPI is a trademark of Motorola Corporation.
1995 Microchip Technology Inc.
DS30390B-page 1
PIC16C7X
Pin Diagrams
SSOP
PDIP, SOIC, Windowed CERDIP
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
• 1
2
18
17
16
15
14
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
• 1
2
20
19
18
17
16
RA1/AN1
RA0/AN0
RA0/AN0
3
OSC1/CLKIN
OSC2/CLKOUT
VDD
3
OSC1/CLKIN
OSC2/CLKOUT
VDD
4
4
5
5
RB0/INT
RB1
6
7
8
13
12
11
RB7
RB6
RB5
VSS
RB0/INT
RB1
6
7
8
15
14
13
VDD
RB7
RB6
RB2
RB3
RB2
9
10
RB4
9
12
11
RB5
RB4
RB3
10
PDIP, SOIC, Windowed CERDIP
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
• 1
2
18
17
16
15
14
RA1/AN1
RA0/AN0
3
OSC1/CLKIN
OSC2/CLKOUT
VDD
4
5
RB0/INT
RB1
6
7
8
13
12
11
RB7
RB6
RB5
RB2
RB3
9
10
RB4
SSOP
PDIP, SOIC, Windowed CERDIP
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
• 1
2
18
17
16
15
14
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
MCLR/VPP
VSS
• 1
2
20
19
18
17
16
RA1/AN1
RA0/AN0
RA0/AN0
3
OSC1/CLKIN
OSC2/CLKOUT
VDD
3
OSC1/CLKIN
OSC2/CLKOUT
VDD
4
4
5
5
RB0/INT
RB1
6
7
8
13
12
11
RB7
RB6
RB5
VSS
RB0/INT
RB1
6
7
8
15
14
13
VDD
RB7
RB6
RB2
RB3
RB2
9
10
RB4
9
12
11
RB5
RB4
RB3
10
SDIP, SOIC, Windowed Side Brazed Ceramic
SSOP
MCLR/VPP
RA0/AN0
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
MCLR/VPP
RA0/AN0
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
RA1/AN1
3
RA1/AN1
3
RA2/AN2
4
RA2/AN2
4
RA3/AN3/VREF
5
RA3/AN3/VREF
5
RA4/T0CKI
RA5/AN4/SS
VSS
6
7
8
23
22
21
RB2
RA4/T0CKI
RA5/AN4/SS
VSS
6
7
8
23
22
21
RB2
RB1
RB1
RB0/INT
RB0/INT
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
9
20
19
18
17
16
15
VDD
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
9
20
19
18
17
16
15
VDD
10
11
12
13
14
VSS
10
11
12
13
14
VSS
RC7
RC7
RC6
RC6
RC2/CCP1
RC5/SDO
RC4/SDI/SDA
RC2/CCP1
RC5/SDO
RC4/SDI/SDA
RC3/SCK/SCL
RC3/SCK/SCL
DS30390B-page 2
1995 Microchip Technology Inc.
PIC16C7X
Pin Diagrams (Cont.’d)
SDIP, SOIC, Windowed Side Brazed Ceramic
MQFP
MCLR/VPP
RA0/AN0
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
RA1/AN1
3
RA2/AN2
4
RA3/AN3/VREF
5
NC
RA4/T0CKI
RA5/AN4/SS
VSS
6
7
8
23
22
21
RB2
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
1
2
3
4
5
6
7
8
33
32
31
30
29
28
27
26
25
24
23
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
RB1
RB0/INT
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
9
20
19
18
17
16
15
VDD
VDD
10
11
12
13
14
VSS
PIC16C74
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS
RA4/T0CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
9
10
11
RB2
RB3
RC3/SCK/SCL
PLCC
MQFP
TQFP
NC
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
1
2
3
4
5
6
33
32
31
30
29
28
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB3
RB2
RB1
RB0/INT
VDD
7
8
9
39
38
37
36
35
34
33
32
31
30
29
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
10
11
12
13
14
15
16
17
VDD
VSS
7
8
9
10
PIC16C74A 27
VDD
RB0/INT
RB1
RB2
RB3
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4/SS
RA4/T0CKI
PIC16C74
PIC16C74A
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
26
25
24
23
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
11
PDIP, Windowed CERDIP
MCLR/VPP
RA0/AN0
1
2
3
4
5
6
7
8
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
RB1
RB0/INT
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
1995 Microchip Technology Inc.
DS30390B-page 3
PIC16C7X
Table of Contents
1.0 General Description................................................................................................................................................5
2.0 PIC16C7X Device Varieties....................................................................................................................................7
3.0 Architectural Overview............................................................................................................................................9
4.0 Memory Organization ...........................................................................................................................................21
5.0 I/O Ports ...............................................................................................................................................................43
6.0 Overview of Timer Modules..................................................................................................................................57
7.0 Timer0 Module......................................................................................................................................................59
8.0 Timer1 Module......................................................................................................................................................65
9.0 Timer2 Module......................................................................................................................................................69
10.0 Capture/Compare/PWM Module(s) ......................................................................................................................71
11.0 Synchronous Serial Port (SSP) Module ...............................................................................................................77
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ...............................................................93
13.0 Analog-to-Digital Converter (A/D) Module..........................................................................................................109
14.0 Special Features of the CPU..............................................................................................................................121
15.0 Instruction Set Summary ....................................................................................................................................141
16.0 Development Support.........................................................................................................................................153
17.0 Electrical Characteristics for PIC16C70 and PIC16C71A ..................................................................................159
18.0 DC and AC Characteristics Graphs and Tables for PIC16C70 and PIC16C71A................................................173
19.0 Electrical Characteristics for PIC16C71 .............................................................................................................175
20.0 DC and AC Characteristics Graphs and Tables for PIC16C71...........................................................................189
21.0 Electrical Characteristics for PIC16C72 .............................................................................................................197
22.0 DC and AC Characteristics Graphs and Tables for PIC16C72...........................................................................217
23.0 Electrical Characteristics for PIC16C73/74 ........................................................................................................219
24.0 DC and AC Characteristics Graphs and Tables for PIC16C73/74......................................................................241
25.0 Electrical Characteristics for PIC16C73A/74A....................................................................................................243
26.0 DC and AC Characteristics Graphs and Tables for PIC16C73A/74A .................................................................265
27.0 Packaging Information........................................................................................................................................267
Appendix A:.................................................................................................................................................................283
Appendix B: Compatibility ...........................................................................................................................................283
Appendix C: What’s New.............................................................................................................................................284
Appendix D: What’s Changed .....................................................................................................................................284
Appendix E: PIC16/17 Microcontrollers.......................................................................................................................285
Index...................................................................................................................................................................293
Connecting to Microchip BBS.............................................................................................................................303
Reader Response...............................................................................................................................................304
Product Information System ...............................................................................................................................305
For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As
an example, the legend below would mean that the following section applies only to the PIC16C71A, PIC16C72,
PIC16C73A and PIC16C74A devices.
Applicable Devices
70 71 71A 72 73 73A 74 74A
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30390B-page 4
1995 Microchip Technology Inc.
PIC16C7X
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
Inter-Integrated Circuit (I C) bus. The Universal Syn-
1.0
GENERAL DESCRIPTION
The PIC16C7X is a family of low-cost, high-perfor-
mance, CMOS, fully-static, 8-bit microcontrollers with
integrated analog-to-digital (A/D) converters, in the
PIC16CXX mid-range family.
2
chronous
Asynchronous
Receiver
Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. An 8-bit Parallel Slave Port is pro-
vided. Also an 8-channel high-speed 8-bit A/D is pro-
vided. The 8-bit resolution is ideally suited for
applications requiring low-cost analog interface, e.g.
thermostat control, pressure sensing, etc.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller fam-
ily has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available.Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
The PIC16C7X family has special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low-cost solution, the LP oscil-
lator minimizes power consumption, XT is a standard
crystal, and the HS is for High Speed crystals. The
SLEEP (power-down) feature provides a power saving
mode. The user can wake up the chip from SLEEP
through several external and internal interrupts and
reset(s).
PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
The PIC16C70/71 devices have 36 bytes of RAM, and
the PIC16C71A has 68 bytes of RAM. The
PIC16C70/71/71Adevices have 13 I/O pins. In addition
a timer/counter is available. Also a 4-channel high-
speed 8-bit A/D is provided. The 8-bit resolution is ide-
ally suited for applications requiring low-cost analog
interface, e.g. thermostat control, pressure sensing,
etc.
A UV erasable CERDIP packaged version is ideal for
code development while the cost-effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
The PIC16C7X family fits perfectly in applications rang-
ing from security and remote sensors to appliance con-
trol and automotive. The EPROM technology makes
customization of application programs (transmitter
codes, motor speeds, receiver frequencies, etc.)
extremely fast and convenient. The small footprint
packages make this microcontroller series perfect for
all applications with space limitations. Low cost, low
power, high performance, ease of use and I/O flexibility
make the PIC16C7X very versatile even in areas
where no microcontroller use has been considered
before (e.g. timer functions, serial communication, cap-
ture and compare, PWM functions and coprocessor
applications).
The PIC16C72 device has 128 bytes of RAM and 22
I/O pins. In addition several peripheral features are
available including: three timer/counters, one Cap-
ture/Compare/PWM module and one serial port. The
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
2
Inter-Integrated Circuit (I C) bus. Also a 5-channel
high-speed 8-bit A/D is provided. The 8-bit resolution
is ideally suited for applications requiring low-cost ana-
log interface, e.g. thermostat control, pressure sens-
ing, etc.
The PIC16C73/73A devices have 192 bytes of RAM
and 22 I/O pins. In addition, several peripheral features
are available including: three timer/counters, two Cap-
ture/Compare/PWM modules and two serial ports. The
Synchronous Serial Port can be configured as either a
3-wire Serial Peripheral Interface (SPI) or the two-wire
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller fam-
ily will realize that this is an enhanced version of the
PIC16C5X architecture. Please refer to Appendix A for
a detailed list of enhancements. Code written for the
PIC16C5X can be easily ported to the PIC16CXX fam-
ily of devices (Appendix B).
2
Inter-Integrated Circuit (I C) bus. The Universal Syn-
chronous
Asynchronous
Receiver
Transmitter
(USART) is also known as the Serial Communications
Interface or SCI. Also a 5-channel high-speed 8-bit A/D
is provided.The 8-bit resolution is ideally suited for
applications requiring low-cost analog interface, e.g.
thermostat control, pressure sensing, etc.
1.2
Development Support
The PIC16CXX family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available. (Section 16.0)
The PIC16C74/74A devices have 192 bytes of RAM
and 33 I/O pins. In addition several peripheral features
are available including: three timer/counters, two Cap-
ture/Compare/PWM modules and two serial ports. The
1995 Microchip Technology Inc.
DS30390B-page 5
PIC16C7X
TABLE 1-1:
PIC16C7X FAMILY OF DEVICES
DS30390B-page 6
1995 Microchip Technology Inc.
PIC16C7X
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC16C7X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C7X Product Selec-
tion System section at the end of this data sheet. When
placing orders, please use that page of the data sheet
to specify the correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
For the PIC16C7X family, there are two device “types”
as indicated in the device number:
1. C, as in PIC16C74. These devices have
EPROM type memory and operate over the
standard voltage range.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
2. LC, as in PIC16LC74. These devices have
EPROM type memory and operate over an
extended voltage range.
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random or sequential.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot pro-
grams.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
The UV erasable version can be erased and repro-
grammed to any of the configuration modes.
Microchip's PICSTART and PRO MATE program-
mers both support the PIC16C7X. Third party program-
mers also are available; refer to the Microchip Third
Party Guide for a list of sources.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1995 Microchip Technology Inc.
DS30390B-page 7
PIC16C7X
NOTES:
DS30390B-page 8
1995 Microchip Technology Inc.
PIC16C7X
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
over traditional von Neumann architecture where pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, all instructions (35)
execute in a single cycle (200 ns @ 20 MHz) except for
program branches.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
The table below lists program memory (EPROM) and
data memory (RAM) for each PIC16C7X device.
Program
Memory
Device
Data Memory
PIC16C70
PIC16C71
PIC16C71A
PIC16C72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
512 x 14
1K x 14
1K x 14
2K x 14
4K x 14
4K x 14
4K x 14
4K x 14
36 x 8
36 x 8
68 x 8
128 x 8
192 x 8
192 x 8
192 x 8
192 x 8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
1995 Microchip Technology Inc.
DS30390B-page 9
PIC16C7X
FIGURE 3-1: PIC16C70/71/71A BLOCK DIAGRAM
Device
Program Memory Data Memory (RAM)
PIC16C70
PIC16C71
PIC16C71A
512 x 14
1K x 14
1K x 14
36 x 8
36 x 8
68 x 8
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Program
Memory
RAM
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
RAM Addr (1)
PORTB
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
8
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
8
Power-on
Reset
Timing
Generation
W reg
Watchdog
Timer
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset(2)
Timer0
MCLR VDD, VSS
A/D
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C71.
DS30390B-page 10
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 3-2: PIC16C72 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
Program
Memory
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RAM
File
Registers
8 Level Stack
2K x 14
(13-bit)
128 x 8
Program
14
RAM Addr(1)
PORTB
Bus
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6
RC7
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
MCLR VDD, VSS
Timer0
Timer1
Timer2
Synchronous
Serial Port
A/D
CCP1
Note 1: Higher order bits are from the STATUS register.
1995 Microchip Technology Inc.
DS30390B-page 11
PIC16C7X
FIGURE 3-3: PIC16C73/73A BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
Program
RA1/AN1
Memory
RA2/AN2
RAM
File
Registers
8 Level Stack
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
4K x 14
(13-bit)
192 x 8
Program
14
RAM Addr(1)
PORTB
Bus
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset(2)
MCLR VDD, VSS
Timer2
Timer0
CCP1
Timer1
CCP2
A/D
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C73.
DS30390B-page 12
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 3-4: PIC16C74/74A BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
Program
Memory
RAM
File
Registers
8 Level Stack
4K x 14
(13-bit)
192 x 8
Program
14
RAM Addr (1)
PORTB
Bus
9
Addr MUX
Instruction reg
RB0/INT
RB7:RB1
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
PORTD
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset(2)
RD7/PSP7:RD0/PSP0
PORTE
Parallel Slave Port
MCLR VDD, VSS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
Timer0
CCP1
Timer1
CCP2
Timer2
A/D
Synchronous
Serial Port
USART
Note 1: Higher order bits are from the STATUS register.
2: Brown-out Reset is not available on the PIC16C74.
1995 Microchip Technology Inc.
DS30390B-page 13
PIC16C7X
TABLE 3-1:
PIC16C70/71A PINOUT DESCRIPTION
DIP SSOP SOIC I/O/P
Buffer
Type
Pin Name
Description
Pin# Pin#
Pin#
Type
(3)
OSC1/CLKIN
16
18
17
16
15
I
Oscillator crystal input/external clock source input.
ST/CMOS
—
OSC2/CLKOUT 15
O
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
4
4
4
I/P
ST
Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
Analog input0
RA0/AN0
17
18
1
19
20
1
17
18
1
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1/AN1
Analog input1
RA2/AN2
Analog input2
RA3/AN3/VREF
RA4/T0CKI
2
2
2
Analog input3/VREF
3
3
3
Can also be selected to be the clock input to the Timer0 module.
Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
(1)
RB0/INT
6
7
7
8
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
TTL/ST
TTL
RB0/INT can also be selected as an external interrupt pin.
RB1
RB2
8
9
8
TTL
RB3
9
10
11
12
13
14
4, 6
9
TTL
RB4
10
11
12
13
5
10
11
12
13
5
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
—
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
(2)
RB7
VSS
VDD
14 15, 16
O = output
— = Not used
14
P
—
Legend: I = input
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30390B-page 14
1995 Microchip Technology Inc.
PIC16C7X
TABLE 3-2:
PIC16C71 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
16
15
16
15
I
Oscillator crystal input/external clock source input.
ST/CMOS
—
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
4
4
I/P
ST
Master clear (reset) input/programming voltage input. This pin is an
active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
Analog input0
RA0/AN0
17
18
1
17
18
1
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1/AN1
Analog input1
RA2/AN2
Analog input2
RA3/AN3/VREF
RA4/T0CKI
2
2
Analog input3/VREF
3
3
Can also be selected to be the clock input to the Timer0 module.
Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software pro-
grammed for internal weak pull-up on all inputs.
(1)
RB0/INT
6
7
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
TTL/ST
TTL
RB0/INT can also be selected as an external interrupt pin.
RB1
RB2
8
8
TTL
RB3
9
9
TTL
RB4
10
11
12
13
5
10
11
12
13
5
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
—
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
(2)
RB7
VSS
VDD
14
14
P
—
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1995 Microchip Technology Inc.
DS30390B-page 15
PIC16C7X
TABLE 3-3:
PIC16C72 PINOUT DESCRIPTION
DIP SSOP SOIC
I/O/P
Type
Buffer
Type
Pin Name
Description
Pin# Pin#
Pin#
(3)
OSC1/CLKIN
9
9
9
I
Oscillator crystal input/external clock source input.
ST/CMOS
—
OSC2/CLKOUT
10
10
10
O
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
1
1
1
I/P
ST
Master clear (reset) input/programming voltage input. This pin
is an active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
Analog input0
RA0/AN0
2
3
4
5
6
2
3
4
5
6
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1/AN1
Analog input1
RA2/AN2
Analog input2
RA3/AN3/VREF
RA4/T0CKI
Analog input3/VREF
Can also be selected to be the clock input to the Timer0
module. Output is open drain type.
RA5/AN4/SS
7
7
7
I/O
TTL
Analog input4 can also be the slave select for the syn-
chronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0/INT can also be selected as an external interrupt pin.
RB2
TTL
RB3
TTL
RB4
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
(2)
RB7
RC0/T1OSO/T1CKI
RC1/T1OSI
11
12
11
12
11
12
I/O
I/O
ST
ST
RC0/T1OSO/T1CKI can also be selected as a Timer1
oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 can also be selected as a Timer1
oscillator input or Capture2, input/Compare2 output/
PWM2 output.
RC2/CCP1
13
14
15
16
13
14
15
16
13
14
15
16
I/O
I/O
I/O
I/O
ST
ST
ST
ST
RC2/CCP1 can also be selected as a Capture1 input/
Compare1 output/PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3/SCK/SCL can also be selected as the synchronous
2
serial clock input/output for both SPI and I C modes.
RC4/SDI/SDA can also be selected as the SPI Data In
2
(SPI mode) or data I/O (I C mode).
RC5/SDO can also be selected as the SPI Data Out (SPI
mode).
RC6
17
18
17
18
17
18
I/O
I/O
P
ST
ST
—
RC7
VSS
8, 19 8, 19
20 20
8, 19
20
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
P
—
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30390B-page 16
1995 Microchip Technology Inc.
PIC16C7X
TABLE 3-4:
PIC16C73/73A PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
Oscillator crystal input/external clock source input.
ST/CMOS
—
OSC2/CLKOUT
10
10
O
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
1
1
I/P
ST
Master clear (reset) input/programming voltage input. This pin
is an active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
Analog input0
RA0/AN0
2
3
4
5
6
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1/AN1
Analog input1
RA2/AN2
Analog input2
RA3/AN3/VREF
RA4/T0CKI
Analog input3/VREF
Can also be selected to be the clock input to the Timer0
module. Output is open drain type.
RA5/AN4/SS
7
7
I/O
TTL
Analog input4 can also be the slave select for the syn-
chronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
RB1
21
22
23
24
25
26
27
28
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST
TTL
RB0/INT can also be selected as an external interrupt pin.
RB2
TTL
RB3
TTL
RB4
TTL
Interrupt on change pin.
RB5
TTL
Interrupt on change pin.
(2)
RB6
TTL/ST
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
(2)
RB7
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
11
12
11
12
I/O
I/O
ST
ST
RC0/T1OSO/T1CKI can also be selected as a Timer1
oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2 can also be selected as a Timer1
oscillator input or Capture2 input/Compare2 output/
PWM2 output.
RC2/CCP1
13
14
15
16
17
18
13
14
15
16
17
18
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
RC2/CCP1 can also be selected as a Capture1 input/
Compare1 output/PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3/SCK/SCL can also be selected as the synchronous
2
serial clock input/output for both SPI and I C modes.
RC4/SDI/SDA can also be selected as the SPI Data In
2
(SPI mode) or data I/O (I C mode).
RC5/SDO can also be selected as the SPI Data Out (SPI
mode).
RC6/TX/CK
RC7/RX/DT
RC6/TX/CK can also be selected as Asynchronous
Transmit or USART Synchronous Clock.
RC7/RX/DT can also be selected as the Asynchronous
Receive or USART Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1995 Microchip Technology Inc.
DS30390B-page 17
PIC16C7X
TABLE 3-5:
PIC16C74/74A PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP I/O/P
Pin# Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
ST/CMOS
—
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (reset) input/programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
Analog input0
RA0/AN0
2
3
4
5
6
3
4
5
6
7
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA1/AN1
Analog input1
RA2/AN2
Analog input2
RA3/AN3/VREF
RA4/T0CKI
Analog input3/VREF
Can also be selected to be the clock input to the
Timer0 timer/counter. Output is open drain type.
RA5/AN4/SS
7
8
24
I/O
TTL
Analog input4 can also be the slave select for the syn-
chronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
33
36
8
I/O
TTL/ST
RB0/INT can also be selected as an external interrupt
pin.
RB1
RB2
RB3
RB4
RB5
RB6
34
35
36
37
38
39
40
37
38
39
41
42
43
44
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
10
11
14
15
16
17
TTL
TTL
Interrupt on change pin.
TTL
Interrupt on change pin.
(2)
TTL/ST
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
(2)
RB7
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
DS30390B-page 18
1995 Microchip Technology Inc.
PIC16C7X
TABLE 3-5:
PIC16C74/74A PINOUT DESCRIPTION (Cont.’d)
DIP
Pin#
PLCC
Pin#
QFP I/O/P
Pin# Type
Buffer
Type
Pin Name
Description
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
15
16
16
18
32
35
I/O
I/O
ST
ST
RC0/T1OSO/T1CKI can also be selected as a Timer1
oscillator output or a Timer1 clock input.
RC1/T1OSI/CCP2 can also be selected as a Timer1
oscillator input or Capture2 input/Compare2 output/
PWM2 output.
RC2/CCP1
17
18
19
20
36
37
I/O
I/O
ST
ST
RC2/CCP1 can also be selected as a Capture1 input/
Compare1 output/PWM1 output.
RC3/SCK/SCL
RC3/SCK/SCL can also be selected as the synchro-
2
nous serial clock input/output for both SPI and I C
modes.
RC4/SDI/SDA
RC5/SDO
23
24
25
26
25
26
27
29
42
43
44
1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
RC4/SDI/SDA can also be selected as the SPI Data In
(SPI mode) or data I/O (I C mode).
2
RC5/SDO can also be selected as the SPI Data Out
(SPI mode).
RC6/TX/CK
RC7/RX/DT
RC6/TX/CK can also be selected as Asynchronous
Transmit or USART Synchronous Clock.
RC7/RX/DT can also be selected as the Asynchro-
nous Receive or USART Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
9
9
25
26
27
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
RE0/RD/AN5 read control for parallel slave port, or
analog input5.
10
11
RE1/WR/AN6 write control for parallel slave port, or
analog input6.
10
RE2/CS/AN7 select control for parallel slave port, or
analog input7.
VSS
VDD
NC
12,31
11,32
—
13,34
12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins should
be left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
1995 Microchip Technology Inc.
DS30390B-page 19
PIC16C7X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
is shown in Figure 3-5.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-5: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30390B-page 20
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 4-2: PIC16C71/71A PROGRAM
MEMORY MAP AND STACK
4.0
MEMORY ORGANIZATION
Applicable Devices
70 71 71A 72 73 73A 74 74A
4.1
Program Memory Organization
PC<12:0>
The PIC16C7X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space.
CALL, RETURN
RETFIE, RETLW
13
For the PIC16C70, only the first 512 x 14 (0000h-
01FFh) is physically implemented. For the
PIC16C71/71A only the first 1K x 14 (0000h-03FFh) is
implemented. For the PIC16C72, only the first 2K x 14
(0000h-07FF) is implemented. For the PIC16C73,
PIC16C73A, PIC16C74, and PIC16C74A, only the first
4K x 14 (0000h-0FFFh) is physically implemented.
Accessing a location above the physically implemented
address will cause a wraparound. The reset vector is at
0000h and the interrupt vector is at 0004h.
Stack Level 1
Stack Level 8
Reset Vector
0000h
FIGURE 4-1: PIC16C70 PROGRAM
MEMORY MAP AND STACK
Interrupt Vector
0004h
0005h
On-chip Program
Memory
03FFh
0200h
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
0000h
Interrupt Vector
0004h
0005h
On-chip Program
Memory
01FFh
0200h
1FFFh
1995 Microchip Technology Inc.
DS30390B-page 21
PIC16C7X
FIGURE 4-3: PIC16C72 PROGRAM
MEMORY MAP AND STACK
FIGURE 4-4: PIC16C73/73A/74/74A
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Stack Level 1
Stack Level 8
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
On-chip Program
Memory
07FFh
0800h
On-chip Program
Memory (Page 1)
07FFh
0800h
0FFFh
1000h
1FFFh
1FFFh
4.2
Data Memory Organization
Applicable Devices
70 71 71A 72 73 73A 74 74A
The data memory is partitioned into two Banks which
contain the General Purpose Registers and the Special
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
Each Bank extends up to 7Fh (128 bytes). The lower
locations of each Bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers. Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 for code
reduction and quicker access.
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
(Section 4.5).
DS30390B-page 22
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 4-5: PIC16C70/71 REGISTER FILE
MAP
FIGURE 4-6: PIC16C71A REGISTER FILE
MAP
File
Address
File
Address
File
Address
File
Address
(1)
(1)
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
TMR0
PCL
OPTION
PCL
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
PORTA
PORTB
TRISA
TRISB
TRISB
(2)
PCON
PCON
ADCON1
ADCON0
ADRES
ADCON1
ADCON0
ADRES
ADRES
ADRES
PCLATH
INTCON
PCLATH
INTCON
PCLATH
INTCON
PCLATH
INTCON
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
Mapped
Mapped
(3)
(2)
in Bank 0
in Bank 0
AFh
B0h
CFh
D0h
2Fh
30h
4Fh
50h
FFh
FFh
7Fh
7Fh
Bank 0
Bank 1
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
Note 1: Not a physical register.
2: The PCON register is not implemented on the
PIC16C71.
3: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
2: These locations are unimplemented in Bank 1.
Any access to these locations will access the
corresponding Bank 0 register.
1995 Microchip Technology Inc.
DS30390B-page 23
PIC16C7X
FIGURE 4-7: PIC16C72 REGISTER FILE
MAP
FIGURE 4-8: PIC16C73/73A/74/74A
REGISTER FILE MAP
File
File
File
File
Address
Address
Address
Address
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
(1)
(1)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
INDF
INDF
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
OPTION
PCL
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
(2)
(2)
08h PORTD
09h PORTE
TRISD
(2)
(2)
TRISE
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
PCLATH
PCLATH
INTCON
PIE1
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
INTCON
PIR1
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
PR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
PR2
SSPADD
SSPSTAT
SSPADD
SSPSTAT
17h CCP1CON
17h CCP1CON
18h
19h
1Ah
1Bh
1Ch
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
TXSTA
18h
19h
1Ah
1Bh
1Ch
1Dh
SPBRG
1Dh CCP2CON
1Eh
1Fh
20h
ADRES
1Eh
1Fh
20h
ADRES
ADCON0
ADCON1
ADCON0
ADCON1
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
BFh
C0h
FFh
7Fh
Bank 0
Bank 1
FFh
7Fh
Bank 0
Bank 1
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
2: These registers are not physically imple-
mented on the PIC16C73/73A, read as '0'.
DS30390B-page 24
1995 Microchip Technology Inc.
PIC16C7X
4.2.2
SPECIAL FUNCTION REGISTERS
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral fea-
ture.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
PIC16C70/71/71A SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
other resets
(1)
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
01h
TMR0
PCL
02h(3)
03h(3)
Program Counter's (PC) Least Significant Byte
IRP(5)
RP1(5)
STATUS
RP0
Indirect data memory address pointer
TO
PD
Z
DC
C
04h(3)
05h
FSR
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
xxxx xxxx uuuu uuuu
PORTA
PORTB
—
—
—
—
PORTA Data Latch when written: PORTA pins when read
06h
PORTB Data Latch when written: PORTB pins when read
Unimplemented
07h
—
—
08h
ADCON0
ADRES
ADCS1
ADCS0
(6)
CHS1
CHS0
GO/DONE
ADIF
ADON
00-0 0000 00-0 0000
xxxx xxxx uuuu uuuu
09h(3)
A/D Result Register
0Ah(2,3)
PCLATH
INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
0Bh(3)
GIE
ADIE
T0IE
Bank 1
80h(3)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
RP0 TO
Indirect data memory address pointer
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(3)
83h(3)
IRP(5)
RP1(5)
STATUS
PD
Z
DC
C
84h(3)
85h
FSR
xxxx xxxx uuuu uuuu
---1 1111 ---1 1111
1111 1111 1111 1111
---- --qq ---- --uu
---- --00 ---- --00
xxxx xxxx uuuu uuuu
TRISA
TRISB
PCON
ADCON1
ADRES
—
—
—
PORTA Data Direction Register
86h
PORTB Data Direction Control Register
87h(4)
88h
—
—
—
—
—
—
—
—
—
—
—
—
POR
BOR
PCFG1
PCFG0
89h(3)
A/D Result Register
8Ah(2,3)
8Bh(3)
PCLATH
INTCON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
GIE
ADIE
T0IE
Legend: x= unknown, u= unchanged, q= value depends on condition, -= unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: These registers can be addressed from either bank.
4: The PCON register is not physically implemented in the PIC16C71, read as ’0’.
5: The IRP and RP1 bits are reserved on the PIC16C7X, always maintain these bits clear.
6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C71 only. For the PIC16C70/71A, this bit is unimplemented,
read as '0'.
1995 Microchip Technology Inc.
DS30390B-page 25
PIC16C7X
TABLE 4-2:
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
other resets
(3)
Bank 0
00h(1)
01h
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
02h(1)
03h(1)
04h(1)
05h
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP(4)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1(4)
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
—
—
—
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
Unimplemented
07h
08h
—
—
—
—
09h
—
Unimplemented
0Ah(1,2) PCLATH
—
GIE
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
0Bh(1)
0Ch
0Dh
0Eh
0Fh
10h
11h
INTCON
PIR1
PEIE
ADIF
INTE
—
RBIE
T0IF
INTF
RBIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
—
Unimplemented
—
—
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Timer2 module’s register
0000 0000 0000 0000
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register (LSB)
Capture/Compare/PWM Register (MSB)
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADRES
ADCON0
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C7X, always maintain these bits clear.
DS30390B-page 26
1995 Microchip Technology Inc.
PIC16C7X
TABLE 4-2:
Address Name
Bank 1
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on: Value on all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
other resets
(3)
80h(1)
81h
INDF
OPTION
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
RBPU
Program Counter's (PC) Least Significant Byte
IRP(4) RP1(4)
RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(1)
83h(1)
84h(1)
85h
STATUS
FSR
PD
Z
DC
C
TRISA
TRISB
TRISC
—
—
—
86h
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
87h
88h
—
—
—
—
89h
—
Unimplemented
8Ah(1,2) PCLATH
—
GIE
—
—
—
T0IE
—
Write Buffer for the upper 5 bits of the PC
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
8Bh(1)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INTCON
PEIE
ADIE
INTE
—
RBIE
T0IF
INTF
RBIF
PIE1
SSPIE
CCP1IE
TMR2IE
TMR1IE
—
Unimplemented
—
—
—
PCON
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PR2
Timer2 Period Register
Synchronous Serial Port (I2C mode) Address Register
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
SSPADD
SSPSTAT
—
—
D/A
P
S
R/W
UA
BF
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADCON1
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C7X, always maintain these bits clear.
1995 Microchip Technology Inc.
DS30390B-page 27
PIC16C7X
TABLE 4-3:
PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
other resets
(2)
Bank 0
00h(4)
01h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--xx xxxx --uu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TMR0
02h(4)
03h(4)
04h(4)
05h
PCL
Program Counter's (PC) Least Significant Byte
STATUS
FSR
IRP(7)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1(7)
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
PORTD
PORTE
—
—
06h
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
07h
08h(5)
09h(5)
—
—
—
—
—
—
—
—
RE2
RE1
RE0
0Ah(1,4) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
0Bh(4)
0Ch
0Dh
0Eh
0Fh
10h
11h
INTCON
PIR1
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
–
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(3)
—
TMR1IF
CCP2IF
PIR2
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
TMR1H
T1CON
TMR2
—
—
T1CKPS1
T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Timer2 module’s register
0000 0000 0000 0000
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
CHS2
CHS1
CHS0
GO/DONE
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C7X, always maintain these bits clear.
DS30390B-page 28
1995 Microchip Technology Inc.
PIC16C7X
TABLE 4-3:
Address Name
Bank 1
PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Value on: Value on all
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
other resets
(2)
80h(4)
81h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP(7) RP1(7)
RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
82h(4)
83h(4)
84h(4)
85h
STATUS
FSR
PD
Z
DC
C
TRISA
TRISB
TRISC
TRISD
TRISE
—
—
86h
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
87h
88h(5)
89h(5)
IBF
—
OBF
—
IBOV
—
PSPMODE
—
TRISE2
TRISE1
TRISE0
8Ah(1,4) PCLATH
Write Buffer for the upper 5 bits of the Program Counter
8Bh(4)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INTCON
PIE1
PIE2
PCON
—
GIE
PEIE
ADIE
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
SSPIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
PSPIE(3)
—
TMR1IE
CCP2IE
BOR(6)
—
—
—
—
—
—
POR
Unimplemented
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
PR2
SSPADD
SSPSTAT
—
Timer2 Period Register
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
Synchronous Serial Port (I2C mode) Address Register
—
—
D/A
P
S
R/W
UA
BF
Unimplemented
Unimplemented
Unimplemented
CSRC
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0
---- -000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
4: These registers can be addressed from either bank.
5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’.
6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'.
7: The IRP and RP1 bits are reserved on the PIC16C7X, always maintain these bits clear.
1995 Microchip Technology Inc.
DS30390B-page 29
PIC16C7X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
Applicable Devices
70 71 71A 72 73 73A 74 74A
The STATUS register, shown in Figure 4-9, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the PIC16C7X and should be
maintained clear. Use of these bits as
general purpose R/W bits is NOT recom-
mended, since this may affect upward
compatibility with future products.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
FIGURE 4-9: STATUS REGISTER (ADDRESS 03h, 83h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C7X, always maintain this bit clear.
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C7X, always maintain this bit clear.
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1 = After power-up, CLRWDTinstruction, or SLEEPinstruction
0 = A WDT time-out occurred
PD: Power-down bit
1 = After power-up or by the CLRWDTinstruction
0 = By execution of the SLEEPinstruction
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
DS30390B-page 30
1995 Microchip Technology Inc.
PIC16C7X
4.2.2.2
OPTION REGISTER
Applicable Devices
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer by setting bit PSA
(OPTION<3>).
70 71 71A 72 73 73A 74 74A
The OPTION register is a readable and writable regis-
ter which contains various control bits to configure the
TMR0/WDT prescaler, the External INT Interrupt,
TMR0, and the weak pull-ups on PORTB.
FIGURE 4-10: OPTION REGISTER (ADDRESS 81h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1995 Microchip Technology Inc.
DS30390B-page 31
PIC16C7X
4.2.2.3
INTCON REGISTER
Applicable Devices
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
70 71 71A 72 73 73A 74 74A
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/Int Pin interrupts.
FIGURE 4-11: INTCON REGISTER FOR PIC16C70/71/71A (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
ADIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
(1)
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables A/D interrupt
0 = Disables A/D interrupt
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C71 only, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be unin-
tentionally re-enabled by the RETFIEinstruction in the user’s Interrupt Service Routine. Refer to
Section 14.5 for a detailed description.
DS30390B-page 32
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 4-12: INTCON REGISTER FOR PIC16C72/73/73A/74/74A (ADDRESS 0Bh, 8Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
(1)
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C73 and PIC16C74 only, if an interrupt occurs while the GIE bit is being cleared, the GIE
bit may be unintentionally re-enabled by the RETFIEinstruction in the user’s Interrupt Service Routine.
Refer to Section 14.5 for a detailed description.
1995 Microchip Technology Inc.
DS30390B-page 33
PIC16C7X
4.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
Applicable Devices
70 71 71A 72 73 73A 74 74A
enable any peripheral interrupt.
This register contains the individual enable bits for the
Peripheral interrupts.
FIGURE 4-13: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)
U-0
—
R/W-0
ADIE
U-0
—
U-0
—
R/W-0
SSPIE
R/W-0
R/W-0
TMR2IE TMR1IE
bit0
R/W-0
CCP1IE
R
= Readable bit
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4: Unimplemented: Read as '0'
bit 3:
bit 2:
bit 1:
bit 0:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS30390B-page 34
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 4-14: PIE1 REGISTER PIC16C73/73A/74/74A (ADDRESS 8Ch)
R/W-0
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
TMR2IE TMR1IE
bit0
R/W-0
(1)
PSPIE
bit7
CCP1IE
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
(1)
bit 7:
PSPIE : Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C73 and PIC16C73A devices do not have a Parallel Slave Port implemented, this bit location is
reserved on these two devices, always maintain this bit clear.
1995 Microchip Technology Inc.
DS30390B-page 35
PIC16C7X
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Applicable Devices
70 71 71A 72 73 73A 74 74A
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 4-15: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch)
U-0
—
R/W-0
ADIF
U-0
—
U-0
—
R/W-0
SSPIF
R/W-0
R/W-0
TMR2IF TMR1IF
bit0
R/W-0
CCP1IF
R
= Readable bit
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4: Unimplemented: Read as '0'
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
DS30390B-page 36
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 4-16: PIR1 REGISTER PIC16C73/73A/74/74A (ADDRESS 0Ch)
R/W-0
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
TMR2IF TMR1IF
bit0
R/W-0
(1)
PSPIF
bit7
RCIF
TXIF
CCP1IF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C73 and PIC16C73A devices do not have a Parallel Slave Port implemented, this bit location is
reserved on these two devices, always maintain this bit clear.
1995 Microchip Technology Inc.
DS30390B-page 37
PIC16C7X
4.2.2.6
PIE2 REGISTER
Applicable Devices
70 71 71A 72 73 73A 74 74A
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
FIGURE 4-17: PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IE
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
DS30390B-page 38
1995 Microchip Technology Inc.
PIC16C7X
.
4.2.2.7
PIR2 REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
Applicable Devices
70 71 71A 72 73 73A 74 74A
This register contains the CCP2 interrupt flag bit.
FIGURE 4-18: PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IF
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-1: Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
1995 Microchip Technology Inc.
DS30390B-page 39
PIC16C7X
4.2.2.8
PCON REGISTER
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a don't care and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset. It
also contains a status bit to determine if a Brown-out
Reset (BOR) occurred.
FIGURE 4-19: PCON REGISTER (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-q
POR
R/W-q
(1)
BOR
R
= Readable bit
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR(1): Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: Brown-out Reset is not implemented on the PIC16C73/74.
DS30390B-page 40
1995 Microchip Technology Inc.
PIC16C7X
4.3
PCL and PCLATH
Applicable Devices
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
70 71 71A 72 73 73A 74 74A
Note 2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW, and RETFIE
instructions, or the vectoring to an inter-
rupt address.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any reset, the PC is cleared. Figure 4-20 shows the
two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). The lower exam-
ple in the figure shows how the PC is loaded during a
CALLor GOTOinstruction (PCLATH<4:3> → PCH).
4.4
Program Memory Paging
Applicable Devices
70 71 71A 72 73 73A 74 74A
The PIC16C73/73A and the PIC16C74/74A have 4K of
program memory, but the CALLand GOTOinstructions
only have a 11-bit address range. This 11-bit address
range allows a branch within a 2K program memory
page size. To allow CALL and GOTO instructions to
address the entire 4K program memory address range,
there must be another bit to specify the program mem-
ory page. This paging bit comes from the PCLATH<3>
bit (Figure 4-20). When doing a CALLor GOTOinstruc-
tion, the user must ensure that this page bit
(PCLATH<3>) is programmed so that the desired pro-
gram memory page is addressed. If a return from a
CALL instruction (or interrupt) is executed, the entire
13-bit PC is PUSHed onto the stack. Therefore, manip-
ulation of the PCLATH<3> is not required for the return
instructions (which POPs the address from the stack).
FIGURE 4-20: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
PC
Destination
8
PCLATH<4:0>
PCLATH
5
ALU result
PCH
12 11 10
PCL
8
7
0
GOTO, CALL
PC
PCLATH<4:3>
PCLATH
11
Note 1: The PIC16C70/71/71A/72 ignore both
paging bits (PCLATH<4:3>, which are
used to access program memory when
more than one page is available. The use
of PCLATH<4:3> as general purpose
read/write bits for the PIC16C7X is not
recommended since this may affect
upward compatibility with future products.
2
Opcode <10:0>
4.3.1
COMPUTED GOTO
Acomputed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
The PIC16C73/73A/74/74A ignores pag-
ing bit (PCLATH<4>), which is used to
access program memory pages 2 and 3
(1000h - 1FFFh). The use of PCLATH<4>
as a general purpose read/write bit is not
recommended since this may affect
upward compatibility with future products.
4.3.2
STACK
The PIC16CXX family has an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
1995 Microchip Technology Inc.
DS30390B-page 41
PIC16C7X
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt ser-
vice routine (if interrupts are used).
4.5
Indirect Addressing, INDF and FSR
Registers
Applicable Devices
70 71 71A 72 73 73A 74 74A
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-21. However, IRP
is not used in the PIC16C7X.
BSF
PCLATH,3 ;Select page 1 (800h-FFFh)
CALL
SUB1_P1
;Call subroutine in
;page 1 (800h-FFFh)
:
:
:
ORG 0x900
SUB1 P1:
;called subroutine
;page 1 (800h-FFFh)
:
:
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw 0x20
movwf FSR
;initialize pointer
;to RAM
NEXT
clrf
incf
INDF
;clear INDF register
FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto
NEXT
;no clear next
CONTINUE
:
;yes continue
FIGURE 4-21: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(1)
(1)
from opcode
7
RP1 RP0
6
0
0
IRP
FSR register
bank select
00h
location select
bank select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1 Bank 2
Bank 3
For register file map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
DS30390B-page 42
1995 Microchip Technology Inc.
PIC16C7X
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
5.0
I/O PORTS
Applicable Devices
70 71 71A 72 73 73A 74 74A
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
5.1
PORTA and TRISA Registers
Applicable Devices
Note: On a Power-on Reset, these pins are con-
70 71 71A 72 73 73A 74 74A
figured as analog inputs and read as '0'.
PORTA is a 5-bit latch for PIC16C70/71/71A.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
PORTA is a 6-bit latch for PIC16C72/73/73A/74/74A.
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL input
levels and full CMOS output drivers. All pins have data
direction bits (TRIS registers) which can configure
these pins as output or input.
EXAMPLE 5-1: INITIALIZING PORTA
CLRF
PORTA
; Initialize PORTA by
; setting output
; data latches
Setting a TRISAregister bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
MOVWF TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.
FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Data bus
D
Q
VDD
P
WR PORT
CK
Q
Data Latch
I/O pin
D
Q
Q
N
WR TRIS
CK
VSS
Analog
TRIS Latch
input
mode
TTL
input
buffer
RD TRIS
Q
D
EN
RD PORT
To A/D Converter
Note: I/O pin has protection diodes to VDD and VSS. The PIC16C70/71/71/A devices do not have a pin RA5.
1995 Microchip Technology Inc.
DS30390B-page 43
PIC16C7X
FIGURE 5-2: BLOCK DIAGRAM OF RA4/T0CKI PIN
Data Bus
D
Q
WR PORT
CK
Q
RA4/T0CKI pin
N
Data Latch
VSS
D
Q
Q
Schmitt
WR TRIS
CK
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
RD PORT
TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
TABLE 5-1:
Name
PORTA FUNCTIONS
Bit#
Buffer Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
Input/output or analog input
Input/output or analog input
Input/output or analog input
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
Input/output or analog input/VREF
Input/output or external clock input for Timer0
Output is open drain type
(1)
RA5/AN4/SS
bit5
TTL
Input/output, slave select input for synchronous serial port, or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C70/71/71A does not have PORTA<5> or TRISA<5>, read as '0'.
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA5
TRISA5
—
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
--11 1111
---- -000
(1)
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
(2)
ADCON1
—
—
PCFG2
PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5> and TRISA<5> are not implemented on the PIC16C70/71/71A.
2: Bit PCFG2 is not implemented on the PIC16C70/71/71A.
DS30390B-page 44
1995 Microchip Technology Inc.
PIC16C7X
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
5.2
PORTB and TRISB Registers
Applicable Devices
70 71 71A 72 73 73A 74 74A
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
EXAMPLE 5-2: INITIALIZING PORTB
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
CLRF
PORTB
; Initialize PORTB by
; setting output
; data latches
This interrupt on mismatch feature, together with soft-
ware configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, "Implementing Wake-Up on Key
Stroke" (AN552).
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Note: For the PIC16C71/73/74 only,
if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then interrupt flag
bit RBIF may not get set.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
done by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
weak
FIGURE 5-4: BLOCK DIAGRAM OF
P
pull-up
RB7:RB4 PINS
Data Latch
Data bus
VDD
D
Q
RBPU(2)
weak
I/O
pin(1)
P
WR Port
pull-up
CK
TRIS Latch
Data Latch
Data bus
D
Q
D
Q
I/O
pin(1)
TTL
Input
Buffer
WR Port
CK
TRIS Latch
WR TRIS
CK
D
Q
WR TRIS
TTL
CK
RD TRIS
RD Port
Input
Buffer
ST
Buffer
Q
D
EN
RD TRIS
RD Port
Latch
Q
D
RB0/INT
EN
Schmitt Trigger
Buffer
RD Port
Set RBIF
Note 1: I/O pins have diode protection to VDD and VSS.
From other
RB7:RB4 pins
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION<7>).
Q
D
EN
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
RD Port
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: TRISB = '1' enables weak pull-up if RBPU = '0'
(OPTION<7>).
1995 Microchip Technology Inc.
DS30390B-page 45
PIC16C7X
TABLE 5-3:
PORTB FUNCTIONS
Name
Bit#
bit0
Buffer
TTL/ST
Function
(1)
RB0/INT
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
TTL/ST
TTL/ST
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
(2)
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
81h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
T0SE PSA PS2 PS1 PS0 1111 1111
OPTION RBPU INTEDG T0CS
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30390B-page 46
1995 Microchip Technology Inc.
PIC16C7X
5.3
PORTC and TRISC Registers
Applicable Devices
EXAMPLE 5-3: INITIALIZING PORTC
CLRF
PORTC
; Initialize PORTC by
; setting output
; data latches
70 71 71A 72 73 73A 74 74A
PORTC is an 8-bit bi-directional port. Each pin is indi-
vidually configurable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
BSF
STATUS, RP0 ; Select Bank 1
MOVLW 0xCF
; Value used to
; initialize data
; direction
MOVWF TRISC
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. The TRIS bit override is in effect
only while the peripheral is enabled. The user should
refer to the corresponding peripheral section for the
correct TRIS bit settings.
FIGURE 5-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
(1)
PORT/PERIPHERAL Select
Peripheral Data-out
0
VDD
1
Data Bus
D
Q
Q
P
WR PORT
CK
Data Latch
I/O pin
D
Q
Q
WR TRIS
N
CK
TRIS Latch
RD TRIS
VSS
Schmitt
Trigger
(2)
Peripheral OE
Q
D
RD PORT
EN
Peripheral input
RD PORT
Note 1: Port/Peripheral select signal selects between port data and peripheral output.
2: Peripheral OE (output enable) is only activated if peripheral select is active.
3: I/O pins have diode protection to VDD and VSS.
1995 Microchip Technology Inc.
DS30390B-page 47
PIC16C7X
TABLE 5-5:
PORTC FUNCTIONS
Name
Bit# Buffer Type
Function
bit0
bit1
RC0/T1OSO/T1CKI
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input
(1)
Input/output port pin, Timer1 oscillator input, Capture2 input/Compare2
output/PWM2 output
RC1/T1OSI/CCP2
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC3/SCK/SCL can also be selected as the synchronous serial clock
2
for both SPI and I C modes.
bit4
ST
RC4/SDI/SDA can also be selected as the SPI Data In (SPI mode) or
2
data I/O (I C mode).
bit5
bit6
ST
ST
Input/output port pin or Synchronous Serial Port data output
(2)
Input/output port pin, USART Asynchronous Transmit, or USART Syn-
chronous Clock
RC6/TX/CK
(2)
bit7
ST
Input/output port pin USART Asynchronous Receive, or USART Syn-
chronous Data
RC7/RX/DT
Legend: ST = Schmitt Trigger Input
Note 1: The CCP2 multiplexed function is not enabled on the PIC16C72.
2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72.
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC
TRISC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
1111 1111
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
Legend: x= unknown, u= unchanged.
DS30390B-page 48
1995 Microchip Technology Inc.
PIC16C7X
PORTD can be configured as an 8-bit wide micropro-
cessor port (or parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
5.4
PORTD and TRISD Registers
Applicable Devices
70 71 71A 72 73 73A 74 74A
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configurable as an input or
output.
FIGURE 5-6: PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
D
Q
Q
I/O pin
WR PORT
CK
Data Latch
D
Q
Q
Schmitt
WR TRIS
CK
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
RD PORT
Note: I/O pins has protection diodes to VDD and VSS.
TABLE 5-7:
PORTD FUNCTIONS
Name
Bit#
Buffer Type
Function
(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
ST/TTL
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
(1)
ST/TTL
Legend: ST = Schmitt Trigger Input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
1995 Microchip Technology Inc.
DS30390B-page 49
PIC16C7X
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
TRISD TRISD7 TRISD6 TRISD5
TRISE IBF OBF
TRISD4
TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
TRISE2 TRISE1 TRISE0 0000 -111 0000 -111
IBOV PSPMODE
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30390B-page 50
1995 Microchip Technology Inc.
PIC16C7X
Figure 5-7 shows the TRISE register, which also con-
trols the parallel slave port operation.
5.5
PORTE and TRISE Register
Applicable Devices
PORTE pins are multiplexed with analog inputs. The
operation of these pins is selected by control bits in the
ADCON1 register. When selected as an analog input,
these pins will read as '0's.
70 71 71A 72 73 73A 74 74A
PORTE has three pins RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configurable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured for dig-
ital I/O. In this mode the input buffers are TTL.
Note: On a Power-on Reset these pins are con-
figured as analog inputs.
FIGURE 5-7: TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
R/W-0
U-0
—
R/W-1
R/W-1
TRISE1 TRISE0
bit0
R/W-1
OBF
IBOV PSPMODE
TRISE2
R
= Readable bit
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
IBF: Input Buffer Full Status bit
1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as '0'
TRISE2: Direction control bit for pin RE2/CS/AN7
1 = Input
0 = Output
bit 1:
bit 0:
TRISE1: Direction control bit for pin RE1/WR/AN6
1 = Input
0 = Output
TRISE0: Direction control bit for pin RE0/RD/AN5
1 = Input
0 = Output
1995 Microchip Technology Inc.
DS30390B-page 51
PIC16C7X
FIGURE 5-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
Data Bus
D
Q
Q
I/O pin
WR PORT
CK
Data Latch
D
Q
Q
Schmitt
WR TRIS
CK
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
RD PORT
TABLE 5-9:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
Function
(1)
(1)
(1)
RE0/RD/AN5
bit0
ST/TTL
ST/TTL
ST/TTL
Input/output port pin, Read control input in parallel slave port mode, or
analog input:
RD
1 = Not a read operation
0 = Read operation. Reads PORTD register (if chip selected)
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
Input/output port pin, Write control input in parallel slave port mode, or
analog input:
WR
1 = Not a write operation
0 = Write operation. Writes PORTD register (if chip selected)
Input/output port pin, Chip select control input in parallel slave port
mode, or analog input:
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger Input TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
09h
89h
9fh
PORTE
TRISE
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
0000 -111
---- -000
IBF OBF IBOV PSPMODE
TRISE2 TRISE1 TRISE0 0000 -111
PCFG2 PCFG1 PCFG0 ---- -000
ADCON1
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
DS30390B-page 52
1995 Microchip Technology Inc.
PIC16C7X
5.6
I/O Programming Considerations
Applicable Devices
EXAMPLE 5-4: READ-MODIFY-WRITE
INSTRUCTIONS ON AN I/O
PORT
70 71 71A 72 73 73A 74 74A
;Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
5.6.1
BI-DIRECTIONAL I/O PORTS
;PORTB<7:6> have external pull-ups and are
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However, if
bit0 is switched to an output, the content of the data
latch may now be unknown.
;not connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ---------
BCF PORTB, 7
BCF PORTB, 6
BSF STATUS, RP0
BCF TRISB, 7
BCF TRISB, 6
; 01pp ppp
; 10pp ppp
;
; 10pp ppp
; 10pp ppp
11pp ppp
11pp ppp
11pp ppp
10pp ppp
;
;Note that the user may have expected the
;pin values to be 00pp ppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
5.6.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-
9). Therefore, care must be exercised if a write followed
by a read operation is carried out on the same I/O port.
The sequence of instructions should be such to allow
the pin voltage to stabilize (load dependent) before the
next instruction which causes that file to be read into
the CPU is executed. Otherwise, the previous state of
that pin may be read into the CPU rather than the new
state. When in doubt, it is better to separate these
instructions with a NOP or another instruction not
accessing this I/O port.
Example 5-4 shows the effect of two sequential read-
modify-write instructions on an I/O port.
FIGURE 5-9: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q1 Q2
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
Note:
This example shows a write to PORTB
followed by a read from PORTB.
PC + 3
NOP
PC
Instruction
fetched
PC + 1
PC + 2
NOP
MOVWF PORTB MOVF PORTB,W
write to
PORTB
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Therefore, at higher clock frequencies,
a write followed by a read may be prob-
lematic.
Instruction
executed
NOP
MOVWF PORTB
write to
MOVF PORTB,W
PORTB
1995 Microchip Technology Inc.
DS30390B-page 53
PIC16C7X
address). In this mode, the TRISD register is ignored,
since the microprocessor is controlling the direction of
data flow.
5.7
Parallel Slave Port
Applicable Devices
70 71 71A 72 73 73A 74 74A
Input Buffer Full Status Flag bit IBF (TRISE<7>), is set
if a received word is waiting to be read by the CPU.
Once the PORTD input latch is read, IBF is cleared. IBF
is a read only status bit. Output Buffer Full Status Flag
bit OBF (TRISE<6>), is set if a word written to PORTD
latch is waiting to be read by the external bus. Once the
PORTD output latch is read by the microprocessor,
OBF is cleared. Input Buffer Overflow Status Flag bit
IBOV (TRISE<5>) is set if a second write to the micro-
processor port is attempted when the previous word
has not been read by the CPU (the first word is retained
in the buffer).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD/AN5 and WR control input pin
RE1/WR/AN6.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input,
RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to
be the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG2:PCFG0
(ADCON1<2:0> must be set, which will configure pins
RE2:RE0 as digital I/O.
When not in Parallel Slave Port mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previ-
ously set, it must be cleared in the software.
An interrupt is generated and latched into flag bit
PSPIF (PIR1<7>) when a read or a write operation is
completed. Interrupt flag bit PSPIF must be cleared by
user software and the interrupt can be disabled by
clearing interrupt enable bit PSPIE (PIE1<7>).
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
FIGURE 5-10: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data bus
Q
D
RDx pin
WR Port
CK
D
Q
TTL
EN
RD Port
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
TTL
Read
RD
Chip Select
Write
CS
WR
Note: I/O pins has protection diodes to VDD and VSS.
DS30390B-page 54
1995 Microchip Technology Inc.
PIC16C7X
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
Value on all
POR
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other resets
BOR
08h
09h
89h
0Ch
8Ch
9fh
PORTD
PORTE
TRISE
PIR1
RD7
—
RD6 RD5
RD4
—
RD3
—
RD2
RE2
RD1
RE1
RD0
RE0
xxxx xxxx
---- -xxx
uuuu uuuu
---- -uuu
0000 -111
0000 0000
0000 0000
---- -000
—
—
IBF
OBF IBOV PSPMODE
—
TRISE2 TRISE1 TRISE0 0000 -111
PSPIF ADIF RCIF
PSPIE ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
PIE1
ADCON1
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
1995 Microchip Technology Inc.
DS30390B-page 55
PIC16C7X
NOTES:
DS30390B-page 56
1995 Microchip Technology Inc.
PIC16C7X
Capture/Compare/PWM module. When used with a
CCP module, Timer1 is the time-base for 16-bit capture
or the 16-bit compare and must be synchronized to the
device.
6.0
OVERVIEW OF TIMER
MODULES
Applicable Devices
70 71 71A 72 73 73A 74 74A
6.3
Timer2 Overview
Applicable Devices
The PIC16C70 and PIC16C71/71A have one timer
module.
70 71 71A 72 73 73A 74 74A
The PIC16C72, PIC16C73/73A and PIC16C74/74A
have three timer modules.
Timer2 is an 8-bit timer with a programmable prescaler
and postscaler, as well as an 8-bit period register
(PR2). Timer2 can be used with the CCP1 module (in
PWM mode) as well as the Baud Rate Generator for
the Synchronous Serial Port (SSP). The prescaler
option allows Timer2 to increment at the following
rates: 1:1, 1:4, 1:16.
Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer overflow). Each of
these modules is explained in full detail in the following
sections. The timer modules are:
• Timer0 Module (Section 7.0)
• Timer1 Module (Section 8.0)
• Timer2 Module (Section 9.0)
The postscaler allows the TMR2 register to match the
period register (PR2) a programmable number of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).
6.1
Timer0 Overview
Applicable Devices
6.4
CCP Overview
70 71 71A 72 73 73A 74 74A
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Timer0 module (previously known as RTCC) is a
simple 8-bit overflow counter. The clock source can be
either the internal system clock (Fosc/4) or an external
clock. When the clock source is an external clock, the
Timer0 module can be selected to increment on either
the rising or falling edge.
The CCP module(s) can operate in one of these three
modes: 16-bit capture, 16-bit compare, or up to 10-bit
Pulse Width Modulation (PWM).
Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or the sixteenth rising edge of
the CCPx pin.
The Timer0 module also has a programmable pres-
caler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler, and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. Timer0
can increment at the following rates: 1:1 (when pres-
caler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16,
1:32, 1:64, 1:128, and 1:256 (Timer0 only).
Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs an interrupt can be generated, and the
output pin CCPx can be forced to given state (High or
Low), TMR1 can be reset (CCP1), or Timer1 reset and
start A/D conversion (CCP2). This depends on the con-
trol bits CCPxM3:CCPxM0.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s fre-
quency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 reg-
ister = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an out-
put) will be forced high.
6.2
Timer1 Overview
Applicable Devices
70 71 71A 72 73 73A 74 74A
Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an external
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (external clock source), the counter can either
operate synchronized to the device or asynchronously
to the device. Asynchronous operation allows Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power sav-
ings of SLEEP mode.
Timer1 also has a prescaler option which allows
Timer1 to increment at the following rates: 1:1, 1:2, 1:4,
and 1:8. Timer1 can be used in conjunction with the
1995 Microchip Technology Inc.
DS30390B-page 57
PIC16C7X
NOTES:
DS30390B-page 58
1995 Microchip Technology Inc.
PIC16C7X
Source Edge Select bit T0SE (OPTION<4>). Clearing
bit T0SE selects the rising edge. Restrictions on the
external clock input are discussed in detail in
Section 7.2.
7.0
TIMER0 MODULE
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Timer0 module timer/counter has the following fea-
tures:
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler assignment is controlled in software by the control
bit PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer0 Interrupt
Applicable Devices
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
the TMR0 register is written, the increment is inhibited
for the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
70 71 71A 72 73 73A 74 74A
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP since the timer is shut off during SLEEP. See
Figure 7-4 for Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS
(OPTION<5>). In counter mode, Timer0 will increment
either on every rising or falling edge of pin RA4/T0CKI.
The incrementing edge is determined by the Timer0
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Data bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
RA4/T0CKI
pin
PSout
(2 cycle delay)
T0SE
3
Set interrupt
flag bit T0IF
on overflow
PS2, PS1, PS0
PSA
T0CS
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).
FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
1995 Microchip Technology Inc.
DS30390B-page 59
PIC16C7X
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
6
NT0
TMR0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
FIGURE 7-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
FFh
00h
01h
02h
1
1
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
PC +1
PC +1
0004h
0005h
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (0004h)
Inst (PC)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS30390B-page 60
1995 Microchip Technology Inc.
PIC16C7X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
7.2
Using Timer0 with an External Clock
Applicable Devices
70 71 71A 72 73 73A 74 74A
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
7.2.2
TMR0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler output
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, Prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1995 Microchip Technology Inc.
DS30390B-page 61
PIC16C7X
caler assignment for the Timer0 module means that
there is no prescaler for the Watchdog Timer, and vice-
versa.
7.3
Prescaler
Applicable Devices
70 71 71A 72 73 73A 74 74A
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a pres-
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The pres-
caler is not readable or writable.
FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (=Fosc/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30390B-page 62
1995 Microchip Technology Inc.
PIC16C7X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the Timer0 mod-
ule use the sequence shown in Example 7-2.
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
EXAMPLE 7-2: CHANGING PRESCALER
(WDT→TIMER0)
Note: To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
CLRWDT
;Clear WDT and
;prescaler
STATUS, RP0 ;Bank 1
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
BSF
MOVLW
MOVWF
BCF
OPTION
;clock source
STATUS, RP0 ;Bank 0
EXAMPLE 7-1: CHANGING PRESCALER
(TIMER0→WDT)
BCF
STATUS, RP0 ;Bank 0
CLRF
BSF
TMR0
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
CLRWDT
;Clears WDT
MOVLW b'xxxx1xxx' ;Select new prescale
MOVWF OPTION ;value & WDT
STATUS, RP0 ;Bank 0
BCF
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0, PIC16C70/71/71A
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 module’s register
xxxx xxxx
0000 000x
1111 1111
uuuu uuuu
0000 000u
1111 1111
---1 1111
0Bh/8Bh INTCON
GIE
OPTION RBPU INTEDG
TRISA
ADIE
T0IE
T0CS
—
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF
PS0
81h
85h
—
—
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER0, PIC16C72/73/73A/74/74A
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
TMR0
Timer0 module’s register
xxxx xxxx
0000 000x
1111 1111
uuuu uuuu
0000 000u
1111 1111
--11 1111
0Bh/8Bh INTCON
GIE
OPTION RBPU INTEDG
TRISA
PEIE
T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF
PS0
81h
85h
T0CS
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
1995 Microchip Technology Inc.
DS30390B-page 63
PIC16C7X
NOTES:
DS30390B-page 64
1995 Microchip Technology Inc.
PIC16C7X
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input on pin RC0/T1OSO/
T1CKI.
8.0
TIMER1 MODULE
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L) which are
readable and writable. The TMR1 Register pair
(TMR1H + TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled or disabled using TMR1 interrupt enable bit
TMR1IE (PIE1<0>).
Timer1 can be turned on and off using the control bit
TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by either of the two CCP modules
(Section 10.0). Figure 8-1 shows the Timer1 control
register.
For the PIC16C72/73A/74A, when the Timer1 oscillator
is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2
and RC0/T1OSO/T1CKI pins become inputs. That is,
the TRISC<1:0> value is ignored.
Timer1 can operate in one of two modes:
• As a timer
For the PIC16C73/74, when the Timer1 oscillator is
enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin
becomes an input, however the RC0/T1OSO/T1CKI
pin will have to be configured as an input by setting the
TRISC<0> bit.
• As a counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
FIGURE 8-1: T1CON:TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R
= Readable bit
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the external clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (OSC/4)
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
1995 Microchip Technology Inc.
DS30390B-page 65
PIC16C7X
8.2.1
EXTERNAL CLOCK INPUT TIMING FOR
SYNCHRONIZED COUNTER MODE
8.1
Timer1 Operation in Timer Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
When an external clock input is used for Timer1 in syn-
chronized counter mode, it must meet certain require-
ments. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after syn-
chronization.
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is OSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
8.2
Timer1 Operation in Synchronized
Counter Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2 when bit
T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit
T1OSCEN is cleared.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-
counter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of 10
ns). Refer to the appropriate electrical specifications,
parameters 40, 42, 45, 46, and 47.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 8-2: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
clock input
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
(3)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
OSC/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI/CCP2
2
SLEEP input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2: The CCP2 module is not implemented in the PIC16C72.
3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode.
DS30390B-page 66
1995 Microchip Technology Inc.
PIC16C7X
8.3
Timer1 Operation in Asynchronous
Counter Mode
EXAMPLE 8-1: READING A 16-BIT FREE-
RUNNING TIMER
Applicable Devices
; All interrupts are disabled
70 71 71A 72 73 73A 74 74A
MOVF
MOVWF TMPH
MOVF TMR1L, W ;Read low byte
MOVWF TMPL
MOVF TMR1H, W ;Read high byte
SUBWF TMPH,
TMR1H, W ;Read high byte
;
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer
(Section 8.3.2).
;
W
;Sub 1st read
; with 2nd read
BTFSC STATUS,Z ;Is result = 0
GOTO CONTINUE ;Good 16-bit read
;
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
;
In asynchronous counter mode, Timer1 can not be
used as a time-base for capture or compare opera-
tions.
MOVF
MOVWF TMPH
MOVF TMR1L, W ;Read low byte
MOVWF TMPL
; Re-enable the Interrupt (if required)
TMR1H, W ;Read high byte
8.3.1
EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK
;
;
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
a certain minimum high time and low time require-
ments. Refer to the appropriate Electrical Specifica-
tions Section, timing parameters 45, 46, and 47.
CONTINUE
;Continue with your code
8.4
Timer1 Oscillator
Applicable Devices
8.3.2
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
70 71 71A 72 73 73A 74 74A
A crystal oscillator circuit is built in between T1OSI pin
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 8-1 shows the capacitor
selection for the Timer1 oscillator.
Reading TMR1H or TMR1L while the timer is running,
from an external asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
TABLE 8-1:
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Reading the 16-bit value requires some care.
Example 8-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
Osc Type
Freq
C1
C2
(1)
LP
32 kHz
15 pF
15 pF
0 - 15 pF
15 pF
15 pF
0 - 15 pF
100 kHz
200 kHz
Higher capacitance increases the stability of oscilla-
tor but also increases the start-up time. These values
are for design guidance only.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
200 kHz
Epson C-2 100.00 KC-P ± 20 PPM
STD XTL 200.000 kHz
± 20 PPM
1995 Microchip Technology Inc.
DS30390B-page 67
PIC16C7X
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer1.
8.5
Resetting Timer1 using a CCP Trigger
Output
Applicable Devices
70 71 71A 72 73 73A 74 74A
8.6
Resetting of Timer1 Register Pair
(TMR1H,TMR1L)
The CCP2 module is not implemented on the
PIC16C72 device.
Applicable Devices
If the CCP1 or CCP2 module is configured in compare
70 71 71A 72 73 73A 74 74A
mode to generate
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer1.
a
“special event trigger"
TMR1H and TMR1L registers are not reset on a POR
or any other reset except by the CCP1 special event
trigger.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset. In any other reset, the register is
unaffected.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature.
If Timer1 is running in asynchronous counter mode,
this reset operation may not work.
8.7
Timer1 Prescaler
Applicable Devices
70 71 71A 72 73 73A 74 74A
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 8-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR
BOR
Value on
all other
resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
(1,2)
(2)
(2)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
PSPIF
PSPIE
ADIF RCIF
ADIE RCIE
TXIF
TXIE
CCP1IF TMR2IF TMR1IF
CCP1IE TMR21E TMR1IE
(1,2)
(2)
(2)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by theTimer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
DS30390B-page 68
1995 Microchip Technology Inc.
PIC16C7X
9.1
Timer2 Prescaler and Postscaler
Applicable Devices
9.0
TIMER2 MODULE
Applicable Devices
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
reset.
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset,
or Watchdog Timer reset)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16
(selected
by
control
bits
TMR2 will not clear when T2CON is written, only for a
WDT, POR, and MCLR reset.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
set during RESET.
9.2
Output of TMR2
Applicable Devices
70 71 71A 72 73 73A 74 74A
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, PIR1<1>).
FIGURE 9-1: TIMER2 BLOCK DIAGRAM
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Sets flag
TMR2
output (1)
bit TMR2IF
Figure 9-2 shows the Timer2 control register.
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
OSC/4
Postscaler
1:1 to 1:16
2
Comparator
EQ
4
PR2 reg
Note 1: TMR2 register output can be software selected
by the SSP Module as a baud clock.
1995 Microchip Technology Inc.
DS30390B-page 69
PIC16C7X
FIGURE 9-2: T2CON:TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
= Readable bit
W = Writable bit
U
bit7
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
TABLE 9-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR
BOR
Value on
all other
resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Bh/8Bh INTCON
GIE
PEIE
ADIF
ADIE
T0IE
INTE
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0Ch
8Ch
11h
12h
92h
PIR1
PSPIF(1,2)
PSPIE(1,2)
RCIF(2)
RCIE(2)
TXIF(2)
TXIE(2)
CCP1IF
CCP1IE
TMR2IF
TMR21E
TMR1IF
TMR1IE
PIE1
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.
DS30390B-page 70
1995 Microchip Technology Inc.
PIC16C7X
CCP1 module:
10.0 CAPTURE/COMPARE/PWM
MODULE(s)
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). Both are readable and writable.
Applicable Devices
70 71 71A 72 73 73A 74 74A CCP1
70 71 71A 72 73 73A 74 74A CCP2
CCP2 module:
Capture/Compare/PWM Register2 (CCPR2) is made
up of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). Both are readable and writable.
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM out-
put. Both the CCP1 and CCP2 modules are identical in
operation, with the exception of the operation of the
special event trigger. Table 10-1 and Table 10-2 show
the resources and interactions of the CCP module(s).
In the following sections, the operation of a CCP mod-
ule is described with respect to CCP1. CCP2 operates
the same as CCP1, except where noted.
For use of the CCP modules, refer to the Embedded
Control Handbook, "Using the CCP Modules" (AN594).
TABLE 10-1: CCP MODE - TIMER RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
TABLE 10-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 timebase.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
Compare
None
None
PWM
1995 Microchip Technology Inc.
DS30390B-page 71
PIC16C7X
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit0
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM High Resolution, Low Order Select bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: Write the two low order bits in high resolution (10-bit) mode. May be kept constant (at '0') if
only 8-bit resolution (in standard resolution mode) is desired.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/compare/PWM off (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1
and starts an A/D conversion (if A/D module is enabled))
11xx= PWM mode
10.1
Capture Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
Note: If the RC2/CCP1 is configured as an out-
put, a write to the port can cause a capture
condition.
In Capture mode, CCPR1H:CCPR1L captures the 16-
bit value of the TMR1 register when an event occurs on
pin RC2/CCP1. An event is defined as:
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
• A falling edge
• A rising edge
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. It must
be reset in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost. In capture mode, the RC2/CCP1 pin
should be configured as an input by setting its corre-
sponding TRIS bit.
DS30390B-page 72
1995 Microchip Technology Inc.
PIC16C7X
10.1.1 PRESCALER
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, a compare interrupt is also generated. The
user must configure the RC2/CCP1 pin as an output by
clearing the TRISC<2> bit.
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
10.2.1 COMPARE MODE SELECTION
Timer1 must be running in timer mode or synchronized
counter mode if the CCP module is using the compare
feature. In asynchronous counter mode, the compare
operation may not work.
EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
10.2.2 SOFTWARE INTERRUPT MODE
Another compare mode is software interrupt mode in
which the CCP1 pin is not affected. Only a CCP inter-
rupt is generated (if enabled).
CLRF
CCP1CON
;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
; mode value and CCP ON
;Load CCP1CON with this
; value
10.2.3 SPECIAL EVENT TRIGGER
MOVWF CCP1CON
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
10.1.2 CAPTURE MODE SELECTION
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
The special trigger output of CCP2 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
FIGURE 10-2: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
For the PIC16C72 only, the special event trigger output
of CCP1 resets the TMR1 register pair, and starts an
A/D conversion (if the A/D module is enabled).
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
RC2/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
Capture
Enable
and
edge detect
FIGURE 10-3: COMPARE MODE
OPERATION BLOCK
DIAGRAM
TMR1H
CCP1CON<3:0>
Q’s
Special Event(1)
Set flag bit CCP1IF
(PIR1<2>)
10.2
Compare Mode
Applicable Devices
CCPR1H CCPR1L
70 71 71A 72 73 73A 74 74A
Q
S
R
Output
Logic
Comparator
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
match
RC2/CCP1
Pin
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
• Driven High
Note 1: For CCP1 (if enabled), reset Timer1.
• Driven Low
For CCP2 (if enabled), reset Timer1, and set bit
GO/DONE (ADCON0<2>), which starts an A/D conver-
sion.
• Remains Unchanged
1995 Microchip Technology Inc.
DS30390B-page 73
PIC16C7X
10.3
PWM Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
FIGURE 10-4: SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON<5:4>
Duty cycle registers
In Pulse Width Modulation mode (PWM), pin
RC2/CCP1 produces up to a 10-bit resolution PWM
output. This pin must be configured as an output by
clearing the TRISC<2> bit. The pin is multiplexed with
the data latch. In PWM mode, the user writes the 8-bit
duty cycle value to the low byte of the CCPR1 register,
namely CCPR1L. The high-byte, CCPR1H is used as
the slave buffer to the low byte. The 8-bit data is trans-
ferred from the master to the slave when the PWM1
output is set (i.e. at the beginning of the duty cycle).
This double buffering is essential for glitchless PWM
output. In PWM mode, CCPR1H is readable but not
writable. The period of the PWM is determined by the
Timer2 period register (PR2).
CCPRxL
CCPRxH (Slave)
Q
R
S
Comparator
TMR2
RCy/CCPx
Pin
(Note 1)
TRISC<y>
Comparator
Clear Timer,
CCP1 pin and
latch Duty Cycle
PWM period is =
PR2
[(PR2) + 1] • 4 TOSC • (TMR2 prescale value)
PWM duty cycle =
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2-bits of the prescaler to create 10-bit
time-base.
(DC1) • TOSC • (TMR2 prescale value)
TABLE 10-3: PWM FREQUENCY vs.
RESOLUTION AT 20 MHz
where DC1 = 10-bit value from CCPRxL and CCPx-
CON<5:4> concatenated.
The PWM output resolution is therefore programmable
up to a maximum of 10-bits.
Max.
Frequency
Resolution
Note: Clearing the CCP1CON register will force
the RC2/CCP1 PWM output latch to the
default low level. This is not the I/O data
latch. The Timer2 postscaler is not used in
the determination of the PWM frequency.
The postscaler could be used to have a
servo update rate at a different frequency
than the PWM output.
(High
Resolution
Mode)
TMR2
TMR2
TMR2
Prescale=1 Prescale=4 Prescale=16
10-bit
9-bit
8-bit
19.53 kHz 4.88 kHz
39.06 kHz 9.77 kHz
1.22 kHz
2.44 kHz
78.13 kHz 19.53 kHz 4.88 kHz
TABLE 10-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
Timer Prescaler (16, 4, 1)
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
PR2 Value
0xFF
10-bit
8-bit
0xFF
10-bit
8-bit
0xFF
10-bit
8-bit
0x3F
8-bit
6-bit
0x1F
7-bit
5-bit
0x17
5.5-bit
3.5-bit
Resolution (High-resolution mode)
(1)
Resolution (Standard-resolution mode)
Note 1: Standard resolution mode has the CCPxX:CCPxY bits constant (or ‘0’), and only compares the TMR2 register value
against the PR2 register value. The Q-cycles are not used.
DS30390B-page 74
1995 Microchip Technology Inc.
PIC16C7X
TABLE 10-5: REGISTERS ASSOCIATED WITH CAPTURE AND TIMER1
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
SSPIF
—
T0IF
INTF
RBIF
0000 000x 0000 000u
(1,2)
(2)
(2)
0Ch
0Dh
8Ch
8Dh
0Eh
0Fh
10h
15h
16h
17h
PIR1
PSPIF
—
ADIF RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(2)
(2)
PIR2
—
—
—
—
(1,2)
(2)
(2)
PIE1
PSPIE
—
ADIE RCIE
TXIE
—
SSPIE
—
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
TMR1L
TMR1H
T1CON
CCPR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
(2)
1Bh
Capture/Compare/PWM register2 (LSB)
(2)
1Ch
1Dh
CCPR2H Capture/Compare/PWM register2 (MSB)
CCP2CON CCP2X CCP2Y
xxxx xxxx uuuu uuuu
(2)
—
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
TABLE 10-6: REGISTERS ASSOCIATED WITH COMPARE AND TIMER1
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
SSPIF
—
T0IF
INTF
RBIF
0000 000x 0000 000u
(1,2)
(2)
(2)
0Ch
0Dh
8Ch
8Dh
0Eh
0Fh
10h
15h
16h
17h
PIR1
PSPIF
—
ADIF RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(2)
(2)
PIR2
—
—
—
—
(1,2)
(2)
(2)
PIE1
PSPIE
—
ADIE RCIE
TXIE
—
SSPIE
—
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
TMR1L
TMR1H
T1CON
CCPR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON
CCPR2L
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
(2)
1Bh
Capture/Compare/PWM register2 (LSB)
(2)
1Ch
1Dh
CCPR2H Capture/Compare/PWM register2 (MSB)
CCP2CON CCP2X CCP2Y
xxxx xxxx uuuu uuuu
(2)
—
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Compare and Timer1.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
1995 Microchip Technology Inc.
DS30390B-page 75
PIC16C7X
TABLE 10-7: REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on: Value on
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
BOR
all other
resets
0Bh/8Bh INTCON
GIE
PSPIF(1,2)
—
PEIE
ADIF
—
T0IE
RCIF(2)
—
INTE
TXIF(2)
—
RBIE
SSPIF
—
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
0Dh(2) PIR2
8Ch PIE1
8Dh(2) PIE2
PIR1
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
—
—
PSPIE(1,2)
ADIE
—
RCIE(2)
TXIE(2)
SSPIE
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
0000 0000 0000 0000
11h
92h
12h
15h
16h
17h
TMR2
Timer2 module’s register
Timer2 module’s period register
PR2
1111 1111 1111 1111
T2CON
CCPR1L
CCPR1H
CCP1CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
1Bh(2) CCPR2L
1Ch(2) CCPR2H
1Dh(2) CCP2CON
Capture/Compare/PWM register2 (LSB)
Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.
DS30390B-page 76
1995 Microchip Technology Inc.
PIC16C7X
Refer toApplication NoteAN578, "Use of the SSP Mod-
ule in the I C Multi-Master Environment."
11.0 SYNCHRONOUS SERIAL
PORT (SSP) MODULE
Applicable Devices
2
70 71 71A 72 73 73A 74 74A
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
2
• Inter-Integrated Circuit (I C)
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
U-0
—
U-0
—
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
2
bit 5:
bit 4:
bit 3:
bit 2:
D/A: Data/Address bit (I C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
2
P: Stop bit (I C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
2
S: Start bit (I C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
2
R/W: Read/Write bit information (I C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid during the
transmission.
1 = Read
0 = Write
2
bit 1:
bit 0:
UA: Update Address (10-bit I C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
2
Receive (SPI and I C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
2
Transmit (I C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
1995 Microchip Technology Inc.
DS30390B-page 77
PIC16C7X
FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
WCOL SSPOV SSPEN
bit7
SSPM3 SSPM2 SSPM1 SSPM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 =Anew byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even
if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since each
new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
2
In I C mode
1 =Abyte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SDK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
2
In I C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Transmit happens on falling edge, receive on rising edge. Idle state for clock is a high level
0 = Transmit happens on rising edge, receive on falling edge. Idle state for clock is a low level
2
In I C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI master mode, clock = FOSC/4
0001= SPI master mode, clock = FOSC/16
0010= SPI master mode, clock = FOSC/64
0011= SPI master mode, clock = TMR2 output/2
0100= SPI slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
2
0110= I C slave mode, 7-bit address
2
0111= I C slave mode, 10-bit address
2
1011= I C start and stop bit interrupts enabled (slave idle)
2
1110= I C slave mode, 7-bit address with start and stop bit interrupts enabled
2
1111= I C slave mode, 10-bit address with start and stop bit interrupts enabled
DS30390B-page 78
1995 Microchip Technology Inc.
PIC16C7X
11.1
SPI Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
BSF
STATUS, RP0
;Specify Bank 1
;Has data been
;received
The SPI mode allows 8-bits of data to be synchro-
nously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
LOOP BTFSS SSPSTAT, BF
;(transmit
;complete)?
GOTO LOOP
;No
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI
• Serial Clock (SCK) RC3/SCK
BCF
STATUS, RP0
;Specify Bank 0
;W reg = contents
; of SSPBUF
MOVF SSPBUF, W
MOVWF RXDATA
;Save in user RAM
Additionally a fourth pin may be used when in a slave
mode of operation:
MOVF TXDATA, W
;W reg = contents
; of TXDATA
MOVWF SSPBUF
;New data to xmit
• Slave Select (SS) RA5/AN4/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the
Rising/Falling edge of SCK)
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
• Clock Rate (Master mode only)
Internal
data bus
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSB first. The
SSPBUF holds the data that was previously written to
the SSPSR, until the received data is ready. Once the
8-bits of data have been received, that information is
moved to the SSPBUF register. Then the buffer full
detect bit BF (SSPSTAT <0>) and interrupt flag bit
SSPIF (PIR1<3>) are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was received.
Any write to the SSPBUF register during transmission/
reception of data will be ignored, and the write collision
detect bit WCOL (SSPCON<7>) will be set. User soft-
ware must clear the WCOL bit so that it can be deter-
mined if the following write(s) to the SSPBUF register
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF should
be read before the next byte of data to transfer is written
to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indi-
cates when SSPBUF has been loaded with the
received data (transmission is complete). When the
SSPBUF is read, bit BF is cleared. This data may be
irrelevant if the SPI is only a transmitter. Generally the
SSP Interrupt is used to determine when the transmis-
sion/reception has completed. The SSPBUF can then
be read (if data is meaningful) and/or the SSPBUF
(SSPSR) can be written. If the interrupt method is not
going to be used, then software polling can be done to
Read
Write
SSPBUF reg
SSPSR reg
SDI
shift
clock
bit0
SDO
Control
Enable
SS
SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
TMR2 output
2
Edge
Select
TCY
Prescaler
4, 16, 64
SCK
Data from TX/RX in SSPSR
TRISC<3>
ensure that
a write collision does not occur.
Example 11-1 shows the loading of the SSPBUF
(SSPSR) for data transmission. The shaded instruction
is only required if the received data is meaningful.
1995 Microchip Technology Inc.
DS30390B-page 79
PIC16C7X
To enable the serial port, SSP enable bit SSPEN (SSP-
CON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) wishes to broadcast data
by the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
Any serial port function that is not desired may be over-
ridden by programming the corresponding data direc-
tion (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
The clock polarity is selected by appropriately pro-
gramming bit CKP (SSPCON<4>). This then would
give waveforms for SPI communication as shown in
Figure 11-5 and Figure 11-6 where the MSB is trans-
mitted first. In master mode, the SPI clock rate (bit rate)
is user programmable to be one of the following:
Figure 11-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their pro-
grammed clock edge, and latched on the opposite
edge of the clock. Both processors should be pro-
grammed to same Clock Polarity (CKP), then both con-
trollers would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 • TCY)
• FOSC/64 (or 16 • TCY)
• Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
SPI Master (SSPM3:SSPM0 = 00xxb)
SPI Slave (SSPM3:SSPM0 = 010xb)
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
SDO
Shift Register
Shift Register
(SSPSR)
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
PROCESSOR 1
PROCESSOR 2
DS30390B-page 80
1995 Microchip Technology Inc.
PIC16C7X
The SS pin allows a synchronous slave mode. The SPI
must be in slave mode (SSPCON<3:0> = 04h) and the
TRISA<5> bit must be set the for the synchronous
slave mode to be enabled. When the SS pin is low,
transmission and reception are enabled and the SDO
pin is driven. When the SS pin goes high, the SDO pin
is no longer driven, even if in the middle of a transmit-
ted byte, and becomes a floating output. External pull-
up/pull-down resistors may be desirable, depending on
the application.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 11-5: SPI MODE TIMING (MASTER MODE OR SLAVE MODE W/O SS CONTROL)
SCK
(CKP = 0)
SCK
(CKP = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
SDO
SDI
bit7
SSPIF
Interrupt flag
FIGURE 11-6: SPI MODE TIMING (SLAVE MODE WITH SS CONTROL)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
bit0
SDO
SDI
bit7
SSPIF
1995 Microchip Technology Inc.
DS30390B-page 81
PIC16C7X
TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1,2)
(2)
(2)
0Ch
8Ch
13h
14h
85h
94h
PIR1
PIE1
PSPIF
PSPIE
ADIF RCIF
ADIE RCIE
TXIF
TXIE
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1,2)
(2)
(2)
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111
D/A R/W UA BF --00 0000 --00 0000
xxxx xxxx uuuu uuuu
TRISA
—
—
—
—
SSPSTAT
P
S
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
DS30390B-page 82
1995 Microchip Technology Inc.
PIC16C7X
2
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The num-
ber of devices that may be attached to the I C bus is
limited only by the maximum bus loading specification
of 400 pF.
11.2
I C Overview
Applicable Devices
70 71 71A 72 73 73A 74 74A
This section provides an overview of the Inter-Inte-
grated Circuit (I C) bus, with Section 11.3 discussing
the operation of the SSP module in I C mode.
2
2
2
2
The I C bus is a two-wire serial interface developed by
the Philips Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. An enhanced specification, or fast mode, sup-
ports data transmission up to 400 Kbps. Both standard
mode and fast mode devices will inter-operate if
attached to the same bus.
11.2.1 INITIATING AND TERMINATING DATA
TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure 11-7 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data trans-
fer. Due to the definition of the START and STOP con-
ditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
2
The I C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
(generates the clock), while the other device(s) acts as
the “slave.” All portions of the slave protocol are imple-
mented in the SSP module’s hardware, while portions
of the master protocol need to be addressed in the
PIC16CXX software. Table 11-2 defines some of the
2
I C bus terminology. For additional information on the
2
I C interface specification, refer to the Philips docu-
2
ment “The I C bus and how to use it.”, which can be
FIGURE 11-7: START AND STOP
CONDITIONS
obtained from the Philips Corporation.
2
In the I C interface protocol each device has an
address. When a master wishes to initiate a data trans-
fer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data trans-
fer. That is they can be thought of operating in either of
these two relations:
SDA
S
SCL
P
Change
of Data
Allowed
Change
of Data
Allowed
Start
Stop
Condition
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
In both cases the master generates the clock signal.
2
TABLE 11-2: I C BUS TERMINOLOGY
Term
Description
Transmitter
Receiver
Master
The device that sends the data to the bus.
The device that receives the data from the bus.
The device which initiates the transfer, generates the clock and terminates the transfer.
The device addressed by a master.
Slave
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
1995 Microchip Technology Inc.
DS30390B-page 83
PIC16C7X
2
11.2.2 ADDRESSING I C DEVICES
11.2.3 TRANSFER ACKNOWLEDGE
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 11-8). The
more complex is the 10-bit address with a R/W bit
(Figure 11-9). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure 11-10). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-7).
FIGURE 11-8: 7-BIT ADDRESS FORMAT
MSb
LSb
FIGURE 11-10: SLAVE-RECEIVER
ACKNOWLEDGE
R/W ACK
S
Data
Output by
Transmitter
slave address
Sent by
Slave
Data
Output by
Receiver
not acknowledge
acknowledge
S
R/W
ACK
Start Condition
Read/Write pulse
Acknowledge
SCL from
Master
9
8
2
1
2
FIGURE 11-9: I C 10-BIT ADDRESS
FORMAT
S
Clock Pulse for
Acknowledgment
Start
Condition
S
1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
sent by slave
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
= 0 for write
S
- Start Condition
R/W - Read/Write Pulse
ACK - Acknowledge
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure 11-11.
FIGURE 11-11: DATA TRANSFER WAIT STATE
SDA
MSB
acknowledgment
signal from receiver
acknowledgment
signal from receiver
byte complete
interrupt with receiver
clock line held low while
interrupts are serviced
SCL
S
1
2
7
8
9
1
2
3 • 8
9
P
Start
Condition
Stop
Condition
Address
R/W ACK Wait
State
Data
ACK
DS30390B-page 84
1995 Microchip Technology Inc.
PIC16C7X
Figure 11-12 and Figure 11-13 show Master-transmit-
ter and Master-receiver data transfer sequences.
SCL is high), but occurs after a data transfer acknowl-
edge pulse (not the bus-free state). This allows a mas-
ter to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-14.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START con-
dition (Sr) must be generated. This condition is identi-
cal to the start condition (SDA goes high-to-low while
FIGURE 11-12: MASTER-TRANSMITTER SEQUENCE
For 7-bit address:
For 10-bit address:
S Slave AddressR/W A1Slave Address A2
S Slave AddressR/W A Data A Data A/A P
First 7 bits
Second byte
'0' (write)
data transferred
(n bytes - acknowledge)
(write)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
Data A
Data A/A P
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
A master transmitter addresses a slave receiver
with a 10-bit address.
From slave to master
P = Stop Condition
FIGURE 11-13: MASTER-RECEIVER SEQUENCE
For 10-bit address:
S Slave AddressR/W A1Slave Address A2
First 7 bits Second byte
(write)
For 7-bit address:
S Slave AddressR/W A Data A Data A
P
'1' (read) data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
SrSlave AddressR/W A3 Data A Data A P
First 7 bits
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
(read)
S = Start Condition
A master transmitter addresses a slave receiver
with a 10-bit address.
From slave to master
P = Stop Condition
FIGURE 11-14: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S Slave AddressR/W A Data A/A Sr Slave Address R/W A Data A/A P
(write)
Direction of transfer
may change at this point
(read)
Sr = repeated
Start Condition
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
SrSlave Address R/W A Slave Address A Data A
First 7 bits Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
From master to slave
S = Start Condition
From slave to master
P = Stop Condition
1995 Microchip Technology Inc.
DS30390B-page 85
PIC16C7X
11.2.4 MULTI-MASTER
11.2.4.2 Clock Synchronization
Clock synchronization occurs after the devices have
started arbitration. This is performed using a wired-
AND connection to the SCL line. A high to low transition
on the SCL line causes the concerned devices to start
counting off their low period. Once a device clock has
gone low, it will hold the SCL line low until its SCL high
state is reached. The low to high transition of this clock
may not change the state of the SCL line, if another
device clock is still within its low period. The SCL line is
held low by the device with the longest low period.
Devices with shorter low periods enter a high wait-
state, until the SCL line comes high. When the SCL line
comes high, all devices start counting off their high
periods. The first device to complete its high period will
pull the SCL line low. The SCL line high time is deter-
mined by the device with the shortest high period,
Figure 11-16.
2
The I C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbi-
tration and synchronization occur.
11.2.4.1 ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 11-15), and turns off its data output stage. A
master which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 11-15: MULTI-MASTER
ARBITRATION
(TWO MASTERS)
FIGURE 11-16: CLOCK SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1 SDA
start counting
HIGH period
wait
state
DATA 1
DATA 2
SDA
CLK
1
counter
reset
CLK
2
SCL
SCL
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning mas-
ter-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condi-
tion
Care needs to be taken to ensure that these conditions
do not occur.
DS30390B-page 86
1995 Microchip Technology Inc.
PIC16C7X
2
2
The SSPCON register allows control of the I C opera-
11.3
SSP I C Operation
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I C modes to be selected:
Applicable Devices
2
70 71 71A 72 73 73A 74 74A
2
• I C Slave mode (7-bit address)
2
The SSP module in I C mode fully implements all slave
functions, and provides interrupts on start and stop bits
in hardware to facilitate software implementations of
the master functions. The SSP module implements the
standard and fast mode specifications as well as 7-bit
and 10-bit addressing. Two pins are used for data
transfer. These are the RC3/SCK/SCL pin, which is the
clock (SCL), and the RC4/SDI/SDA pin, which is the
data (SDA). The user must configure these pins as
inputs or outputs through the TRISC<4:3> bits. The
SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
2
• I C Slave mode (10-bit address)
2
• I C Slave mode (7-bit address), with start and
stop bit interrupts enabled
2
• I C Slave mode (10-bit address), with start and
stop bit interrupts enabled
2
• I C start and stop bit interrupts enabled, slave is
idle
2
Selection of any I C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits.
FIGURE 11-17: SSP BLOCK DIAGRAM
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of 10-
bit address, and if this will be a read or write data trans-
fer. The SSPSTAT register is read only.
2
(I C MODE)
Internal
data bus
Read
Write
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the SSP-
BUF register and flag bit SSPIF is set. If another com-
plete byte is received before the SSPBUF register is
read, a receiver overflow has occurred and bit SSPOV
(SSPCON<6>) is set.
SSPBUF reg
SSPSR reg
RC3/SCK/SCL
shift
clock
RC4/
SDI/
SDA
MSb
LSb
Addr Match
Match detect
SSPADD reg
The SSPADD register holds the slave address. In 10-bit
mode, the user needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
Set, Reset
S, P bits
(SSPSTAT reg)
Start and
Stop bit detect
2
The SSP module has five registers for I C operation.
These are the:
• SSP Control Register (SSPCON)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
sible
• SSP Address Register (SSPADD)
1995 Microchip Technology Inc.
DS30390B-page 87
PIC16C7X
11.3.1 SLAVE MODE
a) The SSPSR register value is loaded into the
SSPBUF register.
In slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
When an address is matched or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 11-9). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write, so the slave device will receive the sec-
ond address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address are as follows, with steps 7- 9 for
slave-transmitter:
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
1. Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 11-3 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
2. Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and param-
eter #101.
5. Update the SSPADD register with the first (high)
byte of Address (clears bit UA, if match releases
SCL line).
2
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
7. Receive repeated START condition.
11.3.1.1 ADDRESSING
8. Receive first (high) byte of Address (bits SSPIF
and BF are set).
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
TABLE 11-3: DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if Enabled)
Generate ACK
Pulse
BF
SSPOV
SSPSR → SSPBUF
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
DS30390B-page 88
1995 Microchip Technology Inc.
PIC16C7X
11.3.1.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow con-
dition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware, and the SSPSTAT register is used to determine
the status of the byte.
2
FIGURE 11-18: I C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
9
ACK
9
ACK
9
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
7
1
2
4
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
1995 Microchip Technology Inc.
DS30390B-page 89
PIC16C7X
11.3.1.3 TRANSMISSION
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the SSP-
STAT register is set. The received address is loaded
into the SSPBUF register. The ACK pulse will be sent
on the ninth bit, and pin RC3/SCK/SCL is held low. The
transmit data must be loaded into the SSPBUF register,
which also loads the SSPSR register. Then pin RC3/
SCK/SCL should be enabled by setting bit CKP (SSP-
CON<4>). The eight data bits are shifted out on the fall-
ing edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 11-19).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. The slave then monitors
for another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR reg-
ister. Then pin RC3/SCK/SCL should be enabled by
setting bit CKP.
2
FIGURE 11-19: I C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
DS30390B-page 90
1995 Microchip Technology Inc.
PIC16C7X
11.3.3 MULTI-MASTER MODE
11.3.2 MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a reset or when the SSP module is dis-
2
2
when the SSP module is disabled. Control of the I C
abled. Control of the I C bus may be taken when the P
bus may be taken when bit P (SSPSTAT<4>) is set, or
the bus is idle and both the S and P bits are cleared.
When the bus is busy, enabling the SSP Interrupt will
generate the interrupt when the STOP condition
occurs.
bit is set, or the bus is idle and both the S and P bits are
clear.
In master mode the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTB<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit.
In multi-master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause the SSP Interrupt Flag
bit SSPIF to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, the device may be being addressed. If
addressed an ACK pulse will be generated. If arbitra-
tion was lost during the data transfer stage, the device
will need to re-transfer the data at a later time.
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
2
TABLE 11-4: REGISTERS ASSOCIATED WITH I C OPERATION
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh/8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
--00 0000
0000 000u
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
--00 0000
1111 1111
(1,2)
(2)
(2)
0Ch
8Ch
13h
93h
14h
94h
89h
PIR1
PIE1
PSPIF
PSPIE
ADIF RCIF
ADIE RCIE
TXIF
TXIE
SSPIF CCP1IF TMR2IF TMR1IF
SSPIE CCP1IE TMR2IE TMR1IE
(1,2)
(2)
(2)
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
2
SSPADD Synchronous Serial Port (I C mode) Address Register
SSPCON
SSPSTAT
TRISC
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
D/A R/W UA BF
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
—
—
P
S
1111 1111
2
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by SSP in I C mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.
1995 Microchip Technology Inc.
DS30390B-page 91
PIC16C7X
2
FIGURE 11-20: OPERATION OF THE I C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE
IDLE_MODE (7-bit):
if (Addr_match)
{
Set interrupt;
if (R/W = 1)
{
}
Send ACK = 0;
set XMIT_MODE;
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF=Full) OR (SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
{
else
transfer SSPSR → SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1)
{
}
End of transmission;
Go back to IDLE_MODE;
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{
PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
{
else
Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{
PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
if (PRIOR_ADDR_MATCH)
{
{
send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
DS30390B-page 92
1995 Microchip Technology Inc.
PIC16C7X
as a half duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
12.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
Applicable Devices
The USART can be configured in the following modes:
• Asynchronous (full duplex)
70 71 71A 72 73 73A 74 74A
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also know as a Serial Commu-
nications Interface or SCI). The USART can be config-
ured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT for the Serial Communication Interface.
FIGURE 12-1: TXSTA:TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
TRMT
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
1995 Microchip Technology Inc.
DS30390B-page 93
PIC16C7X
FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
R-0
R-x
FERR
OERR
RX9D
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0 = Serial port disabled
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register)
0 = No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
RX9D: 9th bit of received data (Can be parity bit)
DS30390B-page 94
1995 Microchip Technology Inc.
PIC16C7X
12.1
USART Baud Rate Generator (BRG)
Applicable Devices
EXAMPLE 12-1: CALCULATING BAUD
RATE ERROR
70 71 71A 72 73 73A 74 74A
Desired Baud rate=Fosc / (64 (X + 1))
9600 =
16000000 /(64 (X + 1))
25.042 = 25
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
X
=
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
=
9615
Error
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
=
(9615 - 9600) / 9600
0.16%
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(x + 1)) equation can reduce the
baud rate error in some cases.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
Writing a new value to the SPBRG register, causes the
BRG timer to be reset (or cleared), this ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
TABLE 12-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
NA
X = value in SPBRG (0 to 255)
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on:
POR
BOR
Value on all
other resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
0000 -010
0000 -010
98h
TXSTA
CSRC TX9 TXEN SYNC
—
—
BRGH TRMT TX9D
FERR OERR RX9D
0000 -00x
0000 0000
0000 -00x
0000 0000
18h
99h
RCSTA SPEN RX9 SREN CREN
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
1995 Microchip Technology Inc.
DS30390B-page 95
PIC16C7X
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
16 MHz
10 MHz
7.15909 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
2.4
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
NA
NA
NA
-
-
-
-
-
-
9.6
NA
-
+1.73
+0.16
+0.16
-1.96
0
-
NA
-
+0.16
+0.16
-0.79
+2.56
0
-
9.766
19.23
75.76
96.15
312.5
500
+1.73
+0.16
-1.36
+0.16
+4.17
0
255
129
32
25
7
4
0
255
9.622
19.24
77.82
94.20
298.3
NA
+0.23
+0.23
+1.32
-1.88
-0.57
-
185
92
22
18
5
-
0
255
19.2
76.8
96
300
500
HIGH
LOW
19.53
76.92
96.15
294.1
500
255
64
51
16
9
19.23
76.92
95.24
307.69
500
207
51
41
12
7
5000
19.53
-
-
0
255
4000
15.625
-
-
0
255
2500
9.766
-
-
1789.8
6.991
-
-
FOSC = 5.0688 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
2.4
NA
NA
NA
-
-
-
0
-
-
-
NA
NA
NA
9.622
19.04
74.57
99.43
298.3
NA
-
-
-
-
-
-
92
46
11
8
2
-
0
255
NA
1.202
2.404
9.615
19.24
83.34
NA
NA
NA
250
0.9766
-
-
207
103
25
12
2
-
-
-
0
0.303
1.170
NA
NA
NA
NA
NA
NA
NA
+1.14
-2.48
26
6
-
-
-
-
-
-
-
+0.16
+0.16
+0.16
+0.16
-
-
-
-
-
-
-
-
-
9.6
9.6
131
65
15
12
3
-
0
255
+0.23
-0.83
-2.90
+3.57
-0.57
-
19.2
76.8
96
300
500
HIGH
LOW
19.2
79.2
97.48
316.8
NA
0
+3.13
+1.54
+5.60
-
-
-
+8.51
-
-
-
-
-
1267
4.950
894.9
3.496
-
-
8.192
0.032
0
255
255
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
16 MHz
10 MHz
7.15909 MHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
2.4
NA
-
-
255
129
32
15
3
2
0
-
0
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
-
-
207
103
25
12
2
-
-
-
0
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
-
-
129
64
15
7
1
-
-
-
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
-
-
92
46
11
5
-
-
-
-
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
+0.16
+0.16
+0.16
+0.16
+0.16
+0.16
+1.73
+1.73
+0.23
-0.83
-2.90
-2.90
-
-
-
-
-
-
9.6
19.2
76.8
96
300
500
HIGH
LOW
+8.51
+1.73
-
-
-
-
-
-
-
-
-
-
312.5
1.221
-
-
0
255
0
255
255
255
FOSC = 5.0688 MHz
3.579545 MHz
1 MHz
32.768 kHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
0.3
1.2
2.4
0.31
1.2
2.4
+3.13
0
0
+3.13
+3.13
+3.13
-
-
-
-
-
255
65
32
7
3
0
-
-
-
0
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
+0.23
-0.83
+1.32
-2.90
185
46
22
5
2
-
-
-
-
0
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.63
0.0610
+0.16
+0.16
-6.99
51
12
6
-
-
-
-
-
-
0.256
NA
NA
NA
NA
NA
NA
NA
NA
-14.67
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
9.6
9.9
-
-
-
-
-
-
-
-
19.2
76.8
96
300
500
HIGH
LOW
19.8
79.2
NA
NA
NA
-2.90
-
-
-
-
-
-
79.2
0.3094
0
255
0.512
0.0020
0
255
255
255
DS30390B-page 96
1995 Microchip Technology Inc.
PIC16C7X
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
16 MHz
10 MHz
7.16 MHz
SPBRG
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
9.6
19.2
38.4
57.6
115.2
250
9.615
19.230
37.878
56.818
113.636
250
+0.16
+0.16
-1.36
-1.36
-1.36
0
129
64
32
21
10
4
9.615
19.230
38.461
58.823
111.111
250
+0.16
+0.16
+0.16
+2.12
-3.55
0
103
51
25
16
8
9.615
18.939
39.062
56.818
125
+0.16
-1.36
+1.7
-1.36
+8.51
-
64
32
15
10
4
9.520
19.454
37.286
55.930
111.860
NA
-0.83
+1.32
-2.90
-2.90
-2.90
-
46
22
11
7
3
-
3
NA
-
625
625
0
1
NA
-
-
625
0
0
NA
-
-
1250
1250
0
0
NA
-
-
NA
-
-
NA
-
-
FOSC = 5.068 MHz
3.579 MHz
1 MHz
32.768 kHz
BAUD
RATE
(K)
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
value
KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal) KBAUD %ERROR (decimal)
9.6
19.2
38.4
57.6
115.2
250
9.6
18.645
39.6
52.8
105.6
NA
0
-2.94
+3.12
-8.33
-8.33
-
32
16
7
5
2
-
9.727
18.643
37.286
55.930
111.860
223.721
NA
+1.32
-2.90
-2.90
-2.90
-2.90
-10.51
-
22
11
5
3
1
0
-
-
8.928
20.833
31.25
62.5
NA
NA
NA
NA
-6.99
+8.51
-18.61
+8.51
-
-
-
-
6
2
1
0
-
-
-
-
NA
NA
NA
NA
NA
NA
NA
NA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
625
1250
NA
NA
-
-
-
-
NA
-
1995 Microchip Technology Inc.
DS30390B-page 97
PIC16C7X
12.1.1 SAMPLING
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x16 clock (Figure 12-3). If bit BRGH is
FIGURE 12-3: RX PIN SAMPLING SCHEME (BRGH = 0)
Start bit
Bit0
RX
(RC7/RX/DT pin)
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
FIGURE 12-4: RX PIN SAMPLING SCHEME (BRGH = 1)
RX pin
bit0
bit1
Start Bit
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
1
2
3
4
1
2
Q2, Q4 clk
Samples
Samples
Samples
FIGURE 12-5: RX PIN SAMPLING SCHEME (BRGH = 1)
RX pin
Start Bit
bit0
Baud clk for all but start bit
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
Q2, Q4 clk
Samples
DS30390B-page 98
1995 Microchip Technology Inc.
PIC16C7X
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled or disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Sta-
tus bit TRMT is a read only bit which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
12.2
USART Asynchronous Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
is set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 12-6). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate trans-
fer to TSR resulting in an empty TXREG. A back-to-
back transfer is thus possible (Figure 12-8). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. As a result the RC6/TX/CK pin will revert to hi-
impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
12.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit maybe loaded in the TSR regis-
ter.
FIGURE 12-6: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
1995 Microchip Technology Inc.
DS30390B-page 99
PIC16C7X
Steps to follow when setting up a Asynchronous Trans-
mission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, then set enable bit
TXIE.
FIGURE 12-7: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Start Bit
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
TXIF bit
(interrupt reg. flag)
WORD 1
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0Ch
18h
19h
8Ch
PIR1
PSPIF
SPEN
TX7
ADIF
RX9
TX6
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCSTA
TXREG
PIE1
SREN CREN
—
FERR
TX2
OERR
TX1
RX9D
TX0
TX5
RCIE
TXEN
TX4
TX3
(1)
PSPIE
CSRC
ADIE
TX9
TXIE SSPIE CCP1IE TMR2IE TMR1IE
SYNC BRGH TRMT TX9D
98h
99h
TXSTA
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
DS30390B-page 100
1995 Microchip Technology Inc.
PIC16C7X
12.2.2 USART ASYNCHRONOUS RECEIVER
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte begin shift-
ing to the RSR register. On the detection of the STOP
bit of the third byte, if the RCREG register is still full
then overrun error bit OERR (RCSTA<1>) will be set.
The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO.
Overrun bit OERR has to be cleared in software. This
is done by resetting the receive logic (CREN is cleared
and then set). If bit OERR is set, transfers from the
RSR register to the RCREG register are inhibited, so it
is essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a stop bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 12-9.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register
(if it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled
or disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, i.e. it is a two deep FIFO. It is
FIGURE 12-9: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
RSR register
LSb
MSb
or
÷ 16
0
Baud Rate Generator
1
7
Stop (8)
Start
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 12-10: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1995 Microchip Technology Inc.
DS30390B-page 101
PIC16C7X
Steps to follow when setting up an Asynchronous
Reception:
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1).
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE were set.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
RX7
ADIF
RX9
RX6
ADIE
TX9
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
RCREG
PIE1
SREN CREN
—
FERR
RX2
OERR
RX1
RX9D
RX0
0000 -00x
0000 0000
RX5
RX4
RX3
(1)
PSPIE
CSRC
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
DS30390B-page 102
1995 Microchip Technology Inc.
PIC16C7X
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN are set, during a
transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
reset although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting since bit TXEN is still set.
The DT line will immediately switch from hi-impedance
receive mode to transmit and start driving. To avoid
this, bit TXEN should be cleared.
12.3
USART Synchronous Master Mode
Applicable Devices
70 71 71A 72 73 73A 74 74A
In Master Synchronous mode, the data is transmitted in
a half-duplex manner i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting bit SYNC
(TXSTA<4>). In addition enable bit SPEN (RCSTA<7>)
is set in order to configure the RC6/TX/CK and
RC7/RX/DT I/O pins to CK (clock) and DT (data) lines
respectively. The Master mode indicates that the pro-
cessor transmits the master clock on the CK line. The
Master mode is entered by setting bit CSRC
(TXSTA<7>).
12.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
The USART transmitter block diagram is shown in
Figure 12-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and an
interrupt bit, TXIF (PIR1<4>) is set. The interrupt can
be enabled or disabled by setting/clearing enable bit
TXIE (PIE1<4>). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register.
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory
so it is not available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-11). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN. This is advantageous when slow baud rates are
selected, since the BRG is kept in reset when bits
TXEN, CREN, and SREN are clear. Setting enable bit
TXEN will start the BRG, creating a shift clock immedi-
ately. Normally when transmission is first started, the
TSR register is empty, so a transfer to the TXREG reg-
ister will result in an immediate transfer to TSR result-
ing in an empty TXREG. Back-to-back transfers are
possible.
1995 Microchip Technology Inc.
DS30390B-page 103
PIC16C7X
TABLE 12-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTERTRANSMISSION
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
TX7
ADIF
RX9
TX6
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCSTA
TXREG
PIE1
SREN CREN
—
FERR
TX2
OERR
TX1
RX9D
TX0
TX5
TX4
TX3
(1)
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
TXEN SYNC
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
FIGURE 12-11: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
Bit 0
Bit 1
Bit 2
Bit 7
Bit 0
Bit 1
WORD 2
Bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT bit
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
'1'
TXEN bit
FIGURE 12-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
DS30390B-page 104
1995 Microchip Technology Inc.
PIC16C7X
12.3.2 USART SYNCHRONOUS MASTER
RECEPTION
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e. it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
RX7
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCSTA
RCREG
PIE1
RX9 SREN CREN
RX6 RX5 RX4
ADIE RCIE
TX9 TXEN SYNC
—
FERR
RX2
OERR
RX1
RX9D
RX0
RX3
(1)
PSPIE
CSRC
TXIE SSPIE CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
1995 Microchip Technology Inc.
DS30390B-page 105
PIC16C7X
FIGURE 12-13: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
DT pin
CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
SREN bit
SREN bit
CREN bit
'0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with SREN = '1' and BRG = '0'.
DS30390B-page 106
1995 Microchip Technology Inc.
PIC16C7X
12.4.2 USART SYNCHRONOUS SLAVE
12.4
USART Synchronous Slave Mode
Applicable Devices
RECEPTION
70 71 71A 72 73 73A 74 74A
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in slave mode.
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in the master mode). This allows the device to transfer
or receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
If receive is enabled, by setting bit CREN, prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
12.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
2. If interrupts are desired, then set enable bit
RCIE.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
Steps to follow when setting up a Synchronous Slave
Transmission:
8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
1995 Microchip Technology Inc.
DS30390B-page 107
PIC16C7X
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
TX7
ADIF
RX9
TX6
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCSTA
TXREG
PIE1
SREN CREN
—
FERR
TX2
OERR
TX1
RX9D
TX0
TX5
TX4
TX3
(1)
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
TXEN SYNC
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
RX7
ADIF
RCIF
TXIF SSPIF CCP1IF TMR2IF TMR1IF
RCSTA
RCREG
PIE1
RX9 SREN CREN
RX6 RX5 RX4
ADIE RCIE
TX9 TXEN SYNC
—
FERR
RX2
OERR
RX1
RX9D
RX0
RX3
(1)
PSPIE
CSRC
TXIE SSPIE CCP1IE TMR2IE TMR1IE
BRGH TRMT TX9D
TXSTA
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.
DS30390B-page 108
1995 Microchip Technology Inc.
PIC16C7X
or the voltage level on the RA3/AN3/VREF pin. The A/D
converter has a unique feature of being able to operate
while the device is in SLEEP mode.
13.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
Applicable Devices
The A/D module has three registers. These registers
are:
70 71 71A 72 73 73A 74 74A
The analog-to-digital (A/D) converter module has four
analog inputs for the PIC16C70/71/71A, five inputs for
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
the
PIC16C72/73/73A,
and
eight
for
the
PIC16C74/74A.
The ADCON0 register, shown in Figure 13-1 and
Figure 13-2, controls the operation of the A/D module.
The ADCON1 register, shown in Figure 13-3 and
Figure 13-4, configures the functions of the port pins.
The port pins can be configured as analog inputs (RA3
can also be a voltage reference) or as digital I/O.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number (refer to Applica-
tion Note AN546 for use of A/D Converter). The output
of the sample and hold is the input into the converter,
which generates the result via successive approxima-
tion. The analog reference voltage is software select-
able to either the device’s positive supply voltage (VDD)
FIGURE 13-1: ADCON0 REGISTER, PIC16C70/71/71A (ADDRESS 08h)
R/W-0 R/W-0
ADCS1 ADCS0
U-0
R/W-0
CHS1
R/W-0
R/W-0
R/W-0
ADIF
R/W-0
ADON
(1)
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented
bit, read as ‘0’
—
bit7
bit0
- n =Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5:
Unimplemented: Read as '0'.
bit 4-3: CHS2:CHS0: Analog Channel Select bits
00= channel 0, (RA0/AN0)
01= channel 1, (RA1/AN1)
10= channel 2, (RA2/AN2)
11= channel 3, (RA3/AN3)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-
sion is complete)
bit 1:
bit 0:
ADIF: A/D Conversion Complete Interrupt Flag bit
1 = conversion is complete (must be cleared in software)
0 = conversion is not complete
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
Note 1: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C71 only. For the PIC16C70/71A, this bit is
unimplemented, read as '0'.
1995 Microchip Technology Inc.
DS30390B-page 109
PIC16C7X
FIGURE 13-2: ADCON0 REGISTER, PIC16C72/73/73A/74/74A (ADDRESS 1Fh)
R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2
bit7
R/W-0
CHS1
R/W-0
R/W-0
U-0
—
R/W-0
ADON
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from an RC oscillation)
bit 5-3: CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)
110= channel 6, (RE1/AN6)
111= channel 7, (RE2/AN7)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 =A/D conversion not in progress (This bit is automatically cleared by hardware when theA/D conversion
is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shutoff and consumes no operating current
FIGURE 13-3: ADCON1 REGISTER FOR PIC16C70/71/71A (ADDRESS 88h)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PCFG1
PCFG0
R =Readable bit
W = Writable bit
bit7
bit0
U =Unimplemented
bit, read as ‘0’
- n =Value at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1-0: PCFG1:PCFG0: A/D Port Configuration Control bits
PCFG1:PCFG0 RA1 & RA0
RA2
RA3
VREF
00
01
10
11
A
A
A
D
A
A
D
D
A
VDD
RA3
VDD
VDD
VREF
D
D
A = Analog input
D = Digital I/O
DS30390B-page 110
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 13-4: ADCON1 REGISTER, PIC16C72/73/73A/74/74A (ADDRESS 9Fh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
PCFG2
PCFG1
PCFG0
R =Readable bit
W = Writable bit
bit7
bit0
U =Unimplemented
bit, read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0
RA0
RA1
RA2
RA5
RA3
RE0
RE1
RE2
VREF
VDD
000
001
010
011
100
101
11x
A
A
A
A
A
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
D
A
A
A
D
D
D
A
A
A
D
D
D
VREF
A
A
D
D
D
D
D
RA3
VDD
RA3
VDD
RA3
—
VREF
A
VREF
D
A = Analog input
D = Digital I/O
1995 Microchip Technology Inc.
DS30390B-page 111
PIC16C7X
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is completed, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagrams of the A/D module are
shown in Figure 13-5 and Figure 13-6.
3. Wait the required sampling time.
4. Start conversion:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
After the A/D module has been configured as desired,
the selected channel must be sampled before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 13.1.
After this sample time has elapsed the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
• Waiting for the A/D interrupt
6. Read A/D Result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next sampling starts.
1. Configure the A/D module:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
FIGURE 13-5: A/D BLOCK DIAGRAM, PIC16C70/71/71A
CHS1:CHS0
11
10
01
00
RA3/AN3/VREF
RA2/AN2
VIN
(Input voltage)
A/D
Converter
RA1/AN1
RA0/AN0
VDD
00or
10or
11
VREF
(Reference
voltage)
01
PCFG1:PCFG0
DS30390B-page 112
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 13-6: A/D BLOCK DIAGRAM, PIC16C72/73/73A/74/74A
CHS2:CHS0
111
110
101
100
011
010
001
000
(1)
RE2/AN7
(1)
RE1/AN6
(1)
RE0/AN5
RA5/AN4
RA3/AN3/VREF
RA2/AN2
VIN
(Input voltage)
A/D
Converter
RA1/AN1
VDD
RA0/AN0
000or
010or
100
VREF
(Reference
voltage)
001or
011or
101
PCFG2:PCFG0
Note 1: Not available on PIC16C72/73/73A.
1995 Microchip Technology Inc.
DS30390B-page 113
PIC16C7X
13.1
A/D Sampling Requirements
Applicable Devices
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
70 71 71A 72 73 73A 74 74A
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 13-7. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 13-7.The maximum recommended
impedance for analog sources is 10 kΩ. After the
analog input channel is selected (changed) this sam-
pling must be done before the conversion can be
started.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0 TAD delay must complete before sam-
pling can begin again. During this time the
holding capacitor is not connected to the
selected A/D input channel.
EXAMPLE 13-1: CALCULATING THE
MINIMUM REQUIRED
To calculate the minimum sampling time, Equation 13-
1 may be used. This equation assumes that 1/2 LSb
error is used (512 steps for the A/D). The 1/2 LSb error
is the maximum error allowed for the A/D to meet its
specified resolution.
SAMPLE TIME
TSMP = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
EQUATION 13-1: A/D MINIMUM CHARGING
TIME
TSMP = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
(-Tc/CHOLD(RIC + RSS + RS))
VHOLD = (VREF - (VREF/512)) • (1 - e
)
TC =
-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2146)
or
Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)
Example 13-1 shows the calculation of the minimum
required sample time TSMP. This calculation is based
on the following system assumptions.
5.724 µs
TSMP = 5 µs + 5.724 µs + [(50°C - 25°C)(0.05 µs/°C)]
Rs = 10 kΩ
10.724 µs + 1.25 µs
11.974 µs
1/2 LSb error
VDD = 5V → Rss = 7 kΩ
Temp (system max.) = 50°C
VHOLD = 0 @ t = 0
FIGURE 13-7: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
RAx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
= DAC capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
I leakage = leakage current at the pin due to
various junctions
VDD 4V
3V
2V
RIC
SS
= interconnect resistance
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30390B-page 114
1995 Microchip Technology Inc.
PIC16C7X
13.2
Selecting the A/D Conversion Clock
Applicable Devices
13.3
Configuring Analog Port Pins
Applicable Devices
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selected. The four possible options for TAD are:
The ADCON1, TRISA, and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
• 2TOSC
• 8TOSC
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
• 32TOSC
• Internal RC oscillator
Note 1: When reading the port register, all pins
configured as analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of:
2.0 µs for the PIC16C71
1.6 µs for all other PIC16C7X devices
Table 13-2 and Table 13-1 show the resultant TAD
times derived from the device operating frequencies
and the A/D clock source selected.
Note 2: Analog levels on any pin that is defined as
a digital input (including the AN7:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
TABLE 13-1: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71
AD Clock Source (TAD)
Device Frequency
4 MHz
Operation
ADCS1:ADCS0
20 MHz
16 MHz
1 MHz
2.0 µs
8.0 µs
333.33 kHz
(2)
(2)
(2)
2TOSC
8TOSC
32TOSC
RC
00
01
10
11
6 µs
100 ns
125 ns
500 ns
(2)
(2)
(3)
2.0 µs
8.0 µs
400 ns
500 ns
24 µs
(2)
(3)
(3)
2.0 µs
1.6 µs
32.0 µs
2 - 6 µs
96 µs
(1,4)
(1,4)
(1,4)
(1)
(1)
2 - 6 µs
2 - 6 µs
2 - 6 µs
2 - 6 µs
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
TABLE 13-2: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C70/71A/72/73/73A/74/74A
AD Clock Source (TAD)
Operation ADCS1:ADCS0
Device Frequency
5 MHz 1.25 MHz
20 MHz
333.33 kHz
(2)
(2)
2TOSC
8TOSC
32TOSC
RC
00
01
10
11
1.6 µs
6.4 µs
6 µs
100 ns
400 ns
(2)
(3)
1.6 µs
6.4 µs
400 ns
24 µs
(3)
(3)
1.6 µs
25.6 µs
96 µs
(1,4)
(1,4)
(1,4)
(1)
2 - 6 µs
2 - 6 µs
2 - 6 µs
2 - 6 µs
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.
1995 Microchip Technology Inc.
DS30390B-page 115
PIC16C7X
13.4
A/D Conversions
Note: The GO/DONE bit should NOT be set in
Applicable Devices
the same instruction that turns on the A/D.
70 71 71A 72 73 73A 74 74A
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next sampling is started. After
this 2TAD wait, sampling is automatically started on the
selected channel.
Example 13-2 and Example 13-3 show how to perform
an A/D conversion. The RA pins are configured as ana-
log inputs. The analog reference (VREF) is the device
VDD. The A/D interrupt is enabled, and the A/D conver-
sion clock is FRC. The conversion is performed on the
RA0 channel.
EXAMPLE 13-2: DOING AN A/D CONVERSION (PIC16C70/71/71A)
BSF
CLRF
BCF
MOVLW
MOVWF
BSF
STATUS, RP0
ADCON1
STATUS, RP0
0xC1
ADCON0
INTCON, ADIE
INTCON, GIE
; Select Page 1
; Configure A/D inputs
; Select Page 0
; RC Clock, A/D is on, Channel 0 is selected
;
; Enable A/D Interrupt
; Enable all interrupts
BSF
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
ADCON0, GO
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
:
;
is cleared upon completion of the A/D Conversion.
EXAMPLE 13-3: DOING AN A/D CONVERSION (PIC16C72/73/73A/74/74A)
BSF
CLRF
BSF
STATUS, RP0
ADCON1
; Select Page 1
; Configure A/D inputs
; Enable A/D interrupts
; Select Page 0
; RC Clock, A/D is on, Channel 0 is selected
;
; Clear A/D interrupt flag bit
; Enable peripheral interrupts
; Enable all interrupts
PIE1,
ADIE
BCF
STATUS, RP0
0xC1
ADCON0
MOVLW
MOVWF
BCF
BSF
BSF
PIR1,
ADIF
INTCON, PEIE
INTCON, GIE
;
;
;
;
Ensure that the required sampling time for the selected input channel has elapsed.
Then the conversion may be started.
BSF
:
ADCON0, GO
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE bit
:
;
is cleared upon completion of the A/D Conversion.
DS30390B-page 116
1995 Microchip Technology Inc.
PIC16C7X
13.4.1 FASTER CONVERSION - LOWER
RESOLUTION TRADE-OFF
Since the TAD is based from the device oscillator, the
user must use some method (a timer, software loop,
etc.) to determine when the A/D oscillator may be
changed. Example 13-4 shows a comparison of time
required for a conversion with 4-bits of resolution, ver-
sus the 8-bit resolution conversion. The example is for
devices operating at 20 MHz and 16 MHz (The A/D
clock is programmed for 32TOSC), and assumes that
immediately after 6TAD, the A/D clock is programmed
for 2TOSC.
Not all applications require a result with 8-bits of reso-
lution, but may instead require a faster conversion
time. The A/D module allows users to make the trade-
off of conversion speed to resolution. Regardless of the
resolution required, the sampling time is the same. To
speed up the conversion, the clock source of the A/D
module may be switched so that the TAD time violates
the minimum specified time (see the applicable electri-
cal specification). Once the TAD time violates the mini-
mum specified time, all the following A/D result bits are
not valid (see A/D Conversion Timing in the Electrical
Specifications section.) The clock sources may only be
switched between the three oscillator versions (cannot
be switched from/to RC). The equation to determine
the time before the oscillator can be switched is as fol-
lows:
The 2TOSC violates the minimum TAD time since the
last 4-bits will not be converted to correct values.
Conversion time = 2TAD + N•TAD + (8 - N)(2TOSC)
Where: N = number of bits of resolution required.
EXAMPLE 13-4: 4-BIT vs. 8-BIT CONVERSION TIMES
Resolution
(1)
Freq. (MHz)
4-bit
8-bit
TAD
20
16
20
16
20
16
1.6 µs
2.0 µs
50 ns
1.6 µs
2.0 µs
50 ns
TOSC
62.5 ns
10 µs
62.5 ns
16 µs
2TAD + N•TAD + (8 - N)(2TOSC)
12.5 µs
20 µs
Note 1: The PIC16C71 has a minimum TAD time of 2.0 µs.
All other PIC16C7X devices have a minimum TAD time of 1.6 µs.
1995 Microchip Technology Inc.
DS30390B-page 117
PIC16C7X
In systems where the device will enter SLEEP mode
after the start of the A/D conversion, the RC clock
source selection is required. In this mode, the digital
noise from the modules in SLEEP are stopped. This
method gives high accuracy.
13.5
A/D Operation During Sleep
Applicable Devices
70 71 71A 72 73 73A 74 74A
TheA/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed the GO/DONE bit will be cleared, and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If theA/D interrupt is not enabled, theA/D mod-
ule will then be turned off, although the ADON bit will
remain set.
13.7
Effects of a RESET
Applicable Devices
70 71 71A 72 73 73A 74 74A
A device reset forces all registers to their reset state.
This forces the A/D module to be turned off, and any
conversion is aborted. The value that is in the ADRES
register is not modified for a Power-on Reset. The
ADRES register will contain unknown data after a
Power-on Reset.
13.8
Use of the CCP Trigger
Applicable Devices
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
70 71 71A 72 73 73A 74 74A
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: In the PIC16C72 the "special event trigger"
is implemented in the CCP1 module.
An A/D conversion can be started by the “special event
trigger” of the CCP2 module (CCP1 on the PIC16C72
only). This requires that the CCP2M3:CCP2M0 bits
(CCP2CON<3:0>) be programmed as 1011 and that
the A/D module is enabled (ADON bit is set). When the
trigger occurs, the GO/DONE bit will be set, starting the
A/D conversion, and the Timer1 counter will be reset to
zero. Timer1 is reset to automatically repeat the A/D
sampling period with minimal software overhead (mov-
ing the ADRES to the desired location). The appropri-
ate analog input channel must be selected and the
minimum sampling done before the “special event trig-
ger” sets the GO/DONE bit (starts a conversion).
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, the GO/DONE bit
must be set, followed by the SLEEPinstruc-
tion.
13.6
A/D Accuracy/Error
Applicable Devices
70 71 71A 72 73 73A 74 74A
The overall accuracy of the A/D is less than ± 1 LSb for
VDD = 5V ± 10% and the analog VREF = VDD. This over-
all accuracy includes offset error, full scale error, and
integral error. The A/D converter is guaranteed to be
monotonic. The resolution and accuracy may be less
when either the analog reference (VDD) is less than
5.0V or when the analog reference (VREF) is less than
VDD.
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
The maximum pin leakage current is ± 5 µA.
In systems where the device frequency is low, use of
the A/D RC clock derived from the device oscillator, is
preferred. At moderate to high frequencies, TAD should
be derived from the device oscillator. TAD must not vio-
late the minimum and should be ≤ 8 µs for preferred
operation. This is because TAD, when derived from
TOSC, is kept away from on-chip phase clock transi-
tions. This reduces, to a large extent, the effects of dig-
ital switching noise. This is not possible with the RC
derived clock. The loss of accuracy due to digital
switching noise can be significant if many I/O pins are
active.
DS30390B-page 118
1995 Microchip Technology Inc.
PIC16C7X
13.9
Connection Considerations
Applicable Devices
FIGURE 13-8: A/D TRANSFER FUNCTION
70 71 71A 72 73 73A 74 74A
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specification.
Note: For the PIC16C70/71/71A,
care must be taken when using the RA0
pin in A/D conversions due to its proximity
to the OSC1 pin.
FFh
FEh
An external RC filter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 kΩ recommended specification. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.)
should have very little leakage current at the pin.
04h
03h
02h
01h
00h
13.10 Transfer Function
Applicable Devices
Analog input voltage
70 71 71A 72 73 73A 74 74A
The ideal transfer function of theA/D converter is as fol-
lows: the first transition occurs when the analog input
voltage (VAIN) is 1 LSb (or Analog VREF / 256)
(Figure 13-8).
FIGURE 13-9: FLOWCHART OF A/D OPERATION
ADON = 0
Yes
ADON = 0?
No
Sample
Selected Channel
Yes
GO = 0?
No
Yes
Yes
Start of A/D
Conversion Delayed
1 Instruction Cycle
Finish Conversion
SLEEP
Instruction?
A/D Clock
= RC?
GO = 0
ADIF = 1
No
No
Yes
Yes
Abort Conversion
GO = 0
Wake-up
From Sleep?
Finish Conversion
Device in
SLEEP?
Wait 2 TAD
GO = 0
ADIF = 1
ADIF = 0
No
No
SLEEP
Power-down A/D
Finish Conversion
Stay in Sleep
Power-down A/D
Wait 2 TAD
GO = 0
ADIF = 1
Wait 2 TAD
1995 Microchip Technology Inc.
DS30390B-page 119
PIC16C7X
TABLE 13-3: SUMMARY OF A/D REGISTERS, PIC16C70/71/71A
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
ADRES
ADCON0 ADCS1 ADCS0
GIE
ADIE T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
xxxx xxxx
0000 000u
uuuu uuuu
00-0 0000
---- --00
---u uuuu
---1 1111
0Bh/8Bh
89h
A/D Result Register
—
—
CHS1
—
CHS0 GO/DONE
ADIF
ADON 00-0 0000
08h
ADCON1
—
—
—
—
PCFG1 PCFG0 ---- --00
88h
---x xxxx
---1 1111
05h
PORTA
TRISA
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
85h
TRISA4 TRISA3
TRISA2 TRISA1 TRISA0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
TABLE 13-4: SUMMARY OF A/D REGISTERS, PIC16C72
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
—
PEIE
ADIF
ADIE
T0IE
—
INTE
—
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
0000 00-0
---- -000
--uu uuuu
--11 1111
0Bh/8Bh
0Ch
8Ch
1Eh
PIR1
CCP1IF TMR2IF TMR1IF -0-- 0000
CCP1IE TMR2IE TMR1IE -0-- 0000
xxxx xxxx
PIE1
—
—
—
ADRES
A/D Result Register
ADCON0 ADCS1 ADCS0 CHS2
CHS1
—
CHS0 GO/DONE
—
ADON 0000 00-0
1Fh
ADCON1
—
—
—
—
PCFG2
RA2
PCFG1 PCFG0 ---- -000
9Fh
--xx xxxx
--11 1111
05h
PORTA
TRISA
—
—
—
—
RA5
RA4
RA3
RA1
RA0
85h
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
TABLE 13-5: SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A
Value on:
POR
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
ADIF
ADIE
—
T0IE
RCIF
RCIE
—
INTE
TXIF
TXIE
—
RBIE
SSPIF
SSPIE
—
T0IF
INTF
RBIF
0000 000x
0000 000u
0000 0000
0000 0000
---- ---0
---- ---0
uuuu uuuu
0000 00-0
---- -000
--uu uuuu
--11 1111
---- -uuu
0000 -111
0Bh/8Bh
0Ch
8Ch
0Dh
8Dh
1Eh
1Fh
(1)
PIR1
PIE1
PSPIF
PSPIE
—
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
(1)
PIR2
—
—
—
—
CCP2IF ---- ---0
CCP2IE ---- ---0
xxxx xxxx
PIE2
—
—
—
—
—
ADRES
A/D Result Register
ADCON0 ADCS1 ADCS0 CHS2
CHS1
—
CHS0 GO/DONE
—
ADON 0000 00-0
ADCON1
—
—
—
—
—
—
PCFG2
RA2
PCFG1 PCFG0 ---- -000
9Fh
--xx xxxx
--11 1111
---- -xxx
0000 -111
05h
PORTA
TRISA
PORTE
TRISE
RA5
RA4
RA3
RA1
RA0
85h
—
—
—
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
—
—
—
—
09h
RE2
RE1
RE0
89h
IBF
OBF
IBOV PSPMODE
TRISE2 TRISE1 TRISE0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73/73A, always maintain these bits clear.
DS30390B-page 120
1995 Microchip Technology Inc.
PIC16C7X
designed to keep the part in reset while the power sup-
ply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
14.0 SPECIAL FEATURES OF THE
CPU
Applicable Devices
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
70 71 71A 72 73 73A 74 74A
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection. These are:
14.1
Configuration Bits
Applicable Devices
• OSC selection
• Reset
70 71 71A 72 73 73A 74 74A
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h -
3FFFh), which can be accessed only during program-
ming.
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
• In-circuit serial programming
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
FIGURE 14-1: CONFIGURATION WORD FOR PIC16C71
—
—
—
—
—
—
—
—
—
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register: CONFIG
Address 2007h
bit13
bit 13-5: Unimplemented: Read as '1'
bit 4:
bit 3:
bit 2:
CP0: Code protection bit
1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
1995 Microchip Technology Inc.
DS30390B-page 121
PIC16C7X
FIGURE 14-2: CONFIGURATION WORD FOR PIC16C70/71A
CP0
CP0
CP0
CP0
CP0
CP0
CP0 BODEN CP0
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register: CONFIG
Address 2007h
bit13
(2)
bit 13-7 CP0: Code protection bits
5-4: 1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
(1)
bit 6:
bit 3:
bit 2:
BODEN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
(1)
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.
FIGURE 14-3: CONFIGURATION WORD FOR PIC16C73/74
—
—
—
—
—
—
—
—
CP1
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register: CONFIG
Address 2007h
bit13
bit 13-5: Unimplemented: Read as '1'
bit 4:
CP1:CP0: Code protection bits
11= Code protection off
10= Upper half of program memory code protected
01= Upper 3/4th of program memory code protected
00= All memory is code protected
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
DS30390B-page 122
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 14-4: CONFIGURATION WORD FOR PIC16C72/73A/74A
CP1
CP0
CP1
CP0
CP1
CP0
—
BODEN CP1
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register: CONFIG
Address
2007h
bit13
(2)
bit 13-8 CP1:CP0: Code Protection bits
5-4: 11= Code protection off
10= Upper half of program memory code protected
01= Upper 3/4th of program memory code protected
00= All memory is code protected
bit 7:
bit 6:
Unimplemented: Read as '1'
(1)
BODEN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
14.2
Oscillator Configurations
Applicable Devices
FIGURE 14-5: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
70 71 71A 72 73 73A 74 74A
OSC CONFIGURATION)
14.2.1 OSCILLATOR TYPES
OSC1
To internal
(2)
The PIC16CXX can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
logic
C1
XTAL
OSC2
SLEEP
PIC16CXX
RF
• LP
• XT
• HS
• RC
Low Power Crystal
To internal
logic
RS
(2)
C2
Note1
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
See Table 14-1, Table 14-2, Table 14-3 and Table 14-4 for
recommended values of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut crystals.
14.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
2: For the PIC16C70/71/71A the buffer is on the
OSC2 pin, all other devices have the buffer on
the OSC1 pin.
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 14-5). The
PIC16CXX Oscillator design requires the use of a par-
allel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifica-
tions. When in XT, LP or HS modes, the device can
have an external clock source to drive the OSC1/
CLKIN pin (Figure 14-6).
FIGURE 14-6: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
OSC2
Clock from
ext. system
PIC16CXX
Open
1995 Microchip Technology Inc.
DS30390B-page 123
PIC16C7X
TABLE 14-1: CERAMIC RESONATORS
PIC16C71
TABLE 14-3: CERAMIC RESONATORS
PIC16C70/71A/72/73/73A/74/
74A
Ranges Tested:
Ranges Tested:
Mode
XT
Freq
OSC1
OSC2
Mode
XT
Freq
OSC1
OSC2
455 kHz
2.0 MHz
4.0 MHz
47 - 100 pF 47 - 100 pF
15 - 68 pF 15 - 68 pF
15 - 68 pF 15 - 68 pF
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
15 - 68 pF 15 - 68 pF
10 - 47 pF 10 - 47 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Note: Recommended values of C1 and C2 are identical to
the ranges tested table.
Note: Recommended values of C1 and C2 are identical to
the ranges tested table.
Higher capacitance increases the stability of oscilla-
tor but also increases the start-up time. These val-
ues are for design guidance only. Since each
resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
Higher capacitance increases the stability of oscil-
lator but also increases the start-up time. These
values are for design guidance only. Since each
resonator has its own characteristics, the user
should consult the resonator manufacturer for
appropriate values of external components.
Resonators Used:
Resonators Used:
455 kHz
Panasonic EFO-A455K04B ± 0.3%
455 kHz Panasonic EFO-A455K04B ± 0.3%
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
± 0.5%
± 0.5%
± 0.5%
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
± 0.5%
± 0.5%
± 0.5%
± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators used did not have built-in capacitors.
All resonators used did not have built-in capacitors.
TABLE 14-4: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
FOR PIC16C70/71A/72/73/73A/
74/74A
TABLE 14-2: CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
FOR PIC16C71
Mode
Freq
OSC1
OSC2
Mode
Freq
OSC1
OSC2
32 kHz(1)
200 kHz
LP
33 - 68 pF
15 - 47 pF
33 - 68 pF
15 - 47 pF
LP
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 33 pF
32 kHz
200 kHz
XT
100 kHz
500 kHz
1 MHz
2 MHz
4 MHz
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
XT
100 kHz
500 kHz
1 MHz
2 MHz
4 MHz
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
HS
8 MHz
20 MHz
15 - 47 pF
15 - 47 pF
15 - 47 pF
15 - 47 pF
HS
8 MHz
20 MHz
15 - 47 pF
15 - 47 pF
15 - 47 pF
15 - 47 pF
Note: Higher capacitance increases the stability of oscil-
lator but also increases the start-up time. These
values are for design guidance only. Rs may be
required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specifica-
tion. Since each crystal has its own characteristics,
the user should consult the crystal manufacturer for
appropriate values of external components.
Note: Higher capacitance increases the stability of oscil-
lator but also increases the start-up time. These
values are for design guidance only. Rs may be
required in HS mode as well as XT mode to avoid
overdriving crystals with low drive level specifica-
tion. Since each crystal has its own characteristics,
the user should consult the crystal manufacturer for
appropriate values of external components.
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-
mended.
DS30390B-page 124
1995 Microchip Technology Inc.
PIC16C7X
14.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
14.2.4 RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (Rext) and capacitor (Cext) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
Cext values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 14-9 shows how the R/C combina-
tion is connected to the PIC16CXX. For Rext values
below 2.2 kΩ, the oscillator operation may become
unstable, or stop completely. For very high Rext values
(e.g. 1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend to keep
Rext between 3 kΩ and 100 kΩ.
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepack-
aged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types of
crystal oscillator circuits can be used; one with series
resonance, or one with parallel resonance.
Figure 14-7 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a par-
allel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potenti-
ometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 14-7: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or pack-
age lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
CLKIN
74AS04
See characterization data for desired device for RC fre-
quency variation from part to part due to normal pro-
cess variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
10k
See characterization data for desired device for varia-
tion of oscillator frequency due to VDD for given Rext/
Cext values as well as frequency variation due to oper-
ating temperature for given R, C, and VDD values.
20 pF
20 pF
Figure 14-8 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a 180-
degree phase shift in a series resonant oscillator cir-
cuit. The 330 kΩ resistors provide the negative feed-
back to bias the inverters in their linear region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic (see Figure 3-5 for
waveform).
FIGURE 14-9: RC OSCILLATOR MODE
FIGURE 14-8: EXTERNAL SERIES
RESONANT CRYSTAL
VDD
OSCILLATOR CIRCUIT
Rext
Internal
OSC1
To Other
clock
Devices
330 kΩ
330 kΩ
PIC16CXX
Cext
74AS04
74AS04
74AS04
PIC16CXX
VSS
CLKIN
0.1 µF
OSC2/CLKOUT
Fosc/4
XTAL
1995 Microchip Technology Inc.
DS30390B-page 125
PIC16C7X
Table 14-7 and Table 14-8. These bits are used in soft-
ware to determine the nature of the reset. See
Table 14-10 for a full description of reset states of all
registers.
14.3
Reset
Applicable Devices
70 71 71A 72 73 73A 74 74A
The PIC16CXX differentiates between various kinds of
reset:
A simplified block diagram of the on-chip reset circuit is
shown in Figure 14-10.
• Power-on Reset (POR)
The PIC16C70/71A/72/73A/74A have a MCLR noise
filter in the MCLR reset path. The filter will detect and
ignore small pulses.
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
It should be noted that a WDT Reset does not drive
MCLR pin low.
• Brown-out Reset (BOR) (PIC16C70/71A/72/73A/
74A only)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, on MCLR reset during SLEEP, and Brown-
out Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation. The TO and PD bits are set or cleared differ-
ently in different reset situations as indicated in
FIGURE 14-10: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
(2)
S
R
Reset
BODEN
OST/PWRT
OST
10-bit Ripple counter
Chip_Reset
Q
OSC1
PWRT
10-bit Ripple counter
(1)
On-chip
RC OSC
Note 1: This is a separate oscillator from the RC
oscillator of the CLKIN pin.
Enable PWRT
Enable OST
See Table 14-5 and Table 14-6 for time-
out situations.
2: Brown-out Reset is implemented on the
PIC16C70/71A/72/73A/74A only.
DS30390B-page 126
1995 Microchip Technology Inc.
PIC16C7X
The power-up time delay will vary from chip to chip and
due to VDD, temperature, and process variation. See
DC parameters for details.
14.4
Power-on Reset (POR), Power-up
Timer (PWRT) and Oscillator Start-up
Timer (OST), Brown-out Reset (BOR)
Applicable Devices
14.4.3 OSCILLATOR START-UP TIMER (OST)
70 71 71A 72 73 73A 74 74A
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal oscil-
lator or resonator has started and stabilized.
14.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
specified. See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
14.4.4 BROWN-OUT RESET (BOR)
Applicable Devices
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be meet to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
70 71 71A 72 73 73A 74 74A
A configuration bit, BODEN, can disable (if clear/pro-
grammed) or enable (if set) the Brown-out Reset cir-
cuitry. If VDD falls below 4.0V (3.8V - 4.2V range) for
greater than parameter #35, the brown-out situation
will reset the chip. A reset may not occur if VDD falls
below 4.0V for less than parameter #35. The chip will
remain in Brown-out Reset until VDD rises above BVDD.
The Power-up Timer will now be invoked and will keep
the chip in RESET an additional 72 ms. If VDD drops
below BVDD while the Power-up Timer is running, the
chip will go back into a Brown-out Reset and the
Power-up Timer will be initialized. Once VDD rises
above BVDD, the Power-up Timer will execute a 72 ms
reset. The Power-up Timer should always be enabled
when Brown-out Reset is enabled. Figure 14-11 shows
typical brown-out situations.
For additional information, refer to Application Note
AN607, "Power-up Trouble Shooting."
14.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in reset as long as the PWRT is active. The
PWRT’s time delay allows VDD to rise to an acceptable
level. A configuration bit is provided to enable/disable
the PWRT.
FIGURE 14-11: BROWN-OUT SITUATIONS
VDD
BVDD Max.
BVDD Min.
Internal
Reset
72 ms
VDD
BVDD Max.
BVDD Min.
Internal
Reset
<72 ms
72 ms
VDD
BVDD Max.
BVDD Min.
Internal
Reset
72 ms
1995 Microchip Technology Inc.
DS30390B-page 127
PIC16C7X
14.4.5 TIME-OUT SEQUENCE
14.4.6 POWER CONTROL/STATUS REGISTER
(PCON)
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after the POR time delay
has expired. Then OST is activated. The total time-out
will vary based on oscillator configuration and the sta-
tus of the PWRT. For example, in RC mode with the
PWRT disabled, there will be no time-out at all.
Figure 14-12, Figure 14-13, and Figure 14-14 depict
time-out sequences on power-up.
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Power Control/Status Register, PCON has up to 2
bits, depending upon the device. Bit0 is not imple-
mented on the PIC16C73 or PIC16C74.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent resets to see if bit
BOR cleared, indicating a BOR occurred. The BOR bit
is a "Don’t Care" bit and is not necessarily predictable
if the Brown-out Reset circuitry is disabled (by clearing
bit BODEN in the Configuration Word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(Figure 14-13). This is useful for testing purposes or to
synchronize more than one PIC16CXX device operat-
ing in parallel.
Bit1 is Power-on Reset Status bit POR. It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
Table 14-9 shows the reset conditions for some special
function registers, while Table 14-10 shows the reset
conditions for all the registers.
TABLE 14-5: TIME-OUT IN VARIOUS SITUATIONS, PIC16C71/73/74
Oscillator Configuration
Power-up
Wake-up from SLEEP
PWRTE = 1
PWRTE = 0
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
1024 TOSC
—
TABLE 14-6: TIME-OUT IN VARIOUS SITUATIONS, PIC16C70/71A/72/73A/74A
Oscillator Configuration
Power-up
PWRTE = 0
Wake-up from SLEEP
Brown-out
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
72 ms + 1024TOSC
72 ms
1024TOSC
—
TABLE 14-7: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71/73/74
(1)
POR
TO
PD
0
0
0
1
1
1
1
1
0
x
0
0
1
1
1
x
0
1
0
1
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Note 1: Bit POR is not implemented on the PIC16C71.
TABLE 14-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C70/71A/72/73A/74A
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
x
0
0
1
1
1
x
0
x
1
0
1
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
DS30390B-page 128
1995 Microchip Technology Inc.
PIC16C7X
TABLE 14-9: RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
PCON
Register
PCON
Register
Condition
Power-on Reset
PIC16C70/71A
PIC16C73/74
PIC16C72/73A/74A
000h
000h
000h
000h
PC + 1
000h
0001 1xxx
0001 1uuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
---- --0-
---- --u-
---- --u-
---- --u-
---- --u-
N/A
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
WDT Wake-up
Brown-out Reset
(1)
Interrupt wake-up from SLEEP
PC + 1
---- --u-
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded
with the interrupt vector (0004h).
TABLE 14-10: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or
Interrupt
W
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
(2)
PC + 1
(3)
(3)
STATUS
FSR
70 71 71A 72 73 73A 74 74A
0001 1xxx
000q quuu
uuuq quuu
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
xxxx xxxx
---x xxxx
--xx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
uuuu uuuu
---u uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
uuuu uuuu
---u uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
(1)
uuuu uuuu
(1)
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
-0-- 0000
-000 0000
0000 0000
---- ---0
-0-- 0000
-000 0000
0000 0000
---- ---0
-u-- uuuu
(1)
PIR1
PIR2
-uuu uuuu
(1)
uuuu uuuu
(1)
---- ---u
TMR1L
TMR1H
T1CON
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
xxxx xxxx
xxxx xxxx
--00 0000
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-9 for reset value for specific condition.
1995 Microchip Technology Inc.
DS30390B-page 129
PIC16C7X
TABLE 14-10: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via
WDT or
Interrupt
TMR2
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
00-0 0000
0000 00-0
1111 1111
---1 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
-0-- 0000
-000 0000
0000 0000
---- ---0
---- --0-
---- --0u
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
---- --00
---- -000
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
00-0 0000
0000 00-0
1111 1111
---1 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
-0-- 0000
-000 0000
0000 0000
---- ---0
---- --u-
---- --uu
1111 1111
0000 0000
--00 0000
0000 -010
0000 0000
---- --00
---- -000
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-u uuuu
uuuu uu-u
uuuu uuuu
---u uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
-u-- uuuu
-uuu uuuu
uuuu uuuu
---- ---u
---- --u-
---- --uu
1111 1111
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
---- --uu
---- -uuu
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON 70 71 71A 72 73 73A 74 74A
RCSTA
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON 70 71 71A 72 73 73A 74 74A
ADRES
ADCON0
OPTION
TRISA
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as '0', q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 14-9 for reset value for specific condition.
DS30390B-page 130
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 14-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 14-14: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1995 Microchip Technology Inc.
DS30390B-page 131
PIC16C7X
FIGURE 14-15: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 14-16: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
VDD
10k
MCLR
D
R
R1
40k
PIC16CXX
MCLR
PIC16CXX
C
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: Internal brown-out detection on the
PIC16C70/71A/72/73A/74A should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the char-
acteristics of the transistor.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin break-
down due to Electrostatic Discharge
FIGURE 14-17: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
(ESD) or Electrical Overstress (EOS).
VDD
VDD
R1
R2
Q1
MCLR
40k
PIC16CXX
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level
such that:
R1
= 0.7V
VDD •
R1 + R2
2: Internal brown-out detection on the
PIC16C70/71A/72/73A/74A should be
disabled when using this circuit.
3: Resistors should be adjusted for the
characteristics of the transistor.
DS30390B-page 132
1995 Microchip Technology Inc.
PIC16C7X
14.5
Interrupts
Applicable Devices
70 71 71A 72 73 73A 74 74A
The PIC16C7X family has up to 12 sources of interrupt:
Interrupt Sources
Applicable Devices
External interrupt RB0/INT
TMR0 overflow interrupt
PORTB change interrupts (pins RB7:RB4)
A/D Interrupt
70 71
70 71
70 71
70 71
70 71
70 71
70 71
70 71
70 71
70 71
70 71
70 71
71A
71A
71A
71A
71A
71A
71A
71A
71A
71A
71A
71A
72 73
72 73
72 73
72 73
72 73
72 73
72 73
72 73
72 73
72 73
72 73
72 73
73A
73A
73A
73A
73A
73A
73A
73A
73A
73A
73A
73A
74
74
74
74
74
74
74
74
74
74
74
74
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
74A
TMR1 overflow interrupt
TMR2 matches period interrupt
CCP1 interrupt
CCP2 interrupt
USART Receive
USART Transmit
Synchronous serial port interrupt
Parallel slave port read/write interrupt
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
22). The latency is the same for one or two cycle
instructions. Individual interrupt flag bits are set regard-
less of the status of their corresponding mask bit or the
GIE bit.
Note: Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
Note: For the PIC16C71/73/74 only,
If an interrupt occurs while the Global Inter-
rupt Enable (GIE) bit is being cleared, the
GIE bit may unintentionally be re-enabled
by the user’s Interrupt Service Routine (the
RETFIE instruction). The events that
would cause this to occur are:
1. An instruction clears the GIE bit while
an interrupt is acknowledged.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
2. The program branches to the Interrupt
vector and executes the Interrupt Ser-
vice Routine.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
3. The Interrupt Service Routine com-
pletes with the execution of the RET-
FIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
Perform the following to ensure that inter-
rupts are globally disabled:
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
LOOP BCF
INTCON, GIE ; Disable global
interrupt bit
BTFSC INTCON, GIE ; Global interrupt
disabled?
; NO, try again
;
;
GOTO LOOP
:
;
;
;
Yes, continue
with program
flow
1995 Microchip Technology Inc.
DS30390B-page 133
PIC16C7X
FIGURE 14-18: INTERRUPT LOGIC FOR PIC16C70/71/71A
Wakeup
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
ADIF
ADIE
GIE
FIGURE 14-19: INTERRUPT LOGIC FOR PIC16C72
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
T0IF
T0IE
INTF
INTE
TMR2IF
TMR2IE
RBIF
RBIE
ADIF
ADIE
PEIF
PEIE
GIE
CCP1IF
CCP1IE
SSPIF
SSPIE
FIGURE 14-20: INTERRUPT LOGIC FOR PIC16C73/73A
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
TMR2IF
TMR2IE
T0IF
T0IE
CCP1IF
CCP1IE
INTF
INTE
CCP2IF
CCP2IE
RBIF
RBIE
ADIF
ADIE
PEIF
PEIE
TXIF
TXIE
GIE
RCIF
RCIE
SSPIF
SSPIE
DS30390B-page 134
1995 Microchip Technology Inc.
PIC16C7X
FIGURE 14-21: INTERRUPT LOGIC FOR PIC16C74/74A
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
TMR2IF
TMR2IE
T0IF
T0IE
CCP1IF
CCP1IE
INTF
INTE
CCP2IF
CCP2IE
RBIF
RBIE
ADIF
ADIE
PEIF
PEIE
TXIF
TXIE
GIE
RCIF
RCIE
SSPIF
SSPIE
PSPIF
PSPIE
FIGURE 14-22: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC+1
PC+1
—
0005h
PC
Instruction
fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
1995 Microchip Technology Inc.
DS30390B-page 135
PIC16C7X
14.5.1 INT INTERRUPT
Note: For the PIC16C71/73/74 only,
if a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
External interrupt on RB0/INT pin is edge triggered:
either rising if bit INTEDG (OPTION<6>) is set, or fall-
ing, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 14.8 for details on SLEEP mode.
14.6
Context Saving During Interrupts
Applicable Devices
70 71 71A 72 73 73A 74 74A
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 14-1 and Example 14-2 store and restore the
STATUS and W registers. For PIC16C72/73/73A/74/
74A, the register, W_TEMP, must be defined in both
banks and must be defined at the same offset from the
bank base address (i.e., if W_TEMP is defined at 0x20
in bank 0, it must also be defined at 0xA0 in bank 1).
14.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 7.0)
For
PIC16C70/71/71A,
the
user
register,
STATUS_TEMP, must be defined in bank 0.
14.5.3 PORTB INTCON CHANGE
The example:
An input change on PORTB <7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Executes the ISR code.
d) Restores the STATUS register (and bank select
bit).
e) Restores the W register.
EXAMPLE 14-1: SAVING STATUS AND W REGISTERS IN RAM (PIC16C70/71/71A)
MOVWF
SWAPF
MOVWF
:
W_TEMP
STATUS,W
STATUS_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
EXAMPLE 14-2: SAVING STATUS AND W REGISTERS IN RAM (PIC16C72/73/73A/74/74A)
MOVWF
SWAPF
BCF
MOVWF
:
W_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Change to bank zero, regardless of current bank
;Save status to bank zero STATUS_TEMP register
STATUS,W
STATUS,RP0
STATUS_TEMP
:(ISR)
:
SWAPF
STATUS_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30390B-page 136
1995 Microchip Technology Inc.
PIC16C7X
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
14.7
Watchdog Timer (WDT)
Applicable Devices
70 71 71A 72 73 73A 74 74A
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction. Dur-
ing normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device
is in SLEEP mode, a WDT time-out causes the device
to wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The WDT can be permanently
disabled by clearing configuration bit WDTE
(Section 14.1).
The CLRWDTand SLEEPinstructions clear the WDT and
the postscaler, if assigned to the WDT, and prevent it
from timing out and generating a device RESET condi-
tion.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
14.7.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
14.7.1 WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
DD
ture, V and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
FIGURE 14-23: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 7-6)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
FIGURE 14-24: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
2007h
81h
Name
Bit 7
(1)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
WDTE
PS2
Bit 1
FOSC1
PS1
Bit 0
FOSC0
PS0
(1)
(1)
Config. bits
OPTION
CP1
CP0
BODEN
PWRTE
PSA
RBPU
INTEDG
T0CS T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 14-1, Figure 14-2, Figure 14-3, and Figure 14-4 for operation of these bits.
1995 Microchip Technology Inc.
DS30390B-page 137
PIC16C7X
power-up is cleared when SLEEPis invoked. The TO bit
is cleared if WDT time-out occurred (and caused wake-
up).
14.8
Power-down Mode (SLEEP)
Applicable Devices
70 71 71A 72 73 73A 74 74A
The following peripheral interrupts can wake the device
from SLEEP:
Power-down mode is entered by executing a SLEEP
instruction.
1. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
2. SSP (Start/Stop) bit detect interrupt.
3. SSP transmit or receive in slave mode (SPI/
2
I C).
4. CCP capture mode interrupt.
5. Parallel Slave Port read or write.
6. A/D conversion (when A/D clock source is RC).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, disable external clocks. Pull all I/O pins, that
are hi-impedance inputs, high or low externally to avoid
switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
7. Special event trigger (Timer1 in asynchronous
mode using an external clock).
8. USART TX or RX (synchronous slave mode).
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
The MCLR pin must be at a logic high level (VIHMC).
14.8.1 WAKE-UP FROM SLEEP
The device can wake up from SLEEP through one of
the following events:
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change, or some
Peripheral Interrupts.
Note: Interrupts that are capable of waking the
device from SLEEP will still set the individ-
ual flag bits regardless of the state of the
global enable bit, GIE.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
FIGURE 14-25: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
DS30390B-page 138
1995 Microchip Technology Inc.
PIC16C7X
14.9
Program Verification/Code Protection
Applicable Devices
14.11 In-Circuit Serial Programming
Applicable Devices
70 71 71A 72 73 73A 74 74A
70 71 71A 72 73 73A 74 74A
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Note: Microchip does not recommend code pro-
tecting windowed devices.
14.10 ID Locations
Applicable Devices
70 71 71A 72 73 73A 74 74A
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of ID
location are used.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A 6-
bit command is then supplied to the device. Depending
on the command, 14-bits of program data are then sup-
plied to or from the device, depending if the command
was a load or a read. For complete details of serial pro-
gramming, please refer to the PIC16C6X/7X Program-
ming Specifications (Literature #DS30228).
FIGURE 14-26: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16CXX
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
VDD
To Normal
Connections
1995 Microchip Technology Inc.
DS30390B-page 139
PIC16C7X
NOTES:
DS30390B-page 140
1995 Microchip Technology Inc.
PIC16C7X
The instruction set is highly orthogonal and is grouped
into three basic categories:
15.0 INSTRUCTION SET SUMMARY
Applicable Devices
• Byte-oriented operations
• Bit-oriented operations
70 71 71A 72 73 73A 74 74A
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 15-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 15-1
shows the opcode field descriptions.
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, 'f' represents a file reg-
ister designator and 'd' represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table 15-2 lists the instructions recognized by the
MPASM assembler.
Figure 15-1 shows the three general formats that the
instructions can have.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
All examples use the following format to represent a
hexadecimal number:
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
0xhh
where h signifies a hexadecimal digit.
Field
Description
FIGURE 15-1: GENERAL FORMAT FOR
INSTRUCTIONS
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
Byte-oriented file register operations
Bit address within an 8-bit file register
Literal field, constant data or label
13
8
7
6
0
0
OPCODE
d
f (FILE #)
Don't care location (= 0 or 1)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
OPCODE
f (FILE #)
label Label name
TOS Top of Stack
PC Program Counter
b = 3-bit bit address
f = 7-bit file register address
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
General
13
8
7
0
0
PD Power-down bit
OPCODE
k (literal)
dest Destination either the W register or the specified
register file location
k = 8-bit immediate value
[ ] Options
Contents
( )
→
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
Assigned to
Register bit field
In the set of
< >
k (literal)
User defined term (font is courier)
italics
1995 Microchip Technology Inc.
DS30390B-page 141
PIC16C7X
TABLE 15-2: PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
Move W to f
No Operation
-
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
0000 0110 0100
1kkk kkkk kkkk
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30390B-page 142
1995 Microchip Technology Inc.
PIC16C7X
15.1
Instruction Descriptions
ANDLW
And Literal with W
ADDLW
Add Literal and W
Syntax:
[ label ] ANDLW
k
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Operation:
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR, 1
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
1995 Microchip Technology Inc.
DS30390B-page 143
PIC16C7X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit 'b' in register 'f' is '0' then the next
instruction is skipped.
Bit 'b' in register 'f' is cleared.
Description:
1
1
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOP is
executed instead, making this a 2 cycle
instruction.
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
After Instruction
Words:
Cycles:
Example
1
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30390B-page 144
1995 Microchip Technology Inc.
PIC16C7X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
0 ≤ f ≤ 127
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit 'b' in register 'f' is '1' then the next
instruction is skipped.
If bit 'b' is '1', then the next instruction
fetched during the current instruction
execution, is discarded and a NOP is
executed instead, making this a 2 cycle
instruction.
The contents of register 'f' are cleared
and the Z bit is set.
Description:
Description:
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Words:
Cycles:
Example
1
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
1(2)
=
0x5A
HERE
FALSE
TRUE
BTFSC FLAG,1
=
=
0x00
1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRW
None
Syntax:
Operands:
Operation:
Operands:
Operation:
00h → (W)
1 → Z
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
0001
0xxx
xxxx
10
0kkk
kkkk
kkkk
W register is cleared. Zero bit (Z) is
set.
Description:
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two cycle instruction.
Description:
Words:
Cycles:
Example
1
1
CLRW
Words:
Cycles:
Example
1
2
Before Instruction
W
=
0x5A
After Instruction
HERE
CALL THERE
W
=
0x00
1
Before Instruction
Z
=
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
1995 Microchip Technology Inc.
DS30390B-page 145
PIC16C7X
CLRWDT
Syntax:
Clear Watchdog Timer
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT,
1
1
Before Instruction
CLRWDT
CNT
Z
=
=
0x01
0
Before Instruction
After Instruction
WDT counter
After Instruction
=
=
?
CNT
Z
=
=
0x00
1
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register 'f' are decre-
mented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register 'f' are comple-
mented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded. A
NOP is executed instead making it a two
cycle instruction.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Words:
Cycles:
Example
1
Before Instruction
1(2)
REG1
After Instruction
REG1
=
0x13
HERE
DECFSZ
GOTO
CNT, 1
LOOP
=
=
0x13
0xEC
CONTINUE •
W
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
=
=
DS30390B-page 146
1995 Microchip Technology Inc.
PIC16C7X
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
INCFSZ
Syntax:
Increment f, Skip if 0
Syntax:
[ label ] INCFSZ f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two cycle instruction.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOP is executed instead making it a
two cycle instruction.
Description:
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
GOTO THERE
1(2)
After Instruction
HERE
INCFSZ
GOTO
CNT,
LOOP
1
PC
=
Address THERE
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. k → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
11
1000
kkkk
kkkk
00
1010
dfff
ffff
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register 'f' are incre-
mented. If 'd' is 0 the result is placed
in the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
Before Instruction
INCF
CNT, 1
W
=
0x9A
Before Instruction
After Instruction
CNT
Z
=
=
0xFF
0
W
=
0xBF
1
Z
=
After Instruction
CNT
Z
=
=
0x00
1
1995 Microchip Technology Inc.
DS30390B-page 147
PIC16C7X
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
The contents of register f is moved to
a destination dependant upon the sta-
tus of d. If d = 0, destination is W reg-
ister. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Description:
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
1
Before Instruction
RESULT =
0x13
0x91
MOVF
FSR, 0
W
=
After Instruction
After Instruction
RESULT =
W
Z
0x13
0x93
1
W = value in FSR register
=
=
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Syntax:
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
11
00xx
kkkk
kkkk
00
0000
1fff
ffff
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Move data from W register to register
'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
MOVLW
0x5A
Before Instruction
OPTION =
After Instruction
0xFF
0x4F
W
=
0x5A
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
DS30390B-page 148
1995 Microchip Technology Inc.
PIC16C7X
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
Syntax:
Syntax:
[ label ] RETFIE
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by set-
ting Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Description:
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
k → (W);
TOS → PC
Status Affected: None
00
0000
0110
0010
Encoding:
Status Affected:
Encoding:
None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code com-
patibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Description:
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Description:
Words:
Cycles:
Example
1
2
Words:
Cycles:
Example
1
1
CALL TABLE
;W contains table
;offset value
•
;W now has table value
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
•
•
TABLE
ADDWF PC
;W = offset
;Begin table
;
RETLW k1
RETLW k2
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
1995 Microchip Technology Inc.
DS30390B-page 149
PIC16C7X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
None
Operation:
See description below
C
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Words:
Cycles:
Example
1
2
C
Register f
RETURN
After Interrupt
Words:
Cycles:
Example
1
1
PC
=
TOS
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ] SLEEP
None
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
0 → PD
00
1101
dfff
ffff
Status Affected:
Encoding:
TO, PD
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
Description:
C
Register f
The processor is put into SLEEP
mode with the oscillator stopped.
Words:
Cycles:
Example
1
1
See Section 14.8 for more details.
Words:
1
RLF
REG1,0
Cycles:
Example:
1
Before Instruction
SLEEP
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
DS30390B-page 150
1995 Microchip Technology Inc.
PIC16C7X
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ]
SUBLW k
[ label ]
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d
[0,1]
k - (W) → (W)
Operation:
(f) - (W) → (dest)
Status
C, DC, Z
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Subtract (2’s complement method) W reg-
ister from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
=
=
=
2
2
?
1; result is zero
C
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
C
=
=
=
0
2
After Instruction
1; result is zero
W
C
=
=
0xFF
0; result is nega-
Example 3:
Before Instruction
tive
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
1995 Microchip Technology Inc.
DS30390B-page 151
PIC16C7X
SWAPF
Syntax:
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
11
1010 kkkk kkkk
Status Affected:
Encoding:
None
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Description:
00
1110
dfff
ffff
The upper and lower nibbles of regis-
ter 'f' are exchanged. If 'd' is 0 the
result is placed in W register. If 'd' is 1
the result is placed in register 'f'.
Description:
Words:
1
1
Cycles:
Example:
Words:
Cycles:
Example
1
1
XORLW
0xAF
Before Instruction
SWAPF REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] TRIS
f
Operands:
Operation:
5 ≤ f ≤ 7
Operands:
d
[0,1]
(W) → TRIS register f;
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
00
Encoding:
0000 0110
0fff
Status Affected:
Encoding:
Z
The instruction is supported for code
compatibility with the PIC16C5X prod-
ucts. Since TRIS registers are read-
able and writable, the user can directly
address them.
Description:
00
0110
dfff
ffff
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd'
is 1 the result is stored back in register
'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
REG
1
XORWF
Before Instruction
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS30390B-page 152
1995 Microchip Technology Inc.
PIC16C7X
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and better) machine platform and Microsoft Win-
dows 3.x environment was chosen to best make
these features available to you, the end user.
16.0 DEVELOPMENT SUPPORT
16.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER Real-Time In-Circuit Emulator
• PRO MATE Universal Programmer
• PICSTART Low-Cost Prototype Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• MPASM Assembler
The PICMASTER Universal Emulator System consists
primarily of four major components:
• Host-Interface Card
• Emulator Control Pod
• Target-Specific Emulator Probe
• PC-Host Emulation Control Software
• MPSIM Software Simulator
• C Compiler (MP-C)
The Windows operating system allows the developer to
take full advantage of the many powerful features and
functions of the PICMASTER system.
• Fuzzy logic development system
(fuzzyTECH −MP)
PICMASTER emulation can operate in one window,
while a text editor is running in a second window.
16.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
PC-Host Emulation Control software takes full advan-
tage of Dynamic Data Exchange (DDE), a feature of
Windows. DDE allows data to be dynamically trans-
ferred between two or more Windows programs. With
this feature, data collected with PICMASTER can be
automatically transferred to a spreadsheet or database
program for further analysis.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC16C5X, PIC16CXX and
PIC17CXX families. PICMASTER is supplied with the
MPLAB Integrated Development Environment (IDE),
which allows editing, "make" and download, and
source debugging from a single environment. A
PICMASTER System configuration is shown in
Figure 16-1.
Under Windows, as many as four PICMASTER emula-
tors can be run simultaneously from the same PC mak-
ing development of multi-microcontroller systems
possible (e.g., a system containing a PIC16CXX pro-
cessor and a PIC17CXX processor).
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different proces-
sors. The universal architecture of the PICMASTER
allows expansion to support all new PIC16C5X,
PIC16CXX and PIC17CXX microcontrollers.
The PICMASTER probes specifications are shown in
Table 16-1.
FIGURE 16-1: PICMASTER SYSTEM CONFIGURATION
In-Line
5 VDC
Power Supply
(Optional)
90 - 250 VAC
Windows 3.x
Power Switch
Interchangeable
Emulator Probe
Power Connector
PC Bus
PC-Interface
PICMASTER Emulator Pod
Common Interface Card
PC Compatible Computer
Logic Probes
1995 Microchip Technology Inc.
DS30390B-page 153
PIC16C7X
TABLE 16-1: PICMASTER PROBE
SPECIFICATION (Cont.’d)
TABLE 16-1: PICMASTER PROBE
SPECIFICATION
PROBE
PROBE
PICMASTER
PICMASTER
PROBE
Devices
Devices
Maximum Operating
PROBE
Maximum Operating
Frequency
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
20 MHz
20 MHz
20 MHz
Voltage
Frequency
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
20 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
10 MHz
Voltage
(1)
(1)
PIC16C64A
PIC16CR64
PIC16C65
PIC16C65A
PIC16C620
PIC16C621
PIC16C622
PIC16C70
PIC16C71
PIC16C71A
PIC16C72
PIC16C73
PIC16C73A
PIC16C74
PIC16C74A
PIC16C83
PIC16C84
PIC17C42
PIC17C43
PIC17C44
PROBE-16E
PROBE-16E
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
PIC16C54
PROBE-16D
PROBE-16D
PROBE-16D
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
4.5V - 5.5V
PIC16C54A
PIC16CR54
PIC16CR54A
PIC16CR54B
PIC16C55
PROBE-16F
(1)
(1)
PROBE-16F
PROBE-16H
PROBE-16H
PROBE-16H
PROBE-16D
PROBE-16D
(1)
PROBE-16D
(1)
PIC16CR55
PIC16C56
PROBE-16D
PROBE-16D
(1)
PROBE-16B
PROBE-16B
(1)
PIC16CR56
PIC16C57
PROBE-16D
PROBE-16D
PROBE-16D
(1)
PROBE-16B
PROBE-16F
(1)
PIC16CR57A
PIC16CR57B
PIC16C58A
PIC16CR58A
PIC16CR58B
PIC16C61
(1)
PROBE-16F
PROBE-16D
PROBE-16D
PROBE-16D
(1)
PROBE-16F
PROBE-16F
(1)
(1)
PROBE-16F
PROBE-16C
PROBE-16C
PROBE-17B
PROBE-17B
PROBE-17B
PROBE-16D
PROBE-16G
PROBE-16E
PIC16C62
(1)
PIC16C62A
PIC16CR62
PIC16C63
PROBE-16E
PROBE-16E
PROBE-16F
(1)
(1)
Note 1: This PICMASTER probe can be used to
functionally emulate the device listed in the
previous column. Contact your Microchip sales
office for details.
PIC16C64
PROBE-16E
DS30390B-page 154
1995 Microchip Technology Inc.
PIC16C7X
16.3
PRO MATE: Universal Programmer
16.5
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PRO MATE Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
The PRO MATE has programmable VDD and VPP sup-
plies which allows it to verify programmed memory at
VDD min and VDD max for maximum reliability. It has an
LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In stand-
alone mode the PRO MATE can read, verify or program
PIC16C5X, PIC16CXX and PIC17CXX devices. It can
also set configuration and code-protect bits in this
mode.
the PICDEM-1 board, on
a
PRO MATE or
PICSTART-16B programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional pro-
totype area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
In PC-hosted mode, the PRO MATE connects to the PC
via one of the COM (RS-232) ports. PC based user-
interface software makes using the programmer simple
and efficient. The user interface is full-screen and
menu-based. Full screen display and editing of data,
easy selection of bit configuration and part type, easy
selection of VDD min, VDD max and VPP levels, load and
store to and from disk files (Intel hex format) are some
of the features of the software. Essential commands
such as read, verify, program and blank check can be
issued from the screen. Additionally, serial program-
ming support is possible where each part is pro-
grammed with a different serial number, sequential or
random.
16.6
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE pro-
grammer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
The PRO MATE has a modular “programming socket
module”. Different socket modules are required for dif-
ferent processor types and/or package types.
PRO MATE supports all PIC16C5X, PIC16CXX and
PIC17CXX processors.
16.4
PICSTART Low-Cost Development
System
The PICSTART programmer is an easy to use, very
low-cost prototype programmer. It connects to the PC
via one of the COM (RS-232) ports. A PC-based user
interface software makes using the programmer simple
and efficient. The user interface is full-screen and
menu-based. PICSTART is not recommended for pro-
duction programming.
2
usage of the I C bus and separate headers for connec-
tion to an LCD module and a keypad.
1995 Microchip Technology Inc.
DS30390B-page 155
PIC16C7X
16.7
MPLABTM Integrated Development
Environment Software.
16.8
Assembler (MPASM)
The MPASM CrossAssembler is a PC-hosted symbolic
assembler. It supports all microcontroller series includ-
ing the PIC16C5X, PIC16CXX and PIC17CXX families.
The MPLAB Software brings an ease of software devel-
opment previously unseen in the 8-bit microcontroller
market. MPLAB is a windows based application which
contains:
MPASM offers full featured Macro capabilities, condi-
tional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator (available soon)
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
MPASM allows full symbolic debugging from
the Microchip Universal Emulator System
(PICMASTER).
MPASM has the following features to assist in develop-
ing software for specific use applications.
• Extensive on-line help
MPLAB allows you to:
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Edit your source files (either assembly or "C")
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
The ability to use MPLAB with Microchip’s simulator
(available soon) allows a consistent platform and the
ability to easily switch from the low cost simulator to the
full featured emulator with minimal retraining due to
development tools.
• Data Directives are those that control the alloca-
tion of memory and provide a way to refer to data
items symbolically, i.e., by meaningful names.
• Control Directives control the MPASM listing dis-
play. They allow the specification of titles and sub-
titles, page ejects and other listing control. This
eases the readability of the printed output file.
• Conditional Directives permit sections of condi-
tionally assembled code. This is most useful
where additional functionality may wished to be
added depending on the product (less functional-
ity for the low end product, then for the high end
product). Also this is very helpful in the debugging
of a program.
• Macro Directives control the execution and data
allocation within macro body definitions. This
makes very simple the re-use of functions in a
program as well as between programs.
DS30390B-page 156
1995 Microchip Technology Inc.
PIC16C7X
16.9
Software Simulator (MPSIM)
16.11 Fuzzy Logic Development System
(fuzzyTECH-MP)
The MPSIM Software Simulator allows code develop-
ment in a PC host environment. It allows the user to
simulate the PIC16/17 series microcontrollers on an
instruction level. On any given instruction, the user may
examine or modify any of the data areas or provide
external stimulus to any of the pins. The input/output
radix can be set by the user and the execution can be
performed in; single step, execute until break, or in a
trace mode. MPSIM fully supports symbolic debugging
using MP-C and MPASM. The Software Simulator
offers the low cost flexibility to develop and debug code
outside of the laboratory environment making it an
excellent multi-project software development tool.
fuzzyTECH-MP fuzzy logic development tool is avail-
able in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for imple-
menting more complex systems.
Both versions include Microchip’s fuzzyLAB demon-
stration board for hands-on experience with fuzzy logic
systems implementation.
16.12 Development Systems
For convenience, the development tools are packaged
into comprehensive systems as listed in Table 16-2.
16.10 C Compiler (MP-C)
The MP-C Code Development System is a complete 'C'
compiler and integrated development environment for
Microchip’s PIC16/17 family of microcontrollers. The
compiler provides powerful integration capabilities and
ease of use not found with other compilers.
For easier source level debugging, the compiler pro-
vides symbol information that is compatible with the
PICMASTER Universal Emulator memory display
(PICMASTER emulator software versions 1.13 and
later).
The MP-C Code Development System is supplied
directly by Byte Craft Limited of Waterloo, Ontario,
Canada. If you have any questions, please contact
your regional Microchip FAE or Microchip technical
support personnel at (602) 786-7627.
TABLE 16-2: DEVELOPMENT SYSTEM PACKAGES
Item
Name
System Description
1.
PICMASTER System
PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler, Soft-
ware Simulator, Samples and your choice of Target Probe.
2.
3.
PICSTART System
PRO MATE System
PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator
and Samples.
PRO MATE Universal Programmer, full featured stand-alone or PC-hosted pro-
grammer, Assembler, Simulator
1995 Microchip Technology Inc.
DS30390B-page 157
PIC16C7X
NOTES:
DS30390B-page 158
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
17.0 ELECTRICAL CHARACTERISTICS FOR PIC16C70 AND PIC16C71A
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.6V to (VDD + 0.6V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA........................................................................................................................200 mA
Maximum current sourced by PORTA...................................................................................................................200 mA
Maximum current sunk by PORTB........................................................................................................................200 mA
Maximum current sourced by PORTB ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 159
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 17-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
DS30390B-page 160
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(5)
17.1
DC Characteristics:
PIC16C70-04 (Commercial, Industrial, Automotive )
(5)
PIC16C71A-04 (Commercial, Industrial, Automotive )
(5)
PIC16C70-10 (Commercial, Industrial, Automotive )
(5)
PIC16C71A-10 (Commercial, Industrial, Automotive )
(5)
PIC16C70-20 (Commercial, Industrial, Automotive )
(5)
PIC16C71A-20 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param.
No.
Characteristic
Sym
Min Typ† Max Units
Conditions
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
-
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
D003
D004
D010
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5*
VSS
-
-
V
Device in SLEEP mode
VDD start voltage to
ensure Power-on Reset
VPOR
-
0.05*
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure SVDD
Power-on Reset
-
V/ms See section on Power-on Reset for details
Supply Current (Note 2) IDD
2.7
5
mA XT, RC osc configuration (PIC16C70/71A-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
D015
-
-
13.5 30
mA HS osc configuration (PIC16C70/71A-20)
FOSC = 20 MHz, VDD = 5.5V
Brown-out Reset Cur-
rent (Note 6)
∆IBOR
300* 500 µA BOR enabled VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3)
IPD
-
-
-
-
10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C
1.5
1.5
21
24
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
1.5 TBD µA VDD = 4.0V, WDT disabled, -40°C to +125°C
D023
Brown-out Reset Cur-
rent (Note 6)
∆IBOR
-
300* 500 µA BOR enabled VDD = 5.0V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Automotive operating range is Advanced information for this device.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 161
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(5)
17.2
DC Characteristics:
PIC16LC70-04 (Commercial, Industrial, Automotive )
(5)
PIC16LC71A-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param
No.
Characteristic
Supply Voltage
Sym Min Typ† Max Units
Conditions
D001
D002
VDD
3.0
-
-
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
Device in SLEEP mode
RAM Data Retention VDR
Voltage (Note 1)
1.5*
D003
D004
D010
VDD start voltage to
ensure Power-on
Reset
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
VDD rise rate to
ensure Power-on
Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
Supply Current
(Note 2,5)
IDD
-
2.0
3.8
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
D015
-
-
22.5 48
300* 500
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
Brown-out Reset Cur- ∆IBOR
µA BOR enabled VDD = 3.0V
rent (Note 6)
D020
D021
D021A
D021B
Power-down Current IPD
(Note 3,5)
-
-
-
-
7.5
0.9
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, -40°C to +125°C
10
D023
Brown-out Reset Cur- ∆IBOR
-
300* 500
µA BOR enabled VDD = 3.0V
rent (Note 6)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Automotive operating range is Advanced information for this device.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30390B-page 162
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(4)
17.3
DC Characteristics:
PIC16C70-04 (Commercial, Industrial, Automotive )
(4)
PIC16C71A-04 (Commercial, Industrial, Automotive )
(4)
PIC16C70-10 (Commercial, Industrial, Automotive )
(4)
PIC16C71A-10 (Commercial, Industrial, Automotive )
(4)
PIC16C70-20 (Commercial, Industrial, Automotive )
(4)
PIC16C71A-20 (Commercial, Industrial, Automotive )
(4)
PIC16LC70-04 (Commercial, Industrial, Automotive )
(4)
PIC16LC71A-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 17.1
and Section 17.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, RA4/T0CKI,OSC1
(in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
2.0
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
0.8VDD
0.8VDD
0.8VDD
0.7VDD
0.9VDD
50
with Schmitt Trigger buffer
MCLR, RA4/T0CKI RB0/INT
D042A OSC1 (XT, HS and LP)
D043
D070
Note1
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
IPURB
IIL
250 400
µA VDD = 5V, VPIN = VSS
D060
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
Output Low Voltage
D080
D080A
D083
D083A
†
I/O ports
VOL
-
-
-
-
-
-
-
-
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKOUT (RC osc config)
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 163
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 17.1
and Section 17.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Output High Voltage
D090
I/O ports (Note 3)
VOH VDD - 0.7 -
VDD - 0.7 -
-
-
-
-
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D090A
D092
OSC2/CLKOUT (RC osc config)
VDD - 0.7 -
D092A
VDD - 0.7 -
Capacitive Loading Specs on Out-
put Pins
D100
OSC2 pin
COSC2
-
-
-
-
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
†
All I/O pins and OSC2 (in RC mode) CIO
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
pF
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
DS30390B-page 164
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
17.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 17-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 165
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
17.5
Timing Diagrams and Specifications
FIGURE 17-2: EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
3
3
4
2
CLKOUT
TABLE 17-2: CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ†
Max
Units Conditions
Fos External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
(Note 1)
MHz HS osc mode (PIC16C70/71A-04,)
MHz HS osc mode (PIC16C70/71A-20)
kHz LP osc mode
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
MHz HS osc mode (PIC16C70/71A-04)
MHz HS osc mode (PIC16C70/71A-10)
4
10
4
—
20
MHz HS osc mode (PIC16C70/71A-20)
kHz LP osc mode
5
—
—
—
—
—
—
—
—
—
—
200
—
1
Tosc External CLKIN Period
250
250
100
50
ns
ns
ns
ns
µs
ns
ns
ns
ns
XT and RC osc mode
(Note 1)
—
HS osc mode (PIC16C70/71A-04)
HS osc mode (PIC16C70/71A-10)
HS osc mode (PIC16C70/71A-20)
LP osc mode
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
100
—
RC osc mode
10,000
250
250
XT osc mode
HS osc mode (PIC16C70/71A-04)
HS osc mode (PIC16C70/71A-10)
50
5
—
—
—
—
—
—
—
—
—
250
—
ns
µs
ns
ns
µs
ns
ns
ns
ns
HS osc mode (PIC16C70/71A-20)
LP osc mode
2
3
TCY
Instruction Cycle Time (Note 1) 200
DC
—
TCY = 4/FOSC
TosL, External Clock in (OSC1) High
TosH or Low Time
50
2.5
10
—
XT oscillator
—
LP oscillator
—
HS oscillator
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
25
50
15
XT oscillator
—
LP oscillator
—
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC16C70/71A.
DS30390B-page 166
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 17-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 17-1 for load conditions.
TABLE 17-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C70/71A
PIC16LC70/71A
PIC16C70/71A
PIC16LC70/71A
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
20
20
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 167
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 17-1 for load conditions.
FIGURE 17-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 17-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
1
—
—
µs VDD = 5V, -40˚C to +125˚C
Twdt
Watchdog Timer Time-out Period
7*
18
33*
ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
—
28*
—
1024TOSC
—
132*
1.1
—
TOSC = OSC1 period
Tpwrt Power up Timer Period
72
—
ms VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR Low
µs
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs 3.8V ≤ VDD ≤ 4.2V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 168
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 17-6: TIMER0 CLOCK TIMINGS
RA4/T0CKI
41
40
42
TMR0
Note: Refer to Figure 17-1 for load conditions.
TABLE 17-5: TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20*
10*
Greater of:
ns N = prescale value
(1, 2, 4,..., 256)
20µs or TCY + 40*
N
48
Tcke2tmrI Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2Tosc
—
7Tosc
—
*
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 169
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 17-6: A/D CONVERTER CHARACTERISTICS:
(3)
PIC16C70-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C71A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C70-10 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C71A-10 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C70-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C71A-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
(3)
(3)
(3)
(3)
(3)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT Integral error
less than
±1 LSb
NDIF Differential error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VSS ≤ AIN ≤ VREF
NFS
Full scale error
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN Analog input voltage VSS - 0.3
V
ZAIN Recommended
impedance of analog
—
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: Automotive operating range is Advanced information for this device.
DS30390B-page 170
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 17-7: A/D CONVERTER CHARACTERISTICS:
PIC16LC70-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
(4)
(4)
PIC16LC71A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
less than
±1 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VSS ≤ AIN ≤ VREF
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage VSS - 0.3
V
Recommended
—
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
90
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
4: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 171
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 17-7: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 17-8: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
VREF ≥ 3.0V
130
TAD
TAD
A/D clock period
1.6
2.0
—
—
µs
µs VREF full range
130
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
µs PIC16LC70, VDD = 3.0V
µs PIC16C70
3.0
2.0
—
6.0
4.0
9.0
6.0
—
131
132
TCNV Conversion time
(not including S/H
time). Note 1
9.5TAD
—
TSMP Sampling time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
DS30390B-page 172
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C70
AND PIC16C71A
NOT AVAILABLE AT THIS TIME
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 173
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 174
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.0 ELECTRICAL CHARACTERISTICS FOR PIC16C71
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.6V to (VDD + 0.6V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power dissipation (Note 1)...........................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................150 mA
Maximum current into VDD pin ..............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................20 mA
Maximum current sunk by PORTA..........................................................................................................................80 mA
Maximum current sourced by PORTA.....................................................................................................................50 mA
Maximum current sunk by PORTB........................................................................................................................150 mA
Maximum current sourced by PORTB ..................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 19-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
OSC
PIC16C71-04
PIC16C71-20
PIC16LC71-04
VDD: 3.0V to 6.0V
JW Devices
VDD: 4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
IDD: 1.8 mA typ. at 5.5V
IPD: 1.0 µA typ. at 4V
Freq: 4 MHz max.
IDD: 1.4 mA typ. at 3.0V
IPD: 0.6 µA typ. at 3V
Freq: 4 MHz max.
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
RC
VDD: 4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 3.0V to 6.0V
VDD: 4.0V to 6.0V
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
IDD: 1.8 mA typ. at 5.5V
IPD: 1.0 µA typ. at 4V
Freq: 4 MHz max.
IDD: 1.4 mA typ. at 3.0V
IPD: 0.6 µA typ. at 3V
Freq: 4 MHz max.
IDD: 3.3 mA max. at 5.5V
IPD: 14 µA max. at 4V
Freq: 4 MHz max.
XT
HS
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V
IPD: 1.0 µA typ. at 4.5V
Freq: 4 MHz max.
IDD: 30 mA max. at 5.5V
IPD: 1.0 µA typ. at 4.5V
Freq: 20 MHz max.
IDD: 30 mA max. at 5.5V
IPD: 1.0 µA typ. at 4.5V
Freq: 20 MHz max.
Do not use in HS mode
VDD: 4.0V to 6.0V
IDD: 15 µA typ. at 32 kHz,
4.0V
VDD: 3.0V to 6.0V
IDD: 32 µA max. at 32 kHz,
3.0V
VDD: 3.0V to 6.0V
IDD: 32 µA max. at 32 kHz,
3.0V
LP
Do not use in LP mode
IPD: 0.6 µA typ. at 4.0V
Freq: 200 kHz max.
IPD: 9 µA max. at 3.0V
Freq: 200 kHz max.
IPD: 9 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom-
mended that the user select the device type that ensures the specifications required.
1995 Microchip Technology Inc.
DS30390B-page 175
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.1
DC Characteristics:
PIC16C71-04 (Commercial, Industrial)
PIC16C71-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
VDR
4.0
4.5
-
-
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002 RAM Data Retention
Voltage (Note 1)
-
1.5*
VSS
-
-
-
-
V
Device in SLEEP mode
D003 VDD start voltage to
guarantee Power-on Reset
VPO
R
-
V
See section on Power-on Reset for details
D004 VDD rise rate to guarantee SVD 0.05*
V/ms See section on Power-on Reset for details
Power-on Reset
D
D010 Supply Current (Note 2)
IDD
-
-
1.8 3.3 mA FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
13.5 30
mA HS osc configuration (PIC16C71-20)
FOSC = 20 MHz, VDD = 5.5V
D020 Power-down Current
D021 (Note 3)
D021A
IPD
-
-
-
7
1.0
1.0
28
14
16
µA VDD = 4.0V, WDT enabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30390B-page 176
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.2
DC Characteristics: PIC16LC71-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
D002
Supply Voltage
VDD
VDR
3.0
-
-
6.0
-
V
V
XT, RC, and LP osc configuration
Device in SLEEP mode
RAM Data Retention
Voltage (Note 1)
1.5*
D003
D004
VDD start voltage to
ensure Power-on Reset
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
D010
Supply Current (Note 2)
IDD
IPD
-
-
1.4
15
2.5
32
mA FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
Power-down Current
(Note 3)
-
-
-
5
0.6
0.6
20
9
12
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
1995 Microchip Technology Inc.
DS30390B-page 177
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.3
DC Characteristics:
PIC16C71-04 (Commercial, Industrial)
PIC16C71-20 (Commercial, Industrial)
PIC16LC71-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 19.1
and Section 19.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, RA4/T0CKI,OSC1
(in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports (Note 4)
with TTL buffer
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
-
-
D040
D040A
D041
D042
D042A
D043
D070
0.36VDD
0.45VDD
0.85VDD
0.85VDD
0.7VDD
0.9VDD
50
VDD
VDD
VDD
VDD
VDD
VDD
V
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
with Schmitt Trigger buffer
MCLR RA4/T0CKI
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
V
V
V
Note1
IPURB
IIL
250 †400
µA VDD = 5V, VPIN = VSS
D060
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
Output Low Voltage
D080
D083
I/O ports
VOL
-
-
-
-
0.6
0.6
V
V
IOL = 8.5mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Output High Voltage
D090
D092
†
I/O ports (Note 3)
VOH VDD - 0.7 -
VDD - 0.7 -
-
-
V
V
IOH = -3.0mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the
PIC16C71 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input
buffer.
DS30390B-page 178
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 19.1
and Section 19.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Capacitive Loading Specs on Out-
put Pins
D100
OSC2 pin
COSC2
15
50
pF In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
All I/O pins and OSC2 (in RC mode) CIO
pF
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt trigger input. It is not recommended that the
PIC16C71 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: PIC16C71 Rev. "Ax" INT pin has a TTL input buffer. PIC16C71 Rev. "Bx" INT pin has a Schmitt Trigger input
buffer.
1995 Microchip Technology Inc.
DS30390B-page 179
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 19-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
15 pF for OSC2 output
DS30390B-page 180
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
19.5
Timing Diagrams and Specifications
FIGURE 19-2: EXTERNAL CLOCK TIMING
Q1
1
Q2
Q3
Q4
Q4
Q1
OSC1
3
3
4
4
2
CLKOUT
TABLE 19-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
Fos External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (PIC16C71-04)
MHz HS osc mode (PIC16C71-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
MHz HS osc mode (PIC16C71-04)
MHz HS osc mode (PIC16C71-20)
1
20
1
Tosc External CLKIN Period
250
250
50
—
ns
ns
ns
µs
ns
ns
ns
ns
µs
µs
ns
µs
ns
ns
ns
ns
XT and RC osc mode
HS osc mode (PIC16C71-04)
HS osc mode (PIC16C71-20)
LP osc mode
(Note 1)
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
50
—
RC osc mode
10,000
1,000
1,000
—
XT osc mode
HS osc mode (PIC16C71-04)
HS osc mode (PIC16C71-20)
LP osc mode
5
2
3
TCY
Instruction Cycle Time (Note 1)
1.0
50
DC
—
Tcy = 4/Fosc
TosL, Clock in (OSC1) High or Low Time
TosH
XT oscillator
2.5
10
—
LP oscillator
—
HS oscillator
4
TosR, Clock in (OSC1) Rise or Fall Time
TosF
25
—
XT oscillator
50
—
LP oscillator
15
—
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected
(has no loading) for the PIC16C71.
1995 Microchip Technology Inc.
DS30390B-page 181
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 19-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C71
PIC16LC71
PIC16C71
PIC16LC71
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
20
20
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30390B-page 182
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
200
7*
—
—
ns
VDD = 5V, -40˚C to +85˚C
VDD = 5V, -40˚C to +85˚C
Twdt
Watchdog Timer Time-out Period
18
33*
ms
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
1024 TOSC
72
TOSC = OSC1 period
Tpwrt Power-up Timer Period
I/O High Impedance from MCLR
Low
28*
132*
100
ms
ns
VDD = 5V, -40˚C to +85˚C
TIOZ
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
1995 Microchip Technology Inc.
DS30390B-page 183
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 19-5: TIMER0 CLOCK TIMINGS
RA4/T0CKI
41
40
42
TMR0
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-5: TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
0.5TCY + 20*
10*
Greater of:
ns N = prescale value
(2, 4,..., 256)
20µs or TCY + 40*
N
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 184
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 19-6: A/D CONVERTER CHARACTERISTICS:
PIC16C71-04 (COMMERCIAL, INDUSTRIAL)
PIC16C71-20 (COMMERCIAL, INDUSTRIAL)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR Resolution
—
—
—
—
8 bits
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT Integral error
less than
±1 LSb
NDIF Differential error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VSS ≤ AIN ≤ VREF
NFS
Full scale error
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
VDD + 0.3
VREF
—
V
VREF Reference voltage
3.0V
—
—
—
VAIN Analog input voltage VSS - 0.3
V
ZAIN Recommended
impedance of analog
—
10.0
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
40
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
1995 Microchip Technology Inc.
DS30390B-page 185
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 19-7: A/D CONVERTER CHARACTERISTICS:
PIC16LC71-04 (COMMERCIAL, INDUSTRIAL)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8 bits
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
less than
±2 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±2 LSb
—
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VSS ≤ AIN ≤ VREF
less than
±2 LSb
NOFF Offset error
less than
±2 LSb
—
Monotonicity
—
guaranteed
—
VDD + 0.3
VREF
—
V
VREF Reference voltage
3.0V
—
—
—
VAIN
ZAIN
Analog input voltage VSS - 0.3
V
Recommended
—
10.0
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
90
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
DS30390B-page 186
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 19-6: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
Q4
130
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 19-8: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
130
130
TAD
TAD
A/D clock period
2.0
—
µs
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11(RC oscillator
source)
3.0
2.0
—
6.0
4.0
9.0
6.0
—
µs PIC16LC71, VDD = 3.0V
µs PIC16C71
131
132
TCNV Conversion time
(not including S/H
time) (Note 1)
10TAD
—
TSMP Sampling time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
1995 Microchip Technology Inc.
DS30390B-page 187
PIC16C7X
NOTES:
DS30390B-page 188
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-2: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
20.0 DC AND AC
CHARACTERISTICS GRAPHS
5.0
AND TABLES FOR PIC16C71
R = 4.7k
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed. In
some graphs or tables the data presented are out-
side specified operating range (e.g. outside speci-
fied VDD range). This is for information only and
devices are guaranteed to operate properly only
within the specified range.
4.5
4.0
3.5
3.0
The data presented in this section is a statistical sum-
mary of data collected on units from different lots over
a period of time. 'Typical' represents the mean of the
distribution while 'max' or 'min' represents (mean + 3σ)
and (mean - 3σ) respectively where σ is standard devi-
ation.
R = 10k
2.5
2.0
1.5
FIGURE 20-1: TYPICAL RC OSCILLATOR
FREQUENCY VS.
Cext = 20 pF, T = 25°C
1.0
TEMPERATURE
R = 100k
Fosc
0.5
Fosc (25°C)
Frequency Normalized to 25°C
1.050
0.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1.025
1.000
Rext = 10k
Cext = 100 pF
VDD (Volts)
FIGURE 20-3: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
VDD = 5.5V
0.975
0.950
2.0
VDD = 3.5V
0.925
0.900
0.875
0.850
R = 3.3k
1.8
1.6
1.4
R = 4.7k
0
10
20
30
40
50
60
70
1.2
1.0
0.8
T(°C)
R = 10k
0.6
Cext = 100 pF, T = 25°C
0.4
0.2
0.0
R = 100k
5.5
3.0
3.5
4.0
4.5
5.0
6.0
VDD (Volts)
1995 Microchip Technology Inc.
DS30390B-page 189
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-4: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
TABLE 20-1: RC OSCILLATOR
FREQUENCIES
8.0
Average
R = 3.3k
Cext
20 pf
Rext
4.7k
10k
100k
FOSC @ 5V, 25°C
7.0
4.52 MHz
2.47 MHz
±17.35%
±10.10%
R = 4.7k
6.0
5.0
290.86 kHz ±11.90%
100 pf
300 pf
3.3k
4.7k
10k
1.92 MHz
1.49 MHz
±9.43%
±9.83%
788.77 kHz ±10.92%
88.11 kHz ±16.03%
100k
3.3k
4.7k
10k
726.89 kHz ±10.97%
573.95 kHz ±10.14%
307.31 kHz ±10.43%
4.0
3.0
2.0
1.0
R = 10k
100k
33.82 kHz
±11.24%
The percentage variation indicated here is part to part
variation due to normal process distribution. The varia-
tion indicated is ±3 standard deviation from average
value for VDD = 5V.
Cext = 300 pF, T = 25°C
R = 100k
5.5
FIGURE 20-6: TYPICAL IPD VS. VDD
WATCHDOGTIMER ENABLED
25°C
0.0
3.0
3.5
4.0
4.5
5.0
6.0
VDD (Volts)
14
FIGURE 20-5: TYPICAL IPD VS. VDD
WATCHDOG TIMER
DISABLED 25°C
12
10
0.6
0.5
0.4
0.3
0.2
8
6
4
2
0
0.1
0.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
3.0
3.5
4.0
4.5
5.0
5.5 6.0
VDD (Volts)
DS30390B-page 190
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-7: MAXIMUM IPD VS. VDD
WATCHDOG DISABLED
FIGURE 20-8: MAXIMUM IPD VS. VDD
WATCHDOG ENABLED
45
25
-55°C
40
35
30
25
20
-40°C
125°C
20
15
125°C
0°C
15
10
5
70°C
85°C
10
5
85°C
70°C
0
3.0 3.5
4.0
4.5
5.0
5.5
6.0
0°C
-40°C
-55°C
VDD (Volts)
IPD, with Watchdog Timer enabled, has two components:
The leakage current which increases with higher tempera-
ture and the operating current of the Watchdog Timer logic
which increases with lower temperature. At -40°C, the latter
dominates explaining the apparently anomalous behavior.
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 20-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS VS. VDD
2.00
1.80
Max (-40˚C to 85˚C)
1.60
25˚C, TYP
1.40
1.20
Min (-40˚C to 85˚C)
1.00
0.80
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
1995 Microchip Technology Inc.
DS30390B-page 191
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-10: VIH, VIL OF MCLR,T0CKI AND OSC1 (IN RC MODE) VS. VDD
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
VIH, Max (-40°C to 85°C)
VIH, Typ (25°C)
VIH, Min (-40°C to 85°C)
VIL, Max (-40°C to 85°C)
VIL, Typ (25°C)
VIL, Min (-40°C to 85°C)
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
Note: These input pins have a Schmitt Trigger input buffer.
FIGURE 20-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
VS. VDD
Min (-40°C to 85°C)
3.60
TYP (25°C)
3.40
3.20
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
Max (-40°C to 85°C)
Min (-40°C to 85°C)
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
DS30390B-page 192
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-12: TYPICAL IDD VS. FREQ (EXT CLOCK, 25°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
100
10
1
100,000,000
1,000,000
10,000
10,000,000
100,000
Frequency (Hz)
FIGURE 20-13: MAXIMUM, IDD VS. FREQ (EXT CLOCK, -40° TO +85°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
100
10
100,000,000
1,000,000
Frequency (Hz)
10,000
10,000,000
100,000
1995 Microchip Technology Inc.
DS30390B-page 193
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-14: MAXIMUM IDD VS. FREQ WITH A/D OFF (EXT CLOCK, -55° TO +125°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
100
10
100,000,000
10,000
100,000
1,000,000
10,000,000
Frequency (Hz)
FIGURE 20-15: WDT TIMER TIME-OUT
PERIOD VS. VDD
FIGURE 20-16: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR VS. VDD
9000
8000
50
45
7000
40
Max, -40°C
6000
35
Max, 85°C
5000
Max, 70°C
30
4000
Typ, 25°C
25
20
3000
Min, 85°C
2000
Typ, 25°C
Min, 0°C
1000
0
15
10
5
2
3
4
5
6
7
Min, -40°C
VDD (Volts)
2
3
4
5
6
7
VDD (Volts)
DS30390B-page 194
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-17: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR VS. VDD
FIGURE 20-19: IOH VS. VOH, VDD = 3V
0
225
200
-5
Max, -40°C
Min, 85°C
175
150
-10
Typ, 25°C
125
Typ, 25°C
100
75
Min, 85°C
-15
Max, -40°C
50
-20
25
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-25
VDD (Volts)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VOH (Volts)
FIGURE 20-20: IOH VS. VOH, VDD = 5V
FIGURE 20-18: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR VS. VDD
0
-5
2500
Max, -40°C
-10
-15
2000
Typ, 25°C
-20
Min @ 85°C
1500
-25
Typ @ 25°C
-30
1000
-35
-40
Max @ -40°C
Min, 85°C
500
-45
-50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0
2
3
4
5
6
7
VDD (Volts)
1995 Microchip Technology Inc.
DS30390B-page 195
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 20-21: IOL VS. VOL, VDD = 3V
TABLE 20-2: INPUT CAPACITANCE*
35
Pin Name
Typical Capacitance (pF)
18L PDIP
5.0
18L SOIC
4.3
Max @ -40°C
RA port
30
RB port
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
25
OSC1/CLKN
OSC2/CLKOUT
TMR0
Typ @ 25°C
4.3
3.5
20
3.2
2.8
*All capacitance values are typical at 25°C. A part-to-
part variation of ±25% (three standard deviations)
should be taken into account.
15
Min @ +85°C
10
5
0
0.0
1.0
VOL (Volts)
0.5
1.5
2.0
2.5
3.0
FIGURE 20-22: IOL VS. VOL, VDD = 5V
90
80
Max @ -40°C
70
60
Typ @ 25°C
50
40
Min @ +85°C
30
20
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (Volts)
DS30390B-page 196
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
21.0 ELECTRICAL CHARACTERISTICS FOR PIC16C72
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.6V to (VDD + 0.6V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA
Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA
Maximum current sunk by PORTC .......................................................................................................................200 mA
Maximum current sourced by PORTC ..................................................................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 197
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 21-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
DS30390B-page 198
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(6)
21.1
DC Characteristics:
PIC16C72-04 (Commercial, Industrial, Automotive )
(6)
PIC16C72-10 (Commercial, Industrial, Automotive )
(6)
PIC16C72-20 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param
No.
Characteristic
Sym
VDD
Min Typ† Max Units
Conditions
D001
D001A
Supply Voltage
4.0
4.5
-
-
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002
D003
D004
D010
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5*
VSS
-
-
V
Device in SLEEP mode
VDD start voltage to
ensure Power-on Reset
VPOR
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
-
V/ms See section on Power-on Reset for details
Supply Current
(Note 2,5)
IDD
-
2.7
5
mA XT, RC osc configuration (PIC16C72-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
D015
-
-
13.5 30
mA HS osc configuration (PIC16C72-20)
FOSC = 20 MHz, VDD = 5.5V
Brown-out Reset Current ∆IBOR
300* 500 µA BOR enabled VDD = 5.0V
(Note 7)
D020
D021
D021A
D021B
Power-down Current
(Note 3,5)
IPD
-
-
-
-
10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C
1.5
1.5
21
24
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
1.5 TBD µA VDD = 4.0V, WDT disabled, -40°C to +125°C
D023
Brown-out Reset Current ∆IBOR
-
300* 500 µA BOR enabled VDD = 5.0V
(Note 7)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: Automotive operating range is Advanced information for this device.
7: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 199
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(6)
21.2
DC Characteristics:
PIC16LC72-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
D002
Supply Voltage
VDD
VDR
3.0
-
-
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
Device in SLEEP mode
RAM Data Retention
Voltage (Note 1)
1.5*
D003
D004
D010
VDD start voltage to
ensure Power-on Reset
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure SVDD 0.05*
Power-on Reset
V/ms See section on Power-on Reset for details
Supply Current
(Note 2,5)
IDD
-
2.0
3.8
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
D015
-
-
22.5 48
300* 500
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
Brown-out Reset Cur-
rent (Note 7)
∆IBOR
µA BOR enabled VDD = 3.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3,5)
IPD
-
-
-
-
7.5
0.9
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, -40°C to +125°C
10
D023
Brown-out Reset Cur-
rent (Note 7)
∆IBOR
-
300* 500
µA BOR enabled VDD = 3.0V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: Automotive operating range is Advanced information for this device.
7: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30390B-page 200
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(4)
21.3
DC Characteristics:
PIC16C72-04 (Commercial, Industrial, Automotive )
(4)
PIC16C72-10 (Commercial, Industrial, Automotive )
(4)
PIC16C72-20 (Commercial, Industrial, Automotive )
(4)
PIC16LC72-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 21.1
and Section 21.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, RA4/T0CKI,OSC1 (in RC
mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
2.0
VDD
VDD
VDD
VDD
V
V
V
V
4.5 ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
0.8VDD
0.8VDD
0.8VDD
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, RC7:RC4, RB0/
INT
D042A
D043
D070
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
0.7VDD
0.9VDD
50
-
-
VDD
VDD
V
V
Note1
IPURB
IIL
250 †400
µA VDD = 5V, VPIN = VSS
D060
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-
impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
Output Low Voltage
D080
D080A
D083
D083A
†
I/O ports
VOL
-
-
-
-
-
-
-
-
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
OSC2/CLKOUT (RC osc config)
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 201
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 21.1
and Section 21.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Output High Voltage
D090
I/O ports (Note 3)
VOH VDD - 0.7 -
VDD - 0.7 -
-
-
-
-
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D090A
D092
OSC2/CLKOUT (RC osc config)
VDD - 0.7 -
D092A
VDD - 0.7 -
Capacitive Loading Specs on Out-
put Pins
D100
OSC2 pin
COSC2
-
-
15
pF In XT, HS and LP modes
when external clock is used to
drive OSC1.
D101
D102
All I/O pins and OSC2 (in RC mode) CIO
-
-
-
-
50
400
pF
pF
2
CB
SCL, SDA in I C mode
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
DS30390B-page 202
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
21.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 21-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 203
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
21.5
Timing Diagrams and Specifications
FIGURE 21-2: EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
3
3
4
2
CLKOUT
TABLE 21-2: CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
Fos External CLKIN Frequency
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
4
4
MHz XT and RC osc mode
MHz HS osc mode (PIC16C72-04)
MHz HS osc mode (PIC16C72-20)
kHz LP osc mode
(Note 1)
20
200
4
Oscillator Frequency
(Note 1)
MHz RC osc mode
4
MHz XT osc mode
4
MHz HS osc mode (PIC16C72-04)
MHz HS osc mode (PIC16C72-10)
4
10
4
—
20
MHz HS osc mode (PIC16C72-20)
kHz LP osc mode
5
—
—
—
—
—
—
—
—
—
—
200
—
1
Tosc External CLKIN Period
250
250
100
50
ns
ns
ns
ns
µs
ns
ns
ns
ns
XT and RC osc mode
HS osc mode (PIC16C72-04)
HS osc mode (PIC16C72-10)
HS osc mode (PIC16C72-20)
LP osc mode
(Note 1)
—
—
—
5
—
Oscillator Period
(Note 1)
250
250
250
100
—
RC osc mode
10,000
250
250
XT osc mode
HS osc mode (PIC16C72-04)
HS osc mode (PIC16C72-10)
50
5
—
—
—
—
—
—
—
—
—
250
—
ns
µs
ns
ns
µs
ns
ns
ns
ns
HS osc mode (PIC16C72-20)
LP osc mode
2
3
TCY
Instruction Cycle Time (Note 1)
200
50
2.5
10
—
DC
—
TCY = 4/FOSC
XT oscillator
TosL, External Clock in (OSC1) High or
TosH Low Time
—
LP oscillator
—
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
25
50
15
XT oscillator
—
LP oscillator
—
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30390B-page 204
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C72
PIC16LC72
PIC16C72
PIC16LC72
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
20
20
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 205
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 21-1 for load conditions.
FIGURE 21-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
1
—
—
µs VDD = 5V, -40˚C to +125˚C
Twdt
Watchdog Timer Time-out Period
7*
18
33*
ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
1024TOSC
72
TOSC = OSC1 period
ms VDD = 5V, -40˚C to +125˚C
µs
Tpwrt Power-up Timer Period
28*
132*
1.1
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs 3.8V ≤ VDD ≤ 4.2V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 206
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-6: TIMER0 AND TIMER1 CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-5: TIMER0 AND TIMER1 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H
T0CKI High Pulse
Width
0.5TCY + 20*
—
—
ns
No Prescaler
With Prescaler
10*
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse No Prescaler
Width
With Prescaler
T0CKI Period
Greater of:
ns N = prescale value
(1, 2, 4, ..., 256)
20µs or TCY + 40*
N
45
46
47
Tt1H
Tt1L
Tt1P
T1CKI High Time Synchronous, no prescaler
Synchronous, PIC16C72
0.5Tcy + 20
10*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
with prescaler
PIC16LC72
20*
Asynchronous
2Tcy
ns
ns
ns
T1CKI Low Time
Synchronous, no prescaler
Synchronous, PIC16C72
0.5Tcy + 20
10*
with prescaler
PIC16LC72
20*
Asynchronous
2Tcy
ns
T1CKI input period Synchronous
Greater of:
20µs or TCY + 40*
ns N = prescale value
(1, 2, 4, 8)
N
Asynchronous
Greater of:
20µs or 4Tcy
—
—
—
—
ns
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting the T1OSCEN bit)
DC
200 kHz
7Tosc
48
Tcke2tmrI Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2Tosc
—
*
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 207
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Param Sym Characteristic
No.
Min
Typ† Max Units Conditions
50
TccL CCP1 input low time
No Prescaler
0.5TCY + 20*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
With Prescaler PIC16C72
PIC16LC72
10*
20*
51
52
TccH
TccP
No Prescaler
0.5TCY + 20*
10*
CCP1 input high time
CCP1 input period
With Prescaler PIC16C72
PIC16LC72
20*
3TCY + 40*
N
ns N = prescale
value (1,4 or 16)
53
54
TccR CCP1 output rise time
TccF CCP1 output fall time
—
—
10
10
25
25
ns
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 208
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-8: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 21-1 for load conditions
TABLE 21-7: SPI MODE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71
72
73
TscH
TscL
SCK input high time (slave mode)
SCK input low time (slave mode)
TCY + 20
TCY + 20
TCY
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
0.5TCY
—
—
ns
75
76
77
78
79
80
TdoR
SDO data output rise time
—
—
10
—
—
—
10
10
—
10
10
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TdoF
SDO data output fall time
TssH2doZ
TscR
SS↓ to SDO output hi-impedance
SCK output rise time (master mode)
SCK output fall time (master mode)
TscF
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 209
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 21-9: I C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 21-1 for load conditions
2
TABLE 21-8: I C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90
91
92
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated START
condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
DS30390B-page 210
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 21-10: I C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 21-1 for load conditions
2
TABLE 21-9: I C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
4.0
0.6
—
—
µs
µs
PIC16C72 must operate at a
minimum of 1.5 MHz
PIC16C72 must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC16C72 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC16C72 must operate at a
minimum of 10 MHz
SSP Module
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 211
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 21-10: SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16C72
—
—
—
—
—
—
—
—
—
—
—
—
50
100
25
ns
ns
ns
ns
ns
ns
PIC16LC72
121
122
Tckrf
Tdtrf
Clock out rise time and fall time PIC16C72
(Master Mode)
PIC16LC72
50
Data out rise time and fall time
PIC16C72
25
PIC16LC72
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TABLE 21-11: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckl
TckL2dtl
SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time)
15
15
—
—
—
—
ns
ns
126
Data hold after CK ↓ (DT hold time)
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 212
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 21-12: A/D CONVERTER CHARACTERISTICS:
(3)
PIC16C72-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C72-10 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C72-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
(3)
(3)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT Integral error
less than
±1 LSb
NDIF Differential error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VSS ≤ AIN ≤ VREF
NFS
Full scale error
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN Analog input voltage VSS - 0.3
V
ZAIN Recommended
impedance of analog
—
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 213
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 21-13: A/D CONVERTER CHARACTERISTICS:
(4)
PIC16LC72-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
less than
±1 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VSS ≤ AIN ≤ VREF
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage VSS - 0.3
V
Recommended
—
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
90
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. Vin must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
4: Automotive operating range is Advanced information for this device.
DS30390B-page 214
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 21-11: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
Q4
130
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 21-14: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
VREF ≥ 3.0V
130
TAD
TAD
A/D clock period
1.6
2.0
—
—
µs
µs VREF full range
130
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
µs PIC16LC72, VDD = 3.0V
µs PIC16C72
3.0
2.0
—
6.0
4.0
9.0
6.0
—
131
132
TCNV Conversion time
(not including S/H
time) (Note 1)
9.5TAD
—
TSMP Sampling time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 215
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 216
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
22.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C72
NOT AVAILABLE AT THIS TIME
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 217
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 218
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73/74
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.6V to (VDD + 0.6V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C73.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 219
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 23-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
DS30390B-page 220
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.1
DC Characteristics:
PIC16C73-04 (Commercial, Industrial)
PIC16C74-04 (Commercial, Industrial)
PIC16C73-10 (Commercial, Industrial)
PIC16C74-10 (Commercial, Industrial)
PIC16C73-20 (Commercial, Industrial)
PIC16C74-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param
No.
Characteristic
Sym
VDD
Min Typ† Max Units
Conditions
D001 Supply Voltage
D001A
4.0
4.5
-
-
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002 RAM Data Retention
Voltage (Note 1)
VDR
-
1.5*
VSS
-
-
V
Device in SLEEP mode
D003
VDD start voltage to
VPOR
-
-
V
See section on Power-on Reset for details
ensure Power-on Reset
D004
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
-
V/ms See section on Power-on Reset for details
D010 Supply Current (Note 2,5) IDD
-
-
2.7
5
mA XT, RC osc configuration (PIC16C74-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
13.5 30
10.5 42
1.5
1.5
mA HS osc configuration (PIC16C74-20)
FOSC = 20 MHz, VDD = 5.5V
D020 Power-down Current
D021 (Note 3,5)
D021A
IPD
-
-
-
µA VDD = 4.0V, WDT enabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
21
24
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 221
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.2
DC Characteristics:
PIC16LC73-04 (Commercial, Industrial)
PIC16LC74-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40˚C
0˚C
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
D002
Supply Voltage
VDD
VDR
3.0
-
-
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
Device in SLEEP mode
RAM Data Retention
Voltage (Note 1)
1.5*
D003
D004
D010
VDD start voltage to
ensure Power-on Reset
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
Supply Current (Note 2,5) IDD
-
-
2.0
3.8
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
22.5 48
7.5 30
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D020
D021
D021A
Power-down Current
(Note 3,5)
IPD
-
-
-
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
0.9 13.5 µA VDD = 3.0V, WDT disabled, 0°C to +70°C
0.9 18 µA VDD = 3.0V, WDT disabled, -40°C to +85°C
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
DS30390B-page 222
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.3
DC Characteristics:
PIC16C73-04 (Commercial, Industrial)
PIC16C74-04 (Commercial, Industrial)
PIC16C73-10 (Commercial, Industrial)
PIC16C74-10 (Commercial, Industrial)
PIC16C73-20 (Commercial, Industrial)
PIC16C74-20 (Commercial, Industrial)
PIC16LC73-04 (Commercial, Industrial)
PIC16LC74-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 23.1 and
Section 23.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, RA4/T0CKI,OSC1
(in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
2.0
VDD
VDD
VDD
VDD
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
0.8VDD
0.8VDD
0.8VDD
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, RC7:RC4,
RD7:RD4, RB0/INT
D042A RE2:RE0, OSC1 (XT, HS and LP)
0.7VDD
0.9VDD
50
-
-
VDD
VDD
V
V
Note1
D043
D070
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
IPURB
IIL
250 400
µA VDD = 5V, VPIN = VSS
D060
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
Output Low Voltage
D080
D083
I/O ports
VOL
-
-
-
-
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 223
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C ≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Section 23.1 and
Section 23.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Output High Voltage
D090
D092
I/O ports (Note 3)
VOH VDD - 0.7 -
VDD - 0.7 -
-
-
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
OSC2/CLKOUT (RC osc config)
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
-
-
15
pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102
All I/O pins and OSC2 (in RC
CIO
CB
-
-
-
-
50
400
pF
pF
2
mode) SCL, SDA in I C mode
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS30390B-page 224
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 23-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 100 pF for PORTD and PORTE outputs when used as system bus
50 pF for all pins except OSC2, but including PORTD and PORTE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 225
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
23.5
Timing Diagrams and Specifications
FIGURE 23-2: EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
3
3
4
2
CLKOUT
TABLE 23-2: CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
Fos External CLKIN Frequency
DC
DC
—
—
4
4
MHz XT and RC osc mode
(Note 1)
MHz HS osc mode (PIC16C73-04,
PIC16C74-04)
DC
—
20
MHz HS osc mode (PIC16C73-20,
PIC16C74-20)
DC
DC
0.1
4
—
—
—
—
200
4
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
Oscillator Frequency
(Note 1)
4
4
MHz HS osc mode (PIC16C73-04,
PIC16C74-04)
4
4
—
—
10
20
MHz HS osc mode (PIC16C73-10,
PIC16C74-10)
MHz HS osc mode (PIC16C73-20,
PIC16C74-20)
5
—
—
—
200
—
kHz LP osc mode
1
Tosc External CLKIN Period
250
250
ns
ns
XT and RC osc mode
(Note 1)
—
HS osc mode (PIC16C73-04,
PIC16C74-04)
100
50
—
—
—
—
ns
ns
HS osc mode (PIC16C73-10,
PIC16C74-10)
HS osc mode (PIC16C73-20,
PIC16C74-20)
5
—
—
—
—
—
—
µs
ns
ns
ns
LP osc mode
RC osc mode
XT osc mode
Oscillator Period
(Note 1)
250
250
250
10,000
250
HS osc mode (PIC16C73-04,
PIC16C74-04)
100
50
—
—
250
250
ns
ns
HS osc mode (PIC16C73-10,
PIC16C74-10)
HS osc mode (PIC16C73-20,
PIC16C74-20)
5
—
—
—
µs
LP osc mode
TCY = 4/FOSC
2
TCY
Instruction Cycle Time (Note 1)
200
DC
ns
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30390B-page 226
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 23-2: CLOCK TIMING REQUIREMENTS (Cont.’d)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
3
TosL, External Clock in (OSC1) High or
TosH Low Time
50
2.5
10
—
—
—
—
—
—
—
—
—
—
25
50
15
ns
µs
ns
ns
ns
ns
XT oscillator
LP oscillator
HS oscillator
XT oscillator
LP oscillator
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 227
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C73/74
PIC16LC73/74
PIC16C73/74
PIC16LC73/74
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
20
20
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30390B-page 228
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
100
7*
—
—
ns VDD = 5V, -40˚C to +85˚C
ms VDD = 5V, -40˚C to +85˚C
Twdt
Watchdog Timer Time-out Period
18
33*
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
1024TOSC
72
TOSC = OSC1 period
ms VDD = 5V, -40˚C to +85˚C
ns
Tpwrt Power up Timer Period
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
These parameters are characterized but not tested.
28*
132*
100
TIOZ
*
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 229
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-5: TIMER0 AND TIMER1 CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-5: TIMER0 AND TIMER1 CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
42
Tt0L
Tt0P
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20*
10*
Greater of:
ns N = prescale value
(1, 2, 4,..., 256)
20µs or TCY + 40*
N
45
46
47
Tt1H
Tt1L
Tt1P
T1CKI High
Time
Synchronous, no prescaler
0.5Tcy + 20
10*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Synchronous,
with prescaler
PIC16C73/74
PIC16LC73/74
20*
Asynchronous
2Tcy
T1CKI Low
Time
Synchronous, no prescaler
0.5Tcy + 20
10*
Synchronous,
with prescaler
PIC16C73/74
PIC16LC73/74
20*
Asynchronous
Synchronous
2Tcy
T1CKI input
period
Greater of:
20µs or TCY + 40*
ns N = prescale value
(1, 2, 4, 8)
N
Asynchronous
Greater of:
20µs or 4Tcy
—
—
—
—
ns
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting the T1OSCEN bit)
DC
200 kHz
7Tosc
48
Tcke2tmrI Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2Tosc
—
*
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 230
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 23-1 for load conditions.
54
TABLE 23-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Parameter Sym Characteristic
No.
Min
Typ† Max Units Conditions
50
TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20*
—
—
ns
PIC16C73/74
PIC16LC73/74
10*
20*
—
—
—
—
—
—
—
—
ns
ns
ns
ns
With Prescaler
51
52
TccH
No Prescaler
0.5TCY + 20*
10*
CCP1 and CCP2
input high time
PIC16C73/74
PIC16LC73/74
With Prescaler
20*
—
—
—
—
ns
TccP
3TCY + 40*
N
ns N = prescale value
(1,4 or 16)
CCP1 and CCP2 input period
53
54
TccR CCP1 and CCP2 output rise time
TccF CCP1 and CCP2 output fall time
—
—
10
10
25
25
ns
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 231
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-7: PARALLEL SLAVE PORT TIMING FOR THE PIC16C74 ONLY
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 23-1 for load conditions
TABLE 23-7: PARALLEL SLAVE PORT REQUIREMENTS FOR THE PIC16C74 ONLY
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
63
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time)
20
20*
35*
—
—
—
—
—
—
—
—
—
60
30
ns
ns
ns
ns
ns
PIC16C74
PIC16LC74
64
65
TrdL2dtV RD↓ and CS↓ to data–out valid
TrdH2dtI RD↑ or CS↓ to data–out invalid
10
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 232
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-8: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 23-1 for load conditions
TABLE 23-8: SPI MODE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71
72
73
TscH
TscL
SCK input high time (slave mode)
SCK input low time (slave mode)
TCY + 20
TCY + 20
TCY
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
0.5TCY
—
—
ns
75
76
77
78
79
80
TdoR
SDO data output rise time
—
—
10
—
—
—
10
10
—
10
10
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TdoF
SDO data output fall time
TssH2doZ
TscR
SS↓ to SDO output hi-impedance
SCK output rise time (master mode)
SCK output fall time (master mode)
TscF
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 233
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 23-9: I C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 23-1 for load conditions
2
TABLE 23-9: I C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90
91
92
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated START
condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
DS30390B-page 234
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 23-10: I C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 23-1 for load conditions
2
TABLE 23-10: I C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
4.0
0.6
—
—
µs
µs
PIC16C73/74 must operate at
a minimum of 1.5 MHz
PIC16C73/74 must operate at
a minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC16C73/74 must operate at
a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC16C73/74 must operate at
a minimum of 10 MHz
SSP Module
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 235
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-11: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
121
pin
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 23-1 for load conditions
TABLE 23-11: SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16C73/74
PIC16LC73/74
—
—
—
—
—
—
—
—
—
—
—
—
50
100
25
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time PIC16C73/74
(Master Mode)
PIC16LC73/74
50
Data out rise time and fall time
PIC16C73/74
PIC16LC73/74
25
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 23-12: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 23-1 for load conditions
TABLE 23-12: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckl
SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK ↓ (DT hold time)
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 236
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 23-13: A/D CONVERTER CHARACTERISTICS:
PIC16C73-04 (COMMERCIAL, INDUSTRIAL)
PIC16C74-04 (COMMERCIAL, INDUSTRIAL)
PIC16C73-10 (COMMERCIAL, INDUSTRIAL)
PIC16C74-10 (COMMERCIAL, INDUSTRIAL)
PIC16C73-20 (COMMERCIAL, INDUSTRIAL)
PIC16C74-20 (COMMERCIAL, INDUSTRIAL)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT Integral error
less than
±1 LSb
NDIF Differential error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VSS ≤ AIN ≤ VREF
NFS
Full scale error
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN Analog input voltage VSS - 0.3
V
ZAIN Recommended
impedance of analog
—
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 237
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 23-14: A/D CONVERTER CHARACTERISTICS:
PIC16LC73-04 (COMMERCIAL, INDUSTRIAL)
PIC16LC74-04 (COMMERCIAL, INDUSTRIAL)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
less than
±1 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VSS ≤ AIN ≤ VREF
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage VSS - 0.3
V
Recommended
—
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
90
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
DS30390B-page 238
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 23-13: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
Q4
130
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 23-15: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
130
TAD
TAD
A/D clock period
1.6
2.0
—
—
µs
VREF ≥ 3.0V
µs VREF full range
130
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
µs PIC16LC73, PIC16LC74, VDD = 3.0V
µs PIC16C73, PIC16C74
—
3.0
2.0
—
6.0
4.0
9.0
6.0
—
131
132
TCNV Conversion time
(not including S/H
time) (Note 1)
9.5TAD
TSMP Sampling time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 239
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 240
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
24.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C73/74
NOT AVAILABLE AT THIS TIME
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 241
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 242
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
25.0 ELECTRICAL CHARACTERISTICS FOR PIC16C73A/74A
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125˚C
Storage temperature .............................................................................................................................. -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD and MCLR) ...................................................-0.6V to (VDD + 0.6V)
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .................................................................................................0 to +14V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................±20 mA
Output clamp current, IOK (V0 < 0 or V0 > VDD)..............................................................................................................±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
Note 3: PORTD and PORTE are not implemented on the PIC16C73A.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 243
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 25-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
DS30390B-page 244
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(6)
25.1
DC Characteristics:
PIC16C73A-04 (Commercial, Industrial, Automotive )
(6)
PIC16C74A-04 (Commercial, Industrial, Automotive )
(6)
PIC16C73A-10 (Commercial, Industrial, Automotive )
(6)
PIC16C74A-10 (Commercial, Industrial, Automotive )
(6)
PIC16C73A-20 (Commercial, Industrial, Automotive )
(6)
PIC16C74A-20 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param
No.
Characteristic
Sym
VDD
Min Typ† Max Units
Conditions
D001 Supply Voltage
D001A
4.0
4.5
-
-
6.0
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D002 RAM Data Retention
Voltage (Note 1)
VDR
-
1.5*
VSS
-
-
V
Device in SLEEP mode
D003
VDD start voltage to
VPOR
-
-
V
See section on Power-on Reset for details
ensure Power-on Reset
D004
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
-
V/ms See section on Power-on Reset for details
D010 Supply Current (Note 2,5) IDD
-
2.7
5
mA XT, RC osc configuration (PIC16C74A-04)
FOSC = 4 MHz, VDD = 5.5V (Note 4)
D013
-
-
13.5 30
mA HS osc configuration (PIC16C74A-20)
FOSC = 20 MHz, VDD = 5.5V
D015 Brown-out Reset Current ∆IBOR
300* 500 µA BOR enabled VDD = 5.0V
(Note 7)
D020 Power-down Current
D021 (Note 3,5)
D021A
IPD
-
-
-
-
10.5 42 µA VDD = 4.0V, WDT enabled, -40°C to +85°C
1.5
1.5
21
24
µA VDD = 4.0V, WDT disabled, -0°C to +70°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
D021B
1.5 TBD µA VDD = 4.0V, WDT disabled, -40°C to +125°C
D023 Brown-out Reset Current ∆IBOR
-
300* 500 µA BOR enabled VDD = 5.0V
(Note 7)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: Automotive operating range is Advanced information for this device.
7: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 245
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(6)
25.2
DC Characteristics:
PIC16LC73A-04 (Commercial, Industrial, Automotive )
(6)
PIC16LC74A-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +125˚C for automotive,
≤ TA ≤ +85˚C for industrial and
≤ TA ≤ +70˚C for commercial
DC CHARACTERISTICS
-40˚C
0˚C
Param
No.
Characteristic
Sym Min Typ† Max Units
Conditions
D001
D002
Supply Voltage
VDD
VDR
3.0
-
-
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
Device in SLEEP mode
RAM Data Retention
Voltage (Note 1)
1.5*
D003
D004
D010
VDD start voltage to
ensure Power-on Reset
VPOR
-
VSS
-
-
-
V
See section on Power-on Reset for details
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
V/ms See section on Power-on Reset for details
Supply Current (Note 2,5) IDD
-
2.0
3.8
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
D010A
D015
-
-
22.5 48
300* 500
µA LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
Brown-out Reset Current ∆IBOR
µA BOR enabled VDD = 3.0V
(Note 7)
D020
D021
D021A
D021B
Power-down Current
(Note 3,5)
IPD
-
-
-
-
7.5
0.9
0.9
0.9
30
5
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, 0°C to +70°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, -40°C to +125°C
10
D023
Brown-out Reset Current ∆IBOR
-
300* 500
µA BOR enabled VDD = 3.0V
(Note 7)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac-
terization and is for design guidance only. This is not tested.
6: Automotive operating range is Advanced information for this device.
7: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30390B-page 246
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
(4)
25.3
DC Characteristics:
PIC16C73A-04 (Commercial, Industrial, Automotive )
(4)
PIC16C74A-04 (Commercial, Industrial, Automotive )
(4)
PIC16C73A-10 (Commercial, Industrial, Automotive )
(4)
PIC16C74A-10 (Commercial, Industrial, Automotive )
(4)
PIC16C73A-20 (Commercial, Industrial, Automotive )
(4)
PIC16C74A-20 (Commercial, Industrial, Automotive )
(4)
PIC16LC73A-04 (Commercial, Industrial, Automotive )
(4)
PIC16LC74A-04 (Commercial, Industrial, Automotive )
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 25.1 and
Section 25.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Input Low Voltage
I/O ports
VIL
D030
D031
D032
with TTL buffer
VSS
VSS
VSS
-
-
-
0.5V
0.2VDD
0.2VDD
V
V
V
with Schmitt Trigger buffer
MCLR, RA4/T0CKI,OSC1
(in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
VSS
-
0.3VDD
V
Note1
VIH
-
-
-
-
-
D040
D040A
D041
D042
with TTL buffer
2.0
VDD
VDD
VDD
VDD
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
For VDD > 5.5V or VDD < 4.5V
For entire VDD range
0.8VDD
0.8VDD
0.8VDD
with Schmitt Trigger buffer
MCLR, RA4/T0CKI, RC7:RC4,
RD7:RD4, RB0/INT
D042A RE2:RE0, OSC1 (XT, HS and LP)
0.7VDD
0.9VDD
50
-
-
VDD
VDD
V
V
Note1
D043
D070
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
IPURB
IIL
250 400
µA VDD = 5V, VPIN = VSS
D060
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at hi-imped-
ance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 247
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for automotive,
-40˚C ≤ TA ≤ +85˚C for industrial and
DC CHARACTERISTICS
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 25.1 and
Section 25.2.
Param
No.
Characteristic
Sym
Min Typ Max Units
†
Conditions
Output Low Voltage
D080
I/O ports
VOL
-
-
-
-
-
-
-
-
0.6
0.6
0.6
0.6
V
V
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
Output High Voltage
D090
I/O ports (Note 3)
VOH VDD - 0.7 -
VDD - 0.7 -
-
-
-
-
V
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
D090A
D092
OSC2/CLKOUT (RC osc config)
VDD - 0.7 -
D092A
VDD - 0.7 -
Capacitive Loading Specs on
Output Pins
D100
OSC2 pin
COSC2
-
-
15
pF In XT, HS and LP modes when exter-
nal clock is used to drive OSC1.
D101
D102
All I/O pins and OSC2 (in RC
CIO
CB
-
-
-
-
50
400
pF
pF
2
mode) SCL, SDA in I C mode
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Automotive operating range is Advanced information for this device.
DS30390B-page 248
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
25.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
2
1. TppS2ppS
2. TppS
3. TCC:ST
4. Ts
(I C specifications only)
2
(I C specifications only)
T
F
Frequency
T
Time
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
2
I C only
AA
output access
Bus free
High
Low
High
Low
BUF
2
TCC:ST (I C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 25-1: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 100 pF for PORTD and PORTE outputs when used as system bus
50 pF for all pins except OSC2, but including PORTD and PORTE outputs as
ports
15 pF for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16C73A.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 249
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
25.5
Timing Diagrams and Specifications
FIGURE 25-2: EXTERNAL CLOCK TIMING
Q4
Q1
1
Q2
Q3
Q4
4
Q1
OSC1
3
3
4
2
CLKOUT
TABLE 25-2: CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
Fos External CLKIN Frequency
DC
DC
—
—
4
4
MHz XT and RC osc mode
(Note 1)
MHz HS osc mode (PIC16C73A-04,
PIC16C74A-04)
DC
—
20
MHz HS osc mode (PIC16C73A-20,
PIC16C74A-20)
DC
DC
0.1
4
—
—
—
—
200
4
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
Oscillator Frequency
(Note 1)
4
4
MHz HS osc mode (PIC16C73A-04,
PIC16C74A-04)
4
4
—
—
10
20
MHz HS osc mode (PIC16C73A-10,
PIC16C74A-10)
MHz HS osc mode (PIC16C73A-20,
PIC16C74A-20)
5
—
—
—
200
—
kHz LP osc mode
1
Tosc External CLKIN Period
250
250
ns
ns
XT and RC osc mode
(Note 1)
—
HS osc mode (PIC16C73A-04,
PIC16C74A-04)
100
50
—
—
—
—
ns
ns
HS osc mode (PIC16C73A-10,
PIC16C74A-10)
HS osc mode (PIC16C73A-20,
PIC16C74A-20)
5
—
—
—
—
—
—
µs
ns
ns
ns
LP osc mode
RC osc mode
XT osc mode
Oscillator Period
(Note 1)
250
250
250
10,000
250
HS osc mode (PIC16C73A-04,
PIC16C74A-04)
100
50
—
—
250
250
ns
ns
HS osc mode (PIC16C73A-10,
PIC16C74A-10)
HS osc mode (PIC16C73A-20,
PIC16C74A-20)
5
—
—
—
µs
LP osc mode
TCY = 4/FOSC
2
TCY
Instruction Cycle Time (Note 1)
200
DC
ns
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
DS30390B-page 250
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 25-2: CLOCK TIMING REQUIREMENTS (Cont.’d)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units Conditions
3
TosL, External Clock in (OSC1) High or
TosH Low Time
50
2.5
10
—
—
—
—
—
—
—
—
—
—
25
50
15
ns
µs
ns
ns
ns
ns
XT oscillator
LP oscillator
HS oscillator
XT oscillator
LP oscillator
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 251
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-3: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
12
18
19
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-3: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
—
—
—
—
15
15
5
30
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
30
TckR
TckF
CLKOUT rise time
CLKOUT fall time
15
15
5
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
—
—
—
0.5TCY + 20
—
0.25TCY + 25
TckH2ioI
Port in hold after CLKOUT ↑
0
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
80 - 100
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
TBD
—
—
ns
Port input invalid (I/O in hold time)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
TBD
—
—
10
—
10
—
—
—
—
25
60
25
60
—
—
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
PIC16C73/74
PIC16LC73/74
PIC16C73/74
PIC16LC73/74
—
21*
TioF
—
—
22††*
23††*
Tinp
Trbp
20
20
RB7:RB4 change INT high or low time
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30390B-page 252
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 25-1 for load conditions.
FIGURE 25-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
1
—
—
µs VDD = 5V, -40˚C to +125˚C
Twdt
Watchdog Timer Time-out Period
7*
18
33*
ms VDD = 5V, -40˚C to +125˚C
(No Prescaler)
32
33
34
Tost
Oscillation Start-up Timer Period
—
28*
—
1024TOSC
—
132*
1.1
—
TOSC = OSC1 period
Tpwrt Power up Timer Period
72
—
ms VDD = 5V, -40˚C to +125˚C
TIOZ
I/O Hi-impedance from MCLR Low
µs
or Watchdog Timer Reset
35
TBOR
Brown-out Reset pulse width
100
—
—
µs 3.8V ≤ VDD ≤ 4.2V
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 253
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-6: TIMER0 AND TIMER1 CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 25-1 for load conditions.
TABLE 25-5: TIMER0 AND TIMER1 CLOCK REQUIREMENTS
Parameter No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
41
Tt0L
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20*
10*
42
45
Tt0P
Tt1H
TCY + 40*
N
ns N = prescale value
(1, 2, 4,..., 256)
T1CKI High Synchronous, no prescaler
0.5Tcy + 20
10*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Time
Synchronous, PIC16C73A/74A
with prescaler
PIC16LC73A/74A
20*
Asynchronous
2Tcy
46
47
Tt1L
T1CKI Low Synchronous, no prescaler
0.5Tcy + 20
10*
Time
Synchronous, PIC16C73A/74A
with prescaler
PIC16LC73A/74A
20*
Asynchronous
2Tcy
Tt1P
Ft1
T1CKI input Synchronous
period
Tcy + 40*
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
4Tcy
DC
—
—
—
ns
Timer1 oscillator input frequency range
200 kHz
(oscillator enabled by setting the T1OSCEN bit)
48
Tcke2tmrI Delay from external clock edge to timer increment
These parameters are characterized but not tested.
2Tosc
—
7Tosc
—
*
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 254
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 25-1 for load conditions.
54
TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param Sym Characteristic
No.
Min
Typ† Max Units Conditions
50
TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20*
—
—
ns
PIC16C73A/74A
PIC16LC73A/74A
10*
20*
—
—
—
—
—
—
—
—
ns
ns
ns
ns
With Prescaler
51
52
TccH
No Prescaler
0.5TCY + 20*
10*
CCP1 and CCP2
input high time
PIC16C73A/74A
PIC16LC73A/74A
With Prescaler
20*
—
—
—
—
ns
TccP
3TCY + 40*
N
ns N = prescale value
(1,4 or 16)
CCP1 and CCP2 input period
53
54
TccR CCP1 and CCP2 output rise time
TccF CCP1 and CCP2 output fall time
—
—
10
10
25
25
ns
ns
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 255
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-8: PARALLEL SLAVE PORT TIMING FOR THE PIC16C74A ONLY
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 25-1 for load conditions
TABLE 25-7: PARALLEL SLAVE PORT REQUIREMENTS FOR THE PIC16C74A ONLY
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
63
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C74A
PIC16LC74A
20
20*
35*
—
—
—
—
—
—
—
—
—
60
30
ns
ns
ns
ns
ns
64
65
TrdL2dtV RD↓ and CS↓ to data–out valid
TrdH2dtI RD↑ or CS↓ to data–out invalid
10
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 256
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-9: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 25-1 for load conditions
TABLE 25-8: SPI MODE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71
72
73
TscH
TscL
SCK input high time (slave mode)
SCK input low time (slave mode)
TCY + 20
TCY + 20
TCY
—
—
—
—
—
—
ns
ns
ns
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
0.5TCY
—
—
ns
75
76
77
78
79
80
TdoR
SDO data output rise time
—
—
10
—
—
—
10
10
—
10
10
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
TdoF
SDO data output fall time
TssH2doZ
TscR
SS↓ to SDO output hi-impedance
SCK output rise time (master mode)
SCK output fall time (master mode)
TscF
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 257
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 25-10: I C BUS START/STOP BITS TIMING
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 25-1 for load conditions
2
TABLE 25-9: I C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min Typ Max Units
Conditions
90
91
92
93
TSU:STA START condition
Setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Only relevant for repeated START
condition
ns
ns
ns
ns
THD:STA START condition
Hold time
4000
600
After this period the first clock
pulse is generated
TSU:STO STOP condition
Setup time
4700
600
THD:STO STOP condition
Hold time
4000
600
DS30390B-page 258
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
2
FIGURE 25-11: I C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 25-1 for load conditions
2
TABLE 25-10: I C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
400 kHz mode
4.0
0.6
—
—
µs
µs
PIC16C73A/74Amust operate
at a minimum of 1.5 MHz
PIC16C73A/74Amust operate
at a minimum of 10 MHz
SSP Module
1.5TCY
4.7
—
—
101
TLOW
Clock low time
100 kHz mode
µs
µs
PIC16C73A/74Amust operate
at a minimum of 1.5 MHz
400 kHz mode
1.3
—
PIC16C73A/74Amust operate
at a minimum of 10 MHz
SSP Module
1.5TCY
—
—
102
103
TR
TF
SDA and SCL rise
time
100 kHz mode
400 kHz mode
1000
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
SDA and SCL fall time 100 kHz mode
400 kHz mode
—
300
300
ns
ns
20 + 0.1Cb
Cb is specified to be from
10 to 400 pF
90
91
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for repeated
START condition
THD:STA START condition hold 100 kHz mode
—
After this period the first clock
pulse is generated
time
400 kHz mode
100 kHz mode
400 kHz mode
—
106
107
92
THD:DAT Data input hold time
—
0
0.9
—
TSU:DAT Data input setup time 100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
Note 2
—
TSU:STO STOP condition setup 100 kHz mode
—
time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
—
109
110
TAA
Output valid from
clock
3500
—
Note 1
—
TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission can
start
—
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2
2
2: A fast-mode I C-bus device can be used in a standard-mode I C-bus system, but the requirement tsu;DAT ≥ 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
2
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I C bus specification) before the SCL line is
released.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 259
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-12: USART MODULE: SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
121
pin
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 25-1 for load conditions
TABLE 25-11: SERIAL PORT SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
SLAVE)
Clock high to data out valid
PIC16C73A/74A
PIC16LC73A/74A
—
—
—
—
—
—
—
—
—
—
—
—
50
100
25
ns
ns
ns
ns
ns
ns
121
122
Tckrf
Tdtrf
Clock out rise time and fall time PIC16C73A/74A
(Master Mode)
PIC16LC73A/74A
50
Data out rise time and fall time PIC16C73A/74A
PIC16LC73A/74A
25
50
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 25-13: USART MODULE: SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 25-1 for load conditions
TABLE 25-12: SERIAL PORT SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckl
SYNC RCV (MASTER & SLAVE)
Data hold before CK ↓ (DT hold time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK ↓ (DT hold time)
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30390B-page 260
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 25-13: A/D CONVERTER CHARACTERISTICS:
(3)
PIC16C73A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C74A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C73A-10 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C74A-10 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C73A-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16C74A-20 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
(3)
(3)
(3)
(3)
(3)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
NINT Integral error
less than
±1 LSb
NDIF Differential error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VREF = VDD = 5.12V, VSS ≤ AIN ≤ VREF
VSS ≤ AIN ≤ VREF
NFS
Full scale error
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN Analog input voltage VSS - 0.3
V
ZAIN Recommended
impedance of analog
—
kΩ
voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
180
—
—
µA Average current consumption when
A/D is on. (Note 1)
IREF
VREF input current
(Note 2)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: Automotive operating range is Advanced information for this device.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 261
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
TABLE 25-14: A/D CONVERTER CHARACTERISTICS:
(4)
PIC16LC73A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
PIC16LC74A-04 (COMMERCIAL, INDUSTRIAL, AUTOMOTIVE )
(4)
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
NR
Resolution
—
—
—
—
8-bits
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
NINT
Integral error
less than
±1 LSb
NDIF
NFS
Differential error
Full scale error
—
—
—
—
—
—
less than
±1 LSb
—
—
—
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VREF = VDD = 3.0V (Note 1)
VSS ≤ AIN ≤ VREF
less than
±1 LSb
NOFF Offset error
less than
±1 LSb
—
Monotonicity
—
guaranteed
—
—
V
VREF Reference voltage
3.0V
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage VSS - 0.3
V
Recommended
—
kΩ
impedance of ana-
log voltage source
IAD
A/D conversion cur-
rent (VDD)
—
—
90
—
—
µA Average current consumption when
A/D is on. (Note 2)
IREF
VREF input current
(Note 3)
1
10
mA During sampling
µA All other times
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: These specifications apply if VREF = 3.0V and if VDD ≥ 3.0V. VIN must be between VSS and VREF
2: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
3: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
4: Automotive operating range is Advanced information for this device.
DS30390B-page 262
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
FIGURE 25-14: A/D CONVERSION TIMING
BSF ADCON0, GO
(TOSC/2) (1)
1 Tcy
131
Q4
130
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 25-15: A/D CONVERSION REQUIREMENTS
Parameter
No.
Sym Characteristic
Min
Typ†
Max
Units
Conditions
VREF ≥ 3.0V
130
TAD
TAD
A/D clock period
1.6
2.0
—
—
µs
µs VREF full range
130
A/D Internal RC
Oscillator source
ADCS1:ADCS0 = 11
(RC oscillator source)
3.0
6.0
9.0
µs PIC16LC73A, PIC16LC74A,
VDD = 3.0V
2.0
—
4.0
6.0
—
µs PIC16C73A, PIC16C74A
131
132
TCNV Conversion time
(not including S/H
time) (Note 1)
9.5TAD
—
TSMP Sampling time
Note 2
20
—
µs
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 13.1 for min conditions.
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 263
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 264
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
26.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR PIC16C73A/
74A
NOT AVAILABLE AT THIS TIME
1995 Microchip Technology Inc.
Preliminary
DS30390B-page 265
PIC16C7X
Applicable Devices 70 71 71A 72 73 73A 74 74A
NOTES:
DS30390B-page 266
Preliminary
1995 Microchip Technology Inc.
PIC16C7X
27.0 PACKAGING INFORMATION
27.1
18-Lead Ceramic CERDIP Dual In-line with Window (300 mil)
N
α
C
E1
E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A3
A2
A1
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
α
0°
10°
0°
10°
A
—
5.080
1.7780
4.699
4.445
0.585
1.651
0.381
23.622
20.320
8.382
7.874
2.540
8.128
10.160
3.810
18
—
0.200
0.070
0.185
0.175
0.023
0.065
0.015
0.930
0.800
0.330
0.310
0.100
0.320
0.400
0.150
18
A1
A2
A3
B
0.381
3.810
3.810
0.355
1.270
0.203
22.352
20.320
7.620
5.588
2.540
7.366
7.620
3.175
18
0.015
0.150
0.150
0.014
0.050
0.008
0.880
0.800
0.300
0.220
0.100
0.290
0.300
0.125
18
B1
C
Typical
Typical
Typical
Typical
D
D1
E
Reference
Reference
E1
e1
eA
eB
L
Reference
Typical
Reference
Typical
N
S
0.508
0.381
1.397
1.270
0.020
0.015
0.055
0.050
S1
1995 Microchip Technology Inc.
DS30390B-page 267
PIC16C7X
27.2
28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil)
N
C
E1 E
eA
eB
α
Pin #1
Indicator Area
D
S1
S
Base
Plane
Seating
Plane
A3
A2
L
A
A1
B1
e1
B
D1
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
α
0°
10°
5.030
1.524
3.506
2.388
0.508
1.321
0.305
35.916
33.147
8.128
7.620
2.667
7.874
8.179
4.064
28
0°
10°
A
3.937
1.016
2.921
1.930
0.406
1.219
0.228
35.204
32.893
7.620
7.366
2.413
7.366
7.594
3.302
28
0.155
0.040
0.115
0.076
0.016
0.048
0.009
1.386
1.295
0.300
0.290
0.095
0.290
0.299
0.130
28
0.198
0.060
0.138
0.094
0.020
0.052
0.012
1.414
1.305
0.320
0.300
0.105
0.310
0.322
0.160
28
A1
A2
A3
B
B1
C
Typical
Typical
D
D1
E
Reference
E1
e1
eA
eB
L
Typical
Reference
N
S
1.143
0.533
1.397
0.737
0.045
0.021
0.055
0.029
S1
DS30390B-page 268
1995 Microchip Technology Inc.
PIC16C7X
27.3
40-Lead Ceramic CERDIP Dual In-line with Window (600 mil)
N
E1
E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A3
A2
A1
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
α
0°
10°
0°
10°
A
4.318
0.381
3.810
3.810
0.355
1.270
0.203
5.715
1.778
4.699
4.445
0.585
1.651
0.381
52.705
48.260
15.875
15.240
2.540
16.002
18.034
3.810
40
0.170
0.015
0.150
0.150
0.014
0.050
0.008
2.025
1.900
0.600
0.510
0.100
0.590
0.600
0.125
40
0.225
0.070
0.185
0.175
0.023
0.065
0.015
2.075
1.900
0.625
0.600
0.100
0.630
0.710
0.150
40
A1
A2
A3
B
B1
C
Typical
Typical
Typical
Typical
D
51.435
48.260
15.240
12.954
2.540
14.986
15.240
3.175
40
D1
E
Reference
Reference
E1
e1
eA
eB
L
Reference
Typical
Reference
Typical
N
S
1.016
0.381
2.286
1.778
0.040
0.015
0.090
0.070
S1
1995 Microchip Technology Inc.
DS30390B-page 269
PIC16C7X
27.4
18-Lead Plastic Dual In-line (300 mil)
N
α
C
E1
E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A2
A1
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
10°
4.064
–
0°
10°
0.160
–
A
–
–
A1
A2
B
0.381
3.048
0.355
1.524
0.203
22.479
20.320
7.620
6.096
2.489
7.620
7.874
3.048
18
0.015
0.120
0.014
0.060
0.008
0.885
0.800
0.300
0.240
0.098
0.300
0.310
0.120
18
3.810
0.559
1.524
0.381
23.495
20.320
8.255
7.112
2.591
7.620
9.906
3.556
18
0.150
0.022
0.060
0.015
0.925
0.800
0.325
0.280
0.102
0.300
0.390
0.140
18
B1
C
Reference
Typical
Reference
Typical
D
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
0.889
0.127
–
0.035
0.005
–
S1
–
–
DS30390B-page 270
1995 Microchip Technology Inc.
PIC16C7X
27.5
28-Lead Plastic Dual In-line (300 mil)
N
α
E1
E
C
eA
eB
Pin No. 1
Indicator
Area
B2
B1
D
S
Base
Plane
Seating
Plane
L
Detail A
B
Detail A
B3
A
A2
A1
e1
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
α
0°
10°
4.572
–
0°
10°
A
3.632
0.381
3.175
0.406
1.016
0.762
0.203
0.203
0.143
0.015
0.125
0.016
0.040
0.030
0.008
0.008
1.385
1.300
0.310
0.280
0.100
0.310
0.320
0.125
28
0.180
–
A1
A2
B
3.556
0.559
1.651
1.016
0.508
0.331
35.179
33.020
8.382
7.493
2.540
7.874
9.652
3.683
-
0.140
0.022
0.065
0.040
0.020
0.013
1.395
1.300
0.330
0.295
0.100
0.310
0.380
0.145
-
B1
B2
B3
C
Typical
4 places
4 places
Typical
Typical
4 places
4 places
Typical
D
34.163
33.020
7.874
7.112
2.540
7.874
8.128
3.175
28
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
0.584
1.220
0.023
0.048
1995 Microchip Technology Inc.
DS30390B-page 271
PIC16C7X
27.6
40-Lead Plastic Dual In-line (600 mil)
N
α
E1
E
C
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
e1
Base
Plane
Seating
Plane
L
B1
B
A
A2
A1
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Inches
Symbol
Min
Max
Notes
Min
Max
Notes
α
0°
10°
5.080
–
0°
10°
0.200
–
A
–
–
A1
A2
B
0.381
3.175
0.355
1.270
0.203
0.015
0.125
0.014
0.050
0.008
2.015
1.900
0.600
0.530
0.098
0.600
0.600
0.115
40
4.064
0.559
1.778
0.381
52.197
48.260
15.875
13.970
2.591
15.240
17.272
3.683
40
0.160
0.022
0.070
0.015
2.055
1.900
0.625
0.550
0.102
0.600
0.680
0.145
40
B1
C
Typical
Typical
Typical
Typical
D
51.181
48.260
15.240
13.462
2.489
15.240
15.240
2.921
40
D1
E
Reference
Reference
E1
e1
eA
eB
L
Typical
Typical
Reference
Reference
N
S
1.270
0.508
–
0.050
0.020
–
S1
–
–
DS30390B-page 272
1995 Microchip Technology Inc.
PIC16C7X
27.7
18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)
e
B
h x 45°
N
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Base
Plane
CP
Seating
Plane
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Max
Inches
Symbol
Min
0°
Notes
Min
Max
Notes
α
A
8°
0°
8°
2.362
0.101
0.355
0.241
11.353
7.416
1.270
10.007
0.381
0.406
18
2.642
0.300
0.483
0.318
11.735
7.595
1.270
10.643
0.762
1.143
18
0.093
0.004
0.014
0.009
0.447
0.292
0.050
0.394
0.015
0.016
18
0.104
0.012
0.019
0.013
0.462
0.299
0.050
0.419
0.030
0.045
18
A1
B
C
D
E
e
Reference
Reference
H
h
L
N
CP
–
0.102
–
0.004
1995 Microchip Technology Inc.
DS30390B-page 273
PIC16C7X
27.8
28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body)
e
B
N
h x 45°
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Base
Plane
CP
Seating
Plane
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Max
Inches
Symbol
Min
0°
Notes
Min
Max
Notes
α
A
8°
0°
8°
2.362
0.101
0.355
0.241
17.703
7.416
1.270
10.007
0.381
0.406
28
2.642
0.300
0.483
0.318
18.085
7.595
1.270
10.643
0.762
1.143
28
0.093
0.004
0.014
0.009
0.697
0.292
0.050
0.394
0.015
0.016
28
0.104
0.012
0.019
0.013
0.712
0.299
0.050
0.419
0.030
0.045
28
A1
B
C
D
E
e
Typical
Typical
H
h
L
N
CP
–
0.102
–
0.004
DS30390B-page 274
1995 Microchip Technology Inc.
PIC16C7X
27.9
20-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm)
N
Index
area
E
H
α
C
L
1 2 3
e
B
A
Base plane
CP
Seating plane
D
A1
Package Group: Plastic SSOP
Millimeters
Max
Inches
Symbol
Min
Notes
Min
Max
Notes
α
A
0°
8°
0°
8°
1.730
0.050
0.250
0.130
7.070
5.200
0.650
7.650
0.550
20
1.990
0.210
0.380
0.220
7.330
5.380
0.650
7.900
0.950
20
0.068
0.002
0.010
0.005
0.278
0.205
0.026
0.301
0.022
20
0.078
0.008
0.015
0.009
0.289
0.212
0.026
0.311
0.037
20
A1
B
C
D
E
e
Reference
Reference
H
L
N
CP
-
0.102
-
0.004
1995 Microchip Technology Inc.
DS30390B-page 275
PIC16C7X
27.10 28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm)
N
Index
area
E
H
α
C
L
1 2 3
e
B
A
Base plane
CP
Seating plane
D
A1
Package Group: Plastic SSOP
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
α
A
0°
8°
0°
8°
1.730
0.050
0.250
0.130
10.070
5.200
0.650
7.650
0.550
28
1.990
0.210
0.380
0.220
10.330
5.380
0.650
7.900
0.950
28
0.068
0.002
0.010
0.005
0.396
0.205
0.026
0.301
0.022
28
0.078
0.008
0.015
0.009
0.407
0.212
0.026
0.311
0.037
28
A1
B
C
D
E
e
Reference
Reference
H
L
N
CP
-
0.102
-
0.004
DS30390B-page 276
1995 Microchip Technology Inc.
PIC16C7X
27.11 44-Lead Plastic Leaded Chip Carrier (Square)
D
0.812/0.661
N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007
S
B D-E S
-A-
0.177
.007
2 Sides
-H-
B A S
9
S
A
D1
A1
-D-
3
D3/E3
D2
0.101
.004
Seating
Plane
D
0.38
.015
-C-
F-G
E2
S
S
3
-G-
4
4
3
-F-
8
E1
E
0.38
.015
F-G
-B-
-E-
3
0.177
.007
A F-G S
S
10
0.812/0.661
.032/.026
3
0.254
.010
0.254
.010
11
Max
Max
11
1.524
.060
0.508
.020
0.508
.020
Min
-H-
2
-H-
2
6
6
-C-
5
1.651
.065
1.651
.065
0.64
.025
0.533/0.331
.021/.013
Min
R
R
1.14/0.64
.045/.025
1.14/0.64
.045/.025
0.177
.007
D-E S
F-G S ,
A
M
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Inches
Max
Symbol
Min
Max
Notes
Min
Notes
A
A1
D
4.191
2.413
17.399
16.510
15.494
12.700
17.399
16.510
15.494
12.700
44
4.572
2.921
0.165
0.095
0.685
0.650
0.610
0.500
0.685
0.650
0.610
0.500
44
0.180
0.115
0.695
0.656
0.630
0.500
0.695
0.656
0.630
0.500
44
17.653
16.663
16.002
12.700
17.653
16.663
16.002
12.700
44
D1
D2
D3
E
Reference
Reference
Reference
Reference
E1
E2
E3
N
CP
LT
–
0.102
–
0.004
0.015
0.203
0.381
0.008
1995 Microchip Technology Inc.
DS30390B-page 277
PIC16C7X
27.12 44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form))
0.20 M C A-B S D S
D
4
0.20 M H A-B S D S
0.05 mm/mm A-B
D1
5
7
0.20 min.
D3
0.13 R min.
Index
area
6
PARTING
LINE
0.13/0.30 R
b
α
9
L
C
E3
E1
E
1.60 Ref.
0.20 M C A-B S D S
4
TYP 4x
10
0.20 M H A-B S D S
0.05 mm/mm D
5
7
e
B
A2
A
Base
Plane
Seating
Plane
A1
Package Group: Plastic MQFP
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
α
A
0°
7°
0°
7°
2.000
0.050
1.950
0.300
0.150
12.950
9.900
8.000
12.950
9.900
8.000
0.800
0.730
44
2.350
0.250
2.100
0.450
0.180
13.450
10.100
8.000
13.450
10.100
8.000
0.800
1.030
44
0.078
0.002
0.768
0.011
0.006
0.510
0.390
0.315
0.510
0.390
0.315
0.031
0.028
44
0.093
0.010
0.083
0.018
0.007
0.530
0.398
0.315
0.530
0.398
0.315
0.032
0.041
44
A1
A2
b
Typical
Typical
C
D
D1
D3
E
Reference
Reference
Reference
Reference
E1
E3
e
L
N
CP
0.102
–
0.004
–
DS30390B-page 278
1995 Microchip Technology Inc.
PIC16C7X
27.13 44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form)
D
D1
1.0ø (0.039ø) Ref.
11°/13°(4x)
0° Min
Pin#1
2
Pin#1
2
E
E1
Θ
11°/13°(4x)
Detail B
e
3.0ø (0.118ø) Ref.
R1 0.08 Min
R 0.08/0.20
Option 1 (TOP side)
Option 2 (TOP side)
Gage Plane
0.250
A1
Base Metal
Lead Finish
b
A2
A
S
0.20
Min
L
L
c
c1
L1
Detail A
Detail B
1.00 Ref
1.00 Ref.
b1
Detail A
Detail B
Package Group: Plastic TQFP
Millimeters
Max
Inches
Max
Symbol
Min
Notes
Min
Notes
A
A1
A2
D
1.00
0.05
0.95
11.75
9.90
11.75
9.90
0.45
1.20
0.15
0.039
0.002
0.037
0.463
0.390
0.463
0.390
0.018
0.047
0.006
0.041
0.482
0.398
0.482
0.398
0.030
1.05
12.25
10.10
12.25
10.10
0.75
D1
E
E1
L
e
0.80 BSC
0.031 BSC
b
0.30
0.30
0.09
0.09
44
0.45
0.40
0.20
0.16
44
0.012
0.012
0.004
0.004
44
0.018
0.016
0.008
0.006
44
b1
c
c1
N
Θ
0°
7°
0°
7°
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
1995 Microchip Technology Inc.
DS30390B-page 279
PIC16C7X
27.14 Package Marking Information
18-Lead PDIP
Example
PIC16C71-04/P
9452CBA
MMMMMMMMMMMMM
XXXXXXXXXXXXXXXX
AABBCDE
18-Lead SOIC
Example
PIC16C71
MMMMMMMMMM
XXXXXXXXXXXX
XXXXXXXXXXXX
-20/50
AABBCDE
9447CBA
18-Lead CERDIP Windowed
Example
MMMMMM
XXXXXXXX
PIC16C71
/JW
AABBCDE
945/CBT
20-Lead SSOP
Example
XXXXXXXX
XXXXXXXX
PIC16C70
20I/SS025
AABBCAE
9517SBP
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C72
20I/SS025
AABBCAE
9517SBP
Legend:
MM...M
XX...X
AA
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
BB
C
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
D
1
E
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
*
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30390B-page 280
1995 Microchip Technology Inc.
PIC16C7X
Package Marking Information (Cont’d)
28-Lead PDIP (Skinny DIP)
Example
PIC16C73-10/SP
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
AABBCDE
AABBCDE
28-Lead Side Brazed Skinny Windowed
Example
XXXXXXXXXXX
XXXXXXXXXXX
AABBCDE
PIC16C73/JW
9517CAT
28-Lead SOIC
Example
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
PIC16C73-10/SO
AABBCDE
945/CAA
40-Lead PDIP
Example
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
PIC16C74-04/P
AABBCDE
9512CAA
Legend:
MM...M
XX...X
AA
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
BB
C
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
D
1
E
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
*
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
1995 Microchip Technology Inc.
DS30390B-page 281
PIC16C7X
Package Marking Information (Cont’d)
40-Lead CERDIP Windowed
Example
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C74/JW
AABBCDE
AABBCDE
44-Lead PLCC
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16C74
-10/L
AABBCDE
44-Lead MQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
PIC16C74
-10/PQ
AABBCDE
AABBCDE
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
PIC16C74A
-10/TQ
AABBCDE
AABBCDE
Legend:
MM...M
XX...X
AA
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
BB
Week code (week of January 1 is week '01’)
C
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
D
1
E
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
Note:
*
Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30390B-page 282
1995 Microchip Technology Inc.
PIC16C7X
APPENDIX A:
APPENDIX B: COMPATIBILITY
The following are the list of modifications over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1. Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (4K now as opposed to 512 before) and
register file (192 bytes now versus 32 bytes
before).
1. Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
2. A PC high latch register (PCLATH) is added to
handle program memory paging. Bits PA2, PA1,
PA0 are removed from STATUS register.
3. Eliminate any data memory page switching.
Redefine data variables to reallocate them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
3. Data memory paging is redefined slightly. STA-
TUS register is modified.
5. Change reset vector to 0000h.
4. Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compati-
bility with PIC16C5X.
5. OPTION and TRIS registers are made address-
able.
6. Interrupt capability is added. Interrupt vector is
at 0004h.
7. Stack size is increased to 8 deep.
8. Reset vector is changed to 0000h.
9. Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Reg-
isters are reset differently.
10. Wake up from SLEEP through interrupt is
added.
11. Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These tim-
ers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
12. PORTB has weak pull-ups and interrupt on
change feature.
13. T0CKI pin is also a port pin (RA4) now.
14. FSR is made a full eight bit register.
15. “In-circuit serial programming” is made possible.
The user can program PIC16CXX devices using
only five pins: VDD, VSS, MCLR/VPP, RB6 (clock)
and RB7 (data in/out).
16. PCON status register is added with a Power-on
Reset status bit (POR).
17. Code protection scheme is enhanced such that
portions of the program memory can be pro-
tected, while the remainder is unprotected.
1995 Microchip Technology Inc.
DS30390B-page 283
PIC16C7X
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
The format of this data sheet has been changed to be
consistent with other product families. This ensures
that important topics are covered across all PIC16/17
microcontroller families. Here is an overview list of new
features:
All product and device family tables have been updated
for the latest devices and specifications.
TX8/9 (TXSTA<6>) has been changed to TX9 - 9-bit
Transmit Enable bit.
RC8/9 (RCSTA<6>) has been changed to RX9 - 9-bit
Receive Enable bit.
Added the following devices:
PIC16C70
RCD8 (RCSTA<0>) has been changed to RX9D.
TXD8 (TXSTA<0>) has been changed to TX9D.
PIC16C71A
PIC16C72
PIC16C73A
PIC16C74A
The above devices have an on-chip Brown-out Detect
circuit added.
A Brown-out Detect Enable Bit (BODEN) has been
added to the Configuration Word register.
A Brown-out Reset detect bit (BOR) has been added to
the PCON register (for the devices with brown-out
detect circuitry).
A MCLR filter circuit has been added to minimize the
influence of pin state changes to the MCLR line.
DS30390B-page 284
1995 Microchip Technology Inc.
PIC16C7X
APPENDIX E: PIC16/17 MICROCONTROLLERS
TABLE E-1:
PIC16C5X FAMILY OF DEVICES
1995 Microchip Technology Inc.
DS30390B-page 285
PIC16C7X
TABLE E-2:
PIC16C62X FAMILY OF DEVICES
DS30390B-page 286
1995 Microchip Technology Inc.
PIC16C7X
TABLE E-3:
PIC16C6X FAMILY OF DEVICES
1995 Microchip Technology Inc.
DS30390B-page 287
PIC16C7X
TABLE E-4:
PIC16C7X FAMILY OF DEVICES
DS30390B-page 288
1995 Microchip Technology Inc.
PIC16C7X
TABLE E-5:
PIC16C8X FAMILY OF DEVICES
1995 Microchip Technology Inc.
DS30390B-page 289
PIC16C7X
TABLE E-6:
PIC17CXX FAMILY OF DEVICES
DS30390B-page 290
1995 Microchip Technology Inc.
PIC16C7X
E.1
Pin Compatibility
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket (ex.,
PIC16C56 and PIC16C61 devices). Not all devices in
the same package size are pin compatible; for
example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-7:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC16C54, PIC16C54A,
18 pin
PIC16CR54, PIC16CR54A, PIC16CR54B,
PIC16C56, PIC16CR56,
(20 pin)
PIC16C58A, PIC16CR58A, PIC16CR58B,
PIC16C61,
PIC16C620, PIC16C621, PIC16C622,
PIC16C70, PIC16C71, PIC16C71A
PIC16C83, PIC16CR83,
PIC16C84, PIC16C84A, PIC16CR84
PIC16C55, PIC16CR55,
PIC16C57, PIC16CR57A, PIC16CR57B
28 pin
28 pin
40 pin
PIC16C62, PIC16CR62, PIC16C62A, PIC16C63,
PIC16C72, PIC16C73, PIC16C73A
PIC16C64, PIC16CR64, PIC16C64A,
PIC16C65, PIC16C65A,
PIC16C74, PIC16C74A
PIC17C42, PIC17C43, PIC17C44
40 pin
1995 Microchip Technology Inc.
DS30390B-page 291
PIC16C7X
NOTES:
DS30390B-page 292
1995 Microchip Technology Inc.
PIC16C7X
Block Diagrams
INDEX
A/D ............................................................................113
Analog Input Model ...................................................114
Capture .......................................................................73
Compare .....................................................................73
Interrupt Logic ...........................................................134
On-Chip Reset Circuit ...............................................126
PIC16C70 ...................................................................10
PIC16C71 ...................................................................10
PIC16C71A .................................................................10
PIC16C72 ...................................................................11
PIC16C73 ...................................................................12
PIC16C73A .................................................................12
PIC16C74 ...................................................................13
PIC16C74A .................................................................13
PORTC .......................................................................47
PORTD (In I/O Port Mode) .........................................49
PORTD and PORTE as a Parallel Slave Port ............54
PORTE (In I/O Port Mode) .........................................52
PWM ...........................................................................74
RA3:RA0 and RA5 Port Pins ......................................43
RA4/T0CKI Pin ...........................................................44
RB3:RB0 Port Pins .....................................................45
RB7:RB4 Port Pins .....................................................45
SPI Master/Slave Connection .....................................80
A
A/D
Accuracy/Error ......................................................... 118
ADCON0 Register .................................................... 109
ADCON1 Register .................................................... 111
ADIF bit .................................................................... 112
Analog Input Model Block Diagram .......................... 114
Analog-to-Digital Converter ...................................... 109
Block Diagram .......................................................... 113
Configuring Analog Port Pins ................................... 115
Configuring the Interrupt .......................................... 112
Configuring the Module ............................................ 112
Connection Considerations ...................................... 119
Conversion Clock ..................................................... 115
Conversion Time ...................................................... 117
Conversions ............................................................. 116
Converter Characteristics ........ 170, 185, 213, 237, 261
Delays ...................................................................... 114
Effects of a Reset ..................................................... 118
Equations ................................................................. 114
Faster Conversion - Lower Resolution Tradeoff ...... 117
Flowchart of A/D Operation ...................................... 119
GO/DONE bit ........................................................... 112
Internal Sampling Switch (Rss) Impedence ............. 114
Operation During Sleep ........................................... 118
Sampling Requirements ........................................... 114
Sampling Time ......................................................... 114
Source Impedence ................................................... 114
Time Delays ............................................................. 114
Transfer Function ..................................................... 119
Using the CCP Trigger ............................................. 118
Absolute Maximum Ratings ............. 159, 175, 197, 219, 243
ACK ........................................................................ 84, 88, 89
ADCS0 bit ........................................................................ 109
ADCS1 bit ........................................................................ 109
ADDLW Instruction .......................................................... 143
ADDWF Instruction .......................................................... 143
ADIE bit ........................................................................ 32, 34
ADIF bit ...................................................................... 36, 109
ADON bit .......................................................................... 109
ADRES Register .......................................... 26, 28, 109, 112
ALU ...................................................................................... 9
ANDLW Instruction .......................................................... 143
ANDWF Instruction .......................................................... 143
Application Notes
2
SSP (I C Mode) ..........................................................87
SSP (SPI Mode) .........................................................79
Timer0 ........................................................................59
Timer0/WDT Prescaler ...............................................62
Timer1 ........................................................................66
Timer2 ........................................................................69
USART Receive .......................................................101
USART Transmit ........................................................99
Watchdog Timer .......................................................137
BODEN bit ........................................................................122
BOR bit .......................................................................40, 128
BRGH bit ......................................................................93, 95
BSF Instruction .................................................................144
BTFSC Instruction ............................................................144
BTFSS Instruction ............................................................145
C
C bit ....................................................................................30
C Compiler (MP-C) ...................................................153, 157
CALL Instruction ...............................................................145
Capture/Compare/PWM
Capture
Block Diagram ....................................................73
CCP1CON Register ...........................................72
CCP1IF ...............................................................72
CCPR1 ...............................................................72
CCPR1H:CCPR1L .............................................72
Mode ..................................................................72
Prescaler ............................................................73
CCP Timer Resources ................................................71
Compare
Block Diagram ....................................................73
Mode ..................................................................73
Software Interrupt Mode .....................................73
Special Event Trigger .........................................73
Special Trigger Output of CCP1 .........................73
Special Trigger Output of CCP2 .........................73
Interaction of Two CCP Modules ................................71
AN546 ...................................................................... 109
AN552 ........................................................................ 45
AN556 ........................................................................ 41
AN578 ........................................................................ 77
AN594 ........................................................................ 71
Architecture
Harvard ........................................................................ 9
Overview ...................................................................... 9
von Neumann ............................................................... 9
Assembler ........................................................................ 156
B
Baud Rate Error ................................................................. 95
Baud Rate Formula ............................................................ 95
Baud Rates .................................................................. 96, 97
BCF Instruction ................................................................ 144
BF bit ...................................................................... 77, 88, 89
1995 Microchip Technology Inc.
DS30390B-page 293
PIC16C7X
PWM
DECF Instruction ............................................................. 146
DECFSZ Instruction ......................................................... 146
Development Support .................................................. 5, 153
Development Systems ..................................................... 157
Development Tools .......................................................... 153
Diagrams - See Block Diagrams
Block Diagram .................................................... 74
CCP1CON ......................................................... 74
Duty Cycle .......................................................... 74
Example Frequencies and Resolutions ............. 74
Mode .................................................................. 74
Period ................................................................. 74
Digit Carry bit ....................................................................... 9
Direct Addressing .............................................................. 42
Dynamic Data Exchange (DDE) ...................................... 153
Section ....................................................................... 71
Special Event Trigger and A/D Conversions .............. 73
Carry bit ................................................................................ 9
CCP1IE bit ......................................................................... 34
CCP1IF bit .................................................................... 36, 37
CCP2IE bit ......................................................................... 38
CCP2IF bit .......................................................................... 39
CCPR1H Register ........................................................ 28, 71
CCPR1L Register ............................................................... 71
CCPR2H Register ........................................................ 28, 71
CCPR2L Register ......................................................... 28, 71
CCPxM0 bit ........................................................................ 72
CCPxM1 bit ........................................................................ 72
CCPxM2 bit ........................................................................ 72
CCPxM3 bit ........................................................................ 72
CCPxX bit ........................................................................... 72
CCPxY bit ........................................................................... 72
CHS0 bit ........................................................................... 109
CHS1 bit ........................................................................... 109
CKP bit ............................................................................... 78
Clocking Scheme ............................................................... 20
CLRF Instruction .............................................................. 145
CLRW Instruction ............................................................. 145
CLRWDT Instruction ........................................................ 146
Code Examples
Call of a Subroutine in Page 1 from Page 0 ............... 42
Changing Between Capture Prescalers ..................... 73
Changing Prescaler (Timer0 to WDT) ........................ 63
Changing Prescaler (WDT to Timer0) ........................ 63
Doing an A/D Conversion ........................................ 116
I/O Programming ........................................................ 53
Indirect Addressing .................................................... 42
Initializing PORTA ...................................................... 43
Initializing PORTB ...................................................... 45
Initializing PORTC ...................................................... 47
Loading the SSPBUF Register .................................. 79
Saving W register and STATUS in RAM .................. 136
Code Protection ....................................................... 121, 139
COMF Instruction ............................................................. 146
Computed GOTO ............................................................... 41
Configuration Bits ............................................................. 121
Configuration Word .......................................................... 122
CP0 bit ............................................................................. 122
CP1 bit ............................................................................. 122
CREN bit ............................................................................ 94
CS pin ................................................................................ 54
CSRC bit ............................................................................ 93
E
Electrical Characteristics
PIC16C70 ................................................................ 159
PIC16C71 ................................................................ 175
PIC16C71A .............................................................. 159
PIC16C72 ................................................................ 197
PIC16C73 ................................................................ 219
PIC16C73A .............................................................. 243
PIC16C74 ................................................................ 219
PIC16C74A .............................................................. 243
External Brown-out Protection Circuit .............................. 132
External Power-on Reset Circuit ...................................... 132
F
Family of Devices
PIC16C5X ................................................................ 285
PIC16C62X .............................................................. 286
PIC16C6X ................................................................ 287
PIC16C7X ............................................................ 6, 288
PIC16C8X ................................................................ 289
PIC17CXX ............................................................... 290
FERR bit ............................................................................ 94
FOSC0 bit ........................................................................ 122
FOSC1 bit ........................................................................ 122
FSR Register ............................................. 26, 27, 28, 29, 42
Fuzzy Logic Dev. System (fuzzyTECH -MP) ......... 153, 157
G
General Description ............................................................. 5
GIE bit ........................................................................ 32, 133
GO/DONE bit ................................................................... 109
GOTO Instruction ............................................................. 147
Graphs and Charts, PIC16C71 ........................................ 189
I
I/O Ports
PORTA ...................................................................... 43
PORTB ...................................................................... 45
PORTC ...................................................................... 47
PORTD ................................................................ 49, 54
PORTE ...................................................................... 51
Section ....................................................................... 43
I/O Programming Considerations ...................................... 53
2
I C, See Synchronous Serial Port
IBF bit ................................................................................ 54
IDLE_MODE ...................................................................... 92
INCF Instruction ............................................................... 147
INCFSZ Instruction .......................................................... 147
In-Circuit Serial Programming .................................. 121, 139
INDF Register ................................ 25–??, 25, 27, 28, 29, 42
Indirect Addressing ............................................................ 42
Initialization Condition for all Register .............................. 129
Instruction Cycle ................................................................ 20
Instruction Flow/Pipelining ................................................. 20
Instruction Format ............................................................ 141
D
D/A bit ................................................................................ 77
DC bit ................................................................................. 30
DC Characteristics
PIC16C70 ................................................................ 161
PIC16C71 ................................................................ 176
PIC16C71A .............................................................. 161
PIC16C72 ................................................................ 199
PIC16C73 ................................................................ 221
PIC16C73A .............................................................. 245
PIC16C74 ................................................................ 221
PIC16C74A .............................................................. 245
DS30390B-page 294
1995 Microchip Technology Inc.
PIC16C7X
Instruction Set
ADDLW .................................................................... 143
M
MCLR .......................................................................126, 129
Memory
ADDWF .................................................................... 143
ANDLW .................................................................... 143
ANDWF .................................................................... 143
BCF .......................................................................... 144
BSF .......................................................................... 144
BTFSC ..................................................................... 144
BTFSS ..................................................................... 145
CALL ........................................................................ 145
CLRF ........................................................................ 145
CLRW ...................................................................... 145
CLRWDT .................................................................. 146
COMF ...................................................................... 146
DECF ....................................................................... 146
DECFSZ ................................................................... 146
GOTO ...................................................................... 147
INCF ......................................................................... 147
INCFSZ .................................................................... 147
IORLW ..................................................................... 147
IORWF ..................................................................... 148
MOVF ....................................................................... 148
MOVLW ................................................................... 148
MOVWF ................................................................... 148
NOP ......................................................................... 149
OPTION ................................................................... 149
RETFIE .................................................................... 149
RETLW .................................................................... 149
RETURN .................................................................. 150
RLF .......................................................................... 150
RRF .......................................................................... 150
SLEEP ..................................................................... 150
SUBLW .................................................................... 151
SUBWF .................................................................... 151
SWAPF .................................................................... 152
TRIS ......................................................................... 152
XORLW .................................................................... 152
XORWF .................................................................... 152
Section ..................................................................... 141
Summary Table ........................................................ 142
INT Interrupt ..................................................................... 136
INTCON Register ............................................................... 32
INTE bit .............................................................................. 32
INTEDG bit ................................................................. 31, 136
Data Memory ..............................................................22
Program Memory ........................................................21
Program Memory Maps
PIC16C70 ...........................................................21
PIC16C71 ...........................................................21
PIC16C71A ........................................................21
PIC16C72 ...........................................................22
PIC16C73 ...........................................................22
PIC16C73A ........................................................22
PIC16C74 ...........................................................22
PIC16C74A ........................................................22
Register File Maps
PIC16C70 ...........................................................23
PIC16C71 ...........................................................23
PIC16C71A ........................................................23
PIC16C72 ...........................................................24
PIC16C73 ...........................................................24
PIC16C73A ........................................................24
PIC16C74 ...........................................................24
PIC16C74A ........................................................24
MOVF Instruction ..............................................................148
MOVLW Instruction ..........................................................148
MOVWF Instruction ..........................................................148
MPASM Assembler ..................................................153, 156
MP-C C Compiler .............................................................157
MPSIM Software Simulator ......................................153, 157
N
NOP Instruction ................................................................149
O
OBF bit ...............................................................................54
OERR bit ............................................................................94
Opcode .............................................................................141
OPTION Instruction ..........................................................149
OPTION Register ...............................................................31
Orthogonal ............................................................................9
OSC selection ...................................................................121
Oscillator
HS .....................................................................123, 128
LP .....................................................................123, 128
RC ............................................................................123
XT .....................................................................123, 128
Oscillator Configurations ..................................................123
Output of TMR2 ..................................................................69
2
Inter-Integrated Circuit (I C) ............................................... 77
Internal Sampling Switch (Rss) Impedence ..................... 114
Interrupts .......................................................................... 121
A/D ........................................................................... 133
CCP1 ....................................................................... 133
CCP2 ....................................................................... 133
PortB Change .......................................................... 136
PSP .......................................................................... 133
RB7:RB4 Port Change ............................................... 45
Section ..................................................................... 133
SSP .......................................................................... 133
TMR0 ....................................................................... 136
TMR1 Overflow ........................................................ 133
TMR2 Matches PR2 ................................................. 133
USART RX ............................................................... 133
USART TX ............................................................... 133
INTF bit .............................................................................. 32
IORLW Instruction ............................................................ 147
IORWF Instruction ........................................................... 148
IRP bit ................................................................................ 30
P
P bit ....................................................................................77
Packaging
18-Lead CERDIP w/Window ....................................267
18-Lead PDIP ...........................................................270
18-Lead SOIC ...........................................................273
20-Lead SSOP .........................................................275
28-Lead Ceramic w/Window .....................................268
28-Lead PDIP ...........................................................271
28-Lead SOIC ...........................................................274
28-Lead SSOP .........................................................276
40-Lead CERDIP w/Window ....................................269
40-Lead PDIP ...........................................................272
44-Lead MQFP .........................................................278
44-Lead PLCC ..........................................................277
44-Lead TQFP ..........................................................279
Paging, Program Memory ...................................................41
L
Loading of PC .................................................................... 41
1995 Microchip Technology Inc.
DS30390B-page 295
PIC16C7X
Parallel Slave Port ........................................................ 49, 54
PCFG0 bit ........................................................................ 111
PCFG1 bit ........................................................................ 111
PCFG2 bit ........................................................................ 111
PCL Register ........................................25, 26, 27, 28, 29, 41
PCLATH ........................................................................... 129
PCLATH Register .................................25, 26, 27, 28, 29, 41
PCON Register .......................................................... 40, 128
PD bit ................................................................. 30, 126, 128
PICDEM-1 Low-Cost PIC16/17 Demo Board ........... 153, 155
PICDEM-2 Low-Cost PIC16CXX Demo Board ........ 153, 155
PICMASTER Probes ........................................................ 154
PICMASTER System Configuration ................................. 153
PICMASTER RT In-Circuit Emulator ............................. 153
PICSTART Low-Cost Development System ......... 153, 155
PIE1 Register ..................................................................... 34
PIE2 Register ..................................................................... 38
Pin Compatible Devices ................................................... 291
Pin Functions
MCLR/VPP ..........................................14, 15, 16, 17, 18
OSC1/CLKIN ......................................14, 15, 16, 17, 18
OSC2/CLKOUT ..................................14, 15, 16, 17, 18
RA0/AN0 ............................................14, 15, 16, 17, 18
RA1/AN1 ............................................14, 15, 16, 17, 18
RA2/AN2 ............................................14, 15, 16, 17, 18
RA3/AN3/VREF ...................................14, 15, 16, 17, 18
RA4/T0CKI .........................................14, 15, 16, 17, 18
RA5/AN4/SS .................................................. 16, 17, 18
RB0/INT .............................................14, 15, 16, 17, 18
RB1 ....................................................14, 15, 16, 17, 18
RB2 ....................................................14, 15, 16, 17, 18
RB3 ....................................................14, 15, 16, 17, 18
RB4 ....................................................14, 15, 16, 17, 18
RB5 ....................................................14, 15, 16, 17, 18
RB6 ....................................................14, 15, 16, 17, 18
RB7 ....................................................14, 15, 16, 17, 18
RC0/T1OSO/T1CKI ....................................... 16, 17, 19
RC1/T1OSI ................................................................ 16
RC1/T1OSI/CCP2 ................................................ 17, 19
RC2/CCP1 ..................................................... 16, 17, 19
RC3/SCK/SCL ............................................... 16, 17, 19
RC4/SDI/SDA ................................................ 16, 17, 19
RC5/SDO ....................................................... 16, 17, 19
RC6 ............................................................................ 16
RC6/TX/CK ............................................17, 19, 93–107
RC7 ............................................................................ 16
RC7/RX/DT ............................................17, 19, 93–107
RD0/PSP0 .................................................................. 19
RD1/PSP1 .................................................................. 19
RD2/PSP2 .................................................................. 19
RD3/PSP3 .................................................................. 19
RD4/PSP4 .................................................................. 19
RD5/PSP5 .................................................................. 19
RD6/PSP6 .................................................................. 19
RD7/PSP7 .................................................................. 19
RE0/RD/AN5 .............................................................. 19
RE1/WR/AN6 ............................................................. 19
RE2/CS/AN7 .............................................................. 19
VDD ....................................................14, 15, 16, 17, 19
VSS .....................................................14, 15, 16, 17, 19
Pinout Descriptions
PIC16C73A ................................................................ 17
PIC16C74 .................................................................. 18
PIC16C74A ................................................................ 18
PIR1 Register .................................................................... 36
PIR2 Register .................................................................... 39
POP ................................................................................... 41
POR ......................................................................... 127, 128
Oscillator Start-up Timer (OST) ....................... 121, 127
Power Control Register (PCON) .............................. 128
Power-on Reset (POR) ............................ 121, 127, 129
Power-up Timer (PWRT) ................................. 121, 127
Power-Up-Timer (PWRT) ........................................ 127
Time-out Sequence ................................................. 128
Time-out Sequence on Power-up ............................ 131
TO .................................................................... 126, 128
POR bit ...................................................................... 40, 128
Port RB Interrupt .............................................................. 136
PORTA ............................................................................ 129
PORTA Register .............................................. 25, 26, 28, 43
PORTB ............................................................................ 129
PORTB Register .............................................. 25, 26, 28, 45
PORTC ............................................................................ 129
PORTC Register .................................................... 26, 28, 47
PORTD ............................................................................ 129
PORTD Register .......................................................... 28, 49
PORTE ............................................................................ 129
PORTE Register .......................................................... 28, 51
Power-down Mode (SLEEP) ............................................ 138
PR2 Register ............................................................... 29, 69
Prescaler, Switching Between Timer0 and WDT ............... 63
PRO MATE Universal Programmer ...................... 153, 155
Probes ............................................................................. 154
Program Branches ............................................................... 9
Program Memory
Paging ....................................................................... 41
Program Memory Maps
PIC16C70 .................................................................. 21
PIC16C71 .................................................................. 21
PIC16C71A ................................................................ 21
PIC16C72 .................................................................. 22
PIC16C73 .................................................................. 22
PIC16C73A ................................................................ 22
PIC16C74 .................................................................. 22
PIC16C74A ................................................................ 22
Program Verification ........................................................ 139
PS0 bit ............................................................................... 31
PS1 bit ............................................................................... 31
PS2 bit ............................................................................... 31
PSA bit ............................................................................... 31
PSPIE bit ..................................................................... 35, 54
PSPIF bit ...................................................................... 37, 54
PSPMODE bit ........................................................ 49, 51, 54
PUSH ................................................................................. 41
PWRTE bit ....................................................................... 122
R
R/W bit ............................................................. 84, 88, 89, 90
R/W bit ............................................................................... 77
RBIE bit .............................................................................. 32
RBIF bit ................................................................ 32, 45, 136
RBPU bit ............................................................................ 31
RC Oscillator ............................................................ 125, 128
RCIE bit ............................................................................. 35
RCIF bit .............................................................................. 37
RCSTA Register ................................................................ 94
RCV_MODE ...................................................................... 92
PIC16C70 ............................................................ 14, 15
PIC16C71 ............................................................ 14, 15
PIC16C71A .......................................................... 14, 15
PIC16C72 .................................................................. 16
PIC16C73 .................................................................. 17
DS30390B-page 296
1995 Microchip Technology Inc.
PIC16C7X
RD pin ................................................................................ 54
Read-Modify-Write ............................................................. 53
Register File ....................................................................... 22
Registers
SSPM2 bit ...........................................................................78
SSPM3 bit ...........................................................................78
SSPOV bit ....................................................................78, 88
SSPSR Register .................................................................88
SSPSTAT Register ...........................................27, 29, 77, 89
Stack ...................................................................................41
Overflows ....................................................................41
Underflow ...................................................................41
STATUS Register ...............................................................30
SUBLW Instruction ...........................................................151
SUBWF Instruction ...........................................................151
SWAPF Instruction ...........................................................152
SYNC bit .............................................................................93
Synchronous Serial Port
Initialization Conditions ............................................ 129
Maps
PIC16C70 .......................................................... 23
PIC16C71 .......................................................... 23
PIC16C71A ........................................................ 23
PIC16C72 .......................................................... 24
PIC16C73 .......................................................... 24
PIC16C73A ........................................................ 24
PIC16C74 .......................................................... 24
PIC16C74A ........................................................ 24
Reset Conditions ...................................................... 129
Summary .............................................................. 25–28
Reset ........................................................................ 121, 126
Reset Conditions for Special Registers ........................... 129
RETFIE Instruction ........................................................... 149
RETLW Instruction ........................................................... 149
RETURN Instruction ........................................................ 150
RLF Instruction ................................................................. 150
RP0 bit ......................................................................... 22, 30
RP1 bit ............................................................................... 30
RRF Instruction ................................................................ 150
RX9 bit ............................................................................... 94
RX9D bit ............................................................................. 94
2
I C
Addressing .........................................................88
2
Addressing I C Devices .....................................84
Arbitration ...........................................................86
Block Diagram ....................................................87
Clock Synchronization ........................................86
Combined Format ...............................................85
2
I C Operation .....................................................87
2
I C Overview ......................................................83
Initiating and Terminating Data Transfer ............83
Master-Receiver Sequence ................................85
Master-Transmitter Sequence ............................85
Multi-master ........................................................86
Multi-master Mode ..............................................91
Reception ...........................................................89
Slave Mode ........................................................88
START ..........................................................83, 90
START (S) ..........................................................91
STOP ............................................................83, 84
STOP (P) ............................................................91
Transfer Acknowledge ........................................84
Transmission ......................................................90
SPI
S
S bit .................................................................................... 77
SCL .............................................................................. 88, 91
SDA .............................................................................. 90, 91
Serial Communication Interface (SCI) Module, See USART
Serial Peripheral Interface (SPI) ........................................ 77
Services
One-Time-Programmable (OTP) ................................. 7
Quick-Turnaround-Production (QTP) ........................... 7
Serialized Quick-Turnaround Production (SQTP) ........ 7
SLEEP ..................................................................... 121, 126
SLEEP Instruction ............................................................ 150
Software Simulator (MPSIM) ........................................... 157
SPBRG Register ................................................................ 29
Special Event Trigger ....................................................... 118
Special Features of the CPU ........................................... 121
Special Function Registers
PIC16C70 .................................................................. 25
PIC16C71 .................................................................. 25
PIC16C71A ................................................................ 25
PIC16C72 .................................................................. 26
PIC16C73 .................................................................. 28
PIC16C73A ................................................................ 28
PIC16C74 .................................................................. 28
PIC16C74A ................................................................ 28
Special Function Registers, Section .................................. 25
SPEN bit ............................................................................ 94
SPI, See Synchronous Serial Port
SREN bit ............................................................................ 94
SS bit ................................................................................. 81
SSPADD Register .................................................. 27, 29, 88
SSPBUF Register ........................................................ 28, 88
SSPCON Register ................................................. 28, 78, 89
SSPEN bit .......................................................................... 78
SSPIE bit ............................................................................ 34
SSPIF bit .......................................................... 36, 37, 88, 89
SSPM0 bit .......................................................................... 78
SSPM1 bit .......................................................................... 78
Block Diagram ....................................................79
Block Diagram of Master/Slave Connection .......80
Master Mode ......................................................80
Serial Clock ........................................................79
Serial Data In ......................................................79
Serial Data Out ...................................................79
Slave Select .......................................................79
SPI Clock ............................................................80
SPI Mode ............................................................79
SSPBUF Register ...............................................80
SSPSR Register .................................................80
Synchronous Serial Port Module ........................................77
T
T0CS bit ..............................................................................31
T0IE bit ...............................................................................32
T0IF bit ...............................................................................32
T1CKPS0 bit .......................................................................65
T1CKPS1 bit .......................................................................65
T1CON Register .................................................................65
T1OSCEN bit ......................................................................65
T1SYNC bit .........................................................................65
T2CKPS0 bit .......................................................................70
T2CKPS1 bit .......................................................................70
T2CON Register .................................................................70
TAD ...................................................................................115
Timer Modules, Overview ...................................................57
Timer0
RTCC ........................................................................129
1995 Microchip Technology Inc.
DS30390B-page 297
PIC16C7X
Timers
Timer0
USART Asynchronous Master Transmission .......... 100
USART Asynchronous Reception ........................... 101
USART RX Pin Sampling .......................................... 98
USART Synchronous Receive ........................ 236, 260
USART Synchronous Reception ............................. 106
USART Synchronous Transmission ........ 104, 236, 260
Wake-up from Sleep via Interrupt ............................ 138
Watchdog Timer ...................... 168, 183, 206, 229, 253
TMR0 Register ................................................................... 28
TMR1CS bit ....................................................................... 65
TMR1H Register .......................................................... 26, 28
TMR1IE bit ......................................................................... 34
TMR1IF bit ................................................................... 36, 37
TMR1L Register ........................................................... 26, 28
TMR1ON bit ....................................................................... 65
TMR2 Register ............................................................. 26, 28
TMR2IE bit ......................................................................... 34
TMR2IF bit ................................................................... 36, 37
TMR2ON bit ....................................................................... 70
TO bit ................................................................................. 30
TOUTPS0 bit ..................................................................... 70
TOUTPS1 bit ..................................................................... 70
TOUTPS2 bit ..................................................................... 70
TOUTPS3 bit ..................................................................... 70
TRIS Instruction ............................................................... 152
TRISA Register ................................................ 25, 27, 29, 43
TRISB Register ................................................ 25, 27, 29, 45
TRISC Register ...................................................... 27, 29, 47
TRISD Register ...................................................... 25, 29, 49
TRISE Register ............................................................ 29, 51
TRMT bit ............................................................................ 93
Two’s Complement .............................................................. 9
TX9 bit ............................................................................... 93
TX9D bit ............................................................................. 93
TXEN bit ............................................................................ 93
TXIE bit .............................................................................. 35
TXIF bit .............................................................................. 37
TXSTA Register ................................................................. 93
Block Diagram .................................................... 59
External Clock .................................................... 61
External Clock Timing ........................................ 61
Increment Delay ................................................. 61
Interrupt .............................................................. 59
Interrupt Timing .................................................. 60
Overview ............................................................ 57
Prescaler ............................................................ 62
Prescaler Block Diagram ................................... 62
Section ............................................................... 59
Switching Prescaler Assignment ........................ 63
Synchronization ................................................. 61
T0CKI ................................................................. 61
T0IF .................................................................. 136
Timing ................................................................ 59
TMR0 Interrupt ................................................. 136
Timer1
Asynchronous Counter Mode ............................ 67
Block Diagram .................................................... 66
Capacitor Selection ............................................ 67
External Clock Input ........................................... 66
External Clock Input Timing ............................... 67
Operation in Timer Mode ................................... 66
Oscillator ............................................................ 67
Overview ............................................................ 57
Prescaler ...................................................... 66, 68
Resetting of Timer1 Registers ........................... 68
Resetting Timer1 using a CCP Trigger Output .. 68
Synchronized Counter Mode ............................. 66
T1CON ............................................................... 65
TMR1H ............................................................... 67
TMR1L ............................................................... 67
Timer2
Block Diagram .................................................... 69
Module ............................................................... 69
Overview ............................................................ 57
Postscaler .......................................................... 69
Prescaler ............................................................ 69
T2CON ............................................................... 70
U
UA bit ................................................................................. 77
Universal Synchronous Asynchronous Receiver Transmitter
(USART) ............................................................................ 93
USART
Timing Diagrams
A/D Conversion ........................172, 187, 215, 239, 263
Brown-out Reset ..............................127, 168, 206, 253
Capture/Compare/PWM ...........................208, 231, 255
CLKOUT and I/O ......................167, 182, 205, 228, 252
External Clock Timing ..............166, 181, 204, 226, 250
Asynchronous Mode .................................................. 99
Asynchronous Receiver ........................................... 101
Asynchronous Reception ......................................... 102
Asynchronous Transmission ................................... 100
Asynchronous Transmitter ......................................... 99
Baud Rate Generator (BRG) ..................................... 95
Receive Block Diagram ........................................... 101
Sampling .................................................................... 98
Synchronous Master Mode ...................................... 103
Synchronous Master Reception .............................. 105
Synchronous Master Transmission ......................... 103
Synchronous Slave Mode ........................................ 107
Synchronous Slave Reception ................................ 107
Synchronous Slave Transmit ................................... 107
Transmit Block Diagram ............................................ 99
UV Erasable Devices ........................................................... 7
2
I C Bus Data ............................................211, 235, 259
2
I C Bus Start/Stop bits .............................210, 234, 258
2
I C Clock Synchronization ......................................... 86
2
I C Data Transfer Wait State ..................................... 84
2
I C Multi-Master Arbitration ........................................ 86
2
I C Reception ............................................................. 89
2
I C Transmission ....................................................... 90
Parallel Slave Port ........................................... 232, 256
Power-up Timer .......................168, 183, 206, 229, 253
Reset ........................................168, 183, 206, 229, 253
SPI Mode .................................................209, 233, 257
SPI Mode Timing (No SS Control) ............................. 81
SPI Mode Timing (SS Control) ................................... 81
Start-up Timer ..........................168, 183, 206, 229, 253
Time-out Sequence .................................................. 131
Timer0 ................................59, 169, 184, 207, 230, 254
Timer0 Interrupt Timing .............................................. 60
Timer0 with External Clock ........................................ 61
Timer1 ......................................................207, 230, 254
W
W Register
ALU .............................................................................. 9
Wake-up from SLEEP ...................................................... 138
Watchdog Timer (WDT) ........................... 121, 126, 129, 137
WCOL bit ........................................................................... 78
DS30390B-page 298
1995 Microchip Technology Inc.
PIC16C7X
WDT ................................................................................. 129
Block Diagram .......................................................... 137
Period ....................................................................... 137
Programming Considerations .................................. 137
Timeout .................................................................... 129
WDTE bit .......................................................................... 122
Word ................................................................................ 122
WR pin ............................................................................... 54
Figure 4-9:
Figure 4-10:
Figure 4-11:
Status Register (Address 03h, 83h)...........30
OPTION Register (Address 81h)...............31
INTCON Register for PIC16C70/71/71A
(Address 0Bh, 8Bh) ...................................32
INTCON Register for PIC16C72/73/
73A/74/74A (Address 0Bh, 8Bh)................33
PIE1 Register PIC16C72 (Address 8Ch)...34
PIE1 Register PIC16C73/73A/74/74A
Figure 4-12:
Figure 4-13:
Figure 4-14:
(Address 8Ch)............................................35
PIR1 Register PIC16C72 (Address 0Ch)...36
PIR1 Register PIC16C73/73A/74/74A
X
Figure 4-15:
Figure 4-16:
XMIT_MODE ...................................................................... 92
XORLW Instruction .......................................................... 152
XORWF Instruction .......................................................... 152
(Address 0Ch)............................................37
PIE2 Register (Address 8Dh) ....................38
PIR2 Register (Address 0Dh) ....................39
PCON Register (Address 8Eh)..................40
Loading of PC In Different Situations.........41
Direct/Indirect Addressing..........................42
Block Diagram of RA3:RA0 and RA5 Pins 43
Block Diagram of RA4/T0CKI Pin..............44
Block Diagram of RB3:RB0 Pins ...............45
Block Diagram of RB7:RB4 Pins ...............45
PORTC Block Diagram (Peripheral Output
Override)....................................................47
PORTD Block Diagram (in I/O Port Mode) 49
TRISE Register (Address 89h) ..................51
PORTE Block Diagram (in I/O Port Mode) 52
Successive I/O Operation..........................53
PORTD and PORTE Block Diagram
Figure 4-17:
Figure 4-18:
Figure 4-19:
Figure 4-20:
Figure 4-21:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Z
Z bit .................................................................................... 30
Zero bit ................................................................................. 9
LIST OF EXAMPLES
Example 3-1: Instruction Pipeline Flow........................... 20
Example 4-1: Call of a Subroutine in Page 1 from
Page 0...................................................... 42
Example 4-2: Indirect Addressing................................... 42
Example 5-1: Initializing PORTA .................................... 43
Figure 5-6:
Figure 5-7:
Figure 5-8:
Figure 5-9:
Figure 5-10:
Example 5-2:
Initializing PORTB ................................... 45
Example 5-3: Initializing PORTC .................................... 47
Example 5-4: Read-Modify-Write Instructions on an
I/O Port..................................................... 53
Example 7-1: Changing Prescaler (Timer0→WDT)........ 63
Example 7-2: Changing Prescaler (WDT→Timer0)........ 63
Example 8-1: Reading a 16-bit Free-Running Timer...... 67
Example 10-1: Changing Between Capture Prescalers ... 73
Example 11-1: Loading the SSPBUF (SSPSR)
Register .................................................... 79
Example 12-1: Calculating Baud Rate Error..................... 95
Equation 13-1: A/D Minimum Charging Time ................. 114
Example 13-1: Calculating the Minimum Required
Sample Time .......................................... 114
(Parallel Slave Port)...................................54
Timer0 Block Diagram ...............................59
Timer0 Timing: Internal Clock/No
Prescale.....................................................59
Timer0 Timing: Internal Clock/
Prescale 1:2...............................................60
Timer0 Interrupt Timing .............................60
Timer0 Timing with External Clock ............61
Block Diagram of the Timer0/WDT
Prescaler....................................................62
T1CON: Timer1 Control Register
(Address 10h) ............................................65
Timer1 Block Diagram ...............................66
Timer2 Block Diagram ...............................69
T2CON: Timer2 Control Register
(Address 12h) ............................................70
CCP1CON Register (Address 17h)/
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Example 13-2: Doing an A/D Conversion
(PIC16C70/71/71A)................................ 116
Example 13-3: Doing an A/D Conversion
Figure 8-1:
Figure 8-2:
Figure 9-1:
Figure 9-2:
(PIC16C72/73/73A/74/74A).................... 116
Example 13-4: 4-bit vs. 8-bit Conversion Times............. 117
Example 14-1: Saving STATUS and W Registers in RAM
(PIC16C70/71/71A)................................ 136
Figure 10-1:
Example 14-2: Saving STATUS and W Registers in RAM
(PIC16C72/73/73A/74/74A).................... 136
CCP2CON Register (Address 1Dh)...........72
Capture Mode Operation Block Diagram...73
Compare Mode Operation Block Diagram.73
Simplified PWM Block Diagram.................74
SSPSTAT: Sync Serial Port Status Register
(Address 94h) ............................................77
SSPCON: Sync Serial Port Control Register
(Address 14h) ............................................78
SSP Block Diagram (SPI Mode)................79
SPI Master/Slave Connection....................80
SPI Mode Timing (Master Mode or Slave
Mode w/o SS Control)................................81
SPI Mode Timing (Slave Mode with
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 11-1:
LIST OF FIGURES
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 4-1:
PIC16C70/71/71A Block Diagram............. 10
PIC16C72 Block Diagram ......................... 11
PIC16C73/73A Block Diagram.................. 12
PIC16C74/74A Block Diagram.................. 13
Clock/Instruction Cycle.............................. 20
PIC16C70 Program Memory Map and
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Stack ......................................................... 21
PIC16C71/71A Program Memory Map
and Stack .................................................. 21
PIC16C72 Program Memory Map and
Stack ......................................................... 22
PIC16C73/73A/74/74A Program Memory
Map and Stack .......................................... 22
PIC16C70/71 Register File Map ............... 23
PIC16C71A Register File Map.................. 23
PIC16C72 Register File Map .................... 24
PIC16C73/73A/74/74A Register File
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 11-6:
SS Control) ................................................81
Start and Stop Conditions..........................83
7-bit Address Format .................................84
Figure 11-7:
Figure 11-8:
Figure 11-9:
2
I C 10-bit Address Format.........................84
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 11-10: Slave-Receiver Acknowledge....................84
Figure 11-11: Data Transfer Wait State ...........................84
Figure 11-12: Master-transmitter Sequence ....................85
Figure 11-13: Master-receiver Sequence.........................85
Map ........................................................... 24
1995 Microchip Technology Inc.
DS30390B-page 299
PIC16C7X
Figure 11-14: Combined Format ..................................... 85
Figure 11-15: Multi-master Arbitration (Two Masters)..... 86
Figure 11-16: Clock Synchronization............................... 86
Figure 14-16: External Brown-out Protection Circuit 1.. 132
Figure 14-17: External Brown-out Protection Circuit 2.. 132
Figure 14-18: Interrupt Logic for PIC16C70/71/71A...... 134
Figure 14-19: Interrupt Logic for PIC16C72.................. 134
Figure 14-20: Interrupt Logic for PIC16C73/73A........... 134
Figure 14-21: Interrupt Logic for PIC16C74/74A........... 135
Figure 14-22: INT Pin Interrupt Timing.......................... 135
Figure 14-23: Watchdog Timer Block Diagram............. 137
Figure 14-24: Summary of Watchdog Timer Registers. 137
Figure 14-25: Wake-up from Sleep Through Interrupt .. 138
Figure 14-26: Typical In-Circuit Serial Programming
2
Figure 11-17: SSP Block Diagram (I C Mode)................ 87
2
Figure 11-18: I C Waveforms for Reception
(7-bit Address)........................................... 89
2
Figure 11-19: I C Waveforms for Transmission
(7-bit Address)........................................... 90
Figure 11-20: Operation of the I2C Module in IDLE_MODE,
RCV_MODE or XMIT_MODE ................... 92
Figure 12-1:
TXSTA: Transmit Status and Control
Register (Address 98h) ............................. 93
RCSTA: Receive Status and Control
Connection.............................................. 139
Figure 12-2:
Figure 15-1:
Figure 16-1:
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
General Format for Instructions.............. 141
PICMASTER System Configuration ....... 153
Load Conditions...................................... 165
External Clock Timing............................. 166
CLKOUT and I/O Timing......................... 167
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing ......... 168
Brown-out Reset Timing ......................... 168
Timer0 Clock Timings............................. 169
A/D Conversion Timing........................... 172
Load Conditions...................................... 180
External Clock Timing............................. 181
CLKOUT and I/O Timing......................... 182
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing ......... 183
Timer0 Clock Timings............................. 184
A/D Conversion Timing........................... 187
Typical RC Oscillator Frequency vs.
Temperature ........................................... 189
Typical RC Oscillator Frequency vs.
VDD ......................................................... 189
Typical RC Oscillator Frequency vs.
VDD ......................................................... 189
Typical RC Oscillator Frequency vs. VDD 190
Typical Ipd vs. VDD Watchdog Timer
Disabled 25°C......................................... 190
Typical Ipd vs. VDD Watchdog Timer
Register (Address 18h)............................. 94
RX Pin Sampling Scheme (BRGH = 0)..... 98
RX Pin Sampling Scheme (BRGH = 1)..... 98
RX Pin Sampling Scheme (BRGH = 1)..... 98
USART Transmit Block Diagram............... 99
Asynchronous Master Transmission....... 100
Asynchronous Master Transmission
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Figure 12-8:
Figure 17-5:
Figure 17-6:
Figure 17-7:
Figure 19-1:
Figure 19-2:
Figure 19-3:
Figure 19-4:
(Back to Back)......................................... 100
USART Receive Block Diagram.............. 101
Figure 12-9:
Figure 12-10: Asynchronous Reception ........................ 101
Figure 12-11: Synchronous Transmission..................... 104
Figure 12-12: Synchronous Transmission
(Through TXEN)...................................... 104
Figure 12-13: Synchronous Reception (Master Mode,
SREN)..................................................... 106
Figure 19-5:
Figure 19-6:
Figure 20-1:
Figure 13-1:
Figure 13-2:
Figure 13-3:
Figure 13-4:
ADCON0 Register, PIC16C70/71/71A
(Address 08h).......................................... 109
ADCON0 Register, PIC16C72/73/73A/74/
74A (Address 1Fh).................................. 110
ADCON1 Register for PIC16C70/71/71A
(Address 88h).......................................... 110
ADCON1 Register, PIC16C72/73/73A/74/
74A (Address 9Fh).................................. 111
A/D Block Diagram, PIC16C70/71/71A... 112
A/D Block Diagram, PIC16C72/73/73A/74/
74A.......................................................... 113
Analog Input Model ................................. 114
A/D Transfer Function............................. 119
Flowchart of A/D Operation..................... 119
Configuration Word for PIC16C71 .......... 121
Configuration Word for PIC16C70/71A... 122
Configuration Word for PIC16C73/74 ..... 122
Configuration Word for PIC16C72/73A/
Figure 20-2:
Figure 20-3:
Figure 20-4:
Figure 20-5:
Figure 13-5:
Figure 13-6:
Figure 20-6:
Figure 20-7:
Figure 20-8:
Figure 20-9:
Figure 13-7:
Figure 13-8:
Figure 13-9:
Figure 14-1:
Figure 14-2:
Figure 14-3:
Figure 14-4:
Enabled 25°C.......................................... 190
Maximum Ipd vs. VDD Watchdog
Disabled.................................................. 191
Maximum Ipd vs. VDD Watchdog
Enabled................................................... 191
Vth (Input Threshold Voltage) of I/O Pins vs.
VDD ......................................................... 191
74A.......................................................... 123
Crystal/Ceramic Resonator Operation
(HS, XT or LP OSC Configuration) ......... 123
External Clock Input Operation
(HS, XT or LP OSC Configuration) ......... 123
External Parallel Resonant Crystal Oscillator
Circuit...................................................... 125
External Series Resonant Crystal Oscillator
Circuit...................................................... 125
RC Oscillator Mode................................. 125
Figure 20-10: VIH, VIL of MCLR, T0CKI and OSC1 (in RC
Mode) vs. VDD ........................................ 192
Figure 20-11: VTH (Input Threshold Voltage) of OSC1 Input
(in XT, HS, and LP Modes) vs. VDD........ 192
Figure 20-12: Typical IDD vs. Freq (Ext Clock, 25°C).... 193
Figure 20-13: Maximum, IDD vs. Freq (Ext Clock, -40° to
+85°C) .................................................... 193
Figure 20-14: Maximum Idd vs. Freq with A/D Off
(Ext Clock, -55° to +125°C) .................... 194
Figure 14-5:
Figure 14-6:
Figure 14-7:
Figure 14-8:
Figure 14-9:
Figure 20-15: WDT Timer Time-out Period vs. VDD...... 194
Figure 20-16: Transconductance (gm) of HS Oscillator vs.
VDD ......................................................... 194
Figure 14-10: Simplified Block Diagram of On-chip Reset
Circuit...................................................... 126
Figure 14-11: Brown-out Situations............................... 127
Figure 14-12: Time-out Sequence on Power-up
(MCLR not Tied to VDD): Case 1............. 131
Figure 14-13: Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2........... 131
Figure 14-14: Time-out Sequence on Power-up
(MCLR Tied to VDD)................................ 131
Figure 14-15: External Power-on Reset Circuit (for Slow
VDD Power-up)........................................ 132
Figure 20-17: Transconductance (gm) of LP Oscillator vs.
VDD ......................................................... 195
Figure 20-18: Transconductance (gm) of XT Oscillator vs.
VDD ......................................................... 195
Figure 20-19: IOH vs. VOH, VDD = 3V.......................... 195
Figure 20-20: IOH vs. VOH, VDD = 5V.......................... 195
Figure 20-21: IOL vs. VOL, VDD = 3V ........................... 196
Figure 20-22: IOL vs. VOL, VDD = 5V ........................... 196
DS30390B-page 300
1995 Microchip Technology Inc.
PIC16C7X
Figure 21-1:
Figure 21-2:
Figure 21-3:
Figure 21-4:
Load Conditions ...................................... 203
External Clock Timing ............................. 204
CLKOUT and I/O Timing......................... 205
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing.......... 206
Brown-out Reset Timing.......................... 206
Timer0 and Timer1 Clock Timings .......... 207
Capture/Compare/PWM Timings
Table 5-2:
Summary of Registers Associated with
PORTA ......................................................44
PORTB Functions......................................46
Summary of Registers Associated with
PORTB ......................................................46
PORTC Functions......................................48
Summary of Registers Associated with
PORTC ......................................................48
PORTD Functions......................................49
Summary of Registers Associated with
PORTD ......................................................50
PORTE Functions......................................52
Summary of Registers Associated with
PORTE ......................................................52
Registers Associated with Parallel Slave
Port ............................................................55
Registers Associated with Timer0,
Table 5-3:
Table 5-4:
Figure 21-5:
Figure 21-6:
Figure 21-7:
Table 5-5:
Table 5-6:
(CCP1) .................................................... 208
SPI Mode Timing..................................... 209
Table 5-7:
Table 5-8:
Figure 21-8:
Figure 21-9:
2
I C Bus Start/Stop Bits Timing................ 210
2
Figure 21-10: I C Bus Data Timing ............................... 211
Figure 21-11: A/D Conversion Timing ........................... 215
Figure 23-1:
Figure 23-2:
Figure 23-3:
Figure 23-4:
Table 5-9:
Table 5-10:
Load Conditions ...................................... 225
External Clock Timing ............................. 226
CLKOUT and I/O Timing......................... 228
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing.......... 229
Timer0 and Timer1 Clock Timings .......... 230
Capture/Compare/PWM Timings (CCP1 and
CCP2) ..................................................... 231
Parallel Slave Port Timing for the PIC16C74
Only......................................................... 232
SPI Mode Timing..................................... 233
Table 5-11:
Table 7-1:
Table 7-2:
Table 8-1:
Table 8-2:
Table 9-1:
PIC16C70/71/71A......................................63
Registers Associated with Timer0,
PIC16C72/73/73A/74/74A .........................63
Capacitor Selection for the Timer1
Figure 23-5:
Figure 23-6:
Figure 23-7:
Oscillator....................................................67
Registers Associated with Timer1 as a
Timer/Counter............................................68
Registers Associated with Timer2 as a
Timer/Counter............................................70
CCP Mode - Timer Resource ....................71
Interaction of Two CCP Modules...............71
PWM Frequency vs. Resolution at
20 MHz ......................................................74
Example PWM Frequencies and Resolutions
at 20 MHz ..................................................74
Registers Associated with Capture and
Timer1........................................................75
Registers Associated with Compare and
Timer1........................................................75
Registers Associated with PWM and
Figure 23-8:
Figure 23-9:
2
I C Bus Start/Stop Bits Timing................ 234
2
Figure 23-10: I C Bus Data Timing ............................... 235
Figure 23-11: USART Module: Synchronous Transmission
(Master/Slave) Timing............................. 236
Figure 23-12: USART Module: Synchronous Receive
(Master/Slave) Timing............................. 236
Table 10-1:
Table 10-2:
Table 10-3:
Figure 23-13: A/D Conversion Timing ........................... 239
Table 10-4:
Table 10-5:
Table 10-6:
Table 10-7:
Figure 25-1:
Figure 25-2:
Figure 25-3:
Figure 25-4:
Load Conditions ...................................... 249
External Clock Timing ............................. 250
CLKOUT and I/O Timing......................... 252
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Timing.......... 253
Brown-out Reset Timing.......................... 253
Timer0 and Timer1 Clock Timings .......... 254
Capture/Compare/PWM Timings (CCP1 and
CCP2) ..................................................... 255
Parallel Slave Port Timing for the PIC16C74A
Only......................................................... 256
Figure 25-5:
Figure 25-6:
Figure 25-7:
Timer2........................................................76
Registers Associated with SPI Operation..82
Table 11-1:
Table 11-2:
Table 11-3:
Table 11-4:
Table 12-1:
Table 12-2:
2
I C Bus Terminology..................................83
Figure 25-8:
Figure 25-9:
Data Transfer Received Byte Actions........88
2
Registers Associated with I C Operation...91
SPI Mode Timing..................................... 257
Baud Rate Formula....................................95
Registers Associated with Baud Rate
Generator...................................................95
Baud Rates for Synchronous Mode...........96
Baud Rates for Asynchronous Mode
2
Figure 25-10: I C Bus Start/Stop Bits Timing................ 258
Figure 25-11: I C Bus Data Timing ............................... 259
Figure 25-12: USART Module: Synchronous Transmission
(Master/Slave) Timing............................. 260
2
Table 12-3:
Table 12-4:
Figure 25-13: USART Module: Synchronous Receive
(Master/Slave) Timing............................. 260
Figure 25-14: A/D Conversion Timing ........................... 263
(BRGH = 0)................................................96
Baud Rates for Asynchronous Mode
Table 12-5:
Table 12-6:
Table 12-7:
Table 12-8:
Table 12-9:
Table 12-10:
Table 12-11:
Table 13-1:
Table 13-2:
(BRGH = 1)................................................97
Registers Associated with Asynchronous
Transmission ...........................................100
Registers Associated with Asynchronous
Reception.................................................102
Registers Associated with Synchronous
Master Transmission ...............................104
Registers Associated with Synchronous
Master Reception.....................................105
Registers Associated with Synchronous
Slave Transmission .................................108
Registers Associated with Synchronous
Slave Reception.......................................108
TAD vs. Device Operating Frequencies,
PIC16C71 ................................................115
TAD vs. Device Operating Frequencies,
PIC16C70/71A/72/73/73A/74/74A...........115
LIST OF TABLES
Table 1-1:
Table 3-1:
Table 3-2:
Table 3-3:
Table 3-4:
Table 3-5:
Table 4-1:
PIC16C7X Family of Devices...................... 6
PIC16C70/71A Pinout Description............ 14
PIC16C71 Pinout Description ................... 15
PIC16C72 Pinout Description ................... 16
PIC16C73/73A Pinout Description............ 17
PIC16C74/74A Pinout Description............ 18
PIC16C70/71/71A Special Function Register
Summary................................................... 25
PIC16C72 Special Function Register
Summary................................................... 26
PIC16C73/73A/74/74A Special Function
Register Summary .................................... 28
PORTA Functions ..................................... 44
Table 4-2:
Table 4-3:
Table 5-1:
1995 Microchip Technology Inc.
DS30390B-page 301
PIC16C7X
Table 13-3:
Summary of A/D Registers, PIC16C70/71/
Table 19-7:
A/D Converter Characteristics:
71A.......................................................... 120
Summary of A/D Registers, PIC16C72... 120
Summary of A/D Registers, PIC16C73/73A/
74/74A..................................................... 120
Ceramic Resonators PIC16C71.............. 124
Capacitor Selection for Crystal Oscillator for
PIC16C71................................................ 124
Ceramic Resonators PIC16C70/71A/72/73/
73A/74/74A ............................................. 124
Capacitor Selection for Crystal Oscillator for
PIC16C70/71A/72/73/73A/74/74A .......... 124
Time-out in Various Situations, PIC16C71/
73/74 ....................................................... 128
Time-out in Various Situations, PIC16C70/
71A/72/73A/74A...................................... 128
Status Bits and Their Significance,
PIC16LC71-04 (Commercial, Industrial). 186
A/D Conversion Requirements ............... 187
RC Oscillator Frequencies...................... 190
Input Capacitance* ................................. 196
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices)........ 198
Clock Timing Requirements.................... 204
CLKOUT and I/O Timing Requirements . 205
Reset, Watchdog Timer, Oscillator
Table 13-4:
Table 13-5:
Table 19-8:
Table 20-1:
Table 20-2:
Table 21-1:
Table 14-1:
Table 14-2:
Table 14-3:
Table 14-4:
Table 14-5:
Table 14-6:
Table 14-7:
Table 14-8:
Table 21-2:
Table 21-3:
Table 21-4:
Start-up Timer and Power-up Timer
Requirements ......................................... 206
Timer0 and Timer1 Clock Requirements 207
Capture/Compare/PWM Requirements
(CCP1).................................................... 208
SPI Mode Requirements......................... 209
Table 21-5:
Table 21-6:
Table 21-7:
Table 21-8:
Table 21-9:
Table 21-10:
2
PIC16C71/73/74...................................... 128
Status Bits and Their Significance,
I C Bus Start/Stop Bits Requirements.... 210
2
I C Bus Data Requirements ................... 211
PIC16C70/71A/72/73A/74A .................... 128
Reset Condition for Special Registers .... 129
Initialization Conditions for all Registers . 129
Opcode Field Descriptions...................... 141
PIC16CXX Instruction Set....................... 142
PICMASTER Probe Specification ........... 154
Development System Packages ............. 157
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies of
Operation (Commercial Devices)............ 160
Clock Timing Requirements.................... 166
CLKOUT and I/O Timing Requirements.. 167
Reset, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer Requirements....
168
Serial Port Synchronous Transmission
Requirements ......................................... 212
Serial Port Synchronous Receive
Requirements ......................................... 212
A/D Converter Characteristics:
PIC16C72-04 (Commercial, Industrial,
Automotive)
PIC16C72-10 (Commercial, Industrial,
Automotive)
Table 14-9:
Table 14-10:
Table 15-1:
Table 15-2:
Table 16-1:
Table 16-2:
Table 17-1:
Table 21-11:
Table 21-12:
PIC16C72-20 (Commercial, Industrial,
Automotive)............................................. 213
A/D Converter Characteristics:
Table 17-2:
Table 17-3:
Table 17-4:
Table 21-13:
PIC16LC72-04 (Commercial, Industrial,
Automotive)............................................. 214
A/D Conversion Requirements ............... 215
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies
of Operation (Commercial Devices)........ 220
Clock Timing Requirements.................... 226
CLKOUT and I/O Timing Requirements . 228
Reset, Watchdog Timer, Oscillator
Table 21-14:
Table 23-1:
Table 17-5:
Table 17-6:
Timer0 Clock Requirements.................... 169
A/D Converter Characteristics:
PIC16C70-04 (Commercial, Industrial,
Automotive)
PIC16C71A-04 (Commercial, Industrial,
Automotive)
Table 23-2:
Table 23-3:
Table 23-4:
PIC16C70-10 (Commercial, Industrial,
Automotive)
PIC16C71A-10 (Commercial, Industrial,
Automotive)
PIC16C70-20 (Commercial, Industrial,
Automotive)
PIC16C71A-20 (Commercial, Industrial,
Automotive)............................................. 170
A/D Converter Characteristics:
Start-up Timer and Power-up Timer
Requirements ......................................... 229
Timer0 and Timer1 Clock Requirements 230
Capture/Compare/PWM Requirements
(CCP1 and CCP2) .................................. 231
Parallel Slave Port Requirements for the
PIC16C74 Only....................................... 232
SPI Mode Requirements......................... 233
Table 23-5:
Table 23-6:
Table 23-7:
Table 23-8:
Table 23-9:
Table 23-10:
Table 23-11:
2
Table 17-7:
I C Bus Start/Stop Bits Requirements.... 234
2
PIC16LC70-04 (Commercial, Industrial,
Automotive)
I C Bus Data Requirements ................... 235
Serial Port Synchronous Transmission
Requirements ......................................... 236
Serial Port Synchronous Receive
Requirements ......................................... 236
A/D Converter Characteristics:
PIC16C73-04 (Commercial, Industrial)
PIC16C74-04 (Commercial, Industrial)
PIC16C73-10 (Commercial, Industrial)
PIC16C74-10 (Commercial, Industrial)
PIC16C73-20 (Commercial, Industrial)
PIC16C74-20 (Commercial, Industrial)... 237
A/D Converter Characteristics:
PIC16LC73-04 (Commercial, Industrial)
PIC16LC74-04 (Commercial, Industrial). 238
A/D Conversion Requirements ............... 239
PIC16LC71A-04 (Commercial, Industrial,
Automotive)............................................. 171
A/D Conversion Requirements................ 172
Cross Reference of Device Specs for
Oscillator Configurations and Frequencies of
Operation (Commercial Devices)............ 175
External Clock Timing Requirements...... 181
CLKOUT and I/O Timing Requirements.. 182
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Requirements.......................................... 183
Timer0 Clock Requirements.................... 184
A/D Converter Characteristics:
Table 23-12:
Table 23-13:
Table 17-8:
Table 19-1:
Table 19-2:
Table 19-3:
Table 19-4:
Table 23-14:
Table 23-15:
Table 19-5:
Table 19-6:
PIC16C71-04 (Commercial, Industrial)
PIC16C71-20 (Commercial, Industrial) ... 185
DS30390B-page 302
1995 Microchip Technology Inc.
PIC16C7X
Table 25-1:
Cross Reference of Device Specs for
Table 25-14:
A/D Converter Characteristics:
Oscillator Configurations and Frequencies
of Operation (Commercial Devices)........ 244
Clock Timing Requirements.................... 250
CLKOUT and I/O Timing Requirements.. 252
Reset, Watchdog Timer, Oscillator
PIC16LC73A-04 (Commercial, Industrial,
Automotive)
Table 25-2:
Table 25-3:
Table 25-4:
PIC16LC74A-04 (Commercial, Industrial,
Automotive)..............................................262
A/D Conversion Requirements ................263
PIC16C5X Family of Devices ..................285
PIC16C62X Family of Devices ................286
PIC16C6X Family of Devices ..................287
PIC16C7X Family of Devices ..................288
PIC16C8X Family of Devices ..................289
PIC17CXX Family of Devices..................290
Pin Compatible Devices...........................291
Table 25-15:
Table E-1:
Table E-2:
Table E-3:
Table E-4:
Table E-5:
Table E-6:
Table E-7:
Start-up Timer and Power-up Timer
Requirements.......................................... 253
Timer0 and Timer1 Clock Requirements 254
Capture/Compare/PWM Requirements
(CCP1 and CCP2)................................... 255
Parallel Slave Port Requirements for the
PIC16C74A Only..................................... 256
SPI Mode Requirements......................... 257
Table 25-5:
Table 25-6:
Table 25-7:
Table 25-8:
Table 25-9:
Table 25-10:
Table 25-11:
2
I C Bus Start/Stop Bits Requirements .... 258
2
I C Bus Data Requirements.................... 259
Serial Port Synchronous Transmission
Requirements.......................................... 260
Serial Port Synchronous Receive
Requirements.......................................... 260
A/D Converter Characteristics:
PIC16C73A-04 (Commercial, Industrial,
Automotive)
Table 25-12:
Table 25-13:
PIC16C74A-04 (Commercial, Industrial,
Automotive)
PIC16C73A-10 (Commercial, Industrial,
Automotive)
PIC16C74A-10 (Commercial, Industrial,
Automotive)
PIC16C73A-20 (Commercial, Industrial,
Automotive)
PIC16C74A-20 (Commercial, Industrial,
Automotive)............................................. 261
1995 Microchip Technology Inc.
DS30390B-page 303
PIC16C7X
NOTES:
DS30390B-page 304
1995 Microchip Technology Inc.
PIC16C7X
CONNECTING TO MICROCHIP BBS
Trademarks:
The Microchip logo, name and PIC are registered
trademarks of Microchip Technology Incorporated
in the U.S.A.
Connect worldwide to the Microchip BBS using the
CompuServe communications network. In most
cases a local call is your only expense. The Microchip
BBS connection does not use CompuServe member-
ship services, therefore you do not need CompuServe
membership to join Microchip's BBS.
PICMASTER, MPLAB, PICSTART, PRO MATE
and fuzzyLAB are trademarks, and SQTP is a ser-
vice mark of Microchip Technology Incorporated.
There is no charge for connecting to the BBS,
except for a toll charge to the CompuServe access
number, where applicable. You do not need to be a
CompuServe member to take advantage of this con-
nection (you never actually log in to CompuServe).
fuzzyTECH is a registered trademark of Inform
Software Corporation.
2
I C is a trademark of Philips Corporation.
IBM, IBM PC-AT are registered trademarks of
International Business Machines Corp.
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allows multiple users at baud rates up to 14400
bps.
Pentium is a trademark of Intel Corporation.
MS-DOS and Microsoft Windows are registered
trademarks of Microsoft Corporation. Windows is a
trademark of Microsoft Corporation.
The following connect procedure applies in most loca-
tions:
CompuServe is a registered trademark of
CompuServe Incorporated.
1. Set your modem to 8 bit, No parity, and One stop
(8N1). This is not the normal CompuServe set-
ting which is 7E1.
All other trademarks mentioned herein are the
property of their respective companies.
2. Dial your local CompuServe access number.
3. Depress <ENTER > and a garbage string will
appear because CompuServe is expecting a
7E1 setting.
4. Type +, depress <ENTER > and Host Name:
will appear.
5. Type MCHIPBBS, depress < ENTER > and
you will be connected to the Microchip BBS.
In the United States, to find CompuServe's phone num-
ber closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with Host Name:, type
NETWORK, depress < ENTER
>
and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 457-1550 for your local CompuServe
number.
1995 Microchip Technology Inc.
DS30390B-page 305
PIC16C7X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device:
PIC16C7X
Literature Number:
DS30390B
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefullness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30390B-page 306
1995 Microchip Technology Inc.
PIC16C7X
PIC16C7X Product Identification System
To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office.
Examples
PART NO. -XX X /XX XXX
Pattern:
QTP, SQTP, ROM Code or Special Requirements
a)
PIC16C71 - 04/P 301
Commercial Temp.,
PDIP Package, 4 MHz,
normal VDD limits, QTP
pattern #301
Package:
JW
PQ
TQ
SO
SP
SJ
P
= Windowed CERDIP
= MQFP (Metric PQFP)
= TQFP (Thin Quad Flatpack)
= SOIC
= Skinny plastic carrier
= Skinny CERDIP
= PDIP
b)
c)
PIC16LC73 - 041/SO
Industrial Temp., SOIC
package, 4 MHz,
L
= PLCC
extended VDD limits
Temperature
Range:
-
= 0°C to +70°C (T for Tape/Reel)
= -40°C to +85°C (S for Tape/Reel)
= -40°C to +125°C
I
PIC16C74A - 10E/P
Automotive Temp.,
PDIP package, 10 MHz,
normal VDD limits
E
Frequency
Range:
04
04
10
16
20
= 200 kHz (PIC16C7X-04)
= 4 MHz
= 10 MHz
= 16 MHz
= 20 MHz
Device
PIC16C7X
:VDD range 4.0V to 6.0V
PIC16C7XT :VDD range 4.0V to 6.0V (Tape/Reel)
PIC16LC7X :VDD range 3.0V to 6.0V
PIC16LC7XT :VDD range 3.0V to 6.0V (Tape/Reel)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office (see below)
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
1995 Microchip Technology Inc.
DS30390B-page 307
WORLDWIDE SALES & SERVICE
AMERICAS
AMERICAS (continued)
EUROPE
Corporate Office
San Jose
United Kingdom
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 602 786-7200 Fax: 602 786-7277
Technical Support: 602 786-7627
Web: http://www.mchip.com/microchip
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: 44 0 1628 851077 Fax: 44 0 1628 850259
Tel: 408 436-7950 Fax: 408 436-7955
ASIA/PACIFIC
Hong Kong
Microchip Technology
Unit No. 3002-3004, Tower 1
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T. Hong Kong
Tel: 852 2 401 1200 Fax: 852 2 401 3431
France
Arizona Microchip Technology SARL
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: 33 1 69 53 63 20 Fax: 33 1 69 30 90 79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: 49 89 627 144 0 Fax: 49 89 627 144 44
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770 640-0034 Fax: 770 640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Korea
Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: 82 2 554 7200 Fax: 82 2 558 5934
Singapore
Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: 65 334 8870 Fax: 65 334 8850
Taiwan
Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886 2 717 7175 Fax: 886 2 545 0139
Italy
Tel: 508 480-9990
Fax: 508 480-8575
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Pegaso Ingresso No. 2
Via Paracelso 23, 20041
Agrate Brianza (MI) Italy
Tel: 39 039 689 9939 Fax: 39 039 689 9883
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 708 285-0071 Fax: 708 285-0075
Dallas
Microchip Technology Inc.
14651 Dallas Parkway, Suite 816
Dallas, TX 75240-8809
Tel: 214 991-7177 Fax: 214 991-8588
JAPAN
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Yokohama
Kanagawa 222 Japan
Dayton
Microchip Technology, Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 513 291-1654 Fax: 513 291-9175
Tel: 81 45 471 6166 Fax: 81 45 471 6122
Los Angeles
Microchip Technology Inc.
18201 Von Karman, Suite 455
Irvine, CA 92715
Tel: 714 263-1888 Fax: 714 263-1338
NewYork
Microchip Technology Inc.
150 Motor Parkway, Suite 416
Hauppauge, NY 11788
Tel: 516 273-5305 Fax: 516 273-5335
Printed in the USA, 12/5/95
1995, Microchip Technology Inc.
Information contained in this publication regarding device applications and the like is intended by way of suggestion only. No representation or warranty is given and no liability is
assumed by Microchip Technology Inc. with respect to the accuracy or use of such information. Use of Microchip’s products as critical components in life support systems is not autho-
rized except with express written approval by Microchip. The Microchip logo and name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks
mentioned herein are the property of their respective companies.
DS30390B-page 308
1995 Microchip Technology Inc.
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