PIC16C745/SO [MICROCHIP]
8-Bit CMOS Microcontrollers with USB; 8位CMOS微控制器与USB
| 型号： | PIC16C745/SO |
| 厂家： | 
MICROCHIP |
| 描述： | 8-Bit CMOS Microcontrollers with USB |
| 文件： | 总158页 (文件大小：2499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C745/765
8-Bit CMOS Microcontrollers with USB
Devices included in this data sheet:
• PIC16C745 • PIC16C765
Pin Diagrams
28-Pin DIP, SOIC
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions
• 1
2
28
27
26
25
24
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
MCLR/VPP
RA0/AN0
RA1/AN1
3
4
5
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
Memory
6
7
8
23
22
21
A/D
A/D
Device
Pins
Vss
Program Data
Resolution Channels
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VUSB
9
20
19
18
17
16
15
x14
x8
Vss
10
11
12
13
14
RC7/RX/DT
RC6/TX/CK
D+
PIC16C745
PIC16C765
8K
8K
256
256
28
40
8
8
5
8
D-
• All single cycle instructions except for program
branches which are two cycle
• Interrupt capability (up to 12 internal/external
interrupt sources)
Peripheral Features:
• Universal Serial Bus (USB 1.1)
• 64 bytes of USB dual port RAM
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• 22 (PIC16C745) or 33 (PIC16C765) I/O pins
- Individual direction control
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
- 1 high voltage open drain (RA4)
- 8 PORTB pins with:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
- Interrupt on change control (RB<7:4> only)
- Weak pull up control
• Brown-out detection circuitry for
Brown-out Reset (BOR)
- 3 pins dedicated to USB
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Programmable code-protection
• Power saving SLEEP mode
• Timer1: 16-bit timer/counter with prescaler
can be incremented during sleep via external
crystal/clock
• Selectable oscillator options
- EC - External clock (24 MHz)
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
- E4 - External clock with PLL (6 MHz)
- HS - Crystal/Resonator (24 MHz)
- H4 - Crystal/Resonator with PLL (6 MHz)
• 2 Capture, Compare and PWM modules
- Capture is 16 bit, max. resolution is 10.4 ns
- Compare is 16 bit, max. resolution is 167 ns
- PWM maximum resolution is 10 bit
• Processor clock of 24MHz derived from 6 MHz
crystal or resonator
• Fully static low-power, high-speed CMOS
• In-Circuit Serial Programming (ICSP)
• Operating voltage range
• 8-bit multi-channel Analog-to-Digital converter
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
- 4.35 to 5.25V
• Parallel Slave Port (PSP) 8-bits wide, with exter-
nal RD, WR and CS controls (PIC16C765 only)
• High Sink/Source Current 25/25 mA
• Wide temperature range
- Industrial (-40°C - 85°C)
• Low-power consumption:
- < TBD @ 5V, 6 MHz
- < TBD typical standby current
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 1
PIC16C745/765
44-Pin PLCC
44-Pin TQFP
RA4/T0CKI
RA5/AN4
RB3
7
39
38
37
36
35
34
33
32
31
30
29
RB2
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
1
33
32
31
30
29
28
27
26
25
24
23
NC
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
9
RB1
2
10
11
12
13
14
15
16
17
RB0/INT
VDD
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
3
4
VSS
PIC16C765
5
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
VSS
6
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
PIC16C765
VDD
7
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD/AN5
RA5/AN4
8
RB0/INT
RB1
9
10
11
RB2
RB3
RA4/T0CKI
40-Pin PDIP
MCLR/VPP
RA0/AN0
1
40
RB7
RB6
RB5
RB4
RB3
RB2
2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RA1/AN1
3
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
4
5
6
RA5/AN4
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
RB1
8
RB0/INT
VDD
9
10
11
12
13
14
15
16
17
18
19
20
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
D+
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
VUSB
RD0/PSP0
RD1/PSP1
D-
RD3/PSP3
RD2/PSP2
Key Features
PICmicroTM Mid-Range Reference Manual
(DS33023)
PIC16C745
PIC16C765
Operating Frequency
Resets (and Delays)
Program Memory (14-bit words)
Data Memory (bytes)
Dual Port Ram
6 MHz or 24 MHz
6 MHz or 24 MHz
POR, BOR (PWRT, OST)
POR, BOR (PWRT, OST)
8K
8K
256
256
64
64
Interrupt Sources
11
12
I/O Ports
22 (Ports A, B, C)
33 (Ports A, B, C, D, E)
Timers
3
3
Capture/Compare/PWM modules
Analog-to-Digital Converter Module
Parallel Slave Port
2
2
5 channel x 8 bit
8 channel x 8 bit
—
Yes
Serial Communication
Brown Out Detect Reset
USB, USART/SCI
Yes
USB, USART/SCI
Yes
DS41124A-page 2
AdvancedInformation
1999 Microchip Technology Inc.
PIC16C745/765
Table of Contents
1.0 General Description .............................................................................................................................................. 5
2.0 PIC16C745/765 Device Varieties ......................................................................................................................... 7
3.0 Architectural Overview.......................................................................................................................................... 9
4.0 Memory Organization.......................................................................................................................................... 15
5.0 I/O Ports.............................................................................................................................................................. 31
6.0 Timer0 Module.................................................................................................................................................... 43
7.0 Timer1 Module.................................................................................................................................................... 45
8.0 Timer2 Module.................................................................................................................................................... 49
9.0 Capture/Compare/PWM Modules....................................................................................................................... 51
10.0 Universal Serial Bus............................................................................................................................................ 57
11.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................. 75
12.0 Analog-to-Digital Converter (A/D) Module .......................................................................................................... 89
13.0 Special Features of the CPU .............................................................................................................................. 95
14.0 Instruction Set Summary................................................................................................................................... 109
15.0 Development Support ....................................................................................................................................... 117
16.0 Electrical Characteristics................................................................................................................................... 123
17.0 DC and AC Characteristics Graphs and Tables ............................................................................................... 141
18.0 Packaging Information ...................................................................................................................................... 143
Index .......................................................................................................................................................................... 151
On-Line Support.......................................................................................................................................................... 155
Reader Response....................................................................................................................................................... 156
Product Identification System ..................................................................................................................................... 157
To Our Valued Customers
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We appreciate your assistance in making this a better document.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 3
PIC16C745/765
NOTES:
DS41124A-page 4
AdvancedInformation
1999 Microchip Technology Inc.
PIC16C745/765
A highly reliable Watchdog Timer (WDT), with a dedi-
cated on-chip RC oscillator, provides protection against
software lock-up, and also provides one way of waking
the device from SLEEP.
1.0
GENERAL DESCRIPTION
The PIC16C745/765 devices are low-cost, high-perfor-
mance, CMOS, fully-static, 8-bit microcontrollers in the
PIC16CXX mid-range family.
A UV erasable CERDIP packaged version is ideal for
code development, while the cost-effective One-Time-
Programmable (OTP) version is suitable for production
in any volume.
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller fam-
ily has enhanced core features, eight-level deep stack
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
the separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches, which require two
cycles. A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
The PIC16C745/765 devices fit nicely in many applica-
tions ranging from security and remote sensors to appli-
ance controls and automotives. The EPROM
technology makes customization of application pro-
grams (data loggers, industrial controls, UPS) extremely
fast and convenient. The small footprint packages make
this microcontroller series perfect for all applications
with space limitations. Low cost, low power, high perfor-
mance, ease of use and I/O flexibility make the
PIC16C745/765 devices very versatile, even in areas
where no microcontroller use has been considered
before (e.g., timer functions, serial communication, cap-
ture and compare, PWM functions and coprocessor
applications).
The PIC16C745 device has 22 I/O pins. The
PIC16C765 device has 33 I/O pins. Each device has
256 bytes of RAM. In addition, several peripheral fea-
tures are available including: three timer/counters, two
Capture/Compare/PWM modules and two serial ports.
The Universal Serial Bus (USB 1.1) peripheral pro-
vides bus communications. The Universal Synchro-
nous Asynchronous Receiver Transmitter (USART) is
also known as the Serial Communications Interface or
SCI. Also, a 5-channel high-speed 8-bit A/D is pro-
vided on the PIC16C745, while the PIC16C765 offers
8 channels. The 8-bit resolution is ideally suited for
applications requiring a low-cost analog interface,
(e.g., thermostat control, pressure sensing, etc).
1.1
Family and Upward Compatibility
Users familiar with the PIC16C5X microcontroller fam-
ily will realize that this is an enhanced version of the
PIC16C5X architecture. Code written for the
PIC16C5X can be easily ported to the PIC16CXX fam-
ily of devices.
1.2
Development Support
PICmicro® devices are supported by the complete line
of Microchip Development tools.
The PIC16C745/765 devices have special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power con-
sumption. There are 4 oscillator options, of which EC is
for the external regulated clock source, E4 is for the
external regulated clock source with PLL, HS is for the
high speed crystals/resonators and H4 is for high
speed crystals/resontators with PLL. The SLEEP
(power-down) feature provides a power-saving mode.
The user can wake up the chip from SLEEP through
several external and internal interrupts and resets.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 5
PIC16C745/765
NOTES:
DS41124A-page 6
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC16C745/765 DEVICE
VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C745/765 Product
Identification System section at the end of this data
sheet. When placing orders, please use that page of
the data sheet to specify the correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.1
UV Erasable Devices
The UV erasable version, offered in windowed CERDIP
packages (600 mil), is optimal for prototype develop-
ment and pilot programs. This version can be erased
and reprogrammed to any of the supported oscillator
modes.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random or sequential.
Microchip’s PICSTART
Plus and PRO MATE II
programmers both support programming of the
PIC16C745/765.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 7
PIC16C745/765
NOTES:
DS41124A-page 8
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
PIC16CXX devices contain an 8-bit ALU and working
register. The ALU is a general purpose arithmetic unit.
It performs arithmetic and Boolean functions between
the data in the working register and any register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which
program and data are accessed from separate memo-
ries using separate buses. This improves bandwidth
over traditional von Neumann architecture in which pro-
gram and data are fetched from the same memory
using the same bus. Separating program and data
buses further allows instructions to be sized differently
than the 8-bit wide data word. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions (Example 3-1). Consequently, most instructions
execute in a single cycle (166.6667 ns @ 24 MHz)
except for program branches.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the working register (W register). The
other operand is a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow bit and a digit borrow out bit,
respectively, in subtraction. See the SUBLWand SUBWF
instructions for examples.
Memory
A/D
A/D
Device
Pins
Program Data
Resolution Channels
x14
x8
PIC16C745
PIC16C765
8K
8K
256
256
28
40
8
8
5
8
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function regis-
ters, including the program counter, are mapped in the
data memory. The PIC16CXX has an orthogonal (sym-
metrical) instruction set that makes it possible to carry
out any operation on any register using any addressing
mode. This symmetrical nature and lack of ‘special
optimal situations’ make programming with the
PIC16CXX simple yet efficient. In addition, the learning
curve is reduced significantly.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 9
PIC16C745/765
FIGURE 3-1: PIC16C745/765 BLOCK DIAGRAM
13
8
PORTA
Data Bus
Program Counter
EPROM
RA0/AN0
Program
Memory
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4
RAM
File
8 Level Stack
(13 bit)
8K x 14
Registers
256 x 8
Program
Bus
14
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
RB0/INT
RB<7:1>
Indirect
Addr
7
Direct Addr
8
FSR reg
STATUS reg
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC6/TX/CK
RC7/RX/DT
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
8
PORTD
OSC1/
CLKIN
Timing
Generation
x4 PLL
Watchdog
Timer
W reg
RD3:0/PSP3:0(2)
OSC2/
CLKOUT
Brown-out
Reset
RD4/PSP4(2)
RD5/PSP5(2)
RD6/PSP6(2)
RD7/PSP7(2)
Parallel Slave Port(2)
MCLR VDD, VSS
PORTE
RE0/AN5/RD(2)
RE1/AN6/WR(2)
RE2/AN7/CS(2)
Timer0
CCP2
Timer1
CCP1
Timer2
8-bit A/D
Dual Port
RAM
64 x 8
VUSB
D-
D+
USB
USART
XCVR
Note 1: Higher order bits are from the STATUS register.
2: Not available on PIC16C745.
DS41124A-page 10
AdvancedInformation
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 3-1:
PIC16C745/765 PINOUT DESCRIPTION
Input
Type
Output
Type
Name
Function
Description
MCLR
VPP
ST
Power
Xtal
ST
—
—
Master Clear
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
Programming Voltage
OSC1
CLKIN
OSC2
CLKOUT
—
Crystal/Resonator
—
External Clock Input/ER resistor connection.
Crystal/Resonator
—
Xtal
—
CMOS Internal Clock (FINT/4) Output
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
VREF
RA4
T0CKI
RA5
AN4
ST
AN
ST
AN
ST
AN
ST
AN
AN
ST
ST
ST
AN
CMOS Bi-directional I/O
RA0/AN0
RA1/AN1
RA2/AN2
—
A/D Input
CMOS Bi-directional I/O
A/D Input
CMOS Bi-directional I/O
A/D Input
CMOS Bi-directional I/O
—
—
RA3/AN3/VREF
—
—
A/D Input
A/D Positive Reference
Bi-directional I/O
Timer 0 Clock Input
Bi-directional I/O
A/D Input
OD
—
RA4/T0CKI
RA5/AN4
—
RB0
INT
TTL
ST
CMOS Bi-directional I/O
Interrupt
RB0/INT
—
RB1
RB2
RB3
RB4
RB5
RB1
TTL
TTL
TTL
TTL
TTL
TTL
ST
CMOS Bi-directional I/O
RB2
CMOS Bi-directional I/O
RB3
CMOS Bi-directional I/O
RB4
CMOS Bi-directional I/O with Interrupt on Change
CMOS Bi-directional I/O with Interrupt on Change
CMOS Bi-directional I/O with Interrupt on Change
In-Circuit Serial Programming Clock input
CMOS Bi-directional I/O with Interrupt on Change
CMOS In-Circuit Serial Programming Data I/O
RB5
RB6
RB6/ICSPC
RB7/ICSPD
ICSPC
RB7
TTL
ST
ICSPD
RC0
T1OSO
T1CKI
RC1
ST
—
CMOS Bi-directional I/O
RC0/T1OSO/T1CKI
Xtal
—
T1 Oscillator Output
T1 Clock Input
ST
ST
Xtal
CMOS Bi-directional I/O
RC!/T1OSI/CCP2
T1OSI
CCP2
RC2
—
T1 Oscillator Input
Capture In/Compare Out/PWM Out 2
ST
CMOS Bi-directional I/O
Capture In/Compare Out/PWM Out 1
RC2/CCP1/VUSB
CCP1
VUSB
D-
VUSB
D-
Power
USB
3.3V for pull up resistor
USB Differential Bus
USB Differential Bus
USB
USB
D+
D+
USB
Legend:
OD = open drain, ST = Schmitt Trigger
Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable.
2: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 11
PIC16C745/765
TABLE 3-1:
PIC16C745/765 PINOUT DESCRIPTION (CONTINUED)
Input
Type
Output
Type
Name
Function
Description
RC6
TX
ST
—
CMOS Bi-directional I/O
RC6/TX/CK
CMOS USART Async Transmit
CK
ST
ST
ST
ST
CMOS USART Master Out/Slave In Clock
CMOS Bi-directional I/O
RC7
RX
RC7/RX/DT
—
USART Async Receive
DT
CMOS USART Data I/O
(2)
RD0
PSP0
RD1
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CMOS Bi-directional I/O
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP1
RD2
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP2
RD3
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP3
RD4
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP4
RD5
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP5
RD6
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP6
RD7
—
Parallel Slave Port data input
(2)
CMOS Bi-directional I/O
PSP7
—
Parallel Slave Port data input
(2)
RE0
RD
ST
TTL
AN
ST
CMOS Bi-directional I/O
(2)
(2)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
—
—
Parallel Slave Port control input
(2)
AN5
RE1
WR
AN6
RE2
CS
A/D Input
(2)
CMOS Bi-directional I/O
TTL
AN
ST
—
—
Parallel Slave Port control input
(2)
A/D Input
(2)
CMOS Bi-directional I/O
(2)
TTL
AN
—
—
Parallel Slave Port data input
(2)
AN7
A/D Input
VDD
VSS
VDD
VSS
Power
Power
Power
Power
—
—
—
—
Power
Ground
AVDD
AVSS
AVDD
AVSS
Analog Power
Analog Ground
Legend:
OD = open drain, ST = Schmitt Trigger
Note 1: Weak pull-ups. PORT B pull-ups are byte wide programmable.
2: PIC16C765 only.
DS41124A-page 12
AdvancedInformation
1999 Microchip Technology Inc.
PIC16C745/765
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input feeds an on-chip PLL. The clock output
from the PLL (FINT) is internally divided by four to gen-
erate four non-overlapping quadrature clocks namely,
Q1, Q2, Q3 and Q4. Internally, the program counter
(PC) is incremented every Q1, the instruction is fetched
from the program memory and latched into the instruc-
tion register in Q4. The instruction is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3 and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
FINT
Q1
Internal
phase
clock
Q2
Q3
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(EC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
TCY0
TCY1
TCY2
TCY3
TCY4
TCY5
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3 (Forced NOP)
Flush
5. Instruction @ address SUB_1
Fetch SUB_1 Execute SUB_1
Note: All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 13
PIC16C745/765
NOTES:
DS41124A-page 14
AdvancedInformation
1999 Microchip Technology Inc.
PIC16C745/765
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 are the bank select bits.
4.1
Program Memory Organization
The PIC16C745/765 has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. All devices covered by this datasheet have 8K x
14 bits of program memory. The address range is
0000h - 1FFFh for all devices.
RP<1:0> (STATUS<6:5>)
= 00→ Bank0
= 01→ Bank1
The reset vector is at 0000h and the interrupt vector is
at 0004h.
= 10→ Bank2
= 11→ Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the SFRs.
Above the SFRs are GPRs, implemented as static
RAM.
FIGURE 4-1: PIC16C745/765 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
All implemented banks contain SFRs. Some “high use”
SFRs from one bank may be mirrored in another bank
for code reduction and quicker access.
CALL, RETURN
RETFIE, RETLW
13
4.2.1
GENERAL PURPOSE REGISTER FILE
Stack Level 1
Stack Level 2
The register file can be accessed either directly or indi-
rectly through the File Select Register (FSR)
(Section 4.5).
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
Page 1
Page 2
On-chip
Program
Memory
0FFFh
1000h
17FFh
1800h
Page 3
1FFFh
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 15
PIC16C745/765
FIGURE 4-2: DATA MEMORY MAP FOR PIC16C745/765
Bank 0
File
Bank 1
File
Bank 2
File
Bank 3
File
Address
Address
Address
Address
Indirect addr.(*)
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
Indirect addr.(*)
OPTION_REG
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
Indirect addr.(*)
TMR0
100h
101h
102h
103h
104h
105h
106h
107h
108h
Indirect addr.(*)
OPTION_REG
PCL
180h
181h
182h
183h
184h
185h
186h
187h
188h
PCL
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
TRISA
TRISB
PORTB
TRISB
TRISC
(2)
(2)
PORTD
TRISD
(2)
(2)
09h
89h
109h
189h
PORTE
TRISE
PCLATH
INTCON
PIR1
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
PCLATH
INTCON
PIE1
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
PCLATH
INTCON
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
PCLATH
INTCON
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
UIR
UIE
T2CON
PR2
UEIR
UEIE
USTAT
UCTRL
UADDR
CCPR1L
CCPR1H
CCP1CON
(1)
USWSTAT
RCSTA
TXREG
RCREG
CCPR2L
18h
19h
1Ah
1Bh
TXSTA
98h
99h
9Ah
9Bh
118h
119h
11Ah
11Bh
UEP0
UEP1
UEP2
198h
199h
19Ah
SPBRG
(1)
19Bh
(1)
CCPR2H
CCP2CON
ADRESH
ADCON0
1Ch
1Dh
1Eh
1Fh
20h
9Ch
9Dh
9Eh
9Fh
A0h
11Ch
11Dh
11Eh
11Fh
120h
19Ch
(1)
19Dh
(1)
19Eh
(1)
ADCON1
19Fh
General
Purpose
Register
96 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
USB Dual Port
Memory
64 Bytes
1A0h
1DFh
1E0h
1EFh
1F0h
1FFh
EFh
F0h
FFh
16Fh
170h
17Fh
accesses
70h-7Fh
accesses
70h-7Fh
accesses
70h-7Fh
7Fh
Unimplemented data memory locations, read as ‘0’.
*Not a physical register.
Note 1: Reserved registers may contain USB state information.
2: Parallel slave ports (PORTD and PORTE) not implemented on PIC16C745; always maintain these bits clear.
DS41124A-page 16
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF(3)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xx-- -xxx uu-- -uuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
PCL(3)
Program Counter's (PC) Least Significant Byte
STATUS(3)
FSR(3)
IRP(2)
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
RC7 RC6
RP1(2)
RP0
TO
PD
Z
DC
C
PORTA
PORTB
PORTC
—
—
RC2
RC1
RE1
RC0
—
—
—
PORTD(4) PORTD Data Latch when written: PORTD pins when read
PORTE(4)
PCLATH(1,3)
INTCON(3)
PIR1
—
—
—
—
—
—
—
—
RE2
RE0
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
–
RBIE
USBIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
PSPIF(4)
—
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
PIR2
TMR1L
TMR1H
T1CON
TMR2
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0
T1OSCEN
T1SYNC
TMR1CS TMR1ON --00 0000 --uu uuuu
0000 0000 0000 0000
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1
T2CON
—
—
TOUTPS0
TMR2ON
T2CKPS1 T2CKPS0 -000 0000 -000 0000
Unimplemented
—
—
—
—
—
Unimplemented
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
DC1B1
SREN
DC1B0
CREN
CCP1M3
—
CCP1M2
FERR
CCP1M1
OERR
CCP1M0 --00 0000 --00 0000
SPEN
RX9
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
DC2B1
CHS2
DC2B1
CHS1
CCP2M3
CHS0
CCP2M2
CCP2M1
—
CCP2M0 --00 0000 --00 0000
A/D Result Register
ADCS1 ADCS0
xxxx xxxx uuuu uuuu
GO/DONE
ADON
0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 17
PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
INDF(3)
OPTION
PCL(3)
STATUS(3)
FSR(3)
TRISA
TRISB
TRISC
TRISD(4)
TRISE(4)
PCLATH(1,3)
INTCON(3)
PIE1
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
11-- -111 11-- -111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
RBPU
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
PORTB Data Direction Register
TRISC7 TRISC8
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
PD
Z
DC
—
—
TRISC2
TRISC1
TRISC0
—
—
—
—
PORTD Data Direction Register
IBF
—
OBF
—
IBOV
—
PSPMODE
PORTE Data Direction Bits
Write Buffer for the upper 5 bits of the Program Counter
GIE
PEIE
ADIE
—
T0IE
RCIE
—
INTE
TXIE
—
RBIE
USBIE
—
T0IF
CCP1IE
—
INTF
TMR2IE
—
RBIF
PSPIE(4)
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PIE2
PCON
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PR2
1111 1111 1111 1111
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124A-page 18
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 2
100h
INDF(3)
TMR0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
101h
PCL(3)
102h
Program Counter's (PC) Least Significant Byte
STATUS(3)
103h
IRP
RP1
RP0
TO
PD
Z
DC
C
FSR(3)
—
104h
Indirect data memory address pointer
Unimplemented
105h
106h
107h
108h
109h
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
PCLATH(1,3)
INTCON(3)
10Ah
10Bh
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF
---0 0000 ---0 0000
0000 000x 0000 000u
GIE
PEIE
T0IE
RBIF
10Ch-
11Fh
—
Unimplemented
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 19
PIC16C745/765
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
Bank 3
180h
INDF(3)
OPTION_REG RBPU
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
181h
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
PCL(3)
182h
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
STATUS(3)
183h
PD
Z
DC
FSR(3)
—
184h
185h
186h
187h
188h
189h
18Ah
Indirect data memory address pointer
Unimplemented
xxxx xxxx uuuu uuuu
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
Write Buffer for the upper 5 bits of the Program Counter
PCLATH(1,3)
INTCON(3)
—
—
—
---0 0000 ---0 0000
0000 000x 0000 000u
18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
18Ch-
18Fh
—
Unimplemented
—
—
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
UIR
—
—
—
—
STALL
STALL
UIDLE
UIDLE
TOK_DNE
TOK_DNE
DFN8
ACTIVITY
ACTIVITY
CRC16
CRC16
IN
UERR
UERR
CRC5
CRC5
—
USB_RST --00 0000 --00 0000
USB_RST --00 0000 --00 0000
PID_ERR 0000 0000 0000 0000
PID_ERR 0000 0000 0000 0000
UIE
UEIR
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
BTS_ERR OWN_ERR WRT_ERR BTO_ERR
UEIE
DFN8
USTAT
UCTRL
UADDR
USWSTAT
UEP0
UEP1
UEP2
—
—
—
—
—
—
ENDP1
PKT_DIS
ADDR4
ENDP0
—
—
---x xx-- ---u uu--
--x0 000- --xq qqq-
SEO
DEV_ATT
ADDR3
RESUME
ADDR2
SWSTAT2
SUSPND
ADDR1
ADDR6
ADDR5
ADDR0 -000 0000 -000 0000
SWSTAT7 SWSTAT6 SWSTAT5 SWSTAT4
SWSTAT3
SWSTAT1 SWSTAT0 0000 0000 0000 0000
—
—
—
—
—
—
—
—
—
—
—
—
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Bh-
19Fh
Reserved
Reserved, do not use.
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
3: These registers can be addressed from either bank.
4: The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
DS41124A-page 20
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 4-2:
USB DUAL PORT RAM
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other resets
(2)
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1A0h
BD0OST
xxxx xxxx uuuu uuuu
1A1h
1A2h
1A3h
BD0OBC
BD0OAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1A4h
BD0IST
xxxx xxxx uuuu uuuu
1A5h
1A6h
1A7h
BD0IBC
BD0IAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1A8h
BD1OST
xxxx xxxx uuuu uuuu
1A9h
1AAh
1ABh
BD1OBC
BD1OAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1ACh
BD1IST
xxxx xxxx uuuu uuuu
1ADh
1AEh
1AFh
BD1IBC
BD1IAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1B0h
BD2OST
xxxx xxxx uuuu uuuu
1B1h
1B2h
1B3h
BD2OBC
BD2OAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
UOWN
UOWN
DATA0/1
DATA0/1
PID3
—
PID2
—
PID1
DTS
PID0
BSTALL
—
—
—
—
1B4h
BD2IST
xxxx xxxx uuuu uuuu
1B5h
1B6h
1B7h
BD2IBC
BD2IAL
—
—
—
—
—
Byte Count
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Buffer Address Low
Reserved
—
—
1B8h-
1DFh
40 byte USB Buffer
xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 21
PIC16C745/765
4.2.2.1
STATUS REGISTER
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
It is recommended that only BCF, BSF, SWAPFand
MOVWFinstructions be used to alter the STATUS regis-
ter. These instructions do not affect the Z, C or DC bits
in the STATUS register. For other instructions which do
not affect status bits, see the "Instruction Set Sum-
mary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as borrow and
digit borrow bits, respectively, in subtrac-
tion. See the SUBLW and SUBWF instruc-
tions for examples.
REGISTER 4-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
(1)
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
C
bit7
bit0
- n = Value at POR reset
bit 7:
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)
00= Bank 0 (00h - 7Fh)
01= Bank 1 (80h - FFh)
10= Bank 2 (100h - 17Fh)
11= Bank 3 (180h - 1FFh)
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)(1)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-
ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
DS41124A-page 22
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the watchdog timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external INT Interrupt,
TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (OPTION_REG: 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
bit7
bit0
-n
=
Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 23
PIC16C745/765
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and external
RB0/INT pin interrupts.
REGISTER 4-3: INTERRUPT CONTROL REGISTER (INTCON: 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
bit7
bit0
-n
=
Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= At least one of the RB<7:4> pins changed state (must be cleared in software)
0= None of the RB<7:4> pins have changed state
DS41124A-page 24
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
4.2.2.4
PIE1 REGISTER
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
REGISTER 4-4: PERIPHERAL INTERRUPT ENABLE1 REGISTER (PIE1: 8Ch)
R/W-0
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
USBIE
R/W-0
R/W-0
R/W-0
(1)
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
PSPIE
CCP1IE
TMR2IE TMR1IE
bit7
bit0
-n
=
Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D interrupt
0= Disables the A/D interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
USBIE: Universal Serial Bus Interrupt Enable bit
1= Enables the USB interrupt
0= Disables the USB interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PIC16C745 device does not have a parallel slave port implemented; always maintain this bit clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 25
PIC16C745/765
4.2.2.5
PIR1 REGISTER
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
This register contains the individual flag bits for the
peripheral interrupts.
REGISTER 4-5: PERIPHERAL INTERRUPT REGISTER1 (PIR1: 0Ch)
R/W-0
R/W-0
ADIF
R-0
R-0
R/W-0
USBIF
R/W-0
R/W-0
R/W-0
(1)
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
RCIF
TXIF
CCP1IF
TMR2IF TMR1IF
PSPIF
bit7
bit0
-n
=
Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed (must be cleared in software)
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full (clear by reading RCREG)
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty (clear by writing to TXREG)
0= The USART transmit buffer is full
USBIF: Universal Serial Bus (USB) Interrupt Flag
1= A USB interrupt condition has occurred. The specific cause can be found by examining the contents
of the UIR and UIE registers.
0= No USB interrupt conditions that are enabled have occurred.
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
bit 0:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PIC16C745 device does not have a parallel slave port implemented. This bit location is reserved on this
device. Always maintain this bit clear.
DS41124A-page 26
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
4.2.2.6
PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
REGISTER 4-6: PERIPHERAL INTERRUPT ENABLE 2 REGISTER (PIE2: 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IE
bit0
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
—
—
—
—
—
—
—
bit7
-n
=
Value at POR reset
bit 7-1: Unimplemented: Read as ’0’
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
4.2.2.7
PIR2 REGISTER
This register contains the CCP2 interrupt flag bit. .
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
REGISTER 4-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit0
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
—
—
—
—
—
—
—
bit7
-n
=
Value at POR reset
bit 7-1: Unimplemented: Read as ’0’
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 27
PIC16C745/765
4.2.2.8
PCON REGISTER
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
resets to see if BOR is clear, indicating a
brown-out has occurred. The BOR status
bit is a “don't care” and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
The Power Control (PCON) register contains flag bits to
allow differentiation between a Power-on Reset (POR),
a Brown-out Reset (BOR), a Watch-dog Reset (WDT)
and an external MCLR Reset.
REGISTER 4-8: POWER CONTROL REGISTER REGSTER (PCON: 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-q
BOR
R
W
U
=
=
=
Readable bit
Writable bit
Unimplemented bit,
read as ‘0’
bit7
bit0
-n
=
Value at POR reset
bit 7-2: Unimplemented: Read as ’0’
bit 1:
POR: Power-on Reset Status bit
1= No power-on reset occurred
0= A power-on reset occurred (must be set in software after a power-on reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1= No brown-out reset occurred
0= A brown-out reset occurred (must be set in software after a brown-out reset occurs)
DS41124A-page 28
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
4.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 4-3 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSHor POP. These are actions that
occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt
address.
4.4
Program Memory Paging
PIC16CXX devices are capable of addressing a contin-
uous 8K word block of program memory. The CALLand
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALLor GOTOinstruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits is not
required for the return instructions (which POPs the
address from the stack).
FIGURE 4-3: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
PC
Destination
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PCL
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the interrupt ser-
vice routine (if interrupts are used).
8
7
0
GOTO,CALL
PC
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
EXAMPLE 4-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF PCLATH,3
CALLSUB1_P1
;Select page 1 (800h-FFFh)
;Call subroutine in
4.3.1
COMPUTED GOTO
:
;page 1 (800h-FFFh)
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
:
ORG 0x900
;page 1 (800h-FFFh)
SUB1_P1
:
:
:
;called subroutine
;page 1 (800h-FFFh)
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
4.3.2
STACK
The PIC16CXX family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSHor POPoperation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 29
PIC16C745/765
4.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 4-2: INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 4-4.
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-2.
FIGURE 4-4: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP<1:0>
6
0
0
IRP
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory
7Fh
FFh
17Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
Note: For register file map detail see Figure 4-2.
DS41124A-page 30
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 5-1: BLOCK DIAGRAM OF RA<3:0>
AND RA5 PINS
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
Q
VDD
P
VDD
WR
Port
5.1
PORTA and TRISA Registers
CK
PORTA is a 6-bit latch.
Data Latch
D
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL input
levels and full CMOS output drivers. All pins have data
direction bits (TRIS registers), which can configure
these pins as output or input.
N
I/O Pin
Q
Q
WR
TRIS
VSS
CK
Analog
Input
Mode
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
TRIS Latch
Schmitt
Trigger
Input
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified, and then written to the port
data latch.
Buffer
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
RD PORT
On the PIC16C745/765, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
To A/D Converter
FIGURE 5-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On all resets, pins with analog and digital
VDD
functions are configured as analog inputs.
Data
Bus
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
D
Q
Q
WR
PORT
CK
I/O pin
N
Data Latch
D
Q
EXAMPLE 5-1: INITIALIZING PORTA
(PIC16C745/765)
VSS
WR
TRIS
Schmitt
Trigger
Input
BCF
BCF
CLRF
STATUS, RP1
STATUS, RP0
PORTA
;
;
Q
CK
TRIS Latch
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
Buffer
BSF
STATUS, RP0
0x06
ADCON1
0xCF
RD TRIS
MOVLW
MOVWF
MOVLW
Q
D
EN
RD PORT
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
TMR0 Clock Input
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 31
PIC16C745/765
TABLE 5-1:
PORTA FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
RA0
ST
AN
ST
AN
ST
AN
ST
AN
AN
ST
ST
ST
AN
CMOS Bi-directional I/O
RA0/AN0
RA1/AN1
RA2/AN2
AN0
RA1
AN1
RA2
AN2
RA3
AN3
VREF
RA4
T0CKI
RA5
AN4
—
A/D Input
CMOS Bi-directional I/O
A/D Input
CMOS Bi-directional I/O
A/D Input
CMOS Bi-directional I/O
—
—
RA3/AN3/VREF
—
—
A/D Input
A/D Positive Reference
Bi-directional I/O
Timer 0 Clock Input
Bi-directional I/O
A/D Input
OD
—
RA4/T0CKI
RA5/AN4
—
Legend:
OD = open drain, ST = Schmitt Trigger
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
PORTA
TRISA
ADCON1
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
PORTA Data Direction Register
9Fh
—
—
—
—
—
PCFG2
PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.
DS41124A-page 32
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The corre-
sponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance input mode. Clearing a bit in
the TRISB register puts the contents of the output latch
on the selected pin(s).
This interrupt-on-mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a power-on reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
FIGURE 5-3: BLOCK DIAGRAM OF RB<3:0>
PINS
VDD
VDD
RB0/INT is discussed in detail in Section 13.5.1.
RBPU(1)
weak
pull-up
P
FIGURE 5-4: BLOCK DIAGRAM OF
RB<7:4> PINS
Data Latch
Data Bus
WR Port
D
Q
VDD
VDD
I/O
pin
RBPU(1)
weak
P
CK
TRIS Latch
pull-up
Data Latch
Data Bus
D
Q
D
Q
TTL
Input
I/O
pin
WR TRIS
WR Port
CK
Buffer
CK
TRIS Latch
D
Q
RD TRIS
RD Port
WR TRIS
TTL
Input
Buffer
CK
Q
D
ST
Buffer
EN
RD TRIS
RD Port
Latch
RB0/INT
Q
Q
D
Schmitt Trigger
Buffer
RD Port
EN
Q1
Set RBIF
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
D
From other
RB<7:4> pins
RD Port
Q3
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins (of RB<7:4>) are
compared with the value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
EN
RB<7:6> in serial programming mode
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 33
PIC16C745/765
TABLE 5-3:
PORTB FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
RB0
INT
TTL
ST
CMOS Bi-directional I/O
RB0/INT
—
Interrupt
RB1
RB2
RB3
RB4
RB5
RB1
RB2
RB3
RB4
RB5
RB6
ICSPC
RB7
TTL
TTL
TTL
TTL
TTL
TTL
ST
CMOS Bi-directional I/O
CMOS Bi-directional I/O
CMOS Bi-directional I/O
CMOS Bi-directional I/O with Interrupt on Change
CMOS Bi-directional I/O with Interrupt on Change
CMOS Bi-directional I/O with Interrupt on Change
In-Circuit Serial Programming Clock input
RB6/ICSPC
TTL
ST
CMOS Bi-directional I/O with Interrupt on Change
CMOS In-Circuit Serial Programming Data I/O
RB7/ICSPD
Legend:
ICSPD
OD = open drain, ST = Schmitt Trigger
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
uuuu uuuu
1111 1111
1111 1111
06h, 106h
86h, 186h
81h, 181h
PORTB
TRISB
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2
RB7
RB6
RB5
RB4
RB3 RB2 RB1 RB0
xxxx xxxx
1111 1111
1111 1111
PORTB Data Direction Register
PS1
PS0
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS41124A-page 34
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
5.3
PORTC and TRISC Registers
FIGURE 5-5: PORTC BLOCK DIAGRAM
PORT/PERIPHERAL Select(1)
PORTC is a 5-bit bi-directional port. Each pin is individ-
ually configureable as an input or output through the
TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
Peripheral Data Out
VDD
VDD
0
Data Bus
WR
PORT
D
Q
Q
P
1
CK
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Data Latch
I/O
pin
D
Q
Q
WR
TRIS
CK
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(2)
Q
D
EN
RD
PORT
Peripheral Input
Note 1: Port/Peripheral select signal selects between port
data and peripheral output.
2: Peripheral OE (output enable) is only activated if
peripheral select is active.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 35
PIC16C745/765
TABLE 5-5:
PORTC FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
RC0
T1OSO
T1CKI
RC1
T1OSI
CCP2
RC2
CCP1
RC6
TX
ST
—
CMOS Bi-directional I/O
RC0/T1OSO/T1CKI
Xtal
—
T1 Oscillator Output
T1 Clock Input
ST
ST
Xtal
—
CMOS Bi-directional I/O
RC!/T1OSI/CCP2
RC2/CCP1/VUSB
RC6/TX/CK
—
—
T1 Oscillator Input
Capture In/Compare Out/PWM Out 2
ST
—
CMOS Bi-directional I/O
—
Capture In/Compare Out/PWM Out 1
ST
—
CMOS Bi-directional I/O
CMOS USART Async Transmit
CMOS USART Master Out/Slave In Clock
CMOS Bi-directional I/O
CK
ST
ST
ST
ST
RC7
RX
RC7/RX/DT
—
USART Async Receive
DT
CMOS USART Data I/O
Legend:
OD = open drain, ST = Schmitt Trigger
TABLE 5-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
07h
87h
PORTC
TRISC
RC7
RC6
—
—
—
—
—
—
RC2
RC1
RC0
xx-- -xxx
uu-- -uuu
11-- -111
TRISC7 TRISC6
TRISC2 TRISC1 TRISC0 11-- -111
Legend: x= unknown, u= unchanged.
DS41124A-page 36
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
5.4
PORTD and TRISD Registers
FIGURE 5-6: PORTD BLOCK DIAGRAM
VDD
Note: The PIC16C745 does not provide PORTD.
The PORTD and TRISD registers are
reserved. Always maintain these bits clear.
Data
Bus
D
Q
WR
PORT
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configured as an input or
output.
I/O pin
CK
Data Latch
D
Q
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD PORT
TABLE 5-7:
PORTD FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
(1)
RD0
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
CMOS Bi-directional I/O
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
(1)
PSP0
RD1
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PSP1
RD2
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP2
RD3
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP3
RD4
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP4
RD5
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP5
RD6
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP6
RD7
—
Parallel Slave Port data input
(1)
CMOS Bi-directional I/O
PSP7
—
Parallel Slave Port data input
Legend:
OD = open drain, ST = Schmitt Trigger
Note 1: PIC16C765 only.
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
08h
88h
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
PORTD
(1)
PORTD Data Direction Register
TRISD
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
Note 1: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 37
PIC16C745/765
5.5
PORTE and TRISE Registers
FIGURE 5-7: PORTE BLOCK DIAGRAM
VDD
Note 1: The PIC16C745 does not provide
PORTE. The PORTE and TRISE registers
are reserved. Always maintain these bits
clear.
Data
Bus
D
Q
WR
I/O pin
PORT
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configured as
inputs or outputs. These pins have Schmitt Trigger
input buffers.
CK
Data Latch
D
Q
WR
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs) and that register ADCON1 is configured for dig-
ital I/O. In this mode, the input buffers are TTL.
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
Register 5-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
EN
PORTE pins may be multiplexed with analog inputs
(PIC16C765 only). The operation of these pins is
selected by control bits in the ADCON1 register. When
selected as an analog input, these pins will read as ’0’s.
RD PORT
To A/D Converter
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
TRISE bits are used to control the parallel slave port.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs.
TABLE 5-9:
PORTE(1) FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
(1)
RE0
ST
TTL
AN
ST
CMOS Bi-directional I/O
(1)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
RD
AN5
RE1
WR
AN6
RE2
CS
—
—
Parallel Slave Port control input
(1)
A/D Input
(1)
CMOS Bi-directional I/O
(1)
TTL
AN
ST
—
—
Parallel Slave Port control input
(1)
A/D Input
(1)
CMOS Bi-directional I/O
(1)
TTL
AN
—
—
Parallel Slave Port data input
(1)
AN7
A/D Input
Legend:
OD = open drain, ST = Schmitt Trigger
Note 1: PIC16C765 only.
DS41124A-page 38
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
REGISTER 5-1: PORTE DATA DIRECTION CONTROL REGISTER(1) (TRISE: 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
R/W-1
R/W-1
OBF
PSPMODE
—
TRISE2
TRISE1
TRISE0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7 :
bit 6:
bit 5:
bit 4:
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1= A write occurred when a previously input word has not been read (must be cleared in software)
0= No overflow occurred
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel slave port mode
0= General purpose I/O mode
bit 3:
bit 2:
Unimplemented: Read as '0'
PORTE Data Direction Bits
TRISE2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1:
bit 0:
TRISE1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
TRISE0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
Note 1: PIC16C765 only.
TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
09h
89h
9Fh
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
0000 -111 0000 -111
---- -000 ---- -000
PORTE
(1)
IBF OBF IBOV PSPMODE
PORTE Data Direction Bits
PCFG2 PCFG1 PCFG0
TRISE
ADCON1
—
—
—
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
Note 1: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 39
PIC16C745/765
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
5.6
Parallel Slave Port (PSP)
Note: The PIC16C745 does not provide a paral-
lel slave port. The PORTD, PORTE, TRISD
and TRISE registers are reserved. Always
maintain these bits clear.
FIGURE 5-8: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
PORTD operates as an 8-bit wide Parallel Slave Port
(PSP), or microprocessor port when control bit PSP-
MODE (TRISE<4>) is set. In slave mode, it is asyn-
chronously readable and writable by the external world
through RD control input pin RE0/RD/AN5 and WR
control input pin RE1/WR/AN6.
VDD
Data Bus
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD/AN5 to be the RD input,
RE1/WR/AN6 to be the WR input and RE2/CS/AN7 to
be the CS (chip select) input. For this functionality, the
corresponding data direction bits of the TRISE register
(TRISE<2:0>) must be configured as inputs (set) and
the A/D port configuration bits PCFG<2:0>
(ADCON1<2:0>) must be set, which will configure pins
RE<2:0> as digital I/O.
D
Q
WR
PORT
RDx
pin
CK
TTL
Q
D
RD
PORT
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
There are actually two 8-bit latches; one for data-out
(from the PICmicro® microcontroller) and one for data
input. The user writes 8-bit data to PORTD data latch
and reads data from the port pin latch (note that they
have the same address). In this mode, the TRISD reg-
ister is ignored, since the microprocessor is controlling
the direction of data flow.
Read
TTL
RD
Chip Select
TTL
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full (IBF) status flag bit (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal the
write is complete (Figure 5-9). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The Input Buffer Overflow (IBOV) status flag
bit (TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
CS
Write
TTL
WR
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 5-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
DS41124A-page 40
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 5-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
08h
09h
89h
0Ch
8Ch
9Fh
0Bh
PORTD
PORTE
Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
(2)
—
IBF
—
—
—
—
RE2
RE1
RE0
(2)
TRISE
PIR1
PIE1
OBF IBOV PSPMODE
—
PORTE Data Direction Bits
(1)
(1)
PSPIF
PSPIE
—
ADIF RCIF
ADIE RCIE
TXIF
TXIE
—
USBIF CCP1IF TMR2IF
TMR1IF 0000 0000 0000 0000
USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
ADCON1
INTCON
—
—
—
PCFG2
T0IF
PCFG1
INTF
PCFG0 ---- -000 ---- -000
RBIF 0000 000x 0000 000u
GIE
PEIE T0IE
INTE
RBIE
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745. Always maintain these bits clear.
2: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 41
PIC16C745/765
NOTES:
DS41124A-page 42
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 6.2.
6.0
TIMER0 MODULE
The Timer0 module timer/counter has the following fea-
tures:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the watchdog timer. The pres-
caler is not readable or writable. Section 6.3 details the
operation of the prescaler.
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
Timer0 Interrupt
Additional information on the Timer0 module is available
in the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt ser-
vice routine before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
FINT
Data Bus
8
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
Pin
SYNC
2
Cycles
TMR0 reg
T0SE
TOCS
Set flag bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION_REG<5:0>).
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 43
PIC16C745/765
The PSA and PS<2:0> bits (OPTION_REG<3:0>) deter-
mine the prescaler assignment and prescale ratio.
6.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the watchdog timer. The prescaler is not
readable or writable.
Note: Writing to TMR0, when the prescaler is
assigned to Timer0, will clear the prescaler
count, but will not change the prescaler
assignment.
6.3
Prescaler
To avoid an unintended device RESET, the following
instruction sequence (shown in Example 6-1) must be
executed when changing the prescaler assignment
from Timer0 to the WDT. This sequence must be fol-
lowed even if the WDT is disabled.
There is only one prescaler available which is mutually
exclusively shared between the Timer0 module and the
watchdog timer. A prescaler assignment for the Timer0
module means that there is no prescaler for the watch-
dog timer, and vice-versa. This prescaler is not readable
or writable (see Figure 6-1).
EXAMPLE 6-1: CHANGING PRESCALER (TIMER0→WDT)
1) BSF
STATUS, RP0
;Bank1
2) MOVLW b’xx0x0xxx’
3) MOVWF OPTION_REG
;Select clock source and prescale value of
Lines 2 and 3 do
NOT have to be
;other than 1:1
included if the final
desired prescale
value is other than
1:1. If 1:1 is the final
desired value, then a
temporary prescale
value is set in lines 2
and 3 and the final
prescale value will
be set in lines 10
and 11.
4) BCF
5) CLRF
6) BSF
STATUS, RP0
TMR0
;Bank0
;Clear TMR0 and prescaler
STATUS, RP1
;Bank1
7) MOVLW b’xxxx1xxx’
8) MOVWF OPTION_REG
9) CLRWDT
;Select WDT, do not change prescale value
;
;Clears WDT and prescaler
10) MOVLW b’xxxx1xxx’
11) MOVWF OPTION_REG
;Select new prescale value and WDT
;
12) BCF
STATUS, RP0
;Bank0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h,101h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 module’s register
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
DS41124A-page 44
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “reset input”. This reset can
be generated by either of the two CCP modules
(Section 9.0). Register 7-1 shows the Timer1 control
register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PICmicro™ Mid-range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 7-1: TIMER1 CONTROL REGISTER (T1CON: 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit0
bit7
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3:
bit 2:
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
bit 0:
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (1) or RC1/T1OSI/CCP2
0= Internal clock (FINT)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Note 1: On the rising edge after the first falling edge.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 45
PIC16C745/765
7.1
Timer1 Operation in Timer Mode
7.2
Timer1 Operation in Synchronized
Counter Mode
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FINT. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The pres-
caler however will continue to increment.
FIGURE 7-1: TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
clock input
TMR1L
TMR1H
T1OSC
1
TMR1ON
on/off
T1SYNC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
FINT
Internal
0
(1)
Clock
2
SLEEP input
T1CKPS<1:0>
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS41124A-page 46
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
7.3
Timer1 Operation in Asynchronous
Counter Mode
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.1).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
In asynchronous counter mode, Timer1 can not be used
as a time-base for capture or compare operations.
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
7.3.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Note 1: Higher capacitance increases the stability of
oscillator but also increases the start-up time.
2: Since each resonator/crystal has its own charac-
teristics, the user should consult the resonator/
crystal manufacturer for appropriate values of
external components.
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems, since
the timer may overflow between the reads.
7.5
Resetting Timer1 using a CCP Trigger
Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in compare
mode to generate “special event trigger”
(CCP1M<3:0> = 1011), this signal will reset Timer1.
a
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Reading the 16-bit value requires some care. Examples
12-2 and 12-3 in the PICmicro™ Mid-Range MCU Fam-
ily Reference Manual (DS33023) show how to read and
write Timer1 when it is running in asynchronous mode.
Timer1 must be configured for either timer or synchro-
nized counter mode to take advantage of this feature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
7.4
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
7.6
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other reset except by the CCP1 and CCP2
special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other resets, the register is
unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 47
PIC16C745/765
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,
18Bh
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
USBIF
USBIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 48
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
8.1
Timer2 Prescaler and Postscaler
8.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP module(s). The TMR2 reg-
ister is readable and writable, and is cleared on any
device reset.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, MCLR reset, WDT reset
or BOR)
The input clock (FINT/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits T2CKPS<1:0>
(T2CON<1:0>).
TMR2 is not cleared when T2CON is written.
The Timer2 module has an 8-bit period register PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is ini-
tialized to FFh upon reset.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSPort module, which optionally uses it to generate
shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 8-1: TIMER2 BLOCK DIAGRAM
Sets flag
TMR2
bit TMR2IF
output (1)
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FINT
Register 8-1 shows the Timer2 control register.
Postscaler
2
Comparator
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
1:1 to 1:16
EQ
T2CKPS<1:0>
4
PR2 reg
T2OUTPS<3:0>
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
REGISTER 8-1: TIMER2 CONTROL REGISTER (T2CON: 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented bit,
read as ‘0’
bit7
- n = Value at POR reset
bit 7:
Unimplemented: Read as '0'
bit 6-3: TOUTPS<3:0>: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2:
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0: T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 49
PIC16C745/765
TABLE 8-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
USBIF
USBIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
8Ch
PIE1
11h
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
12h
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 50
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
CCP2 Module:
9.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register1 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is gen-
erated by a compare match and will reset Timer1 and
start an A/D conversion (if the A/D module is enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave Duty Cycle register
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in “Using the CCP Modules”
(AN594).
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 9-1 and Table 9-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
TABLE 9-1:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
CCP1 Module:
Capture
Compare
PWM
Timer1
Timer1
Timer2
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is gen-
erated by a compare match and will reset Timer1.
TABLE 9-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 time-base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
Compare
None.
None.
PWM
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 51
PIC16C745/765
REGISTER 9-1: CAPTURE/COMPARE/PWMN CONTROL REGISTER
(CCP1CON: 17H, CCP2CON: 1Dh)
U
U
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
—
—
DCnB1 DCnB0 CCPnM3 CCPnM2 CCPnM1 CCPnM0
bit7
bit0
- n = Value at POR reset
bit 7-6: Unimplemented: Read as ’0’
bit 5-4: DCnB<1:0>: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRnL.
bit 3-0: CCPnM<3:0>: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPn module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPnIF bit is set)
1001= Compare mode, clear output on match (CCPnIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPnIF bit is set, CCPn pin is unaffected)
1011= Compare mode, trigger special event (CCPnIF bit is set; CCPn resets TMR1or TMR3)
11xx= PWM mode
DS41124A-page 52
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
9.1.2
TIMER1 MODE SELECTION
9.1
Capture Mode
Timer1 must be running in timer mode or synchronized
counter mode for the CCP module to use the capture
feature. In asynchronous counter mode, the capture
operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as:
• Every falling edge
• Every rising edge
9.1.3
SOFTWARE INTERRUPT
• Every 4th rising edge
• Every 16th rising edge
When the capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
An event is selected by control bits CCP1M<3:0>
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value will be lost.
9.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned off,
or the CCP module is not in capture mode, the pres-
caler counter is cleared. Any reset will clear the pres-
caler counter.
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a cap-
ture condition.
FIGURE 9-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
Set flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
EXAMPLE 9-1: CHANGING BETWEEN
CAPTURE PRESCALERS
RC2/CCP1
Pin
CCPR1H
CCPR1L
TMR1L
CLRF
CCP1CON
;Turn CCP module off
MOVLW
NEW_CAPT_PS ;Load the W reg with
; the new precscaler
Capture
Enable
and
edge detect
; move value and CCP ON
TMR1H
MOVWF
CCP1CON
;Load CCP1CON with this
; value
CCP1CON<3:0>
Q’s
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 53
PIC16C745/765
9.2
Compare Mode
9.3
PWM Mode (PWM)
In pulse width modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M<3:0> (CCP1CON<3:0>). At the same
time, interrupt flag bit CCP1IF is set.
Figure 9-3 shows a simplified block diagram of the CCP
module in PWM mode.
FIGURE 9-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
FIGURE 9-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Special Event Trigger
CCP1CON<5:4>
Set flag bit CCP1IF
(PIR1<2>)
Duty Cycle Registers
CCPR1L
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
TRISC<2>
Output Enable
CCPR1H (Slave)
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
Q
R
S
Comparator
9.2.1
CCP PIN CONFIGURATION
RC2/CCP1
(Note 1)
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
TMR2
TRISC<2>
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
9.2.2
TIMER1 MODE SELECTION
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 9-4) has a time base (period) and
a time that the output stays high (duty cycle). The fre-
quency of the PWM is the inverse of the period (1/period).
9.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
FIGURE 9-4: PWM OUTPUT
Period
9.2.4
SPECIAL EVENT TRIGGER
CCP1(2)
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Duty Cycle
(1)
The special event trigger output of CCP1 resets the TMR1
register pair. This allows the CCPR1 register to effectively
be a 16-bit programmable period register for Timer1.
(1)
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Note 1: At this time, the TMR2 register is equal to the PR2 register.
2: Output signal is shown as asserted high.
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
DS41124A-page 54
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
9.3.1
PWM PERIOD
9.3.3
SET-UP FOR PWM OPERATION
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
The following steps should be taken when configuring
the CCP module for PWM operation:
1. Set the PWM period by writing to the PR2 register.
PWM period = [(PR2) + 1] • 4 • TOSC •
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
• TMR2 is cleared
5. Configure the CCP1 module for PWM operation.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
Note: The Timer2 postscaler (see Section 8.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
9.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
FINT
log( )
FPWM
Resolution
bits
=
log(2)
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 55
PIC16C745/765
TABLE 9-3:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF(1) ADIF
RCIF
—
TXIF
—
USBIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
—
—
PIE1
PSPIE(1) ADIE
RCIE
—
TXIE
—
USBIE
—
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
DCnB1
DCnB0
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
—
—
DCnB1
DCnB0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16C745; always maintain these bits clear.
TABLE 9-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
PIR1
PSPIF(1)
—
ADIF
—
RCIF
—
TXIF
—
USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
—
PIE1
PSPIE(1)
ADIE
—
RCIE
—
TXIE
—
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 module’s register
Timer2 module’s period register
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
CCP1CON
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0
DCnB1
DCnB0
1Bh
1Ch
1Dh
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
CCP2CON
—
—
CCP2M3 CCP2M2 CCP2M1 CCP2M0
DCnB1
DCnB0
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 56
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.1.2 FRAMES
10.0 UNIVERSAL SERIAL BUS
Information communicated on the bus is grouped in a
format called Frames. Each Frame is 1 ms in duration
and is composed of multiple transfers. Each transfer
type can be repeated more than once within a frame.
10.1
Overview
This section introduces a minimum amount of informa-
tion on USB. If you already have basic knowledge of
USB, you can safely skip this section. If terms like
Enumeration, Endpoint, IN/OUT Transactions, Trans-
fers and Low Speed/Full Speed are foreign to you,
read on.
10.1.3 POWER
Power has always been a concern with any device.
With USB, 5 volt power is now available directly from
the bus. Devices may be self-powered or bus-pow-
ered. Self-powered devices will draw power from a
wall adapter or power brick. On the other hand, bus-
powered devices will draw power directly from the
USB bus itself. There are limits to how much power
can be drawn from the USB bus. Power is expressed
in terms of “unit loads” (≤100 mA). All devices, includ-
ing Hubs, are guaranteed at least 1 unit load (low
power), but must negotiate with the host for up to 5
unit loads (high power). If the host determines that the
bus as currently configured cannot support a device’s
request for more unit loads, the device will be denied
the extra unit loads and must remain in a low power
configuration.
USB was developed to address the increased connec-
tivity needs of PC’s in the PC 2000 specification.
There was a base requirement to increase the band-
width and number of devices, which could be attached.
Also desired were the ability for hot swapping, user
friendly operation, robust communications and low
cost. The primary promoters of USB are Intel, Com-
paq, Microsoft and NEC.
USB is implemented as a Tiered Star topology, with
the host at the top, hubs in the middle, spreading out
to the individual devices at the end. USB is limited to
127 devices on the bus, and the tree cannot be more
than 6 levels deep.
USB is a host centric architecture. The host is always
the master. Devices are not allowed to “speak” unless
“spoken to” by the host.
10.1.4 END POINTS
At the lowest level, each device controls one or more
endpoints. An endpoint can be thought of as a virtual
port. Endpoints are used to communicate with a
device’s functions. Each endpoint is a source or sink of
data. Endpoints have both an In and Out direction
associated with it. Each device must implement end-
point 0 to support Control Transfers for configuration.
There are a maximum of 15 endpoints available for
use by each full speed device and 6 endpoints for
each slow speed device. Remember that the bus is
host centric, so In/Out is with respect to the host and
not the device.
Transfers take place at one of two speeds. Full Speed
is 12 Mb/s and Low Speed is 1.5 Mb/s. Full Speed
covers the middle ground of data intensive audio and
compressed video applications, while low speed sup-
ports less data intensive applications.
10.1.1 TRANSFER PROTOCOLS
Four transfer protocols are defined, each with
attributes:
- Isochronous Transfers, meaning equal time,
guarantee a fixed amount of data at a fixed
rate. This mode trades off guaranteed data
accuracy for guaranteed timeliness. Data
validity is not checked because there isn’t
time to re-send bad packets anyway and the
consequences of bad data are not cata-
strophic.
10.1.5 ENUMERATION
Prior to communicating on the bus, the host must see
that a new device has been connected and then go
through an “enumeration process”. This process
allows the host to ask the device to introduce itself,
and negotiate performance parameters, such as
power consumption, transfer protocol and polling rate.
The enumeration process is initiated by the host when
it detects that a new device has attached itself to the
bus. This takes place completely in the background
from the application process.
- Bulk Transfers are the converse of Isocho-
nous. Data accuracy is guaranteed, but time-
liness is not.
- Interrupt Transfers are designed to communi-
cate with devices which have a moderate
data rate requirement. Human Interface
Devices like keyboards are but one example.
For Interrupt Transfers, the key is the desire
to transfer data at regular intervals. USB peri-
odically polls these devices at a fixed rate to
see if there is data to transfer.
10.1.6 DESCRIPTORS
The USB specification requires a number of different
descriptors to provide information necessary to iden-
tify a device, specify its endpoints, and each endpoint’s
function. The five general categories of descriptors are
Device, Configuration, Interface, End Point and String.
- Control Transfers are used for configuration
purposes.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 57
PIC16C745/765
The Device descriptor provides general information
such as manufacturer, product number, serial number,
USB device class the product falls under, and the num-
ber of different configurations supported. There can
only be one Device descriptor for any given applica-
tion.
10.2
Application Isolation
Microchip provides a comprehensive support library of
standard chapter 9 USB commands. These libraries
provide a software layer to insulate the application
software from having to handle the complexities of the
USB protocol. A simple Put/Get interface is imple-
mented to allow most of the USB processing to take
place in the background within the USB interrupt ser-
vice routine. Applications are encouraged to use the
provided libraries during both enumeration and config-
ured operation.
The Configuration descriptor provides information on
the power requirements of the device and how many
different interfaces are supported when in this configu-
ration. There may be more than one configuration for
each device, (i.e., a high power device may also sup-
port a low power configuration).
10.3
Introduction
The Interface descriptor details the number of end-
points used in this interface, as well as the class driver
to use should the device support functions in more
than just one device class. There can only be one
Interface descriptor for each configuration.
The USB peripheral module supports Low Speed con-
trol and interrupt (IN and OUT) transfers. The imple-
mentation supports 3 endpoint numbers (0, 1, 2) for a
total of 6 endpoints.
The Endpoint descriptor details the actual registers for
a given function. Information is stored about the trans-
fer types supported, direction (In/Out), bandwidth
requirements and polling interval. There may be more
than one endpoint in a device, and endpoints may be
shared between different interfaces.
The following terms are used in the description of the
USB module:
• MCU - The core processor and corresponding
firmware
• SIE - Serial Interface Engine: That part of the
USB that performs functions such as CRC gener-
ation and clocking of the D+ and D- signals.
Many of the four descriptors listed above will reference
or index different String descriptors. String descriptors
are used to provide vendor specific or application spe-
cific information. They may be optional and are
encoded in “Unicode” format.
• USB - The USB module including SIE and regis-
ters
• Bit Stuffing - forces insertion of a transition on D+
and D- to maintain clock synchronization
10.1.7 DEVICE CLASSES/CLASS DRIVERS
• BD - Buffer Descriptor
Operating systems provide drivers which group func-
tions together by common device types called classes.
Examples of device classes include, but are not limited
to, storage, audio, communications and HID (Human
Interface). Class drivers for a given application are ref-
erenced in both the Device descriptor and Interface
descriptor. Most applications can find a Class Driver
which supports the majority of their function/command
needs. Vendors who have a requirement for specific
commands which are not supported by any of the
standard class drivers may provide a vendor specific
“.inf” file or driver for extra support.
• BDT - Buffer Descriptor Table
• EP - Endpoint (combination of endpoint number
and direction)
• IN - Packet transfer into the host
• OUT - Packet transfer out of the host
10.4
USB Transaction
When the USB transmits or receives data the SIE will
first check that the corresponding endpoint and direc-
tion Buffer Description UOWN bit equals 1. The USB
will move the data to or from the corresponding buffer.
When the TOKEN is complete, the USB will update the
BD status and change the UOWN bit to 0. The USTAT
register is updated and the TOK_DNE interrupt is set.
When the MCU processes the TOK_DNE interrupt it
reads the USTAT register, which gives the MCU the
information it needs to process the endpoint. At this
point the MCU will process the data and set the corre-
sponding UOWN bit. Figure 10-1 shows a time line of
how a typical USB token would be processed.
10.1.8 SUMMARY
While a complete USB overview is beyond the scope
of this document, a few key concepts must be noted.
Low speed communication is designed for devices,
which in the past, used an interrupt to communicate
with the host. In the USB scheme, devices do not
directly interrupt the processor when they have data.
Instead the host periodically polls each device to see if
they have any data. This polling rate is negotiated
between the device and host, giving the system a
guaranteed latency.
For more details on USB, see the USB V1.1 spec,
available from the USB website at www.usb.org.
DS41124A-page 58
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 10-1: USB TOKENS
USB RESET
USB_RST
Interrupt Generated
SETUP TOKEN
DATA
DATA
ACK
TOK_DNE
Interrupt Generated
IN TOKEN
ACK
TOK_DNE
Interrupt Generated
OUT TOKEN
DATA
ACK
TOK_DNE
Interrupt Generated
= Host
= Device
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 59
PIC16C745/765
10.5.1.1 USB Interrupt Register (UIR)
10.5
USB Register Map
The USB Interrupt Status Register (UIR) contains flag
bits for each of the interrupt sources within the USB.
Each of these bits are qualified with their respective
interrupt enable bits (see the Interrupt Enable Register
UIE). All bits of the register are logically OR’ed
together to form a single interrupt source for the micro-
processor interrupt found in PIR1 (USBIF). Once an
interrupt bit has been set, it must be cleared by writing
a 0.
The USB Control Registers, Buffer Descriptors and
Buffers are located in Bank 3.
10.5.1 CONTROL AND STATUS REGISTERS
The USB module is controlled by 7 registers, plus
those that control each endpoint and endpoint/direc-
tion buffer.
REGISTER 10-1: USB INTERRUPT FLAGS REGISTER (UIR: 190h)
U-0
U-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
—
—
STALL UIDLE TOK_DNE ACTIVITY UERR USB_RST
bit0
R = Readable bit
C = Clearable bit
U = Unimplemented bit,
read as ‘0’
bit7
-n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'.
bit 5:
bit 4:
STALL: A STALL handshake was sent by the SIE.
UIDLE: This bit is set if the USB has detected a constant idle on the USB bus signals for 3 ms. The idle
timer is reset by activity on the USB bus. Once a IDLE condition has been detected, the user may wish
to place the USB module in SUSPEND by setting the SUSPEND bit in the UCTRL register.
bit 3:
bit 2:
TOK_DNE: This bit is set when the current token being processed is complete. The microprocessor
should immediately read the USTAT register to determine the Endpoint number and direction used for
this token. Clearing this bit causes the USTAT register to be cleared or the USTAT holding register to be
loaded into the STAT register if another token has been processed.
ACTIVITY: Activity on the D+/D- lines will cause the SIE to set this bit. Typically this bit is unmasked
following detection of SLEEP. Users must enable the activity interrupt in the USB Interrupt Register
(UIE: 191h) prior to entering suspend.
bit 1:
bit 0:
UERR: This bit is set when any of the error conditions within the ERR_STAT register has occurred. The
MCU must then read the ERR_STAT register to determine the source of the error.
USB_RST: This bit is set when the USB has decoded a valid USB reset. This will inform the MCU to write
00h into the address register and enable endpoint 0. USB_RST is set once a USB reset has been
detected for 2.5 microseconds. It will not be asserted again until the USB reset condition has been
removed, and then reasserted.
Note 1: Bits can only be modified when UCTRL.SUSPND = 0.
DS41124A-page 60
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.5.1.2 USB Interrupt Enable Register (UIE)
The USB Interrupt Enable Register (UIE) contains
enable bits for each of the interrupt sources within the
USB. Setting any of these bits will enable the respec-
tive interrupt source in the UIR register. The values in
the UIE register only affect the propagation of an inter-
rupt condition to the PIE1 register. Interrupt conditions
can still be polled and serviced.
REGISTER 10-2: USB INTERRUPT ENABLE REGISTER (UIE: 191h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
STALL
UIDLE TOK_DNE ACTIVITY UERR USB_RST
bit0
R = Readable bit
W = Writable bit
bit7
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7-6: Unimplemented: Read as '0'.
bit 5:
bit 4:
bit 3:
STALL: Set to enable STALL interrupts.
1= STALL interrupt enabled
0= STALL interrupt disabled
UIDLE: Set to enable IDLE interrupts.
1= IDLE interrupt enabled
0= IDLE interrupt disabled
TOK_DNE: Set to enable TOK_DNE interrupts.
1= TOK_DNE interrupt enabled
0= TOK_DNE interrupt disabled
bit 2(1): ACTIVITY: Set to enable ACTIVITY interrupts.
1= ACTIVITY interrupt enabled
0= ACTIVITY interrupt disabled
bit 1:
bit 0:
UERR: Set to enable ERROR interrupts.
1= ERROR interrupt enabled
0= ERROR interrupt disabled
USB_RST: Set to enable USB_RST interrupts.
1= USB_RST interrupt enabled
0= USB_RST interrupt disabled
Note 1: This interrupt is the only interrupt active during UCTRL suspend = 1.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 61
PIC16C745/765
10.5.1.3 USB Error Interrupt Status Register (UEIR)
interrupt bit has been set it must be cleared by writing
a zero to the respective interrupt bit. Each bit is set as
soon as the error condition is detected. Thus, the inter-
rupt will typically not correspond with the end of a
token being processed.
The USB Error Interrupt Status Register (UEIR) con-
tains bits for each of the error sources within the USB.
Each of these bits are enabled by their respective error
enable bits (UEIE). The result is OR’ed together and
sent to the ERROR bit of the UIR register. Once an
REGISTER 10-3: USB ERROR INTERRUPT FLAGS STATUS REGISTER (UEIR: 192h)
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8 CRC16 CRC5 PID_ERR
R = Readable bit
C = Clearable bit
U = Unimplemented
bit, read as ‘0’
-n = Value at POR
reset
bit7
bit0
bit 7:
bit 6:
BTS_ERR: A bit stuff error has been detected.
OWN_ERR: This bit is set if the USB is processing a token and the OWN bit within the BDT is equal to 0
(signifying that the microprocessor owns the BDT and the SIE does not have access to the BDT). If process-
ing an IN TOKEN this would cause a transmit data underflow condition. Processing an OUT or SETUP
TOKEN would cause a receive data overflow condition.
bit 5:
bit 4:
WRT_ERR: Write Error. A write by the MCU to the USB Buffer Descriptor Table or Buffer area was unsuc-
cessful.
BTO_ERR: This bit is set if a bus turnaround time-out error has occurred. This USB uses a bus turnaround
timer to keep track of the amount of time elapsed between the token and data phases of a SETUP or OUT
TOKEN or the data and handshake phases of a IN TOKEN. If more than 17-bit times are counted from the
previous EOP before a transition from IDLE, a bus turnaround time-out error will occur.
bit 3:
DFN8: The data field received was not 8 bits. The USB Specification 1.1 specifies that data field must be an
integral number of bytes. If the data field was not an integral number of bytes this bit will be set.
bit 2:
bit 1:
CRC16: The CRC16 failed.
CRC5: This interrupt will detect CRC5 error in the token packets generated by the host. If set the token
packet was rejected due to a CRC5 error.
bit 0:
PID_ERR: The PID check field failed.
Note 1: Bits can only be modified when UCTRL.SUSPND = 0.
DS41124A-page 62
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.5.1.4 Error Interrupt Enable Register (UEIE)
The USB Error Interrupt Enable Register (UEIE) con-
tains enable bits for each of the error interrupt sources
within the USB. Setting any of these bits will enable
the respective error interrupt source in the UEIR regis-
ter.
REGISTER 10-4: USB ERROR INTERRUPT ENABLE REGISTER (UEIE: 193h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
R/W-0
CRC16 CRC5 PID_ERR
bit0
BTS_ERR OWN_ERR WRT_ERR BTO_ERR DFN8
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
-n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
BTS_ERR: Set this bit to enable BTS_ERR interrupts.
1= BTS_ERR interrupt enabled
0= BTS_ERR interrupt disabled
OWN_ERR: Set this bit to enable OWN_ERR interrupts.
1= OWN_ERR interrupt enabled
0= OWN_ERR interrupt disabled
WRT_ERR: Set this bit to enable WRT_ERR interrupts.
1= WRT_ERR interrupt enabled
0= WRT_ERR interrupt disabled
BTO_ERR: Set this bit to enable BTO_ERR interrupts.
1= BTO_ERR interrupt enabled
0= BTO_ERR interrupt disabled
DFN8: Set this bit to enable DFN8 interrupts.
1= DFN8 interrupt enabled
0= DFN8 interrupt disabled
CRC16: Set this bit to enable CRC16 interrupts.
1= CRC16 interrupt enabled
0= CRC16 interrupt disabled
CRC5: Set this bit to enable CRC5 interrupts.
1= CRC5 interrupt enabled
0= CRC5 interrupt disabled
PID_ERR: Set this bit to enable PID_ERR interrupts.
1= PID_ERR interrupt enabled
0= PID_ERR interrupt disabled
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 63
PIC16C745/765
10.5.1.5 Status Register (USTAT)
USB transaction is performed before the TOK_DNE
interrupt is serviced the USB will store the status of the
next transaction in the STAT FIFO. Thus, the STAT reg-
ister is actually a four byte FIFO which allows the MCU
to process one transaction while the SIE is processing
the next. Clearing the TOK_DNE bit in the INT_STAT
register causes the SIE to update the STAT register
with the contents of the next STAT value. If the data in
the STAT holding register is valid, the SIE will immedi-
ately reassert the TOK_DNE interrupt.
The USB Status Register reports the transaction sta-
tus within the USB. When the MCU recognizes a
TOK_DNE interrupt, this register should be read to
determine the status of the previous endpoint commu-
nication. The data in the status register is valid when
the TOK_DNE interrupt bit is asserted.
The USTAT register is actually a read window into a
status FIFO maintained by the USB. When the USB
uses a BD, it updates the status register. If another
REGISTER 10-5: USB STATUS REGISTER (USTAT: 194h)
U-0
U-0
U-0
R-X
R-X
R-X
IN
U-0
U-0
ENDP1
ENDP0
—
—
—
—
—
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-5: Unimplemented: Read as ’0’.
bit 4-3: ENDP<1:0>: These bits encode the endpoint address that received or transmitted the previous token.
This allows the microprocessor to determine which BDT entry was updated by the last USB transaction.
bit 2:
IN: This bit indicates the direction of the last BD that was updated.
1= The last transaction was an IN TOKEN
0= The last transaction was an OUT or SETUP TOKEN
bit 1-0: Unimplemented: Read as ’0’.
DS41124A-page 64
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.5.1.6 USB Control Register (UCTRL)
The control register provides various control and con-
figuration information for the USB.
REGISTER 10-6: USB CONTROL REGISTER (UCTRL: 195h)
U-0
U-0
R-X
SE0
R/C-0
R/W-0
R/W-0
R/W-0
U-0
PKT_DIS Config_Bit RESUME SUSPND
—
—
—
R = Readable bit
W = Writable bit
bit7
bit0
C = Clearable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-6: Unimplemented: Read as ’0’.
bit 5:
SE0: Live Single Ended Zero. This status bit indicates that the D+ and D- lines are both pulled to low.
1= single ended zero being received
0= single ended zero not being received
bit 4
PKT_DIS: The PKT_DIS bit informs the MCU that the SIE has disabled packet transmission and recep-
tion. Clearing this bit allows the SIE to continue token processing. This bit is set by the SIE when a Setup
Token is received allowing software to dequeue any pending packet transactions in the BDT before resum-
ing token processing. The PKT_DIS bit is set under certain conditions such as back to back SETUP
tokens. This bit is not set on every SETUP token and can be modified only when UCTRL.SUSPND = 0.
bit 3:
bit 2:
Config_Bit: Configuration bit used by firmware during enumeration.
RESUME: Setting this bit will allow the USB to execute resume signaling. This will allow the USB to per-
form remote wake-up. Software must set RESUMEto 1 for 10 mS then clear it to 0 to enable remote wake-
up. For more information on RESUMEsignaling, see Section 7.1.7.5, 11.9 and 11.4.4 in the USB 1.1 spec-
ification.
1= perform Resume signaling
0= normal operation
bit 1:
bit 0:
SUSPND: Suspends USB operation and clocks and places the module in low power mode. This bit will
generally be set in response to a UIDLEinterrupt. It will generally be reset after an ACTIVITY interrupt.
The VUSB pin will still be driven, however the transceiver outputs are disabled.
1= USB module in power conserve mode
0= USB module normal operation
Unimplemented: Read as ’0’.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 65
PIC16C745/765
10.5.1.7 USB Address Register (UADDR)
The Address Register (UADDR) contains the unique
USB address that the USB will decode. The register is
reset to 00h after the reset input has gone active or the
USB has decoded a USB reset signaling. That will ini-
tialize the address register to decode address 00h as
required by the USB specification. The USB address
must be written by the MCU during the USB SETUP
phase.
REGISTER 10-7: USB ADDRESS REGISTER (UADDR: 196h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR6 ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
—
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
bit 7:
Unimplemented: Read as ’0’.
bit 6-0: ADDR<6:0>: This 7-bit value defines the USB address that the USB will decode.
10.5.1.8 USB Software Status Register
This register is used by the USB firmware libraries for
USB status.
REGISTER 10-8: RESERVED SOFTWARE LIBRARY REGISTER (USWSTAT: 197H):.
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R = Readable bit
W = Writable bit
6
5
4
3
2
1
0
7
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
Function IDs
Configuration Status
10.5.1.9 Endpoint Registers
Each endpoint is controlled by an Endpoint Control
Register. The PIC16C745/765 supports Buffer
Descriptors (BD) for the following endpoints:
- EP0 Out
- EP0 In
- EP1 Out
- EP1 In
- EP2 Out
- EP2 In
The user will be required to disable unused Endpoints
and directions using the Endpoint Control Registers.
DS41124A-page 66
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.5.1.10 USB Endpoint Control Register (EPCn)
The Endpoint Control Registers contains the endpoint
control bits for each of the 6 endpoints available on
USB for a decoded address. These four bits define the
control necessary for any one endpoint. Endpoint 0
(ENDP0) is associated with control pipe 0 which is
required by USB for all functions (IN, OUT, and
SETUP). Therefore, after a USB_RST interrupt has
been received the microprocessor should set ENDPT0
to contain 06h.
REGISTER 10-9: USB ENDPOINT CONTROL REGISTER (UEPn: 198H-19Ah)
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL
—
—
—
—
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplementedbit,
read as ‘0’
-n = Value at POR reset
bit 7-4: Unimplemented: Read as ’0’.
bit 3-1: EP_CTL_DIS, EP_OUT_EN, EP_IN_EN: These three bits define if an endpoint is enabled and the direc-
tion of the endpoint. The endpoint enable/direction control is defined as follows:
EP_CTL_DIS EP_OUT_EN EP_IN_EN Endpoint Enable/Direction Control
X
X
X
1
0
0
1
1
1
0
1
0
1
1
Disable Endpoint
Enable Endpoint for IN tokens only
Enable Endpoint for OUT tokens only
Enable Endpoint for IN and OUT tokens
Enable Endpoint for IN, OUT, and SETUP tokens
0
bit 0:
EP_STALL: When this bit is set it indicates that the endpoint is stalled. This bit has priority over all other
control bits in the Endpoint Enable register, but is only valid if EP_IN_EN=1 or EP_OUT_EN=1. Any access
to this endpoint will cause the USB to return a STALL handshake. The EP_STALL bit can be set or cleared
by the SIE. Refer to the USB 1.1 Specification, Sections 4.4.4 and 8.5.2 for more details on the STALL
protocol.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 67
PIC16C745/765
10.6
Buffer Descriptor Table (BDT)
To efficiently manage USB endpoint communications
the USB implements a Buffer Descriptor Table (BDT)
in register space. Every endpoint requires a 4 byte
Buffer Descriptor (BD) entry. Because the buffers are
shared between the MCU and the USB, a simple
semaphore mechanism is used to distinguish which is
allowed to update the BD and buffers in system mem-
ory. The UOWN bit is cleared when the BD entry is
“owned” by the MCU. When the UOWN bit is set to 1,
the BD entry and the buffer in system memory is
owned by the USB. The MCU should not modify the
BD or its corresponding data buffer.
The Buffer Descriptors provide endpoint buffer control
information for the USB and MCU. The Buffer Descrip-
tors have different meaning based on the value of the
UOWN bit.
The USB Controller uses the data stored in the BDs
when UOWN = 1 to determine:
•
•
•
•
Data0 or Data1 PID
Data toggle synchronization enable
Number of bytes to be transmitted or received
Starting location of the buffer
The MCU uses the data stored in the BDs when
UOWN = 0 to determine:
•
•
•
Data0 or Data1 PID
The received TOKEN PID
Number of bytes transmitted or received
Each endpoint has a 4 byte Buffer Descriptor and
points to a data buffer in the USB dual port register
space. Control of the BD and buffer would typically be
handled in the following fashion:
•
The MCU verifies UOWN = 0, sets the BDndAL to
point to the start of a buffer, if necessary fills the
buffer, then sets the BDndST byte to the desired
value with UOWN = 1.
•
When the host commands an in or out transac-
tion, the Serial Interface Engine (SIE) performs
the following:
- Get the buffer address
- Read or write the buffer
- Update the USTAT register
- Update the buffer descriptors with the packet
ID (PID) value
- Set the data 0/1 bit
- Update the byte count
- Clear the UOWN bit
•
The MCU is interrupted and reads the USTAT,
translates that value to a BD, where the UOWN,
PID, Data 0/1, and byte count values are checked.
DS41124A-page 68
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
REGISTER 10-10: BUFFER DESCRIPTOR STATUS REGISTER. BITS WRITTEN BY THE MCU
(BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h)
W-X
UOWN DATA0/1
bit7
W-X
U-X
U-X
W-X
W-X
U-X
U-X
—
—
DTS
BSTALL
—
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
-n = Value at POR reset
X = Don’t care
bit 7:
UOWN: USB Own. This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this
bit when it has completed a token. This byte of the BD should always be the last byte the MCU updates
when it initializes a BD. Once the BD has been assigned to the USB, the MCU should not change it in any
way.
1= USB has exclusive access to the BD. The MCU should not modify the BD or buffer.
0= The MCU has exclusive access to the BD. The USB ignores all other fields in the BD.
bit 6:
DATA0/1: This bit defines the type of data toggle packet that was transmitted or received.
1= Data 1 packet
0= Data 0 packet
bit 5-4: Reserved: Read as ’X’.
bit 3:
DTS: Setting this bit will enable the USB to perform Data Toggle Synchronization. If a packet arrives with
an incorrect DTS, it will be ignored and the buffer will remain unchanged.
1= Data Toggle Synchronization is performed
0= No Data Toggle Synchronization is performed
bit 2:
BSTALL: Buffer Stall. Setting this bit will cause the USB to issue a STALL handshake if a token is received
by the SIE that would use the BD in this location. The BD is not consumed by the SIE (the own bit remains
and the rest of the BD are unchanged) when a BSTALL bit is set.
bit 1-0: Reserved: Read as ’X’.
Note: Recommend that users not use BSF, BCF due to the dual functionality of this register.
REGISTER 10-11: BUFFER DESCRIPTOR STATUS. BITS READ BY THE MCU.
(BDndST: 1A0h, 1A4h, 1A8h, 1ACh, 1B0h, 1B4h)
R/W-0
UOWN DATA0/1
bit7
R/W-X
R/W-X
PID3
R/W-X
PID2
R/W-X
PID1
R/W-X
PID0
U-X
—
U-X
—
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit0
-n = Value at POR reset
X = Don’t care
bit 7:
UOWN: USB Own. This UOWN bit determines who currently owns the buffer. The SIE writes a 0 to this
bit when it has completed a token. This byte of the BD should always be the last byte the MCU updates
when it initializes a BD. Once the BD has been assigned to the USB, the MCU should not change it in any
way.
1= USB has exclusive access to the BD. The MCU should not modify the BD or buffer.
0= The MCU has exclusive access to the BD. The USB ignores all other fields in the BD.
bit 6:
DATA0/1: This bit defines the type of data toggle packet that was transmitted or received.
1= Data 1 packet
0= Data 0 packet
bit 5-2: PID<3:0>: Packet Identifier. The received token PID value
bit 1-0: Reserved: Read as 'X'.
Note: Recommend that users not use BSF, BCF due to the dual functionality of this register.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 69
PIC16C745/765
REGISTER 10-12: BUFFER DESCRIPTOR BYTE COUNT (BDndBC: 1A1h, 1A5h, 1A9h, 1ADh, 1B1h,
1B5h))
U-X
—
U-X
—
U-X
—
U-X
—
R/W-X
BC3
R/W-X
BC2
R/W-X
BC1
R/W-X
BC0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-4: Reserved: Read as ’X’.
bit 3-0: BC<3:0>: The Byte Count bits represent the number of bytes that will be transmitted for an IN TOKEN or
received during an OUT TOKEN. Valid byte counts are 0 - 8. The SIE will change this field upon the com-
pletion of an OUT or SETUP token with the actual byte count of the data received.
REGISTER 10-13: BUFFER DESCRIPTOR ADDRESS LOW (BDndAL: 1A2h, 1A6h, 1AAh, 1AEh,
1B2h, 1B6h)
R/W-X
BA7
R/W-X
BA6
R/W-X
BA5
R/W-X
BA4
R/W-X
BA3
R/W-X
BA2
R/W-X
BA1
R/W-X
BA0
R = Readable bit
W = Writable bit
bit7
bit0
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
X = Don’t care
bit 7-0: BA<7:0>: Buffer Address. The base address of the buffer controlled by this endpoint. The upper order bit
address (BA8) of the 9-bit address is assumed to be 1h. This value must point to a location within the dual
port memory space (1B8h - 1DFh). The upper order bits of the address are assumed to point to Bank 3.
Note 1: This register should always contain a value between B8h-DFh.
10.6.1 ENDPOINT BUFFERS
10.7.1.1 VUSB Output
Endpoint buffers are located in the Dual Port RAM
area. The starting location of an endpoint buffer is
determined by the Buffer Descriptor.
The VUSB provides a 3.3V nominal output. This drive
current is sufficient for a pull-up only.
10.8
USB Software Libraries
10.7
TRANSCEIVER
Microchip Technology provides a comprehensive set
of Chapter 9 Standard requests functions to aid devel-
opers in implementing their designs. See Microchip
Technology’s website for the latest version of the soft-
ware libraries.
An on-chip integrated transceiver is included to drive
the D+/D- physical layer of the USB.
10.7.1 REGULATOR
A 3.3V regulator provides the D+/D- drives with power.
A +20% 10nF capacitor is required on VUSB for regula-
tor stability.
TABLE 10-1: USB PORT FUNCTIONS
Input
Type
Output
Type
Name
Function
Description
VUSB
VUSB
D-
—
Power
USB
3.3V for pull up resistor
USB Differential Bus
USB Differential Bus
D-
USB
USB
D+
D+
USB
Legend:
OD = open drain, ST = Schmitt Trigger
DS41124A-page 70
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
10.9.3 INTERRUPT STRUCTURE CONCERNS
10.9.3.1 Processor Resources
10.9
USB Firmware Users Guide
10.9.1 INTRODUCING THE USB SOFTWARE
INTERFACE
Most of the USB processing occurs via the interrupt
and thus is invisible to application. However it still con-
sumes processor resources. These include ROM,
RAM, Common RAM, Stack Levels and processor
cycles. This section attempts to quantify the impact on
each of these resources, and shows ways to avoid
conflicts.
Microchip provides a layer of software that handles the
lowest level interface so your application won’t have to.
This provides a simple Put/Get interface for communi-
cation. Most of the USB processing takes place in the
background through the Interrupt Service Routine.
From the application viewpoint, the enumeration pro-
cess and data communication takes place without fur-
ther interaction.
These are the considerations you'll need to take into
account if you write your own Interrupt Service Rou-
tine: Save W, Status, FSR and PCLATH which are the
file registers that may be corrupted by servicing the
USB interrupt.
FIGURE 10-2: USB SOFTWARE INTERFACE
Main Application
We provide a skeleton ISR which will do this for you,
and includes tests for each of the possible ISR bits.
This provides a good place to start from if you haven't
already written your own. See file USB_INT.ASM.
Put
Get
Init
10.9.3.2 Stack Levels
USB Peripheral
The hardware stack on the device is only 8 levels
deep. So the worst case call between the application
and ISR can only be 8 levels. The enumeration pro-
cess requires 6 levels, so it's best if the main applica-
tion holds off on any processing until enumeration is
complete. ConfiguredUSB is a macro that waits until
the enumeration process is complete for exactly this
purpose.
USB
10.9.2 INTEGRATING USB INTO YOUR
APPLICATION
The latest version of the USB interface software is
available on Microchip Technology’s website. See
http://www.microchip.com/
Communicating on USB is similar to communicating
via a hardware USART. The main difference is that a
USART typically works on a single byte at a time,
where USB operates on a buffer of up to 8 bytes at a
time.
10.9.3.3 ROM
The code required to support the USB interrupt,
including the chapter 9 interface calls, but not including
the descriptor tables is about 1kW. The descriptor and
string descriptor tables can each take up to an addi-
tional 256W. The location of these parts is not
restricted, and the linker script may be edited to control
the placement of each part. See the Strings and
Descriptors sections in the linker script
There is one function defined to start the enumeration
process and two additional functions are defined for
moving buffers between the main application and the
USB peripheral. InitUSB initializes the USB peripheral
allowing the host to enumerate the device. Then for
normal data communications, function PutUSB sends
data to the host and function GetUSB receives data
from the host.
10.9.3.4 RAM
With the exception of Common RAM discussed below,
servicing the USB interrupt costs ~40 bytes of RAM in
Bank 2. That leaves all the General Purpose RAM in
banks zero and one, plus half of bank two available for
your application to use.
There's a lot that happens behind the scenes to make
the communication work, but these calls are all an
application needs to communicate on the bus. The
rest is handled on an interrupt basis.
InitUSB initializes the Buffer Descriptor table, and
enables the USB interrupt so enumeration can begin.
The actual enumeration process occurs automatically,
driven by the host and interrupt service routine. The
macro ConfiguredUSB waits until the device is in the
CONFIGURED mode and ready to go. The time
required to enumerate is completely dependent on the
host and bus loading.
10.9.3.5 Common RAM usage
The PIC16C745/765 has 16 bytes of common RAM.
These are the last 16 addresses in each bank and all
refer to the same 16 bytes of memory without regard
to which register bank is currently addressed by the
RP0 and RP1 bits.
These are particularly useful when responding to inter-
rupts. When an interrupt occurs, the ISR doesn't
immediately know which bank is addressed. With
devices that don't support common RAM, the W regis-
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 71
PIC16C745/765
ter must be provided for in each bank. The 16C745/
765 can save the appropriate registers in Common
RAM and not have to waste a byte in each bank for W
register.
GetUSB (Buffer Pointer, Endpoint) returns data sent
from the host. If there is a buffer ready (i.e., data has
been received from the host) it is copied to the desti-
nation pointed to by FSR/IRP (A buffer pointer in FSF/
IRP and the endpoint number in W must be provided.).
If no data is available, it returns a failure code. Thus,
the functions of polling for buffer ready and copying the
data are combined into the one function.
10.9.3.6 Buffer allocation
The PIC16C745/765 has 64 bytes of Dual Port RAM.
24 are used for the Buffer Descriptor Table (BDT) leav-
ing 40 bytes for buffers.
ServiceUSBInt handles all interrupts generated by the
USB peripheral. First it copies the active buffer to
common RAM which provides a quick turn around on
the buffer in dual port RAM and also to avoids having
to switch banks during processing of the buffer.
Endpoint 0 IN and OUT need dedicated buffers since a
setup transaction can never be NAKed. That leaves
three buffers for four possible Endpoints. But the USB
spec requires that low speed devices are only allowed
2 endpoints (USB 1.1 paragraph 5.3.1.2), where an
endpoint is a simplex connection that defined by the
combination of Endpoint number and direction.
StallUSBEP/UnstallUSBEP sets or clears the stall bit
in the endpoint control register. The stall bit indicates
to the host that user intervention is required and until
such intervention is made, further attempts to commu-
nicate with the endpoint will not be successful. Once
the user intervention has been made, UnstallUSBEP
will clear the bit allowing communications to take
place. These calls are useful to signal to the host that
user intervention is required. An example of this might
be a printer out of paper.
The default configuration allocates individual buffers to
EP0 OUT, EP0 In, EP1 Out, and EP1 In. The last
buffer is shared between EP2 In and EP2 Out. Again,
the spec says low speed devices can only use 2 end-
points beyond EP0. This configuration supports most
of the possible combinations of endpoints (EP1 OUT
and EP1 IN, EP1OUT and EP2IN, EP1 OUT and EP2
OUT, EP1 IN and EP2 OUT, EP1 IN and EP2 IN). The
only combination that is not supported by this configu-
ration is Endpoint 2 IN and Endpoint 2 OUT. If your
application needs both EP2 IN and EP2 OUT, the func-
tion USBReset will need to be edited to give each of
these dedicated buffers at the expense of EP1.
CheckSleep Tests the UCTRL.UIDLE bit if set, indi-
cating that there has been no activity on the bus for 3
mS, puts the device to sleep. This puts the part into a
low power standby mode until awakened by bus activ-
ity. This has to be handled outside the ISR because we
need the interrupt to wake us from sleep, and also
because the application may not be ready to sleep
when the interrupt occurs. Instead, the application
should periodically call this function to poll the bit when
the device is in a good place to sleep.
10.9.4 FUNCTION CALL REFERENCE
Interface between the Application and Protocol layer
takes place in three main functions: InitUSB, PutUSB
and GetUSB.
Prior to putting the device to sleep, it enables the activ-
ity interrupt so the device will be awakened by the first
transition on the bus. The device will immediately
jump to the ISR, recognizing the activity interrupt,
which then disables the interrupt and resumes pro-
cessing with the instruction following the CheckSleep
call.
InitUSB should be called by the main program imme-
diately upon power-up. It sets up the Buffer Descriptor
Table, transitions the part to the Powered state, and
prepares the device for enumeration. At this point the
USB Reset is the only USB interrupt allowed, prevent-
ing the part from responding to anything on the bus
until it’s been reset. The USB Reset interrupt transi-
tions the part to the default state where it responds to
commands on address zero. When it receives a SET
ADDRESS command, the device transitions to the
addressed state and now responds to commands on
the new address.
ConfiguredUSB (Macro) Continuously polls the enu-
meration status bits and waits until the device has
been configured by the host.
10.9.5 BEHIND THE SCENES
The ISR calls ServiceUSBInt, which then further has
to mask the USB Interrupt register with the USB Inter-
rupt Enable bits, then see what caused the interrupt.
InitUSB only enables the Reset interrupt (USB_RST).
This prevents the device from responding to anything
on the bus until it’s been reset by the host. When the
reset is received, the Buffer Descriptors are initialized,
most of the rest of the interrupts are unmasked and
the device transitions from the POWERED to
DEFAULT state. Now it can respond to commands on
address zero. From there the rest of the enumeration
process takes place, including assigning an address to
the device through the SET_ADDRESS command and
PutUSB (Buffer pointer, Buffer size, Endpoint) sends
data up to the host. The pointer to the block of data to
transmit, is in the FSR/IRP, and the block size and
endpoint is passed in W register. If the IN buffer is
available for that endpoint, the block of data is copied
to the buffer, then the Data 0/1 bit is flipped and the
owns bit is set. A buffer not available would occur
when it has been previously loaded and the host has
not requested that the USB peripheral transmit it. In
this case, a failure code would be returned so the
application can try again later.
selecting
a
configuration
through
the
DS41124A-page 72
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
SET_CONFIGURATION command. Once the device
is configured, the application can communicate with
the host using the GetUSB and PutUSB calls.
CheckSleep is a separate call that takes the bus idle
one step further and puts the device to sleep if the
USB peripheral has detected no activity on the bus.
This powers down most of the device to minimal cur-
rent draw. This call should be made at a point in the
main loop where all other processing is complete.
The USB peripheral detects several different errors
and handles most internally. The USB_ERR interrupt
notifies the microcontroller that an error has occurred.
No action is required by the device when an error
occurs. Instead the errors are simply acknowledged
and counted. There is no mechanism to pull the
device off the bus if there are too many errors. If this
behavior is desired it must be implemented in the
application.
10.9.6 EXAMPLES
This example shows how the USB functions are used.
This example first initializes the USB peripheral which
allows the host to enumerate the device. The enumer-
ation process occurs in the background, via an Inter-
rupt service routine.
This function waits until
The Activity interrupt is left disabled until the USB
peripheral detects no bus activity for 3 mS. Then it
suspends the USB peripheral and enables the activity
interrupt. The activity interrupt then reactivates the
USB peripheral when bus activity resumes so process-
ing may continue.
enumeration is complete, and then polls EP1 OUT to
see if there is any data available. When a buffer is
available, it is copied to the IN buffer. Presumably your
application would do something more interesting with
the data than this example.
; ******************************************************************
; Demo program that initializes the USB peripheral, allows the Host
;
to Enumerate, then copies buffers from EP1OUT to EP1IN.
; ******************************************************************
main
call
InitUSB
; Set up everything so we can enumerate
ConfiguredUSB
; wait here until we have enumerated.
idleloop
CheckEP1
call
CheckSleep
; Ok, here’s a good point to put part to sleep if no activity on the bus.
; Check Endpoint 1 for an OUT transaction
; point to lower banks
bcf
STATUS,IRP
buffer
FSR
movlw
movwf
movlw
call
btfss
goto
; point FSR to our buffer
; check end point 1
; If data is ready, it will be copied.
; was there any data for us?
; Nope, check again.
1
GetUSB
STATUS,C
idleloop
PutBuffer
bcf
STATUS,IRP
bufferlen
buffer
FSR
bufferlen,w
1
; point to lower banks
; save buffer length
movwf
movlw
movwf
swapf
iorlw
call
; point FSR to our buffer
; upper nybble of W is buffer length
; lower nybble of W is EndPoint number
PutUSB
btfss
goto
goto
STATUS,C
PutBuffer
idleloop
; was it successful?
; No: try again until successful
; Yes: restart loop
end
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 73
PIC16C745/765
10.9.7 ASSEMBLING THE CODE
The code is designed to be used with the linker. There
is no provision for include-able files. The code comes
packaged as several different files:
• USB_CH9.ASM - handles all the Chapter 9 com-
mand processing.
• USB_INTF.ASM - Provides the interface functions
PutUSB, GetUSB
• USBMACRO.INC - Macros used by
• USB_DEFS.INC - #Defines used throughout the
code.
• USB_INT.ASM - Sample interrupt service routine.
• 16C765.LKR - Linker script (provided with
MPLAB)
10.9.7.1 Assembly Options:
There are two #defines at the top of the code that con-
trol assembly options.
10.9.7.2 #define ERRORCOUNTERS
This define includes code to count the number of
errors that occur, by type of error. This requires extra
code and RAM locations to implement the counters.
10.9.7.3 #define FUNCTIONIDS
This is useful for debug. It encodes the upper 6 bits of
USWSTAT (0x197) to indicate which function is exe-
cuting.
DS41124A-page 74
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, Serial EEPROMs etc.
11.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
The USART can be configured in the following modes:
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial I/
O modules. (USART is also known as a Serial Commu-
nications Interface or SCI). The USART can be config-
ured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
Bits SPEN (RCSTA<7>) and TRISC<7:6> have to be
set in order to configure pins RC6/TX/CK and RC7/RX/
DT as the universal synchronous asynchronous
receiver transmitter.
REGISTER 11-1: TRANSMIT STATUS AND CONTROL REGISTER (TXSTA: 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
R/W-0
TX9D
R
= Readable bit
TRMT
W = Writable bit
U
bit7
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6:
bit 5:
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3:
bit 2:
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit 1:
bit 0:
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. (Can be used for parity.)
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 75
PIC16C745/765
REGISTER 11-2: RECEIVE STATUS AND CONTROL REGISTER (RCSTA: 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
R-0
R-0
R-x
R
= Readable bit
—
FERR
OERR
RX9D
W = Writable bit
U
bit7
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3:
bit 2:
Unimplemented: Read as '0'
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
bit 1:
bit 0:
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data. (Can be used for parity.)
DS41124A-page 76
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
11.1
USART Baud Rate Generator (BRG)
The BRG supports both the asynchronous and syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode, bit BRGH is ignored.
Table 11-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
11.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
near the center of each bit time by a majority detect cir-
cuit to determine if a high or a low level is present at the
RX pin.
Given the desired baud rate and FINT, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FINT/(16(X + 1)) equation can reduce the
baud rate error in some cases.
TABLE 11-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FINT/(64(SPBRG+1))
(Synchronous) Baud Rate = FINT/(4(SPBRG+1))
Baud Rate= FINT/(16(SPBRG+1))
NA
TABLE 11-2: BAUD RATES FOR SYNCHRONOUS MODE
4 MHz
6 MHz
24 MHz
Desired
Baud
Actual
Baud
% of
Error
Actual
Baud
% of
Error
Actual
Baud
% of
Error
SPBRG
SPBRG
SPBRG
300
1200
2400
4800
4807.69
9615.38
0.16
207
9600
0.16
0.16
0.16
2.12
8.51
8.51
8.51
103
51
25
16
7
9615.38
19230.77
38461.54
57692.31
115384.62
250000.00
500000.00
0.16
155
19200
38400
57600
19230.77
38461.54
58823.53
0.16
0.16
0.16
0.16
8.51
8.51
77
38
25
12
5
38461.54
57692.31
0.16
155
0.16
0.16
0.16
0.16
8.51
103
51
25
12
5
115200 125000.00
230400 250000.00
460800 500000.00
921600
115384.62
230769.23
461538.46
1000000.00
3
1
2
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 77
PIC16C745/765
TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
4 MHz
6 MHz
24 MHz
Desired
Baud
Actual
Baud
% of
Error
Actual
Baud
% of
Error
Actual
Baud
% of
Error
SPBRG
SPBRG
SPBRG
300
300.48
1201.92
2403.85
4807.69
10416.67
20833.33
0.16
207
1200
2400
0.16
0.16
0.16
8.51
8.51
51
25
12
5
1201.92
2403.85
0.16
77
0.16
2.80
38
18
8
2403.85
4807.69
0.16
155
4800
4934.21
0.16
0.16
2.80
8.51
8.51
8.51
77
38
18
8
9600
10416.67
23437.50
46875.00
8.51
9615.38
19200
38400
57600
115200
230400
460800
921600
2
22.07
22.07
3
19736.84
41666.67
62500.00
125000.00
1
5
2
TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
4 MHz
6 MHz
24 MHz
Desired
Baud
Actual
Baud
% of
Error
Actual
Baud
% of
Error
Actual
Baud
% of
Error
SPBRG
SPBRG
SPBRG
300
1200
2400
1201.92
2403.85
4807.69
9615.38
19230.77
41666.67
62500.00
12500.00
0.16
207
0.16
0.16
0.16
0.16
8.51
8.51
8.51
103
51
25
12
5
2403.85
4807.69
0.16
155
4800
0.16
0.16
2.80
8.51
8.51
8.51
77
38
18
8
9600
9615.38
9615.38
19230.77
38461.54
57692.31
115384.62
250000.00
500000.00
0.16
155
77
38
25
12
5
19200
38400
57600
115200
230400
460800
921600
19736.84
41666.67
62500.00
12500.00
0.16
0.16
0.16
0.16
8.51
8.51
3
5
1
2
2
TABLE 11-5: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on:
POR,
BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
0000 -010
0000 -00x
0000 0000
0000 -010
0000 -00x
0000 0000
98h
18h
99h
TXSTA
CSRC TX9 TXEN SYNC
—
—
BRGH TRMT TX9D
FERR OERR RX9D
RCSTA SPEN RX9 SREN CREN
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
DS41124A-page 78
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicated the sta-
tus of the TXREG register, another bit TRMT
(TXSTA<1>) shows the status of the TSR register. Sta-
tus bit TRMT is a read only bit, which is set when the
TSR register is empty. No interrupt logic is tied to this
bit, so the user has to poll this bit in order to determine
if the TSR register is empty.
11.2
USART Asynchronous Mode
In this mode, the USART uses standard nonreturn-to-
zero (NRZ) format (one start bit, eight or nine data bits,
and one stop bit). The most common data format is 8
bits. An on-chip, dedicated, 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent, but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 11-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 11-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
11.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 11-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG Register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
•
•
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 79
PIC16C745/765
Steps to follow when setting up an Asynchronous
Transmission:
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1)
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
7. Load data to the TXREG register (starts trans-
mission).
3. If interrupts are desired, then set enable bit
TXIE.
FIGURE 11-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 11-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Start Bit
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
Stop Bit
TXIF bit
(interrupt reg. flag)
WORD 1
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 11-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
RCSTA
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SREN CREN
—
FERR
OERR
RX9D 0000 -00x 0000 -00x
TXREG USART Transmit Register
0000 0000 0000 0000
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 80
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
11.2.2 USART ASYNCHRONOUS RECEIVER
two bytes of data to be received and transferred to the
RCREG FIFO and a third byte to begin shifting to the
RSR register. On the detection of the STOP bit of the
third byte, if the RCREG register is still full, then overrun
error bit OERR (RCSTA<1>) will be set. The word in the
RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Overrun bit
OERR has to be cleared in software. This is done by
resetting the receive logic (CREN is cleared and then
set). If bit OERR is set, transfers from the RSR register
to the RCREG register are inhibited, so it is essential to
clear error bit OERR if it is set. Framing error bit FERR
(RCSTA<2>) is set if a stop bit is detected as clear. Bit
FERR and the 9th receive bit are buffered the same
way as the receive data. Reading the RCREG, will load
bits RX9D and FERR with new values, therefore it is
essential for the user to read the RCSTA register before
reading RCREG register in order not to lose the old
FERR and RX9D information.
The receiver block diagram is shown in Figure 11-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FINT.
Once asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit which is cleared by the
hardware. It is cleared when the RCREG register has
been read and is empty. The RCREG is a double buff-
ered register, i.e. it is a two deep FIFO. It is possible for
FIGURE 11-4: USART RECEIVE BLOCK DIAGRAM
FERR
OERR
CREN
SPBRG
RSR Register
MSb
LSb
Baud Rate Generator
RC7/RX/DT
Stop (8)
7
1
0
Start
• • •
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 11-5: ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX (pin)
bit0
bit1
Stop
bit
Stop
bit
bit7/8 Stop
bit
bit0
bit7/8
bit7/8
Rcv shift
reg
Rcv buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 81
PIC16C745/765
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 11.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
TABLE 11-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 82
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-imped-
ance receive mode to transmit and start driving. To
avoid this, bit TXEN should be cleared.
11.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e., transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
11.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 11-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 11-6). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 11-7). This is advantageous when slow
baud rates are selected, since the BRG is kept in reset
when bits TXEN, CREN and SREN are clear. Setting
enable bit TXEN will start the BRG, creating a shift
clock immediately. Normally, when transmission is first
started, the TSR register is empty, so a transfer to the
TXREG register will result in an immediate transfer to
TSR resulting in an empty TXREG. Back-to-back trans-
fers are possible.
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-imped-
ance. If either bit CREN or bit SREN is set during a
transmission, the transmission is aborted and the DT
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 83
PIC16C745/765
TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
FIGURE 11-6: SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
WORD 2
bit 7
WORD 1
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
T
TRMT bit
’1’
Note: Sync master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words
’1’
TXEN bit
FIGURE 11-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
DS41124A-page 84
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
11.3.2 USART SYNCHRONOUS MASTER
RECEPTION
OERR if it is set. The ninth receive bit is buffered the
same way as the receive data. Reading the RCREG
register will load bit RX9D with a new value, therefore it
is essential for the user to read the RCSTA register
before reading RCREG in order not to lose the old
RX9D information.
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
CREN takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register, i.e., it is a two deep FIFO. It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin
shifting into the RSR register. On the clocking of the last
bit of the third byte, if the RCREG register is still full,
then overrun error bit OERR (RCSTA<1>) is set. The
word in the RSR will be lost. The RCREG register can
be read twice to retrieve the two bytes in the FIFO. Bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. (Section 11.1)
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
TABLE 11-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 85
PIC16C745/765
FIGURE 11-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = ’1’ and bit BRG = ’0’.
DS41124A-page 86
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
11.4.2 USART SYNCHRONOUS SLAVE
11.4
USART Synchronous Slave Mode
RECEPTION
Synchronous slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous master and slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a don’t care in slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
11.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical, except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
Steps to follow when setting up a synchronous slave
transmission:
8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the
TXREG register.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 87
PIC16C745/765
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on all
other Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous slave transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on all
other Resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF USBIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE USBIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous slave reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
DS41124A-page 88
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
The A/D converter has a unique feature of being able to
operate while the device is in SLEEP mode. To operate
in sleep, the A/D conversion clock must be derived from
the A/D’s dedicated internal RC oscillator.
12.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The 8-bit Analog-To-Digital (A/D) converter module has
five inputs for the PIC16C745 and eight for the
PIC16C765.
The A/D module has three registers. These registers
are:
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital value. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD) or the
voltage level on the RA3/AN3/VREF pin.
The ADCON0 register, shown in Register 12-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 12-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference)
or as digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023) and in Application Note,
AN546.
REGISTER 12-1: A/D CONTROL REGISTER (ADCON0: 1Fh)
R/W-0 R/W-0 R/W-0
ADCS1 ADCS0 CHS2
bit7
R/W-0
CHS1
R/W-0
R/W-0
U-0
—
R/W-0
ADON
CHS0 GO/DONE
R =Readable bit
W = Writable bit
U =Unimplemented bit,
read as ‘0’
bit0
- n = Value at POR reset
bit 7-6: ADCS<1:0>: A/D Conversion Clock Select bits
00= FINT/2
01= FINT/8
10= FINT/32
11= FRC (clock derived from dedicated internal oscillator)
bit 5-3: CHS<2:0>: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)(1)
110= channel 6, (RE1/AN6)(1)
111= channel 7, (RE2/AN7)(1)
bit 2:
GO/DONE: A/D Conversion Status bit
If ADON = 1
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-
sion is complete)
bit 1:
bit 0:
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 89
PIC16C745/765
REGISTER 12-2: A/D CONTROL REGISTER 1 (ADCON1: 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1
PCFG0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
bit7
bit0
- n = Value at POR
reset
bit 7-3: Unimplemented: Read as '0'
bit 2-0: PCFG<2:0>: A/D Port Configuration Control bits
PCFG<2:0> AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
VREF
VDD
000
001
010
011
100
101
11x
A
A
D
D
D
A
D
A
A
A
A
A
A
A
A
A
A
A
D
A
A
D
D
D
A
D
A
D
D
D
A
D
A
A
A
D
A
D
VREF
A
A
A
A
D
A
D
A
A
A
A
A
D
RA3
VDD
AN3
VDD
AN3
VDD
VREF
A
VREF
D
A = Analog input
D = Digital I/O
DS41124A-page 90
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
The following steps should be followed for doing an A/D
conversion:
4. Start conversion:
• Set GO/DONE bit (ADCON0)
1. Configure the A/D module:
5. Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
OR
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
• Waiting for the A/D interrupt
6. Read A/D result register (ADRES), clear bit
ADIF if required.
7. For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Set ADIE bit
• Set GIE bit
3. Wait the required acquisition time.
FIGURE 12-1: A/D BLOCK DIAGRAM
CHS<2:0>
111
RE2/AN7(1)
110
RE1/AN6(1)
101
RE0/AN5(1)
100
RA5/AN4
VIN
011
(Input voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
100or
11x
VREF
(Reference
voltage)
001or
011or
101
PCFG<2:0>
Note 1: Not available on PIC16C745.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 91
PIC16C745/765
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition must pass before
the conversion can be started.
12.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-2. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), Figure 12-2. The source impedance affects the
offset voltage at the analog input (due to pin leakage
current).
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (512 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023). In general, however, given a max
of 10kΩ and a worst case temperature of 100°C, TACQ
will be no more than 16µsec.
FIGURE 12-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
Rs
CHOLD
CPIN
5 pF
= DAC capacitance
= 51.2 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
6V
5V
Legend CPIN
VT
= input capacitance
= threshold voltage
VDD 4V
3V
= leakage current at the pin due to
various junctions
I leakage
2V
= interconnect resistance
= sampling switch
RIC
5 6 7 8 9 1011
Sampling Switch
SS
CHOLD
= sample/hold capacitance (from DAC)
(kΩ)
EQUATION 12-1: ACQUISITION TIME
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
TAMP + TC + TCOFF
TAMP = 5µS
TC = - (51.2pF)(1kΩ + RSS + RS) In(1/511)
TCOFF = (Temp -25°C)(0.05µS/°C)
DS41124A-page 92
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
12.2
Selecting the A/D Conversion Clock
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.5TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
• 2TOSC
• 8TOSC
• 32TOSC
• Dedicated Internal RC oscillator
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD)
Operation ADCS1:ADCS0
Device Frequency
5 MHz 1.25 MHz
400 ns(2)
1.6 µs
20 MHz
100 ns(2)
333.33 kHz
6 µs
24 µs(3)
96 µs(3)
2 - 6 µs(1)
2TOSC
8TOSC
32TOSC
RC
00
01
10
11
400 ns(2)
1.6 µs
6.4 µs
1.6 µs
2 - 6 µs(1,4)
6.4 µs
25.6 µs(3)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
Note 1: The RC source has a typical TAD time of 4 µs.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion, or the A/D
accuracy may be out of specification.
12.3
Configuring Analog Port Pins
12.4
A/D Conversions
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their corresponding
TRIS bits set (input). If the TRIS bit is cleared (output),
the digital output level (VOH or VOL) will be converted.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of specification.
3: The TRISE register is not provided on the
PIC16C745.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 93
PIC16C745/765
12.5
A/D Operation During Sleep
12.6
Effects of a RESET
The A/D module can operate during SLEEP mode.
This requires that the A/D clock source be set to RC
(ADCS<1:0> = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the con-
version is completed, the GO/DONE bit will be
cleared, and the result loaded into the ADRES regis-
ter. If the A/D interrupt is enabled, the device will
wake-up from SLEEP. If the A/D interrupt is not
enabled, the A/D module will then be turned off,
although the ADON bit will remain set.
A device reset forces all registers to their reset state.
The A/D module is disabled and any conversion in
progress is aborted. All pins with analog functions are
configured as available inputs.
The ADRES register will contain unknown data after a
power-on reset.
12.7
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M<3:0> bits (CCP2CON<3:0>) be programmed as
1011 and that the A/D module is enabled (ADON bit is
set). When the trigger occurs, the GO/DONE bit will be
set, starting the A/D conversion, and the Timer1 counter
will be reset to zero. Timer1 is reset to automatically
repeat the A/D acquisition period with minimal software
overhead (moving the ADRES to the desired location).
The appropriate analog input channel must be selected
and the minimum acquisition done before the “special
event trigger” sets the GO/DONE bit (starts a conversion).
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS<1:0> = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 12-2: SUMMARY OF A/D REGISTERS
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
Resets
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Bh,8Bh,
10Bh,18Bh
(1)
PIR1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
USBIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
USBIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0Ch
8Ch
1Eh
1Fh
(1)
PIE1
ADRES
A/D Result Register
ADCON0 ADCS1 ADCS0 CHS2
CHS1
CHS0
GO/
—
ADON 0000 00-0 0000 00-0
DONE
ADCON1
—
—
—
—
—
—
—
PCFG2
PCFG1 PCFG0 ---- -000 ---- -000
9Fh
05h
85h
09h
89h
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTA
TRISA
PORTE
TRISE
RA5
RA4
RA3
RA2
RA1
RA0
—
—
—
—
PORTA Data Direction Register
(1)
(1)
(1)
—
—
—
—
RE2
RE1
RE0
(1)
(1)
(1)
(1)
(1)
IBF
OBF
IBOV
PSP-MODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These bits are reserved on the PIC6C745; always maintain these bits clear.
DS41124A-page 94
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
keep the chip in reset until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up only
and is designed to keep the part in reset, while the
power supply stabilizes. With these two timers on-chip,
most applications need no external reset circuitry.
13.0 SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits to deal with the needs of real-
time applications. The PIC16C745/765 family has a
host of such features intended to maximize system reli-
ability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external reset, WDT wake-up or through an
interrupt. Several oscillator options are also made
available to allow the part to fit the application. The EC
oscillator allows the user to directly drive the microcon-
troller, while the HS oscillator allows the use of a high
speed crystal/resonator. A set of configuration bits are
used to select various options.
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
13.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID locations
The user will note that address 2007h is beyond the user
program memory space. In fact, it belongs to the special
test/configuration memory space (2000h - 3FFFh),
which can be accessed only during programming.
• In-Circuit Serial Programming™ (ICSP)
The PIC16C745/765 has a Watchdog Timer, which can
be shut off only through configuration bits. It runs off its
own dedicated RC oscillator for added reliability. There
are two timers that offer necessary delays on power-up.
One is the Oscillator Start-up Timer (OST), intended to
REGISTER 13-1: CONFIGURATION WORD
CP1
CP0
CP1
CP0
CP1
CP0
—
—
CP1
CP0 PWRTE WDTE FOSC1 FOSC0
bit0
Register: CONFIG
Address 2007h
bit13
bit 13-12: CP<1:0>: Code Protection bits(1)
11-10: 00= All memory is code protected
9-8: 01= Upper 3/4th of program memory code protected
5-4: 10= Upper half of program memory code protected
11= Code protection off
bit 7-6: Unimplemented: Read as ’1’
bit 3:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled • No delay after Power-up reset or Brown-out reset
0 = PWRT enabled • A delay of 4x WDT (72 ms) is present after Power-up and Brown-out
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0: FOSC<1:0>: Oscillator Selection
00- HS- HS osc
01- EC- External clock. CLKOUT on OSC2 pin
10- H4- HS osc with 4x PLL enabled
11- E4- External clock with 4x PLL enabled. CLKOUT on OSC2 pin
Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 95
PIC16C745/765
13.2
Oscillator Configurations
TABLE 13-1: CERAMIC RESONATORS
Ranges Tested:
13.2.1
OSCILLATOR TYPES
Mode
Freq
OSC1
OSC2
The PIC16C745/765 can be operated in four different
oscillator modes. The user can program a configuration
bit (FOSC0) to select one of these four modes:
HS
6.0 MHz
TBD
TBD
These values are for design guidance only. See notes at
bottom of page.
•EC
•E4
•HS
•H4
External Clock
TABLE 13-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
External Clock with PLL
High Speed Crystal/Resonator
High Speed Crystal/Resonator with PLL
Osc Type
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
13.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
TBD
TBD
HS
6.0 MHz
These values are for design guidance only. See notes at
bottom of page.
In HS mode, a crystal or ceramic resonator is con-
nected to the OSC1/CLKIN and OSC2/CLKOUT pins to
establish oscillation (Figure 13-1). The PIC16C745/
765 oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may give a frequency
out of the crystal manufacturers specifications. When in
HS mode, the device can have an external clock source
to drive the OSC1/CLKIN pin (Figure 13-2). In this
mode, the oscillator start-up timer is active for a period
of 1024*TOSC. See the PICmicro™ Mid-Range MCU
Reference Manual (DS33023) for details on building an
external oscillator.
Note 1: Higher capacitance increases the stability
of the oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
3: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
FIGURE 13-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
5: Users should consult the USB Specification
1.0 to ensure their resonator/crystal oscilla-
tor meets the required jitter limits for USB
operation.
(HS OSC CONFIGURATION)
OSC1
To internal
logic
C1
13.2.3 H4 MODE
XTAL
OSC2
SLEEP
Rf
In H4 mode, a PLL module is switched on in-line with
the clock provided across OSC1 and OCS2. The output
of the PLL drives FINT.
PIC16C745/765
Rs
C2
Note1
Note 1:
A series resistor may be required for AT strip cut
crystals.
DS41124A-page 96
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
13.2.4 EXTERNAL CLOCK IN
13.2.5 E4 MODE
In EC mode, users may directly drive the PIC16C745/
765 provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4.
Figure 13-2 below shows how an external clock circuit
should be configured.
In E4 mode, a PLL module is switched on in-line with
the clock provided to OSC1. The output of the PLL
drives FINT.
Note: CLKOUT is the same frequency as OSC1 if
in E4 mode, otherwise CLKOUT = OSC1/4.
FIGURE 13-2: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
Clock from
ext. system
OSC1
PIC16C745/765
CLKOUT
OSC2/CLKOUT
FIGURE 13-3: OSCILLATOR/PLL CLOCK CONTROL
6 MHz
EC
E4
OSC2
HS
H4
EC
E4
HS
H4
Q Clock
24 MHz
To Circuits
Generator
FINT
OSC1
4x PLL
A simplified block diagram of the on-chip reset circuit is
shown in Figure 13-4.
The PICmicro® devices have a MCLR noise filter in the
MCLR reset path. The filter will detect and ignore small
pulses.
13.3
Reset
The PIC16CXX differentiates between various kinds of
reset:
• Power-on Reset (POR)
• MCLR reset during normal operation
• MCLR reset during SLEEP
• WDT Reset (normal operation)
• Brown-out Reset (BOR)
It should be noted that a WDT reset does not drive
MCLR pin low.
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on POR, on the MCLR and WDT Reset, on
MCLR reset during SLEEP, and on BOR. The TO and
PD bits are set or cleared differently in different reset
situations as indicated in Table 13-4. These bits are
used in software to determine the nature of the reset.
See Table 13-7 for a full description of reset states of all
registers.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 97
PIC16C745/765
FIGURE 13-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR
SLEEP
Time-out
Reset
WDT
Module
Power-on Reset
VDD rise
detect
VDD
Brown-out
Reset
S
R
OST/PWRT
OST
10-bit Ripple counter
Chip Reset
Q
OSC1
PWRT
10-bit Ripple counter
Dedicated
On-chip
RC OSC
Enable PWRT
Enable OST
DS41124A-page 98
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
13.4.4 BROWN-OUT RESET (BOR)
13.4
Resets
If VDD falls below VBOR (parameter D005) for longer
than TBOR (parameter #35), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a reset may not occur.
13.4.1 POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to VDD. This will elimi-
nate external RC components usually needed to create
a POR. A maximum rise time for VDD is specified. See
Electrical Specifications for details.
Once the brown-out occurs, the device will remain in
brown-out reset until VDD rises above VBOR. The
power-up timer then keeps the device in reset for
TPWRT (parameter #33). If VDD should fall below VBOR
during TPWRT, the brown-out reset process will restart
when VDD rises above VBOR with the power-up timer
reset. Since the device is intended to operate at 5V
nominal only, the brown-out detect is always enabled
and the device will reset when Vdd falls below the
brown-out threshold. This device is unique in that the
4•WDT timer will not activate after a brown-out if
PWRTE = 1 (inactive).
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature) must be met to ensure opera-
tion. If these conditions are not met, the device must be
held in reset until the operating conditions are met.
Brown-out reset may be used to meet the startup con-
ditions.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.5 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (HS). When the OST ends,
the device comes out of RESET.
13.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up from the POR. The PWRT oper-
ates on an internal RC oscillator. The device is kept in
reset as long as the PWRT is active. The PWRT’s time
delay allows VDD to rise to an acceptable level. A con-
figuration bit is provided to enable/disable the PWRT.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16CXX device operating in
parallel.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Table 13-5 shows the reset conditions for the STATUS,
PCON and PC registers, while Table 13-7 shows the
reset conditions for all the registers.
13.4.3 OSCILLATOR START-UP TIMER (OST)
The Oscillator Start-up Timer provides a delay of 1024
oscillator cycles (from OSC1 input) after the PWRT
delay. This ensures that the crystal oscillator or resona-
tor has started and stabilized.
13.4.6 POWER CONTROL/STATUS REGISTER
(PCON)
The Brown-out Reset Status bit, BOR, is unknown on a
POR. It must be set by the user and checked on subse-
quent resets to see if bit BOR was cleared, indicating a
BOR occurred. The BOR bit is not predictable if the
brown-out reset circuitry is disabled.
The OST time-out is invoked only for HS mode and only
on power-on reset or wake-up from SLEEP.
The Power-on Reset Status bit, POR, is cleared on a
POR and unaffected otherwise. The user must set this
bit following a POR and check it on subsequent resets
to see if it has been cleared.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 99
PIC16C745/765
13.5
Time-out in Various Situations
TABLE 13-3: RESET TIME-OUTS
POR
BORt
Oscillator
Wake-up
Configuration
from SLEEP
PWRTE = 0
PWRTE = 1
1024•TOSC
PWRTE = 0
PWRTE = 1
1024•TOSC
HS
H4
TPWRT + 1024•TOSC
TPWRT + 1024•TOSC
1024•TOSC
TPWRT + TPLLRT +
TPLLRT + 1024•TOSC
TPWRT + TPLLRT +
TPLLRT + 1024•TOSC
TPLLRT +
1024•TOSC
1024•TOSC
1024•TOSC
EC
E4
TPWRT
0
TPWRT
0
0
TPWRT + TPLLRT
TPLLRT
TPWRT + TPLLRT
TPLLRT
TPLLRT
TABLE 13-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
0
BOR
TO
1
PD
1
x
x
x
0
1
1
1
1
Power-on Reset
0
0
x
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
0
x
0
1
1
1
1
0
1
WDT Reset
1
0
0
WDT Wake-up
1
u
u
MCLR Reset during normal operation
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 13-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
Condition
STATUS
Register
PCON
Register
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
Interrupt wake-up from SLEEP
PC + 1(1)
Legend: u= unchanged, x= unknown, -= unimplemented bit read as ’0’.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
TABLE 13-6: REGISTERS ASSOCIATED WITH RESETS
Value on:
POR, BOR
Value on all
other resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h, 83h,
103h, 183h
Status
PCON
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
POR
BOR
8Eh
—
—
—
—
—
—
---- --qq ---- --uu
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'.
DS41124A-page 100
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 13-7: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
W
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
PCL
xxxx xxxx
0000h
uuuu uuuu
0000h
uuuu uuuu
PC + 1(2)
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uu-- -uuu
uuuu uuuu
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uu-- -uuu
uuuu uuuu
STATUS
0001 1xxx
FSR
xxxx xxxx
--0x 0000
xxxx xxxx
xx-- -xxx
xxxx xxxx
PORTA
PORTB
PORTC
PORTD(4)
PORTE(4)
PCLATH
INTCON
---- -xxx
---- -uuu
---- -uuu
---u uuuu
---0 0000
0000 000x
---0 0000
0000 000u
uuuu uuuu(1)
uuuu uuuu(1)
0000 0000
---- ---0
0000 0000
---- ---0
PIR1
PIR2
---- ---u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uu-- -uuu
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
11-- -111
1111 1111
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
11-- -111
1111 1111
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD(4)
Legend:
u
= unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 13-5 for reset value for specific condition.
4: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 101
PIC16C745/765
TABLE 13-7: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset
Brown-out Reset
MCLR Resets
WDT Reset
Wake-up via WDT or
Interrupt
Register
TRISE(4)
0000 -111
0000 -111
uuuu -uuu
PIE1
0000 0000
---- ---0
0000 0000
---- ---0
---- --uu
uuuu uuuu
---- ---u
---- --uu
PIE2
---- --0q(3)
1111 1111
0000 -010
0000 0000
---- -000
PCON
PR2
1111 1111
0000 -010
0000 0000
---- -000
1111 1111
uuuu -uuu
uuuu uuuu
---- -uuu
TXSTA
SPBRG
ADCON1
UIR
--00 0000
--00 0000
0000 0000
0000 0000
---x xx--
--x0 000-
-000 0000
0000 0000
---- 0000
---- 0000
---- 0000
--00 0000
--00 0000
0000 0000
0000 0000
---u uu--
--xq qqq-
-000 0000
0000 0000
---- 0000
---- 0000
---- 0000
--00 0000
--00 0000
0000 0000
0000 0000
---u uu--
--xq qqq-
-000 0000
0000 0000
---- 0000
---- 0000
---- 0000
UIE
UEIR
UEIE
USTAT
UCTRL
UADDR
USWSTAT
UEP0
UEP1
UEP2
Legend:
u
= unchanged,
x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 13-5 for reset value for specific condition.
4: PIC16C765 only.
DS41124A-page 102
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
13.6
Interrupts
Note: If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be re-
enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
1. An instruction clears the GIE bit while
an interrupt is acknowledged.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
2. The program branches to the inter-
rupt vector and executes the interrupt
service routine.
3. The interrupt service routine com-
pletes the execution of the RETFIE
instruction. This causes the GIE bit to
be set (enables interrupts), and the
program returns to the instruction
after the one which was meant to dis-
able interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
LOOP BCF
INTCON, GIE ; Disable global
interrupt bit
BTFSC INTCON, GIE ; Global interrupt
disabled?
; NO, try again
;
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
;
GOTO LOOP
:
;
;
;
Yes, continue
with program
flow
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 103
PIC16C745/765
FIGURE 13-5: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
Tost(2)
INTF flag
Interrupt Latency(2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
fetched
Inst(0004h)
Inst(PC + 2)
Inst(0005h)
Instruction
executed
Dummy cycle
Dummy cycle
Inst(PC + 1)
Inst(0004h)
Note 1: HS oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay is not present in EC osc mode.
3: GIE = ’1’ assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
FIGURE 13-6: INTERRUPT LOGIC
PSPIF(1)
PSPIE(1)
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
USBIF
USBIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows the interrupts for each device.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF USBIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C745
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C765
Yes
Yes
Yes
Yes
Note 1: PIC16C765 only.
DS41124A-page 104
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
13.6.1 INT INTERRUPT
13.7
Context Saving During Interrupts
The external interrupt on RB0/INT pin is edge trig-
gered: either rising, if bit INTEDG (OPTION_REG<6>)
is set or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the interrupt service rou-
tine before re-enabling this interrupt. The INT interrupt
can wake-up the processor from SLEEP, if bit INTE was
set prior to going into SLEEP. The status of global inter-
rupt enable bit GIE decides whether or not the proces-
sor branches to the interrupt vector following wake-up.
See Section 13.9 for details on SLEEP mode.
During an interrupt, only the PC is saved on the stack.
At the very least, W and STATUS should be saved to
preserve the context for the interrupted program. All
registers that may be corrupted by the ISR, such as
PCLATH or FSR, should be saved.
Example 13-1 stores and restores the STATUS, W and
PCLATH registers. The register, W_TEMP, is defined in
Common RAM, the last 16 bytes of each bank that may
be accessed from any bank. The STATUS_TEMP and
PCLATH_TEMP are defined in bank 0.
The example:
a) Stores the W register.
b) Stores the STATUS register in bank 0.
c) Stores the PCLATH register in bank 0.
d) Executes the ISR code.
13.6.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 6.0)
e) Restores the PCLATH register.
f) Restores the STATUS register
g) Restores W.
13.6.3 PORTB INTERRUPT ON CHANGE
Note
that
W_TEMP,
STATUS_TEMP
and
PCLATH_TEMP are defined in the common RAM area
(70h - 7Fh) to avoid register bank switching during con-
text save and restore.
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 5.2)
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
EXAMPLE 13-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
#define
#define
#define
org
W_TEMP
0x70
0x71
0x72
STATUS_TEMP
PCLATH_TEMP
0x04
; start at Interrupt Vector
; Save W register
MOVWF
W_TEMP
MOVF
MOVWF
MOVF
MOVWF
:
STATUS,W
STATUS_TEMP
PCLATH,W
PCLATH_TEMP
; save STATUS
; save PCLATH
(Interrupt Service Routine)
:
MOVF
MOVWF
MOVF
MOVWF
SWAPF
SWAPF
RETFIE
PCLATH_TEMP,W
PCLATH
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
;
; swapf loads W without affecting STATUS flags
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 105
PIC16C745/765
ratio of up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Time-out periods up to 128 TWDT can be realized.
13.8
Watchdog Timer (WDT)
The watchdog timer is a free running on-chip dedicated
oscillator, which does not require any external compo-
nents. The WDT will run, even if the clock on the OSC1/
CLKIN and OSC2/CLKOUT pins of the device has
been stopped, for example, by execution of a SLEEP
instruction.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT. In addition,
the SLEEPinstruction prevents the WDT from generat-
ing a reset, but will allow the WDT to wake the device
from sleep mode.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and resume normal operation (Watchdog
Timer Wake-up).
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.8.2 WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., and
max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 13.1).
13.8.1 WDT PERIOD
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT has a nominal time-out period of 18 ms
(parameter #31, TWDT). The time-out periods vary with
temperature, VDD and process variations. If longer
time-out periods are desired, a prescaler with a division
FIGURE 13-7: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS<2:0>
PSA
WDT
Enable Bit
To TMR0 MUX
(Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS<2:0> are bits in the OPTION register.
TABLE 13-8: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on
All Other
Resets
Value on
POR, BOR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
2007h
Config. bits
—
BODEN
CP1
CP0 PWRTE
PSA
WDTE PLL FOSC0
PS2 PS1 PS0
81h,181h OPTION_REG
RBPU
INTEDG
T0CS T0SE
1111 1111 1111 1111
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 13-1 for operation of these bits.
DS41124A-page 106
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip Q clocks are present.
13.9
Power-Down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
instruction.
If enabled, the WDT will be cleared but keeps running,
the PD bit (STATUS<3>) is cleared, the TO (STA-
TUS<4>) bit is set, and the oscillator driver is turned off.
The I/O ports maintain the status they had, before the
SLEEP instruction was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D, and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should be considered.
13.9.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
The MCLR pin must be at a logic high level (VIHMC).
13.9.1 WAKE-UP FROM SLEEP
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
The device can wake up from SLEEP through one of
the following events:
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake up from sleep. The SLEEPinstruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
1. External reset input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was enabled).
3. Interrupt from INT pin, RB port change or some
Peripheral Interrupts.
External MCLR reset will cause a device reset. All other
events are considered a continuation of program exe-
cution and cause a “wake-up”. The TO and PD bits in
the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up, is cleared when SLEEPis invoked. The TO
bit is cleared if a WDT time-out occurred (and caused
wake-up).
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
The following peripheral interrupts can wake the device
from SLEEP:
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
1. TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
2. USB Interrupt
3. CCP capture mode interrupt.
4. Parallel slave port read or write. (PIC16C765
only)
5. A/D conversion (when A/D clock source is dedi-
cated internal oscillator).
6. USART TX or RX (synchronous slave mode).
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 107
PIC16C745/765
FIGURE 13-8: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
Tost(2)
INTF flag
Interrupt Latency(2)
(INTCON<1>)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: HS oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). This delay is not present in EC osc mode.
3: GIE = ’1’ assumed. After wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
13.10 Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
Note: Microchip does not recommend code pro-
tecting windowed devices. Devices that are
code protected may be erased, but not pro-
grammed again.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device. Depend-
ing on the command, 14 bits of program data are then
supplied to or from the device, depending if the com-
mand was a load or a read. For complete details of
serial programming, please refer to the PIC16C6X/7X
Programming Specifications (Literature #DS30228).
13.11 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are read-
able and writable during program/verify. It is recom-
mended that only the four least significant bits of the ID
location are used.
FIGURE 13-9: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
13.12 In-Circuit Serial Programming
To Normal
Connections
External
Connector
Signals
PIC16CXX microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming volt-
age. This allows customers to manufacture boards with
unprogrammed devices, and then program the micro-
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
PIC16CXX
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
VDD
To Normal
Connections
DS41124A-page 108
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
The instruction set is highly orthogonal and is grouped
into three basic categories:
14.0 INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE, which specifies the instruction type
and one or more operands, which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 14-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
Table 14-2 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Figure 14-1 shows the general formats that the instruc-
tions can have.
Note: To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTIONand TRISinstructions.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
TABLE 14-1: OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
0xhh
Field
Description
where h signifies a hexadecimal digit.
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
FIGURE 14-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Byte-oriented file register operations
13
8
7
6
0
0
Don’t care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
OPCODE
d
f (FILE #)
x
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Destination select; d = 0: store result in W,
d = 1: store result in file register f. Default is d = 1
d
label Label name
TOS Top of Stack
PC Program Counter
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
OPCODE
f (FILE #)
PCLATH
Program Counter High Latch
b = 3-bit bit address
f = 7-bit file register address
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
Literal and control operations
General
PD Power-down bit
13
8
7
0
0
Destination either the W register or the specified
register file location
dest
OPCODE
k (literal)
[ ] Options
k = 8-bit immediate value
( ) Contents
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
→
Assigned to
< > Register bit field
In the set of
k (literal)
italics User defined term (font is courier)
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 109
PIC16C745/765
TABLE 14-2: PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
DS41124A-page 110
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
14.1
Instruction Descriptions
Add Literal and W
ADDLW
ANDWF
Syntax:
AND W with f
[label] ANDWF f,d
0 ≤ f ≤ 127
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Operands:
d
[0,1]
(W) + k → (W)
Operation:
(W) .AND. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
The contents of the W register are
added to the eight bit literal ’k’ and the
result is placed in the W register.
Description:
AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
ADDWF
Syntax:
Add W and f
BCF
Bit Clear f
[label] ADDWF f,d
0 ≤ f ≤ 127
Syntax:
Operands:
[label] BCF f,b
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
d
[0,1]
Operation:
(W) + (f) → (destination)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Add the contents of the W register
Description:
Description:
Bit 'b' in register 'f' is cleared.
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[label] ANDLW
k
Syntax:
Operands:
[label] BSF f,b
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 255
0 ≤ f ≤ 127
0 ≤ b ≤ 7
(W) .AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected: None
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W register.
Description:
Bit ’b’ in register ’f’ is set.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 111
PIC16C745/765
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
cleared and the Z bit is set.
instruction is executed.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
CLRW
Clear W
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] CLRW
None
Syntax:
[label] BTFSC f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected:
Description:
Z
Status Affected: None
W register is cleared. Zero bit (Z)
is set.
Description:
If bit ’b’ in register ’f’ is ’1’, the next
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
CALL
Call Subroutine
Operands:
Operation:
Syntax:
[ label ] CALL k
00h → WDT
0 → WDT prescaler,
1 → TO
Operands:
Operation:
0 ≤ k ≤ 2047
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
1 → PD
Status Affected: TO, PD
Status Affected: None
Description: CLRWDTinstruction resets the
Description:
Call Subroutine. First, return
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
DS41124A-page 112
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
Operands:
Syntax:
Operands:
Operation:
d
[0,1]
k → PC<10:0>
Operation:
(f) → (destination)
PCLATH<4:3> → PC<12:11>
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
DECF
Decrement f
[label] DECF f,d
0 ≤ f ≤ 127
INCF
Increment f
Syntax:
Operands:
Syntax:
Operands:
[ label ] INCF f,d
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operands:
Operation:
(f) - 1 → (destination);
skip if result = 0
d
[0,1]
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Description: The contents of register ’f’ are
Status Affected: None
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
Description:
The contents of register ’f’ are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0, a
NOPis executed instead making it
a 2TCY instruction.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 113
PIC16C745/765
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. k → (W)
Z
k → (W)
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The eight bit literal 'k' is loaded into W
register. The don’t cares will assem-
ble as 0’s.
Description:
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 127
MOVWF
Syntax:
Move W to f
Syntax:
[ label ] MOVWF
0 ≤ f ≤ 127
f
Operands:
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(W) .OR. (f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description:
Move data from W register to reg-
ister ’f’.
Inclusive OR the W register with
register ’f’. If ’d’ is 0 the result is
placed in the W register. If ’d’ is 1
the result is placed back in regis-
ter ’f’.
NOP
No Operation
[ label ] NOP
None
Syntax:
MOVF
Move f
Operands:
Operation:
Syntax:
Operands:
[ label ] MOVF f,d
0 ≤ f ≤ 127
No operation
d
[0,1]
Status Affected: None
Description: No operation.
Operation:
(f) → (destination)
Status Affected:
Description:
Z
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS41124A-page 114
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
[ label ] RLF f,d
0 ≤ f ≤ 127
Syntax:
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C
Register f
RETLW
Return with Literal in W
Syntax:
[ label ] RETLW k
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Operands:
Operation:
0 ≤ k ≤ 255
Syntax:
Operands:
k → (W);
TOS → PC
d
[0,1]
Status Affected: None
Operation:
See description below
C
Description:
The W register is loaded with the
Status Affected:
Description:
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
C
Register f
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
SLEEP
Operands:
Operation:
Syntax:
[ label
]
TOS → PC
SLEEP
Status Affected: None
Operands:
Operation:
None
Description: Return from subroutine. The stack
00h → WDT,
0 → WDT prescaler,
1 → TO,
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
0 → PD
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 13.9 for more
details.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 115
PIC16C745/765
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[label]
SUBLW k
XORLW k
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The W register is subtracted (2’s
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
XORWF
Syntax:
Exclusive OR W with f
[label] XORWF f,d
0 ≤ f ≤ 127
SUBWF
Subtract W from f
Syntax:
[ label ]
SUBWF f,d
Operands:
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .XOR. (f) → (destination)
Operation:
(f) - (W) → (destination)
Status Affected:
Description:
Z
Status Affected: C, DC, Z
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 127
Operands:
d
[0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
DS41124A-page 116
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
MPLAB allows you to:
15.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB™ IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
15.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
15.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
15.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 117
PIC16C745/765
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
15.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
15.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
15.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXX products through the use of interchangeable
personality modules or daughter boards. The emulator is
capable of emulating without target application circuitry
being present.
15.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
15.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXX family. MPLAB-ICD utilizes the In-
Circuit Debugging capability built into the PIC16F87X.
This feature, along with Microchip’s In-Circuit Serial
Programming protocol, offers cost-effective in-circuit
flash programming and debugging from the graphical
user interface of the MPLAB Integrated Development
Environment. This enables a designer to develop and
debug source code by watching variables, single-step-
ping and setting break points. Running at full speed
enables testing hardware in real-time. The MPLAB-ICD
is also a programmer for the flash PIC16F87X family.
15.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS41124A-page 118
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
15.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
15.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
15.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
15.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
15.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
15.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 119
PIC16C745/765
15.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
15.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
15.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS41124A-page 120
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 15-1: DEVELOPMENT TOOLS FROM MICROCHIP
5 1 2 0 P M C
X X R X F C M
X X
H C S X
X X C 9 3
/ X X C 2 5
/ X X C 2 4
X X C 8 2 C 1 P I
X X 7 C 7 C 1 P I
X 4 C 7 C 1 P I
X X 9 C 6 C 1 P I
X 8 X 1 6 C I F P
X 8 C 6 C 1 P I
X X 7 C 6 C 1 P I
X 7 C 6 C 1 P I
X 6 2 6 1 F C I P
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0 0 4 0 1 C I P
X X C 2 X C 1 P I
s l o o e T a r f t o w S s r o t a u l E m e r g g b e u D s m e a r m o g P r r
t i s K v a E l d a n d s a r o B o m e D
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 121
PIC16C745/765
NOTES:
DS41124A-page 122
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
16.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR and RA4)........................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS ................................................................................................... -0.3V to +13.25V
Voltage on RA4 with respect to Vss......................................................................................................... -0.3V to +10.5V
Total power dissipation (Note 1) ...............................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 2) (combined) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 2) (combined)..............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 2) (combined)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 2) (combined).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: PORTD and PORTE not available on the PIC16C745.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation list-
ings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 123
PIC16C745/765
FIGURE 16-1: VALID OPERATING REGIONS. FREQUENCY ON FINT.
-40°C ≤ TA ≤ +85°C
5.5 V
5.25 V
4.35 V
4.0 V
24 MHz
Frequency
DS41124A-page 124
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
16.1
DC Characteristics:
PIC16C745/765 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
-40°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
Param
Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
VDD
VDR
Supply Voltage
4.35
5.25
V
V
See Figure 16-1
–
D002*
RAM Data Retention
Voltage (Note 1)
1.5
–
–
D003
VPOR
SVDD
VDD Start Voltage to ensure
internal
Power-on Reset signal
VSS
V
See section on Power-on Reset for details
–
–
D004*
D004A*
VDD Rise Rate to ensure inter-
nal Power-on Reset signal
0.05
TBD
V/mS PWRT enabled (PWRTE bit clear)
V/mS PWRT disabled (PWRTE bit set)
See section on Power-on Reset for details
–
–
–
–
D005
VBOR
IDD
Brown-out Reset
voltage trip point
3.65
4.35
V
Brown-out Reset is always active
–
D010
D013
Supply Current
(Note 2, 4)
TBD
TBD
TBD
TBD
TBD
TBD
mA FINT = 24 MHz, VDD = 4.35V
FINT = 24 MHz, VDD = 5.25V
D020
D021
D021B
IPD
Power-down Current
(Note 3, 4)
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
VDD = 4.35V
VDD = 5.25V
Module Differential
Current (Note 5, 6)
Watchdog Timer
Brown-out Reset
Capture Compare PWM
Analog
Not suspend mode
Suspend mode
Phase Lock Loop
D022*
D022A*
∆IWDT
∆IBOR
∆ICCP
∆IA/D
∆IUSB
∆IUSB
∆PLL
–
–
6.0
100
20
150
µA
µA
µA
µA
µA
µA
µA
WDTE bit set, VDD = 4.35V
BODEN bit set, VDD = 5.0V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
1A
FOSC
HS oscillator operating freq.
H4 oscillator operating freg.
EC oscillator operating freq.
E4 oscillator operating freq.
24
6
24
6
—
—
—
—
24
6
24
6
MHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consump-
tion.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for
design guidance only. This is not tested.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD
or IPD measurement.
6: Module differential currents measured at FINT = 24 MHz.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 125
PIC16C745/765
16.2
DC Characteristics:
PIC16C745/765 (Commercial, Industrial)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤
-40°C ≤ TA ≤
+70°C for commercial
+85°C for industrial
Operating voltage VDD range as described in DC spec Section 16.1
and Section 16.2
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports
VIL
D030
with TTL buffer
VSS
0.8
V
D030A
D031
D032
D033
with Schmitt Trigger buffer
MCLR, OSC1 (in EC, E4 mode)
OSC1 (in HS, H4 mode)
Input High Voltage
I/O ports
VSS
VSS
VSS
0.2 VDD
0.2 VDD
0.3 VDD
V
V
V
For entire VDD range
Note 1
VIH
D040
D041
D042
D042A
D043
with TTL buffer
2.0
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
with Schmitt Trigger buffer
MCLR
0.8 VDD
0.8 VDD
0.7 VDD
0.9 VDD
For entire VDD range
OSC1 (HS, H4 mode)
OSC1 (in EC, E4 mode)
Note 1
Input Leakage Current
(Notes 2, 3)
D060
IIL
I/O ports
±1
µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
±5
±5
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD,
HS osc mode
D070
IPURB
AVIH
PORTB weak pull-up current
50
250
400
µA VDD = 5V, VPIN = VSS
D+ In
D- In
D+ Out
D- Out
D+ In
D- In
D+ Out
D- Out
V
V
V
V
V
V
V
V
AVOH
AVIL
AVOL
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels repre-
sent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS41124A-page 126
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
DC Characteristics:
DC CHARACTERISTICS
PIC16C745/765 (Commercial, Industrial) (CONTINUED)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
0°C ≤ TA ≤ +70°C for commercial
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec
Section 16.1 and Section 16.2
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
Output Low Voltage
I/O ports
D080
D083
VOL
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.35V,
-40°C to +85°C
OSC2/CLKOUT (EC, E4 osc mode)
IOL = 1.6 mA, VDD = 4.35V,
-40°C to +85°C
Output High Voltage
D090
D092
D150*
VOH
VOD
I/O ports (Note 3)
VDD-0.7
VDD-0.7
V
V
V
IOH = -3.0 mA, VDD = 4.35V,
-40°C to +85°C
OSC2/CLKOUT (EC osc mode)
IOH = -1.3 mA, VDD = 4.35V,
-40°C to +85°C
Open-Drain High Voltage
10.5
RA4 pin
Capacitive Loading Specs on Out-
put Pins
D100
D101
COSC2 OSC2 pin
15
50
pF In HS mode when external clock
is used to drive OSC1.
CIO
All I/O pins and OSC2 (in EC mode)
pF
CVUSB Vusb regulation capacitor
*These parameters are characterized but not tested.
.01
µF + 20%
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In EC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels repre-
sent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 127
PIC16C745/765
16.3
AC (Timing) Characteristics
16.3.1 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
DS41124A-page 128
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
16.3.2 TIMING CONDITIONS
The temperature and voltages specified in Table 16-1
apply to all timing specifications unless otherwise
noted. Figure 16-2 specifies the load conditions for the
timing specifications.
TABLE 16-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated)
Operating temperature 0°C ≤ TA ≤ +70°C for commercial
AC CHARACTERISTICS
-40°C ≤ TA ≤ +85°C for industrial
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2. LC parts operate for commercial/industrial temperatures only.
FIGURE 16-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
CL
RL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins except OSC2/CLKOUT
and USB pins, but including D and E(1)
outputs as ports
VSS
CL = 15 pF for OSC2 output
Note 1: PIC16C765 only.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 129
PIC16C745/765
16.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 16-3: EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
4
Q4
Q1
OSC1
3
3
1
4
2
CLKOUT
FIGURE 16-4: CLOCK MULTIPLIER (PLL) PHASE RELATIONSHIP
OSC1/
CLKIN
FINT
Note 1: FINT represents the internal clock signal. FINT equals FOSC or CLKIN if the PLL is disabled. FINT
equals 4x FOSC or 4x CLKIN if the PLL is enabled. TCY is always 4/FINT. FINT is OSC1 pin in EC
mode, PLL disabled.
2: FINT = OSC1 in EC mode with PLL disabled.
DS41124A-page 130
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
TABLE 16-2: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
24
Units Conditions
1A
FOSC
External CLKIN Frequency
(Note 1)
24
6
—
—
—
—
—
—
—
—
—
—
MHz EC osc mode
MHz E4 osc mode
MHz HS osc mode
MHz H4 osc mode
6
24
6
Oscillator Frequency
(Note 1)
24
6
1
TOSC
TCY
External CLKIN Period
(Note 1)
41
167
41
167
167
41
167
41
167
DC
—
ns
ns
ns
ns
ns
ns
EC osc modes
E4 osc mode
HS osc modes
H4 osc mode
TCY = 4/FINT
EC oscillator
Oscillator Period
(Note 1)
2
Instruction Cycle Time (Note 1)
3*
TOSL,
TOSH
External Clock in (OSC1) High or Low TBD
Time
4*
TOSR, External Clock in (OSC1) Rise or Fall TBD
TOSF Time
—
25
ns
EC oscillator
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period when the PLL is enabled, or the input
oscillator time-base period divided by 4 when the PLL is disabled. All specified values are based on characterization data
for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these
specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices
are tested to operate at “min.” values with an external clock applied to the OSC1/CLKIN pin. When an external clock input
is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 131
PIC16C745/765
FIGURE 16-5: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
FINT
11
10
CLKOUT
13
12
19
18
14
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-3: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
10*
TOSH2CKL OSC1↑ to CLKOUT↓
TOSH2CKH OSC1↑ to CLKOUT↑
—
—
—
—
—
75
75
35
35
—
—
—
50
—
—
—
10
—
10
—
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
11*
12*
200
100
100
TCKR
CLKOUT rise time
13*
TCKF
CLKOUT fall time
14*
TCKL2IOV
TIOV2CKH
TCKH2IOI
TOSH2IOV
TOSH2IOI
CLKOUT ↓ to Port out valid
Port in valid before CLKOUT ↑
Port in hold after CLKOUT ↑
OSC1↑ (Q1 cycle) to Port out valid
0.5 TCY + 20
15*
TOSC + 200
—
—
16*
0
—
17*
150
—
18*
OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold
100
200
0
time)
18A*
19*
—
TIOV2OSH Port input valid to OSC1↑ (I/O in setup time)
—
20*
TIOR
Port output rise time
—
40
80
40
80
20A*
21*
—
TIOF
Port output fall time
—
21A*
—
22††* TINP
23††* TRBP
INT pin high or low time
TCY
TCY
—
—
—
—
ns
ns
RB<7:4> change INT high or low time
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
††These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in EC Mode where CLKOUT output is 4 x TOSC.
2: FINT = OSC1 when PLL
DS41124A-page 132
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 16-2 for load conditions.
FIGURE 16-7: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Param No. Sym
Characteristic
Min
Typ†
Max
Units Conditions
30
TMCL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40°C to +85°C
31*
TWDT
Watchdog Timer Time-out
Period (No Prescaler)
7
18
33
ms
VDD = 5V, -40°C to +85°C
32
33*
34
TOST
Oscillation Start-up Timer Period
Power-up Timer Period
—
28
—
1024 TOSC
—
—
ms
µs
TOSC = OSC1 period
TPWRT
TIOZ
72
—
132
2.1
VDD = 5V, -40°C to +85°C
I/O Hi-impedance from MCLR
Low or WDT reset
35
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 133
PIC16C745/765
FIGURE 16-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
41
40
42
T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40*
TT0H
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
10
0.5 TCY + 20
10
ns
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
ns Must also meet
parameter 42
ns
TCY + 40
ns
With Prescaler Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4,..., 256)
N
45*
46*
47*
TT1H
TT1L
TT1P
T1CKI High Time Synchronous, Prescaler = 1
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
15
ns
25
ns
Asynchronous
30
ns
50
ns
T1CKI Low Time Synchronous, Prescaler = 1
0.5 TCY + 20
ns Must also meet
parameter 47
Synchronous,
Prescaler = 2,4,8
15
25
30
50
ns
ns
ns
ns
Asynchronous
T1CKI input
period
Synchronous
Asynchronous
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Greater of:
50 OR TCY + 40
N
N = prescale value
(1, 2, 4, 8)
60
100
DC
—
—
—
—
—
ns
ns
FT1
Timer1 oscillator input frequency range
200 kHz
(oscillator enabled by setting bit T1OSCEN)
48
TCKEZTMR1 Delay from external clock edge to timer increment
2Tosc
—
7Tosc
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124A-page 134
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
CCPx
(Capture Mode)
50
51
52
54
CCPx
(Compare or PWM Mode)
53
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param
No.
Sym Characteristic
Min
0.5 TCY + 20
Typ† Max Units Conditions
50*
TCCL CCP1 and CCP2 No Prescaler
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
input low time
With Prescaler
10
ns
20
ns
51*
TCCH CCP1 and CCP2 No Prescaler
0.5 TCY + 20
ns
input high time
With Prescaler
10
20
ns
ns
52*
53*
TCCP CCP1 and CCP2 input period
TCCR CCP1 and CCP2 output rise time
3 TCY + 40
ns N = prescale
N
value (1,4, or 16)
—
—
—
—
10
25
10
25
25
45
25
45
ns
ns
ns
ns
54*
TCCF CCP1 and CCP2 output fall time
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 135
PIC16C745/765
FIGURE 16-10: PARALLEL SLAVE PORT TIMING (PIC16C745/765)
RE2/CS
RE0/RD
RE1/WR
65
RD<7:0>
62
64
63
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-7: PARALLEL SLAVE PORT REQUIREMENTS
Param No. Sym
Characteristic
Min Typ†
Max
—
Units
ns
Conditions
62*
TDTV2WRH Data in valid before WR↑ or CS↑ (setup time)
TWRH2DTI WR↑ or CS↑ to data–in invalid (hold time)
20
20
35
—
10
—
—
—
—
—
63*
—
ns
—
ns
64
TRDL2DTV RD↓ and CS↓ to data–out valid
TRDH2DTI RD↑ or CS↑ to data–out invalid
80
30
ns
65*
ns
*These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
DS41124A-page 136
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
Note: Refer to Figure 16-2 for load conditions.
122
TABLE 16-8: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
120*
TCKH2DTV
SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
—
—
—
—
—
—
—
80
ns
ns
ns
ns
ns
ns
—
—
—
—
—
100
45
121*
122*
TCKRF
TDTRF
Clock out rise time and fall time (Master Mode)
Data out rise time and fall time
50
45
50
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 16-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK pin
125
RC7/RX/DT pin
126
Note: Refer to Figure 16-2 for load conditions.
TABLE 16-9: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max
Units Conditions
125*
TDTV2CKL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
—
—
ns
ns
126*
TCKL2DTL
Data hold after CK ↓ (DT hold time)
15
*These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 137
PIC16C745/765
TABLE 16-10: A/D CONVERTER CHARACTERISTICS:
PIC16C745/765 (COMMERCIAL, INDUSTRIAL)
Param
Sym Characteristic
NR Resolution
EABS Total Absolute error
Min
Typ†
Max
8 bits
Units Conditions
No.
A01
A02
—
—
—
—
bit
< ± 1
< ± 1
< ± 1
< ± 1
< ± 1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
A04
A05
A06
EIL
Integral linearity error
Differential linearity error
Full scale error
—
—
—
—
—
—
—
—
—
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EDL
EFS
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EOFF Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
A20
A25
A30
—
Monotonicity (Note 3)
guaranteed
—
—
V
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
2.5V
VSS - 0.3
—
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VAIN
ZAIN
Analog input voltage
V
Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD
A/D conversion current (VDD)
—
—
10
180
90
—
—
µA Average current consump-
tion when A/D is on. (Note 1)
µA
IREF
VREF input current (Note 2)
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 12.1.
During A/D Conversion cycle
µA
—
—
10
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes
any such leakage from the A/D module.
2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS41124A-page 138
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
FIGURE 16-13: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
134
(TOSC/2) (1)
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 16-11: A/D CONVERSION REQUIREMENTS
Param
No.
Sym Characteristic
A/D clock period
Min
1.6
Typ†
Max
Units Conditions
130
TAD
—
—
—
—
µs
µs
TOSC based, VREF ≥ 3.0V
2.0
TOSC based,
2.5V ≤ VREF ≤ 5.5V
2.0
3.0
11
4.0
6.0
—
6.0
9.0
11
µs
µs
A/D RC Mode
A/D RC Mode
131
132
TCNV Conversion time (not including S/H time)
TAD
(Note 1)
TACQ Acquisition time
5*
—
—
µs
The minimum time is the ampli-
fier settling time. This may be
used if the “new” input voltage
has not changed by more than 1
LSb (i.e., 20.0 mV @ 5.12V)
from the last sampled voltage
(as stated on CHOLD).
134
135
TGO
Q4 to A/D clock start
—
TOSC/2
—
—
If the A/D clock source is
selected as RC, a time of TCY is
added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
TSWC Switching from convert → sample time
1.5 §
—
—
TAD
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 for min conditions.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 139
PIC16C745/765
FIGURE 16-14: MAXIMUM INPUT WAVEFORM TIMING SPECIFICATIONS
66.7ns
RSRC
6MHz
60ns
min
Pin
V
4.6V
-1.0V
RSRC = 39Ω ± 2%
4ns
min
4ns
min
20ns
max
20ns
max
Note 1: The D+/D- signals can withstand a continuous short to VBUS, GND, cable shield or any other signal.
FIGURE 16-15: USB LOW SPEED SIGNALING
Data Differential Lines
90%
90%
72
10%
10%
71
70
TABLE 16-12: USB AC AND DC SPECIFICATIONS
Parameter Sym
No.
Characteristic
Min TYP† Max
Units Conditions
70
TLR
Transition Rise Time
75
75
1.3
80
300
300
2.0
ns
ns
V
71
72
TLF
Transition Fall Time
VCRS
TLRFM
VIL
Crossover Voltage
Rise and Fall Time Matching
Voltage Input Low
125
0.8
%
V
VIH
Voltage Input High
2.0
2.7
0.2
0.8
0.0
2.8
2.7
V
VIHZ
Voltage Input High Floating
Differential Input Sensitivity
Differential Common Mode Range
Voltage Output Low
3.6
V
V
V
V
V
V
(D+)-(D-)
2.5
0.3
3.6
3.6
VOL
VOH
VUSB
Voltage Output High
USB Voltage Output
DS41124A-page 140
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
17.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
Graphs and Tables not available at this time.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 141
PIC16C745/765
NOTES:
DS41124A-page 142
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
18.0 PACKAGING INFORMATION
18.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
Example
MMMMMMMMMMMM
XXXXXXXXXXXXXXX
YYMMNNN
PIC16C745/SP
9917017
28-Lead SOIC
MMMMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXXXX
PIC16C745/SO
9917017
YYMMNNN
28-Lead CERDIP Windowed
Example
PIC16C745/JW
9905017
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend: MM...M Microchip part number information
XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 143
PIC16C745/765
Package Marking Information (Cont’d)
40-Lead PDIP
Example
PIC16C765/P
9917017
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
YYMMNNN
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
PIC16C765/PT
9917017
YYMMNNN
44-Lead PLCC
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
YYMMNNN
PIC16C765/L
9917017
DS41124A-page 144
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
β
B1
A1
p
eB
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
28
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
A
.140
.160
3.56
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.125
.015
.300
.279
1.345
.125
.008
.040
.016
.320
5
.135
3.18
0.38
7.62
7.09
34.16
3.18
0.20
1.02
0.41
8.13
5
3.43
.313
.307
1.365
.130
.012
.053
.019
.350
10
.325
.335
1.385
.135
.015
.065
.022
.430
15
7.94
7.80
34.67
3.30
0.29
1.33
0.48
8.89
10
8.26
8.51
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
eB
α
β
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 145
PIC16C745/765
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS41124A-page 146
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
E1
W
D
2
n
1
E
A2
A
L
c
B1
eB
A1
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
28
28
.100
.185
.160
.038
.600
.520
1.460
.138
.010
.058
.020
.660
.280
2.54
4.70
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.200
.165
.060
.625
.526
1.490
.150
.012
.065
.023
.710
.290
4.32
5.08
A2
A1
.155
.015
.595
.514
1.430
.125
.008
.050
.016
.610
.270
3.94
0.38
4.06
4.19
1.52
0.95
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.11
13.06
36.32
3.18
15.24
13.21
37.08
3.49
15.88
13.36
37.85
3.81
Tip to Seating Plane
Lead Thickness
c
0.20
0.25
0.30
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B1
B
1.27
1.46
1.65
0.41
0.51
0.58
eB
W
15.49
6.86
16.76
7.11
18.03
7.37
*Controlling Parameter
JEDEC Equivalent: MO-103
Drawing No. C04-013
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 147
PIC16C745/765
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
eB
α
β
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
DS41124A-page 148
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
*Controlling Parameter
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 149
PIC16C745/765
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
B1
B
α
β
0
5
10
0
5
10
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS41124A-page 150
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
INDEX
C
C bit ................................................................................... 22
Capture/Compare/PWM
A
A/D
Capture
ADCON0 Register ..................................................... 89
Block Diagram ................................................... 53
CCP1CON Register .......................................... 52
CCP1IF ............................................................. 53
Mode ................................................................. 53
Prescaler ........................................................... 53
CCP Timer Resources .............................................. 51
Compare
Analog Input Model Block Diagram............................. 92
Analog-to-Digital Converter......................................... 89
Block Diagram ........................................................... 91
Configuring Analog Port Pins .................................... 93
Configuring the Interrupt ............................................ 91
Configuring the Module ............................................. 91
Conversion Clock ...................................................... 93
Conversions .............................................................. 93
Converter Characteristics ........................................ 138
Effects of a Reset ...................................................... 94
Faster Conversion - Lower Resolution Tradeoff ........ 93
Internal Sampling Switch (Rss) Impedance .............. 92
Operation During Sleep ............................................. 94
Sampling Requirements ............................................ 92
Source Impedance .................................................... 92
Timing Diagram ....................................................... 139
Using the CCP Trigger .............................................. 94
Absolute Maximum Ratings ............................................. 123
ADRES Register ......................................................... 17, 89
Application Notes
Block Diagram ................................................... 54
Mode ................................................................. 54
Software Interrupt Mode ................................... 54
Special Event Trigger ........................................ 54
Special Trigger Output of CCP1 ....................... 54
Special Trigger Output of CCP2 ....................... 54
Interaction of Two CCP Modules.................... 51
Section ...................................................................... 51
Special Event Trigger and A/D Conversions ............. 54
Capture/Compare/PWM (CCP)
PWM Block Diagram ................................................. 54
PWM Mode ............................................................... 54
Timing Diagram ....................................................... 135
CCP1CON ......................................................................... 19
CCP2CON ......................................................................... 19
CCPR1H Register ............................................... 17, 19, 51
CCPR1L Register ....................................................... 19, 51
CCPR2H Register ...................................................... 17, 19
CCPR2L Register ....................................................... 17, 19
Clocking Scheme .............................................................. 13
Code Examples
AN552, Implementing Wake-up on Key Strokes Using
PIC16CXXX ............................................................... 33
AN556, Table Reading Using PIC16CXX ................. 29
AN607, Power-up Trouble Shooting .......................... 99
Architecture
Overview ..................................................................... 9
Assembler
MPASM Assembler ................................................. 117
Call of a Subroutine in Page 1 from Page 0 .............. 29
Changing Prescaler (Timer0 to WDT) ....................... 44
Indirect Addressing ................................................... 30
Initializing PORTA ..................................................... 31
Code Protection ....................................................... 95, 108
Computed GOTO .............................................................. 29
Configuration Bits .............................................................. 95
Control ............................................................................... 60
CREN bit ........................................................................... 76
CS pin ............................................................................... 40
B
Baud Rate Formula ........................................................... 77
Block Diagrams
A/D ............................................................................ 91
Analog Input Model ................................................... 92
Capture ...................................................................... 53
Compare .................................................................... 54
On-Chip Reset Circuit ............................................... 98
PORTC ...................................................................... 35
PORTD (In I/O Port Mode) ........................................ 37
PORTD and PORTE as a Parallel Slave Port ........... 40
PORTE (In I/O Port Mode) ........................................ 38
PWM .......................................................................... 54
RA4/T0CKI Pin .......................................................... 31
RB Port Pins .............................................................. 33
RB Port Pins .............................................................. 33
Timer0/WDT Prescaler .............................................. 43
Timer2 ....................................................................... 49
USART Receive ........................................................ 81
USART Transmit ....................................................... 79
Watchdog Timer ...................................................... 106
BOR bit .............................................................................. 99
BRGH bit ........................................................................... 77
Brown-out Reset (BOR)
D
DC bit ................................................................................ 22
DC Characteristics ........................................ 125, 126, 127
Development Support ................................................ 5, 117
Direct Addressing .............................................................. 30
E
EC Oscillator ................................................................... 100
Electrical Characteristics ................................................. 123
Endpoint ............................................................................ 70
Errata .................................................................................. 3
Error .................................................................................. 63
F
FERR bit ............................................................................ 76
FSR Register ................................................ 17, 18, 20, 30
G
Timing Diagram ....................................................... 133
Buffer Descriptor Table ...................................................... 68
General Description ............................................................ 5
GIE bit ............................................................................. 103
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 151
PIC16C745/765
I
K
I/O Ports ............................................................................31
PORTA ......................................................................31
PORTB ......................................................................33
PORTC ......................................................................35
PORTD ...............................................................37, 40
PORTE ......................................................................38
In-Circuit Serial Programming ..................................95, 108
INDF ...........................................................................19, 20
INDF Register ...................................................... 17, 18, 30
Indirect Addressing ............................................................30
Instruction Cycle ................................................................13
Instruction Flow/Pipelining .................................................13
Instruction Format ............................................................109
Instruction Set
KeeLoq Evaluation and Programming Tools ................ 120
L
Loading of PC ................................................................... 29
M
MCLR ....................................................................... 97, 100
Memory
Data Memory ............................................................. 15
Program Memory ...................................................... 15
Program Memory Maps
PIC16C745/765 ................................................ 15
MPLAB Integrated Development Environment Software 117
O
OERR bit ........................................................................... 76
OPCODE ......................................................................... 109
OPTION Register .............................................................. 23
OSC selection ................................................................... 95
Oscillator
E4 .............................................................................. 96
EC ............................................................................. 96
H4 .............................................................................. 96
HS .................................................................... 96, 100
Oscillator Configurations ................................................... 96
Output of TMR2 ................................................................. 49
ADDLW ....................................................................111
ADDWF ...................................................................111
ANDLW ....................................................................111
ANDWF ...................................................................111
BCF .........................................................................111
BSF ..........................................................................111
BTFSC .....................................................................112
BTFSS .....................................................................112
CALL ........................................................................112
CLRF .......................................................................112
CLRW ......................................................................112
CLRWDT .................................................................112
COMF ......................................................................113
DECF .......................................................................113
DECFSZ ..................................................................113
GOTO ......................................................................113
INCF ........................................................................113
INCFSZ ....................................................................113
IORLW .....................................................................114
IORWF .....................................................................114
MOVF ......................................................................114
MOVLW ...................................................................114
MOVWF ...................................................................114
NOP .........................................................................114
RETFIE ....................................................................115
RETLW ....................................................................115
RETURN ..................................................................115
RLF ..........................................................................115
RRF .........................................................................115
SLEEP .....................................................................115
SUBLW ....................................................................116
SUBWF ....................................................................116
SWAPF ....................................................................116
XORLW ...................................................................116
XORWF ...................................................................116
Summary Table .......................................................110
Instruction Set Summary .................................................109
INT Interrupt ....................................................................105
INTCON .............................................................................20
INTCON Register ..............................................................24
INTEDG bit ......................................................................105
Internal Sampling Switch (Rss) Impedance .......................92
Interrupts ..................................................................95, 103
PortB Change ..........................................................105
RB Port Change ........................................................33
TMR0 .......................................................................105
IRP bit ................................................................................22
P
Packaging ....................................................................... 143
Paging, Program Memory ................................................. 29
Parallel Slave Port ...................................................... 37, 40
Parallel Slave Port (PSP)
Timing Diagram ....................................................... 136
PCL Register ....................................................... 17, 18, 29
PCLATH .......................................................................... 101
PCLATH Register ......................................... 17, 18, 20, 29
PCON Register ........................................................... 28, 99
PD bit ......................................................................... 22, 97
PICDEM-1 Low-Cost PICmicro Demo Board .................. 119
PICDEM-2 Low-Cost PIC16CXX Demo Board ............... 119
PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 119
PICSTART Plus Entry Level Development System ..... 119
PIE1 Register .................................................................... 25
PIE2 Register .................................................................... 27
Pinout Descriptions
PIC16C745/765 ......................................................... 11
PIR1 Register .................................................................... 26
PIR2 Register .................................................................... 27
POP ................................................................................... 29
POR .................................................................................. 99
Oscillator Start-up Timer (OST) ......................... 95, 99
Power Control Register (PCON) ............................... 99
Power-on Reset (POR) ............................. 95, 99, 101
Power-up Timer (PWRT) ........................................... 95
Power-Up-Timer (PWRT) .......................................... 99
TO ............................................................................. 97
POR bit .............................................................................. 99
Port RB Interrupt ............................................................. 105
PORTA ..................................................................... 20, 101
PORTA Register ......................................................... 17, 31
PORTB ..................................................................... 20, 101
PORTB Register ......................................................... 17, 33
PORTC ..................................................................... 20, 101
PORTC Register ........................................................ 17, 35
PORTD ..................................................................... 20, 101
PORTD Register ........................................................ 17, 37
PORTE ..................................................................... 20, 101
DS41124A-page 152
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
PORTE Register ......................................................... 17, 38
Power-down Mode (SLEEP) ............................................ 107
Power-on Reset (POR)
Timing Diagram......................................................... 133
PR2 Register .............................................................. 18, 49
PRO MATE II Universal Programmer ........................... 119
Product Identification System .......................................... 159
Program Counter
PCLATH Register .................................................... 105
Program Memory
Paging ....................................................................... 29
Program Memory Maps
T
T1CKPS0 bit ..................................................................... 45
T1CKPS1 bit ..................................................................... 45
T1CON .............................................................................. 20
T1CON Register ......................................................... 19, 45
T1OSCEN bit .................................................................... 45
T1SYNC bit ....................................................................... 45
T2CKPS0 bit ..................................................................... 49
T2CKPS1 bit ..................................................................... 49
T2CON Register ......................................................... 19, 49
TAD .................................................................................... 93
Timer0
PIC16C745/765 ......................................................... 15
Program Verification ........................................................ 108
PSPMODE bit ...................................................... 37, 38, 40
PUSH ................................................................................. 29
RTCC ...................................................................... 101
Timing Diagram ....................................................... 134
Timer1
Timing Diagram ....................................................... 134
Timers
R
Timer0 ....................................................................... 43
External Clock ................................................... 44
Interrupt ............................................................. 43
Prescaler ........................................................... 44
Prescaler Block Diagram .................................. 43
T0CKI ................................................................ 44
T0IF ................................................................. 105
TMR0 Interrupt ................................................ 105
Timer1
Asynchronous Counter Mode ........................... 47
Capacitor Selection ........................................... 47
Operation in Timer Mode .................................. 46
Oscillator ........................................................... 47
Prescaler ........................................................... 47
Resetting of Timer1 Registers .......................... 47
Resetting Timer1 using a CCP Trigger Output . 47
Synchronized Counter Mode ............................ 46
T1CON .............................................................. 45
TMR1H .............................................................. 47
TMR1L .............................................................. 47
Timer2
RBIF bit ..................................................................... 33, 105
RCREG ................................................................................ 9
RCSTA Register ......................................................... 19, 76
RD pin ................................................................................ 40
Register File ...................................................................... 15
Registers
FSR Summary ........................................................... 19
INDF Summary .......................................................... 19
INTCON Summary .................................................... 19
PCL Summary ........................................................... 19
PCLATH Summary .................................................... 19
PORTB Summary ...................................................... 19
Reset Conditions ..................................................... 100
Special Function Register Summary ......................... 17
STATUS Summary .................................................... 19
TMR0 Summary ........................................................ 19
TRISB Summary ....................................................... 20
Reset .......................................................................... 95, 97
Timing Diagram ....................................................... 133
Reset Conditions for Special Registers ........................... 100
RP0 bit ........................................................................ 15, 22
RP1 bit ............................................................................... 22
RX9 bit ............................................................................... 76
RX9D bit ............................................................................ 76
Block Diagram ................................................... 49
Module .............................................................. 49
Postscaler ......................................................... 49
Prescaler ........................................................... 49
T2CON .............................................................. 49
Timing Diagrams
S
SEEVAL Evaluation and Programming System ........... 120
Services
USART Asynchronous Master Transmission ............ 80
USART Asynchronous Reception ............................. 81
USART Synchronous Reception ............................... 86
USART Synchronous Transmission .......................... 84
Wake-up from Sleep via Interrupt .................. 104, 108
Timing Diagrams and Specifications ............................... 130
A/D Conversion ....................................................... 139
Brown-out Reset (BOR) .......................................... 133
Capture/Compare/PWM (CCP) ............................... 135
CLKOUT and I/O ..................................................... 132
External Clock ......................................................... 130
Oscillator Start-up Timer (OST) .............................. 133
Parallel Slave Port (PSP) ........................................ 136
Power-up Timer (PWRT) ......................................... 133
Reset ....................................................................... 133
Timer0 and Timer1 .................................................. 134
USART Synchronous Receive ( Master/Slave) ....... 137
USART Synchronous Transmission
One-Time-Programmable (OTP) ................................. 7
Quick-Turnaround-Production (QTP) .......................... 7
Serialized Quick-Turnaround Production (SQTP) ....... 7
SLEEP ........................................................................ 95, 97
Software Simulator (MPLAB-SIM) ................................... 118
SPBRG Register ................................................................ 18
Special Features of the CPU ............................................. 95
Special Function Registers ................................................ 17
PIC16C745/765 ......................................................... 17
SPEN bit ............................................................................ 76
SREN bit ............................................................................ 76
SSPBUF ............................................................................ 19
Stack .................................................................................. 29
Overflows .................................................................. 29
Underflow .................................................................. 29
Status ................................................................................ 64
STATUS Register ..................................................... 22, 105
Synchronous Serial Port Module ....................................... 57
( Master/Slave) ........................................................ 137
Watchdog Timer (WDT) .......................................... 133
TMR0 ................................................................................ 20
TMR0 Register .................................................................. 17
TMR1CS bit ....................................................................... 45
1999 Microchip Technology Inc.
Advanced Information
DS41124A-page 153
PIC16C745/765
TMR1H ..............................................................................20
TMR1H Register ................................................................17
TMR1L ...............................................................................20
TMR1L Register ................................................................17
TMR1ON bit .......................................................................45
TMR2 .................................................................................20
TMR2 Register ..................................................................17
TMR2ON bit .......................................................................49
TO bit .................................................................................22
TOUTPS0 bit .....................................................................49
TOUTPS1 bit .....................................................................49
TOUTPS2 bit .....................................................................49
TOUTPS3 bit .....................................................................49
TRISA Register ...........................................................18, 31
TRISB Register ...........................................................18, 33
TRISC Register ..........................................................18, 35
TRISD Register ..........................................................18, 37
TRISE Register .................................................... 18, 38, 39
TXREG ..............................................................................19
TXSTA Register .................................................................75
U
Universal Synchronous Asynchronous
Receiver Transmitter (USART) ..........................................75
USART
Asynchronous Mode ..................................................79
Asynchronous Receiver .............................................81
Asynchronous Reception ...........................................82
Asynchronous Transmitter .........................................79
Baud Rate Generator (BRG) .....................................77
Receive Block Diagram .............................................81
Sampling ....................................................................77
Synchronous Master Mode ........................................83
Timing Diagram, Synchronous Receive ..........137
Timing Diagram, Synchronous Transmission ..137
Synchronous Master Reception ................................85
Synchronous Master Transmission ...........................83
Synchronous Slave Mode ..........................................87
Synchronous Slave Reception ..................................87
Synchronous Slave Transmit .....................................87
Transmit Block Diagram ............................................79
USB .......................................................21, 58, 60, 61, 62
USB Address Register .......................................................66
USB Control Register ........................................................65
USB Endpoint Control Register...........................................67
UV Erasable Devices ...........................................................7
W
W Register .......................................................................105
Wake-up from SLEEP .....................................................107
Watchdog Timer (WDT) ............................95, 97, 100, 106
Timing Diagram .......................................................133
WDT ................................................................................100
Block Diagram .........................................................106
Period ......................................................................106
Programming Considerations ..................................106
Timeout ....................................................................101
WR pin ...............................................................................40
WWW, On-Line Support ......................................................3
Z
Z bit ....................................................................................22
DS41124A-page 154
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
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DS41124A-page 155
PIC16C745/765
READER RESPONSE
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DS41124A-page 156
Advanced Information
1999 Microchip Technology Inc.
PIC16C745/765
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a) PIC16C745/P 301 = Commercial temp., PDIP
package, 6 MHz, QTP pattern #301.
Device
PIC16C745(1), PIC16C745T(2)
PIC16C765(1), PIC16C765T(2)
Temperature Range
Package
blank
I
=
=
0°C to
70°C (Commercial)
Note 1:
Note 2:
C
T
= CMOS
= in tape and reel - SOIC,
PLCC, TQFP, packages only.
-40°C to +85°C (Industrial)
JW
PT
SO
SP
P
=
=
=
=
=
=
Windowed CERDIP - 600 mil
TQFP (Thin Quad Flatpack)
SOIC
Skinny plastic dip
PDIP
L
PLCC
Pattern
QTP Code or Special Requirements
(blank otherwise)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
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Advanced Information
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WORLDWIDE SALES AND SERVICE
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Taipei, Taiwan, ROC
ASIA/PACIFIC
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
Atlanta
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Microchip Technology Inc.
5 Mount Royal Avenue
Marlborough, MA 01752
Tel: 508-480-9990 Fax: 508-480-8575
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
Denmark
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 86-10-85282100 Fax: 86-10-85282104
India
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75248
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Shanghai
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Italy
Los Angeles
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
11/15/99
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
1999 Microchip Technology Inc.
相关型号：
PIC16C745T-I/SO
8-BIT, OTPROM, 24 MHz, RISC MICROCONTROLLER, PDSO28, 0.300 INCH, PLASTIC, MS-013, SO-28
MICROCHIP
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