PIC16C773-04I/PT_技术文档

PIC16C77X

28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D

Microcontroller Core Features:

Pin Diagram

600 mil. PDIP, Windowed CERDIP

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

MCLR/VPP

RA0/AN0

1

2

3

4

5

6

7

8

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

RB7

RB6

RA1/AN1

RA2/AN2/VREF-/VRL

RB5

RB4

RB3/AN9/LVDIN

RB2/AN8

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

RA3/AN3/VREF+/VRH

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

AVDD

RB1/SS

RB0/INT

VDD

• 4K x 14 words of Program Memory,

256 x 8 bytes of Data Memory (RAM)

9

10

11

12

13

14

15

16

17

18

19

20

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5/SDO

• Interrupt capability (up to 14 internal/external

interrupt sources)

AVSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

RC3/SCK/SCL

RD0/PSP0

RC4/SDI/SDA

RD3/PSP3

RD1/PSP1

RD2/PSP2

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Timer1: 16-bit timer/counter with prescaler,

can be incremented during sleep via external

crystal/clock

• Low-power, high-speed CMOS EPROM

technology

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Fully static design

• Two Capture, Compare, PWM modules

• In-Circuit Serial Programming (ISCP)

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial and Industrial temperature ranges

• Low-power consumption:

• Capture is 16-bit, max. resolution is 12.5 ns,

Compare is 16-bit, max. resolution is 200 ns,

PWM max. resolution is 10-bit

• 12-bit multi-channel Analog-to-Digital converter

*

• On-chip absolute bandgap voltage reference

generator

- < 2 mA @ 5V, 4 MHz

• Synchronous Serial Port (SSP) with SPI (Master

Mode) and I²C

- 22.5 µA typical @ 3V, 32 kHz

- < 1 µA typical standby current

• Universal Synchronous Asynchronous Receiver

Transmitter, supports high/low speeds and 9-bit

address mode (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with

external RD, WR and CS controls

• Programmable Brown-out detection circuitry for

Brown-out Reset (BOR)

*

Enhanced features

• Programmable Low-voltage detection circuitry

This is an advanced copy of the data sheet and therefore the contents and

specifications are subject to change based on device characterization.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 1

PIC16C77X

Pin Diagrams

300 mil. SDIP, SOIC, Windowed CERDIP, SSOP

MCLR/VPP

RA0/AN0

• 1

2

28

27

RB7

RB6

RA1/AN1

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

3

4

5

26

25

24

RB5

RB4

RB3/AN9/LVDIN

RA4/T0CKI

AVDD

6

7

8

23

22

21

RB2/AN8

RB1/SS

RB0/INT

AVSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

9

20

19

18

17

16

15

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

10

11

12

13

14

RC3/SCK/SCL

PLCC

RA4/T0CKI

RA5/AN4

RB3/AN9/LVDIN

7

8

9

39

38

37

36

35

34

33

32

31

30

29

RB2/AN8

RB1/SS

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

AVDD

10

11

12

13

14

15

16

17

RB0/INT

VDD

VSS

PIC16C774

AVSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

NC

MQFP

TQFP

NC

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

1

2

3

4

5

6

7

8

33

32

31

30

29

28

27

26

25

24

23

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

AVSS

AVDD

PIC16C774

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4

RB0/INT

RB1/SS

9

10

11

RB2/AN8

RB3/AN9/LVDIN

RA4/T0CKI

DS30275A-page 2

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Key Features

PICmicro™ Mid-Range Reference Manual

(DS33023)

PIC16C773

DC - 20 MHz

PIC16C774

Operating Frequency

Resets (and Delays)

DC - 20 MHz

POR, BOR, MCLR, WDT

(PWRT, OST)

POR, BOR, MCLR, WDT

(PWRT, OST)

Program Memory (14-bit words)

Data Memory (bytes)

Interrupts

4K

256

13

14

I/O Ports

Ports A,B,C

Ports A,B,C,D,E

Timers

3

Capture/Compare/PWM modules

Serial Communications

Parallel Communications

12-bit Analog-to-Digital Module

Instruction Set

2

MSSP, USART

—

MSSP, USART

PSP

6 input channels

35 Instructions

10 input channels

35 Instructions

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 3

PIC16C77X

Table of Contents

1.0 Device Overview ............................................................................................................................................................................ 5

2.0 Memory Organization................................................................................................................................................................... 11

3.0 I/O Ports....................................................................................................................................................................................... 27

4.0 Timer0 Module ............................................................................................................................................................................. 39

5.0 Timer1 Module ............................................................................................................................................................................. 41

6.0 Timer2 Module ............................................................................................................................................................................. 45

7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 47

8.0 Master Synchronous Serial Port (MSSP) Module........................................................................................................................ 53

9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................. 97

10.0 Voltage Reference Module and Low-voltage Detect.................................................................................................................. 113

11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117

12.0 Special Features of the CPU ..................................................................................................................................................... 127

13.0 Instruction Set Summary............................................................................................................................................................ 143

14.0 Development Support ................................................................................................................................................................ 145

15.0 Electrical Characteristics............................................................................................................................................................ 151

16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 173

17.0 Packaging Information ............................................................................................................................................................... 175

Appendix A: Revision History......................................................................................................................................................... 187

Appendix B: Device Differences..................................................................................................................................................... 187

Appendix C: Conversion Considerations........................................................................................................................................ 187

Index .................................................................................................................................................................................................. 189

Bit/Register Cross-Reference List...................................................................................................................................................... 196

On-Line Support................................................................................................................................................................................. 197

Reader Response .............................................................................................................................................................................. 198

PIC16C77X Product Identification System......................................................................................................................................... 199

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended

workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-

sion of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Web site; http://www.microchip.com

Your local Microchip sales office (see last page)

The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-

ature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure

that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing

or appears in error, please:

•

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We appreciate your assistance in making this a better document.

DS30275A-page 4

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

There a two devices (PIC16C773 and PIC16C774)

covered by this datasheet. The PIC16C773 devices

come in 28-pin packages and the PIC16C774 devices

come in 40-pin packages. The 28-pin devices do not

have a Parallel Slave Port implemented.

1.0

DEVICE OVERVIEW

This document contains device-specific information.

Additional information may be found in the PICmicro™

Mid-Range Reference Manual, (DS33023), which may

be obtained from your local Microchip Sales Represen-

tative or downloaded from the Microchip website. The

Reference Manual should be considered a comple-

mentary document to this data sheet, and is highly rec-

ommended reading for a better understanding of the

device architecture and operation of the peripheral

modules.

The following two figures are device block diagrams

sorted by pin number; 28-pin for Figure 1-1 and 40-pin

for Figure 1-2. The 28-pin and 40-pin pinouts are listed

in Table 1-1 and Table 1-2, respectively.

FIGURE 1-1: PIC16C773 BLOCK DIAGRAM

13

8

PORTA

Data Bus

Program Counter

EPROM

RA0/AN0

RA1/AN1

Program

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

RA4/T0CKI

Memory

RAM

File

Registers

8 Level Stack

(13-bit)

4K x 14

256 x 8

Program

Bus

14

RAM Addr ⁽¹⁾

PORTB

9

RB0/INT

RB1/SS

Addr MUX

Instruction reg

7

Indirect

Addr

RB2/AN8

RB3/AN9/LVDIN

RB7:RB4

Direct Addr

8

FSR reg

STATUS reg

PORTC

8

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

3

MUX

Instruction

Decode &

Control

Power-up

Timer

RC5/SDO

RC6/TX/CK

RC7/RX/DT

ALU

Timing

Generation

Oscillator

Start-up Timer

OSC1/CLKIN

8

OSC2/CLKOUT

Power-on

Reset

W reg

Watchdog

Timer

Precision

Reference

Low-voltage

Detect

Brown-out

Reset

MCLR VDD, VSS

AVDD

AVSS

12-bit

ADC

Timer0

Timer1

Timer2

USART

Synchronous

Serial Port

CCP1,2

Note 1: Higher order bits are from the STATUS register.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 5

PIC16C77X

FIGURE 1-2: PIC16C774 BLOCK DIAGRAM

13

8

PORTA

Data Bus

Program Counter

EPROM

RA0/AN0

RA1/AN1

Program

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

RA4/T0CKI

Memory

RAM

File

Registers

8 Level Stack

4K x 14

(13-bit)

RA5/AN4

256 x 8

Program

14

RAM Addr ⁽¹⁾

PORTB

Bus

9

RB0/INT

RB1/SS

RB2/AN8

RB3/AN9/LVDIN

RB7:RB4

Addr MUX

Instruction reg

7

Indirect

Addr

Direct Addr

8

FSR reg

STATUS reg

PORTC

8

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

3

MUX

Instruction

Decode &

Control

Power-up

Timer

RC6/TX/CK

RC7/RX/DT

ALU

Timing

Generation

Oscillator

OSC1/CLKIN

OSC2/CLKOUT

Start-up Timer

8

PORTD

Power-on

Reset

W reg

Watchdog

Timer

RD7/PSP7:RD0/PSP0

Brown-out

Reset

Precision

Reference

Low-voltage

Detect

PORTE

Parallel Slave Port

RE0/AN5/RD

MCLR VDD, VSS

RE1/AN6/WR

RE2/AN7/CS

AVDD

AVSS

12-bit

ADC

Timer0

Timer1

Timer2

USART

Synchronous

Serial Port

CCP1,2

Note 1: Higher order bits are from the STATUS register.

DS30275A-page 6

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 1-1

PIC16C773 PINOUT DESCRIPTION

DIP,

SSOP,

SOIC

Pin#

I/O/P

Type

Buffer

Type

Pin Name

Description

(3)

OSC1/CLKIN

9

I

Oscillator crystal input/external clock source input.

ST/CMOS

OSC2/CLKOUT

10

O

—

Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has

1/4 the frequency of OSC1, and denotes the instruction cycle rate.

1

I/P

ST

Master clear (reset) input or programming voltage input. This pin is an

active low reset to the device.

MCLR/VPP

PORTA is a bi-directional I/O port.

RA0 can also be analog input0

RA1 can also be analog input1

RA0/AN0

2

3

4

I/O

TTL

RA1/AN1

RA2/AN2/VREF-/VRL

RA2 can also be analog input2 or negative analog reference voltage

input or internal voltage reference low

RA3/AN3/VREF+/VRH

5

6

I/O

TTL

ST

RA3 can also be analog input3 or positive analog reference voltage

input or internal voltage reference high

RA4/T0CKI

RA4 can also be the clock input to the Timer0 module. Output is

open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs.

(1)

RB0/INT

21

22

23

24

I/O

TTL/ST

TTL

RB0 can also be the external interrupt pin.

RB1 can also be the SSP slave select

RB2 can also be analog input8

(1)

RB1/SS

RB2/AN8

RB3/AN9/LVDIN

TTL

RB3 can also be analog input9 or the low voltage detect input

reference

RB4

RB5

RB6

RB7

25

26

27

28

I/O

TTL

Interrupt on change pin.

(2)

TTL/ST

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

11

12

I/O

ST

RC0 can also be the Timer1 oscillator output or Timer1 clock input.

RC1 can also be the Timer1 oscillator input or Capture2 input/

Compare2 output/PWM2 output.

RC2/CCP1

13

14

15

I/O

ST

RC2 can also be the Capture1 input/Compare1 output/PWM1

output.

RC3/SCK/SCL

RC4/SDI/SDA

RC3 can also be the synchronous serial clock input/output for both

2

SPI and I C modes.

RC4 can also be the SPI Data In (SPI mode) or

2

data I/O (I C mode).

RC5/SDO

16

17

I/O

ST

RC5 can also be the SPI Data Out (SPI mode).

RC6/TX/CK

RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT

18

I/O

ST

RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

AVSS

8

7

P

Ground reference for A/D converter

Positive supply for A/D converter

AVDD

VSS

19

20

—

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

VDD

Legend: I = input

O = output

— = Not used

I/O = input/output

TTL = TTL input

P = power

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 7

PIC16C77X

TABLE 1-2

PIC16C774 PINOUT DESCRIPTION

DIP

Pin#

PLCC

Pin#

QFP I/O/P

Pin# Type

Buffer

Type

Pin Name

Description

(4)

OSC1/CLKIN

13

14

15

30

31

I

ST/CMOS

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

—

Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

MCLR/VPP

1

2

18

I/P

ST

Master clear (reset) input or programming voltage input.

This pin is an active low reset to the device.

PORTA is a bi-directional I/O port.

RA0 can also be analog input0

RA1 can also be analog input1

RA0/AN0

2

3

4

3

4

5

19

20

21

I/O

TTL

RA1/AN1

RA2 can also be analog input2 or negative analog

reference voltage input or internal voltage reference

low

RA2/AN2/VREF-/VRL

RA3 can also be analog input3 or positive analog

reference voltage input or internal voltage reference

high

RA3/AN3/VREF+/VRH

5

6

22

I/O

TTL

RA4/T0CKI

RA5/AN4

6

7

8

23

24

I/O

ST

RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

TTL

RA5 can also be analog input4

PORTB is a bi-directional I/O port. PORTB can be soft-

ware programmed for internal weak pull-up on all inputs.

(1)

RB0/INT

33

34

35

36

37

38

39

8

9

I/O

TTL/ST

TTL

RB0 can also be the external interrupt pin.

RB1 can also be the SSP slave select

RB2 can also be analog input8

(1)

RB1/SS

RB2/AN8

10

11

RB3/AN9/LVDIN

TTL

RB3 can also be analog input9 or input reference for

low voltage detect

RB4

RB5

RB6

37

38

39

41

42

43

44

14

15

16

17

I/O

TTL

Interrupt on change pin.

(2)

TTL/ST

Interrupt on change pin. Serial programming clock.

Interrupt on change pin. Serial programming data.

RB7

40

Legend: I = input

O = output

— = Not used

I/O = input/output

TTL = TTL input

P = power

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

DS30275A-page 8

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 1-2

PIC16C774 PINOUT DESCRIPTION (Cont.’d)

DIP

Pin#

PLCC

Pin#

QFP I/O/P

Pin# Type

Buffer

Type

Pin Name

Description

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

15

16

17

18

23

24

25

26

16

18

19

20

25

26

27

29

32

35

36

37

42

43

44

1

I/O

ST

RC0 can also be the Timer1 oscillator output or a

Timer1 clock input.

RC1 can also be the Timer1 oscillator input or

Capture2 input/Compare2 output/PWM2 output.

RC2/CCP1

RC2 can also be the Capture1 input/Compare1

output/PWM1 output.

RC3/SCK/SCL

RC4/SDI/SDA

RC5/SDO

RC3 can also be the synchronous serial clock input/

2

output for both SPI and I C modes.

RC4 can also be the SPI Data In (SPI mode) or

2

data I/O (I C mode).

RC5 can also be the SPI Data Out

(SPI mode).

RC6/TX/CK

RC7/RX/DT

RC6 can also be the USART Asynchronous

Transmit or Synchronous Clock.

RC7 can also be the USART Asynchronous Receive

or Synchronous Data.

PORTD is a bi-directional I/O port or parallel slave port

when interfacing to a microprocessor bus.

(3)

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

19

20

21

22

27

28

29

30

21

22

23

24

30

31

32

33

38

39

40

41

2

I/O

ST/TTL

(3)

3

4

5

PORTE is a bi-directional I/O port.

(3)

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

AVss

8

9

25

26

27

29

I/O

P

ST/TTL

RE0 can also be read control for the parallel slave

port, or analog input5.

10

11

13

RE1 can also be write control for the parallel slave

port, or analog input6.

10

RE2 can also be select control for the parallel slave

port, or analog input7.

Ground reference for A/D converter

Positive supply for A/D converter

12

AVDD

VSS

VDD

NC

11

31

32

—

12

34

35

28

6

P

—

Ground reference for logic and I/O pins.

Positive supply for logic and I/O pins.

7

1,17,28, 12,13,

40 33,34

These pins are not internally connected. These pins

should be left unconnected.

Legend: I = input

O = output

I/O = input/output

P = power

— = Not used

TTL = TTL input

ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured for the multiplexed function.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 9

PIC16C77X

NOTES:

DS30275A-page 10

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2

Data Memory Organization

2.0

MEMORY ORGANIZATION

There are two memory blocks in each of these

PICmicro^®microcontrollers. Each block (Pro-

gram Memory and Data Memory) has its own bus

so that concurrent access can occur.

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 and RP0 are the

bank select bits.

Additional information on device memory may be found

RP1 RP0

(STATUS<6:5>)

in the PICmicro

(DS33023).

Mid-Range Reference Manual,

= 00 → Bank0

= 01 → Bank1

= 10 → Bank2

= 11 → Bank3

2.1

Program Memory Organization

The PIC16C77X PICmicros have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. Each device has 4K x 14 words of pro-

gram memory. Accessing a location above the physi-

cally implemented address will cause a wraparound.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain special

function registers. Some “high use” special function

registers from one bank may be mirrored in another

bank for code reduction and quicker access.

The reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK

2.2.1

GENERAL PURPOSE REGISTER FILE

The register file can be accessed either directly, or indi-

rectly through the File Select Register FSR.

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

0000h

Interrupt Vector

Page 0

0004h

0005h

On-chip

Program

Memory

07FFh

0800h

Page 1

0FFFh

1000h

3FFFh

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 11

PIC16C77X

FIGURE 2-2: REGISTER FILE MAP

File

Address

File

Address

File

Address

File

Address

Indirect addr.^(*)

TMR0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

Indirect addr.^(*)

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

Indirect addr.^(*)

TMR0

Indirect addr.^(*)

OPTION_REG

PCL

80h

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

OPTION_REG

PCL

STATUS

FSR

STATUS

FSR

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

PORTB

TRISB

TRISC

TRISD

TRISE

(1)

PORTD

PORTE

(1)

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PCLATH

INTCON

PIR2

PIE2

TMR1L

TMR1H

T1CON

TMR2

PCON

SSPCON2

PR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

SSPADD

SSPSTAT

RCSTA

TXREG

TXSTA

SPBRG

RCREG

REFCON

LVDCON

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON0

ADRESL

ADCON1

A0h

1A0h

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

80 Bytes

96 Bytes

1EFh

1F0h

EFh

F0h

6Fh

70h

accesses

70h - 7Fh

accesses

70h - 7Fh

accesses

70h-7Fh

7Fh

FFh

17Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

(1) Not implemented on PIC16C773.

Unimplemented data memory locations, read as ’0’.

Not a physical register.

*

DS30275A-page 12

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2.2

SPECIAL FUNCTION REGISTERS

The special function registers can be classified into two

sets; core (CPU) and peripheral. Those registers asso-

ciated with the core functions are described in detail in

this section. Those related to the operation of the

peripheral features are described in detail in that

peripheral feature section.

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Table 2-1.

TABLE 2-1

Address Name

Bank 0

PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY

Value on: Value on all

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

other resets

(2)

00h⁽⁴⁾

01h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

0000 0000

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--0x 0000

xxxx 11xx

xxxx xxxx

---- -000

0000 0000

uuuu uuuu

0000 0000

000q quuu

uuuu uuuu

--0u 0000

uuuu 11uu

uuuu uuuu

---- -000

TMR0

PCL

02h⁽⁴⁾

03h⁽⁴⁾

04h⁽⁴⁾

05h

Program Counter's (PC) Least Significant Byte

STATUS

FSR

IRP

Indirect data memory address pointer

PORTA5⁽⁵⁾PORTA Data Latch when written: PORTA<4:0> pins when read

RP1

RP0

TO

PD

Z

DC

C

PORTA

PORTB

PORTC

PORTD

PORTE

—

06h

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

PORTD Data Latch when written: PORTD pins when read

07h

08h⁽⁵⁾

09h⁽⁵⁾

—

RE2

RE1

RE0

0Ah^(1,4)PCLATH

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0000 000x

0000 0000

0--- 0--0

---0 0000

0Bh⁽⁴⁾

0Ch

0Dh

0Eh

0Fh

10h

INTCON

PIR1

GIE

PEIE

ADIF

—

T0IE

RCIF

—

INTE

TXIF

–

RBIE

SSPIF

BCLIF

T0IF

CCP1IF

—

INTF

TMR2IF

—

RBIF

0000 000u

0000 0000

0--- 0--0

PSPIF⁽³⁾

LVDIF

TMR1IF

CCP2IF

PIR2

TMR1L

Holding register for the Least Significant Byte of the 16-bit TMR1 register

Holding register for the Most Significant Byte of the 16-bit TMR1 register

xxxx xxxx

--00 0000

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

uuuu uuuu

--uu uuuu

0000 0000

-000 0000

uuuu uuuu

0000 0000

uuuu uuuu

--00 0000

0000 000x

0000 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 0000

TMR1H

T1CON

TMR2

—

T1CKPS1

T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

11h

Timer2 module’s register

TOUTPS3 TOUTPS2

12h

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

—

TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

13h

Synchronous Serial Port Receive Buffer/Transmit Register

14h

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

15h

Capture/Compare/PWM Register1 (LSB)

Capture/Compare/PWM Register1 (MSB)

16h

17h

—

CCP1X

SREN

CCP1Y

CREN

CCP1M3 CCP1M2 CCP1M1 CCP1M0

ADDEN FERR OERR RX9D

18h

SPEN

RX9

19h

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON0

USART Transmit Data Register

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Legend:

USART Receive Data Register

Capture/Compare/PWM Register2 (LSB)

Capture/Compare/PWM Register2 (MSB)

—

CCP2X

A/D High Byte Result Register

ADCS1 ADCS0 CHS2

CCP2Y

CCP2M3 CCP2M2 CCP2M1 CCP2M0

CHS1

CHS0

GO/DONE

CHS3

ADON

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to

the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

4: These registers can be addressed from any bank.

5: These registers/bits are not implemented on the 28-pin devices read as '0'.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 13

PIC16C77X

TABLE 2-1

Address Name

Bank 1

PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Value on: Value on all

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

other resets

(2)

80h⁽⁴⁾

81h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

1111 1111

0000 0000

0001 1xxx

xxxx xxxx

--11 1111

1111 1111

0000 -111

---0 0000

0000 000x

0000 0000

0--- 0--0

---- --qq

—

0000 0000

1111 1111

0000 0000

000q quuu

uuuu uuuu

--11 1111

1111 1111

0000 -111

---0 0000

0000 000u

0000 0000

0--- 0--0

---- --uu

—

OPTION_REG RBPU

INTEDG

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO

Indirect data memory address pointer

bit5⁽⁵⁾

T0CS

T0SE

PSA

PS2

PS1

PS0

82h⁽⁴⁾

83h⁽⁴⁾

84h⁽⁴⁾

85h

PCL

STATUS

FSR

PD

Z

DC

C

TRISA

TRISB

TRISC

TRISD

TRISE

—

PORTA Data Direction Register

86h

PORTB Data Direction Register

PORTC Data Direction Register

PORTD Data Direction Register

87h

88h⁽⁵⁾

89h⁽⁵⁾

IBF

—

OBF

—

IBOV

—

PSPMODE

—

PORTE Data Direction Bits

8Ah^(1,4)PCLATH

Write Buffer for the upper 5 bits of the Program Counter

8Bh⁽⁴⁾

8Ch

8Dh

8Eh

8Fh

90h

INTCON

PIE1

GIE

PEIE

ADIE

—

T0IE

RCIE

—

INTE

TXIE

—

RBIE

SSPIE

BCLIE

—

T0IF

CCP1IE

—

INTF

TMR2IE

—

RBIF

TMR1IE

CCP2IE

BOR

PSPIE⁽³⁾

LVDIE

—

PIE2

PCON

—

POR

Unimplemented

—

91h

SSPCON2

PR2

GCEN

AKSTAT

AKDT

AKEN

RCEN

PEN

R/W

RSEN

UA

SEN

BF

0000 0000

1111 1111

0000 0000

—

0000 0000

1111 1111

0000 0000

—

92h

Timer2 Period Register

93h

SSPADD

SSPSTAT

—

Synchronous Serial Port (I²C mode) Address Register

94h

SMP

CKE

D/A

P

S

95h

Unimplemented

CSRC

96h

—

97h

—

98h

TXSTA

SPBRG

—

TX9

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010

0000 0000

—

0000 -010

0000 0000

—

99h

Baud Rate Generator Register

Unimplemented

9Ah

9Bh

9Ch

9Ah

9Eh

9Fh

Legend:

REFCON

LVDCON

—

VRHEN

—

VRLEN

—

VRHOEN

BGST

VRLOEN

LVDEN

—

0000 ----

--00 0101

—

0000 ----

--00 0101

—

LV3

LV2

LV1

LV0

Unimplemented

A/D Low Byte Result Register

ADFM VCFG2 VCFG1

ADRESL

ADCON1

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to

the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

4: These registers can be addressed from any bank.

5: These registers/bits are not implemented on the 28-pin devices read as '0'.

DS30275A-page 14

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 2-1

Address Name

Bank 2

PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Value on: Value on all

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

other resets

(2)

100h⁽⁴⁾

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 module’s register

0000 0000

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

000q quuu

uuuu uuuu

101h

TMR0

PCL

102h⁽⁴⁾

103h⁽⁴⁾

Program Counter's (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

104h⁽⁴⁾

105h

106h

107h

108h

109h

Indirect data memory address pointer

Unimplemented

—

PORTB

—

PORTB Data Latch when written: PORTB pins when read

xxxx 11xx

uuuu 11uu

Unimplemented

—

10Ah^(1,4)

10Bh⁽⁴⁾

PCLATH

INTCON

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE T0IF INTF RBIF

---0 0000

GIE

PEIE

T0IE

0000 000x

0000 000u

10Ch-

10Fh

—

Unimplemented

—

Bank 3

180h⁽⁴⁾

181h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000

1111 1111

0000 0000

0001 1xxx

0000 0000

1111 1111

0000 0000

000q quuu

OPTION_REG RBPU

INTEDG

Program Counter's (PC) Least Significant Byte

IRP RP1 RP0 TO

T0CS

T0SE

PSA

PS2

PS1

PS0

182h⁽⁴⁾

183h⁽⁴⁾

PCL

STATUS

PD

Z

DC

C

184h⁽⁴⁾

185h

186h

187h

188h

189h

FSR

—

Indirect data memory address pointer

Unimplemented

xxxx xxxx

uuuu uuuu

—

1111 1111

—

1111 1111

—

TRISB

—

PORTB Data Direction Register

Unimplemented

—

Unimplemented

—

Unimplemented

—

18Ah^(1,4)

18Bh⁽⁴⁾

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE T0IF INTF RBIF

PCLATH

—

---0 0000

INTCON

—

GIE

PEIE

T0IE

0000 000x

0000 000u

18Ch-

18Fh

Unimplemented

—

Legend:

x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to

the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

4: These registers can be addressed from any bank.

5: These registers/bits are not implemented on the 28-pin devices read as '0'.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 15

PIC16C77X

2.2.2.1

STATUS REGISTER

For example, CLRF STATUSwill clear the upper-three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

The STATUS register, shown in Figure 2-3, contains

the arithmetic status of the ALU, the RESET status and

the bank select bits for data memory.

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register because these instructions do not

affect the Z, C or DC bits from the STATUS register. For

other instructions, not affecting any status bits, see the

"Instruction Set Summary."

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as a borrow and

digit borrow bit, respectively, in subtraction.

See the SUBLWand SUBWFinstructions for

examples.

FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

bit7

bit0

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11= Bank 3 (180h - 1FFh)

10= Bank 2 (100h - 17Fh)

01= Bank 1 (80h - FFh)

00= Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

DS30275A-page 16

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2.2.2

OPTION_REG REGISTER

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to

the Watchdog Timer.

The OPTION_REG register is a readable and writable

register which contains various control bits to configure

the TMR0 prescaler/WDT postscaler (single assign-

able register known also as the prescaler), the External

INT Interrupt, TMR0, and the weak pull-ups on PORTB.

FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h, 181h)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6:

bit 5:

bit 4:

bit 3:

INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 17

PIC16C77X

2.2.2.3

INTCON REGISTER

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

The INTCON Register is a readable and writable regis-

ter which contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

R

= Readable bit

W = Writable bit

bit7

bit0

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

IINTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 register did not overflow

INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

DS30275A-page 18

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2.2.4

PIE1 REGISTER

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

This register contains the individual enable bits for the

peripheral interrupts.

FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

TMR2IE TMR1IE

bit0

R/W-0

(1)

PSPIE

CCP1IE

R

= Readable bit

W = Writable bit

bit7

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

PSPIE⁽¹⁾: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

bit 1:

bit 0:

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: PSPIE is reserved on the 28-pin devices, always maintain this bit clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 19

PIC16C77X

2.2.2.5

PIR1 REGISTER

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

This register contains the individual flag bits for the

peripheral interrupts.

FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

TMR2IF TMR1IF

bit0

R/W-0

(1)

PSPIF

RCIF

TXIF

CCP1IF

R

= Readable bit

W = Writable bit

bit7

U

= Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit 7:

PSPIF⁽¹⁾: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occurred

bit 6:

bit 5:

bit 4:

bit 3:

bit 2:

ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG)

0 = The USART receive buffer is empty

TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG)

0 = The USART transmit buffer is full

SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode

bit 1:

bit 0:

TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 register did not overflow

Note 1: PSPIF is reserved on the 28-pin devices, always maintain this bit clear.

DS30275A-page 20

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2.2.6

PIE2 REGISTER

This register contains the individual enable bits for the

CCP2, SSP bus collision, and low voltage detect inter-

rupts.

FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh)

R/W-0

LVDIE

U-0

R/W-0

U-0

R/W-0

—

BCLIE

—

CCP2IE

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7

LVDIE: Low-voltage Detect Interrupt Enable bit

1 = LVD Interrupt is enabled

0 = LVD Interrupt is disabled

bit 6-4: Unimplemented: Read as ’0’

bit 3:

BCLIE: Bus Collision Interrupt Enable bit

1 = Bus Collision interrupt is enabled

0 = Bus Collision interrupt is disabled

bit 2-1: Unimplemented: Read as ’0’

bit 0:

CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 21

PIC16C77X

.

2.2.2.7

PIR2 REGISTER

Note: Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

This register contains the CCP2, SSP Bus Collision,

and Low-voltage detect interrupt flag bits.

FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)

R/W-0

LVDIF

U-0

R/W-0

U-0

R/W-0

—

BCLIF

—

CCP2IF

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7:

LVDIF: Low-voltage Detect Interrupt Flag bit

1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)

0 = The supply voltage is greater than the specified LVD voltage

bit 6-4: Unimplemented: Read as ’0’

bit 3:

BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred while the SSP module configured in I²C Master was transmitting

(must be cleared in software)

0 = No bus collision occurred

bit 2-1: Unimplemented: Read as ’0’

bit 0:

CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused

DS30275A-page 22

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2.2.2.8

PCON REGISTER

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked

on subsequent resets to see if BOR is

clear, indicating a brown-out has occurred.

The BOR status bit is a don’t care and is

not necessarily predictable if the brown-out

circuit is disabled (by clearing the BODEN

bit in the Configuration word).

The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset

(POR) to an external MCLR Reset or WDT Reset.

Those devices with brown-out detection circuitry con-

tain an additional bit to differentiate a Brown-out Reset

condition from a Power-on Reset condition.

FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)

U-0

R/W-0

R/W-1

—

POR

BOR

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7-2: Unimplemented: Read as ’0’

bit 1:

POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0:

BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 23

PIC16C77X

2.3

PCL and PCLATH

2.4

Program Memory Paging

The program counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 13 bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<12:8>

bits and is not directly readable or writable. All updates

to the PCH register go through the PCLATH register.

PIC16C77X devices are capable of addressing a con-

tinuous 8K word block of program memory. The CALL

and GOTOinstructions provide only 11 bits of address

to allow branching within any 2K program memory

page. When doing a CALL or GOTO instruction the

upper

2 bits of the address are provided by

PCLATH<4:3>. When doing a CALL or GOTO instruc-

tion, the user must ensure that the page select bits are

programmed so that the desired program memory

page is addressed. If a return from a CALLinstruction

(or interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<4:3> bits are not required for the return

instructions (which POPs the address from the stack).

2.3.1

STACK

The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Midrange devices have an 8 level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or

POPed.

After the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

DS30275A-page 24

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The INDF register is not a physical register. Address-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer). This is indirect addressing.

EXAMPLE 2-1: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x20 ;initialize pointer

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

movwf FSR

clrf

incf

;

to RAM

INDF ;clear INDF register

FSR ;inc pointer

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-1.

goto

NEXT ;NO, clear next

CONTINUE

:

;YES, continue

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 2-11.

FIGURE 2-11: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

from opcode

7

RP1:RP0

6

0

IRP

FSR register

bank select

location select

bank select

location select

00

01

80h

10

100h

11

00h

180h

Data

Memory(1)

7Fh

FFh

17Fh

1FFh

Bank 0

Bank 1 Bank 2

Bank 3

Note 1: For register file map detail see Figure 2-2.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 25

PIC16C77X

NOTES:

DS30275A-page 26

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 3-1: BLOCK DIAGRAM OF

3.0

I/O PORTS

RA3:RA2 PINS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Data

bus

D

Q

VDD

P

WR

Port

Additional information on I/O ports may be found in the

PICmicro™

(DS33023).

Mid-Range

Reference

Manual,

CK

Data Latch

3.1

PORTA and the TRISA Register

I/O pin⁽¹⁾

N

D

Q

PORTA is a 6-bit wide bi-directional port for the 40/44

pin devices and is 5-bits wide for the 28-pin devices.

PORTA<5> is not on the 28-pin devices. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (=1) will make the corresponding PORTA pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISA bit (=0) will

make the corresponding PORTA pin an output, i.e., put

the contents of the output latch on the selected pin.

WR

TRIS

VSS

Analog

Q

CK

input

mode

TRIS Latch

TTL

input

buffer

RD TRIS

Q

D

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore a write to a port implies that the port pins are

read, this value is modified, and then written to the port

data latch.

EN

RD PORT

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and full

CMOS output drivers.

To A/D Converter

Other PORTA pins are multiplexed with analog inputs

and analog VREF inputs and precision on-board refer-

ences (VRL/VRH). The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register1).

VRH, VRL

Note: On a Power-on Reset, these pins are con-

figured as analog inputs and read as '0'.

VRHOEN, VRLOEN

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

Sense input for

VRO+, VRO- amplifier

EXAMPLE 3-1: INITIALIZING PORTA

BCF

STATUS, RP0

;

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

Note 1: I/O pins have protection diodes to VDD and

VSS.

BSF

STATUS, RP0 ; Select Bank 1

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ’0’.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 27

PIC16C77X

FIGURE 3-2: BLOCK DIAGRAM OF

RA1:RA0 AND RA5 PINS

FIGURE 3-3: BLOCK DIAGRAM OF

RA4/T0CKI PIN

Data

bus

Data

bus

D

Q

D

Q

WR

PORT

VDD

P

CK

WR

Port

I/O pin⁽¹⁾

N

CK

Data Latch

D

Q

VSS

Data Latch

WR

TRIS

I/O pin⁽¹⁾

N

D

Q

Schmitt

Trigger

input

Q

CK

WR

TRIS

TRIS Latch

buffer

VSS

Analog

Q

CK

input

mode

RD TRIS

TRIS Latch

Q

D

TTL

input

buffer

RD TRIS

EN

RD PORT

Q

D

TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

EN

RD PORT

To A/D Converter

Note 1: I/O pins have protection diodes to VDD and

VSS.

TABLE 3-1

Name

PORTA FUNCTIONS

Bit#

Buffer Function

RA0/AN0

bit0

bit1

bit2

TTL

Input/output or analog input0

RA1/AN1

Input/output or analog input1

RA2/AN2/VREF-/VRL

Input/output or analog input2 or VREF- input or internal reference

voltage low

RA3/AN3/VREF+/VRH

RA4/T0CKI

bit3

bit4

bit5

TTL

ST

Input/output or analog input or VREF+ input or output of internal

reference voltage high

Input/output or external clock input for Timer0

Output is open drain type

RA5/AN4⁽¹⁾

TTL

Input/output or analog input

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: RA5 is reserved on the 28-pin devices, maintain this bit clear.

TABLE 3-2

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

05h

85h

9Fh

PORTA

—

RA5

RA4

RA3

RA2

RA1

RA0

--0x 0000 --0u 0000

--11 1111 --11 1111

(1)

TRISA

PORTA Data Direction Register

ADCON1 ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by PORTA.

Note 1: PORTA<5>, TRISA<5> are reserved on the 28-pin devices, maintain these bits clear.

DS30275A-page 28

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The RB1 pin is multiplexed with the SSP module slave

select (RB1/SS).

3.2

PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (=1) will make the corresponding PORTB pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISB bit (=0) will

make the corresponding PORTB pin an output, i.e., put

the contents of the output latch on the selected pin.

FIGURE 3-5: BLOCK DIAGRAM OF RB1/SS

VDD

RBPU⁽²⁾

weak

pull-up

P

Data Latch

Data bus

D

Q

EXAMPLE 3-1: INITIALIZING PORTB

I/O

pin⁽¹⁾

WR Port

CK

TRIS Latch

BCF

STATUS, RP0

;

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

D

Q

TTL

Input

Buffer

WR TRIS

BSF

STATUS, RP0 ; Select Bank 1

CK

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

RD TRIS

RD Port

Q

D

EN

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION_REG<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are dis-

abled on a Power-on Reset.

SS input

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

The RB0 pin is multiplexed with the external interrupt

(RB0/INT).

The RB2 pin is multiplexed with analog channel 8

(RB2/AN8).

FIGURE 3-4: BLOCK DIAGRAM OF RB0 PIN

VDD

RBPU⁽²⁾

FIGURE 3-6: BLOCK DIAGRAM OF

weak

P

pull-up

RB2/AN8 PIN

Data Latch

Data bus

VDD

D

Q

RBPU⁽²⁾

weak

P

I/O

pin⁽¹⁾

pull-up

WR Port

CK

TRIS Latch

Data Latch

Data bus

D

Q

D

Q

I/O

pin⁽¹⁾

TTL

Input

Buffer

WR Port

CK

TRIS Latch

WR TRIS

CK

D

Q

Analog

input mode

WR TRIS

CK

RD TRIS

RD Port

TTL

Input

Buffer

Q

D

EN

RD TRIS

Q

D

RB0/INT

EN

RD Port

Schmitt Trigger

Buffer

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

To A/D converter

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

RD Port

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 29

PIC16C77X

The RB3 pin is multiplexed with analog channel 9 and

the low voltage detect input (RB3/AN9/LVDIN)

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e. any RB7:RB4 pin con-

figured as an output is excluded from the interrupt on

change comparison). The input pins (of RB7:RB4) are

compared with the old value latched on the last read of

PORTB. The “mismatch” outputs of RB7:RB4 are

OR’ed together to generate the RB Port Change Inter-

rupt with flag bit RBIF (INTCON<0>).

FIGURE 3-7: BLOCK DIAGRAM OF

RB3/AN9/LVDIN PIN

VDD

RBPU⁽²⁾

weak

pull-up

P

Data Latch

Data bus

D

Q

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the inter-

rupt in the following manner:

I/O

pin⁽¹⁾

WR Port

CK

TRIS Latch

a) Any read or write of PORTB. This will end the

mismatch condition.

D

Q

Analog

WR TRIS

CK

input mode

or LVD input

mode

b) Clear flag bit RBIF.

TTL

Input

Buffer

A mismatch condition will continue to set flag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow flag bit RBIF to be cleared.

RD TRIS

Q

D

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

EN

RD Port

To A/D converter and LVD reference input

RD Port

FIGURE 3-8: BLOCK DIAGRAM OF

Note 1: I/O pins have diode protection to VDD and VSS.

RB7:RB4 PINS

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

VDD

RBPU⁽²⁾

weak

pull-up

P

Data Latch

Data bus

D

Q

I/O

pin⁽¹⁾

WR Port

CK

TRIS Latch

D

Q

WR TRIS

TTL

Input

Buffer

CK

ST

Buffer

RD TRIS

RD Port

Latch

Q

D

EN

Q1

Set RBIF

D

From other

RB7:RB4 pins

RD Port

Q3

EN

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

DS30275A-page 30

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 3-3

PORTB FUNCTIONS

Name

Bit#

Buffer

Function

RB0/INT

bit0

TTL/ST⁽¹⁾Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

TTL/ST⁽³⁾

RB1/SS

RB2/AN8

RB3/AN9/LVDIN

RB4

bit1

bit2

bit3

bit4

bit5

bit6

bit7

Input/output pin or SSP slave select. Internal software programmable

weak pull-up.

TTL

Input/output pin or analog input8. Internal software programmable

weak pull-up.

Input/output pin or analog input9 or Low-voltage detect input. Internal

software programmable weak pull-up.

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

RB5

Input/output pin (with interrupt on change). Internal software

programmable weak pull-up.

TTL/ST⁽²⁾Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming clock.

TTL/ST⁽²⁾Input/output pin (with interrupt on change). Internal software

programmable weak pull-up. Serial programming data.

RB6

RB7

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

3: This buffer is a Schmitt Trigger input when used as the SSP slave select.

TABLE 3-4

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h, 106h PORTB

86h, 186h TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx 11xx uuuu 11uu

1111 1111 1111 1111

PORTB Data Direction Register

T0SE

81h, 181h OPTION_REG RBPU INTEDG T0CS

9Fh ADCON1

Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.

PSA

PS2

PS1

PS0

ADFM VCFG2 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 31

PIC16C77X

3.3

PORTC and the TRISC Register

FIGURE 3-9: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT

OVERRIDE)

PORTC is an 8-bit wide bi-directional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (=1) will make the corresponding PORTC pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISC bit (=0) will

make the corresponding PORTC pin an output, i.e., put

the contents of the output latch on the selected pin.

PORT/PERIPHERAL Select⁽²⁾

Peripheral Data Out

VDD

0

Data bus

D

Q

P

WR

PORT

1

CK

PORTC is multiplexed with several peripheral functions

(Table 3-5). PORTC pins have Schmitt Trigger input

buffers.

Data Latch

I/O

D

Q

pin⁽¹⁾

WR

TRIS

When enabling peripheral functions, care should be

taken in defining TRIS bits for each PORTC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-mod-

ify-write instructions (BSF, BCF, XORWF) with TRISC

as destination should be avoided. The user should refer

to the corresponding peripheral section for the correct

TRIS bit settings.

CK

N

TRIS Latch

VSS

Schmitt

Trigger

RD TRIS

Peripheral

OE⁽³⁾

Q

D

EN

RD

PORT

Peripheral input

EXAMPLE 3-1: INITIALIZING PORTC

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port

data and peripheral output.

BCF

STATUS, RP0 ; Select Bank 0

CLRF

PORTC ; Initialize PORTC by

; clearing output

; data latches

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

BSF

STATUS, RP0 ; Select Bank 1

MOVLW 0xCF

; Value used to

; initialize data

; direction

MOVWF TRISC

; Set RC<3:0> as inputs

; RC<5:4> as outputs

; RC<7:6> as inputs

DS30275A-page 32

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 3-5

Name

PORTC FUNCTIONS

Bit# Buffer Type

Function

bit0

bit1

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

ST

Input/output port pin or Timer1 oscillator output/Timer1 clock input

Input/output port pin or Timer1 oscillator input or Capture2

input/Compare2 output/PWM2 output

RC2/CCP1

bit2

bit3

ST

Input/output port pin or Capture1 input/Compare1 output/PWM1

output

RC3 can also be the synchronous serial clock for both SPI and I²C

modes.

RC3/SCK/SCL

RC4 can also be the SPI Data In (SPI mode) or data I/O (I²C mode).

Input/output port pin or Synchronous Serial Port data output

RC4/SDI/SDA

bit4

ST

RC5/SDO

bit5

bit6

ST

RC6/TX/CK

Input/output port pin or USART Asynchronous transmit or

Synchronous clock

RC7/RX/DT

bit7

ST

Input/output port pin or USART Asynchronous receive or

Synchronous data

Legend: ST = Schmitt Trigger input

TABLE 3-6

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

07h

87h

PORTC

TRISC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

PORTC Data Direction Register

Legend: x= unknown, u= unchanged.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 33

PIC16C77X

3.4

PORTD and TRISD Registers

FIGURE 3-10: PORTD BLOCK DIAGRAM (IN

I/O PORT MODE)

This section is applicable to the 40/44-pin devices only.

Data

bus

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is individually configurable as an input or

output.

D

Q

WR

PORT

I/O pin⁽¹⁾

CK

Data Latch

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mode, the input buffers

are TTL.

D

Q

WR

TRIS

Schmitt

Trigger

input

CK

TRIS Latch

buffer

RD TRIS

Q

D

EN

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 3-7

Name

PORTD FUNCTIONS

Bit#

Buffer Type

Function

RD0/PSP0

RD1/PSP1

RD2/PSP2

RD3/PSP3

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

ST/TTL⁽¹⁾

Input/output port pin or parallel slave port bit0

Input/output port pin or parallel slave port bit1

Input/output port pin or parallel slave port bit2

Input/output port pin or parallel slave port bit3

Input/output port pin or parallel slave port bit4

Input/output port pin or parallel slave port bit5

Input/output port pin or parallel slave port bit6

Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.

TABLE 3-8

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

88h

89h

PORTD RD7 RD6 RD5

RD4

RD3

RD2

RD1

RD0

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

0000 -111 0000 -111

TRISD PORTD Data Direction Register

TRISE IBF OBF IBOV PSPMODE

—

PORTE Data Direction Bits

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.

DS30275A-page 34

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

3.5

PORTE and TRISE Register

FIGURE 3-11: PORTE BLOCK DIAGRAM (IN

I/O PORT MODE)

This section is applicable to the 40/44-pin devices only.

Data

bus

PORTE has three pins RE0/RD/AN5, RE1/WR/AN6

and RE2/CS/AN7, which are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers.

D

Q

WR

PORT

I/O pin⁽¹⁾

CK

Data Latch

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

inputs). Ensure ADCON1 is configured for digital I/O. In

this mode the input buffers are TTL.

D

Q

WR

TRIS

Schmitt

Trigger

input

CK

TRIS Latch

buffer

Figure 3-12 shows the TRISE register, which also con-

trols the parallel slave port operation.

RD TRIS

PORTE pins are multiplexed with analog inputs. When

selected as an analog input, these pins will read as ’0’s.

Q

D

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

EN

RD PORT

Note 1: I/O pins have protection diodes to VDD and VSS.

Note: On a Power-on Reset these pins are con-

figured as analog inputs.

FIGURE 3-12: TRISE REGISTER (ADDRESS 89h)

R-0

IBF

R-0

R/W-0

U-0

R/W-1

OBF

IBOV PSPMODE

—

bit2

bit1

bit0

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

bit0

- n = Value at POR reset

bit 7 :

bit 6:

bit 5:

bit 4:

IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software)

0 = No overflow occurred

PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode

0 = General purpose I/O mode

bit 3:

bit 2:

Unimplemented: Read as '0'

PORTE Data Direction Bits

Bit2: Direction Control bit for pin RE2/CS/AN7

1 = Input

0 = Output

bit 1:

bit 0:

Bit1: Direction Control bit for pin RE1/WR/AN6

1 = Input

0 = Output

Bit0: Direction Control bit for pin RE0/RD/AN5

1 = Input

0 = Output

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 35

PIC16C77X

TABLE 3-9

PORTE FUNCTIONS

Name

Bit#

Buffer Type

Function

RE0/RD/AN5

bit0

ST/TTL⁽¹⁾

Input/output port pin or read control input in parallel slave port mode or

analog input:

RD

1 = Not a read operation

0 = Read operation. Reads PORTD register (if chip selected)

RE1/WR/AN6

RE2/CS/AN7

bit1

bit2

ST/TTL⁽¹⁾

Input/output port pin or write control input in parallel slave port mode or

analog input:

WR

1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected)

Input/output port pin or chip select control input in parallel slave port

mode or analog input:

CS

1 = Device is not selected

0 = Device is selected

Legend: ST = Schmitt Trigger input TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

TABLE 3-10

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on:

POR,

BOR

Value on all

other resets

Addr Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

09h

89h

9Fh

PORTE

—

RE2

RE1

RE0

---- -xxx ---- -uuu

0000 -111 0000 -111

TRISE

IBF

OBF

IBOV

PSPMODE

VCFG0

PORTE Data Direction Bits

ADCON1 ADFM VCFG2 VCFG1

PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.

DS30275A-page 36

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

3.6

Parallel Slave Port

FIGURE 3-13: PORTD AND PORTE BLOCK

DIAGRAM (PARALLEL SLAVE

PORT)

The Parallel Slave Port is implemented on the

40/44-pin devices only.

PORTD operates as an 8-bit wide Parallel Slave Port,

or microprocessor port when control bit PSPMODE

(TRISE<4>) is set. In slave mode it is asynchronously

readable and writable by the external world through RD

control input pin RE0/RD and WR control input pin

RE1/WR.

Data bus

D

Q

WR

PORT

RDx

CK

TTL

Q

D

It can directly interface to an 8-bit microprocessor data

bus. The external microprocessor can read or write the

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set). The configuration

bits, PCFG3:PCFG0 (ADCON1<3:0>) must be config-

ured to make pins RE2:RE0 as digital I/O.

RD

PORT

EN

One bit of PORTD

Set interrupt flag

PSPIF (PIR1<7>)

A write to the PSP occurs when both the CS and WR

lines are first detected low. A read from the PSP occurs

when both the CS and RD lines are first detected low.

Read

RD

CS

WR

TTL

Chip Select

TTL

Write

Note: I/O pin has protection diodes to VDD and VSS.

FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 37

PIC16C77X

FIGURE 3-15: PARALLEL SLAVE PORT READ WAVEFORMS

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

CS

WR

RD

PORTD<7:0>

IBF

OBF

PSPIF

TABLE 3-11

REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on:

POR,

BOR

Value on all

other resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

09h

89h

0Ch

8Ch

9Fh

PORTD

PORTE

TRISE

PIR1

Port data latch when written: Port pins when read

xxxx xxxx uuuu uuuu

---- -xxx ---- -uuu

0000 -111 0000 -111

—

RE2

RE1

RE0

IBF

OBF

IBOV PSPMODE

PORTE Data Direction Bits

PSPIF ADIF

PSPIE ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000

PIE1

ADCON1 ADFM VCFG2 VCFG1

VCFG0

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.

DS30275A-page 38

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Additional information on external clock requirements

is available in the PICmicro™ Mid-Range Reference

Manual, (DS33023).

4.0

TIMER0 MODULE

The Timer0 module timer/counter has the following fea-

tures:

4.2

Prescaler

• 8-bit timer/counter

• Readable and writable

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 4-2). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

available which is mutually exclusively shared between

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

• Internal or external clock select

• Edge select for external clock

• 8-bit software programmable prescaler

• Interrupt on overflow from FFh to 00h

Figure 4-1 is a simplified block diagram of the Timer0

module.

Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

The prescaler is not readable or writable.

The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and prescale ratio.

4.1

Timer0 Operation

Timer0 can operate as a timer or as a counter.

Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0

module, prescale values of 1:2, 1:4, ..., 1:256 are

selectable.

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In timer mode, the Timer0 mod-

ule will increment every instruction cycle (without pres-

caler). If the TMR0 register is written, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Setting bit PSA will assign the prescaler to the Watch-

dog Timer (WDT). When the prescaler is assigned to

the WDT, prescale values of 1:1, 1:2, ..., 1:128 are

selectable.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In counter mode, Timer0 will

increment either on every rising or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the Timer0 Source Edge Select bit T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in below.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF

1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the WDT.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler

count, but will not change the prescaler

assignment.

When an external clock input is used for Timer0, it must

meet certain requirements. The requirements ensure

the external clock can be synchronized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

FIGURE 4-1: TIMER0 BLOCK DIAGRAM

Data bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

clocks

TMR0

Programmable

Prescaler

RA4/T0CKI

PSout

(2 cycle delay)

T0SE

3

Set interrupt

flag bit T0IF

on overflow

PS2, PS1, PS0

PSA

T0CS

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 39

PIC16C77X

4.2.1

SWITCHING PRESCALER ASSIGNMENT

4.3

Timer0 Interrupt

The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the fly” during program

execution.

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the Timer0 module interrupt ser-

vice routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP since the timer is shut off during SLEEP.

Note: To avoid an unintended device RESET, a

specific instruction sequence (shown in the

PICmicro™ Mid-Range Reference Man-

ual, DS33023) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This sequence must

be followed even if the WDT is disabled.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

Data Bus

8

CLKOUT (=Fosc/4)

M

U

X

1

0

1

M

U

X

RA4/T0CKI

SYNC

2

Cycles

TMR0 reg

T0SE

T0CS

Set flag bit T0IF

on Overflow

PSA

0

1

8-bit Prescaler

M

U

X

Watchdog

Timer

8

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

M U X

PSA

WDT

Time-out

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

TABLE 4-1

REGISTERS ASSOCIATED WITH TIMER0

Value on:

POR,

BOR

Value on all

other resets

Address

Name

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h,101h

TMR0

Timer0 module’s register

GIE PEIE T0IE INTE

xxxx xxxx uuuu uuuu

RBIF 0000 000x 0000 000u

0Bh,8Bh,

10Bh,18Bh

INTCON

RBIE

PSA

T0IF

PS2

INTF

PS1

81h,181h

85h

OPTION_REG RBPU INTEDG T0CS T0SE

TRISA

PS0

1111 1111 1111 1111

--11 1111 --11 1111

—

PORTA Data Direction Register

Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.

DS30275A-page 40

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

5.1

Timer1 Operation

5.0

TIMER1 MODULE

The Timer1 module timer/counter has the following fea-

tures:

Timer1 can operate in one of these modes:

• As a timer

• 16-bit timer/counter

(Two 8-bit registers; TMR1H and TMR1L)

• As a synchronous counter

• As an asynchronous counter

• Readable and writable (Both registers)

• Internal or external clock select

The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

• Interrupt on overflow from FFFFh to 0000h

• Reset from CCP module trigger

In timer mode, Timer1 increments every instruction

cycle. In counter mode, it increments on every rising

edge of the external clock input.

Timer1 has a control register, shown in Figure 5-1.

Timer1 can be enabled/disabled by setting/clearing

control bit TMR1ON (T1CON<0>).

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored.

Figure 5-3 is a simplified block diagram of the Timer1

module.

Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

Timer1 also has an internal “reset input”. This reset can

be generated by the CCP module (Section 7.0).

FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0

R/W-0

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit0

bit7

- n = Value at POR reset

bit 7-6: Unimplemented: Read as ’0’

bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale value

10= 1:4 Prescale value

01= 1:2 Prescale value

00= 1:1 Prescale value

bit 3:

bit 2:

T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled

0 = Oscillator is shut off

Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1

1 = Do not synchronize external clock input

0 = Synchronize external clock input

TMR1CS = 0

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1:

bit 0:

TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1 = Enables Timer1

0 = Stops Timer1

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 41

PIC16C77X

5.1.1

TIMER1 COUNTER OPERATION

In this mode, Timer1 is being incremented via an exter-

nal source. Increments occur on a rising edge. After

Timer1 is enabled in counter mode, the module must

first have a falling edge before the counter begins to

increment.

FIGURE 5-2: TIMER1 INCREMENTING EDGE

T1CKI

(Default high)

T1CKI

(Default low)

Note: Arrows indicate counter increments.

FIGURE 5-3: TIMER1 BLOCK DIAGRAM

Set flag bit

TMR1IF on

Overflow

Synchronized

clock input

0

TMR1

TMR1L

TMR1H

T1OSC

1

TMR1ON

on/off

T1SYNC

RC0/T1OSO/T1CKI

RC1/T1OSI

1

Synchronize

det

Prescaler

1, 2, 4, 8

T1OSCEN

Enable

Oscillator

FOSC/4

Internal

Clock

0

(1)

2

SLEEP input

T1CKPS1:T1CKPS0

TMR1CS

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

DS30275A-page 42

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

5.2

Timer1 Oscillator

5.3

Timer1 Interrupt

A crystal oscillator circuit is built in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The oscilla-

tor is a low power oscillator rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for a 32 kHz crystal. Table 5-1 shows the capacitor

selection for the Timer1 oscillator.

The TMR1 Register pair (TMR1H:TMR1L) increments

from 0000h to FFFFh and rolls over to 0000h. The

TMR1 Interrupt, if enabled, is generated on overflow

which is latched in interrupt flag bit TMR1IF (PIR1<0>).

This interrupt can be enabled/disabled by setting/clear-

ing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

5.4

Resetting Timer1 using a CCP Trigger

Output

The Timer1 oscillator is identical to the LP oscillator.

The user must provide a software time delay to ensure

proper oscillator start-up.

If the CCP module is configured in compare mode to

generate a “special event trigger" (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1 and start an A/D

conversion (if the A/D module is enabled).

TABLE 5-1

CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

Osc Type

Freq

C1

C2

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

LP

32 kHz

100 kHz

200 kHz

33 pF

15 pF

33 pF

15 pF

Timer1 must be configured for either timer or synchro-

nized counter mode to take advantage of this feature. If

Timer1 is running in asynchronous counter mode, this

reset operation may not work.

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

In the event that a write to Timer1 coincides with a spe-

cial event trigger from CCP1, the write will take prece-

dence.

100 kHz

200 kHz

Epson C-2 100.00 KC-P

STD XTL 200.000 kHz

± 20 PPM

Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up

time.

In this mode of operation, the CCPR1H:CCPR1L regis-

ters pair effectively becomes the period register for

Timer1.

2: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appropri-

ate values of external components.

TABLE 5-2

REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on:

POR,

BOR

Value on

all other

resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0000 000x 0000 000u

0Bh,8Bh,

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

10Bh,18Bh

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

--00 0000 --uu uuuu

0Ch

PIR1

PIE1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

8Ch

0Eh

TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register

TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register

0Fh

10h

T1CON

—

T1CKPS1

T1CKPS0

T1OSCEN

T1SYNC TMR1CS TMR1ON

Legend:

x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 43

PIC16C77X

NOTES:

DS30275A-page 44

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

6.1

Timer2 Operation

6.0

TIMER2 MODULE

The Timer2 module timer has the following features:

Timer2 can be used as the PWM time-base for PWM

mode of the CCP module.

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

The TMR2 register is readable and writable, and is

cleared on any device reset.

• Readable and writable (Both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

The input clock (F^OSC/4) has a prescale option of 1:1,

1:4

or

1:16,

selected

by

control

bits

T2CKPS1:T2CKPS0 (T2CON<1:0>).

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF, (PIR1<1>)).

• SSP module optional use of TMR2 output to gen-

erate clock shift

Timer2 has a control register, shown in Figure 6-1.

Timer2 can be shut off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

The prescaler and postscaler counters are cleared

when any of the following occurs:

Figure 6-2 is a simplified block diagram of the Timer2

module.

• a write to the TMR2 register

• a write to the T2CON register

Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

• any device reset (Power-on Reset, MCLR reset,

Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

U-0

R/W-0

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit0

R

W

U

= Readable bit

= Writable bit

= Unimplemented bit,

read as ‘0’

bit7

- n = Value at POR reset

bit 7:

Unimplemented: Read as '0'

bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000= 1:1 Postscale

0001= 1:2 Postscale

•

1111= 1:16 Postscale

bit 2:

TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 45

PIC16C77X

6.2

Timer2 Interrupt

FIGURE 6-2: TIMER2 BLOCK DIAGRAM

Sets flag

TMR2

The Timer2 module has an 8-bit period register PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is ini-

tialized to FFh upon reset.

output ⁽¹⁾

bit TMR2IF

Reset

Prescaler

1:1, 1:4, 1:16

TMR2 reg

FOSC/4

Postscaler

1:1 to 1:16

2

Comparator

6.3

Output of TMR2

EQ

4

The output of TMR2 (before the postscaler) is fed to the

Synchronous Serial Port module which optionally uses

it to generate shift clock.

PR2 reg

Note 1: TMR2 register output can be software selected

by the SSP Module as a baud clock.

TABLE 6-1

REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on:

POR,

BOR

Value on

all other

resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0000 000x 0000 000u

0Bh,8Bh,

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

10Bh,18Bh

0000 0000 0000 0000

-000 0000 -000 0000

1111 1111 1111 1111

0Ch

8Ch

11h

12h

92h

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

PIE1

TMR2

T2CON

PR2

Timer2 module’s register

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

Timer2 Period Register

—

Legend:

Note 1:

x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

These bits are reserved on the 28-pin, always maintain these bits clear.

DS30275A-page 46

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

CCP2 Module

7.0

CAPTURE/COMPARE/PWM

(CCP) MODULE(S)

Capture/Compare/PWM Register2 (CCPR2) is com-

prised of two 8-bit registers: CCPR2L (low byte) and

CCPR2H (high byte). The CCP2CON register controls

the operation of CCP2. All are readable and writable.

Each CCP (Capture/Compare/PWM) module contains

a 16-bit register which can operate as a 16-bit capture

register, as a 16-bit compare register or as a PWM

master/slave Duty Cycle register. Table 7-1 shows the

timer resources of the CCP module modes.

Additional information on the CCP module is available

in the PICmicro™ Mid-Range Reference Manual,

(DS33023).

The operation of CCP1 is identical to that of CCP2, with

the exception of the special trigger. Therefore, opera-

tion of a CCP module in the following sections is

described with respect to CCP1.

TABLE 7-1

CCP MODE - TIMER

RESOURCE

CCP Mode

Timer Resource

Table 7-2 shows the interaction of the CCP modules.

Capture

Compare

PWM

Timer1

Timer2

CCP1 Module

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

TABLE 7-2

INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode

Interaction

Capture

Compare

PWM

Capture

Compare

PWM

Same TMR1 time-base.

The compare should be configured for the special event trigger, which clears TMR1.

The compare(s) should be configured for the special event trigger, which clears TMR1.

The PWMs will have the same frequency, and update rate (TMR2 interrupt).

PWM

Capture

Compare

None

PWM

FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)

U-0

—

U-0

—

R/W-0

CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit0

R = Readable bit

W = Writable bit

bit7

U = Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit 7-6: Unimplemented: Read as '0'

bit 5-4: CCPxX:CCPxY: PWM Least Significant bits

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits

0000= Capture/Compare/PWM off (resets CCPx module)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCPxIF bit is set)

1001= Compare mode, clear output on match (CCPxIF bit is set)

1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected)

1011= Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1

and starts an A/D conversion (if A/D module is enabled))

11xx= PWM mode

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 47

PIC16C77X

7.1.4

CCP PRESCALER

7.1

Capture Mode

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in capture mode,

the prescaler counter is cleared. This means that any

reset will clear the prescaler counter.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC2/CCP1. An event is defined as:

• every falling edge

• every rising edge

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore the first capture may be from

a non-zero prescaler. Example 7-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

• every 4th rising edge

• every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the inter-

rupt request flag bit CCP1IF (PIR1<2>) is set. It must

be cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value will be lost.

EXAMPLE 7-1: CHANGING BETWEEN

CAPTURE PRESCALERS

7.1.1

CCP PIN CONFIGURATION

CLRF

CCP1CON

;Turn CCP module off

MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler

In Capture mode, the RC2/CCP1 pin should be config-

ured as an input by setting the TRISC<2> bit.

; mode value and CCP ON

MOVWF CCP1CON

;Load CCP1CON with this

; value

Note: If the RC2/CCP1 is configured as an out-

put, a write to the port can cause a capture

condition.

FIGURE 7-2: CAPTURE MODE OPERATION

BLOCK DIAGRAM

Set flag bit CCP1IF

(PIR1<2>)

Prescaler

÷ 1, 4, 16

RC2/CCP1

CCPR1H

CCPR1L

TMR1L

Capture

Enable

and

edge detect

TMR1H

CCP1CON<3:0>

Q’s

7.1.2

TIMER1 MODE SELECTION

Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture

feature. In asynchronous counter mode, the capture

operation may not work.

7.1.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF following any such

change in operating mode.

DS30275A-page 48

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

7.2.1

CCP PIN CONFIGURATION

7.2

Compare Mode

The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC2/CCP1 pin is:

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

• driven High

• driven Low

• remains Unchanged

7.2.2

TIMER1 MODE SELECTION

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

FIGURE 7-3: COMPARE MODE

OPERATION BLOCK

DIAGRAM

7.2.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>)

which starts an A/D conversion

7.2.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

Special Event Trigger (CCP2 only)

Set flag bit CCP1IF

(PIR1<2>)

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

CCPR1H CCPR1L

Q

S

R

Output

Logic

Comparator

match

RC2/CCP1

The special trigger output of CCP2 resets the TMR1

register pair, and starts an A/D conversion (if the A/D

module is enabled).

TRISC<2>

Output Enable

TMR1H TMR1L

CCP1CON<3:0>

Mode Select

Note: The special event trigger from the CCP2

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

TABLE 7-3

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Value on:

POR,

BOR

Value on

all other

resets

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

8Ch

87h

0Eh

0Fh

10h

15h

16h

17h

PIR1

PSPIF⁽¹⁾ADIF

PSPIE⁽¹⁾ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

1111 1111 1111 1111

PIE1

TRISC

TMR1L

TMR1H

T1CON

CCPR1L

PORTC Data Direction Register

Holding register for the Least Significant Byte of the 16-bit TMR1 register

Holding register for the Most Significant Byte of the 16-bit TMR1register

xxxx xxxx uuuu uuuu

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Capture/Compare/PWM register1 (LSB)

xxxx xxxx uuuu uuuu

CCPR1H Capture/Compare/PWM register1 (MSB)

CCP1CON CCP1X CCP1Y

—

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 49

PIC16C77X

7.3.1

PWM PERIOD

7.3

PWM Mode

The PWM period is specified by writing to the PR2 reg-

ister. The PWM period can be calculated using the fol-

lowing formula:

In Pulse Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output. Since

the CCP1 pin is multiplexed with the PORTC data latch,

the TRISC<2> bit must be cleared to make the CCP1

pin an output.

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

PWM frequency is defined as 1 / [PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

Figure 7-4 shows a simplified block diagram of the CCP

module in PWM mode.

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

For a step by step procedure on how to set up the CCP

module for PWM operation, see Section 7.3.3.

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

Note: The Timer2 postscaler (see Section 6.0) is

not used in the determination of the PWM

frequency. The postscaler could be used to

have a servo update rate at a different fre-

quency than the PWM output.

FIGURE 7-4: SIMPLIFIED PWM BLOCK

DIAGRAM

CCP1CON<5:4>

Duty cycle registers

CCPR1L

7.3.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available: the CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

CCPR1H (Slave)

Q

R

S

Comparator

TMR2

RC2/CCP1

(Note 1)

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

Tosc • (TMR2 prescale value)

TRISC<2>

Comparator

Clear Timer,

CCP1 pin and

latch D.C.

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

PR2

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

A PWM output (Figure 7-5) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period (1/

period).

When the CCPR1H and 2-bit latch match TMR2 con-

catenated with an internal 2-bit Q clock or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

FIGURE 7-5: PWM OUTPUT

Maximum PWM resolution (bits) for a given PWM

frequency:

Period

FOSC

log

(

)

FPWM

=

bits

log(2)

Duty Cycle

TMR2 = PR2

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be

cleared.

TMR2 = Duty Cycle

TMR2 = PR2

For an example PWM period and duty cycle calcu-

lation, see the PICmicro™ Mid-Range Reference

Manual, (DS33023).

DS30275A-page 50

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

7.3.3

SET-UP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 regis-

ter.

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

5. Configure the CCP1 module for PWM operation.

TABLE 7-4

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency

1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

5.5

Maximum Resolution (bits)

TABLE 7-5

REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on:

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

all other

resets

0Bh,8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

8Ch

87h

11h

92h

12h

15h

16h

17h

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

1111 1111 1111 1111

PIE1

TRISC

TMR2

PORTC Data Direction Register

Timer2 module’s register

0000 0000 0000 0000

PR2

Timer2 module’s period register

1111 1111 1111 1111

T2CON

CCPR1L

CCPR1H

CCP1CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Capture/Compare/PWM register1 (LSB)

Capture/Compare/PWM register1 (MSB)

xxxx xxxx uuuu uuuu

—

CCP1X

CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 51

PIC16C77X

NOTES:

DS30275A-page 52

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.0

MASTER SYNCHRONOUS

SERIAL PORT (MSSP)

MODULE

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers, dis-

play drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C™)

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 53

PIC16C77X

FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)

R/W-0 R/W-0

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

SMP

CKE

R/W

R =Readable bit

W =Writable bit

bit7

bit0

U =Unimplemented bit, read

as ‘0’

- n =Value at POR reset

bit 7:

SMP: Sample bit

SPI Master Mode

1 = Input data sampled at end of data output time

0 = Input data sampled at middle of data output time

SPI Slave Mode

SMP must be cleared when SPI is used in slave mode

In I²C master or slave mode:

1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)

0= Slew rate control enabled for high speed mode (400 kHz)

bit 6:

CKE: SPI Clock Edge Select (Figure 8-6, Figure 8-8, and Figure 8-9)

CKP = 0

1 = Data transmitted on rising edge of SCK

0 = Data transmitted on falling edge of SCK

CKP = 1

1 = Data transmitted on falling edge of SCK

0 = Data transmitted on rising edge of SCK

bit 5:

bit 4:

D/A: Data/Address bit (I²C mode only)

1 = Indicates that the last byte received or transmitted was data

0 = Indicates that the last byte received or transmitted was address

P: Stop bit

(I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)

1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)

0 = Stop bit was not detected last

bit 3:

bit 2:

S: Start bit

(I²C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)

1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)

0 = Start bit was not detected last

R/W: Read/Write bit information (I²C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the

address match to the next start bit, stop bit, or not ACK bit.

In I²C slave mode:

1 = Read

0 = Write

In I²C master mode:

1 = Transmit is in progress

0 = Transmit is not in progress.

Or’ing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode

bit 1:

bit 0:

UA: Update Address (10-bit I²C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register

0 = Address does not need to be updated

BF: Buffer Full Status bit

Receive (SPI and I²C modes)

1 = Receive complete, SSPBUF is full

0 = Receive not complete, SSPBUF is empty

Transmit (I²C mode only)

1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full

0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty

DS30275A-page 54

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0

CKP

R/W-0

WCOL SSPOV SSPEN

bit7

SSPM3 SSPM2 SSPM1 SSPM0

bit0

R = Readable bit

W = Writable bit

- n =Value at POR reset

bit 7:

WCOL: Write Collision Detect bit

Master Mode:

1 = A write to the SSPBUF register was attempted while the I²C conditions were not valid for a

transmission to be started

0 = No collision

Slave Mode:

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6:

SSPOV: Receive Overflow Indicator bit

In SPI mode

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,

the data in SSPSR is lost. Overflow can only occur in slave mode. In slave mode, the user must read the

SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode, the overflow bit is not

set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be

cleared in software).

0 = No overflow

In I²C mode

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"

in transmit mode. (Must be cleared in software).

0 = No overflow

bit 5:

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output.

In SPI mode

1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In I²C mode

1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins

0 = Disables serial port and configures these pins as I/O port pins

bit 4:

CKP: Clock Polarity Select bit

In SPI mode

1 = Idle state for clock is a high level

0 = Idle state for clock is a low level

In I²C slave mode

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

In I²C master mode

Unused in this mode

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000= SPI master mode, clock = FOSC/4

0001= SPI master mode, clock = FOSC/16

0010= SPI master mode, clock = FOSC/64

0011= SPI master mode, clock = TMR2 output/2

0100= SPI slave mode, clock = SCK pin. SS pin control enabled.

0101= SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin

0110= I²C slave mode, 7-bit address

0111= I²C slave mode, 10-bit address

1000= I²C master mode, clock = FOSC / (4 * (SSPADD+1) )

1xx1= Reserved

1x1x= Reserved

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 55

PIC16C77X

FIGURE 8-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)

R/W-0

GCEN

bit7

R/W-0

AKDT

R/W-0

AKEN

R/W-0

RCEN

R/W-0 R/W-0 R/W-0

AKSTAT

PEN

RSEN

SEN

R =Readable bit

W =Writable bit

U =Unimplemented bit,

Read as ‘0’

bit0

- n =Value at POR reset

bit 7:

bit 6:

GCEN: General Call Enable bit (In I²C slave mode only)

1 = Enable interrupt when a general call address (0000h) is received in the SSPSR.

0 = General call address disabled.

AKSTAT: Acknowledge Status bit (In I²C master mode only)

In master transmit mode:

1 = Acknowledge was not received from slave

0 = Acknowledge was received from slave

bit 5:

bit 4:

AKDT: Acknowledge Data bit (In I²C master mode only)

In master receive mode:

Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.

1 = Not Acknowledge

0 = Acknowledge

AKEN: Acknowledge Sequence Enable bit (In I²C master mode only).

In master receive mode:

1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit AKDT data bit. Automatically

cleared by hardware.

0 = Acknowledge sequence idle

bit 3:

RCEN: Receive Enable bit (In I²C master mode only).

1 = Enables Receive mode for I²C

0 = Receive idle

bit 2:

PEN: Stop Condition Enable bit (In I²C master mode only).

SCK release control

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition idle

bit 1: RSEN: Repeated Start Condition Enabled bit (In I²C master mode only)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition idle.

bit 0: SEN: Start Condition Enabled bit (In I²C master mode only)

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition idle.

Note: For bits AKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the idle mode, this bit may not be

set (no spooling), and the SSPBUF may not be written (or writes to the SSPBUF are disabled).

DS30275A-page 56

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.1

SPI Mode

FIGURE 8-4: MSSP BLOCK DIAGRAM

(SPI MODE)

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. All

four modes of SPI are supported. To accomplish com-

munication, typically three pins are used:

Internal

data bus

Read

Write

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

SSPBUF reg

SSPSR reg

Additionally, a fourth pin may be used when in a slave

mode of operation:

shift

clock

SDI

• Slave Select (SS)

bit0

8.1.1

OPERATION

SDO

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

Control

Enable

SS

Edge

Select

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data input sample phase

2

Clock Select

(middle or end of data output time)

• Clock edge

(output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

SSPM3:SSPM0

SMP:CKE

2

4

TMR2 output

2

Edge

Select

TOSC

Prescaler

4, 16, 64

Figure 8-4 shows the block diagram of the MSSP mod-

ule when in SPI mode.

SCK

Data to TX/RX in SSPSR

Data direction bit

The MSSP consists of a transmit/receive Shift Register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8-bits of data

have been received, that byte is moved to the SSPBUF

register. Then the buffer full detect bit BF

(SSPSTAT<0>) and the interrupt flag bit SSPIF

(PIR1<3>) are set. This double buffering of the

received data (SSPBUF) allows the next byte to start

reception before reading the data that was just

received. Any write to the SSPBUF register during

transmission/reception of data will be ignored, and the

write collision detect bit WCOL (SSPCON<7>) will be

set. User software must clear the WCOL bit so that it

can be determined if the following write(s) to the SSP-

BUF register completed successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

full bit, BF (SSPSTAT<0>), indicates when the SSP-

BUF has been loaded with the received data (transmis-

sion is complete). When the SSPBUF is read, bit BF is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally the MSSP Interrupt is used to

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 57

PIC16C77X

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 8-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

SDI, SDO, SCK, and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the TRIS register)

appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

EXAMPLE 8-1: LOADING THE SSPBUF

(SSPSR) REGISTER

• SCK (Slave mode) must have TRISC<3> set

• SS must have TRISA<5> set

BSF

STATUS, RP0

;Specify Bank 1

;Has data been

;received

LOOP BTFSS SSPSTAT, BF

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value.

;(transmit

;complete)?

GOTO LOOP

;No

BCF

STATUS, RP0

;Specify Bank 0

;W reg = contents

;of SSPBUF

8.1.3

TYPICAL CONNECTION

MOVF SSPBUF, W

Figure 8-5 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite edge

of the clock. Both processors should be programmed to

same Clock Polarity (CKP), then both controllers would

send and receive data at the same time. Whether the

data is meaningful (or dummy data) depends on the

application software. This leads to three scenarios for

data transmission:

MOVWF RXDATA

MOVF TXDATA, W

;Save in user RAM

;W reg = contents

; of TXDATA

MOVWF SSPBUF

;New data to xmit

The SSPSR is not directly readable or writable, and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT) indi-

cates the various status conditions.

8.1.2

ENABLING SPI I/O

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

isters, and then set bit SSPEN. This configures the

• Master sends dummy data — Slave sends data

FIGURE 8-5: SPI MASTER/SLAVE CONNECTION

SPI Master SSPM3:SSPM0 = 00xxb

SPI Slave SSPM3:SSPM0 = 010xb

SDO

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

PROCESSOR 1

PROCESSOR 2

DS30275A-page 58

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.1.4

MASTER MODE

Figure 8-6, Figure 8-8, and Figure 8-9 where the MSb

is transmitted first. In master mode, the SPI clock rate

(bit rate) is user programmable to be one of the follow-

ing:

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 8-5) is to broad-

cast data by the software protocol.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

In master mode the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI

module is only going to receive, the SDO output could

be disabled (programmed as an input). The SSPSR

register will continue to shift in the signal present on the

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “line activity monitor”.

This allows a maximum bit clock frequency (at 20 MHz)

of 8.25 MHz.

Figure 8-6 shows the waveforms for Master mode.

When CKE = 1, the SDO data is valid before there is a

clock edge on SCK. The change of the input sample is

shown based on the state of the SMP bit. The time

when the SSPBUF is loaded with the received data is

shown.

The clock polarity is selected by appropriately program-

ming bit CKP (SSPCON<4>). This then would give

waveforms for SPI communication as shown in

FIGURE 8-6: SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 clock

modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit6

bit2

bit5

bit4

bit1

bit0

SDO

(CKE = 0)

bit7

bit3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit0

bit7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 59

PIC16C77X

8.1.5

SLAVE MODE

SDO pin is no longer driven, even if in the middle of

a transmitted byte, and becomes a floating output.

External pull-up/ pull-down resistors may be desirable,

depending on the application.

In slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched the interrupt flag bit SSPIF (PIR1<3>)

is set.

Note: When the SPI module is in Slave Mode

with SS pin control enabled, (SSP-

CON<3:0> = 0100) the SPI module will

reset if the SS pin is set to VDD.

While in slave mode the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

Note: If the SPI is used in Slave Mode with

CKE = ’1’, then SS pin control must be

enabled.

While in sleep mode, the slave can transmit/receive

data. When a byte is received the device will wake-up

from sleep.

When the SPI module resets, the bit counter is forced

to 0. This can be done by either forcing the SS pin to a

high level or clearing the SSPEN bit.

8.1.6

SLAVE SELECT SYNCHRONIZATION

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver the SDO pin can be configured as

an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

The SS pin allows a synchronous slave mode. The

SPI must be in slave mode with SS pin control

enabled (SSPCON<3:0> = 0100). The pin must not

be driven low for the SS pin to function as an input.

TRISA<5> must be set. When the SS pin is low,

transmission and reception are enabled and the

SDO pin is driven. When the SS pin goes high, the

FIGURE 8-7: SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit7

bit0

SDO

bit7

SDI

(SMP = 0)

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

DS30275A-page 60

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 8-8: SPI SLAVE MODE WAVEFORM (CKE = 0)

SS

optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

bit0

bit7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 8-9: SPI SLAVE MODE WAVEFORM (CKE = 1)

SS

not optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit6

bit2

bit5

bit4

bit1

bit0

SDO

bit7

bit3

SDI

(SMP = 0)

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 cycle

after Q2↓

SSPSR to

SSPBUF

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 61

PIC16C77X

8.1.7

SLEEP OPERATION

8.1.8

EFFECTS OF A RESET

In master mode all module clocks are halted, and the

transmission/reception will remain in that state until the

device wakes from sleep. After the device returns to

normal mode, the module will continue to transmit/

receive data.

A reset disables the MSSP module and terminates the

current transfer.

In slave mode, the SPI transmit/receive shift register

operates asynchronously to the device. This allows the

device to be placed in sleep mode, and data to be

shifted into the SPI transmit/receive shift register.

When all 8-bits have been received, the MSSP interrupt

flag bit will be set and if enabled will wake the device

from sleep.

TABLE 8-1

REGISTERS ASSOCIATED WITH SPI OPERATION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR MCLR, WDT

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

8Ch

13h

14h

94h

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

PIE1

SSPBUF

SSPCON

SSPSTAT

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL

SMP

SSPOV

CKE

SSPEN

D/A

CKP

P

SSPM3

S

SSPM2

R/W

SSPM1

UA

SSPM0 0000 0000 0000 0000

BF

0000 0000 0000 0000

Legend:

x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by the SSP in SPI mode.

Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.

DS30275A-page 62

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.2

MSSP I²C Operation

FIGURE 8-11: I²C MASTER MODE BLOCK

DIAGRAM

The MSSP module in I²C mode fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on start and stop bits in

hardware to determine a free bus (multi-master func-

tion). The MSSP module implements the standard

mode specifications as well as 7-bit and 10-bit address-

ing.

Internal

data bus

Read

Write

SSPADD<6:0>

7

Baud Rate Generator

Refer to Application Note AN578, "Use of the SSP

Module in the I ²C Multi-Master Environment."

SSPBUF reg

SSPSR reg

SCL

A "glitch" filter is on the SCL and SDA pins when the pin

is an input. This filter operates in both the 100 kHz and

400 kHz modes. In the 100 kHz mode, when these pins

are an output, there is a slew rate control of the pin that

is independant of device frequency.

shift

clock

SDA

MSb

LSb

Addr Match

FIGURE 8-10: I²C SLAVE MODE BLOCK

DIAGRAM

Match detect

SSPADD reg

Internal

data bus

Set/Clear S bit

and

Read

Write

Start and Stop bit

detect / generate

Clear/Set P bit

(SSPSTAT reg)

SSPBUF reg

SSPSR reg

SCL

SDA

and Set SSPIF

shift

clock

Two pins are used for data transfer. These are the SCL

pin, which is the clock, and the SDA pin, which is the

data. The SDA and SCL pins that are automatically

configured when the I²C mode is enabled. The SSP

module functions are enabled by setting SSP Enable

bit SSPEN (SSPCON<5>).

MSb

LSb

Addr Match

Match detect

SSPADD reg

The MSSP module has six registers for I²C operation.

They are the:

• SSP Control Register (SSPCON)

• SSP Control Register2 (SSPCON2)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces-

sible

Set, Reset

S, P bits

(SSPSTAT reg)

Start and

Stop bit detect

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I²C opera-

tion. Four mode selection bits (SSPCON<3:0>) allow

one of the following I²C modes to be selected:

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Master mode, clock = OSC/4 (SSPADD +1)

Before selecting any I²C mode, the SCL and SDA pins

must be programmed to inputs by setting the appropri-

ate TRIS bits. Selecting an I²C mode, by setting the

SSPEN bit, enables the SCL and SDA pins to be used

as the clock and data lines in I²C mode.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 63

PIC16C77X

The SSPSTAT register gives the status of the data

transfer. This information includes detection of a

START (S) or STOP (P) bit, specifies if the received

byte was data or address if the next byte is the comple-

tion of 10-bit address, and if this will be a read or write

data transfer.

8.2.1.1

ADDRESSING

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

SSPBUF is the register to which the transfer data is

written to or read from. The SSPSR register shifts the

data in or out of the device. In receive operations, the

SSPBUF and SSPSR create a doubled buffered

receiver. This allows reception of the next byte to begin

before reading the last byte of received data. When the

complete byte is received, it is transferred to the

SSPBUF register and flag bit SSPIF is set. If another

complete byte is received before the SSPBUF register

is read, a receiver overflow has occurred and bit

SSPOV (SSPCON<6>) is set and the byte in the

SSPSR is lost.

a) The SSPSR register value is loaded into the

SSPBUF register on the falling edge of the 8th

SCL pulse.

b) The buffer full bit, BF is set on the falling edge of

the 8th SCL pulse.

c) An ACK pulse is generated.

d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) - on the falling

edge of the 9th SCL pulse.

The SSPADD register holds the slave address. In 10-bit

mode, the user needs to write the high byte of the

address (1111 0 A9 A8 0). Following the high byte

address match, the low byte of the address needs to be

loaded (A7:A0).

In 10-bit address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSbs) of the first address byte specify if this is a 10-bit

address. Bit R/W (SSPSTAT<2>) must specify a write

so the slave device will receive the second address

byte. For a 10-bit address the first byte would equal

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs

of the address. The sequence of events for a 10-bit

address is as follows, with steps 7- 9 for slave-transmit-

ter:

8.2.1

SLAVE MODE

In slave mode, the SCL and SDA pins must be config-

ured as inputs. The MSSP module will override the

input state with the output data when required (slave-

transmitter).

When an address is matched or the data transfer after

an address match is received, the hardware automati-

cally will generate the acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

1. Receive first (high) byte of Address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the

SCL line).

There are certain conditions that will cause the MSSP

module not to give this ACK pulse. These are if either

(or both):

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

5. Update the SSPADD register with the first (high)

byte of Address. This will clear bit UA and

release the SCL line.

b) The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

If the BF bit is set, the SSPSR register value is not

loaded into the SSPBUF, but bit SSPIF and SSPOV are

set. Table 8-2 shows what happens when a data trans-

fer byte is received, given the status of bits BF and

SSPOV. The shaded cells show the condition where

user software did not properly clear the overflow condi-

tion. Flag bit BF is cleared by reading the SSPBUF reg-

ister while bit SSPOV is cleared through software.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

7. Receive Repeated Start condition.

8. Receive first (high) byte of Address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

The SCL clock input must have a minimum high and

low time for proper operation. The high and low times

of the I²C specification as well as the requirement of the

MSSP module is shown in timing parameter #100 and

parameter #101 of the Electrical Specifications.

Note: Following the Repeated Start condition

(step 7) in 10-bit mode, the user only

needs to match the first 7-bit address. The

user does not update the SSPADD for the

second half of the address.

DS30275A-page 64

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.2.1.2

SLAVE RECEPTION

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-

ware. The SSPSTAT register is used to determine the

status of the received byte.

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register.

Note: The SSPBUF will be loaded if the SSPOV

bit is set and the BF flag is cleared. If a

read of the SSPBUF was performed, but

the user did not clear the state of the

SSPOV bit before the next receive

occured. The ACK is not sent and the SSP-

BUF is updated.

When the address byte overflow condition exists, then

no acknowledge (ACK) pulse is given. An overflow con-

dition is defined as either bit BF (SSPSTAT<0>) is set

or bit SSPOV (SSPCON<6>) is set.

TABLE 8-2

DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

Set bit SSPIF

Generate ACK

Pulse

(SSP Interrupt occurs

if enabled)

BF

SSPOV

SSPSR → SSPBUF

0

1

0

1

Yes

No

Yes

No

Yes

No

Yes

Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

8.2.1.3

SLAVE TRANSMISSION

An SSP interrupt is generated for each data transfer

byte. The SSPIF flag bit must be cleared in software,

and the SSPSTAT register is used to determine the sta-

tus of the byte tranfer. The SSPIF flag bit is set on the

falling edge of the ninth clock pulse.

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

be sent on the ninth bit, and the SCL pin is held low.

The transmit data must be loaded into the SSPBUF

register, which also loads the SSPSR register. Then the

SCL pin should be enabled by setting bit CKP (SSP-

CON<4>). The master must monitor the SCL pin prior

to asserting another clock pulse. The slave devices

may be holding off the master by stretching the clock.

The eight data bits are shifted out on the falling edge of

the SCL input. This ensures that the SDA signal is valid

during the SCL high time (Figure 8-13).

As a slave-transmitter, the ACK pulse from the master-

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then the

data transfer is complete. When the not ACK is latched

by the slave, the slave logic is reset and the slave then

monitors for another occurrence of the START bit. If the

SDA line was low (ACK), the transmit data must be

loaded into the SSPBUF register, which also loads the

SSPSR register. Then the SCL pin should be enabled

by setting the CKP bit.

FIGURE 8-12: I²C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W=0

ACK

Not

Receiving Address

A7 A6 A5 A4

Receiving Data

ACK

SDA

A3 A2 A1

D7 D6 D5 D4 D3 D2

D0

8

D7 D6

D5

D4 D3

D2

D0

8

D1

7

D1

7

3

9

7

1

2

4

9

5

4

3

6

9

5

6

1

2

3

6

1

2

4

8

5

P

SCL

S

SSPIF

Bus Master

terminates

transfer

BF (SSPSTAT<0>)

Cleared in software

SSPBUF register is read

SSPOV (SSPCON<6>)

Bit SSPOV is set because the SSPBUF register is still full.

ACK is not sent.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 65

PIC16C77X

FIGURE 8-13: I²C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

R/W = 0

Transmitting Data Not ACK

D7 D6 D5 D4 D3 D2 D1 D0

R/W = 1

Receiving Address

ACK

SDA

SCL

A7 A6 A5 A4 A3 A2 A1

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

S

P

SCL held low

while CPU

responds to SSPIF

Data in

sampled

SSPIF

BF (SSPSTAT<0>)

CKP (SSPCON<4>)

cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

(the SSPBUF must be written-to

before the CKP bit can be set)

DS30275A-page 66

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2

FIGURE 8-14: I C SLAVE-TRANSMITTER (10-BIT ADDRESS)

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 67

PIC16C77X

2

FIGURE 8-15: I C SLAVE-RECEIVER (10-BIT ADDRESS)

DS30275A-page 68

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1999 Microchip Technology Inc.

PIC16C77X

8.2.2

GENERAL CALL ADDRESS SUPPORT

If the general call address matches, the SSPSR is

transfered to the SSPBUF, the BF flag is set (eighth bit),

and on the falling edge of the ninth bit (ACK bit) the

SSPIF flag is set.

The addressing procedure for the I²C bus is such that

the first byte after the START condition usually deter-

mines which device will be the slave addressed by the

master. The exception is the general call address which

can address all devices. When this address is used, all

devices should, in theory, respond with an acknowl-

edge.

When the interrupt is serviced. The source for the

interrupt can be checked by reading the contents of the

SSPBUF to determine if the address was device spe-

cific or a general call address.

In 10-bit mode, the SSPADD is required to be updated

for the second half of the address to match, and the UA

bit is set (SSPSTAT<1>). If the general call address is

sampled when GCEN is set while the slave is config-

ured in 10-bit address mode, then the second half of

the address is not necessary, the UA bit will not be set,

and the slave will begin receiving data after the

acknowledge (Figure 8-16).

The general call address is one of eight addresses

reserved for specific purposes by the I²C protocol. It

consists of all 0’s with R/W = 0

The general call address is recognized when the Gen-

eral Call Enable bit (GCEN) is enabled (SSPCON2<7>

is set). Following a start-bit detect, 8-bits are shifted

into SSPSR and the address is compared against

SSPADD, and is also compared to the general call

address, fixed in hardware.

FIGURE 8-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT MODE)

Address is compared to General Call Address

after ACK, set interrupt flag

Receiving data

D5 D4 D3 D2 D1

ACK

9

R/W = 0

ACK

General Call Address

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

S

SSPIF

BF

(SSPSTAT<0>)

Cleared in software

SSPBUF is read

SSPOV

(SSPCON<6>)

’0’

’1’

GCEN

(SSPCON2<7>)

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 69

PIC16C77X

8.2.3

SLEEP OPERATION

8.2.4

EFFECTS OF A RESET

While in sleep mode, the I²C module can receive

addresses or data, and when an address match or

complete byte transfer occurs wake the processor from

sleep (if the SSP interrupt is enabled).

A reset diables the SSP module and terminates the

current transfer.

TABLE 8-3

REGISTERS ASSOCIATED WITH I²C OPERATION

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR, BOR MCLR, WDT

0Bh, 8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

0Ch

8Ch

0Dh

8Dh

13h

14h

91h

94h

PIR1

PSPIF⁽¹⁾

PSPIE⁽¹⁾

LVDIF

ADIF

ADIE

—

RCIF

RCIE

—

TXIF

TXIE

—

SSPIF

SSPIE

BCLIF

BCLIE

CCP1IF

CCP1IE

—

TMR2IF

TMR2IE

—

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

CCP2IF 0--- 0--0 0--- 0--0

CCP2IE 0--- 0--0 0--- 0--0

xxxx xxxx uuuu uuuu

PIE1

PIR2

PIE2

LVDIE

—

SSPBUF

SSPCON

SSPCON2

SSPSTAT

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL

GCEN

SMP

SSPOV

AKSTAT

CKE

SSPEN

AKDT

D/A

CKP

AKEN

P

SSPM3

RCEN

S

SSPM2

PEN

SSPM1

RSEN

UA

SSPM0 0000 0000 0000 0000

SEN

0000 0000 0000 0000

R/W

BF

0000 0000 0000 0000

Legend:

x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in I²C mode.

Note 1: These bits are reserved on the 28-pin devices, always maintain these bits clear.

2: These bits are reserved on these devices, always maintain these bits clear.

DS30275A-page 70

Advance Information

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PIC16C77X

8.2.5

MASTER MODE

In master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a reset or when the MSSP module is dis-

abled. Control of the I²C bus may be taken when the P

bit is set, or the bus is idle with both the S and P bits

clear.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge transmit

• Repeated Start

2

FIGURE 8-17: SSP BLOCK DIAGRAM (I C MASTER MODE)

Internal

data bus

SSPM3:SSPM0,

SSPADD<6:0>

Read

Write

SSPBUF

SSPSR

Baud

rate

generator

SDA

shift

clock

SDA in

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate

SCL

Start bit detect,

Stop bit detect

Write collision detect

Clock Arbitration

State counter for

end of XMIT/RCV

SCL in

Bus Collision

Set/Reset, S, P, WCOL (SSPSTAT)

Set SSPIF, BCLIF

Reset AKSTAT, PEN (SSPCON2)

1999 Microchip Technology Inc.

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DS30275A-page 71

PIC16C77X

8.2.6

MULTI-MASTER OPERATION

8.2.7.4

I²C MASTER MODE OPERATION

In multi-master mode, the interrupt generation on the

detection of the START and STOP conditions allows

the determination of when the bus is free. The STOP

(P) and START (S) bits are cleared from a reset or

when the MSSP module is disabled. Control of the I²C

bus may be taken when bit P (SSPSTAT<4>) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the STOP condition occurs.

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

Start condition. Since the Repeated Start condition is

also the beginning of the next serial transfer, the I²C

bus will not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic '0'. Serial data is

transmitted 8 bits at a time. After each byte is transmit-

ted, an acknowledge bit is received. START and STOP

conditions are output to indicate the beginning and the

end of a serial transfer.

In multi-master operation, the SDA line must be moni-

tored, for abitration, to see if the signal level is the

expected output level. This check is performed in hard-

ware, with the result placed in the BCLIF bit.

The states where arbitration can be lost are:

• Address Transfer

In Master receive mode the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case the R/W bit will be

logic '1'. Thus the first byte transmitted is a 7-bit slave

address followed by a '1' to indicate receive bit. Serial

data is received via SDA while SCL outputs the serial

clock. Serial data is received 8 bits at a time. After each

byte is received, an acknowledge bit is transmitted.

START and STOP conditions indicate the beginning

and end of transmission.

• Data Transfer

• A Start Condition

• A Repeated Start Condition

• An Acknowledge Condition

8.2.7

I²C MASTER OPERATION SUPPORT

Master Mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON and by setting the

SSPEN bit. Once master mode is enabled, the user

has six options.

The baud rate generator used for SPI mode operation

is now used to set the SCL clock frequency for either

100 kHz, 400 kHz, or 1 MHz I²C operation. The baud

rate generator reload value is contained in the lower 7

bits of the SSPADD register. The baud rate generator

will automatically begin counting on a write to the SSP-

BUF. Once the given operation is complete (i.e. trans-

mission of the last data bit is followed by ACK), the

internal clock will automatically stop counting and the

SCL pin will remain in its last state

- Assert a start condition on SDA and SCL.

- Assert a Repeated Start condition on SDA and

SCL.

- Write to the SSPBUF register initiating trans-

mission of data/address.

- Generate a stop condition on SDA and SCL.

- Configure the I²C port to receive data.

- Generate an Acknowledge condition at the end

of a received byte of data.

A typical transmit sequence would go as follows:

Note: The MSSP Module, when configured in I²C

Master Mode, does not allow queueing of

events. For instance: The user is not

allowed to initiate a start condition, and

immediately write the SSPBUF register to

initiate transmission before the START

condition is complete. In this case the

SSPBUF will not be written to, and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

a) The user generates a Start Condition by setting

the START enable bit (SEN) in SSPCON2.

b) SSPIF is set. The module will wait the required

start time before any other operation takes

place.

c) The user loads the SSPBUF with address to

transmit.

d) Address is shifted out the SDA pin until all 8 bits

are transmitted.

e) The MSSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register ( SSPCON2<6>).

f) The module generates an interrupt at the end of

the ninth clock cycle by setting SSPIF.

g) The user loads the SSPBUF with eight bits of

data.

h) DATA is shifted out the SDA pin until all 8 bits

are transmitted.

DS30275A-page 72

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PIC16C77X

i) The MSSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register ( SSPCON2<6>).

In I²C master mode, the BRG is reloaded automatically.

If Clock Arbitration is taking place for instance, the BRG

will be reloaded when the SCL pin is sampled high

(Figure 8-19).

j) The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

FIGURE 8-18: BAUD RATE GENERATOR

BLOCK DIAGRAM

k) The user generates a STOP condition by setting

the STOP enable bit PEN in SSPCON2.

SSPM3:SSPM0

SSPADD<6:0>

l) Interrupt is generated once the STOP condition

is complete.

8.2.8

BAUD RATE GENERATOR

SSPM3:SSPM0

SCL

Reload

Control

Reload

In I²C master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 8-18). When the BRG is loaded with this value,

the BRG counts down to 0 and stops until another

reload has taken place. The BRG count is decremented

twice per instruction cycle (TCY) on the Q2 and Q4

clock.

Fosc/4

BRG Down Counter

CLKOUT

FIGURE 8-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX-1

SCL allowed to transition high

SCL de-asserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements

(on Q2 and Q4 cycles)

BRG

value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place, and BRG starts its count.

BRG

reload

1999 Microchip Technology Inc.

Advance Information

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PIC16C77X

8.2.9

I²C MASTER MODE START CONDITION

TIMING

8.2.9.5

WCOL STATUS FLAG

If the user writes the SSPBUF when an START

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

To initiate a START condition, the user sets the start

condition enable bit, SEN (SSPCON2<0>). If the SDA

and SCL pins are sampled high, the baud rate genera-

tor is re-loaded with the contents of SSPADD<6:0>,

and starts its count. If SCL and SDA are both sampled

high when the baud rate generator times out (T_BRG),

the SDA pin is driven low. The action of the SDA being

driven low while SCL is high is the START condition,

and causes the S bit (SSPSTAT<3>) to be set. Follow-

ing this, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and resumes its count.

When the baud rate generator times out (T_BRG), the

SEN bit (SSPCON2<0>) will be automatically cleared

by hardware, the baud rate generator is suspended

leaving the SDA line held low, and the START condition

is complete.

Note: Because queueing of events is not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

Note: If at the beginning of START condition the

SDA and SCL pins are already sampled

low, or if during the START condition the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs, the

Bus Collision Interrupt Flag (BCLIF) is set,

the START condition is aborted, and the

I²C module is reset into its IDLE state.

FIGURE 8-20: FIRST START BIT TIMING

Set S bit (SSPSTAT<3>)

Write to SEN bit occurs here.

SDA = 1,

At completion of start bit,

Hardware clears SEN bit

and sets SSPIF bit

SCL = 1

T_BRG

Write to SSPBUF occurs here

2nd Bit

1st Bit

T_BRG

SDA

SCL

T_BRG

S

DS30275A-page 74

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 8-21: START CONDITION FLOWCHART

SSPEN = 1,

SSPCON<3:0> = 1000

Idle Mode

SEN (SSPCON2<0> = 1)

Bus collision detected,

Set BCLIF,

No

SDA = 1?

Release SCL,

Clear SEN

SCL = 1?

Yes

Load BRG with

SSPADD<6:0>

No

Yes

No

BRG

Rollover?

SCL= 0?

SDA = 0?

Yes

Reset BRG

Force SDA = 0,

Load BRG with

SSPADD<6:0>,

Set S bit.

BRG

rollover?

No

SCL = 0?

Yes

Reset BRG

Force SCL = 0,

Start Condition Done,

Clear SEN

and set SSPIF

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 75

PIC16C77X

8.2.10 I²C MASTER MODE REPEATED START

CONDITION TIMING

Immediately following the SSPIF bit getting set, the

user may write the SSPBUF with the 7-bit address in

7-bit mode, or the default first address in 10-bit mode.

After the first eight bits are transmitted and an ACK is

received, the user may then transmit an additional eight

bits of address (10-bit mode) or eight bits of data (7-bit

mode).

A Repeated Start condition occurs when the RSEN bit

(SSPCON2<1>) is programmed high and the I²C mod-

ule is in the idle state. When the RSEN bit is set, the

SCL pin is asserted low. When the SCL pin is sampled

low, the baud rate generator is loaded with the contents

of SSPADD<6:0>, and begins counting. The SDA pin

is released (brought high) for one baud rate generator

count (T_BRG). When the baud rate generator times out,

if SDA is sampled high, the SCL pin will be de-asserted

(brought high). When SCL is sampled high the baud

rate generator is re-loaded with the contents of

SSPADD<6:0> and begins counting. SDA and SCL

must be sampled high for one T_BRG. This action is then

followed by assertion of the SDA pin (SDA is low) for

one T_BRGwhile SCL is high. Following this, the RSEN

bit in the SSPCON2 register will be automatically

cleared, and the baud rate generator is not reloaded,

leaving the SDA pin held low. As soon as a start con-

dition is detected on the SDA and SCL pins, the S bit

(SSPSTAT<3>) will be set. The SSPIF bit will not be set

until the baud rate generator has timed-out.

8.2.10.6 WCOL STATUS FLAG

If the user writes the SSPBUF when a Repeated Start

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

Note: Because queueing of events is not

allowed, writing of the lower 5 bits of

SSPCON2 is disabled until the Repeated

Start condition is complete.

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

Note 2: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes from low to

high.

• SCL goes low before SDA is asserted low. This

may indicate that another master is attempting

to transmit a data "1".

FIGURE 8-22: REPEAT START CONDITION WAVEFORM

Set S (SSPSTAT<3>)

Write to SSPCON2

occurs here.

SDA = 1,

SCL(no change)

SDA = 1,

SCL = 1

At completion of start bit,

hardware clear RSEN bit

and set SSPIF

T_BRG

1st Bit

SDA

Write to SSPBUF occurs here.

T_BRG

Falling edge of ninth clock

End of Xmit

SCL

T_BRG

Sr = Repeated Start

DS30275A-page 76

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PIC16C77X

FIGURE 8-23: REPEATED START CONDITION FLOWCHART (PAGE 1)

Start

Idle Mode,

SSPEN = 1,

SSPCON<3:0> = 1000

B

RSEN = 1

Force SCL = 0

No

SCL = 0?

Yes

Release SDA,

Load BRG with

SSPADD<6:0>

No

BRG

rollover?

Yes

Release SCL

(Clock Arbitration)

No

SCL = 1?

Yes

Bus Collision,

Set BCLIF,

Release SDA,

Clear RSEN

No

SDA = 1?

Yes

Load BRG with

SSPADD<6:0>

C

A

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 77

PIC16C77X

FIGURE 8-24: REPEATED START CONDITION FLOWCHART (PAGE 2)

B

C

A

Yes

No

BRG

rollover?

SDA = 0?

SCL = 1?

Yes

Reset BRG

Force SDA = 0,

Load BRG with

SSPADD<6:0>

Set S

No

BRG

rollover?

SCL = ’0’?

Yes

Force SCL = 0,

Reset BRG

Repeated Start

condition done,

Clear RSEN,

Set SSPIF.

DS30275A-page 78

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PIC16C77X

8.2.11 I²C MASTER MODE TRANSMISSION

8.2.11.7 BF STATUS FLAG

Transmission of a data byte, a 7-bit address, or either

half of a 10-bit address is accomplished by simply writ-

ing a value to SSPBUF register. This action will set the

buffer full flag (BF) and allow the baud rate generator to

begin counting and start the next transmission. Each

bit of address/data will be shifted out onto the SDA pin

after the falling edge of SCL is asserted (see data hold

time spec). SCL is held low for one baud rate gener-

ator roll over count (T_BRG). Data should be valid before

SCL is released high (see Data setup time spec).

When the SCL pin is released high, it is held that way

for T_BRG, the data on the SDA pin must remain stable

for that duration and some hold time after the next fall-

ing edge of SCL. After the eighth bit is shifted out (the

falling edge of the eighth clock), the BF flag is cleared

and the master releases SDA allowing the slave device

being addressed to respond with an ACK bit during the

ninth bit time, if an address match occurs or if data was

received properly. The status of ACK is read into the

AKDT on the falling edge of the ninth clock. If the mas-

ter receives an acknowledge, the acknowledge status

bit (AKSTAT) is cleared. If not, the bit is set. After the

ninth clock the SSPIF is set, and the master clock

(baud rate generator) is suspended until the next data

byte is loaded into the SSPBUF leaving SCL low and

SDA unchanged (Figure 8-26).

In transmit mode, the BF bit (SSPSTAT<0>) is set when

the CPU writes to SSPBUF and is cleared when all 8

bits are shifted out.

8.2.11.8 WCOL STATUS FLAG

If the user writes the SSPBUF when a transmit is

already in progress (i.e. SSPSR is still shifting out a

data byte), then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

WCOL must be cleared in software.

8.2.11.9 AKSTAT STATUS FLAG

In transmit mode, the AKSTAT bit (SSPCON2<6>) is

cleared when the slave has sent an acknowledge

(ACK = 0), and is set when the slave does not acknowl-

edge (ACK = 1). A slave sends an acknowledge when

it has recognized its address (including a general call),

or when the slave has properly received its data.

After the write to the SSPBUF, each bit of address will

be shifted out on the falling edge of SCL until all seven

address bits and the R/W bit are completed. On the fall-

ing edge of the eighth clock the master will de-assert

the SDA pin allowing the slave to respond with an

acknowledge. On the falling edge of the ninth clock the

master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the AKSTAT status bit (SSPCON2<6>). Fol-

lowing the falling edge of the ninth clock transmission

of the address, the SSPIF is set, the BF flag is cleared,

and the baud rate generator is turned off until another

write to the SSPBUF takes place, holding SCL low and

allowing SDA to float.

1999 Microchip Technology Inc.

Advance Information

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PIC16C77X

FIGURE 8-25: MASTER TRANSMIT FLOWCHART

Idle Mode

Write SSPBUF

Num_Clocks = 0,

BF = 1

Force SCL = 0

Release SDA so

slave can drive ACK,

Force BF = 0

Yes

Num_Clocks

= 8?

No

Load BRG with

SSPADD<6:0>,

start BRG count

Load BRG with

SSPADD<6:0>,

start BRG count,

SDA = Current Data bit

No

BRG

rollover?

BRG

No

rollover?

Yes

Force SCL = 1,

Stop BRG

Stop BRG,

Force SCL = 1

(Clock Arbitration)

No

(Clock Arbitration)

SCL = 1?

Yes

No

SCL = 1?

Yes

Read SDA and place into

AKSTAT bit (SSPCON2<6>)

Bus collision detected

No

SDA =

Data bit?

Set BCLIF, hold prescale off,

Clear XMIT enable

Load BRG with

SSPADD<6:0>,

count high time

Yes

Load BRG with

SSPADD<6:0>,

count SCL high time

No

Rollover?

Yes

No

SDA =

Data bit?

BRG

rollover?

Yes

SCL = 0?

Force SCL = 0,

Set SSPIF

Yes

Reset BRG

Num_Clocks

= Num_Clocks + 1

DS30275A-page 80

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

2

FIGURE 8-26: I C MASTER MODE TIMING (TRANSMISSION, 7 OR 10-BIT ADDRESS)

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 81

PIC16C77X

8.2.12 I²C MASTER MODE RECEPTION

8.2.12.10 BF STATUS FLAG

Master mode reception is enabled by programming the

receive enable bit, RCEN (SSPCON2<3>).

In receive operation, BF is set when an address or data

byte is loaded into SSPBUF from SSPSR. It is cleared

when SSPBUF is read.

Note: The SSP Module must be in an IDLE

STATE before the RCEN bit is set, or the

RCEN bit will be disregarded.

8.2.12.11 SSPOV STATUS FLAG

In receive operation, SSPOV is set when 8 bits are

received into the SSPSR, and the BF flag is already set

from a previous reception.

The baud rate generator begins counting, and on each

rollover, the state of the SCL pin changes (high to low/

low to high) and data is shifted into the SSPSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPSR are loaded into the SSPBUF, the BF flag is set,

the SSPIF is set, and the baud rate generator is sus-

pended from counting, holding SCL low. The SSP is

now in IDLE state, awaiting the next command. When

the buffer is read by the CPU, the BF flag is automati-

cally cleared. The user can then send an acknowledge

bit at the end of reception, by setting the acknowledge

sequence enable bit, AKEN (SSPCON2<4>).

8.2.12.12 WCOL STATUS FLAG

If the user writes the SSPBUF when a receive is

already in progress (i.e. SSPSR is still shifting in a data

byte), then WCOL is set and the contents of the buffer

are unchanged (the write doesn’t occur).

DS30275A-page 82

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PIC16C77X

FIGURE 8-27: MASTER RECEIVER FLOWCHART

Idle mode

RCEN = 1

Num_Clocks = 0,

Release SDA

Force SCL=0,

Load BRG w/

SSPADD<6:0>,

start count

BRG

No

rollover?

Yes

Release SCL

(Clock Arbitration)

No

SCL = 1?

Yes

Sample SDA,

Shift data into SSPSR

Load BRG with

SSPADD<6:0>,

start count.

No

BRG

rollover?

SCL = 0?

Yes

Num_Clocks

= Num_Clocks + 1

No

Num_Clocks

= 8?

Yes

Force SCL = 0,

Set SSPIF,

Set BF.

Move contents of SSPSR

into SSPBUF,

Clear RCEN.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 83

PIC16C77X

2

FIGURE 8-28: I C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)

DS30275A-page 84

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1999 Microchip Technology Inc.

PIC16C77X

8.2.13 ACKNOWLEDGE SEQUENCE TIMING

rate generator counts for T_BRG. The SCL pin is then

pulled low. Following this, the AKEN bit is automati-

cally cleared, the baud rate generator is turned off, and

the SSP module then goes into IDLE mode. (Figure 8-

29)

An acknowledge sequence is enabled by setting the

acknowledge

sequence

enable

bit,

AKEN

(SSPCON2<4>). When this bit is set, the SCL pin is

pulled low and the contents of the acknowledge data

bit is presented on the SDA pin. If the user wishes to

generate an acknowledge, then the AKDT bit should be

cleared. If not, the user should set the AKDT bit before

starting an acknowledge sequence. The baud rate

generator then counts for one rollover period (T_BRG),

and the SCL pin is de-asserted (pulled high). When the

SCL pin is sampled high (clock arbitration), the baud

8.2.13.13 WCOL STATUS FLAG

If the user writes the SSPBUF when an acknowledege

sequence is in progress, then WCOL is set and the

contents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 8-29: ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

Write to SSPCON2

AKEN automatically cleared

AKEN = 1, AKDT = 0

T_BRG

SDA

SCL

D0

ACK

8

9

SSPIF

Cleared in

software

Set SSPIF at the end

of receive

Cleared in

software

Set SSPIF at the end

of acknowledge sequence

Note: T_BRG= one baud rate generator period.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 85

PIC16C77X

FIGURE 8-30: ACKNOWLEDGE FLOWCHART

Idle mode

Set AKEN

Force SCL = 0

BRG

Yes

rollover?

No

SCL = 0?

Yes

Force SCL = 0,

Clear AKEN,

Set SSPIF

Yes

SCL = 0?

No

Reset BRG

Drive AKDT bit

(SSPCON2<5>)

onto SDA pin,

Load BRG with

SSPADD<6:0>,

start count.

No

AKDT = 1?

Yes

No

BRG

rollover?

Yes

SDA = 1?

No

Yes

Force SCL = 1

Bus collision detected,

Set BCLIF,

Release SCL,

Clear AKEN

No

SCL = 1?

Yes

(Clock Arbitration)

Load BRG with

SSPADD <6:0>,

start count.

DS30275A-page 86

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.2.14 STOP CONDITION TIMING

while SCL is high, the P bit (SSPSTAT<4>) is set. A

TBRG later the PEN bit is cleared and the SSPIF bit is

set (Figure 8-31).

A stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit PEN (SSPCON2<2>). At the end of a receive/trans-

mit the SCL line is held low after the falling edge of the

ninth clock. When the PEN bit is set, the master will

assert the SDA line low . When the SDA line is sam-

pled low, the baud rate generator is reloaded and

counts down to 0. When the baud rate generator times

out, the SCL pin will be brought high, and one T_BRG

(baud rate generator rollover count) later, the SDA pin

will be de-asserted. When the SDA pin is sampled high

Whenever the firmware decides to take control of the

bus, it will first determine if the bus is busy by checking

the S and P bits in the SSPSTAT register. If the bus is

busy, then the CPU can be interrupted (notified) when

a Stop bit is detected (i.e. bus is free).

8.2.14.14 WCOL STATUS FLAG

If the user writes the SSPBUF when a STOP sequence

is in progress, then WCOL is set and the contents of the

buffer are unchanged (the write doesn’t occur).

FIGURE 8-31: STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1 for T_BRG, followed by SDA = 1 for T_BRG

after SDA sampled high. P bit (SSPSTAT<4>) is set

Write to SSPCON2

Set PEN

PEN bit (SSPCON2<2>) is cleared by

hardware and the SSPIF bit is set

Falling edge of

9th clock

T_BRG

SCL

ACK

SDA

P

T_BRG

SCL brought high after T_BRG

SDA asserted low before rising edge of clock

to setup stop condition.

Note: T_BRG= one baud rate generator period.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 87

PIC16C77X

FIGURE 8-32: STOP CONDITION FLOWCHART

Idle Mode,

SSPEN = 1,

SSPCON<3:0> = 1000

PEN = 1

Start BRG

Force SDA = 0

SCL doesn’t change

No

BRG

rollover?

Yes

No

SDA = 0?

Release SDA,

Start BRG

Yes

Start BRG

No

BRG

rollover?

No

BRG

Yes

rollover?

Bus Collision detected,

Set BCLIF,

No

Yes

P bit Set?

Yes

Clear PEN

De-assert SCL,

SCL = 1

SDA going from

0 to 1 while SCL = 1

(Clock Arbitration)

Set SSPIF,

No

Stop Condition done

PEN cleared.

SCL = 1?

Yes

DS30275A-page 88

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

8.2.15 CLOCK ARBITRATION

8.2.16 SLEEP OPERATION

Clock arbitration occurs when the master, during any

receive, transmit, or repeated start/stop condition, de-

asserts the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the baud rate gen-

erator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and begins counting. This

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device (Figure 8-33).

While in sleep mode, the I²C module can receive

addresses or data, and when an address match or

complete byte transfer occurs wake the processor from

sleep ( if the SSP interrupt is enabled).

8.2.17 EFFECTS OF A RESET

A reset disables the SSP module and terminates the

current transfer.

FIGURE 8-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

BRG overflow,

Release SCL,

If SCL = 1 Load BRG with

SSPADD<6:0>, and start count

to measure high time interval

BRG overflow occurs,

Release SCL, Slave device holds SCL low.

SCL = 1 BRG starts counting

clock high interval.

SCL

SDA

SCL line sampled once every machine cycle (T • 4).

Hold off BRG until SCL is sampled high.

osc

T_BRG

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 89

PIC16C77X

8.2.18 MULTI -MASTER COMMUNICATION, BUS

COLLISION, AND BUS ARBITRATION

If a START, Repeated Start, STOP, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user

services the bus collision interrupt service routine, and

if the I²C bus is free, the user can resume communica-

tion by asserting a START condition.

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ’1’ on SDA by letting SDA float high and

another master asserts a ’0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ’1’ and the data sampled on the SDA pin = ’0’,

then a bus collision has taken place. The master will

set the Bus Collision Interrupt Flag, BCLIF and reset

the I²C port to its IDLE state. (Figure 8-34).

The Master will continue to monitor the SDA and SCL

pins, and if a STOP condition occurs, the SSPIF bit will

be set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the trans-

mitter left off when bus collision occurred.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision interrupt service routine, and if the I²C

bus is free, the user can resume communication by

asserting a START condition.

In multi-master mode, the interrupt generation on the

detection of start and stop conditions allows the deter-

mination of when the bus is free. Control of the I²C bus

can be taken when the P bit is set in the SSPSTAT reg-

ister, or the bus is idle and the S and P bits are cleared.

FIGURE 8-34: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high

data doesn’t match what is driven

by the master.

SDA line pulled low

by another source

Data changes

while SCL = 0

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt.

BCLIF

DS30275A-page 90

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1999 Microchip Technology Inc.

PIC16C77X

8.2.18.15 BUS COLLISION DURING A START

CONDITION

while SDA is high, a bus collision occurs, because it is

assumed that another master is attempting to drive a

data ’1’ during the START condition.

During a START condition, a bus collision occurs if:

If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 8-37). If however a ’1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The baud rate generator is then reloaded and

counts down to 0, and during this time, if the SCL pins

is sampled as ’0’, a bus collision does not occur. At the

end of the BRG count the SCL pin is asserted low.

a) SDA or SCL are sampled low at the beginning of

the START condition (Figure 8-35).

b) SCL is sampled low before SDA is asserted low.

(Figure 8-36).

During a START condition both the SDA and the SCL

pins are monitored.

If:

Note: The reason that bus collision is not a factor

during a START condition is that no two

bus masters can assert a START condition

at the exact same time. Therefore, one

master will always assert SDA before the

other. This condition does not cause a bus

collision because the two masters must be

allowed to arbitrate the first address follow-

ing the START condition, and if the

address is the same, arbitration must be

allowed to continue into the data portion,

REPEATED START, or STOP conditions.

the SDA pin is already low

or the SCL pin is already low,

then:

the START condition is aborted,

and the BCLIF flag is set,

and the SSP module is reset to its IDLE state

(Figure 8-35).

The START condition begins with the SDA and SCL

pins de-asserted. When the SDA pin is sampled high,

the baud rate generator is loaded from SSPADD<6:0>

and counts down to 0. If the SCL pin is sampled low

FIGURE 8-35: BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCLIF,

S bit and SSPIF set because

SDA = 0, SCL = 1

SDA

SCL

Set SEN, enable start

condition if SDA = 1, SCL=1

SEN cleared automatically because of bus collision.

SSP module reset into idle state.

SEN

SDA sampled low before

START condition.

Set BCLIF.

S bit and SSPIF set because

SDA = 0, SCL = 1

BCLIF

SSPIF and BCLIF are

cleared in software.

S

SSPIF

SSPIF and BCLIF are

cleared in software.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 91

PIC16C77X

FIGURE 8-36: BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

T_BRG

SDA

SCL

SEN

Set SEN, enable start

sequence if SDA = 1, SCL = 1

SCL = 0 before SDA = 0,

Bus collision occurs, Set BCLIF.

SCL = 0 before BRG time out,

Bus collision occurs, Set BCLIF.

BCLIF

Interrupts cleared

in software.

S

’0’

SSPIF

FIGURE 8-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION

SDA = 0, SCL = 1

Set S

T_BRG

Set SSPIF

Less than T_BRG

SDA pulled low by other master.

Reset BRG and assert SDA

SDA

SCL

S

SCL pulled low after BRG

Timeout

SEN

Set SEN, enable start

sequence if SDA = 1, SCL = 1

’0’

BCLIF

S

SSPIF

Interrupts cleared

in software.

SDA = 0, SCL = 1

Set SSPIF

DS30275A-page 92

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PIC16C77X

8.2.18.16 BUS COLLISION DURING A REPEATED

START CONDITION

however SDA is sampled high then the BRG is

reloaded and begins counting. If SDA goes from high

to low before the BRG times out, no bus collision

occurs, because no two masters can assert SDA at

exactly the same time.

During a Repeated Start condition, a bus collision

occurs if:

a) A low level is sampled on SDA when SCL goes

from low level to high level.

If, however, SCL goes from high to low before the BRG

times out and SDA has not already been asserted, then

a bus collision occurs. In this case, another master is

attempting to transmit a data ’1’ during the Repeated

Start condition.

b) SCL goes low before SDA is asserted low, indi-

cating that another master is attempting to trans-

mit a data ’1’.

When the user de-asserts SDA and the pin is allowed

to float high, the BRG is loaded with SSPADD<6:0>,

and counts down to 0. The SCL pin is then de-

asserted, and when sampled high, the SDA pin is sam-

pled. If SDA is low, a bus collision has occurred (i.e.

another master is attempting to transmit a data ’0’). If

If at the end of the BRG time out both SCL and SDA are

still high, the SDA pin is driven low, the BRG is

reloaded, and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is com-

plete (Figure 8-38).

FIGURE 8-38: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCLIF and release SDA and SCL

RSEN

BCLIF

Cleared in software

’0’

S

’0’

SSPIF

FIGURE 8-39: BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

BCLIF

RSEN

Set BCLIF. Release SDA and SCL

Interrupt cleared

in software

’0’

S

SSPIF

1999 Microchip Technology Inc.

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PIC16C77X

8.2.18.17 BUS COLLISION DURING A STOP

CONDITION

The STOP condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allow to float.

When the pin is sampled high (clock arbitration), the

baud rate generator is loaded with SSPADD<6:0> and

counts down to 0. After the BRG times out SDA is sam-

pled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ’0’. If the SCL pin is sampled low before

SDA is allowed to float high, a bus collision occurs.

This is another case of another master attempting to

drive a data ’0’ (Figure 8-40).

Bus collision occurs during a STOP condition if:

a) After the SDA pin has been de-asserted and

allowed to float high, SDA is sampled low after

the BRG has timed out.

b) After the SCL pin is de-asserted, SCL is sam-

pled low before SDA goes high.

FIGURE 8-40: BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

Set BCLIF

TBRG

SDA

SDA asserted low

SCL

PEN

BCLIF

P

’0’

SSPIF

FIGURE 8-41: BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high

Set BCLIF

Assert SDA

SCL

PEN

BCLIF

P

’0’

SSPIF

DS30275A-page 94

Advance Information

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PIC16C77X

Connection Considerations for I²C

Bus

example, with a supply voltage of VDD = 5V+10% and

VOL max = 0.4V at 3 mA, R_{p min}= (5.5-0.4)/0.003 =

1.7 kΩ. VDD as a function of R_pis shown in Figure 8-42.

The desired noise margin of 0.1VDD for the low level

limits the maximum value of R_s. Series resistors are

optional and used to improve ESD susceptibility.

8.3

For standard-mode I²C bus devices, the values of

resistors R_pR_sin Figure 8-42 depends on the following

parameters

• Supply voltage

• Bus capacitance

• Number of connected devices

(input current + leakage current).

The bus capacitance is the total capacitance of wire,

connections, and pins. This capacitance limits the max-

imum value of R_pdue to the specified rise time

(Figure 8-42).

The supply voltage limits the minimum value of resistor

R_pdue to the specified minimum sink current of 3 mA

at VOL max = 0.4V for the specified output stages. For

The SMP bit is the slew rate control enabled bit. This bit

is in the SSPSTAT register, and controls the slew rate

of the I/O pins when in I²C mode (master or slave).

FIGURE 8-42: SAMPLE DEVICE CONFIGURATION FOR I²C BUS

VDD + 10%

DEVICE

R_p

R_s

SDA

SCL

C_b=10 - 400 pF

2

NOTE: I C devices with input levels related to VDD must have one common supply

line to which the pull up resistor is also connected.

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PIC16C77X

NOTES:

DS30275A-page 96

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1999 Microchip Technology Inc.

PIC16C77X

The USART can be configured in the following modes:

9.0

ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to

be set in order to configure pins RC6/TX/CK and RC7/

RX/DT as the Universal Synchronous Asynchronous

Receiver Transmitter.

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial Com-

munications Interface or SCI). The USART can be con-

figured as a full duplex asynchronous system that can

communicate with peripheral devices such as CRT ter-

minals and personal computers, or it can be configured

as a half duplex synchronous system that can commu-

nicate with peripheral devices such as A/D or D/A inte-

grated circuits, Serial EEPROMs etc.

The USART module also has a multi-processor com-

munication capability using 9-bit address detection.

FIGURE 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

R = Readable bit

W = Writable bit

bit7

bit0

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit 7:

CSRC: Clock Source Select bit

Asynchronous mode

Don’t care

Synchronous mode

1 = Master mode (Clock generated internally from BRG)

0 = Slave mode (Clock from external source)

bit 6:

TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5:

TXEN: Transmit Enable bit

1 = Transmit enabled

0 = Transmit disabled

Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4:

SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3:

bit 2:

Unimplemented: Read as '0'

BRGH: High Baud Rate Select bit

Asynchronous mode

1 = High speed

0 = Low speed

Synchronous mode

Unused in this mode

bit 1:

bit 0:

TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

TX9D: 9th bit of transmit data. Can be parity bit.

1999 Microchip Technology Inc.

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PIC16C77X

FIGURE 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

R-0

R-x

CREN ADDEN

FERR

OERR

RX9D

R = Readable bit

W = Writable bit

bit7

bit0

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit 7:

bit 6:

bit 5:

SPEN: Serial Port Enable bit

1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)

0 = Serial port disabled

RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode

Don’t care

Synchronous mode - master

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - slave

Unused in this mode

bit 4:

CREN: Continuous Receive Enable bit

Asynchronous mode

1 = Enables continuous receive

0 = Disables continuous receive

Synchronous mode

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3:

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1)

1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set

0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2:

bit 1:

bit 0:

FERR: Framing Error bit

1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

OERR: Overrun Error bit

1 = Overrun error (Can be cleared by clearing bit CREN)

0 = No overrun error

RX9D: 9th bit of received data (Can be parity bit)

DS30275A-page 98

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

9.1

USART Baud Rate Generator (BRG)

EXAMPLE 9-1: CALCULATING BAUD RATE

ERROR

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In asynchronous

mode bit BRGH (TXSTA<2>) also controls the baud

rate. In synchronous mode bit BRGH is ignored.

Table 9-1 shows the formula for computation of the

baud rate for different USART modes which only apply

in master mode (internal clock).

Desired Baud rate = Fosc / (64 (X + 1))

9600

X

=

16000000 /(64 (X + 1))

25.042 = 25

Calculated Baud Rate=16000000 / (64 (25 + 1))

=

9615

Error

(Calculated Baud Rate - Desired Baud Rate)

Desired Baud Rate

=

(9615 - 9600) / 9600

0.16%

Given the desired baud rate and Fosc, the nearest inte-

ger value for the SPBRG register can be calculated

using the formula in Table 9-1. From this, the error in

baud rate can be determined.

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

because the FOSC/(16(X + 1)) equation can reduce the

baud rate error in some cases.

Example 9-1 shows the calculation of the baud rate

error for the following conditions:

FOSC = 16 MHz

Desired Baud Rate = 9600

BRGH = 0

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before output-

ting the new baud rate.

SYNC = 0

9.1.1

SAMPLING

The data on the RC7/RX/DT pin is sampled three times

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

TABLE 9-1

SYNC

BAUD RATE FORMULA

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

0

1

(Asynchronous) Baud Rate = FOSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1))

Baud Rate= FOSC/(16(X+1))

NA

X = value in SPBRG (0 to 255)

TABLE 9-2

REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on:

Value on all

other resets

Address Name

Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR,

BOR

0000 -010 0000 -010

98h

TXSTA CSRC TX9 TXEN SYNC

—

BRGH TRMT TX9D

0000 000x 0000 000x

0000 0000 0000 0000

18h

99h

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

SPBRG Baud Rate Generator Register

Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 99

PIC16C77X

TABLE 9-3

BAUD RATES FOR SYNCHRONOUS MODE

FOSC = 20 MHz

16 MHz

KBAUD

10 MHz

KBAUD

7.15909 MHz

KBAUD

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

ERROR (decimal)

SPBRG

value

ERROR (decimal)

SPBRG

value

ERROR (decimal)

%

KBAUD

ERROR (decimal)

0.3

1.2

2.4

NA

-

NA

-

NA

-

NA

-

9.6

NA

-

+1.73

+0.16

-1.96

0

-

NA

-

+0.16

-0.79

+2.56

0

-

9.766

19.23

75.76

96.15

312.5

500

+1.73

+0.16

-1.36

+0.16

+4.17

0

255

129

32

25

7

4

0

255

9.622

19.24

77.82

94.20

298.3

NA

+0.23

+1.32

-1.88

-0.57

-

185

92

22

18

5

-

0

255

19.2

76.8

96

300

500

HIGH

LOW

19.53

76.92

96.15

294.1

500

255

64

51

16

9

19.23

76.92

95.24

307.69

500

207

51

41

12

7

5000

19.53

-

0

255

4000

15.625

-

0

255

2500

9.766

-

1789.8

6.991

-

FOSC = 5.0688 MHz

SPBRG

4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

SPBRG

value

ERROR (decimal)

SPBRG

value KBAUD

ERROR (decimal)

SPBRG

value KBAUD

ERROR (decimal)

SPBRG

value

RATE KBAUD

(K)

%

value KBAUD

%

KBAUD

%

ERROR (decimal)

0.3

1.2

2.4

NA

-

0

-

NA

-

NA

9.622

19.04

74.57

99.43

298.3

NA

-

92

46

11

8

2

-

0

255

NA

1.202

2.404

9.615

19.24

83.34

NA

250

0.9766

-

207

103

25

12

2

-

0

0.303

1.170

NA

+1.14

-2.48

26

6

-

+0.16

-

9.6

131

65

15

12

3

-

0

255

9.615

19.231 +0.16

76.923 +0.16

1000

NA

+0.16

103

51

12

9

-

+0.23

-0.83

-2.90

+3.57

-0.57

-

19.2

76.8

96

300

500

HIGH

LOW

19.2

79.2

97.48

316.8

NA

0

+3.13

+1.54

+5.60

-

+8.51

+4.17

-

1267

4.950

100

3.906

0

255

894.9

3.496

-

8.192

0.032

0

255

TABLE 9-4

BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

FOSC = 20 MHz

16 MHz

10 MHz

7.15909 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)

0.3

1.2

2.4

NA

-

255

129

32

15

3

2

0

-

0

NA

1.202

2.404

9.615

19.23

83.33

NA

250

0.977

-

207

103

25

12

2

-

0

NA

1.202

2.404

9.766

19.53

78.13

NA

156.3

0.6104

-

129

64

15

7

1

-

NA

1.203

2.380

9.322

18.64

NA

111.9

0.437

-

92

46

11

5

-

1.221

2.404

9.469

19.53

78.13

104.2

312.5

NA

+1.73

+0.16

-1.36

+1.73

+8.51

+4.17

-

+0.16

+1.73

+0.23

-0.83

-2.90

-

9.6

19.2

76.8

96

300

500

HIGH

LOW

+8.51

+1.73

-

312.5

1.221

-

0

255

0

255

FOSC = 5.0688 MHz

4 MHz

3.579545 MHz

1 MHz

32.768 kHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)

0.3

1.2

2.4

0.31

1.2

2.4

+3.13

0

+3.13

-

255

65

32

7

3

0

-

0

0.3005 -0.17

207

51

25

-

0.301

1.190

2.432

9.322

18.64

NA

55.93

0.2185

+0.23

-0.83

+1.32

-2.90

185

46

22

5

2

-

0

0.300

1.202

2.232

NA

15.63

0.0610

+0.16

-6.99

51

12

6

-

0.256 -14.67

1

-

1.202

2.404

NA

+1.67

NA

-

9.6

9.9

-

NA

19.2

76.8

96

300

500

HIGH

LOW

19.8

79.2

NA

-2.90

NA

-

NA

79.2

0.3094

62.500

3.906

0

255

0

255

0.512

0.0020

0

255

DS30275A-page 100

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 9-5

BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 20 MHz

16 MHz

10 MHz

7.16 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)

9.6

9.615

19.230

37.878

56.818

+0.16

-1.36

0

129

64

32

21

10

4

9.615

19.230

38.461

58.823

111.111

250

+0.16

+2.12

-3.55

0

103

51

25

16

8

9.615

18.939

39.062

56.818

125

+0.16

-1.36

+1.7

-1.36

+8.51

-

64

32

15

10

4

9.520

19.454

37.286

55.930

111.860

NA

-0.83

+1.32

-2.90

-

46

22

11

7

3

-

19.2

38.4

57.6

115.2 113.636

250

625

250

625

3

-

NA

625

-

0

1

NA

-

0

NA

-

1250

0

NA

-

NA

-

NA

-

FOSC = 5.068 MHz

%

4 MHz

3.579 MHz

1 MHz

32.768 kHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

SPBRG

value

%

KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)

9.6

19.2

9.6

18.645

0

32

16

NA

1.202

-

9.727

18.643 -2.90

+1.32

22

11

8.928

20.833 +8.51

-6.99

6

2

NA

-

-2.94

207

+0.17

+0.13

+0.16

38.4

57.6

115.2

250

625

1250

39.6

52.8

105.6

NA

+3.12

-8.33

-

7

5

2

-

2.403

9.615

19.231 +0.16

NA

103

25

12

-

37.286 -2.90

55.930 -2.90

111.860 -2.90

223.721 -10.51

NA

5

3

1

0

-

31.25 -18.61

1

0

-

NA

-

62.5

NA

+8.51

-

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 101

PIC16C77X

(occurs in one TCY), the TXREG register is empty and

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicated the sta-

tus of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register. Sta-

tus bit TRMT is a read only bit which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

9.2

USART Asynchronous Mode

In this mode, the USART uses standard nonreturn-to-

zero (NRZ) format (one start bit, eight or nine data bits

and one stop bit). The most common data format is

8-bits. An on-chip dedicated 8-bit baud rate generator

can be used to derive standard baud rate frequencies

from the oscillator. The USART transmits and receives

the LSb first. The USART’s transmitter and receiver are

functionally independent but use the same data format

and baud rate. The baud rate generator produces a

clock either x16 or x64 of the bit shift rate, depending

on bit BRGH (TXSTA<2>). Parity is not supported by

the hardware, but can be implemented in software (and

stored as the ninth data bit). Asynchronous mode is

stopped during SLEEP.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

Note 2: Flag bit TXIF is set when enable bit TXEN

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

is set.

Steps to follow when setting up an Asynchronous

Transmission:

The USART Asynchronous module consists of the fol-

lowing important elements:

1. Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired,

set bit BRGH. (Section 9.1)

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit

TXIE.

9.2.1

USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in

Figure 9-3. The heart of the transmitter is the transmit

(serial) shift register (TSR). The shift register obtains its

data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

4. If 9-bit transmission is desired, then set transmit

bit TX9.

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts trans-

mission).

FIGURE 9-3: USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG register

TXIE

8

MSb

(8)

LSb

0

Pin Buffer

and Control

•

TSR register

RC6/TX/CK pin

Interrupt

TXEN

Baud Rate CLK

TRMT

SPEN

SPBRG

Baud Rate Generator

TX9

TX9D

DS30275A-page 102

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 9-4: ASYNCHRONOUS TRANSMISSION

Write to TXREG

Word 1

BRG output

(shift clock)

RC6/TX/CK (pin)

Start Bit

Bit 0

Bit 1

WORD 1

Bit 7/8

Stop Bit

TXIF bit

(Transmit buffer

reg. empty flag)

WORD 1

Transmit Shift Reg

TRMT bit

(Transmit shift

reg. empty flag)

FIGURE 9-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG

Word 2

Word 1

BRG output

(shift clock)

RC6/TX/CK (pin)

Start Bit

Bit 0

Bit 1

Bit 7/8

Bit 0

Stop Bit

TXIF bit

(interrupt reg. flag)

WORD 2

WORD 1

TRMT bit

(Transmit shift

reg. empty flag)

WORD 1

Transmit Shift Reg.

WORD 2

Transmit Shift Reg.

Note: This timing diagram shows two consecutive transmissions.

TABLE 9-6

REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on:

POR,

BOR

Value on

all other

Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0000 0000 0000 0000

0000 000x 0000 000x

0000 0000 0000 0000

0000 -010 0000 -010

0000 0000 0000 0000

0Ch

18h

19h

8Ch

PIR1

PSPIF

SPEN

ADIF RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

RCSTA

RX9 SREN CREN ADDEN FERR OERR RX9D

TXREG USART Transmit Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE

BRGH TRMT TX9D

98h

TXSTA

TX9 TXEN SYNC

—

99h

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 103

PIC16C77X

9.2.2

USART ASYNCHRONOUS RECEIVER

9.2.3

SETTING UP 9-BIT MODE WITH ADDRESS

DETECT

The receiver block diagram is shown in Figure 9-6. The

data is received on the RC7/RX/DT pin and drives the

data recovery block. The data recovery block is actually

a high speed shifter operating at x16 times the baud

rate, whereas the main receive serial shifter operates at

the bit rate or at FOSC.

Steps to follow when setting up an Asynchronous

Reception with Address Detect Enabled:

• Initialize the SPBRG register for the appropriate

baud rate. If a high speed baud rate is desired, set

bit BRGH.

The USART module has a special provision for multi-

processor communication. When the RX9 bit is set in

the RCSTA register, 9-bits are received and the ninth bit

is placed in the RX9D status bit of the RSTA register.

The port can be programmed such that when the stop

bit is received, the serial port interrupt will only be acti-

vated if the RX9D bit = 1. This feature is enabled by

setting the ADDEN bit RCSTA<3> in the RCSTA regis-

ter. This feature can be used in a multi-processor sys-

tem as follows:

• Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• If interrupts are desired, then set enable bit RCIE.

• Set bit RX9 to enable 9-bit reception.

• Set ADDEN to enable address detect.

• Enable the reception by setting enable bit CREN.

• Flag bit RCIF will be set when reception is com-

plete, and an interrupt will be generated if enable

bit RCIE was set.

• Read the RCSTA register to get the ninth bit and

determine if any error occurred during reception.

A master processor intends to transmit a block of data

to one of many slaves. It must first send out an address

byte that identifies the target slave. An address byte is

identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for

a data byte). If the ADDEN bit is set in the slave’s

RCSTA register, all data bytes will be ignored. How-

ever, if the ninth received bit is equal to a ‘1’, indicating

that the received byte is an address, the slave will be

interrupted and the contents of the RSR register will be

transferred into the receive buffer. This allows the slave

to be interrupted only by addresses, so that the slave

can examine the received byte to see if it is addressed.

The addressed slave will then clear its ADDEN bit and

prepare to receive data bytes from the master.

• Read the 8-bit received data by reading the

RCREG register, to determine if the device is

being addressed.

• If any error occurred, clear the error by clearing

enable bit CREN.

• If the device has been addressed, clear the

ADDEN bit to allow data bytes and address bytes

to be read into the receive buffer, and interrupt the

CPU.

When ADDEN is set, all data bytes are ignored. Fol-

lowing the STOP bit, the data will not be loaded into the

receive buffer, and no interrupt will occur. If another

byte is shifted into the RSR register, the previous data

byte will be lost.

The ADDEN bit will only take effect when the receiver

is configured in 9-bit mode.

The receiver block diagram is shown in Figure 9-6.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

DS30275A-page 104

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

FERR

OERR

CREN

SPBRG

÷ 64

RSR register

LSb

MSb

or

÷ 16

0

Baud Rate Generator

1

7

Stop (8)

Start

• • •

RC7/RX/DT

Pin Buffer

and Control

Data

Recovery

RX9

8

SPEN

RX9

Enable

Load of

ADDEN

Receive

Buffer

RX9

ADDEN

RSR<8>

8

RX9D

RCREG register

FIFO

8

RCIF

RCIE

Interrupt

Data Bus

FIGURE 9-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT

Start

bit

Start

bit

RC7/RX/DT (pin)

bit0

bit1

Stop

bit

bit8 Stop

bit

bit0

bit8

Load RSR

Read

WORD 1

RCREG

Bit8 = 0, Data Byte

Bit8 = 1, Address Byte

RCIF

Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer)

because ADDEN = 1.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 105

PIC16C77X

FIGURE 9-8: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST

Start

bit

Start

bit

RC7/RX/DT (pin)

bit0

bit1

Stop

bit

bit8 Stop

bit

bit0

bit8

Load RSR

Read

WORD 1

RCREG

Bit8 = 1, Address Byte

Bit8 = 0, Data Byte

RCIF

Note: This timing diagram shows an address byte followed by a data byte. The data byte is not read into the RCREG (receive buffer)

because ADEN was not updated and still = 0.

TABLE 9-7

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on:

POR,

BOR

Value on

all other

Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0Ch

18h

1Ah

8Ch

98h

99h

PIR1

PSPIF

SPEN

ADIF RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

RCSTA

RX9 SREN CREN ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

RCREG USART Receive Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

TXSTA

TX9 TXEN SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

0000 0000 0000 0000

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

DS30275A-page 106

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit TRMT (TXSTA<1>)

shows the status of the TSR register. TRMT is a read

only bit which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory so it is not

available to the user.

9.3

USART Synchronous Master Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner i.e. transmission and reception

do not occur at the same time. When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition enable bit SPEN (RCSTA<7>) is set in order to

configure the RC6/TX/CK and RC7/RX/DT I/O pins to

CK (clock) and DT (data) lines respectively. The Master

mode indicates that the processor transmits the master

clock on the CK line. The Master mode is entered by

setting bit CSRC (TXSTA<7>).

Steps to follow when setting up a Synchronous Master

Transmission:

9.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

1. Initialize the SPBRG register for the appropriate

baud rate (Section 9.1).

The USART transmitter block diagram is shown in

Figure 9-3. The heart of the transmitter is the transmit

(serial) shift register (TSR). The shift register obtains its

data from the read/write transmit buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one Tcycle), the TXREG is empty and inter-

rupt bit, TXIF (PIR1<4>) is set. The interrupt can be

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmission is desired, then set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the

TXREG register.

TABLE 9-8

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on:

POR,

BOR

Value on all

other Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0Ch

18h

19h

8Ch

98h

99h

PIR1

PSPIF

SPEN

ADIF RCIF TXIF

SSPIF CCP1IF TMR2IF TMR1IF

OERR RX9D

RCSTA

RX9 SREN CREN ADDEN FERR

TXREG USART Transmit Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

TX9 TXEN SYNC BRGH TRMT TX9D

TXSTA

—

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 107

PIC16C77X

FIGURE 9-9: SYNCHRONOUS TRANSMISSION

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4

Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4

RC7/RX/DT pin

RC6/TX/CK pin

Bit 0

Bit 1

Bit 2

Bit 7

Bit 0

Bit 1

WORD 2

Bit 7

WORD 1

Write to

TXREG reg

Write word1

Write word2

TXIF bit

(Interrupt flag)

TRMT

TRMT bit

’1’

Note: Sync master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.

’1’

TXEN bit

FIGURE 9-10: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin

RC6/TX/CK pin

bit0

bit2

bit1

bit6

bit7

Write to

TXREG reg

TXIF bit

TRMT bit

TXEN bit

DS30275A-page 108

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

9.3.2

USART SYNCHRONOUS MASTER

RECEPTION

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, then set enable bit

RCIE.

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN (RCSTA<5>)

or enable bit CREN (RCSTA<4>). Data is sampled on

the RC7/RX/DT pin on the falling edge of the clock. If

enable bit SREN is set, then only a single word is

received. If enable bit CREN is set, the reception is

continuous until CREN is cleared. If both bits are set

then CREN takes precedence.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous reception set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Steps to follow when setting up a Synchronous Master

Reception:

9. Read the 8-bit received data by reading the

RCREG register.

1. Initialize the SPBRG register for the appropriate

baud rate. (Section 9.1)

10. If any error occurred, clear the error by clearing

bit CREN.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN, and CSRC.

TABLE 9-9

REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on:

POR,

BOR

Value on all

other Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0Ch

18h

1Ah

8Ch

98h

99h

PIR1

PSPIF

SPEN

ADIF RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

RCSTA

RX9 SREN CREN ADDEN FERR OERR RX9D

RCREG USART Receive Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

TX9 TXEN SYNC BRGH TRMT TX9D

TXSTA

—

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2Q3 Q4Q1Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1 Q2Q3Q4Q1Q2 Q3 Q4 Q1 Q2Q3Q4Q1Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3Q4

RC7/RX/DT pin

RC6/TX/CK pin

bit0

bit1

bit2

bit3

bit4

bit5

bit6

bit7

Write to

bit SREN

SREN bit

CREN bit

'0'

RCIF bit

(interrupt)

Read

RXREG

Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 109

PIC16C77X

9.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

9.4

USART Synchronous Slave Mode

Synchronous slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK pin (instead of being supplied internally

in master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

The operation of the synchronous master and slave

modes is identical except in the case of the SLEEP

mode. Also, bit SREN is a don’t care in slave mode.

If receive is enabled, by setting bit CREN, prior to the

SLEEPinstruction, then a word may be received during

SLEEP. On completely receiving the word, the RSR

register will transfer the data to the RCREG register

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from SLEEP. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

9.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the synchronous master and slave

modes are identical except in the case of the SLEEP

mode.

Steps to follow when setting up a Synchronous Slave

Reception:

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

2. If interrupts are desired, then set enable bit

RCIE.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set.

3. If 9-bit reception is desired, then set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated, if

enable bit RCIE was set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP and if the global interrupt

is enabled, the program will branch to the inter-

rupt vector (0004h).

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Steps to follow when setting up a Synchronous Slave

Transmission:

7. Read the 8-bit received data by reading the

RCREG register.

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

8. If any error occurred, clear the error by clearing

bit CREN.

2. Clear bits CREN and SREN.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmission is desired, then set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the

TXREG register.

DS30275A-page 110

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 9-10

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on:

POR,

BOR

Value on all

other Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0Ch

18h

19h

8Ch

98h

99h

PIR1

PSPIF

SPEN

ADIF RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

RCSTA

RX9 SREN CREN ADDEN FERR OERR RX9D

TXREG USART Transmit Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE TXIE

TX9 TXEN SYNC

SSPIE CCP1IE TMR2IE TMR1IE

BRGH TRMT TX9D

TXSTA

—

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

TABLE 9-11

REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on:

POR,

BOR

Value on all

other Resets

Address Name

Bit 7

Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0000 000x

0000 0000

0000 -010

0000 0000

0Ch

18h

1Ah

8Ch

98h

99h

PIR1

PSPIF

SPEN

ADIF RCIF

TXIF

SSPIF CCP1IF TMR2IF TMR1IF

RCSTA

RX9 SREN CREN ADDEN FERR OERR RX9D

RCREG USART Receive Register

(1)

PIE1

PSPIE

CSRC

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

TX9 TXEN SYNC BRGH TRMT TX9D

TXSTA

—

SPBRG Baud Rate Generator Register

Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 111

PIC16C77X

NOTES:

DS30275A-page 112

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The source for the reference voltages comes from the

bandgap reference circuit. The bandgap circuit is ener-

gized anytime the reference voltage is required by the

other sub-modules, and is powered down when not in

use. The control registers for this module are LVDCON

and REFCON, as shown in Figure 10-1 and

Figure 10-2.

10.0 VOLTAGE REFERENCE

MODULE AND LOW-VOLTAGE

DETECT

The Voltage Reference module provides reference volt-

ages for the Brown-out Reset circuitry, the Low-voltage

Detect circuitry and the A/D converter.

FIGURE 10-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER

U-0

R-0

R/W-0

R/W-1

R/W-0

R/W-1

—

BGST

LVDEN

LV3

LV2

LV1

LV0

R = Readable bit

W = Writable bit

U = Unimplementedbit,

read as ‘0’

bit7

bit0

- n =Value at POR reset

bit 7-6: Unimplemented: Read as '0'

bit 5:

BGST: Bandgap Stable Status Flag bit

1 = Indicates that the bandgap voltage is stable, and LVD interrupt is reliable

0 = Indicates that the bandgap voltage is not stable, and LVD interrupt should not be enabled

bit 4:

LVDEN: Low-voltage Detect Power Enable bit

1 = Enables LVD, powers up bandgap circuit and reference generator

0 = Disables LVD, powers down bandgap circuit if unused by BOR or VRH/VRL

bit 3-0: LV3:LV0: Low Voltage Detection Limit bits ⁽¹⁾

1111= External analog input is used

1110= 4.5V

1101= 4.2V

1100= 4.0V

1011= 3.8V

1010= 3.6V

1001= 3.5V

1000= 3.3V

0111= 3.0V

0110= 2.8V

0101= 2.7V

0100= 2.5V

Note 1: These are the minimum trip points for the LVD, see Table 15-3 for the trip point tolerances. Selection

of an unused setting may result in an inadvertant interrupt.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 113

PIC16C77X

FIGURE 10-2: REFCON: VOLTAGE REFERENCE CONTROL REGISTER

R/W-0

VRHEN

bit7

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

VRLEN VRHOEN VRLOEN

R = Readable bit

W = Writable bit

U = Unimplemented

bit, read as ‘0’

- n =Value at POR

reset

bit0

bit 7:

bit 6:

bit 5:

bit 4:

VRHEN: Voltage Reference High Enable bit (VRH = 4.096V)

1 = Enabled, powers up reference generator

0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRL

VRLEN: Voltage Reference Low Enable bit (VRL = 2.048V)

1 = Enabled, powers up reference generator

0 = Disabled, powers down reference generator if unused by LVD, BOR, or VRH

VRHOEN: High Voltage Reference Output Enable bit

1 = Enabled, VRH analog reference is presented on RA3 if enabled (VRHEN = 1)

0 = Disabled, analog reference is used internally only

VRLOEN: Low Voltage Reference Output Enable bit

1 = Enabled, VRL analog reference is presented on RA2 if enabled (VRLEN = 1)

0 = Disabled, analog reference is used internally only

bit 3-0: Unimplemented: Read as '0’

Each voltage reference can source/sink up to 5 mA of

current.

10.1

Bandgap Voltage Reference

The bandgap module generates a stable voltage refer-

ence of 1.22V over a range of temperatures and device

supply voltages. This module is enabled anytime any of

the following are enabled:

Each reference, if enabled, can be presented on an

external pin by setting the VRHOEN (high reference

output enable) or VRLOEN (low reference output

enable) control bit. If the reference is not enabled, the

VRHOEN and VRLOEN bits will have no effect on the

corresponding pin. The device specific pin can then be

used as general purpose I/O.

• Brown-out Reset

• Low-voltage Detect

• Either of the internal analog references (VRH,

VRL)

Note: If VRH or VRL is enabled and the other ref-

erence (VRL or VRH), the BOR, and the

LVD modules are not enabled, the band-

gap will require a start-up time of no more

than 50 µs before the bandgap reference is

stable. Before using the internal VRH or

VRL reference, ensure that the bandgap

reference voltage is stable by monitoring

the BGST bit in the LVDCON register. The

voltage references will not be reliable until

the bandgap is stable as shown by BGST

being set.

Whenever the above are all disabled, the bandgap

module is disabled and draws no current.

10.2

Internal VREF for A/D Converter

The bandgap output voltage is used to generate two

stable references for the A/D converter module. These

references are enabled in software to provide the user

with the means to turn them on and off in order to min-

imize current consumption. Each reference can be indi-

vidually enabled.

The 4.096V reference (VRH) is enabled with control bit

VRHEN (REFCON<7>). When this bit is set, the gain

amplifier is enabled. After a specified start-up time a

stable reference of 4.096V is generated and can be

used by the A/D converter as the VRH input.

The 2.048V reference (VRL) is enabled by setting con-

trol bit VRLEN (REFCON<6>). When this bit is set, the

gain amplifier is enabled. After a specified start up time

a stable reference of 2.048V is generated and can be

used by the A/D converter as the VRL input.

DS30275A-page 114

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

control. This allows a user to power the module on

and off to periodically monitor the supply voltage, and

thus minimize total current consumption.

10.3

Low-voltage Detect (LVD)

This module is used to generate an interrupt when the

supply voltage falls below a specified “trip” voltage.

This module operates completely under software

FIGURE 10-3: BLOCK DIAGRAM OF LVD AND VOLTAGE REFERENCE CIRCUIT

VDD

LVDCON

REFCON

VDD

LVDEN

VRxEN

RB3/AN9/LVDIN

LVD

A/D Ref = 4.096V

BODEN

BGAP

A/D Ref = 2.048V

EN

The LVD module is enabled by setting the LVDEN bit in

the LVDCON register. The “trip point” voltage is the

minimum supply voltage level at which the device can

operate before the LVD module asserts an interrupt.

When the supply voltage is equal to or less than the trip

point, the module will generate an interrupt signal set-

ting interrupt flag bit LVDIF. If interrupt enable bit LVDIE

was set, then an interrupt is generated. The LVD inter-

rupt can wake the device from sleep. The "trip point"

voltage is software programmable to any one of 16 val-

ues, five of which are reserved (See Figure 10-1). The

trip point is selected by programming the LV3:LV0 bits

(LVDCON<3:0>).

If the bandgap reference voltage is previously unused

by either the brown-out circuitry or the voltage refer-

ence circuitry, then the bandgap circuit requires a time

to start-up and become stable before a low voltage con-

dition can be reliably detected. The low-voltage inter-

rupt flag is prevented from being set until the bandgap

has reached a stable reference voltage.

When the bandgap is stable the BGST (LVDCON<5>)

bit is set indicating that the low-voltage interrupt flag bit

is released to be set if VDD is equal to or less than the

LVD trip point.

10.3.1 EXTERNAL ANALOG VOLTAGE INPUT

Note: The LVDIF bit can not be cleared until the

supply voltage rises above the LVD trip

point. If interrupts are enabled, clear the

LVDIE bit once the first LVD interrupt

occurs to prevent reentering the interrupt

service routine immediately after exiting

the ISR.

The LVD module has an additional feature that allows

the user to supply the trip voltage to the module from

an external source. This mode is enabled when

LV3:LV0 = 1111. When these bits are set the compar-

ator input is multiplexed from an external input pin

(RB3/AN9/LVDIN.

Once the LV bits have been programmed for the speci-

fied trip voltage, the low-voltage detect circuitry is then

enabled by setting the LVDEN (LVDCON<4>) bit.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 115

PIC16C77X

NOTES:

DS30275A-page 116

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The A/D module has four registers. These registers

are:

11.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has six

inputs for the PIC16C773 and ten for the PIC16C774.

• A/D Result Register Low ADRESL

• A/D Result Register High ADRESH

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The analog-to-digital converter (A/D) allows conver-

sion of an analog input signal to a corresponding

12-bit digital number. The A/D module has up to 10

analog inputs, which are multiplexed into one sample

and hold. The output of the sample and hold is the

input into the converter, which generates the result via

successive approximation. The analog reference volt-

ages are software selectable to either the device’s

analog positive and negative supply voltages

(AVDD/AVSS), the voltage level on the VREF+ and

VREF- pins, or internal voltage references if available

(VRH, VRL).

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off and any

conversion is aborted.

11.1

Control Registers

The ADCON0 register, shown in Figure 11-1, controls

the operation of the A/D module. The ADCON1 regis-

ter, shown in Figure 11-2, configures the functions of

the port pins, the voltage reference configuration and

the result format. The port pins can be configured as

analog inputs or as digital I/O.

The A/D converter has a unique feature of being able to

operate while the device is in SLEEP mode. To operate

in sleep, the A/D conversion clock must be derived from

the A/D’s internal RC oscillator.

The combination of the ADRESH and ADRESL regis-

ters contain the result of the A/D conversion. The reg-

ister pair is referred to as the ADRES register. When

the A/D conversion is complete, the result is loaded

into ADRES, the GO/DONE bit (ADCON0<2>) is

cleared, and the A/D interrupt flag ADIF is set. The

block diagram of the A/D module is shown in

Figure 11-3.

FIGURE 11-1: ADCON0 REGISTER (ADDRESS 1Fh).

R/W-0

ADCS1

bit7

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

CHS3

R/W-0

ADON

bit 0

ADCS0

GO/DONE

R =

W =

Readable bit

Writable bit

- n = Value at POR reset

bit 7:6

ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = Fosc/2

01 = Fosc/8

10 = Fosc/32

11 = FRC (clock derived from an RC oscillator = 1 MHz max)

bit 5:3,1 CHS3:CHS0: Analog Channel Select bits

0000 = channel 00 (AN0)

0001 = channel 01 (AN1)

0010 = channel 02 (AN2)

0011 = channel 03 (AN3)

0100 = channel 04 (AN4) (Reserved on 28-pin devices, do not use)

0101 = channel 05 (AN5) (Reserved on 28-pin devices, do not use)

0110 = channel 06 (AN6) (Reserved on 28-pin devices, do not use)

0111 = channel 07 (AN7) (Reserved on 28-pin devices, do not use)

1000 = channel 08 (AN8)

1001 = channel 09 (AN9)

1010, 1011, 1100, 1101, 1110,1111 are reserved, do not select.

bit 2:

bit 0:

GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0 = A/D conversion completed/not in progress

ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter is shutoff and consumes no operating current

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 117

PIC16C77X

FIGURE 11-2: ADCON1 REGISTER (ADDRESS 9Fh)

R/W-0

ADFM

R/W-0

VCFG2

VCFG1

VCFG0 PCFG3 PCFG2 PCFG1 PCFG0

R =

W =

U =

Readable bit

Writable bit

Unimplemented bit, read as ‘0’

bit7

bit 0

- n = Value at POR reset

bit 7:

ADFM: A/D Result Format Select bit

1 = Right justified

0 = Left justified

bit 6:4

VCFG2:VCFG0: Voltage reference configuration bits

A/D VREFH

AVDD

A/D VREFL

AVSS

000

001

010

011

100

101

110

111

External VREF+

Internal VRH

External VREF+

Internal VRH

AVDD

External VREF-

Internal VRL

AVSS

External VREF-

Internal VRL

AVSS

AVDD

Internal VRL

(1)

bit 3:0

PCFG3:PCFG0: A/D Port Configuration bits

AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A

D

A = Analog input D= Digital I/O

Note 1: Selection of an unimplemented channel produces a result of 0xFFFFFF.

DS30275A-page 118

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The value that is in the ADRESH and ADRESL regis-

ters are not modified for a Power-on Reset. The

ADRESH and ADRESL registers will contain unknown

data after a Power-on Reset.

After the A/D module has been configured as desired.

and the analog input channels have their correspond-

ing TRIS bits selected for port inputs, the selected

channel must be acquired before conversion is

started. The A/D conversion cycle can be initiated by

setting the GO/DONE bit. The A/D conversion begins,

and lasts for 13TAD. The following steps should be fol-

lowed for performing an A/D conversion:

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To determine acquisition time, see Section 11.6.

After this acquisition time has elapsed the A/D conver-

sion can be started. The following steps should be fol-

lowed for doing an A/D conversion:

1. Configure the A/D module

• Configure analog pins / voltage reference /

and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if required)

• Clear ADIF bit

11.2

11.3

Configuring the A/D Module

Configuring Analog Port Pins

The ADCON1 and TRIS registers control the operation

of the A/D port pins. The port pins that are desired as

analog inputs must have their corresponding TRIS bit

set (input). If the TRIS bit is cleared (output), the digital

output level (VOH or VOL) will be converted.

• Set ADIE bit

• Set PEIE bit

• Set GIE bit

3. Wait the required acquisition time (3TAD)

4. Start conversion

The A/D operation is independent of the state of the

CHS3:CHS0 bits and the TRIS bits.

• Set GO/DONE bit (ADCON0)

Note 1: When reading the PORTA or PORTE reg-

ister, all pins configured as analog input

channels will read as cleared (a low level).

When reading the PORTB register, all

pins configured as analog input channels

will read as set (a high level). Pins config-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

configured input will not affect the conver-

sion accuracy.

5. Wait 13TAD until A/D conversion is complete, by

either:

• Polling for the GO/DONE bit to be cleared

OR

• Waiting for the A/D interrupt

6. Read A/D Result registers (ADRESH and

ADRESL), clear ADIF if required.

7. For next conversion, go to step 1, step 2 or step

3 as required.

Note 2: Analog levels on any pin that is defined as

a digital input (including the ANx pins),

may cause the input buffer to consume

current that is out of the devices specifica-

tion.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRESH and

ADRESL registers WILL be updated with the partially

completed A/D conversion value. That is, the ADRESH

and ADRESL registers WILL contain the value of the

current incomplete conversion.

11.3.1 CONFIGURING THE REFERENCE

VOLTAGES

Note: Do not set the ADON bit and the

GO/DONE bit in the same instruction.

Doing so will cause the GO/DONE bit to be

automatically cleared.

The VCFG bits in the ADCON1 register configure the

A/D module reference inputs. The reference high

input can come from an internal reference (VRH) or

(VRL), an external reference (VREF+), or AVDD. The

low reference input can come from an internal refer-

ence (VRL), an external reference (VREF-), or AVSS. If

an external reference is chosen for the reference high

or reference low inputs, the port pin that multiplexes

the incoming external references is configured as an

analog input, regardless of the values contained in the

A/D port configuration bits (PCFG3:PCFG0).

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 119

PIC16C77X

FIGURE 11-3: A/D BLOCK DIAGRAM

CHS3:CHS0

RB3/AN9

RB2/AN8

RE2/AN7

(1)

RE1/AN6

(1)

VAIN

RE0/AN5

RA5/AN4

(1)

(Input voltage)

RA3/AN3/VREF+/VRH

RA2/AN2/VREF-/VRL

RA1/AN1

AVDD

RA0/AN0

VREFH

VRH

VRL

(Reference

voltage)

VCFG2:VCFG0

A/D

Converter

VREFL

VRL

(Reference

voltage)

AVSS

VCFG2:VCFG0

Note 1: Not available on 28-pin devices.

DS30275A-page 120

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Note that these options are the same as those of the

8-bit A/D.

11.4

Selecting the A/D Conversion Clock

The A/D conversion cycle requires 13TAD: 1 TAD for set-

tling time, and 12 TAD for conversion. The source of the

A/D conversion clock is software selected. The four

possible options for TAD are:

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 µs. Table 11-1 shows the resultant TAD times

derived from the device operating frequencies and the

A/D clock source selected.

• 2 TOSC

• 8 TOSC

The ADIF bit is set on the rising edge of the 14th TAD.

The GO/DONE bit is cleared on the falling edge of the

14th TAD.

• 32 TOSC

• Internal RC oscillator

TABLE 11-1

TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)

Device Frequency

Operation

ADCS<1:0>

20 MHz

5 MHz

4 MHz

1.25 MHz

2 TOSC

8 TOSC

32 TOSC

RC

00

01

10

11

100 ns⁽²⁾

800 ns⁽²⁾

1.6 µs

400 ns⁽²⁾

500 ns⁽²⁾

1.6 µs

6.4 µs

24 µs⁽³⁾

2 - 6 µs^(1,4)

1.6 µs

2.0 µs

6.4 µs

2 - 6 µs^(1,4)

8.0 µs⁽³⁾

2 - 6 µs^(1,4)

Note 1: The RC source has a typical TAD time of 4 µs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the RC A/D conversion clock source is only recommended if the conver-

sion will be performed during sleep.

11.5

A/D Conversions

Figure 11-5 shows an example that performs an A/D

conversion. The port pins are configured as analog

inputs. The analog reference VREF+ is the device AVDD

and the analog reference VREF- is the device AVSS. The

A/D interrupt is enabled, and the A/D conversion clock

is TRC. The conversion is performed on the AN0 chan-

nel.

FIGURE 11-4: PERFORMING AN A/D CONVERSION

BCF

BSF

CLRF

BSF

BCF

PIR1, ADIF

STATUS, RP0

ADCON1

PIE1, ADIE

STATUS, RP0

0xC1

;Clear A/D Int Flag

;Select Page 1

;Configure A/D Inputs

;Enable A/D interrupt

;Select Page 0

;RC clock, A/D is on,

;Ch 0 is selected

;

;Enable Peripheral

;Enable All Interrupts

MOVLW

MOVWF

BSF

ADCON0

INTCON, PEIE

INTCON, GIE

;

; Ensure that the required sampling time for the

; selected input channel has lapsed. Then the

; conversion may be started.

BSF

ADCON0, GO

:

;Start A/D Conversion

;The ADIF bit will be

;set and the GO/DONE bit

;cleared upon completion-

;of the A/D conversion.

:

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 121

PIC16C77X

FIGURE 11-5: FLOWCHART OF A/D OPERATION

ADON = 0

Yes

ADON = 0?

No

Sample

Selected Channel

Yes

GO = 0?

No

Yes

Start of A/D

Conversion Delayed

1 Instruction Cycle

Finish Conversion

SLEEP

Instruction?

A/D Clock

= RC?

GO = 0

ADIF = 1

No

Yes

Abort Conversion

GO = 0

Wake-up

From Sleep?

Finish Conversion

SLEEP

Instruction?

Wait 2 TAD

GO = 0

ADIF = 1

ADIF = 0

No

SLEEP

Power down A/D

Finish Conversion

Stay in Sleep

Powerdown A/D

Wait 2 TAD

GO = 0

ADIF = 1

Wait 2 TAD

DS30275A-page 122

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD), see Figure 11-8. The maximum recom-

mended impedance for analog sources is 2.5 kΩ.

After the analog input channel is selected (changed)

this sampling must be done before the conversion can

be started.

11.6

A/D Sample Requirements

11.6.1 RECOMMENDED SOURCE IMPEDANCE

The maximum recommended impedance for ana-

log sources is 2.5 kΩ. This value is calculated based

on the maximum leakage current of the input pin. The

leakage current is 100 nA max., and the analog input

voltage cannot be vary by more than 1/4 LSb or

250 mV due to leakage. This places a requirement on

the input impedance of 250 µV/100 nA = 2.5 kΩ.

To calculate the minimum sampling time,

Equation 11-6 may be used. This equation assumes

that 1/4 LSb error is used (16384 steps for the A/D).

The 1/4 LSb error is the maximum error allowed for the

A/D to meet its specified resolution.

11.6.2 SAMPLING TIME CALCULATION

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 11-8. The

The CHOLD is assumed to be 25 pF for the 12-bit

A/D.

FIGURE 11-6: A/D SAMPLING TIME EQUATION

(-T^C/C (RIC +RSS + RS)

VHOLD =(VREF - VREF/16384) = (VREF) • (1 -e

) VREF(1 - 1/16384) = VREF • (1 -e

)

TC = -CHOLD (1kΩ + RSS + RS) In (1/16384)

Figure 11-7 shows the calculation of the minimum time

required to charge CHOLD. This calculation is based on

the following system assumptions:

CHOLD = 25 pF

RS = 2.5 kΩ

1/4 LSb error

VDD = 5V → RSS = 10 kΩ (worst case)

Temp (system Max.) = 50°C

Note 1:The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

2:The charge holding capacitor (CHOLD) is

not discharged after each conversion.

3:The maximum recommended impedance

for analog sources is 2.5 kΩ. This is

required to meet the pin leakage specifi-

cation.

4:After a conversion has completed, 2 TAD

time must be waited before sampling can

begin again. During this time the holding

capacitor is not connected to the selected

A/D input channel.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 123

PIC16C77X

FIGURE 11-7: CALCULATING THE MINIMUM REQUIRED SAMPLE TIME

TACQ =

Amplifier Settling Time

+ Holding Capacitor Charging Time

+Temperature Coefficient

†

TACQ =

5 µs

+ TC

+ [(Temp - 25°C)(0.05 µs/°C)] †

TC = + Holding Capacitor Charging Time

TC = (CHOLD) (RIC + RSS + RS) In (1/16384)

TC = -25 pF (1 kΩ +10 kΩ + 2.5 kΩ) In (1/16384)

TC = -25 pF (13.5 kΩ) In (1/16384)

TC = -0.338 (-9.704)µs

TC = 3.3µs

TACQ =

5 µs

+ 3.3 µs

+ [(50°C - 25°C)(0.05 µs / °C)]

TACQ =

8.3 µs + 1.25 µs

9.55 µs

† The temperature coefficient is only required for

temperatures > 25°C.

FIGURE 11-8: ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

Port Pin

Rs

SS

RIC ≤ 1k

RSS

CPIN

VA

ILEAKAGE

± 100 nA

CHOLD = 25 pF

VSS

5 pF

Legend CPIN

VT

= input capacitance

= threshold voltage

6V

5V

ILEAKAGE = leakage current at the pin due to

various junctions

VDD 4V

3V

2V

RIC

SS

= interconnect resistance

= sampling switch

CHOLD

= sample/hold capacitance (from DAC)

5 6 7 8 9 10 11

Sampling Switch

( kΩ )

DS30275A-page 124

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

11.7

Use of the CCP Trigger

11.9

Faster Conversion - Lower

Resolution Trade-off

An A/D conversion can be started by the “special event

trigger” of the CCP module. This requires that the

CCPnM<3:0> bits be programmed as 1011b and that

the A/D module is enabled (ADON is set). When the

trigger occurs, the GO/DONE bit will be set on Q2 to

start the A/D conversion and the Timer1 counter will

be reset to zero. Timer1 is reset to automatically

repeat the A/D conversion cycle, with minimal software

overhead (moving the ADRESH and ADRESL to the

desired location). The appropriate analog input chan-

nel must be selected before the “special event trigger”

sets the GO/DONE bit (starts a conversion cycle).

Not all applications require a result with 12-bits of res-

olution, but may instead require a faster conversion

time. The A/D module allows users to make the

trade-off of conversion speed to resolution. Regard-

less of the resolution required, the acquisition time is

the same. To speed up the conversion, the A/D mod-

ule may be halted by clearing the GO/DONE bit after

the desired number of bits in the result have been con-

verted. Once the GO/DONE bit has been cleared, all

of the remaining A/D result bits are ‘0’. The equation

to determine the time before the GO/DONE bit can be

switched is as follows:

If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the

A/D module, but will still reset the Timer1 counter.

Conversion time = N•TAD + 1TAD

Where: N = number of bits of resolution required,

and 1TAD is the amplifier settling time.

11.8

Effects of a RESET

Since TAD is based from the device oscillator, the user

must use some method (a timer, software loop, etc.) to

determine when the A/D GO/DONE bit may be

cleared. Table 11-2 shows a comparison of time

required for a conversion with 4-bits of resolution, ver-

sus the normal 12-bit resolution conversion. The

example is for devices operating at 20 MHz. The A/D

clock is programmed for 32 T^OSC.

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is aborted. The value that is in the

ADRESH and ADRESL registers are not modified.

The ADRESH and ADRESL registers will contain

unknown data after a Power-on Reset.

TABLE 11-2

4-BIT vs. 12-BIT

CONVERSION TIMES

Resolution

Freq.

(MHz)

4-bit

12-bit

Tosc

20 50 ns

20 1.6 µs

20 8 µs

50 ns

TAD = 32 Tosc

1TAD+N•TAD

1.6 µs

20.8 µs

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 125

PIC16C77X

Turning off the A/D places the A/D module in its lowest

current consumption state.

11.10 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be configured for RC

(ADCS1:ADCS0 = 11b). With the RC clock source

selected, when the GO/DONE bit is set the A/D module

waits one instruction cycle before starting the conver-

sion cycle. This allows the SLEEP instruction to be exe-

cuted, which eliminates all digital switching noise

during the sample and conversion. When the conver-

sion cycle is completed the GO/DONE bit is cleared,

and the result loaded into the ADRESH and ADRESL

registers. If the A/D interrupt is enabled, the device will

wake-up from SLEEP. If the A/D interrupt is not

enabled, the A/D module will then be turned off,

although the ADON bit will remain set.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be configured to

RC (ADCS1:ADCS0 = 11b).

11.11 Connection Considerations

Since the analog inputs employ ESD protection, they

have diodes to VDD and VSS. This requires that the

analog input must be between VDD and VSS. If the input

voltage exceeds this range by greater than 0.3V (either

direction), one of the diodes becomes forward biased

and it may damage the device if the input current spec-

ification is exceeded.

An external RC filter is sometimes added for anti-alias-

ing of the input signal. The R component should be

selected to ensure that the total source impedance is

kept under the 2.5 kΩ recommended specification. Any

external components connected (via hi-impedance) to

an analog input pin (capacitor, zener diode, etc.) should

have very little leakage current at the pin.

When the A/D clock source is another clock option (not

RC), a SLEEP instruction causes the present conver-

sion to be aborted and the A/D module is turned off,

though the ADON bit will remain set.

TABLE 11-3

SUMMARY OF A/D REGISTERS

Value on:

POR,

BOR

Value on all

other Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh,

10Bh,18Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000u

(1)

PIR1

PIE1

PSPIF

PSPIE

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF TMR1IF 0000 0000 0000 0000

TMR2IE TMR1IE 0000 0000 0000 0000

0Ch

8Ch

1Eh

9Eh

9Bh

1Fh

(1)

ADRESH A/D High Byte Result Register

ADRESL A/D Low Byte Result Register

REFCON VRHEN VRLEN VRHOEN

xxxx xxxx uuuu uuuu

VRLOEN

CHS1

—

0000---- 0000 ----

0000 0000 0000 0000

00000000 0000 0000

--0x 0000 --0u 0000

xxxx 11xx uuuu 11uu

---- -000 ---- -000

--11 1111 --11 1111

1111 1111 1111 1111

0000 -111 0000 -111

ADCON0

ADCON1

PORTA

PORTB

PORTE

TRISA

ADCS1

ADFM

—

ADCS0

VCFG2

—

CHS2

CHS0

PCFG3

GO/DONE

PCFG2

CHS3

PCFG1

ADON

PCFG0

9Fh

VCFG1

VCFG0

05h

PORTA5⁽²⁾PORTA Data Latch when written: PORTA<4:0> pins when read

06h

PORTB Data Latch when written: PORTB pins when read

09h⁽²⁾

85h

—

RE2

RE1

RE0

bit5⁽²⁾

PORTA Data Direction Register

86h

TRISB

PORTB Data Direction Register

IBF OBF IBOV

89h⁽²⁾

TRISE

PSPMODE

—

PORTE Data Direction Bits

Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used for A/D conversion.

Note 1: Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.

2: These bits/registers are not implemented on the 28-pin devices, read as ’0’.

DS30275A-page 126

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Some of the core features provided may not be neces-

sary to each application that a device may be used for.

The configuration word bits allow these features to be

configured/enabled/disabled as necessary. These fea-

tures include code protection, brown-out reset and its

trippoint, the power-up timer, the watchdog timer and

the devices oscillator mode. As can be seen in

Figure 12-1, some additional configuration word bits

have been provided for brown-out reset trippoint selec-

tion.

12.0 SPECIAL FEATURES OF THE

CPU

These PICmicro devices have a host of features

intended to maximize system reliability, minimize cost

through elimination of external components, provide

power saving operating modes and offer code protec-

tion. These are:

• Oscillator Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Low-voltage detection

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

These devices have a Watchdog Timer which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer necessary delays on power-up. One is

the Oscillator Start-up Timer (OST), intended to keep

the chip in reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a

fixed delay of 72 ms (nominal) on power-up type resets

only (POR, BOR), designed to keep the part in reset

while the power supply stabilizes. With these two timers

on-chip, most applications need no external reset cir-

cuitry.

SLEEP mode is designed to offer a very low current

power-down mode. The user can wake-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Several oscillator options are also

made available to allow the part to fit the application.

The RC oscillator option saves system cost while the

LP crystal option saves power. A set of configuration

bits are used to select various options.

Additional information on special features is available in

the PICmicro™ Mid-Range Reference Manual,

(DS33023).

12.1

Configuration Bits

The configuration bits can be programmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/configuration memory space (2000h -

3FFFh), which can be accessed only during program-

ming.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 127

PIC16C77X

FIGURE 12-1: CONFIGURATION WORD

CP1 CP0 BORV1 BORV0 CP1 CP0

bit13 12 11 10

-

BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0

bit0

Register: CONFIG

Address 2007h

9

8

7

6

5

4

3

2

1

(2)

bit 13-12: CP1:CP0: Code Protection bits

bit 9-8: 11 = Program memory code protection off

bit 5-4: 10 = 0800h-0FFFh code protected

01 = 0400h-0FFFh code protected

00 = 0000h-0FFFh code protected

(3)

bit 11-10: BORV1:BORV0: Brown-out Reset Voltage bits

11 = VBOR set to 2.5V

10 = VBOR set to 2.7V

01 = VBOR set to 4.2V

00 = VBOR set to 4.5V

bit 7:

bit 6:

Unimplemented, Read as ’1’

(1)

BODEN: Brown-out Reset Enable bit

1 = Brown-out Reset enabled

0 = Brown-out Reset disabled

(1)

bit 3:

bit 2:

PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

WDTE: Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

3: These are the minimum trip points for the BOR, see Table 15-4 for the trip point tolerances. Selection of an unused

setting may result in an inadvertant interrupt.

12.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

12.2

Oscillator Configurations

12.2.1

OSCILLATOR TYPES

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 12-2). The

PIC16C77X oscillator design requires the use of a par-

allel cut crystal. Use of a series cut crystal may give a

frequency out of the crystal manufacturers specifica-

tions.

The PIC16C77X can be operated in four different oscil-

lator modes. The user can program two configuration

bits (FOSC1 and FOSC0) to select one of these four

modes:

• LP

• XT

• HS

• RC

Low Power Crystal

Crystal/Resonator

A difference from the other mid-range devices may be

noted in that the device can be driven from an external

clock only when configured in HS mode (Figure 12-3).

High Speed Crystal/Resonator

Resistor/Capacitor

DS30275A-page 128

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 12-2: CRYSTAL/CERAMIC

RESONATOR OPERATION

(HS, XT OR LP

TABLE 12-2

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Crystal

Freq

Cap. Range

C1

Cap. Range

C2

OSC CONFIGURATION)

Osc Type

C1⁽¹⁾

OSC1

LP

32 kHz

200 kHz

1 MHz

33 pF

15 pF

33 pF

15 pF

To

internal

XT

HS

47-68 pF

15 pF

47-68 pF

15 pF

logic

XTAL

RS⁽²⁾

RF⁽³⁾

OSC2

4 MHz

15 pF

SLEEP

PIC16C77X

4 MHz

15 pF

C2⁽¹⁾

8 MHz

15-33 pF

20 MHz

Note1: See Table 12-1 and Table 12-2 for recom-

mended values of C1 and C2.

These values are for design guidance only. See

2: A series resistor (RS) may be required for

AT strip cut crystals.

notes at bottom of page.

Crystals Used

3: RF varies with the crystal chosen.

32 kHz

200 kHz

1 MHz

Epson C-001R32.768K-A

STD XTL 200.000KHz

ECS ECS-10-13-1

± 20 PPM

± 50 PPM

± 30 PPM

FIGURE 12-3: EXTERNAL CLOCK INPUT

OPERATION (HS OSC

4 MHz

ECS ECS-40-20-1

CONFIGURATION)

8 MHz

EPSON CA-301 8.000M-C

EPSON CA-301 20.000M-C

20 MHz

OSC1

OSC2

Clock from

ext. system

PIC16C77X

Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 12-1).

2: Higher capacitance increases the stability

of oscillator but also increases the start-up

time.

Open

TABLE 12-1

CERAMIC RESONATORS

3: Since each resonator/crystal has its own

characteristics, the user should consult the

resonator/crystal manufacturer for appropri-

ate values of external components.

4: Rs may be required in HS mode as well as

XT mode to avoid overdriving crystals with

low drive level specification.

Ranges Tested:

Mode

XT

Freq

OSC1

OSC2

455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS

8.0 MHz

16.0 MHz

10 - 68 pF

10 - 22 pF

10 - 68 pF

10 - 22 pF

These values are for design guidance only. See

notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG

4.0 MHz Murata Erie CSA4.00MG

8.0 MHz Murata Erie CSA8.00MT

16.0 MHz Murata Erie CSA16.00MX

± 0.5%

All resonators used did not have built-in capacitors.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 129

PIC16C77X

12.2.3 RC OSCILLATOR

For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the resis-

tor (REXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. These factors and the variation due to tol-

erances of external R and C components used need to

be taken into account for each application. Figure 12-4

shows how the R/C combination is connected to the

PIC16C77X.

FIGURE 12-4: RC OSCILLATOR MODE

VDD

Rext

Internal

OSC1

clock

Cext

PIC16C77X

VSS

OSC2/CLKOUT

Fosc/4

DS30275A-page 130

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Some registers are not affected in any reset condition.

Their status is unknown on a power-up reset and

unchanged in any other reset. Most other registers are

placed into an initialized state upon reset, however they

are not affected by a WDT reset during sleep because

this is considered a WDT Wakeup, which is viewed as

the resumption of normal operation.

12.3

Reset

The PIC16C77X devices have several different resets.

These resets are grouped into two classifications;

power-up and non-power-up. The power-up type resets

are the power-on and brown-out resets which assume

the device VDD was below its normal operating range

for the device’s configuration. The non-power up type

resets assume normal operating limits were main-

tained before/during and after the reset.

Several status bits have been provided to indicate

which reset occurred (see Table 12-4). See Table 12-6

for a full description of reset states of all registers.

• Power-on Reset (POR)

A simplified block diagram of the on-chip reset circuit is

shown in Figure 12-5.

• Brown-out Reset (BOR)

• MCLR reset during normal operation

• MCLR reset during SLEEP

• WDT Reset (during normal operation)

These devices have a MCLR noise filter in the MCLR

reset path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

FIGURE 12-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

SLEEP

WDT

Module

Time-out

Reset

VDD rise

detect

Power-on Reset

VDD

Brown-out

Reset

BODEN

S

R

OST/PWRT

OST

10-bit Ripple counter

Chip_Reset

Q

OSC1

(1)

On-chip

RC OSC

PWRT

10-bit Ripple counter

Enable PWRT

Enable OST

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 131

PIC16C77X

12.4

Power-On Reset (POR)

12.5

Power-up Timer (PWRT)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR pin

directly (or through a resistor) to VDD. This will elimi-

nate external RC components usually needed to create

a Power-on Reset. A maximum rise time for VDD is

specified. See Electrical Specifications for details. For

a slow rise time, see Figure 12-6.

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up type resets only. For a POR, the

PWRT is invoked when the POR pulse is generated.

For a BOR, the PWRT is invoked when the device exits

the reset condition (VDD rises above BOR trippoint).

The Power-up Timer operates on an internal RC oscil-

lator. The chip is kept in reset as long as the PWRT is

active. The PWRT’s time delay is designed to allow VDD

to rise to an acceptable level. A configuration bit is pro-

vided to enable/disable the PWRT for the POR only. For

a BOR the PWRT is always available regardless of the

configuration bit setting.

Two delay timers have been provided which hold the

device in reset after a POR (dependant upon device

configuration) so that all operational parameters have

been met prior to releasing to device to resume/begin

normal operation.

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature,...) must be met to ensure oper-

ation. If these conditions are not met, the device must

be held in reset until the operating conditions are met.

Brown-out Reset may be used to meet the startup con-

ditions, or if necessary an external POR circuit may be

implemented to delay end of reset for as long as

needed.

12.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over. This ensures that the crystal oscil-

lator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on a power-up type reset or a wake-up

from SLEEP.

FIGURE 12-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

12.7

Brown-Out Reset (BOR)

The Brown-out Reset module is used to generate a

reset when the supply voltage falls below a specified

trip voltage. The trip voltage is configurable to any one

of four voltages provided by the BORV1:BORV0 config-

uration word bits.

VDD

D

R

R1

MCLR

Configuration bit, BODEN, can disable (if clear/pro-

grammed) or enable (if set) the Brown-out Reset cir-

cuitry. If VDD falls below the specified trippoint for

greater than parameter #35 in the electrical specifica-

tions section, the brown-out situation will reset the chip.

A reset may not occur if VDD falls below the trippoint for

less than parameter #35. The chip will remain in Brown-

out Reset until VDD rises above BVDD. The Power-up

Timer will be invoked at that point and will keep the chip

in RESET an additional 72 ms. If VDD drops below

BVDD while the Power-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up

Timer will be re-initialized. Once VDD rises above

BVDD, the Power-up Timer will again begin a 72 ms

time delay. Even though the PWRT is always enabled

when brown-out is enabled, the PWRT configuration

word bit should be cleared (enabled) when brown-out is

enabled.

PIC16C77X

C

Note 1: External Power-on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

DS30275A-page 132

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Table 12-5 shows the reset conditions for some special

function registers, while Table 12-6 shows the reset

conditions for all the registers.

12.8

Time-out Sequence

On power-up the time-out sequence is as follows: First

PWRT time-out is invoked by the POR pulse. When the

PWRT delay expires the Oscillator Start-up Timer is

activated. The total time-out will vary based on oscilla-

tor configuration and the status of the PWRT. For exam-

ple, in RC mode with the PWRT disabled, there will be

no time-out at all. Figure 12-7, Figure 12-8, Figure 12-

9 and Figure 12-10 depict time-out sequences on

power-up.

12.9

Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON has two sta-

tus bits that provide indication of which power-up type

reset occurred.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is set

on a Power-on Reset. It must then be set by the user

and checked on subsequent resets to see if bit BOR

cleared, indicating a BOR occurred. However, if the

brown-out circuitry is disabled, the BOR bit is a "Don’t

Care" bit and is considered unknown upon a POR.

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then

bringing MCLR high will begin execution immediately

(Figure 12-9). This is useful for testing purposes or to

synchronize more than one PICmicro microcontroller

operating in parallel.

Bit1 is POR (Power-on Reset Status bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

TABLE 12-3

TIME-OUT IN VARIOUS SITUATIONS

Power-up

Wake-up from

Oscillator Configuration

Brown-out

SLEEP

PWRTE = 0

72 ms + 1024TOSC

72 ms

PWRTE = 1

XT, HS, LP

RC

1024TOSC

72 ms + 1024TOSC

1024TOSC

—

72 ms

—

TABLE 12-4

STATUS BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

0

1

x

0

1

0

x

1

0

u

1

x

0

1

0

u

0

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up

MCLR Reset during normal operation

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

TABLE 12-5

RESET CONDITION FOR SPECIAL REGISTERS

Program

Counter

STATUS

Register

PCON

Register

Condition

Power-on Reset

000h

0001 1xxx

000u uuuu

0001 0uuu

0000 1uuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---- --01

---- --uu

---- --u0

---- --uu

MCLR Reset during normal operation

MCLR Reset during SLEEP

WDT Reset

000h

WDT Wake-up

PC + 1

000h

Brown-out Reset

Interrupt wake-up from SLEEP

PC + 1⁽¹⁾

Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 133

PIC16C77X

TABLE 12-6

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

Wake-up via WDT or

Interrupt

W

773 774

xxxx xxxx

N/A

uuuu uuuu

N/A

uuuu uuuu

N/A

INDF

TMR0

PCL

xxxx xxxx

0000h

uuuu uuuu

0000h

uuuu uuuu

PC + 1⁽²⁾

000q quuu⁽³⁾

uuuu uuuu

--0u 0000

uuuu 11uu

uuuu uuuu

---- -000

---0 0000

0000 000u

uuuq quuu⁽³⁾

uuuu uuuu

--uu uuuu

uuuu uuuu

---- -uuu

---u uuuu

STATUS

773 774

0001 1xxx

FSR

773 774

xxxx xxxx

--0x 0000

xxxx 11xx

xxxx xxxx

---- -000

---0 0000

0000 000x

PORTA

PORTB

PORTC

PORTD

PORTE

PCLATH

INTCON

uuuu uuuu⁽¹⁾

ruuu uuuu⁽¹⁾

uuuu uuuu⁽¹⁾

PIR1

773 774

r000 0000

0000 0000

0--- 0--0

r000 0000

0000 0000

0--- 0--0

u--- u--u⁽¹⁾

uuuu uuuu

--uu uuuu

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

PIR2

TMR1L

773 774

xxxx xxxx

--00 0000

0000 0000

-000 0000

xxxx xxxx

0000 0000

xxxx xxxx

--00 0000

0000 000x

0000 0000

xxxx xxxx

--00 0000

xxxx xxxx

0000 0000

1111 1111

uuuu uuuu

--uu uuuu

0000 0000

-000 0000

uuuu uuuu

0000 0000

uuuu uuuu

--00 0000

0000 000x

0000 0000

uuuu uuuu

--00 0000

uuuu uuuu

0000 0000

1111 1111

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON0

OPTION_REG

Legend: u = unchanged,

x = unknown, -= unimplemented bit, read as ’0’, q= value depends

on condition

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the

interrupt vector (0004h).

3: See Table 12-5 for reset value for specific condition.

DS30275A-page 134

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 12-6

Register

INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

Wake-up via WDT or

Interrupt

773 774

---1 1111

--11 1111

1111 1111

0000 -111

r000 0000

0000 0000

0--- 0--0

---- --qq

1111 1111

0000 0000

0000 -010

0000 0000

0000 ----

--00 0101

xxxx xxxx

0000 000

---1 1111

--11 1111

1111 1111

0000 -111

r000 0000

0000 0000

0--- 0--0

---- --uu

1111 1111

0000 0000

0000 -010

0000 0000

0000 ----

--00 0101

uuuu uuuu

0000 0000

---u uuuu

--uu uuuu

uuuu uuuu

uuuu -uuu

ruuu uuuu

uuuu uuuu

u--- u--u

---- --uu

1111 1111

uuuu uuuu

uuuu -uuu

uuuu uuuu

uuuu ----

--uu uuuu

uuuu uuuu

TRISA

TRISB

TRISC

TRISD

TRISE

PIE1

PIE2

PCON

PR2

SSPADD

SSPSTAT

TXSTA

SPBRG

REFCON

LVDCON

ADRESL

ADCON1

Legend: u = unchanged,

x = unknown, -= unimplemented bit, read as ’0’, q= value depends

on condition

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the

interrupt vector (0004h).

3: See Table 12-5 for reset value for specific condition.

FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 135

PIC16C77X

FIGURE 12-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

OST TIME-OUT

TOST

INTERNAL RESET

FIGURE 12-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

FIGURE 12-10: SLOW RISE TIME (MCLR TIED TO VDD)

5V

1V

0V

VDD

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT

INTERNAL RESET

DS30275A-page 136

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The RB0/INT pin interrupt, the RB port change interrupt

and the TMR0 overflow interrupt flags are contained in

the INTCON register.

12.10 Interrupts

The PIC16C77X family has up to 14 sources of inter-

rupt. The interrupt control register (INTCON) records

individual interrupt requests in flag bits. It also has indi-

vidual and global interrupt enable bits.

The peripheral interrupt flags are contained in the spe-

cial function registers PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in special function reg-

ister INTCON.

Note: Individual interrupt flag bits are set regard-

less of the status of their corresponding

mask bit or the GIE bit.

A global interrupt enable bit, GIE (INTCON<7>)

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled, and an

interrupt’s flag bit and mask bit are set, the interrupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set

regardless of the status of the GIE bit. The GIE bit is

cleared on reset.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pushed onto the stack and the PC is loaded

with 0004h. Once in the interrupt service routine the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the same for one or two cycle instructions. Individual

interrupt flag bits are set regardless of the status of

their corresponding mask bit or the GIE bit

The “return from interrupt” instruction, RETFIE, exits

the interrupt routine as well as sets the GIE bit, which

re-enables interrupts.

FIGURE 12-11: INTERRUPT LOGIC

LVDIF

LVDIE

PSPIF

PSPIE

Wake-up (If in SLEEP mode)

ADIF

ADIE

T0IF

T0IE

RCIF

RCIE

INTF

INTE

Interrupt to CPU

TXIF

TXIE

RBIF

RBIE

SSPIF

SSPIE

PEIE

GIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

CCP2IF

CCP2IE

BCLIF

BCLIE

The following table shows which devices have which interrupts.

Device

T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF LVDIF

BCLIF CCP2IF

PIC16C773 Yes Yes Yes

PIC16C774 Yes Yes Yes

-

Yes

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 137

PIC16C77X

12.10.1 INT INTERRUPT

12.10.3 PORTB INTCON CHANGE

External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION_REG<6>) is set,

or falling, if the INTEDG bit is clear. When a valid edge

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 12.13 for details on SLEEP mode.

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 3.2)

12.11 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt, i.e., W register and STATUS

register. This will have to be implemented in software.

Example 12-1 stores and restores the W and STATUS

registers. The register, W_TEMP, must be defined in

each bank and must be defined at the same offset from

the bank base address (i.e., if W_TEMP is defined at

0x20 in bank 0, it must also be defined at 0xA0 in bank

1).

12.10.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 4.0)

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Stores the PCLATH register.

d) Executes the interrupt service routine code

(User-generated).

e) Restores the STATUS register (and bank select

bit).

f) Restores the W and PCLATH registers.

EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF

SWAPF

CLRF

MOVWF

MOVF

MOVWF

CLRF

BCF

W_TEMP

STATUS,W

STATUS

STATUS_TEMP

PCLATH, W

PCLATH_TEMP

PCLATH

STATUS, IRP

FSR, W

;Copy W to TEMP register, could be bank one or zero

;Swap status to be saved into W

;bank 0, regardless of current bank, Clears IRP,RP1,RP0

;Save status to bank zero STATUS_TEMP register

;Only required if using pages 1, 2 and/or 3

;Save PCLATH into W

;Page zero, regardless of current page

;Return to Bank 0

MOVF

MOVWF

:

;Copy FSR to W

;Copy FSR from W to FSR_TEMP

FSR_TEMP

:(ISR)

:

MOVF

MOVWF

SWAPF

PCLATH_TEMP, W

PCLATH

STATUS_TEMP,W

;Restore PCLATH

;Move W into PCLATH

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into STATUS register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS30275A-page 138

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

The WDT can be permanently disabled by clearing

configuration bit WDTE (Section 12.1).

12.12 Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC

oscillator which does not require any external compo-

nents. This RC oscillator is separate from the RC oscil-

lator of the OSC1/CLKIN pin. That means that the WDT

will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device has been stopped,

for example, by execution of a SLEEPinstruction.

WDT time-out period values may be found in the Elec-

trical Specifications section under parameter #31. Val-

ues for the WDT prescaler may be assigned using the

OPTION_REG register.

Note: The CLRWDTand SLEEPinstructions clear

the WDT and the postscaler, if assigned to

the WDT, and prevent it from timing out and

generating a device RESET condition.

During normal operation, a WDT time-out generates a

device RESET (Watchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The TO bit in the STATUS register

will be cleared upon a Watchdog Timer time-out.

.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT,

the prescaler count will be cleared, but the

prescaler assignment is not changed.

FIGURE 12-12: WATCHDOG TIMER BLOCK DIAGRAM

From TMR0 Clock Source

(Figure 4-2)

0

Postscaler

8

M

1

U

WDT Timer

X

8 - to - 1 MUX

PS2:PS0

PSA

WDT

Enable Bit

To TMR0 (Section 4-2)

0

1

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

FIGURE 12-13: SUMMARY OF WATCHDOG TIMER REGISTERS

Address

2007h

Name

Bit 7

(1)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

WDTE

PS2

Bit 1

FOSC1

PS1

Bit 0

FOSC0

PS0

BODEN⁽¹⁾

INTEDG

PWRTE⁽¹⁾

PSA

Config. bits

OPTION_REG

CP1

CP0

81h,181h

RBPU

T0CS T0SE

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Figure 12-1 for the full description of the configuration word bits.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 139

PIC16C77X

Other peripherals cannot generate interrupts since dur-

ing SLEEP, no on-chip clocks are present.

12.13 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOPafter the SLEEPinstruction.

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit (STATUS<3>) is cleared, the

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D, disable external clocks. Pull all I/O pins, that

are hi-impedance inputs, high or low externally to avoid

switching currents caused by floating inputs. The

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should be considered.

12.13.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

The MCLR pin must be at a logic high level (VIHMC).

12.13.1 WAKE-UP FROM SLEEP

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will com-

plete as a NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bits will not be cleared.

The device can wake up from SLEEP through one of

the following events:

• If the interrupt occurs during or after the execu-

tion of a SLEEPinstruction, the device will imme-

diately wake up from sleep. The SLEEPinstruction

will be completely executed before the wake-up.

Therefore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

1. External reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change, or some

Peripheral Interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEPis invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDTinstruc-

tion should be executed before a SLEEPinstruction.

The following peripheral interrupts can wake the device

from SLEEP:

1. PSP read or write.

2. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

3. CCP capture mode interrupt.

4. Special event trigger (Timer1 in asynchronous

mode using an external clock).

5. SSP (Start/Stop) bit detect interrupt.

6. SSP transmit or receive in slave mode (SPI/I²C).

7. USART RX or TX (synchronous slave mode).

8. A/D conversion (when A/D clock source is RC).

9. Low-voltage detect.

DS30275A-page 140

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 12-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

TOST(2)

INTF flag

(INTCON<1>)

Interrupt Latency

(Note 2)

GIE bit

(INTCON<7>)

Processor in

SLEEP

INSTRUCTION FLOW

PC

PC+1

PC+2

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = SLEEP

Inst(PC - 1)

fetched

Instruction

executed

Dummy cycle

SLEEP

Inst(PC + 1)

Inst(0004h)

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

12.14 Program Verification/Code Protection

12.16 In-Circuit Serial Programming

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purposes.

PIC16CXXX microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with two lines for clock and data, and three

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom firm-

ware to be programmed.

Note: Microchip does not recommend code pro-

tecting windowed devices.

12.15 ID Locations

Four memory locations (2000h - 2003h) are designated

as ID locations where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least significant bits of the ID

location are used.

For complete details of serial programming, please

refer to the In-Circuit Serial Programming (ICSP™)

Guide, (DS30277).

For ROM devices, these values are submitted along

with the ROM code.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 141

PIC16C77X

NOTES:

DS30275A-page 142

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Table 13-2 lists the instructions recognized by the

MPASM assembler.

13.0 INSTRUCTION SET SUMMARY

Each PIC16CXXX instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC16CXX instruction

set summary in Table 13-2 lists byte-oriented, bit-ori-

ented, and literal and control operations. Table 13-1

shows the opcode field descriptions.

Figure 13-1 shows the general formats that the instruc-

tions can have.

Note: To maintain upward compatibility with

future PIC16CXXX products, do not use

the OPTIONand TRISinstructions.

All examples use the following format to represent a

hexadecimal number:

For byte-oriented instructions, ’f’ represents a file reg-

ister designator and ’d’ represents a destination desig-

nator. The file register designator specifies which file

register is to be used by the instruction.

0xhh

where h signifies a hexadecimal digit.

The destination designator specifies where the result of

the operation is to be placed. If ’d’ is zero, the result is

placed in the W register. If ’d’ is one, the result is placed

in the file register specified in the instruction.

FIGURE 13-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

For bit-oriented instructions, ’b’ represents a bit field

designator which selects the number of the bit affected

by the operation, while ’f’ represents the number of the

file in which the bit is located.

OPCODE

d

f (FILE #)

d = 0 for destination W

d = 1 for destination f

f = 7-bit file register address

For literal and control operations, ’k’ represents an

eight or eleven bit constant or literal value.

Bit-oriented file register operations

13 10 9

b (BIT #)

TABLE 13-1

OPCODE FIELD

DESCRIPTIONS

7

6

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Field

Description

f

W

b

k

x

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Don’t care location (= 0 or 1)

Literal and control operations

General

13

8

7

0

The assembler will generate code with x = 0. It is the

recommended form of use for compatibility with all

Microchip software tools.

OPCODE

k (literal)

k = 8-bit immediate value

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

PC

TO

PD

Program Counter

Time-out bit

k (literal)

Power-down bit

The instruction set is highly orthogonal and is grouped

into three basic categories:

A description of each instruction is available in the

PICmicro™

(DS33023).

Mid-Range

Reference

Manual,

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle executed as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 µs. If a conditional test is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 143

PIC16C77X

TABLE 13-2

PIC16CXXX INSTRUCTION SET

Mnemonic,

Operands

Description

Cycles

14-Bit Opcode

Status

Affected

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

f, d Add W and f

f, d AND W with f

1

1(2)

1

1(2)

1

00

0111 dfff ffff C,DC,Z

1,2

2

0101 dfff ffff

0001 lfff ffff

0001 0xxx xxxx

1001 dfff ffff

0011 dfff ffff

1011 dfff ffff

1010 dfff ffff

1111 dfff ffff

0100 dfff ffff

1000 dfff ffff

0000 lfff ffff

0000 0xx0 0000

1101 dfff ffff

1100 dfff ffff

Z

f

-

Clear f

Clear W

f, d Complement f

f, d Decrement f

f, d Decrement f, Skip if 0

f, d Increment f

f, d Increment f, Skip if 0

f, d Inclusive OR W with f

f, d Move f

1,2

1,2,3

1,2

1,2,3

1,2

DECFSZ

INCF

Z

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

Z

1,2

f

-

Move W to f

No Operation

f, d Rotate Left f through Carry

f, d Rotate Right f through Carry

f, d Subtract W from f

f, d Swap nibbles in f

f, d Exclusive OR W with f

C

1,2

0010 dfff ffff C,DC,Z

1110 dfff ffff

0110 dfff ffff Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b Bit Clear f

f, b Bit Set f

f, b Bit Test f, Skip if Clear

f, b Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

1,2

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C,DC,Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

Z

00 0000 0110 0100 TO,PD

10 1kkk kkkk kkkk

Inclusive OR literal with W

Move literal to W

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

Z

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

00 0000 0110 0011 TO,PD

11 110x kkkk kkkk C,DC,Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ’0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

DS30275A-page 144

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

14.3

ICEPIC: Low-Cost PICmicro

In-Circuit Emulator

14.0 DEVELOPMENT SUPPORT

14.1

Development Tools

ICEPIC is a low-cost in-circuit emulator solution for the

Microchip PIC12CXXX, PIC16C5X and PIC16CXXX

families of 8-bit OTP microcontrollers.

The PICmicro microcontrollers are supported with a

full range of hardware and software development tools:

• MPLAB -ICE Real-Time In-Circuit Emulator

ICEPIC is designed to operate on PC-compatible

machines ranging from 386 through Pentium based

machines under Windows 3.x, Windows 95, or Win-

dows NT environment. ICEPIC features real time, non-

intrusive emulation.

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX

In-Circuit Emulator

• PRO MATE II Universal Programmer

• PICSTART Plus Entry-Level Prototype

Programmer

14.4

PRO MATE II: Universal Programmer

• SIMICE

The PRO MATE II Universal Programmer is a full-fea-

tured programmer capable of operating in stand-alone

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE II can read, verify or pro-

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System

(fuzzyTECH −MP)

• KEELOQ^®Evaluation Kits and Programmer

14.2

MPLAB-ICE: High Performance

Universal In-Circuit Emulator with

MPLAB IDE

gram

PIC12CXXX,

PIC14C000,

PIC16C5X,

PIC16CXXX and PIC17CXX devices. It can also set

configuration and code-protect bits in this mode.

14.5

PICSTART Plus Entry Level

Development System

The MPLAB-ICE Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). MPLAB-ICE is sup-

plied with the MPLAB Integrated Development Environ-

ment (IDE), which allows editing, “make” and

download, and source debugging from a single envi-

ronment.

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efficient. PICSTART Plus is not

recommended for production programming.

Interchangeable processor modules allow the system

to be easily reconfigured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support all new Microchip micro-

controllers.

PICSTART Plus supports all PIC12CXXX, PIC14C000,

PIC16C5X, PIC16CXXX and PIC17CXX devices with

up to 40 pins. Larger pin count devices such as the

PIC16C923, PIC16C924 and PIC17C756 may be sup-

ported with an adapter socket. PICSTART Plus is CE

compliant.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC compatible 386 (and higher)

machine platform and Microsoft Windows 3.x or

Windows 95 environment were chosen to best make

these features available to you, the end user.

MPLAB-ICE

is

available

in

two

versions.

MPLAB-ICE 1000 is a basic, low-cost emulator system

with simple trace capabilities. It shares processor mod-

ules with the MPLAB-ICE 2000. This is a full-featured

emulator system with enhanced trace, trigger, and data

monitoring features. Both systems will operate across

the entire operating speed reange of the PICmicro

MCU.

1999 Microchip Technology Inc.

DS30275A-page 145

PIC16C77X

14.6

SIMICE Entry-Level Hardware

Simulator

14.8

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB™-SIM. Both SIM-

ICE and MPLAB-SIM run under Microchip Technol-

ogy’s MPLAB Integrated Development Environment

(IDE) software. Specifically, SIMICE provides hardware

simulation for Microchip’s PIC12C5XX, PIC12CE5XX,

and PIC16C5X families of PICmicro 8-bit microcontrol-

lers. SIMICE works in conjunction with MPLAB-SIM to

provide non-real-time I/O port emulation. SIMICE

enables a developer to run simulator code for driving

the target system. In addition, the target system can

provide input to the simulator code. This capability

allows for simple and interactive debugging without

having to manually generate MPLAB-SIM stimulus

files. SIMICE is a valuable debugging tool for entry-

level system development.

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTART-Plus, and easily test firmware.

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test firmware. Additional prototype

area has been provided to the user for adding addi-

tional hardware and connecting it to the microcontroller

socket(s). Some of the features include a RS-232 inter-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of the I²C bus and separate headers for connec-

tion to an LCD module and a keypad.

14.7

PICDEM-1 Low-Cost PICmicro

Demonstration Board

14.9

PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and download the

firmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microcontrollers with a LCD Module. All the neces-

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDEM-3 board, on a PRO MATE II program-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Additional prototype area has been provided to

the user for adding hardware and connecting it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a keypad. Also provided on the PICDEM-3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week. The PICDEM-3 provides an addi-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplexed LCD signals on a PC. A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

DS30275A-page 146

1999 Microchip Technology Inc.

PIC16C77X

14.10 MPLAB Integrated Development

Environment Software

14.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PICmicro series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The input/

output radix can be set by the user and the execution

can be performed in; single step, execute until break, or

in a trace mode.

The MPLAB IDE Software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a windows based application

which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPASM. The Software Simulator

offers the low cost flexibility to develop and debug code

outside of the laboratory environment making it an

excellent multi-project software development tool.

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

14.13 MPLAB-C17 Compiler

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

project information)

• Debug using:

- source files

The MPLAB-C17 Code Development System is a

complete ANSI ‘C’ compiler and integrated develop-

ment environment for Microchip’s PIC17CXXX family of

microcontrollers. The compiler provides powerful inte-

gration capabilities and ease of use not found with

other compilers.

- absolute listing file

For easier source level debugging, the compiler pro-

vides symbol information that is compatible with the

MPLAB IDE memory display.

The ability to use MPLAB with Microchip’s simulator

allows a consistent platform and the ability to easily

switch from the low cost simulator to the full featured

emulator with minimal retraining due to development

tools.

14.14 Fuzzy Logic Development System

(fuzzyTECH-MP)

14.11 Assembler (MPASM)

fuzzyTECH-MP fuzzy logic development tool is avail-

able in two versions - a low cost introductory version,

MP Explorer, for designers to gain a comprehensive

working knowledge of fuzzy logic system design; and a

full-featured version, fuzzyTECH-MP, Edition for imple-

menting more complex systems.

The MPASM Universal Macro Assembler is a PC-

hosted symbolic assembler. It supports all microcon-

troller series including the PIC12C5XX, PIC14000,

PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, condi-

tional assembly, and several source and listing formats.

It generates various object code formats to support

Microchip's development tools as well as third party

programmers.

Both versions include Microchip’s fuzzyLAB demon-

stration board for hands-on experience with fuzzy logic

systems implementation.

14.15 SEEVAL Evaluation and

Programming System

MPASM allows full symbolic debugging from MPLAB-

ICE, Microchip’s Universal Emulator System.

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analysis and reliability calculations. The total kit can

significantly reduce time-to-market and result in an

optimized system.

MPASM has the following features to assist in develop-

ing software for specific use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the files (Object, Listing, Symbol, and

special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

MPASM provides a rich directive language to support

programming of the PICmicro. Directives are helpful in

making the development of your assemble source code

shorter and more maintainable.

1999 Microchip Technology Inc.

DS30275A-page 147

PIC16C77X

14.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microchips HCS Secure Data Products. The HCS eval-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

DS30275A-page 148

1999 Microchip Technology Inc.

PIC16C77X

TABLE 14-1

DEVELOPMENT TOOLS FROM MICROCHIP

y

z

u

s t

o d u P c r o t r u l m a E

s l o o

a r e f t T w S o

s e r

r a g m o r m P

s

B o o a r d D e m

1999 Microchip Technology Inc.

DS30275A-page 149

PIC16C77X

NOTES:

DS30275A-page 150

1999 Microchip Technology Inc.

PIC16C77X

15.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias.................................................................................................................-55 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4).......................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V

Voltage on MCLR with respect to VSS (Note 2).................................................................................................0 to +8.5V

Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V

Total power dissipation (Note 1)................................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin ..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3)....................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3) ..............................................200 mA

Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA

Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,

a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling

this pin directly to VSS.

Note 3: PORTD and PORTE are not implemented on the PIC16C773.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

TABLE 15-1

CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

PIC16C773-04

PIC16C774-04

PIC16C773-20

PIC16C774-20

PIC16LC773-04

PIC16LC774-04

OSC

JW Devices

VDD: 4.0V to 5.5V

VDD: 4.5V to 5.5V

VDD: 2.5V to 5.5V

VDD: 4.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 16 µA max. at 4V

Freq: 4 MHz max.

IDD: 2.7 mA typ. at 5.5V

IPD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

IDD: 3.8 mA max. at 3.0V

IPD: 5 µA max. at 3V

Freq: 4 MHz max.

IDD: 5 mA max. at 5.5V

IPD: 16 µA max. at 4V

Freq: 4 MHz max.

RC

XT

VDD: 4.0V to 5.5V

VDD: 4.5V to 5.5V

VDD: 2.5V to 5.5V

VDD: 4.0V to 5.5V

IDD: 5 mA max. at 5.5V

IPD: 16 µA max. at 4V

Freq: 4 MHz max.

IDD: 2.7 mA typ. at 5.5V

IPD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

IDD: 3.8 mA max. at 3.0V

IPD: 5 µA max. at 3V

Freq: 4 MHz max.

IDD: 5 mA max. at 5.5V

IPD: 16 µA max. at 4V

Freq: 4 MHz max.

VDD: 4.5V to 5.5V

IDD: 13.5 mA typ. at 5.5V IDD: 20 mA max. at 5.5V

IDD: 20 mA max. at 5.5V

IPD: 1.5 µA typ. at 4.5V

Freq: 20 MHz max.

HS

LP

Not tested for functionality

IPD: 1.5 µA typ. at 4.5V

Freq: 4 MHz max.

Freq: 20 MHz max.

VDD: 4.0V to 5.5V

IDD: 52.5 µA typ. at 32

kHz, 4.0V

VDD: 2.5V to 5.5V

IDD: 48 µA max. at 32 kHz,

3.0V

VDD: 2.5V to 5.5V

IDD: 48 µA max. at 32 kHz,

3.0V

Not tested for functionality

IPD: 0.9 µA typ. at 4.0V

Freq: 200 kHz max.

IPD: 5.0 µA max. at 3.0V

Freq: 200 kHz max.

IPD: 5.0 µA max. at 3.0V

Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.

It is recommended that the user select the device type that ensures the specifications required.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 151

PIC16C77X

15.1

DC Characteristics: PIC16C77X (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C

≤ TA ≤ +70°C for commercial

Param

No.

Characteristic

Supply Voltage

Sym

Min Typ† Max Units

Conditions

D001

D001A

VDD

4.0

4.5

—

5.5

V

XT, RC and LP osc configuration

HS osc configuration

D002* RAM Data Retention

Voltage (Note 1)

VDR

—

1.5

—

V

D003

VDD start voltage to

ensure internal Power-on

Reset signal

VPOR

—

VSS

—

V

See section on Power-on Reset for details

D004* VDD rise rate to ensure

internal Power-on Reset

signal

SVDD

IDD

0.05

—

5

V/ms See section on Power-on Reset for details.

PWRT enabled

D010

Supply Current (Note 2)

—

2.7

mA XT, RC osc configuration

FOSC = 4 MHz, VDD = 5.5V (Note 4)

D013

D020

13.5 30

mA HS osc configuration

FOSC = 20 MHz, VDD = 5.5V

Power-down Current

IPD

—

1.5

16

19

µA VDD = 4.0V, -0°C to +70°C

µA VDD = 4.0V, -40°C to +85°C

D020A (Note 3)

Module Differential Cur-

rent (Note 5)

D021

Watchdog Timer

∆IWDT

—

6.0

20

—

µA VDD = 4.0V

D023* Brown-out Reset Current ∆IBOR

TBD 200

µA BOR enabled, VDD = 5.0V

(Note 5)

D023B* Bandgap voltage

generator

6

—

40µA TBD µA

∆IBG

D025* Timer1 oscillator

∆IT1OSC

5

9

µA VDD = 4.0V

D026* A/D Converter

∆IAD

300

—

µA VDD = 5.5V, A/D on, not converting

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is mea-

sured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when the peripheral is enabled. This current should be

added to the base (IPD or IDD) current.

6: The bandgap voltate reference provides 1.22V to the VRL, VRH, LVD and BOR circuits. When calculating cur-

rent consumption use the following formula: ∆IVRL + ∆IVRH + ∆ILVD + ∆IBOR + ∆IBG. Any of the ∆IVRL, ∆IVRH,

∆ILVD or ∆IBOR can be 0.

DS30275A-page 152

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

15.2

DC Characteristics:PIC16LC77X-04 (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

DC CHARACTERISTICS

0°C

≤ TA ≤ +70°C for commercial

Param

No.

Characteristic

Supply Voltage

Sym

Min Typ† Max Units

Conditions

—

D001

VDD

2.5

5.5

—

V

LP, XT, RC osc configuration (DC - 4

MHz)

—

D002* RAM Data Retention

Voltage (Note 1)

VDR

1.5

VSS

D003

VDD start voltage to

ensure internal Power-on

Reset signal

VPOR

—

See section on Power-on Reset for

details

D004* VDD rise rate to ensure

internal Power-on Reset

signal

SVDD

IDD

0.05

—

V/ms See section on Power-on Reset for

details. PWRT enabled

D010

Supply Current (Note 2)

—

2.0

3.8

mA XT, RC osc configuration

FOSC = 4 MHz, VDD = 3.0V (Note 4)

D010A

22.5 48

µA LP osc configuration

FOSC = 32 kHz, VDD = 3.0V, WDT dis-

abled

D020

D020A (Note 3)

Power-down Current

IPD

—

0.9

5

µA VDD = 3.0V, 0°C to +70°C

µA VDD = 3.0V, -40°C to +85°C

Module Differential Cur-

rent (note5)

D021

Watchdog Timer

∆IWDT

—

6

20

—

µA VDD = 3.0V

D023* Brown-out Reset Current ∆IBOR

TBD 200

µA BOR enabled, VDD = 5.0V

(Note 5)

D025* Timer1 oscillator

D026* A/D Converter

∆IT1OSC

∆IAD

—

1.5

3

µA VDD = 3.0V

300

—

µA VDD = 5.5V, A/D on, not converting

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

4: For RC osc configuration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when the peripheral is enabled. This current should be

added to the base (IPD or IDD) current.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 153

PIC16C77X

15.3

DC Characteristics: PIC16C77X (Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 15.1 and

Section 15.2.

Param

No.

Characteristic

Sym

Min

Typ†

Max Units

Conditions

Input Low Voltage

I/O ports

VIL

—

D030

D030A

D031

with TTL buffer

VSS

0.15VDD

0.8V

V

For entire VDD range

4.5V ≤ VDD ≤ 5.5V

with Schmitt Trigger buffer

RC3 and RC4

All others

—

I²C compliant

For entire VDD range

VSS

0.3VDD

0.2VDD

V

—

D032

D033

MCLR, OSC1 (in RC mode)

OSC1 (in XT, HS and LP)

Input High Voltage

I/O ports

VSS

0.2VDD

0.3VDD

V

Note1

—

VIH

with TTL buffer

—

D040

D040A

2.0

0.25VDD

+ 0.8V

VDD

V

4.5V ≤ VDD ≤ 5.5V

For entire VDD range

with Schmitt Trigger buffer

RC3 and RC4

All others

—

I²C compliant

For entire VDD range

D041

D042

0.7VDD

0.8VDD

VDD

V

—

MCLR

0.8VDD

0.7VDD

0.9VDD

50

VDD

400

V

D042A OSC1 (XT, HS and LP)

Note1

—

D043

D070

OSC1 (in RC mode)

PORTB weak pull-up current

Input Leakage Current

(Notes 2, 3)

IPURB

250

µA VDD = 5V, VPIN = VSS

—

D060

I/O ports (digital)

IIL

±1

µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

nA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D060A I/O ports (RA0-RA3, RA5, RB2,

RB3 analog)

±100

—

D061

D063

MCLR, RA4/T0CKI

OSC1

±5

µA Vss ≤ VPIN ≤ VDD

µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc configuration

Output Low Voltage

—

D080

D083

I/O ports

VOL

0.6

V

IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

IOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

OSC2/CLKOUT (RC osc config)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C77X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.

DS30275A-page 154

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 15.1 and

Section 15.2.

Param

No.

Characteristic

Sym

Min

Typ†

Max Units

Conditions

Output High Voltage

—

D090

D092

I/O ports (Note 3)

VOH VDD - 0.7

VDD - 0.7

V

IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

OSC2/CLKOUT (RC osc config)

—

D150* Open-Drain High Voltage

Capacitive Loading Specs on

Output Pins

VOD

8.5

RA4 pin

—

D100

OSC2 pin

COSC2

15

pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

—

D101

D102

All I/O pins and OSC2 (in RC

mode) SCL, SDA in I²C mode

CIO

CB

50

400

pF

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C77X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as current sourced by the pin.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 155

PIC16C77X

15.4

DC Characteristics: VREF

TABLE 15-2

ELECTRICAL CHARACTERISTICS: VREF

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial

Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.

DC CHARACTERISTICS

Param

No.

Characteristic

Symbol

Min

Typ†

Max

Units

Conditions

Output Voltage

VRL

VRH

∆IVRL

∆IVRH

TCVOUT

IVREFSO

IVREFSI

2.0

4.0

—

2.048

4.096

70

15*

—

2.1

4.2

TBD

50*

5*

-5*

TBD*

V

µA

VDD ≥ 2.5V

VDD ≥ 4.5V

No load on VRL.

No load on VRH.

D400

D401A VRL Quiescent Supply Current

D401B VRH Quiescent Supply Current

—

D402

D404

D405

D406

Ouput Voltage Drift

External Load Source

External Load Sink

Load Regulation

ppm/°C Note 1

mA

—

1

Isource = 0 mA to

5 mA

Isink

5 mA

∆VOUT/

∆IOUT

mV/mA

—

1

TBD*

50*

= 0 mA to

D407

Line Regulation

∆VOUT/

∆VDD

—

µV/V

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Production tested at TAMB = 25°C. Specifications over temp limits guaranteed by characterization.

DS30275A-page 156

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 15-1: LOW-VOLTAGE DETECT CHARACTERISTICS

VDD

VLHYS

VLVD

(LVDIF set by hardware)

LVDIF

(LVDIF can be cleared in software anytime during

the gray area)

TABLE 15-3

ELECTRICAL CHARACTERISTICS: LVD

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial

Operating voltage VDD range as described in DC spec Section 15.1 and Section 15.2.

DC CHARACTERISTICS

Param

No.

Characteristic

Symbol

Min Typ† Max Units

Conditions

D420

LVV = 0100

LVV = 0101

LVV = 0110

LVV = 0111

LVV = 1000

LVV = 1001

LVV = 1010

LVV = 1011

LVV = 1100

LVV = 1101

LVV = 1110

2.5

2.7

2.8

3.0

3.3

3.5

3.6

3.8

4.0

4.2

4.5

—

2.58 2.66

2.78 2.86

2.89 2.98

V

LVD Voltage

3.1

3.2

3.41 3.52

3.61 3.72

3.72 3.84

3.92 4.04

4.13 4.26

4.33 4.46

4.64 4.78

V

µA

D421 Supply Current

D422* LVD Voltage Drift Temperature

coefficient

∆ILVD

TCVOUT

10

15

20

—

50 ppm/°C

—

D423* LVD Voltage Drift with respect to

VDD Regulation

∆VLVD/

∆VDD

50

µV/V

D424* Low-voltage Detect Hysteresis

VLHYS

TBD

—

100

mV

*

These parameters are characterized but not tested.

Note 1: Production tested at Tamb = 25°C. Specifications over temp limits ensured by characterization.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 157

PIC16C77X

FIGURE 15-2: BROWN-OUT RESET CHARACTERISTICS

VDD

(device not in Brown-out Reset)

VBHYS

VBOR

(device in Brown-out Reset)

RESET (due to BOR)

72 ms time out

TABLE 15-4

ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and

0°C ≤ TA ≤ +70°C for commercial

DC CHARACTERISTICS

Operating voltage VDD range as described in DC spec Section 15.1 and

Section 15.2.

Param

No.

Characteristic

Symbol

Min

Typ

Max

Units

Conditions

2.5

2.58

2.66

D005

BOR Voltage

BORV1:0 = 11

BORV1:0 = 10

BORV1:0 = 01

BORV1:0 = 00

2.7

4.2

4.5

—

2.78

4.33

4.64

15

2.86

4.46

4.78

50

VBOR

V

D006*

BOR Voltage Drift Temperature coef-

ficient

TCVOUT

ppm/°C

—

D006A* BOR Voltage Drift with respect to

∆VBOR/

∆VDD

50

µV/V

VDD Regulation

D007

Brown-out Hysteresis

VBHYS

∆IBOR

TBD

—

10

100

20

mV

µA

D022A Supply Current

*

These parameters are characterized but not tested.

Note 1: Production tested at TAMB = 25°C. Specifications over temp limits ensured by characterization.

DS30275A-page 158

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

15.5

AC Characteristics: PIC16C77X (Commercial, Industrial)

15.5.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

3. TCC:ST

4. Ts

(I²C specifications only)

2. TppS

T

F

Frequency

T

Time

Lowercase letters (pp) and their meanings:

pp

cc

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

I²C only

AA

output access

Bus free

High

Low

High

Low

BUF

TCC:ST (I²C specifications only)

CC

HD

ST

DAT

STA

Hold

SU

Setup

DATA input hold

START condition

STO

STOP condition

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 159

PIC16C77X

FIGURE 15-3: LOAD CONDITIONS

Load condition 1

Load condition 2

VDD/2

RL

CL

VSS

RL = 464Ω

CL = 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as

ports

15 pF for OSC2 output

Note: PORTD and PORTE are not implemented on the PIC16C773.

DS30275A-page 160

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

15.5.2 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 15-4: EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

4

Q1

OSC1

1

3

4

3

2

CLKOUT

TABLE 15-5

EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic

Min

Typ†

Max

Units Conditions

Fosc External CLKIN Frequency

DC

0.1

—

4

MHz XT and RC osc mode

MHz HS osc mode (-04)

MHz HS osc mode (-20)

kHz LP osc mode

(Note 1)

20

200

4

Oscillator Frequency

(Note 1)

MHz RC osc mode

4

MHz XT osc mode

4

5

—

20

200

MHz HS osc mode

kHz LP osc mode

1

Tosc External CLKIN Period

250

50

—

TCY

—

ns

µs

ns

µs

ns

µs

ns

XT and RC osc mode

HS osc mode (-04)

HS osc mode (-20)

LP osc mode

(Note 1)

—

5

—

Oscillator Period

(Note 1)

250

50

—

RC osc mode

XT osc mode

10,000

250

—

HS osc mode (-04)

HS osc mode (-20)

LP osc mode

5

2

TCY

Instruction Cycle Time (Note 1)

200

100

2.5

15

DC

—

TCY = 4/FOSC

3*

TosL, External Clock in (OSC1) High or

TosH Low Time

XT oscillator

—

LP oscillator

—

HS oscillator

4*

TosR, External Clock in (OSC1) Rise or

TosF Fall Time

—

25

XT oscillator

—

50

LP oscillator

—

15

HS oscillator

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-

sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.

When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 161

PIC16C77X

FIGURE 15-5: CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

CLKOUT

13

14

12

18

19

16

I/O Pin

(input)

15

17

I/O Pin

new value

old value

(output)

20, 21

Note: Refer to Figure 15-3 for load conditions.

TABLE 15-6

CLKOUT AND I/O TIMING REQUIREMENTS

Parameter Sym

No.

Characteristic

Min

Typ†

Max

Units Conditions

10*

11*

12*

13*

14*

15*

16*

17*

TosH2ckL OSC1↑ to CLKOUT↓

TosH2ckH OSC1↑ to CLKOUT↑

—

75

35

—

50

200

ns

Note 1

TckR

TckF

CLKOUT rise time

CLKOUT fall time

100

TckL2ioV CLKOUT ↓ to Port out valid

TioV2ckH Port in valid before CLKOUT ↑

0.5TCY + 20

—

0.25TCY + 25

TckH2ioI

Port in hold after CLKOUT ↑

0

—

TosH2ioV OSC1↑ (Q1 cycle) to

—

150

Port out valid

PIC16C77X

18*

TosH2ioI

OSC1↑ (Q2 cycle) to

Port input invalid (I/O in

hold time)

100

200

—

ns

PIC16LC77X

19*

20*

TioV2osH Port input valid to OSC1↑ (I/O in setup time)

0

—

10

—

10

—

25

60

25

60

—

ns

PIC16C77X

PIC16LC77X

PIC16C77X

PIC16LC77X

TioR

Port output rise time

Port output fall time

INT pin high or low time

—

21*

TioF

—

22††*

23††*

Tinp

Trbp

TCY

RB7:RB4 change INT high or low time

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

DS30275A-page 162

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O Pins

Note: Refer to Figure 15-3 for load conditions.

FIGURE 15-7: BROWN-OUT RESET TIMING

BVDD

VDD

35

TABLE 15-7

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER,POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

Conditions

30*

TmcL MCLR Pulse Width (low)

100

—

ns

VDD = 5V, -40°C to +85°C

31*

Twdt

Watchdog Timer Time-out Period

7

18

33

ms VDD = 5V, -40°C to +85°C

(No Prescaler)

32*

33*

34*

Tost

Oscillation Start-up Timer Period

—

28

—

1024TOSC

—

TOSC = OSC1 period

Tpwrt Power up Timer Period

72

—

132

100

ms VDD = 5V, -40°C to +85°C

TIOZ

I/O Hi-impedance from MCLR Low

ns

or Watchdog Timer Reset

35*

TBOR

Brown-out Reset pulse width

100

—

µs

VDD ≤ VBOR (D005)

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 163

PIC16C77X

FIGURE 15-8: BANDGAP START-UP TIME

VBGAP

VBGAP = 1.2V

Enable Bandgap

TBGAP

Bandgap stable

TABLE 15-8

BANDGAP START-UP TIME

Parameter

No.

Sym

Characteristic

Min

Typ†

Max Units

TBD

Conditions

36*

TBGAP Bandgap start-up time

—

30

µs Defined as the time between

the instant that the bandgap

is enabled and the moment

that the bandgap reference

voltage is stable.

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS30275A-page 164

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

TABLE 15-9

A/D CONVERTER CHARACTERISTICS:

Param

No.

Sym Characteristic

Min

Typ†

Max

Units

Conditions

A01

NR

Resolution

—

12 bits

bit Min. resolution for A/D is 1 mV,

VREF+ = AVDD = 4.096V,

VREF- = AVSS = 0V,

VREF- ≤ VAIN ≤ VREF+

A03

A04

EIL

Integral error

—

+/-2 LSb

—

VREF+ = AVDD = 4.096V,

VREF- = AVSS = 0V,

VREF- ≤ VAIN ≤ VREF+

EDL

Differential error

+2 LSb

-1 LSb

No missing codes to 12-bits

VREF+ = AVDD = 4.096V,

VREF- = AVSS = 0V,

VREF- ≤ VAIN ≤ VREF+

A06

A07

EOFF Offset error

—

less than

±2 LSb

—

VREF+ = AVDD = 4.096V,

VREF- = AVSS = 0V,

VREF- ≤ VAIN ≤ VREF+

EGN

Gain Error

+/- 2LSb

LSb VREF+ = AVDD = 4.096V,

VREF- = AVSS = 0V,

VREF- ≤ VAIN ≤ VREF+

(3)

A10

A20

—

Monotonicity

—

guaranteed

—

V

AVSS ≤ VAIN ≤ VREF+

VREF Reference voltage

(VREF+ VREF-)

4.096

VDD +0.3V

Absolute minimum electrical spec to

ensure 12-bit accuracy.

A21

A22

VREF+ Reference V High

(AVDD or VREF+)

VREF-

AVSS

—

AVDD

V

Min. resolution for A/D is 1 mV

VREF- Reference V Low

(AVSS or VREF-)

VREF+

Min. resolution for A/D is 1 mV

A25

A30

VAIN

ZAIN Recommended

impedance of analog

Analog input voltage

VREFL

—

VREFH

V

—

2.5

kΩ

voltage source

A50

IREF

VREF input current

—

10

µA During VAIN acquisition.

(Note 2)

Based on differential of VHOLD to VAIN.

To charge CHOLD see Section 11.0.

During A/D conversion cycle.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: When A/D is off, it will not consume any current other than minor leakage current. The power down current spec includes any

such leakage from the A/D module.

2: VREF current is from External VREF+, OR VREF-, or AVSS, or AVDD pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 165

PIC16C77X

FIGURE 15-9: A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

1/2 Tcy

134

131

Q4

130

A/D CLK

9

8

7

6

3

2

1

0

A/D DATA

ADRES

NEW_DATA

DONE

OLD_DATA

ADIF

GO

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 15-10 A/D CONVERSION REQUIREMENTS

Parameter

No.

Sym Characteristic

Min

Typ†

Max

Units

Conditions

130*

TAD

A/D clock period

1.6

—

µs

Tosc based, VREF ≥ 2.5V

3.0

Tosc based, VREF full range

130*

TAD

A/D Internal RC

oscillator period

ADCS1:ADCS0 = 11 (RC mode)

3.0

2.0

—

6.0

4.0

9.0

6.0

—

µs

At VDD = 2.5V

At VDD = 5.0V

131*

132*

TCNV Conversion time (not

including

13TAD

TAD Set GO bit to new data in A/D result

register

acquisition time)

(Note 1)

TACQ Acquisition Time

Note 2

5*

11.5

—

µs

µs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1LSb (i.e

1mV @ 4.096V) from the last sam-

pled voltage (as stated on CHOLD).

134*

TGO

Q4 to A/D clock start

—

TOSC/2

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: ADRES register may be read on the following TCY cycle.

2: See Section 11.6 for minimum conditions.

DS30275A-page 166

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 15-10: A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

134

131

Q4

130

A/D CLK

9

8

7

3

2

1

0

6

A/D DATA

ADRES

NEW_DATA

OLD_DATA

ADIF

GO

DONE

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 15-11 A/D CONVERSION REQUIREMENTS

Parameter

No.

Sym Characteristic

Min

Typ†

Max

Units

Conditions

130*

TAD

A/D clock period

1.6

—

µs

VREF ≥ 2.5V

TBD

VREF full range

130*

TAD

A/D Internal RC

oscillator period

ADCS1:ADCS0 = 11 (RC mode)

3.0

2.0

—

6.0

4.0

9.0

6.0

—

µs

—

At VDD = 3.0V

At VDD = 5.0V

131*

132*

TCNV Conversion time (not

including acquisition

time)(Note 1)

13TAD

TACQ Acquisition Time

Note 2

5*

11.5

—

µs

µs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1LSb (i.e

1mV @ 4.096V) from the last sam-

pled voltage (as stated on CHOLD).

134*

TGO

Q4 to A/D clock start

—

TOSC/2 + TCY

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: ADRES register may be read on the following TCY cycle.

2: See Section 11.6 for minimum conditions.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 167

PIC16C77X

FIGURE 15-11: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

RA4/T0CKI

41

40

42

RC0/T1OSO/T1CKI

46

45

47

48

TMR0 or

TMR1

Note: Refer to Figure 15-3 for load conditions.

TABLE 15-12 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ† Max Units Conditions

40*

Tt0H

T0CKI High Pulse Width

No Prescaler

0.5TCY + 20

—

ns Must also meet

parameter 42

With Prescaler

No Prescaler

10

0.5TCY + 20

10

—

ns

41*

42*

Tt0L

Tt0P

T0CKI Low Pulse Width

T0CKI Period

ns Must also meet

parameter 42

With Prescaler

No Prescaler

With Prescaler

ns

TCY + 40

Greater of:

20 or TCY + 40

ns N = prescale value

(2, 4, ..., 256)

N

0.5TCY + 20

15

45*

46*

47*

Tt1H

Tt1L

Tt1P

T1CKI High Time Synchronous, Prescaler = 1

—

ns Must also meet

parameter 47

Synchronous, PIC16C77X

ns

Prescaler =

2,4,8

PIC16LC77X

25

Asynchronous PIC16C77X

PIC16LC77X

30

—

ns

50

T1CKI Low Time

Synchronous, Prescaler = 1

Synchronous, PIC16C77X

0.5TCY + 20

ns Must also meet

parameter 47

15

25

ns

Prescaler =

2,4,8

PIC16LC77X

Asynchronous PIC16C77X

PIC16LC77X

30

—

ns

50

Greater of:

30 OR TCY + 40

N

T1CKI input period Synchronous

PIC16C77X

ns N = prescale value

(1, 2, 4, 8)

PIC16LC77X

Greater of:

50 OR TCY + 40

N

—

ns N = prescale value

(1, 2, 4, 8)

Asynchronous PIC16C77X

PIC16LC77X

60

100

DC

—

50

ns

Ft1

Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN)

kHz

48

*

TCKEZtmr1 Delay from external clock edge to timer increment

2Tosc

—

7Tosc

—

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS30275A-page 168

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 15-12: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

RC1/T1OSI/CCP2

and RC2/CCP1

(Capture Mode)

50

51

52

RC1/T1OSI/CCP2

and RC2/CCP1

(Compare or PWM Mode)

53

Note: Refer to Figure 15-3 for load conditions.

54

TABLE 15-13 CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Parameter Sym Characteristic

No.

Min

Typ† Max Units Conditions

50*

TccL CCP1 and CCP2 No Prescaler

input low time

0.5TCY + 20

—

ns

PIC16C77X

10

—

ns

With Prescaler

PIC16LC77X

20

51*

TccH

No Prescaler

0.5TCY + 20

CCP1 and CCP2

input high time

PIC16C77X

10

20

With Prescaler

PIC16LC77X

52*

53*

TccP

3TCY + 40

ns N = prescale value

(1,4 or 16)

CCP1 and CCP2 input period

N

PIC16C77X

PIC16LC77X

PIC16C77X

PIC16LC77X

TccR CCP1 and CCP2 output fall time

TccF CCP1 and CCP2 output fall time

—

10

25

10

25

45

25

45

ns

54*

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 169

PIC16C77X

FIGURE 15-13: PARALLEL SLAVE PORT TIMING (PIC16C774)

RE2/CS

RE0/RD

RE1/WR

65

RD7:RD0

62

64

63

Note: Refer to Figure 15-3 for load conditions.

TABLE 15-14 PARALLEL SLAVE PORT REQUIREMENTS (PIC16C774)

Parameter

No.

Sym

Characteristic

Min Typ† Max Units Conditions

62*

TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)

20

25

—

ns

Extended

Temperature

Range Only

63*

64*

TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) PIC16C774

PIC16LC774

20

35

—

ns

TrdL2dtV RD↓ and CS↓ to data–out valid

—

80

90

ns Extended

Temperature

Range Only

65*

TrdH2dtI RD↑ or CS↓ to data–out invalid

10

—

30

ns

*

These parameters are characterized but not tested.

†

Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

DS30275A-page 170

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

FIGURE 15-14: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

121

RC7/RX/DT

120

122

Note: Refer to Figure 15-3 for load conditions.

TABLE 15-15 USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param Sym

No.

Characteristic

Min

Typ† Max Units Conditions

120*

TckH2dtV

SYNC XMIT (MASTER &

SLAVE)

Clock high to data out valid

PIC16C774/773

PIC16LC774/773

—

80

100

45

ns

121*

122*

Tckrf

Tdtrf

Clock out rise time and fall time PIC16C774/773

(Master Mode)

PIC16LC774/773

50

Data out rise time and fall time PIC16C774/773

PIC16LC774/773

45

50

*

These parameters are characterized but not tested.

†:

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

FIGURE 15-15: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK

125

RC7/RX/DT

126

Note: Refer to Figure 15-3 for load conditions.

TABLE 15-16 USART SYNCHRONOUS RECEIVE REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ†

Max

Units Conditions

125*

TdtV2ckL

SYNC RCV (MASTER & SLAVE)

Data setup before CK ↓ (DT setup time)

15

—

ns

126*

TckL2dtl

Data hold after CK ↓ (DT hold time)

15

*

These parameters are characterized but not tested.

†:

Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 171

PIC16C77X

NOTES:

DS30275A-page 172

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are guaranteed to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. ’Typical’ represents the mean of the distribution at 25°C. ’Max’ or ’min’ represents

(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.

Graphs and Tables not available at this time.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 173

PIC16C77X

NOTES:

DS30275A-page 174

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.0 PACKAGING INFORMATION

17.1

Package Marking Information

28-Lead PDIP (Skinny DIP)

Example

PIC16C773-20/SP

XXXXXXXXXXXXXXXXXXXX

AABBCDE

9917HAT

28-Lead CERDIP Windowed

Example

XXXXXXXXXXX

PIC16C774/JW

9905HAT

AABBCDE

28-Lead SOIC

Example

PIC16C773-20/SO

9910SAA

XXXXXXXXXXXXXXXXXXXXXXXX

AABBCDE

28-Lead SSOP

Example

XXXXXXXXXXXX

PIC16C773

20I/SS

AABBCAE

9817SBP

Legend: MM...M Microchip part number information

XX...X Customer specific information*

AA

BB

C

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D

E

Mask revision number

Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with

your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 175

PIC16C77X

Package Marking Information (Cont’d)

40-Lead PDIP

Example

PIC16C774-04/P

9912SAA

XXXXXXXXXXXXXXXXXX

AABBCDE

40-Lead CERDIP Windowed

Example

XXXXXXXXXXXXX

PIC16C774/JW

XXXXXXXXXXXXX

AABBCDE

9905HAT

44-Lead TQFP

Example

XXXXXXXXXXXX

PIC16C774

-04/PT

9911HAT

AABBCDE

44-Lead MQFP

Example

XXXXXXXXXXXX

PIC16C774

-20/PQ

AABBCDE

9904SAT

44-Lead PLCC

Example

XXXXXXXXXXXX

AABBCDE

PIC16C774

-04/L

9903SAT

DS30275A-page 176

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.2

K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil

E

D

2

α

n

1

E1

A1

A

R

L

c

B1

β

A2

p

eB

B

Units

INCHES*

NOM

0.300

28

MILLIMETERS

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

Molded Package Width

Radius to Radius Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

MIN

MAX

MIN

NOM

7.62

MAX

n

p

B

B1

R

c

28

2.54

0.48

1.33

0.13

0.25

3.81

2.29

0.51

3.30

34.67

7.30

7.18

8.89

10

0.100

0.019

0.053

0.005

0.010

0.150

0.090

0.020

0.130

1.365

0.288

0.283

0.350

10

0.016

0.022

0.41

0.56

†

0.040

0.000

0.008

0.140

0.070

0.015

0.125

1.345

0.280

0.270

0.320

5

0.065

0.010

0.012

0.160

0.110

0.025

0.135

1.385

0.295

0.380

15

1.02

0.00

0.20

3.56

1.78

0.38

3.18

34.16

7.11

6.86

8.13

5

1.65

0.25

0.30

4.06

2.79

0.64

3.43

35.18

7.49

9.65

15

A

A1

A2

L

D

E

E1

eB

α

‡

β

5

10

15

5

10

15

*

Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 177

PIC16C77X

17.3

K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil

E

D

W2

2

1

n

W1

E1

A

A1

R

L

c

B1

B

A2

eB

p

Units

INCHES*

NOM

0.300

28

MILLIMETERS

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

MIN

MAX

MIN

NOM

7.62

28

MAX

n

p

B

B1

R

c

A

A1

A2

L

D

E

E1

eB

W1

W2

0.098

0.100

0.019

0.058

0.013

0.010

0.183

0.125

0.023

0.140

1.458

0.290

0.270

0.385

0.140

0.300

0.102

2.49

0.41

2.54

0.47

1.46

0.32

0.25

4.64

3.18

0.57

3.56

37.02

7.37

6.86

9.78

0.14

0.3

2.59

0.016

0.050

0.010

0.008

0.170

0.107

0.015

0.135

1.430

0.285

0.255

0.345

0.130

0.290

0.021

0.065

0.015

0.012

0.195

0.143

0.030

0.145

1.485

0.295

0.285

0.425

0.150

0.310

0.53

1.65

0.38

0.30

4.95

3.63

0.76

3.68

37.72

7.49

7.24

10.80

0.15

0.31

1.27

0.25

0.20

4.32

2.72

0.00

3.43

36.32

7.24

6.48

8.76

0.13

0.29

Package Width

Radius to Radius Width

Overall Row Spacing

Window Width

Window Length

* Controlling Parameter.

DS30275A-page 178

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.4

K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil

E1

E

p

D

B

2

1

n

X

α

45°

L

R2

c

A

A1

φ

R1

β

L1

A2

Units

Dimension Limits

Pitch

INCHES*

NOM

0.050

28

MILLIMETERS

MIN

MAX

MIN

NOM

1.27

MAX

p

n

A

A1

A2

Number of Pins

28

2.50

1.47

0.19

17.93

7.51

10.33

0.50

0.13

0.41

4

Overall Pack. Height

Shoulder Height

Standoff

Molded Package Length

Molded Package Width

Outside Dimension

Chamfer Distance

Shoulder Radius

Gull Wing Radius

Foot Length

0.093

0.099

0.058

0.008

0.706

0.296

0.407

0.020

0.005

0.016

4

0.104

2.36

2.64

0.048

0.004

0.700

0.292

0.394

0.010

0.005

0.011

0

0.068

0.011

0.712

0.299

0.419

0.029

0.010

0.021

8

1.22

0.10

17.78

7.42

10.01

0.25

0.13

0.28

0

1.73

0.28

18.08

7.59

10.64

0.74

0.25

0.53

8

‡

D

E

‡

E1

X

R1

R2

L

Foot Angle

φ

Radius Centerline

Lead Thickness

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

*

L1

c

B

α

β

0.010

0.009

0.014

0

0.015

0.011

0.017

12

0.020

0.012

0.019

15

0.25

0.23

0.36

0

0.38

0.27

0.42

12

0.51

0.30

0.48

15

†

0

12

15

0

12

15

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 179

PIC16C77X

17.5

K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm

E1

E

p

D

B

2

1

n

α

L

A

R2

c

A1

R1

A2

φ

L1

β

Units

Dimension Limits

Pitch

INCHES

NOM

0.026

28

MILLIMETERS*

MIN

MAX

MIN

NOM

0.65

28

MAX

p

n

A

A1

A2

D

E

E1

R1

R2

L

Number of Pins

Overall Pack. Height

Shoulder Height

Standoff

Molded Package Length

Molded Package Width

Outside Dimension

Shoulder Radius

Gull Wing Radius

Foot Length

0.068

0.073

0.036

0.005

0.402

0.208

0.306

0.005

0.020

4

0.078

1.73

0.66

1.86

0.91

0.13

10.20

5.29

7.78

0.13

0.51

4

1.99

0.026

0.002

0.396

0.205

0.301

0.005

0.015

0

0.046

0.008

0.407

0.212

0.311

0.010

0.025

8

1.17

0.21

10.33

5.38

7.90

0.25

0.64

8

0.05

10.07

5.20

7.65

0.13

0.38

0

‡

Foot Angle

φ

Radius Centerline

Lead Thickness

Lower Lead Width

Mold Draft Angle Top

Mold Draft Angle Bottom

*

L1

c

B

α

β

0.000

0.005

0.010

0

0.005

0.007

0.012

5

0.010

0.009

0.015

10

0.00

0.13

0.25

0

0.13

0.18

0.32

5

0.25

0.22

0.38

10

†

0

5

10

0

5

10

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

DS30275A-page 180

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.6

K04-016 40-Lead Plastic Dual In-line (P) – 600 mil

E

D

α

2

n

1

A1

L

E1

A

R

c

B1

B

β

A2

p

eB

Units

INCHES*

NOM

0.600

40

MILLIMETERS

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

Molded Package Width

Radius to Radius Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

MIN

MAX

MIN

NOM

15.24

MAX

n

p

B

B1

R

c

A

A1

A2

L

D

E

E1

eB

α

40

2.54

0.46

1.27

0.13

0.25

4.06

2.36

0.51

3.30

51.26

13.59

14.35

15.49

10

0.100

0.018

0.050

0.005

0.010

0.160

0.093

0.020

0.130

2.018

0.535

0.565

0.610

10

0.016

0.020

0.41

0.51

†

0.045

0.000

0.009

0.110

0.073

0.020

0.125

2.013

0.530

0.545

0.630

5

0.055

0.010

0.011

0.160

0.113

0.040

0.135

2.023

0.540

0.585

0.670

15

1.14

0.00

0.23

2.79

1.85

0.51

3.18

51.13

13.46

13.84

16.00

5

1.40

0.25

0.28

4.06

2.87

1.02

3.43

51.38

13.72

14.86

17.02

15

‡

β

5

10

15

5

10

15

*

Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 181

PIC16C77X

17.7

K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil

E

W

D

2

1

n

A1

L

E1

A

R

c

eB

B1

A2

p

B

Units

INCHES*

NOM

0.600

40

MILLIMETERS

Dimension Limits

PCB Row Spacing

Number of Pins

Pitch

Lower Lead Width

Upper Lead Width

Shoulder Radius

Lead Thickness

Top to Seating Plane

Top of Lead to Seating Plane

Base to Seating Plane

Tip to Seating Plane

Package Length

MIN

MAX

MIN

NOM

15.24

40

MAX

n

p

B

B1

R

c

A

A1

A2

L

D

E

E1

eB

W

0.098

0.100

0.020

0.053

0.005

0.011

0.205

0.135

0.045

0.140

2.050

0.520

0.580

0.660

0.350

0.102

2.49

0.41

2.54

0.50

2.59

0.58

1.40

0.25

0.36

5.59

3.89

1.52

3.68

52.32

13.36

15.24

18.03

9.14

0.016

0.050

0.000

0.008

0.190

0.117

0.030

0.135

2.040

0.514

0.560

0.610

0.340

0.023

0.055

0.010

0.014

0.220

0.153

0.060

0.145

2.060

0.526

0.600

0.710

0.360

1.27

0.00

1.33

0.13

0.20

0.28

4.83

5.21

2.97

3.43

0.00

1.14

3.43

3.56

51.82

13.06

14.22

15.49

8.64

52.07

13.21

14.73

16.76

8.89

Package Width

Radius to Radius Width

Overall Row Spacing

Window Diameter

*

Controlling Parameter.

DS30275A-page 182

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.8

K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form

E1

E

# leads = n1

p

D

D1

2

1

B

n

X x 45°

L

α

A

R2

c

φ

R1

A1

β

A2

L1

Units

Dimension Limits

Pitch

INCHES

NOM

0.031

44

MILLIMETERS*

MIN

MAX

MIN

NOM

0.80

44

MAX

p

n

n1

A

A1

A2

R1

R2

L

Number of Pins

Pins along Width

Overall Pack. Height

Shoulder Height

Standoff

Shoulder Radius

Gull Wing Radius

Foot Length

11

0.039

0.015

0.002

0.003

0.005

0

0.043

0.025

0.004

0.003

0.006

0.010

3.5

0.047

1.00

0.38

1.10

0.64

0.10

0.08

0.14

0.25

3.5

1.20

0.035

0.006

0.010

0.008

0.015

7

0.89

0.15

0.25

0.20

0.38

7

0.05

0.08

0.13

0

Foot Angle

φ

Radius Centerline

Lead Thickness

Lower Lead Width

Outside Tip Length

Outside Tip Width

Molded Pack. Length

Molded Pack. Width

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

L1

c

B

0.003

0.004

0.012

0.463

0.390

0.025

5

0.008

0.006

0.015

0.472

0.394

0.035

10

0.013

0.008

0.018

0.482

0.398

0.045

15

0.08

0.09

0.30

11.75

9.90

0.64

5

0.20

0.15

0.38

12.00

10.00

0.89

10

0.33

0.20

0.45

12.25

10.10

1.14

15

†

D1

E1

‡

D

E

‡

X

α

β

5

12

15

5

12

15

*

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

JEDEC equivalent:MS-026 ACB

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 183

PIC16C77X

17.9

K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form

E1

E

# leads = n1

p

D

D1

2

1

B

n

X x 45°

α

L

R2

c

A

R1

φ

A1

β

L1

A2

Units

Dimension Limits

Pitch

INCHES

NOM

0.031

MILLIMETERS*

MIN

MAX

MIN

NOM

0.80

44

MAX

p

n

n1

A

A1

A2

R1

R2

L

Number of Pins

Pins along Width

Overall Pack. Height

Shoulder Height

Standoff

Shoulder Radius

Gull Wing Radius

Foot Length

44

11

0.079

0.086

0.044

0.006

0.005

0.012

0.020

3.5

0.093

2.00

0.81

2.18

1.11

0.15

0.13

0.30

0.51

3.5

2.35

0.032

0.002

0.005

0.015

0.056

0.010

0.015

0.025

1.41

0.25

0.38

0.64

7

0.05

0.13

0.38

0

Foot Angle

φ

0

7

Radius Centerline

Lead Thickness

Lower Lead Width

Outside Tip Length

Outside Tip Width

Molded Pack. Length

Molded Pack. Width

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

L1

c

B

D1

E1

0.011

0.005

0.012

0.510

0.390

0.025

0.016

0.007

0.015

0.520

0.394

0.035

10

0.021

0.009

0.018

0.530

0.398

0.045

15

0.28

0.13

0.30

12.95

9.90

0.635

5

0.41

0.18

0.37

13.20

10.00

0.89

10

0.53

0.23

0.45

13.45

10.10

1.143

15

†

‡

D

‡

E

X

α

5

β

12

15

5

12

15

*

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

JEDEC equivalent:MS-022AB

DS30275A-page 184

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

17.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square

E1

E

# leads = n1

D1

D

n 1 2

α

A3

CH2 x 45°

CH1 x 45°

R1

c

L

A

35°

A1

B1

B

R2

β

A2

p

E2

D2

Units

INCHES*

NOM

44

MILLIMETERS

Dimension Limits

Number of Pins

Pitch

Overall Pack. Height

Shoulder Height

Standoff

MIN

MAX

MIN

NOM

MAX

n

p

A

A1

A2

A3

CH1

CH2

E1

D1

E

D

E2

D2

n1

c

B1

B

44

0.050

0.173

0.103

0.023

0.029

0.045

0.005

0.690

0.653

0.620

11

0.010

0.029

0.018

0.058

0.005

0.025

5

1.27

4.38

2.60

0.57

0.74

1.14

0.13

17.53

16.59

15.75

11

0.165

0.180

4.19

2.41

0.38

0.61

1.02

4.57

2.79

0.76

0.86

1.27

0.095

0.015

0.024

0.040

0.000

0.685

0.650

0.610

0.110

0.030

0.034

0.050

0.010

0.695

0.656

0.630

Side 1 Chamfer Dim.

Corner Chamfer (1)

Corner Chamfer (other)

Overall Pack. Width

Overall Pack. Length

Molded Pack. Width

Molded Pack. Length

Footprint Width

Footprint Length

Pins along Width

Lead Thickness

Upper Lead Width

Lower Lead Width

Upper Lead Length

Shoulder Inside Radius

J-Bend Inside Radius

Mold Draft Angle Top

Mold Draft Angle Bottom

*

0.00

0.25

17.40

16.51

15.49

17.65

16.66

16.00

‡

0.008

0.026

0.015

0.050

0.003

0.015

0

0.012

0.032

0.021

0.065

0.010

0.035

10

0.20

0.66

0.38

1.27

0.08

0.38

0

0.25

0.74

0.46

1.46

0.13

0.64

5

0.30

0.81

0.53

1.65

0.25

0.89

10

†

L

R1

R2

α

β

0

5

10

0

5

10

Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.”

JEDEC equivalent:MO-047 AC

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 185

PIC16C77X

NOTES:

DS30275A-page 186

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

APPENDIX A: REVISION HISTORY

Version

Date

Revision Description

A

99

This is a new data sheet. However, the devices described in this data sheet are

the upgrades to the devices found in the PIC16C7X Data Sheet, DS30390E.

APPENDIX B: DEVICE DIFFERENCES

The differences between the devices in this data sheet

are listed in Table B-1.

TABLE B-1:

DEVICE DIFFERENCES

Difference

PIC16C773

6 channels, 12 bits

no

PIC16C774

10 channels, 12 bits

A/D

Parallel Slave Port

Packages

yes

28-pin PDIP, 28-pin windowed CERDIP,

28-pin SOIC, 28-pin SSOP

40-pin PDIP, 40-pin windowed CERDIP,

44-pin TQFP, 44-pin MQFP,

44-pin PLCC

APPENDIX C: CONVERSION CONSIDERATIONS

Considerations for converting from previous versions of

devices to the ones listed in this data sheet are listed in

the following:

Program Memory Differences

none

Data Memory Differences

PIC16C774 vs. PIC16C74A

1. Data memory size has increased to 256 from

192 by adding bank 2.

• RA2

• RA3

• RA5

Added VREF- and VRL

Added VREF+ and VRH

Removed SS

2. Bank 1 locations 0xF0 - 0xFF are now common

RAM locations across banks 0-3.

• Pin 11 AVDD vs. VDD

• Pin 12 AVSS vs. VSS

Peripheral Differences

1. 12-bit A/D replaces 8-bit A/D.

• RB1

• RB2

• RB3

Added SS, SS is now ST vs. TTL

2. Master Synchronous Serial Port replace

Synchronous Serial Port.

Added AN8

Added AN9 and LVDIN

3. USART adds 9-bit address mode to module.

4. Bandgap Voltage Reference added.

PIC16C773 vs. PIC16C73A

5. Low-voltage Detect Module added.

• RA2

• RA3

• Pin 7

• Pin 8

• RB1

• RB2

• RB3

Added VREF- and VRL

6. Selectable Brown-out Reset voltages added.

Added VREF+ and VRH

AVDD vs. removed RA5/SS/AN4

AVSS vs. VSS

Added SS, SS is now ST vs. TTL

Added AN8

Added AN9 and LVDIN

1999 Microchip Technology Inc.

Advance Information

DS30275A-page 187

PIC16C77X

NOTES:

DS30275A-page 188

Advance Information

1999 Microchip Technology Inc.

PIC16C77X

INDEX

A

C

Capture (CCP Module) ...................................................... 48

Block Diagram ........................................................... 48

CCP Pin Configuration .............................................. 48

CCPR1H:CCPR1L Registers .................................... 48

Changing Between Capture Prescalers .................... 48

Software Interrupt ...................................................... 48

Timer1 Mode Selection .............................................. 48

Capture/Compare/PWM (CCP) ......................................... 47

CCP1 ......................................................................... 47

CCP1CON Register ........................................... 47

CCPR1H Register ............................................. 47

CCPR1L Register .............................................. 47

Enable (CCP1IE Bit) .......................................... 19

Flag (CCP1IF Bit) .............................................. 20

RC2/CCP1 Pin ................................................. 7, 9

CCP2 ......................................................................... 47

CCP2CON Register ........................................... 47

CCPR2H Register ............................................. 47

CCPR2L Register .............................................. 47

Enable (CCP2IE Bit) .......................................... 21

Flag (CCP2IF Bit) .............................................. 22

RC1/T1OSI/CCP2 Pin ..................................... 7, 9

Interaction of Two CCP Modules ............................... 47

Timer Resources ....................................................... 47

CCP1CON ......................................................................... 15

CCP1CON Register ........................................................... 47

CCP1M3:CCP1M0 Bits ............................................. 47

CCP1X:CCP1Y Bits ................................................... 47

CCP2CON ......................................................................... 15

CCP2CON Register ........................................................... 47

CCP2M3:CCP2M0 Bits ............................................. 47

CCP2X:CCP2Y Bits ................................................... 47

CCPR1H Register ........................................................ 13, 15

CCPR1L Register .............................................................. 15

CCPR2H Register ........................................................ 13, 15

CCPR2L Register ........................................................ 13, 15

CKE ................................................................................... 54

CKP ................................................................................... 55

Clock Polarity Select bit, CKP ............................................ 55

Code Examples

A/D ................................................................................... 117

A/D Converter Enable (ADIE Bit) ............................... 19

A/D Converter Flag (ADIF Bit) ................................... 20

ADCON0 Register .................................................... 117

ADCON1 Register ............................................ 117, 118

ADRES Register ...................................................... 117

Analog Port Pins ...................................... 7, 8, 9, 36, 37

Block Diagram .......................................................... 120

Configuring Analog Port ........................................... 119

Conversion time ....................................................... 125

Conversions ............................................................. 121

converter characteristics .................. 156, 157, 158, 165

Faster Conversion - Lower Resolution Tradeoff ...... 125

Internal Sampling Switch (Rss) Impedence ............. 123

Operation During Sleep ........................................... 126

Sampling Requirements ........................................... 123

Sampling Time ......................................................... 123

Source Impedance ................................................... 123

Special Event Trigger (CCP) ...................................... 49

A/D Conversion Clock ...................................................... 121

ACK .................................................................................... 64

Acknowledge Data bit, AKD ............................................... 56

Acknowledge Pulse ............................................................ 64

Acknowledge Sequence Enable bit, AKE .......................... 56

Acknowledge Status bit, AKS ............................................ 56

ADCON0 Register ............................................................ 117

ADCON1 Register .................................................... 117, 118

ADRES ............................................................................. 117

ADRES Register .......................................... 13, 14, 117, 126

AKD .................................................................................... 56

AKE .................................................................................... 56

AKS .............................................................................. 56, 79

Application Note AN578, "Use of the SSP

Module in the I2C Multi-Master Environment." ................... 63

Architecture

PIC16C63A/PIC16C73B Block Diagram ...................... 5

PIC16C65B/PIC16C74B Block Diagram ...................... 6

Assembler

MPASM Assembler .................................................. 147

Loading the SSPBUF register ................................... 58

Code Protection ....................................................... 127, 141

Compare (CCP Module) .................................................... 49

Block Diagram ........................................................... 49

CCP Pin Configuration .............................................. 49

CCPR1H:CCPR1L Registers .................................... 49

Software Interrupt ...................................................... 49

Special Event Trigger .......................................... 43, 49

Timer1 Mode Selection .............................................. 49

Configuration Bits ............................................................ 127

Conversion Considerations .............................................. 187

B

Banking, Data Memory ................................................ 11, 16

Baud Rate Generator ......................................................... 73

BF .................................................................... 54, 64, 79, 82

Block Diagrams

Baud Rate Generator ................................................. 73

2

I C Master Mode ........................................................ 71

2

I C Module ................................................................. 63

2

SSP (I C Mode) ......................................................... 63

SSP (SPI Mode) ......................................................... 57

BOR. See Brown-out Reset

D

BRG ................................................................................... 73

Brown-out Reset (BOR) ................... 127, 131, 132, 133, 134

BOR Status (BOR Bit) ................................................ 23

Buffer Full bit, BF ............................................................... 64

Buffer Full Status bit, BF .................................................... 54

Bus Arbitration ................................................................... 90

Bus Collision

Section ....................................................................... 90

Bus Collision During a RESTART Condition ...................... 93

Bus Collision During a Start Condition ............................... 91

Bus Collision During a Stop Condition ............................... 94

D/A ..................................................................................... 54

Data Memory ..................................................................... 11

Bank Select (RP1:RP0 Bits) ................................ 11, 16

General Purpose Registers ....................................... 11

Register File Map ...................................................... 12

Special Function Registers ........................................ 13

Data/Address bit, D/A ........................................................ 54

DC Characteristics

PIC16C73 ................................................................ 152

PIC16C74 ................................................................ 152

Development Support ...................................................... 145

Development Tools .......................................................... 145

Device Differences ........................................................... 187

Direct Addressing .............................................................. 25

1999 Microchip Technology Inc.

Preliminary

DS30275A-page 189

PIC16C77X

Restart Condition Flowchart ...................................... 77

Slave Mode ................................................................ 64

Slave Reception ........................................................ 65

Slave Transmission ................................................... 65

SSPBUF .................................................................... 64

Start Condition Flowchart .......................................... 75

Stop Condition Flowchart ........................................... 88

Stop Condition Receive or Transmit timing ............... 87

Stop Condition timing ................................................. 87

Waveforms for 7-bit Reception .................................. 65

Waveforms for 7-bit Transmission ............................. 66

E

Errata ...................................................................................4

External Power-on Reset Circuit ......................................132

F

Firmware Instructions .......................................................143

Flowcharts

Acknowledge ..............................................................86

Master Receiver .........................................................83

Master Transmit .........................................................80

Restart Condition .......................................................77

Start Condition ...........................................................75

Stop Condition ...........................................................88

FSR Register ..........................................................13, 14, 15

Fuzzy Logic Dev. System (fuzzyTECH -MP) ..................147

2

I C Module Address Register, SSPADD ........................... 64

I C Slave Mode .................................................................. 64

2

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ......... 145

ID Locations ............................................................. 127, 141

In-Circuit Serial Programming (ICSP) ...................... 127, 141

INDF .................................................................................. 15

INDF Register .............................................................. 13, 14

Indirect Addressing ............................................................ 25

FSR Register ............................................................. 11

Instruction Format ............................................................ 143

Instruction Set .................................................................. 143

Summary Table ....................................................... 144

INTCON ............................................................................. 15

INTCON Register ............................................................... 18

GIE Bit ....................................................................... 18

INTE Bit ..................................................................... 18

INTF Bit ..................................................................... 18

PEIE Bit ..................................................................... 18

RBIE Bit ..................................................................... 18

RBIF Bit ............................................................... 18, 30

T0IE Bit ...................................................................... 18

T0IF Bit ...................................................................... 18

G

GCE ...................................................................................56

General Call Address Sequence ........................................69

General Call Address Support ...........................................69

General Call Enable bit, GCE ............................................56

I

I/O Ports .............................................................................27

2

I C ......................................................................................63

2

I C Master Mode Receiver Flowchart ................................83

2

I C Master Mode Reception ...............................................82

2

I C Master Mode Restart Condition ...................................76

2

I C Mode Selection ............................................................63

2

I C Module

Acknowledge Flowchart .............................................86

Acknowledge Sequence timing ..................................85

Addressing .................................................................64

Baud Rate Generator .................................................73

Block Diagram ............................................................71

BRG Block Diagram ...................................................73

BRG Reset due to SDA Collision ...............................92

BRG Timing ...............................................................73

Bus Arbitration ...........................................................90

Bus Collision ..............................................................90

Acknowledge ......................................................90

Restart Condition ...............................................93

Restart Condition Timing (Case1) ......................93

Restart Condition Timing (Case2) ......................93

Start Condition ...................................................91

Start Condition Timing ................................. 91, 92

Stop Condition ...................................................94

Stop Condition Timing (Case1) ..........................94

Stop Condition Timing (Case2) ..........................94

Transmit Timing .................................................90

Bus Collision timing ....................................................90

Clock Arbitration .........................................................89

Clock Arbitration Timing (Master Transmit) ................89

Conditions to not give ACK Pulse ..............................64

General Call Address Support ...................................69

Master Mode ..............................................................71

Master Mode 7-bit Reception timing ..........................84

Master Mode Operation .............................................72

Master Mode Start Condition .....................................74

Master Mode Transmission ........................................79

Master Mode Transmit Sequence ..............................72

Master Transmit Flowchart ........................................80

Multi-Master Communication .....................................90

Multi-master Mode .....................................................72

Operation ...................................................................63

Repeat Start Condition timing ....................................76

2

Inter-Integrated Circuit (I C) .............................................. 53

internal sampling switch (Rss) impedence ...................... 123

Interrupt Sources ..................................................... 127, 137

Block Diagram ......................................................... 137

Capture Complete (CCP) ........................................... 48

Compare Complete (CCP) ......................................... 49

Interrupt on Change (RB7:RB4 ) ............................... 30

RB0/INT Pin, External ...................................... 7, 8, 138

TMR0 Overflow .................................................. 40, 138

TMR1 Overflow .................................................... 41, 43

TMR2 to PR2 Match .................................................. 46

TMR2 to PR2 Match (PWM) ................................ 45, 50

USART Receive/Transmit Complete ......................... 97

Interrupts, Context Saving During .................................... 138

Interrupts, Enable Bits

A/D Converter Enable (ADIE Bit) ............................... 19

CCP1 Enable (CCP1IE Bit) ................................. 19, 48

CCP2 Enable (CCP2IE Bit) ....................................... 21

Global Interrupt Enable (GIE Bit) ....................... 18, 137

Interrupt on Change (RB7:RB4) Enable

(RBIE Bit) ........................................................... 18, 138

Peripheral Interrupt Enable (PEIE Bit) ....................... 18

PSP Read/Write Enable (PSPIE Bit) ......................... 19

RB0/INT Enable (INTE Bit) ........................................ 18

SSP Enable (SSPIE Bit) ............................................ 19

TMR0 Overflow Enable (T0IE Bit) ............................. 18

TMR1 Overflow Enable (TMR1IE Bit) ........................ 19

TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19

USART Receive Enable (RCIE Bit) ........................... 19

USART Transmit Enable (TXIE Bit) ........................... 19

DS30275A-page 190

Preliminary

1999 Microchip Technology Inc.

PIC16C77X

Interrupts, Flag Bits

A/D Converter Flag (ADIF Bit) ................................... 20

PCON Register .......................................................... 23, 133

BOR Bit ...................................................................... 23

POR Bit ...................................................................... 23

PICDEM-1 Low-Cost PICmicro Demo Board .................. 146

PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 146

PICDEM-3 Low-Cost PIC16CXXX Demo Board ............. 146

PICSTART Plus Entry Level Development System ...... 145

PIE1 Register .................................................................... 19

ADIE Bit ..................................................................... 19

CCP1IE Bit ................................................................ 19

PSPIE Bit ................................................................... 19

RCIE Bit ..................................................................... 19

SSPIE Bit ................................................................... 19

TMR1IE Bit ................................................................ 19

TMR2IE Bit ................................................................ 19

TXIE Bit ..................................................................... 19

PIE2 Register .................................................................... 21

CCP2IE Bit ................................................................ 21

Pinout Descriptions

CCP1 Flag (CCP1IF Bit) ................................ 20, 48, 49

CCP2 Flag (CCP2IF Bit) ............................................ 22

Interrupt on Change (RB7:RB4) Flag

(RBIF Bit) ..................................................... 18, 30, 138

PSP Read/Write Flag (PSPIF Bit) .............................. 20

RB0/INT Flag (INTF Bit) ............................................. 18

SSP Flag (SSPIF Bit) ................................................. 20

TMR0 Overflow Flag (T0IF Bit) .......................... 18, 138

TMR1 Overflow Flag (TMR1IF Bit) ............................ 20

TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20

USART Receive Flag (RCIF Bit) ................................ 20

USART Transmit Flag (TXIE Bit) ............................... 20

K

KeeLoq Evaluation and Programming Tools ................. 148

M

Master Clear (MCLR) ....................................................... 7, 8

MCLR Reset, Normal Operation .............. 131, 133, 134

MCLR Reset, SLEEP ............................... 131, 133, 134

Memory Organization

Data Memory ............................................................. 11

Program Memory ....................................................... 11

MPLAB Integrated Development Environment Software . 147

Multi-Master Communication ............................................. 90

Multi-Master Mode ............................................................. 72

PIC16C63A/PIC16C73B .............................................. 7

PIC16C65B/PIC16C74B .............................................. 8

PIR1 Register .................................................................... 20

ADIF Bit ..................................................................... 20

CCP1IF Bit ................................................................. 20

PSPIF Bit ................................................................... 20

RCIF Bit ..................................................................... 20

SSPIF Bit ................................................................... 20

TMR1IF Bit ................................................................ 20

TMR2IF Bit ................................................................ 20

TXIF Bit ...................................................................... 20

PIR2 Register .................................................................... 22

CCP2IF Bit ................................................................. 22

Pointer, FSR ...................................................................... 25

POR. See Power-on Reset

PORTA ...................................................................... 7, 8, 15

Analog Port Pins ...................................................... 7, 8

Initialization ................................................................ 27

PORTA Register ........................................................ 27

RA3:RA0 and RA5 Port Pins ..................................... 28

RA4/T0CKI Pin .................................................. 7, 8, 28

RA5/SS/AN4 Pin .......................................................... 8

TRISA Register .......................................................... 27

PORTA Register ........................................................ 13, 126

PORTB ...................................................................... 7, 8, 15

Initialization ................................................................ 29

PORTB Register ........................................................ 29

Pull-up Enable (RBPU Bit) ......................................... 17

RB0/INT Edge Select (INTEDG Bit) .......................... 17

RB0/INT Pin, External ..................................... 7, 8, 138

RB3:RB0 Port Pins .................................................... 29

RB7:RB4 Interrupt on Change ................................. 138

RB7:RB4 Interrupt on Change Enable (RBIE Bit) .... 18,

138

O

OPCODE Field Descriptions ............................................ 143

OPTION_REG Register ..................................................... 17

INTEDG Bit ................................................................ 17

PS2:PS0 Bits ....................................................... 17, 39

PSA Bit ................................................................. 17, 39

RBPU Bit .................................................................... 17

T0CS Bit ............................................................... 17, 39

T0SE Bit ............................................................... 17, 39

OSC1/CLKIN Pin ............................................................. 7, 8

OSC2/CLKOUT Pin ......................................................... 7, 8

Oscillator Configuration .................................................... 128

HS .................................................................... 128, 133

LP ..................................................................... 128, 133

RC ............................................................ 128, 130, 133

XT .................................................................... 128, 133

Oscillator, Timer1 ......................................................... 41, 43

Oscillator, WDT ................................................................ 139

P

P ......................................................................................... 54

Packaging ........................................................................ 175

Paging, Program Memory ............................................ 11, 24

Parallel Slave Port (PSP) ......................................... 9, 34, 37

Block Diagram ............................................................ 37

RE0/RD/AN5 Pin .............................................. 9, 36, 37

RE1/WR/AN6 Pin ............................................. 9, 36, 37

RE2/CS/AN7 Pin .............................................. 9, 36, 37

Read Waveforms ....................................................... 38

Read/Write Enable (PSPIE Bit) .................................. 19

Read/Write Flag (PSPIF Bit) ...................................... 20

Select (PSPMODE Bit) .................................. 34, 35, 37

Write Waveforms ....................................................... 37

PCL Register ................................................................ 13, 14

PCLATH Register .................................................. 13, 14, 15

RB7:RB4 Interrupt on Change Flag (RBIF Bit) ... 18,30,

138

RB7:RB4 Port Pins .................................................... 30

TRISB Register .......................................................... 29

PORTB Register ........................................................ 13, 126

PORTC ...................................................................... 7, 9, 15

Block Diagram ........................................................... 32

Initialization ................................................................ 32

PORTC Register ........................................................ 32

RC0/T1OSO/T1CKI Pin ........................................... 7, 9

RC1/T1OSI/CCP2 Pin ............................................. 7, 9

RC2/CCP1 Pin ......................................................... 7, 9

RC3/SCK/SCL Pin ................................................... 7, 9

1999 Microchip Technology Inc.

Preliminary

DS30275A-page 191

PIC16C77X

RC4/SDI/SDA Pin ....................................................7, 9

RC5/SDO Pin ...........................................................7, 9

RC6/TX/CK Pin .................................................. 7, 9, 98

RC7/RX/DT Pin ............................................ 7, 9, 98, 99

TRISC Register .................................................... 32, 97

PORTC Register ................................................................13

PORTD ..................................................................... 9, 15, 37

Block Diagram ............................................................34

Parallel Slave Port (PSP) Function ............................34

PORTD Register ........................................................34

TRISD Register ..........................................................34

PORTD Register ................................................................13

PORTE ...........................................................................9, 15

Analog Port Pins .............................................. 9, 36, 37

Block Diagram ............................................................35

Input Buffer Full Status (IBF Bit) ................................35

Input Buffer Overflow (IBOV Bit) ................................35

Output Buffer Full Status (OBF Bit) ............................35

PORTE Register ........................................................35

PSP Mode Select (PSPMODE Bit) ................34, 35, 37

RE0/RD/AN5 Pin .............................................. 9, 36, 37

RE1/WR/AN6 Pin ............................................. 9, 36, 37

RE2/CS/AN7 Pin .............................................. 9, 36, 37

TRISE Register ..........................................................35

PORTE Register ........................................................ 13, 126

Postscaler, Timer2

Select (TOUTPS3:TOUTPS0 Bits) ............................45

Postscaler, WDT ................................................................39

Assignment (PSA Bit) .......................................... 17, 39

Block Diagram ............................................................40

Rate Select (PS2:PS0 Bits) ................................. 17, 39

Switching Between Timer0 and WDT ........................40

Power-on Reset (POR) ....................127, 131, 132, 133, 134

Oscillator Start-up Timer (OST) ....................... 127, 132

POR Status (POR Bit) ................................................23

Power Control (PCON) Register ..............................133

Power-down (PD Bit) .................................................16

Power-on Reset Circuit, External .............................132

Power-up Timer (PWRT) ................................. 127, 132

Time-out (TO Bit) .......................................................16

Time-out Sequence ..................................................133

Time-out Sequence on Power-up ....................135, 136

PR2 Register ......................................................................14

Prescaler, Capture .............................................................48

Prescaler, Timer0 ...............................................................39

Assignment (PSA Bit) .......................................... 17, 39

Block Diagram ............................................................40

Rate Select (PS2:PS0 Bits) ................................. 17, 39

Switching Between Timer0 and WDT ........................40

Prescaler, Timer1 ...............................................................42

Select (T1CKPS1:T1CKPS0 Bits) ..............................41

Prescaler, Timer2 ...............................................................50

Select (T2CKPS1:T2CKPS0 Bits) ..............................45

PRO MATE II Universal Programmer ............................145

Product Identification System ...........................................199

Program Counter

Programming, Device Instructions ................................... 143

PWM (CCP Module) .......................................................... 50

Block Diagram ........................................................... 50

CCPR1H:CCPR1L Registers ..................................... 50

Duty Cycle ................................................................. 50

Example Frequencies/Resolutions ............................ 51

Output Diagram ......................................................... 50

Period ........................................................................ 50

Set-Up for PWM Operation ........................................ 51

TMR2 to PR2 Match ............................................ 45, 50

TMR2 to PR2 Match Enable (TMR2IE Bit) ................ 19

TMR2 to PR2 Match Flag (TMR2IF Bit) ..................... 20

Q

Q-Clock .............................................................................. 50

R

R/W .................................................................................... 54

R/W bit ............................................................................... 64

R/W bit ............................................................................... 65

RCE,Receive Enable bit, RCE ........................................... 56

RCREG .............................................................................. 15

RCSTA Register .......................................................... 15, 98

CREN Bit ................................................................... 98

FERR Bit .................................................................... 98

OERR Bit ................................................................... 98

RX9 Bit ...................................................................... 98

RX9D Bit .................................................................... 98

SPEN Bit .............................................................. 97, 98

SREN Bit ................................................................... 98

Read/Write bit, R/W ........................................................... 54

Receive Overflow Indicator bit, SSPOV ............................. 55

Register File ....................................................................... 11

Register File Map ............................................................... 12

Registers

FSR

Summary ........................................................... 15

INDF

Summary ........................................................... 15

INTCON

Summary ........................................................... 15

PCL

Summary ........................................................... 15

PCLATH

Summary ........................................................... 15

PORTB

Summary ........................................................... 15

SSPSTAT .................................................................. 54

STATUS

Summary ........................................................... 15

Summary ................................................................... 13

TMR0

Summary ........................................................... 15

TRISB

Summary ........................................................... 15

Reset ....................................................................... 127, 131

Block Diagram ......................................................... 131

Reset Conditions for All Registers ........................... 134

Reset Conditions for PCON Register ...................... 133

Reset Conditions for Program Counter .................... 133

Reset Conditions for STATUS Register ................... 133

Restart Condition Enabled bit, RSE ................................... 56

Revision History ............................................................... 187

RSE ................................................................................... 56

PCL Register ..............................................................24

PCLATH Register .............................................. 24, 138

Reset Conditions ......................................................133

Program Memory ...............................................................11

Interrupt Vector ..........................................................11

Paging ..................................................................11, 24

Program Memory Map ...............................................11

Reset Vector ..............................................................11

Program Verification .........................................................141

Programming Pin (Vpp) ....................................................7, 8

DS30275A-page 192

Preliminary

1999 Microchip Technology Inc.

PIC16C77X

SSP Module

S

SPI Master Mode ....................................................... 59

SPI Master./Slave Connection ................................... 58

SPI Slave Mode ......................................................... 60

SSPCON1 Register ................................................... 63

SSP Overflow Detect bit, SSPOV ...................................... 64

SSPADD Register .............................................................. 14

SSPBUF ...................................................................... 15, 64

SSPBUF Register .............................................................. 13

SSPCON Register ............................................................. 13

SSPCON1 ................................................................... 55, 63

SSPCON2 ......................................................................... 56

SSPEN .............................................................................. 55

SSPIF ................................................................................ 65

SSPM3:SSPM0 ................................................................. 55

SSPOV .................................................................. 55, 64, 82

SSPSTAT .................................................................... 54, 64

SSPSTAT Register ............................................................ 14

Stack .................................................................................. 24

Start bit (S) ........................................................................ 54

Start Condition Enabled bit, SAE ....................................... 56

STATUS Register ...................................................... 16, 138

C Bit ........................................................................... 16

DC Bit ........................................................................ 16

IRP Bit ....................................................................... 16

PD Bit ........................................................................ 16

RP1:RP0 Bits ............................................................. 16

TO Bit ........................................................................ 16

Z Bit ........................................................................... 16

Stop bit (P) ......................................................................... 54

Stop Condition Enable bit .................................................. 56

Synchronous Serial Port .................................................... 53

Synchronous Serial Port Enable bit, SSPEN ..................... 55

Synchronous Serial Port Mode Select bits,

SAE .................................................................................... 56

SCK .................................................................................... 57

SCL .................................................................................... 64

SDA .................................................................................... 64

SDI ..................................................................................... 57

SDO ................................................................................... 57

SEEVAL Evaluation and Programming System ............ 147

Serial Clock, SCK .............................................................. 57

Serial Clock, SCL ............................................................... 64

Serial Data Address, SDA .................................................. 64

Serial Data In, SDI ............................................................. 57

Serial Data Out, SDO ......................................................... 57

Slave Select Synchronization ............................................ 60

Slave Select, SS ................................................................ 57

SLEEP ............................................................. 127, 131, 140

SMP ................................................................................... 54

Software Simulator (MPLAB-SIM) ................................... 147

SPBRG Register ................................................................ 14

SPE .................................................................................... 56

Special Features of the CPU ........................................... 127

Special Function Registers ................................................ 13

PIC16C73 .................................................................. 13

PIC16C73A ................................................................ 13

PIC16C74 .................................................................. 13

PIC16C74A ................................................................ 13

PIC16C76 .................................................................. 13

PIC16C77 .................................................................. 13

Speed, Operating ................................................................. 1

SPI

Master Mode .............................................................. 59

Serial Clock ................................................................ 57

Serial Data In ............................................................. 57

Serial Data Out .......................................................... 57

Serial Peripheral Interface (SPI) ................................ 53

Slave Select ............................................................... 57

SPI clock .................................................................... 59

SPI Mode ................................................................... 57

SPI Clock Edge Select, CKE ............................................. 54

SPI Data Input Sample Phase Select, SMP ...................... 54

SPI Master/Slave Connection ............................................ 58

SPI Module

SSPM3:SSPM0 ................................................................. 55

T

T1CON .............................................................................. 15

T1CON Register .......................................................... 15, 41

T1CKPS1:T1CKPS0 Bits ........................................... 41

T1OSCEN Bit ............................................................ 41

T1SYNC Bit ............................................................... 41

TMR1CS Bit ............................................................... 41

TMR1ON Bit .............................................................. 41

T2CON Register .......................................................... 15, 45

T2CKPS1:T2CKPS0 Bits ........................................... 45

TMR2ON Bit .............................................................. 45

TOUTPS3:TOUTPS0 Bits ......................................... 45

Timer0 ............................................................................... 39

Block Diagram ........................................................... 39

Clock Source Edge Select (T0SE Bit) ................. 17, 39

Clock Source Select (T0CS Bit) .......................... 17, 39

Overflow Enable (T0IE Bit) ........................................ 18

Overflow Flag (T0IF Bit) .................................... 18, 138

Overflow Interrupt .............................................. 40, 138

RA4/T0CKI Pin, External Clock ............................... 7, 8

Timer1 ............................................................................... 41

Block Diagram ........................................................... 42

Capacitor Selection ................................................... 43

Clock Source Select (TMR1CS Bit) ........................... 41

External Clock Input Sync (T1SYNC Bit) ................... 41

Module On/Off (TMR1ON Bit) ................................... 41

Oscillator .............................................................. 41, 43

Oscillator Enable (T1OSCEN Bit) .............................. 41

Overflow Enable (TMR1IE Bit) .................................. 19

Overflow Flag (TMR1IF Bit) ....................................... 20

Master/Slave Connection ........................................... 58

Slave Mode ................................................................ 60

Slave Select Synchronization .................................... 60

Slave Synch Timnig ................................................... 60

SS ...................................................................................... 57

SSP .................................................................................... 53

Block Diagram (SPI Mode) ........................................ 57

Enable (SSPIE Bit) ..................................................... 19

Flag (SSPIF Bit) ......................................................... 20

RA5/SS/AN4 Pin .......................................................... 8

RC3/SCK/SCL Pin ................................................... 7, 9

RC4/SDI/SDA Pin .................................................... 7, 9

RC5/SDO Pin ........................................................... 7, 9

SPI Mode ................................................................... 57

SSPADD .................................................................... 64

SSPBUF ............................................................... 59, 64

SSPCON1 .................................................................. 55

SSPCON2 .................................................................. 56

SSPSR ................................................................. 59, 64

SSPSTAT ............................................................. 54, 64

TMR2 Output for Clock Shift ................................ 45, 46

2

SSP I C

2

SSP I C Operation ..................................................... 63

1999 Microchip Technology Inc.

Preliminary

DS30275A-page 193

PIC16C77X

Overflow Interrupt ................................................ 41, 43

RC0/T1OSO/T1CKI Pin ...........................................7, 9

RC1/T1OSI/CCP2 Pin ..............................................7, 9

Special Event Trigger (CCP) ................................ 43, 49

T1CON Register ........................................................41

TMR1H Register ........................................................41

TMR1L Register .........................................................41

Timer2

Block Diagram ............................................................46

PR2 Register ........................................................ 45, 50

SSP Clock Shift .................................................... 45, 46

T2CON Register ........................................................45

TMR2 Register ...........................................................45

TMR2 to PR2 Match Enable (TMR2IE Bit) ................19

TMR2 to PR2 Match Flag (TMR2IF Bit) .....................20

TMR2 to PR2 Match Interrupt ........................ 45, 46, 50

Timing Diagrams

PSPMODE Bit ................................................ 34, 35, 37

TXREG .............................................................................. 15

TXSTA Register ................................................................. 97

BRGH Bit ............................................................. 97, 99

CSRC Bit ................................................................... 97

SYNC Bit ................................................................... 97

TRMT Bit .................................................................... 97

TX9 Bit ....................................................................... 97

TX9D Bit .................................................................... 97

TXEN Bit .................................................................... 97

U

UA ...................................................................................... 54

Universal Synchronous Asynchronous Receiver Transmitter

(USART)

Asynchronous Receiver

Setting Up Reception ....................................... 104

Timing Diagram ............................................... 105

Update Address, UA .......................................................... 54

USART ............................................................................... 97

Asynchronous Mode ................................................ 102

Master Transmission ....................................... 103

Receive Block Diagram ................................... 105

Transmit Block Diagram .................................. 102

Baud Rate Generator (BRG) ..................................... 99

Baud Rate Error, Calculating ............................. 99

Baud Rate Formula ........................................... 99

Baud Rates, Asynchronous Mode (BRGH=0) . 100

Baud Rates, Asynchronous Mode (BRGH=1) . 101

Baud Rates, Synchronous Mode ..................... 100

High Baud Rate Select (BRGH Bit) ............. 97, 99

Sampling ............................................................ 99

Clock Source Select (CSRC Bit) ................................ 97

Continuous Receive Enable (CREN Bit) .................... 98

Framing Error (FERR Bit) .......................................... 98

Mode Select (SYNC Bit) ............................................ 97

Overrun Error (OERR Bit) .......................................... 98

RC6/TX/CK Pin ........................................................ 7, 9

RC7/RX/DT Pin ........................................................ 7, 9

RCSTA Register ........................................................ 98

Receive Data, 9th bit (RX9D Bit) ............................... 98

Receive Enable (RCIE Bit) ........................................ 19

Receive Enable, 9-bit (RX9 Bit) ................................. 98

Receive Flag (RCIF Bit) ............................................. 20

Serial Port Enable (SPEN Bit) ............................. 97, 98

Single Receive Enable (SREN Bit) ............................ 98

Synchronous Master Mode ...................................... 107

Reception ........................................................ 109

Transmission ................................................... 108

Synchronous Slave Mode ........................................ 110

Transmit Data, 9th Bit (TX9D) ................................... 97

Transmit Enable (TXEN Bit) ...................................... 97

Transmit Enable (TXIE Bit) ........................................ 19

Transmit Enable, Nine-bit (TX9 Bit) ........................... 97

Transmit Flag (TXIE Bit) ............................................ 20

Transmit Shift Register Status (TRMT Bit) ................ 97

TXSTA Register ......................................................... 97

Acknowledge Sequence Timing .................................85

Baud Rate Generator with Clock Arbitration ..............73

BRG Reset Due to SDA Collision ..............................92

Brown-out Reset ......................................................163

Bus Collision

Start Condition Timing .......................................91

Bus Collision During a Restart Condition (Case 1) ....93

Bus Collision During a Restart Condition (Case2) .....93

Bus Collision During a Start Condition (SCL = 0) ......92

Bus Collision During a Stop Condition .......................94

Bus Collision for Transmit and Acknowledge .............90

Capture/Compare/PWM ...........................................169

CLKOUT and I/O ......................................................162

External Clock Timing ..............................................161

2

I C Master Mode First Start bit timing ........................74

2

I C Master Mode Reception timing ............................84

2

I C Master Mode Transmission timing .......................81

Master Mode Transmit Clock Arbitration ....................89

Power-up Timer .......................................................163

Repeat Start Condition ...............................................76

Reset ........................................................................163

Slave Synchronization ...............................................60

Start-up Timer ..........................................................163

Stop Condition Receive or Transmit ..........................87

Time-out Sequence on Power-up ....................135, 136

Timer0 ......................................................................168

Timer1 ......................................................................168

USART Asynchronous Master Transmission ...........103

USART Synchronous Receive .................................171

USART Synchronous Reception ..............................109

USART Synchronous Transmission ................ 108, 171

USART, Asynchronous Reception ...........................105

Wake-up from SLEEP via Interrupt ..........................141

Watchdog Timer .......................................................163

TMR0 .................................................................................15

TMR0 Register ...................................................................13

TMR1H ...............................................................................15

TMR1H Register ................................................................13

TMR1L ...............................................................................15

TMR1L Register .................................................................13

TMR2 .................................................................................15

TMR2 Register ...................................................................13

TRISA Register .......................................................... 14, 126

TRISB Register .......................................................... 14, 126

TRISC Register ..................................................................14

TRISD Register ..................................................................14

TRISE Register .................................................... 14, 35, 126

IBF Bit ........................................................................35

IBOV Bit .....................................................................35

OBF Bit ......................................................................35

DS30275A-page 194

Preliminary

1999 Microchip Technology Inc.

PIC16C77X

W

W Register ....................................................................... 138

Wake-up from SLEEP .............................................. 127, 140

Interrupts .......................................................... 133, 134

MCLR Reset ............................................................ 134

Timing Diagram ........................................................ 141

WDT Reset .............................................................. 134

Watchdog Timer (WDT) ........................................... 127, 139

Block Diagram .......................................................... 139

Enable (WDTE Bit) ................................................... 139

Programming Considerations .................................. 139

RC Oscillator ............................................................ 139

Time-out Period ....................................................... 139

WDT Reset, Normal Operation ................ 131, 133, 134

WDT Reset, SLEEP ......................................... 133, 134

Waveform for General Call Address Sequence ................. 69

WCOL .................................................. 55, 74, 79, 82, 85, 87

WCOL Status Flag ............................................................. 74

Write Collision Detect bit, WCOL ....................................... 55

WWW, On-Line Support ...................................................... 4

1999 Microchip Technology Inc.

Preliminary

DS30275A-page 195

PIC16C77X

T0CS ..................................................OPTION_REG<5>

T0IE ...................................................INTCON<5>

T0IF ...................................................INTCON<2>

T0SE ..................................................OPTION_REG<4>

T1CKPS1:T1CKPS0 ..........................T1CON<5:4>

T1OSCEN ..........................................T1CON<3>

T1SYNC .............................................T1CON<2>

T2CKPS1:T2CKPS0 ..........................T2CON<1:0>

TMR1CS ............................................T1CON<1>

TMR1IE ..............................................PIE1<0>

TMR1IF ..............................................PIR1<0>

TMR1ON ............................................T1CON<0>

TMR2IE ..............................................PIE1<1>

TMR2IF ..............................................PIR1<1>

TMR2ON ............................................T2CON<2>

TO ......................................................STATUS<4>

TOUTPS3:TOUTPS0 .........................T2CON<6:3>

TRMT .................................................TXSTA<1>

TX9 ....................................................TXSTA<6>

TX9D ..................................................TXSTA<0>

TXEN .................................................TXSTA<5>

TXIE ...................................................PIE1<4>

TXIF ...................................................PIR1<4>

UA ......................................................SSPSTAT<1>

WCOL ................................................SSPCON<7>

Z .........................................................STATUS<2>

BIT/REGISTER CROSS-REFERENCE

LIST

ADCS1:ADCS0 ..................................ADCON0<7:6>

ADIE ...................................................PIE1<6>

ADIF ...................................................PIR1<6>

ADON .................................................ADCON0<0>

BF .......................................................SSPSTAT<0>

BOR ...................................................PCON<0>

BRGH .................................................TXSTA<2>

C .........................................................STATUS<0>

CCP1IE ..............................................PIE1<2>

CCP1IF ..............................................PIR1<2>

CCP1M3:CCP1M0 .............................CCP1CON<3:0>

CCP1X:CCP1Y ..................................CCP1CON<5:4>

CCP2IE ..............................................PIE2<0>

CCP2IF ..............................................PIR2<0>

CCP2M3:CCP2M0 .............................CCP2CON<3:0>

CCP2X:CCP2Y ..................................CCP2CON<5:4>

CHS2:CHS0 .......................................ADCON0<5:3>

CKE ....................................................SSPSTAT<6>

CKP ....................................................SSPCON<4>

CREN .................................................RCSTA<4>

CSRC .................................................TXSTA<7>

D/A .....................................................SSPSTAT<5>

DC ......................................................STATUS<1>

FERR .................................................RCSTA<2>

GIE .....................................................INTCON<7>

GO/DONE ..........................................ADCON0<2>

IBF ......................................................TRISE<7>

IBOV ...................................................TRISE<5>

INTE ...................................................INTCON<4>

INTEDG ..............................................OPTION_REG<6>

INTF ...................................................INTCON<1>

IRP .....................................................STATUS<7>

OBF ....................................................TRISE<6>

OERR .................................................RCSTA<1>

P .........................................................SSPSTAT<4>

PCFG2:PCFG0 ..................................ADCON1<2:0>

PD ......................................................STATUS<3>

PEIE ...................................................INTCON<6>

POR ...................................................PCON<1>

PS2:PS0 .............................................OPTION_REG<2:0>

PSA ....................................................OPTION_REG<3>

PSPIE .................................................PIE1<7>

PSPIF .................................................PIR1<7>

PSPMODE .........................................TRISE<4>

R/W ....................................................SSPSTAT<2>

RBIE ...................................................INTCON<3>

RBIF ...................................................INTCON<0>

RBPU .................................................OPTION_REG<7>

RCIE ...................................................PIE1<5>

RCIF ...................................................PIR1<5>

RP1:RP0 ............................................STATUS<6:5>

RX9 ....................................................RCSTA<6>

RX9D ..................................................RCSTA<0>

S .........................................................SSPSTAT<3>

SMP ...................................................SSPSTAT<7>

SPEN .................................................RCSTA<7>

SREN .................................................RCSTA<5>

SSPEN ...............................................SSPCON<5>

SSPIE .................................................PIE1<3>

SSPIF .................................................PIR1<3>

SSPM3:SSPM0 ..................................SSPCON<3:0>

SSPOV ...............................................SSPCON<6>

SYNC .................................................TXSTA<4>

DS30275A-page 196

Preliminary

1999 Microchip Technology Inc.

PIC16C77X

Systems Information and Upgrade Hot Line

ON-LINE SUPPORT

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip’s development systems software products.

Plus, this line provides information on how customers

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1-602-786-7302 for the rest of the world.

981103

ConnectingtotheMicrochipInternetWebSite

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The file transfer site is available by using an FTP ser-

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The web site and file transfer site provide a variety of

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1998 Microchip Technology Inc.

DS30275A-page 197

PIC16C77X

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

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DS30275A-page 198

1998 Microchip Technology Inc.

PIC16C77X

PIC16C77X PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

X

/XX

XXX

PART NO.

Device

-XX

Examples:

Frequency Temperature Package

Range Range

Pattern

g)

PIC16C774 -04/P 301 = Commercial temp.,

PDIP package, 4 MHz, normal VDD limits, QTP

pattern #301.

h)

i)

PIC16LC773 - 04I/SO = Industrial temp., SOIC

package, 200 kHz, Extended VDD limits.

Device

PIC16C77X⁽¹⁾, PIC16C77XT⁽²⁾;VDD range 4.0V to 5.5V

PIC16LC77X⁽¹⁾, PIC16LC77XT⁽²⁾;VDD range 2.5V to 5.5V

PIC16C774 - 20I/P = Industrial temp., PDIP

package, 20MHz, normal VDD limits.

Frequency Range

04

20

= 4 MHz

= 20 MHz

Note 1:

C

= CMOS

LC = Low Power CMOS

= in tape and reel - SOIC, SSOP,

PLCC,

MQFP, TQFP packages only.

b = blank

Temperature Range

b⁽³⁾

I

=

0°C to

70°C (Commercial)

T

-40°C to +85°C (Industrial)

2:

Package

JW

PQ

PT

SO

SP

P

=

Windowed CERDIP/Ceramic

MQFP (Metric PQFP)

TQFP (Thin Quad Flatpack)

SOIC

Skinny plastic dip

PDIP

L

PLCC

SSOP

SS

Pattern

QTP, SQTP, Code or Special Requirements

(blank otherwise)

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of

each oscillator type (including LC devices).

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

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1999 Microchip Technology Inc.

Advance Information

DS30275A-page 199

WORLDWIDE SALES AND SERVICE

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Corporate Office

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®

Our field-programmable PICmicro 8-

®

bit MCUs, KEELOQ code hopping

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DS30275A-page 200

1999 Microchip Technology Inc.


型号：	PIC16C773-04I/PT
厂家：	MICROCHIP
描述：	28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D 40分之28引脚， 8位CMOS微控制器W / 12位A / D 微控制器
文件：	总200页 (文件大小：3606K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16C773-04I/PT [MICROCHIP]

相关型号：

PIC16C773-04I/SO

PIC16C773-04I/SP

PIC16C773-04I/SS

PIC16C773-20/JW

PIC16C773-20/L

PIC16C773-20/P

PIC16C773-20/PQ

PIC16C773-20/PT

PIC16C773-20/SO

PIC16C773-20/SP

PIC16C773-20/SS

PIC16C773-20I/JW