PIC16CE625-E/JW [MICROCHIP]
8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, CERDIP-18;型号: | PIC16CE625-E/JW |
厂家: | MICROCHIP |
描述: | 8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, CERDIP-18 可编程只读存储器 时钟 CD 微控制器 外围集成电路 |
文件: | 总113页 (文件大小:1143K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16CE62X
OTP 8-Bit CMOS MCU with EEPROM Data Memory
Devices included in this data sheet:
Pin Diagrams
• PIC16CE623
• PIC16CE624
• PIC16CE625
PDIP, SOIC, Windowed CERDIP
RA1/AN1
RA2/AN2/VREF
RA3/AN3
•1
18
RA0/AN0
17
2
3
4
5
6
7
8
9
High Performance RISC CPU:
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RA4/T0CKI
16
MCLR/VPP
15
14
13
12
11
10
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
VSS
RB0/INT
RB1
RB2
RB3
RB4
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
Device
Program
Memory
RAM
Data
EEPROM
Data
SSOP
Memory Memory
RA1/AN1
RA2/AN2/VREF
RA3/AN3
•1
2
20
RA0/AN0
19
18
17
16
15
14
13
PIC16CE623
PIC16CE624
PIC16CE625
512x14
1Kx14
2Kx14
96x8
96x8
128x8
128x8
128x8
OSC1/CLKIN
OSC2/CLKOUT
RA4/T0CKI
3
MCLR/VPP
4
VDD
VDD
RB7
RB6
RB5
RB4
VSS
5
VSS
6
RB0/INT
RB1
7
128x8
8
RB2
RB3
9
12
11
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
10
• Direct, Indirect and Relative addressing modes
Special Microcontroller Features (cont’d)
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Four user programmable ID locations
CMOS Technology:
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range
- 2.5V to 5.5V
• Commercial, industrial and extended temperature
range
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) (via two
pins)
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
1999 Microchip Technology Inc.
DS40182C-page 1
PIC16CE62X
Table of Contents
1.0 General Description...............................................................................................................................................3
2.0 PIC16CE62X Device Varieties ..............................................................................................................................5
3.0 Architectural Overview...........................................................................................................................................7
4.0 Memory Organization ..........................................................................................................................................11
5.0 I/O Ports...............................................................................................................................................................23
6.0 EEPROM Peripheral Operation...........................................................................................................................29
7.0 Timer0 Module.....................................................................................................................................................35
8.0 Comparator Module.............................................................................................................................................41
9.0 Voltage Reference Module ..................................................................................................................................47
10.0 Special Features of the CPU ...............................................................................................................................49
11.0 Instruction Set Summary .....................................................................................................................................65
12.0 Development Support..........................................................................................................................................77
13.0 Electrical Specifications.......................................................................................................................................83
14.0 Packaging Information.........................................................................................................................................97
Appendix A: Code for Accessing EEPROM Data Memory ........................................................................................103
Index ..........................................................................................................................................................................105
On Line Support ..........................................................................................................................................................107
Reader Response .......................................................................................................................................................108
PIC16CE62X Product Identification System ..............................................................................................................109
To Our Valued Customers
Most Current Data Sheet
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
•
Microchip’s Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
•
•
Fill out and mail in the reader response form in the back of this data sheet.
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We appreciate your assistance in making this a better document.
DS40182C-page 2
1999 Microchip Technology Inc.
PIC16CE62X
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
1.0
GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20-Pin EPROM-based
members of the versatile PICmicro® family of low-cost,
A UV-erasable CERDIP-packaged version is ideal for
code development, while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
high-performance,
microcontrollers with EEPROM data memory.
CMOS,
fully-static,
8-bit
All PICmicro® microcontrollers employ an advanced
RISC architecture. The PIC16CE62X family has
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a sin-
gle-cycle, except for program branches (which require
two cycles). A total of 35 instructions (reduced instruc-
tion set) are available. Additionally, a large register set
gives some of the architectural innovations used to
achieve a very high performance.
Table 1-1 shows the features of the PIC16CE62X
mid-range microcontroller families.
A simplified block diagram of the PIC16CE62X is
shown in Figure 3-1.
The PIC16CE62X series fits perfectly in applications
ranging from multi-pocket battery chargers to
low-power remote sensors. The EPROM technology
makes customization of application programs (detec-
tion levels, pulse generation, timers, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applica-
tions with space limitations. Low-cost, low-power,
high-performance, ease of use and I/O flexibility make
the PIC16CE62X very versatile.
PIC16CE62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16CE623 and PIC16CE624 have 96 bytes of
RAM. The PIC16CE625 has 128 bytes of RAM. Each
microcontroller contains a 128x8 EEPROM memory
array for storing non-volatile information, such as cali-
bration data or security codes. This memory has an
endurance of 1,000,000 erase/write cycles and a reten-
tion of 40 plus years.
1.1
Development Support
The PIC16CE62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler is also
available.
Each device has 13 I/O pins and an 8-bit timer/counter
with an 8-bit programmable prescaler. In addition, the
PIC16CE62X adds two analog comparators with a
programmable on-chip voltage reference module. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc).
PIC16CE62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power con-
sumption. There are four oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and reset.
1999 Microchip Technology Inc.
DS40182C-page 3
PIC16CE62X
TABLE 1-1:
PIC16CE62X FAMILY OF DEVICES
PIC16CE623
PIC16CE624
PIC16CE625
Clock
Maximum Frequency of Operation (MHz)
EPROM Program Memory (x14 words)
Data Memory (bytes)
EEPROM Data Memory (bytes)
Timer Module(s)
20
20
20
512
96
1K
96
2K
Memory
128
128
128
128
TMR0
2
TMR0
2
TMR0
2
Peripherals
Comparators(s)
Internal Reference Voltage
Interrupt Sources
Yes
4
Yes
4
Yes
4
I/O Pins
13
13
13
Voltage Range (Volts)
Brown-out Reset
2.5-5.5
Yes
2.5-5.5
Yes
2.5-5.5
Yes
Features
Packages
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
20-pin SSOP
20-pin SSOP
20-pin SSOP
®
All PICmicro Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capa-
bility. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40182C-page 4
1999 Microchip Technology Inc.
PIC16CE62X
2.3
Quick-Turn-Programming (QTP)
Devices
2.0
PIC16CE62X DEVICE
VARIETIES
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16CE62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.1
UV Erasable Devices
The UV erasable version, offered in the CERDIP pack-
age is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
2.4
Serialized Quick-Turn-Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Microchip’s
PICSTART
and
PRO MATE
programmers both support programming of the
PIC16CE62X.
2.2
One-Time-Programmable (OTP)
Devices
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1999 Microchip Technology Inc.
DS40182C-page 5
PIC16CE62X
NOTES:
DS40182C-page 6
1999 Microchip Technology Inc.
PIC16CE62X
The PIC16CE62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CE62X uses a Harvard architecture in
which program and data are accessed from separate
memories using separate buses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit wide
data word. Instruction opcodes are 14-bits wide making
it possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline over-
laps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single-cycle (200 ns @
20 MHz) except for program branches.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit
respectively, bit in subtraction. See the SUBLW and
SUBWFinstructions for examples.
The table below lists program memory (EPROM), data
memory (RAM) and non-volatile memory (EEPROM)
for each PIC16CE62X device.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
Device
Program
Memory
RAM
Data
EEPROM
Data
Memory Memory
PIC16CE623
PIC16CE624
PIC16CE625
512x14
1Kx14
2Kx14
96x8
96x8
128x8
128x8
128x8
128x8
The PIC16CE62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16CE62X family has an
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make program-
ming with the PIC16CE62X simple yet efficient. In addi-
tion, the learning curve is reduced significantly.
1999 Microchip Technology Inc.
DS40182C-page 7
PIC16CE62X
FIGURE 3-1:
BLOCK DIAGRAM
Data Memory
(RAM)
EEPROM DATA
MEMORY
Device
Program Memory
PIC16CE623
PIC16CE624
PIC16CE625
512 x 14
1K x 14
2K x 14
96 x 8
96 x 8
128 x 8
128 x 8
128 x 8
128 x 8
Voltage
Reference
13
8
Data Bus
RAM
Program Counter
EPROM
Program
Memory
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
RAM Addr (1)
9
Comparator
RA0/AN0
Addr MUX
Instruction reg
RA1/AN1
-
+
Indirect
Addr
7
Direct Addr
RA2/AN2/VREF
RA3/AN3
8
-
+
FSR reg
STATUS reg
TMR0
3
MUX
Power-up
Timer
RA4/T0CKI
Instruction
Decode &
Control
Oscillator
Start-up Timer
ALU
Power-on
Reset
Timing
Generation
W reg
I/O Ports
Watchdog
Timer
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
PORTB
MCLR/VPP VDD, VSS
EESCL
EESDA
EEVDD
EEPROM
Data
Memory
128 x 8
EEINTF
Note 1: Higher order bits are from the STATUS register.
DS40182C-page 8
1999 Microchip Technology Inc.
PIC16CE62X
TABLE 3-1:
Name
PIC16CE62X PINOUT DESCRIPTION
DIP/
SSOP
Pin #
I/O/P
Type
Buffer
Type
SOIC
Pin #
Description
OSC1/CLKIN
16
15
18
17
I
ST/CMOS Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
4
4
I/P
ST
Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
MCLR/VPP
PORTA is a bi-directional I/O port.
Analog comparator input
RA0/AN0
17
18
1
19
20
1
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RA1/AN1
Analog comparator input
RA2/AN2/VREF
RA3/AN3
Analog comparator input or VREF output
Analog comparator input /output
2
2
RA4/T0CKI
3
3
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
TTL/ST(1)
RB0/INT
6
7
I/O
RB0/INT can also be selected as an external
interrupt pin.
RB1
RB2
RB3
RB4
RB5
RB6
RB7
VSS
7
8
8
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
TTL
TTL
TTL
TTL
TTL
9
10
10
11
12
13
5
11
Interrupt on change pin.
12
Interrupt on change pin.
(2)
13
TTL/ST
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
(2)
14
TTL/ST
5,6
15,16
—
—
VDD
14
P
Legend:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
I = Input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1999 Microchip Technology Inc.
DS40182C-page 9
PIC16CE62X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (i.e., GOTO) then
two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
5. Instruction @
address SUB_1
Fetch SUB_1
Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
DS40182C-page 10
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
PIC16CE624
The PIC16CE62X has a 13-bit program counter capa-
ble of addressing an 8K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16CE623, 1K x 14 (0000h - 03FFh) for the
PIC16CE624 and 2K x 14 (0000h - 07FFh) for the
PIC16CE625 are physically implemented. Accessing a
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
location above these boundaries will cause
a
wrap-around within the first 512 14 space
x
(PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K
x 14 space (PIC16CE625). The reset vector is at 0000h
and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2, Figure 4-3).
Stack Level 8
Reset Vector
000h
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
Interrupt Vector
0004
0005
PIC16CE623
PC<12:0>
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
13
03FFh
0400h
Stack Level 1
Stack Level 2
1FFFh
Stack Level 8
FIGURE 4-3: PROGRAM MEMORY MAP
AND STACK FOR THE
Reset Vector
PIC16CE625
000h
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Interrupt Vector
0004
0005
Stack Level 1
Stack Level 2
On-chip Program
Memory
Stack Level 8
01FFh
0200h
Reset Vector
000h
1FFFh
Interrupt Vector
0004
0005
On-chip Program
Memory
07FFh
0800h
1FFFh
1999 Microchip Technology Inc.
DS40182C-page 11
PIC16CE62X
4.2.1
GENERAL PURPOSE REGISTER FILE
4.2
Data Memory Organization
The register file is organized as 96 x 8 in the
PIC16CE623/624 and 128 x 8 in the PIC16CE625.
Each is accessed either directly or indirectly through
the File Select Register FSR (Section 4.4).
The data memory (Figure 4-4 and Figure 4-5) is
partitioned into two Banks which contain the General
Purpose Registers and the Special Function Registers.
Bank 0 is selected when the RP0 bit is cleared. Bank 1
is selected when the RP0 bit (STATUS <5>) is set. The
Special Function Registers are located in the first 32
locations of each Bank. Register locations 20-7Fh
(Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0)
and A0-BFh (Bank1) on the PIC16CE625 are General
Purpose Registers implemented as static RAM. Some
special purpose registers are mapped in Bank 1. In all
three microcontrollers, address space F0h-FFh
(Bank1) is mapped to 70-7Fh (Bank0) as common
RAM.
DS40182C-page 12
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 4-4: DATA MEMORY MAP FOR
THE PIC16CE623/624
FIGURE 4-5: DATA MEMORY MAP FOR
THE PIC16CE625
File
Address
File
Address
File
Address
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
INDF(1)
OPTION
PCL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
PORTA
PORTB
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
PCON
EEINTF
EEINTF
CMCON
VRCON
CMCON
VRCON
A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
BFh
C0h
EFh
F0h
F0h
FFh
Accesses
70h-7Fh
Accesses
70h-7Fh
FFh
7Fh
7Fh
Bank 0
Bank 1
Bank 0
Bank 1
Unimplemented data memory locations, read as ’0’.
Unimplemented data memory locations, read as ’0’.
Note 1: Not a physical register.
Note 1: Not a physical register.
1999 Microchip Technology Inc.
DS40182C-page 13
PIC16CE62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets
(core and peripheral). The Special Function Registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS FOR THE PIC16CE62X
Value on all
Value on
other
Address Name
Bank 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Reset
resets(1)
Addressing this location uses contents of FSR to address data memory (not a physical
register)
00h
INDF
xxxx xxxx
xxxx xxxx
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
TMR0
Timer0 Module’s Register
xxxx xxxx
0000 0000
0001 1xxx
uuuu uuuu
0000 0000
000q quuu
PCL
Program Counter's (PC) Least Significant Byte
IRP(2)
RP1(2)
STATUS
FSR
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
xxxx xxxx
---x 0000
xxxx xxxx
—
uuuu uuuu
---u 0000
uuuu uuuu
—
PORTA
—
—
—
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
PORTB
RB7
RB6
RB5
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIR1
—
—
—
—
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
---0 0000
0000 000u
-0-- ----
—
PEIE
CMIF
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
0Dh-1Eh Unimplemented
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
Bank 1
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
xxxx xxxx
80h
INDF
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
1111 1111
0000 0000
000q quuu
uuuu uuuu
---1 1111
1111 1111
—
STATUS
PD
Z
DC
C
FSR
TRISA
—
—
—
TRISB
Unimplemented
Unimplemented
Unimplemented
PCLATH
INTCON
PIE1
—
—
—
—
—
GIE
—
—
—
T0IE
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
-0-- ----
—
---0 0000
0000 000u
-0-- ----
—
PEIE
CMIE
INTE
—
RBIE
—
T0IF
—
INTF
—
RBIF
—
Unimplemented
PCON
—
—
—
—
—
—
POR
BOD
---- --0x
—
---- --uq
—
8Fh-9Eh Unimplemented
90h
EEINTF
—
—
—
—
—
—
EESCL
VR2
EESDA
VR1
EEVDD
---- -111
000- 0000
---- -111
000- 0000
9Fh
VRCON
VREN
VROE
VRR
VR3
VR0
Legend: — = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
Note 2: IRP & RPI bits are reserved; always maintain these bits clear.
DS40182C-page 14
1999 Microchip Technology Inc.
PIC16CE62X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16CE62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits
is NOT recommended, since this may
affect upward compatibility with future
products.
Note 2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLWand SUBWF
instructions for examples.
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the status register as
000uu1uu(where u= unchanged).
REGISTER 4-1: STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved R/W-0
IRP RP1
bit7
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
RP0
R
=
Readable bit
W = Writable bit
U
bit0
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7:
IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5 RP<1:O>: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1999 Microchip Technology Inc.
DS40182C-page 15
PIC16CE62X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2: OPTION REGISTER (ADDRESS 81H)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
R
=
Readable bit
W = Writable bit
bit7
bit0
U
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7:
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
bit 6:
bit 5:
bit 4:
bit 3:
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0: PS<2:0>: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS40182C-page 16
1999 Microchip Technology Inc.
PIC16CE62X
4.2.2.3
INTCON REGISTER
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for
description of the comparator enable and flag bits.
a
REGISTER 4-3: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
R
=
Readable bit
W = Writable bit
bit7
bit0
U
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= When at least one of the RB<7:4> pins changed state (must be cleared in software)
0= None of the RB<7:4> pins have changed state
1999 Microchip Technology Inc.
DS40182C-page 17
PIC16CE62X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIE
—
—
—
—
—
—
R
=
Readable bit
W = Writable bit
bit7
bit0
U
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7:
Unimplemented: Read as ’0’
bit 6:
CMIE: Comparator Interrupt Enable bit
1= Enables the Comparator interrupt
0= Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as ’0’
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the com-
parator interrupt.
Note: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 4-5: PIR1 REGISTER (ADDRESS 0CH)
U-0
—
R/W-0
CMIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
=
Readable bit
W = Writable bit
bit7
bit0
U
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7:
Unimplemented: Read as ’0’
bit 6:
CMIF: Comparator Interrupt Flag bit
1= Comparator input has changed
0= Comparator input has not changed
bit 5-0: Unimplemented: Read as ’0’
DS40182C-page 18
1999 Microchip Technology Inc.
PIC16CE62X
4.2.2.6
PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR reset,
WDT reset or a Brown-out Reset.
Note: BOD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOD is
cleared, indicating
a
brown-out has
occurred. The BOD status bit is a "don’t
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BODEN
bit
in
the
configuration word).
REGISTER 4-6: PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
POR
BOD
R
=
Readable bit
W = Writable bit
bit7
bit0
U
=
Unimplemented bit,
read as ‘0’
-n
-x
=
=
Value at POR reset
Unknown at POR reset
bit 7-2: Unimplemented: Read as ’0’
bit 1:
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOD: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1999 Microchip Technology Inc.
DS40182C-page 19
PIC16CE62X
4.3.2
STACK
4.3
PCL and PCLATH
The PIC16CE62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data
space and the stack pointer is not readable or writ-
able. The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a
RETURN, RETLWor a RETFIEinstruction execution.
PCLATH is not affected by a PUSH or POP operation.
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-6 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
FIGURE 4-6: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
12
8
7
0
Instruction with
PCL as
Destination
PC
8
PCLATH<4:0>
PCLATH
5
Note 2: There are no instruction/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLWand RETFIE
instructions or the vectoring to an
interrupt address.
ALU result
PCH
12 11 10
PCL
8
7
0
GOTO, CALL
PC
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing
a
Table Read"
(AN556).
DS40182C-page 20
1999 Microchip Technology Inc.
PIC16CE62X
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
4.4
Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20
movwf FSR
;initialize pointer
;to RAM
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-7. However, IRP is not used in the
PIC16CE62X.
NEXT
clrf
incf
INDF
FSR
;clear INDF register
;inc pointer
btfss FSR,4 ;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
FIGURE 4-7: DIRECT/INDIRECT ADDRESSING PIC16CE62X
Direct Addressing
Indirect Addressing
(1)
(1)
RP1 RP0
bank select
from opcode
7
6
0
0
IRP
FSR Register
bank select
180h
location select
location select
00
01
10
11
00h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1 Bank 2
Bank 3
For memory map detail see Figure 4-4 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
1999 Microchip Technology Inc.
DS40182C-page 21
PIC16CE62X
NOTES:
DS40182C-page 22
1999 Microchip Technology Inc.
PIC16CE62X
Note: On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
5.0
I/O PORTS
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
5.1
PORTA and TRISA Registers
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers), which can con-
figure these pins as input or output.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
A ’1’ in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A ’0’ in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
EXAMPLE 5-1: INITIALIZING PORTA
CLRF PORTA
;Initialize PORTA by setting
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
MOVLW 0X07
MOVWF CMCON
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control Register) register and the
VRCON (Voltage Reference Control Register) register.
When selected as a comparator input, these pins will
read as ’0’s.
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as ’0’.
FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN
FIGURE 5-1: BLOCK DIAGRAM OF
RA<1:0> PINS
Data
Bus
D
Q
Q
Data
Bus
VDD VDD
P
WR
PortA
D
Q
Q
CK
VDD VDD
P
WR
PortA
Data Latch
CK
D
Q
RA2 Pin
Data Latch
N
WR
TRISA
D
Q
Q
CK
I/O Pin
N
WR
TRISA
VSS
TRIS Latch
Analog
Input Mode
CK
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
Analog
Input Mode
RD TRISA
Schmitt Trigger
Input Buffer
Q
D
RD TRISA
Q
D
EN
RD PORTA
EN
RD PORTA
To Comparator
VROE
To Comparator
VREF
1999 Microchip Technology Inc.
DS40182C-page 23
PIC16CE62X
FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN
Data
Comparator Mode = 110
Comparator Output
Bus
D
Q
Q
VDD
P
VDD
WR
PORTA
CK
Data Latch
D
Q
RA3 Pin
N
WR
TRISA
CK
Q
VSS
TRIS Latch
Analog
Input Mode
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN
Data
Comparator Mode = 110
Comparator Output
Bus
D
Q
Q
WR
PORTA
CK
Data Latch
D
Q
RA4 Pin
N
WR
TRISA
CK
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
DS40182C-page 24
1999 Microchip Technology Inc.
PIC16CE62X
TABLE 5-1:
Name
PORTA FUNCTIONS
Buffer
Bit #
Type
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Input/output or comparator input
Input/output or comparator input
RA1/AN1
RA2/AN2/VREF
RA3/AN3
Input/output or comparator input or VREF output
Input/output or comparator input/output
RA4/T0CKI
Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
All Other
Resets
Value on:
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
05h
85h
1Fh
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000 ---u 0000
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
CMCON
VRCON
C2OUT C1OUT
VREN VROE
—
—
—
CIS
CM2
VR2
CM1
VR1
CM0
VR0
00-- 0000 00-- 0000
000- 0000 000- 0000
VRR
VR3
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged
Note: Shaded bits are not used by PORTA.
1999 Microchip Technology Inc.
DS40182C-page 25
PIC16CE62X
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A ’1’ in
the TRISB register puts the corresponding output driver
in a high impedance mode. A ’0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implement-
ing Wake-Up on Key Strokes”.)
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Four of PORTB’s pins, RB<7:4>, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins of RB<7:4> are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6: BLOCK DIAGRAM OF
RB<3:0> PINS
VDD
RBPU(1)
FIGURE 5-5: BLOCK DIAGRAM OF
P
weak
RB<7:4> PINS
I/O pin
Data Latch
pull-up
Data Bus
VDD
D
Q
RBPU(1)
P
WR PORTB
CK
CK
weak
I/O pin
pull-up
Data Latch
Data Bus
D
Q
D
Q
TTL
WR PORTB
Input
Buffer
WR TRISB(1)
CK
TRIS Latch
D
Q
WR TRISB(1)
TTL
CK
RD TRISB
RD PORTB
Input
Buffer
ST
Buffer
Q
D
EN
RD TRISB
Latch
Q
Q
D
RB0/INT
EN
RD PORTB
ST
Buffer
RD Port
Set RBIF
From other
RB<7:4> pins
D
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
(OPTION<7>).
EN
RD Port
RB<7:6> in serial programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = ’0’
(OPTION<7>).
DS40182C-page 26
1999 Microchip Technology Inc.
PIC16CE62X
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit #
Buffer Type
Function
TTL/ST(1)
RB0/INT
bit0
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock pin.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
All Other
Resets
Value on:
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h
86h
81h
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
OPTION
RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Legend: u= unchanged, x= unknown
Note: Shaded bits are not used by PORTB.
1999 Microchip Technology Inc.
DS40182C-page 27
PIC16CE62X
5.3
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
5.3.1
I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs
;
Any instruction which writes, operates internally as a
read followed by a write operation. The BCFand BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSFoperation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-up and are not
;connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BCF PORTB, 7
BCF PORTB, 6
BSF STATUS,RP0
BCF TRISB, 7
BCF TRISB, 6
;01pp pppp 11pp pppp
;10pp pppp 11pp pppp
;
;10pp pppp 11pp pppp
;10pp pppp 10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O PORTS
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-7). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction causes that file to be read
into the CPU. Otherwise, the previous state of that pin
may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instruc-
tions with an NOP or another instruction not accessing
this I/O port.
Example 5-2 shows the effect of two sequential
read-modify-write instructions (i.e., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
FIGURE 5-7: SUCCESSIVE I/O OPERATION
Note:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
This example shows write to PORTB
followed by a read from PORTB.
PC
PC + 1
PC + 2
NOP
PC + 3
NOP
PC
Instruction
MOVWF PORTB
Write to
PORTB
MOVF PORTB, W
Read PORTB
Note that:
Fetched
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
RB<7:0>
Port pin
sampled here
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
TPD
Execute
MOVWF
PORTB
Execute
MOVF
PORTB, W
Execute
NOP
DS40182C-page 28
1999 Microchip Technology Inc.
PIC16CE62X
The code for these functions is available on our web
site (www.microchip.com). The code will be accessed
by either including the source code FL62XINC.ASM or
by linking FLASH62X.ASM. FLASH62.IMC provides
external definition to the calling program.
6.0
EEPROM PERIPHERAL
OPERATION
The PIC16CE623/624/625 each have 128 bytes of
EEPROM data memory. The EEPROM data memory
supports a bi-directional, 2-wire bus and data transmis-
sion protocol. These two-wires are serial data (SDA)
and serial clock (SCL), and are mapped to bit1 and bit2,
respectively, of the EEINTF register (SFR 90h). In addi-
tion, the power to the EEPROM can be controlled using
bit0 (EEVDD) of the EEINTF register. For most appli-
cations, all that is required is calls to the following func-
tions:
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the memory.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
; Byte_Write: Byte write routine
;
;
;
;
;
Inputs:EEPROM Address
EEPROM Data
EEADDR
EEDATA
6.0.2
SERIAL CLOCK
Outputs:
Return 01 in W if OK, else
return 00 in W
This SCL input is used to synchronize the data transfer
to and from the memory.
; Read_Current: Read EEPROM at address
currently held by EE device.
6.0.3
EEINTF REGISTER
;
;
;
;
;
Inputs:NONE
Outputs:
The EEINTF register (SFR 90h) controls the access to
the EEPROM. Register 6-1 details the function of each
bit. User code must generate the clock and data sig-
nals.
EEPROM Data
EEDATA
Return 01 in W if OK, else
return 00 in W
; Read_Random: Read EEPROM byte at supplied
; address
;
;
;
;
Inputs:EEPROM Address
Outputs: EEPROM Data
EEADDR
EEDATA
Return 01 in W if OK,
else return 00 in W
REGISTER 6-1: EEINTF REGISTER (ADDRESS 90h)
U-0
bit7
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
EESCL
EESDA
EEVDD
R
= Readable bit
W = Writable bit
U
bit0
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as ’0’
bit 2:
EESCL: Clock line to the EEPROM
1= Clock high
0= Clock low
bit 1:
EESDA: Data line to EEPROM
1= Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor)
0= Data line is low
bit 0:
EEVDD: VDD control bit for EEPROM
1= VDD is turned on to EEPROM
0= VDD is turned off to EEPROM (all pins are tri-stated and the EEPROM is powered down)
Note: EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off.
1999 Microchip Technology Inc.
DS40182C-page 29
PIC16CE62X
6.1.5
ACKNOWLEDGE
6.1
Bus Characteristics
The EEPROM will generate an acknowledge after the
reception of each byte. The processor must generate
an extra clock pulse which is associated with this
acknowledge bit.
In this section, the term “processor” refers to the portion
of the PIC16CE62X that interfaces to the EEPROM
through software manipulating the EEINTF register.
The following bus protocol is to be used with the
EEPROM data memory.
Note: Acknowledge bits are not generated if an
• Data transfer may be initiated only when the bus
is not busy.
internal programming cycle is in progress.
When the EEPROM acknowledges, it pulls down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-2).
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted by the EEPROM as a START or STOP
condition.
Accordingly, the following bus conditions have been
defined (Figure 6-1).
6.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor and
is theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out fashion.
DS40182C-page 30
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(C)
(D)
(C) (A)
SCL
SDA
START
CONDITION
STOP
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
FIGURE 6-2: ACKNOWLEDGE TIMING
Acknowledge
Bit
1
2
3
4
5
6
7
8
9
1
2
3
SCL
SDA
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
Device Addressing
FIGURE 6-3: CONTROL BYTE FORMAT
Read/Write Bit
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don’t care bits.
Device Select
Don’t Care
Bits
Bits
S
1
0
1
0
X
X
X
R/W ACK
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected. (Figure 6-3). The bus is monitored for its cor-
responding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
EEPROM Address
Acknowledge Bit
Start Bit
1999 Microchip Technology Inc.
DS40182C-page 31
PIC16CE62X
6.3
Write Operations
6.4
Acknowledge Polling
6.3.1
BYTE WRITE
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com-
mand has been issued from the processor, the
EEPROM initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves the
processor sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then no ACK will
be returned. If no ACK is returned, then the start bit and
control byte must be re-sent. If the cycle is complete,
then the device will return the ACK and the processor
can then proceed with the next read or write command.
See Figure 6-4 for flow diagram.
Following the start signal from the processor, the
device code (4 bits), the don’t care bits (3 bits), and the
R/W bit, which is a logic low, is placed onto the bus by
the processor. This indicates to the EEPROM that a
byte with a word address will follow after it has gener-
ated an acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the processor is
the word address and will be written into the address
pointer of the EEPROM. After receiving another
acknowledge signal from the EEPROM, the processor
will transmit the data word to be written into the
addressed memory location. The EEPROM acknowl-
edges again and the processor generates a stop con-
dition. This initiates the internal write cycle, and during
this time, the EEPROM will not generate acknowledge
signals (Figure 6-5).
FIGURE 6-4: ACKNOWLEDGE POLLING
FLOW
6.3.2
PAGE WRITE
Send
Write Command
The write control byte, word address and the first data
byte are transmitted to the EEPROM in the same way
as in a byte write. But instead of generating a stop con-
dition, the processor transmits up to eight data bytes to
the EEPROM, which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the processor has transmitted a stop condition.
After the receipt of each word, the three lower order
address pointer bits are internally incremented by one.
The higher order five bits of the word address remains
constant. If the processor should transmit more than
eight words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an inter-
nal write cycle will begin (Figure 6-6).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
NO
Acknowledge
(ACK = 0)?
YES
Next
Operation
FIGURE 6-5: BYTE WRITE
S
T
A
R
T
S
BUS ACTIVITY
PROCESSOR
CONTROL
BYTE
WORD
ADDRESS
T
DATA
O
P
SDA LINE
P
S
1
0
1
0
X
X
X
0
X
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
X = Don’t Care Bit
DS40182C-page 32
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-6: PAGE WRITE
S
BUS ACTIVITY
PROCESSOR
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
A
R
T
DATAn
DATAn + 1
DATAn + 7
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY
6.5
Read Operation
6.8
Sequential Read
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations: current address read, random
read, and sequential read.
Sequential reads are initiated in the same way as a ran-
dom read except that after the EEPROM transmits the
first data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-9).
6.6
Current Address Read
To provide sequential reads, the EEPROM contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
The EEPROM contains an address counter that main-
tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the EEPROM
address with R/W bit set to one, the EEPROM issues
an acknowledge and transmits the eight bit data word.
The processor will not acknowledge the transfer, but
does generate a stop condition and the EEPROM dis-
continues transmission (Figure 6-7).
6.9
Noise Protection
The EEPROM employs a VCC threshold detector cir-
cuit, which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits, which suppress noise spikes to assure proper
device operation even on a noisy bus.
6.7
Random Read
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condi-
tion following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and trans-
mits the eight bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-8).
1999 Microchip Technology Inc.
DS40182C-page 33
PIC16CE62X
FIGURE 6-7: CURRENT ADDRESS READ
S
T
BUS ACTIVITY
CONTROL
S
T
O
P
A
R
T
PROCESSOR
BYTE
DATAn
SDA LINE
S
P
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 6-8: RANDOM READ
S
T
A
R
T
S
T
A
R
T
S
T
O
P
CONTROL
BYTE
WORD
ADDRESS (n)
CONTROL
BYTE
BUS ACTIVITY
PROCESSOR
DATAn
S
P
S
SDA LINE
A
C
K
A
C
K
A
C
K
N
O
BUS ACTIVITY
A
C
K
FIGURE 6-9: SEQUENTIAL READ
S
T
O
P
A
C
K
A
C
K
A
C
K
CONTROL
BYTE
BUS ACTIVITY
PROCESSOR
SDA LINE
P
A
C
K
N
O
BUS ACTIVITY
DATAn
DATAn + 1
DATAn + 2
DATAn + X
A
C
K
DS40182C-page 34
1999 Microchip Technology Inc.
PIC16CE62X
bit (OPTION<4>). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.2.
7.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 7.3 details the operation of the
prescaler.
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer0 Interrupt
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 7-2 and Figure 7-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before
re-enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 7-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 7-1: TIMER0 BLOCK DIAGRAM
Data Bus
RA4/T0CKI
pin
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
clocks
TMR0
Programmable
Prescaler
PSout
(2 TCY delay)
T0SE
Set Flag bit T0IF
on Overflow
PS<2:0>
PSA
T0CS
Note 1: Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2: TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0+1
NT0+2
TMR0
Instruction
Executed
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0 Read TMR0
Read TMR0
reads NT0
reads NT0 + 1 reads NT0 + 2
1999 Microchip Technology Inc.
DS40182C-page 35
PIC16CE62X
FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
TMR0
Instruction
Execute
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed reads NT0 reads NT0 reads NT0 reads NT0 reads NT0 + 1
FIGURE 7-4: TIMER0 INTERRUPT TIMING
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
Q1 Q2 Q3
Q4
OSC1
(3)
CLKOUT
TMR0 timer
FEh
1
FFh
1
00h
01h
02h
T0IF bit
(INTCON<2>)
GIE bit
(INTCON<7>)
Interrupt Latency Time
PC +1
INSTRUCTION FLOW
PC
PC
PC +1
0004h
0005h
Instruction
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
fetched
Instruction
executed
Inst (PC-1)
Dummy cycle
Dummy cycle
Inst (PC)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS40182C-page 36
1999 Microchip Technology Inc.
PIC16CE62X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement on
T0CKI high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
misses sampling
External Clock Input or
(2)
Prescaler output
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1999 Microchip Technology Inc.
DS40182C-page 37
PIC16CE62X
The PSA and PS<2:0> bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= FOSC/4)
M
U
X
1
0
0
1
M
U
X
T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set flag bit T0IF
on Overflow
PSA
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8-to-1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
DS40182C-page 38
1999 Microchip Technology Inc.
PIC16CE62X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
EXAMPLE 7-2: CHANGING PRESCALER
RESET,
the
following
instruction
sequence
(WDT→TIMER0)
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
CLRWDT
;Clear WDT and
;prescaler
EXAMPLE 7-1: CHANGING PRESCALER
BSF
STATUS, RP0
(TIMER0→WDT)
STATUS, RP0 ;Skip if already in
MOVLW
b'xxxx0xxx' ;Select TMR0, new
;prescale value and
;clock source
1.BCF
; Bank 0
2.CLRWDT
3.CLRF
4.BSF
;Clear WDT
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
MOVWF
BCF
OPTION_REG
STATUS, RP0
TMR0
5.MOVLW '00101111’b ;These 3 lines (5, 6, 7)
6.MOVWF OPTION
; are required only if
; desired PS<2:0> are
; 000 or 001
7.CLRWDT
8.MOVLW '00101xxx’b ;Set Postscaler to
9.MOVWF OPTION ; desired WDT rate
10.BCF STATUS, RP0 ;Return to Bank 0
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
Value on:
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All Other
Resets
01h
TMR0
Timer0 module register
GIE PEIE T0IE
xxxx xxxx uuuu uuuu
0000 000x 0000 000u
1111 1111 1111 1111
0Bh/8Bh
81h
INTCON
INTE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF
PS0
OPTION RBPU INTEDG T0CS
TRISA
T0SE
85h
—
—
—
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’, x= unknown, u= unchanged.
Note: Shaded bits are not used by TMR0 module.
1999 Microchip Technology Inc.
DS40182C-page 39
PIC16CE62X
NOTES:
DS40182C-page 40
1999 Microchip Technology Inc.
PIC16CE62X
The CMCON register, shown in Register 8-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 8-1.
8.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The
on-chip voltage reference (Section 9.0) can also be an
input to the comparators.
REGISTER 8-1: CMCON REGISTER (ADDRESS 1Fh)
R-0
R-0
U-0
U-0
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
R
= Readable bit
C2OUT C1OUT
bit7
—
—
W = Writable bit
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
C2OUT: Comparator 2 output
1= C2 VIN+ > C2 VIN–
0= C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
1= C1 VIN+ > C1 VIN–
0= C1 VIN+ < C1 VIN–
bit 5-4: Unimplemented: Read as '0'
bit 3:
CIS: Comparator Input Switch
When CM<2:0>: = 001:
1= C1 VIN– connects to RA3
0= C1 VIN– connects to RA0
When CM<2:0> = 010:
1= C1 VIN– connects to RA3
C2 VIN– connects to RA2
0= C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM<2:0>: Comparator mode
Figure 8-1.
1999 Microchip Technology Inc.
DS40182C-page 41
PIC16CE62X
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 13-1.
8.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 8-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
Note: Comparator interrupts should be disabled
during a comparator mode change, other-
wise a false interrupt may occur.
FIGURE 8-1: COMPARATOR I/O OPERATING MODES
VIN-
VIN-
A
A
D
D
-
-
Off
Off
RA0/AN0
RA3/AN3
RA0/AN0
RA3/AN3
C1
C2
C1
C2
VIN+
VIN+
(Read as ’0’)
(Read as ’0’)
+
+
VIN-
VIN-
A
A
D
D
-
-
Off
Off
RA1/AN1
RA2/AN2
RA1/AN1
RA2/AN2
VIN+
VIN+
(Read as ’0’)
(Read as ’0’)
+
+
CM<2:0> = 000
C1OUT
CM<2:0> = 111
Comparators Reset
Comparators Off
VIN-
A
A
A
-
RA0/AN0
CIS=0
CIS=1
VIN-
RA0/AN0
RA3/AN3
-
C1
C2
VIN+
A
C1OUT
RA3/AN3
+
C1
VIN+
+
VIN-
A
A
A
-
RA1/AN1
CIS=0
CIS=1
VIN-
RA1/AN1
RA2/AN2
-
C2OUT
VIN+
A
C2OUT
RA2/AN2
+
C2
VIN+
+
CM<2:0> = 100
From VREF Module
CM<2:0> = 010
Two Independent Comparators
Four Inputs Multiplexed to
Two Comparators
VIN-
VIN-
A
A
-
-
RA0/AN0
RA0/AN0
C1OUT
C1OUT
C1
C2
C1
VIN+
VIN+
D
D
+
+
RA3/AN3
RA3/AN3
VIN-
VIN-
A
A
-
-
RA1/AN1
RA1/AN1
C2OUT
C2OUT
C2
VIN+
VIN+
A
A
+
+
RA2/AN2
RA2/AN2
RA4 Open Drain
CM<2:0> = 011
CM<2:0> = 110
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
VIN-
A
A
CIS=0
VIN-
CIS=1
VIN+
D
D
-
RA0/AN0
RA3/AN3
Off
RA0/AN0
RA3/AN3
-
C1
C2
VIN+
(Read as ’0’)
C1OUT
+
C1
C2
+
VIN-
A
A
-
VIN-
RA1/AN1
RA2/AN2
A
A
-
C2OUT
RA1/AN1
RA2/AN2
VIN+
C2OUT
+
VIN+
+
CM<2:0> = 101
CM<2:0> = 001
Three Inputs Multiplexed to
Two Comparators
One Independent Comparator
A = Analog Input, Port Reads Zeros Always
D = Digital Input
CIS = CMCON<3>, Comparator Input Switch
DS40182C-page 42
1999 Microchip Technology Inc.
PIC16CE62X
The code example in Example 8-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
8.3
Comparator Reference
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 8-2).
EXAMPLE 8-1: INITIALIZING
COMPARATOR MODULE
FIGURE 8-2: SINGLE COMPARATOR
FLAG_REGEQU
0X20
CLRF
CLRF
MOVF
ANDLW
IORWF
MOVLW
MOVWF
BSF
FLAG_REG
;Init flag register
;Init PORTA
;Move comparator contents to W
;Mask comparator bits
PORTA
CMCON,W
0xC0
VIN+
+
–
Output
FLAG_REG,F ;Store bits in flag register
0x03
CMCON
VIN–
;Init comparator mode
;CM<2:0> = 011
STATUS,RP0 ;Select Bank1
MOVLW
MOVWF
0x07
TRISA
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
STATUS,RP0 ;Select Bank 0
V
VIN–
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
VIN+
DELAY 10
CMCON,F
PIR1,CMIF
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
;10µs delay
;Read CMCONtoendchangecondition
;Clear pending interrupts
;Enable comparator interrupts
Output
8.2
Comparator Operation
8.3.1
EXTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 8-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 8-2
represent the uncertainty due to input offsets and
response time.
When external voltage references are used, the
comparator module can be configured to have the com-
parators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
8.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 13, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM<2:0>=010 (Figure 8-1). In this mode, the internal
voltage reference is applied to the VIN+ pin of both
comparators.
1999 Microchip Technology Inc.
DS40182C-page 43
PIC16CE62X
8.4
Comparator Response Time
8.5
Comparator Outputs
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal refer-
ence is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs, otherwise the maximum delay of
the comparators should be used (Table 13-1 ).
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 8-3 shows the comparator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
a ‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 8-3: COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
To RA3 or
RA4 Pin
Data
Bus
Q
D
RD CMCON
EN
Set
CMIF
Bit
D
Q
From
Other
Comparator
EN
CL
RD CMCON
NRESET
DS40182C-page 44
1999 Microchip Technology Inc.
PIC16CE62X
wake-up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
8.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
8.8
Effects of a RESET
The CMIE bit (PIE1<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM<2:0> = 000. This ensures
that all potential inputs are analog inputs. Device cur-
rent is minimized when analog inputs are present at
reset time. The comparators will be powered-down
during the reset interval.
Note: If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
8.9
Analog Input Connection
Considerations
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
A simplified circuit for an analog input is shown in
Figure 8-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
8.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
FIGURE 8-4: ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10K
RIC
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6V
VSS
Legend
CPIN
VT
= Input capacitance
= Threshold voltage
ILEAKAGE
RIC
= Leakage current at the pin due to various junctions
= Interconnect resistance
RS
= Source impedance
VA
= Analog voltage
1999 Microchip Technology Inc.
DS40182C-page 45
PIC16CE62X
TABLE 8-1:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
Resets
Value on:
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1Fh
9Fh
0Bh
0Ch
8Ch
85h
CMCON C2OUT C1OUT
—
VRR
T0IE
—
—
—
CIS
VR3
RBIE
—
CM2
VR2
T0IF
—
CM1
VR1
INTF
—
CM0
VR0
RBIF
—
00-- 0000 00-- 0000
000- 0000 000- 0000
0000 000x 0000 000u
-0-- ---- -0-- ----
-0-- ---- -0-- ----
VRCON
INTCON
PIR1
VREN
GIE
—
VROE
PEIE
CMIF
CMIE
—
INTE
—
PIE1
—
—
—
—
—
—
—
TRISA
—
—
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: - = Unimplemented, read as "0", x= Unknown, u= unchanged
DS40182C-page 46
1999 Microchip Technology Inc.
PIC16CE62X
9.1
Configuring the Voltage Reference
9.0
VOLTAGE REFERENCE
MODULE
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Register 9-1. The block diagram
is given in Figure 9-1.
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR<3:0>/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 13-1). Example 9-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
REGISTER 9-1: VRCON REGISTER (ADDRESS 9Fh)
R/W-0
R/W-0
R/W-0
VRR
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R
= Readable bit
VREN
VROE
—
VR3
VR2
VR1
VR0
W = Writable bit
bit7
bit0
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
VREN: VREF Enable
1= VREF circuit powered on
0= VREF circuit powered down, no IDD drain
VROE: VREF Output Enable
1= VREF is output on RA2 pin
0= VREF is disconnected from RA2 pin
VRR: VREF Range selection
1= Low Range
0= High Range
Unimplemented: Read as ’0’
bit 3-0: VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
when VRR = 1: VREF = (VR<3:0>/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
FIGURE 9-1: VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
R
R
R
R
8R
8R
VRR
VR3
VR0
VREF
(From VRCON<3:0>)
16-1 Analog Mux
Note: R is defined in Table 13-2.
1999 Microchip Technology Inc.
DS40182C-page 47
PIC16CE62X
EXAMPLE 9-1: VOLTAGE REFERENCE
CONFIGURATION
9.4
Effects of a Reset
A device reset disables the Voltage Reference by clear-
ing bit VREN (VRCON<7>). This reset also disconnects
the reference from the RA2 pin by clearing bit VROE
(VRCON<6>) and selects the high voltage range by
clearing bit VRR (VRCON<5>). The VREF value select
bits, VRCON<3:0>, are also cleared.
MOVLW
MOVWF
BSF
0x02
; 4 Inputs Muxed
; to 2 comps.
; go to Bank 1
; RA3-RA0 are
; outputs
CMCON
STATUS,RP0
0x07
MOVLW
MOVWF
MOVLW
MOVWF
TRISA
0xA6
; enable VREF
; low range
9.5
Connection Considerations
Voltage Reference Module
VRCON
; set VR<3:0>=6
; go to Bank 0
; 10µs delay
The
operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
BCF
STATUS,RP0
DELAY10
CALL
9.2
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 9-1) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 13-2.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 9-2 shows an example buffering
technique.
9.3
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 9-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
(1)
RA2
R
VREF
+
–
Module
•
VREF Output
•
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 9-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Value On
All Other
Resets
Value On
POR / BOD
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Fh
1Fh
85h
VRCON
CMCON
TRISA
VREN
VROE VRR
—
—
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
000- 0000 000- 0000
00-- 0000 00-- 0000
C2OUT C1OUT
—
—
—
—
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
Legend: - = Unimplemented, read as "0"
DS40182C-page 48
1999 Microchip Technology Inc.
PIC16CE62X
The PIC16CE62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only, and is
designed to keep the part in reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
10.0 SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real time appli-
cations are what sets a microcontroller apart from other
processors. The PIC16CE62X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external compo-
nents, provide power saving operating modes and offer
code protection.
These are:
1. OSC selection
2. Reset
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up from
SLEEP through external reset, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOD)
3. Interrupts
4. Watchdog Timer (WDT)
5. SLEEP
6. Code protection
7. ID Locations
8. In-circuit serial programming
1999 Microchip Technology Inc.
DS40182C-page 49
PIC16CE62X
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
10.1
Configuration Bits
The configuration bits can be programmed (read as ’0’)
or left unprogrammed (read as ’1’) to select various
device configurations. These bits are mapped in
program memory location 2007h.
REGISTER 10-1: CONFIGURATION WORD
(2)
(2)
(2)
CP1 CP0
(1)
(2)
(1)
PWRTE
CP1 CP0
bit13
CP1 CP0
—
BODEN
CP1 CP0
WDTE F0SC1 F0SC0
CONFIG
REGISTER: 2007h
Address
bit0
(2)
bit 13-8, CP1:CP0 Pairs: Code protection bit pairs
5-4: Code protection for 2K program memory
11= Program memory code protection off
10= 0400h-07FFh code protected
01= 0200h-07FFh code protected
00= 0000h-07FFh code protected
Code protection for 1K program memory
11= Program memory code protection off
10=Program memory code protection on
01= 0200h-03FFh code protected
00= 0000h-03FFh code protected
Code protection for 0.5K program memory
11= Program memory code protection off
10= Program memory code protection off
01= Program memory code protection off
00= 0000h-01FFh code protected
bit 7:
bit 6:
Unimplemented: Read as ’1’
(1)
BODEN: Brown-out Reset Enable bit
1= BOD enabled
0= BOD disabled
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.
DS40182C-page 50
1999 Microchip Technology Inc.
PIC16CE62X
10.2
Oscillator Configurations
TABLE 10-1: CERAMIC RESONATORS,
PIC16CE62X
10.2.1
OSCILLATOR TYPES
Ranges Tested:
The PIC16CE62X can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
Mode
XT
Freq
OSC1
OSC2
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
• LP
• XT
• HS
• RC
Low Power Crystal
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Crystal/Resonator
These values are for design guidance only. See notes at
bottom of page.
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 10-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR,
10.2.2 CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
PIC16CE62X
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 10-1). The PIC16CE62X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 10-2).
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
HS
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
FIGURE 10-1: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
CONFIGURATION)
These values are for design guidance only. See notes at
bottom of page.
OSC1
1. Recommended values of C1 and C2 are identical to
C1
C2
To Internal Logic
SLEEP
the ranges tested table.
XTAL
OSC2
RF
2. Higher capacitance increases the stability of oscillator,
but also increases the start-up time.
RS
see Note
3. Since each resonator/crystal has its own characteris-
tics, the user should consult the resonator/crystal
manufacturer for appropriate values of external com-
ponents.
PIC16CE62X
See Table 10-1 and Table 10-2 for recommended values
of C1 and C2.
4. Rs may be required in HS mode, as well as XT mode,
to avoid overdriving crystals with low drive level spec-
ification.
Note:
A series resistor may be required for AT
strip cut crystals.
FIGURE 10-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Clock From
ext. system
OSC1
PIC16CE62X
OSC2
Open
1999 Microchip Technology Inc.
DS40182C-page 51
PIC16CE62X
10.2.3 EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
10.2.4 RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 10-5 shows how the
R/C combination is connected to the PIC16CE62X. For
Rext values below 2.2 kΩ, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (i.e., 1 MΩ), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep Rext between 3 kΩ and 100 kΩ.
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepack-
aged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types of
crystal oscillator circuits can be used; one with series
resonance or one with parallel resonance.
Figure 10-3 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 10-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CE62X
CLKIN
74AS04
See Section 14.0 for RC frequency variation from part
to part due to normal process variation. The variation is
larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller C
(since variation of input capacitance will affect RC fre-
quency more).
10k
XTAL
10k
See Section 14.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values, as well as
frequency variation due to operating temperature for
given R, C, and VDD values.
20 pF
20 pF
Figure 10-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin and can be used for test pur-
poses or to synchronize other logic (Figure 3-2 for
waveform).
FIGURE 10-5: RC OSCILLATOR MODE
FIGURE 10-4: EXTERNAL SERIES
RESONANT CRYSTAL
VDD
PIC16CE62X
Rext
OSCILLATOR CIRCUIT
To other
Devices
OSC1
330
330
Internal Clock
74AS04
74AS04
74AS04
PIC16CE62X
Cext
CLKIN
VDD
0.1 µF
OSC2/CLKOUT
FOSC/4
XTAL
DS40182C-page 52
1999 Microchip Technology Inc.
PIC16CE62X
state” on Power-on reset, MCLR reset, WDT reset and
MCLR reset during SLEEP. They are not affected by a
WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 10-4. These bits are used in software to deter-
mine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
10.3
Reset
The PIC16CE62X differentiates between various kinds
of reset:
a) Power-on reset (POR)
b) MCLR reset during normal operation
c) MCLR reset during SLEEP
d) WDT reset (normal operation)
e) WDT wake-up (SLEEP)
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-6.
f) Brown-out Reset (BOD)
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 13-5 for pulse width
specification.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
FIGURE 10-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
10-bit Ripple-counter
Chip_Reset
Q
OSC1/
CLKIN
Pin
PWRT
10-bit Ripple-counter
(1)
On-chip
RC OSC
Enable PWRT
Enable OST
See Table 10-3 for time-out situations.
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1999 Microchip Technology Inc.
DS40182C-page 53
PIC16CE62X
The Power-Up Time delay will vary from chip-to-chip
and due to VDD, temperature and process variation.
See DC parameters for details.
10.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOD)
10.4.3 OSCILLATOR START-UP TIMER (OST)
10.4.1 POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper opera-
tion. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
electrical specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
10.4.4 BROWN-OUT RESET (BOD)
The POR circuit does not produce an internal reset
when VDD declines.
The PIC16CE62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BOREN, can disable
(if clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If VDD falls below 4.0V (refer to BVDD
parameter D005) for greater than parameter (TBOR) in
Table 13-5, the brown-out situation will reset the chip. A
reset won’t occur if VDD falls below 4.0V for less than
parameter (TBOR).
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
On any reset (Power-on, Brown-out, Watch-dog, etc.)
the chip will remain in reset until VDD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in reset an additional 72 ms.
AN607, “Power-up Trouble Shooting”.
10.4.2 POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE, can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 10-7
shows typical Brown-out situations.
FIGURE 10-7: BROWN-OUT SITUATIONS
VDD
BVDD
Internal
Reset
72 ms
VDD
BVDD
Internal
Reset
<72 ms
72 ms
VDD
BVDD
Internal
Reset
72 ms
DS40182C-page 54
1999 Microchip Technology Inc.
PIC16CE62X
10.4.5 TIME-OUT SEQUENCE
10.4.6 POWER CONTROL (PCON)/STATUS
REGISTER
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired, then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 10-8,
Figure 10-9 and Figure 10-10 depict time-out
sequences.
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOR = 0
indicating that a brown-out has occurred. The BOR
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-9). This is useful for testing purposes or
to synchronize more than one PICmicro® device oper-
ating in parallel.
Bit1 is POR (Power-on-reset). It is
a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset, if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (VDD may have
gone too low).
Table 10-5 shows the reset conditions for some special
registers, while Table 10-6 shows the reset conditions
for all the registers.
TABLE 10-3: TIME-OUT IN VARIOUS SITUATIONS
Power-up
Wake-up
Brown-out Reset
Oscillator Configuration
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
RC
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
72 ms
—
72 ms
—
TABLE 10-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
X
X
X
0
1
1
1
1
1
0
X
X
0
0
u
1
1
X
0
X
u
0
u
0
Power-on-reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP
Legend: x= unknown, u= unchanged
1999 Microchip Technology Inc.
DS40182C-page 55
PIC16CE62X
TABLE 10-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Condition
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 uuuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset
000h
000h
WDT Wake-up
PC + 1
000h
Brown-out Reset
Interrupt Wake-up from SLEEP
PC + 1(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set and the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
TABLE 10-6: INITIALIZATION CONDITION FOR REGISTERS
•
•
MCLR Reset during
normal operation
MCLR Reset during
SLEEP
WDT Reset
Brown-out Reset (1)
•
•
Wake-up from SLEEP
through interrupt
Wake-up from SLEEP
through WDT time-out
•
•
Register
Address
Power-on Reset
W
-
xxxx xxxx
-
uuuu uuuu
-
uuuu uuuu
-
INDF
TMR0
00h
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000 0000
0000 0000
PC + 1(3)
STATUS
FSR
03h
04h
05h
06h
1Fh
0Ah
0001 1xxx
xxxx xxxx
---x xxxx
xxxx xxxx
00-- 0000
---0 0000
000q quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
00-- 0000
---0 0000
uuuq quuu(4)
uuuu uuuu
---u uuuu
uuuu uuuu
uu-- uuuu
---u uuuu
PORTA
PORTB
CMCON
PCLATH
INTCON
0Bh
0000 000x
0000 000u
uuuu uqqq(2)
PIR1
0Ch
81h
85h
86h
8Ch
-0-- ----
1111 1111
---1 1111
1111 1111
-0-- ----
-0-- ----
1111 1111
---1 1111
1111 1111
-0-- ----
-q-- ----(2,5)
uuuu uuuu
---u uuuu
uuuu uuuu
-u-- ----
OPTION
TRISA
TRISB
PIE1
PCON
8Eh
90h
9Fh
---- --0x
---- -111
000- 0000
---- --uq(1,6)
---- -111
---- --uu
---- -111
uuu- uuuu
EEINTF
VRCON
000- 0000
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’,q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 10-5 for reset value for specific condition.
5: If wake-up was due to comparator input changing , then bit 6 = 1. All other interrupts generating a wake-up will cause
bit 6 = u.
6: If reset was due to brown-out, then PCON bit 0 = 0. All other resets will cause bit 0 = u.
DS40182C-page 56
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 10-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
1999 Microchip Technology Inc.
DS40182C-page 57
PIC16CE62X
FIGURE 10-11: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 10-13: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
VDD
VDD
R1
R2
Q1
MCLR
D
R
40k
R1
PIC16CE62X
MCLR
PIC16CE62X
C
Note 1: External power-on reset circuit is required only
if VDD power-up slope is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
R1
2: < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flowing
into MCLR from external capacitor C in the
event of MCLR/VPP pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS).
= 0.7 V
VDD x
R1 + R2
2: Internal brown-out detection should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the charac-
teristics of the transistor.
FIGURE 10-14: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
FIGURE 10-12: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
MCP809
VDD
bypass
VDD
VDD
VSS
capacitor
33k
VDD
RST
MCLR
10k
MCLR
PIC16CE62X
40k
PIC16CE62X
This brown-out protection circuit employs Microchip
Technology’s MCP809 microcontroller supervisor. The
MCP8XX and MCP1XX families of supervisors provide
push-pull and open collector outputs with both high and
low active reset pins. There are 7 different trip point
selections to accommodate 5V and 3V systems.
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should be
disabled when using this circuit.
DS40182C-page 58
1999 Microchip Technology Inc.
PIC16CE62X
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
10.5
Interrupts
The PIC16CE62X has 4 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs
(Figure 10-16). The latency is the same for one or two
cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by poll-
ing the interrupt flag bits. The interrupt flag bit(s) must
be cleared in software before re-enabling interrupts to
avoid multiple interrupt requests.
• PortB change interrupts (pins RB<7:4>)
• Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine, the source(s) of
FIGURE 10-15: INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
CMIF
CMIE
PEIE
GIE
1999 Microchip Technology Inc.
DS40182C-page 59
PIC16CE62X
10.5.1 RB0/INT INTERRUPT
10.5.3 PORTB INTERRUPT
External interrupt on RB0/INT pin is edge triggered;
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before
re-enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 10.8 for
details on SLEEP and Figure 10-19 for timing of
wake-up from SLEEP through RB0/INT interrupt.
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
10.5.4 COMPARATOR INTERRUPT
See Section 8.6 for complete description of comparator
interrupts.
10.5.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 7.0.
FIGURE 10-16: INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT
3
4
INT pin
1
1
Interrupt Latency
INTF flag
(INTCON<1>)
5
2
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC
PC+1
PC+1
0005h
Instruction
Inst (PC+1)
—
Inst (0004h)
Inst (PC)
Inst (0005h)
Inst (0004h)
fetched
Instruction
executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note
1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 Tcy where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS40182C-page 60
1999 Microchip Technology Inc.
PIC16CE62X
10.6
Context Saving During Interrupts
10.7
Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e. W register and STATUS
register). This will have to be implemented in software.
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
have been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 10.1).
Example 10-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x70 in Bank 0 and it must also be defined at 0xF0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 10-1:
• Stores the W register
10.7.1 WDT PERIOD
• Stores the STATUS register in Bank 0
• Executes the ISR code
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
• Restores the STATUS (and bank select bit
register)
DD
ture, V and process variations from part to part (see
• Restores the W register
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
EXAMPLE 10-1: SAVING THE STATUS AND
W REGISTERS IN RAM
MOVWF
W_TEMP
;copy W to temp register,
;could be in either bank
The CLRWDTand SLEEPinstructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
SWAPF
BCF
STATUS,W
;swap status to be saved into W
STATUS,RP0
;change to bank 0 regardless
;of current bank
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
MOVWF
STATUS_TEMP
(ISR)
;save status to bank 0
;register
:
10.7.2 WDT PROGRAMMING CONSIDERATIONS
:
:
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT time-out occurs.
SWAPF
STATUS_TEMP,W ;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF
SWAPF
SWAPF
STATUS
;move W into STATUS register
;swap W_TEMP
W_TEMP,F
W_TEMP,W
;swap W_TEMP into W
1999 Microchip Technology Inc.
DS40182C-page 61
PIC16CE62X
FIGURE 10-17: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
M
U
X
Postscaler
8
1
Watchdog
Timer
•
PS<2:0>
To TMR0 (Figure 7-6)
PSA
8 - to -1 MUX
PSA
WDT
Enable Bit
•
1
0
MUX
WDT
Time-out
Note: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION register.
FIGURE 10-18: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Config. bits
OPTION
BOREN
INTEDG
CP1
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
RBPU
T0CS
T0SE
Legend: _ = Unimplemented location, read as “0”, + = Reserved for future use
Note: Shaded cells are not used by the Watchdog Timer.
DS40182C-page 62
1999 Microchip Technology Inc.
PIC16CE62X
The first event will cause a device reset. The two latter
events are considered a continuation of program exe-
cution. The TO and PD bits in the STATUS register can
be used to determine the cause of device reset. PD
bit, which is set on power-up is cleared when SLEEP is
invoked. TO bit is cleared if WDT wake-up occurred.
10.8
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set and the oscillator driver is
turned off. The I/O ports maintain the status they had
before SLEEP was executed (driving high, low, or
hi-impedance).
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOPafter the SLEEPinstruction.
For lowest current consumption in this mode, all I/O
pins should be either at VDD or VSS, with no external
circuitry drawing current from the I/O pin, and the com-
parators and VREF should be disabled. I/O pins that are
hi-impedance inputs should be pulled high or low exter-
nally to avoid switching currents caused by floating
inputs. The T0CKI input should also be at VDD or VSS
for lowest current consumption. The contribution from
on chip pull-ups on PORTB should be considered.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from sleep. The
sleep instruction is completely executed.
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
10.8.1 WAKE-UP FROM SLEEP
The WDT is cleared when the device wakes-up from
sleep, regardless of the source of wake-up.
The device can wake-up from SLEEP through one of
the following events:
1. External reset input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
FIGURE 10-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
TOST(2)
INTF flag
(INTCON<1>)
Interrupt Latency
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Inst(PC - 1)
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay does not occur for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
1999 Microchip Technology Inc.
DS40182C-page 63
PIC16CE62X
10.9
Code Protection
10.11 In-Circuit Serial Programming
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
The PIC16CE62X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
Note: Microchip does not recommend code
protecting windowed devices.
10.10 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify. Only the
least significant 4 bits of the ID locations are used.
The device is placed into a program/verify mode by
holding the RB6 and RB7 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After reset, to place the device into programming/verify
mode, the program counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending if the
command was a load or a read. For complete details of
serial
programming,
please
refer
to
the
PIC16C6X/7X/9XX Programming Specifications (Liter-
ature #DS30228).
A typical in-circuit serial programming connection is
shown in Figure 10-20.
FIGURE 10-20: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16CE62X
+5V
0V
VDD
VSS
VPP
MCLR/VPP
RB6
RB7
CLK
Data I/O
VDD
To Normal
Connections
DS40182C-page 64
1999 Microchip Technology Inc.
PIC16CE62X
The instruction set is highly orthogonal and is grouped
into three basic categories:
11.0 INSTRUCTION SET SUMMARY
Each PIC16CE62X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CE62X instruc-
tion set summary in Table 11-2 lists byte-oriented,
bit-oriented, and literal and control operations.
Table 11-1 shows the opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, ’f’ represents a file
register designator and ’d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is 1 µs. If
a
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
Table 11-1 lists the instructions recognized by the
MPASM assembler.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Figure 11-1 shows the three general formats that the
instructions can have.
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
Note: To maintain upward compatibility with
future PICmicro® products, do not use the
OPTIONand TRISinstructions.
TABLE 11-1: OPCODE FIELD
DESCRIPTIONS
All examples use the following format to represent a
hexadecimal number:
Field
Description
0xhh
f
W
b
k
x
Register file address (0x00 to 0x7F)
Working register (accumulator)
where h signifies a hexadecimal digit.
FIGURE 11-1: GENERAL FORMAT FOR
INSTRUCTIONS
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1)
Byte-oriented file register operations
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
13
8
7
6
0
0
OPCODE
d
f (FILE #)
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
label Label name
TOS Top of Stack
PC Program Counter
Bit-oriented file register operations
13 10 9
b (BIT #)
7
6
OPCODE
f (FILE #)
PCLATH
Program Counter High Latch
GIE Global Interrupt Enable bit
WDT Watchdog Timer/Counter
TO Time-out bit
b = 3-bit bit address
f = 7-bit file register address
PD Power-down bit
Literal and control operations
dest Destination either the W register or the specified
register file location
General
[ ] Options
13
8
7
0
0
Contents
( )
→
OPCODE
k (literal)
Assigned to
k = 8-bit immediate value
Register bit field
In the set of
< >
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
User defined term (font is courier)
italics
k (literal)
1999 Microchip Technology Inc.
DS40182C-page 65
PIC16CE62X
TABLE 11-2: PIC16CE62X INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
Status
Affected
Notes
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
f, d Add W and f
f, d AND W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
f
-
Clear f
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
DECFSZ
INCF
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
Z
Z
1,2
f
-
Move W to f
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
1
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
1 (2) 01
1 (2) 01
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
1001 kkkk kkkk
0kkk kkkk kkkk
Z
0000 0110 0100 TO,PD
1kkk kkkk kkkk
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40182C-page 66
1999 Microchip Technology Inc.
PIC16CE62X
11.1
Instruction Descriptions
ANDLW
AND Literal with W
ADDLW
Add Literal and W
Syntax:
[ label ] ANDLW
k
Syntax:
[ label ] ADDLW
k
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Operation:
Z
Status Affected:
Encoding:
11
1001
kkkk
kkkk
11
111x
kkkk
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of the W register are
added to the eight bit literal ’k’ and the
result is placed in the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ANDLW
0x5F
ADDLW
0x15
Before Instruction
Before Instruction
W
=
0xA3
0x03
W
=
0x10
0x25
After Instruction
After Instruction
W
=
W
=
ADDWF
Syntax:
Add W and f
ANDWF
Syntax:
AND W with f
[ label ] ADDWF f,d
[ label ] ANDWF f,d
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected:
Encoding:
C, DC, Z
Status Affected:
Encoding:
Z
00
0111
dfff
ffff
00
0101
dfff
ffff
Add the contents of the W register
with register ’f’. If ’d’ is 0, the result is
stored in the W register. If ’d’ is 1, the
result is stored back in register ’f’.
AND the W register with register 'f'. If
'd' is 0, the result is stored in the W
register. If 'd' is 1, the result is stored
back in register 'f'.
Description:
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
ADDWF
FSR,
0
ANDWF
FSR, 1
Before Instruction
Before Instruction
W
FSR =
=
0x17
0xC2
W
FSR =
=
0x17
0xC2
After Instruction
After Instruction
W
FSR =
=
0xD9
0xC2
W
FSR =
=
0x17
0x02
1999 Microchip Technology Inc.
DS40182C-page 67
PIC16CE62X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
Operands:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
If bit ’b’ in register ’f’ is ’0’, then the next
instruction is skipped.
Bit ’b’ in register ’f’ is cleared.
Description:
1
1
If bit ’b’ is ’0’, then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a
two-cycle instruction.
Cycles:
BCF
FLAG_REG, 7
Example
Before Instruction
FLAG_REG = 0xC7
After Instruction
Words:
Cycles:
Example
1
1(2)
FLAG_REG = 0x47
HERE
FALSE
TRUE
BTFSC FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
BSF
Bit Set f
Syntax:
Operands:
[ label ] BSF f,b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
1 → (f<b>)
None
01
01bb
bfff
ffff
Bit ’b’ in register ’f’ is set.
1
1
Cycles:
BSF
FLAG_REG,
7
Example
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS40182C-page 68
1999 Microchip Technology Inc.
PIC16CE62X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
[ label ] CLRF
Syntax:
[ label ] BTFSS f,b
Syntax:
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
0 ≤ f ≤ 127
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
None
Status Affected:
Encoding:
Status Affected:
Encoding:
Z
01
11bb
bfff
ffff
00
0001
1fff
ffff
If bit ’b’ in register ’f’ is ’1’ then the next
instruction is skipped.
The contents of register ’f’ are cleared
and the Z bit is set.
Description:
Description:
If bit ’b’ is ’1’, then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a
two-cycle instruction.
Words:
Cycles:
Example
1
1
CLRF
FLAG_REG
Before Instruction
FLAG_REG
After Instruction
FLAG_REG
Z
Words:
Cycles:
Example
1
=
0x5A
1(2)
=
=
0x00
1
HERE
FALSE
TRUE
BTFSS FLAG,1
GOTO
PROCESS_CODE
•
•
•
Before Instruction
PC
=
address HERE
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
CLRW
Clear W
Syntax:
[ label ] CLRW
None
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
Operands:
Operation:
Syntax:
00h → (W)
1 → Z
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
Encoding:
Z
00
0001
0000
0011
Status Affected:
Encoding:
None
W register is cleared. Zero bit (Z) is
set.
Description:
10
0kkk
kkkk
kkkk
Words:
Cycles:
Example
1
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
Description:
1
CLRW
Before Instruction
W
=
0x5A
After Instruction
W
Z
=
=
0x00
1
Words:
Cycles:
Example
1
2
HERE
CALL THERE
Before Instruction
PC
=
Address HERE
After Instruction
PC
= Address THERE
TOS = Address HERE+1
1999 Microchip Technology Inc.
DS40182C-page 69
PIC16CE62X
CLRWDT
Syntax:
Clear Watchdog Timer
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 127
[ label ] CLRWDT
None
Syntax:
Operands:
Operands:
Operation:
d
[0,1]
00h → WDT
0 → WDT prescaler,
1 → TO
Operation:
(f) - 1 → (dest)
Status Affected:
Encoding:
Z
1 → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Decrement register ’f’. If ’d’ is 0, the
result is stored in the W register. If ’d’
is 1, the result is stored back in regis-
ter ’f’.
Description:
00
0000
0110
0100
CLRWDTinstruction resets the
Description:
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits TO
and PD are set.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
DECF
CNT, 1
1
Before Instruction
CLRWDT
CNT
Z
=
=
0x01
0
Before Instruction
After Instruction
WDT counter
After Instruction
=
=
?
CNT
Z
=
=
0x00
1
WDT counter
0x00
WDT prescaler=
0
1
1
TO
PD
=
=
COMF
Complement f
[ label ] COMF f,d
0 ≤ f ≤ 127
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) - 1 → (dest); skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1001
dfff
ffff
00
1011
dfff
ffff
The contents of register ’f’ are
Description:
The contents of register ’f’ are
Description:
complemented. If ’d’ is 0, the result is
stored in W. If ’d’ is 1, the result is
stored back in register ’f’.
decremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1, the
result is placed back in register ’f’.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOPis executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
1
COMF
REG1,0
Before Instruction
Words:
Cycles:
Example
1
REG1
After Instruction
REG1
=
0x13
1(2)
HERE
DECFSZ
GOTO
CNT, 1
LOOP
=
=
0x13
0xEC
W
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
if CNT =
PC
if CNT ≠
PC
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
=
=
DS40182C-page 70
1999 Microchip Technology Inc.
PIC16CE62X
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 127
Syntax:
Operands:
Operation:
Operands:
d
[0,1]
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) + 1 → (dest), skip if result = 0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1111
dfff
ffff
GOTOis an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
The contents of register ’f’ are
Description:
Description:
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1, the
result is placed back in register ’f’.
If the result is 0, the next instruction,
which is already fetched, is discarded.
A NOPis executed instead making it a
two-cycle instruction.
Words:
Cycles:
Example
1
2
GOTO THERE
Words:
Cycles:
Example
1
After Instruction
1(2)
PC
=
Address THERE
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address HERE
After Instruction
CNT
=
CNT + 1
if CNT=
0,
PC
if CNT≠
=
address CONTINUE
0,
PC
=
address HERE +1
INCF
Increment f
IORLW
Inclusive OR Literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
0 ≤ f ≤ 127
d
[0,1]
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operation:
(f) + 1 → (dest)
(W) .OR. k → (W)
Z
Status Affected:
Encoding:
Z
00
1010
dfff
ffff
11
1000
kkkk
kkkk
The contents of register ’f’ are
Description:
The contents of the W register are
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1, the
result is placed back in register ’f’.
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
IORLW
0x35
INCF
CNT, 1
Before Instruction
Before Instruction
W
=
0x9A
CNT
Z
=
=
0xFF
0
After Instruction
W
Z
=
=
0xBF
1
After Instruction
CNT
Z
=
=
0x00
1
1999 Microchip Technology Inc.
DS40182C-page 71
PIC16CE62X
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
Syntax:
Operands:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ 127
0 ≤ f ≤ 127
d
[0,1]
d
[0,1]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Inclusive OR the W register with
register ’f’. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1, the
result is placed back in register ’f’.
The contents of register f are moved
to a destination dependant upon the
status of d. If d = 0, destination is W
register. If d = 1, the destination is file
register f itself. d = 1 is useful to test a
file register since status flag Z is
affected.
Description:
Description:
Words:
Cycles:
Example
1
1
IORWF
RESULT, 0
Words:
Cycles:
Example
1
1
Before Instruction
RESULT =
0x13
0x91
MOVF
FSR, 0
W
=
After Instruction
After Instruction
RESULT =
W
Z
0x13
0x93
1
W = value in FSR register
=
=
Z
= 1
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
MOVWF
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 127
(W) → (f)
Syntax:
Syntax:
f
Operands:
Operation:
Status Affected:
Encoding:
Description:
Operands:
Operation:
Status Affected:
Encoding:
Description:
k → (W)
None
None
11
00xx
kkkk
kkkk
00
0000
1fff
ffff
The eight bit literal ’k’ is loaded into W
register. The don’t cares will assemble
as 0’s.
Move data from W register to register
'f'.
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
MOVWF
OPTION
MOVLW
0x5A
Before Instruction
After Instruction
OPTION =
0xFF
0x4F
W
=
0x5A
W
=
After Instruction
OPTION =
0x4F
0x4F
W
=
DS40182C-page 72
1999 Microchip Technology Inc.
PIC16CE62X
NOP
No Operation
[ label ] NOP
None
RETFIE
Return from Interrupt
[ label ] RETFIE
None
Syntax:
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Operands:
Operation:
No operation
None
TOS → PC,
1 → GIE
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global Interrupt Enable bit,
GIE (INTCON<7>). This is a two-cycle
instruction.
Description:
1
Cycles:
1
NOP
Example
Words:
Cycles:
Example
1
2
RETFIE
After Interrupt
PC
GIE =
=
TOS
1
OPTION
Syntax:
Load Option Register
[ label ] OPTION
None
RETLW
Return with Literal in W
[ label ] RETLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Operands:
Operation:
(W) → OPTION
k → (W);
TOS → PC
Status Affected: None
00
0000
0110
0010
Encoding:
Status Affected:
Encoding:
None
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code
compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly
address it.
Description:
11
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
2
CALL TABLE
;W contains table
;offset value
;W now has table
To maintain upward compatibility
•
®
value
with future PICmicro products, do
not use this instruction.
•
•
TABLE
ADDWF PC
;W = offset
;Begin table
;
RETLW k1
RETLW k2
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
1999 Microchip Technology Inc.
DS40182C-page 73
PIC16CE62X
RETURN
Return from Subroutine
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] RETURN
None
Syntax:
Operands:
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
TOS → PC
None
Operation:
See description below
C
Status Affected:
Encoding:
00
0000
0000
1000
00
1100
dfff
ffff
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two cycle instruction.
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
placed back in register ’f’.
Description:
Words:
Cycles:
Example
1
2
C
Register f
RETURN
Words:
Cycles:
Example
1
1
After Interrupt
PC
=
TOS
RRF
REG1,0
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
RLF
Rotate Left f through Carry
SLEEP
Syntax:
Operands:
[ label ]
RLF f,d
Syntax:
[ label ] SLEEP
None
0 ≤ f ≤ 127
Operands:
Operation:
d
[0,1]
00h → WDT,
0 → WDT prescaler,
1 → TO,
Operation:
See description below
C
Status Affected:
Encoding:
00
1101
dfff
ffff
0 → PD
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0, the result is placed in
the W register. If ’d’ is 1, the result is
stored back in register ’f’.
Status Affected:
Encoding:
TO, PD
Description:
00
0000
0110
0011
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its
Description:
C
Register f
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
See Section 10.8 for more details.
Words:
Cycles:
Example
1
1
RLF
REG1,0
Words:
1
Before Instruction
Cycles:
Example:
1
REG1
C
=
=
1110 0110
0
SLEEP
After Instruction
REG1
W
C
=
=
=
1110 0110
1100 1100
1
DS40182C-page 74
1999 Microchip Technology Inc.
PIC16CE62X
SUBLW
Subtract W from Literal
SUBWF
Syntax:
Subtract W from f
Syntax:
[ label ]
SUBLW k
[ label ]
SUBWF f,d
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d
[0,1]
k - (W) → (W)
Operation:
(f) - (W) → (dest)
Status
C, DC, Z
Affected:
Status
C, DC, Z
Affected:
Encoding:
11
110x
kkkk
kkkk
Encoding:
00
0010
dfff
ffff
The W register is subtracted (2’s com-
plement method) from the eight bit literal
'k'. The result is placed in the W register.
Description:
Subtract (2’s complement method)
Description:
W register from register 'f'. If 'd' is 0, the
result is stored in the W register. If 'd' is 1,
the result is stored back in register 'f'.
Words:
1
1
Cycles:
Words:
1
1
Example 1:
SUBLW
0x02
Cycles:
Before Instruction
Example 1:
SUBWF
REG1,1
W
C
=
=
1
?
Before Instruction
REG1
W
C
=
=
=
3
2
?
After Instruction
W
C
=
=
1
1; result is positive
After Instruction
Example 2:
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
W
C
=
=
2
?
1; result is positive
After Instruction
Example 2:
Before Instruction
W
C
=
=
0
REG1
W
=
=
=
2
2
?
1; result is zero
C
Before Instruction
After Instruction
W
C
=
=
3
?
REG1
W
=
=
=
0
2
After Instruction
C
1; result is zero
W
=
0xFF
Example 3:
Before Instruction
C
=
0; result is nega-
tive
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
0xFF
2
0; result is negative
1999 Microchip Technology Inc.
DS40182C-page 75
PIC16CE62X
SWAPF
Syntax:
Swap Nibbles in f
XORLW
Exclusive OR Literal with W
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
Status Affected:
Encoding:
d
[0,1]
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
11
1010 kkkk kkkk
Status Affected:
Encoding:
None
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the
W register.
Description:
00
1110
dfff
ffff
The upper and lower nibbles of
Description:
register ’f’ are exchanged. If ’d’ is 0,
the result is placed in W register. If ’d’
is 1, the result is placed in register ’f’.
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
SWAPF REG,
0
W
=
0xB5
0x1A
Before Instruction
REG1
After Instruction
=
0xA5
W
=
After Instruction
REG1
W
=
=
0xA5
0x5A
TRIS
Load TRIS Register
XORWF
Syntax:
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 127
Syntax:
[ label ] TRIS
f
Operands:
Operation:
5 ≤ f ≤ 7
Operands:
d
[0,1]
(W) → TRIS register f;
Status Affected: None
Operation:
(W) .XOR. (f) → (dest)
00
Encoding:
0000 0110
0fff
Status Affected:
Encoding:
Z
The instruction is supported for code
compatibility with the PIC16C5X
products. Since TRIS registers are
readable and writable, the user can
directly address them.
Description:
00
0110
dfff
ffff
Exclusive OR the contents of the
W register with register 'f'. If 'd' is 0,
the result is stored in the W register. If
'd' is 1, the result is stored back in reg-
ister 'f'.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
To maintain upward compatibility
REG
1
XORWF
®
with future PICmicro products, do
Before Instruction
not use this instruction.
REG
W
=
=
0xAF
0xB5
After Instruction
REG
W
=
=
0x1A
0xB5
DS40182C-page 76
1999 Microchip Technology Inc.
PIC16CE62X
MPLAB allows you to:
12.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- PICMASTER®/PICMASTER-CE In-Circuit
12.2
MPASM Assembler
Emulator
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- ICEPIC™
• In-Circuit Debugger
- MPLAB-ICD for PIC16F877
• Device Programmers
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
• Low-Cost Demonstration Boards
- SIMICE
- PICDEM-1
- PICDEM-2
- PICDEM-3
MPASM features include:
- PICDEM-17
- SEEVAL
• MPASM and MPLINK are integrated into MPLAB
projects.
- KEELOQ
• MPASM allows user defined macros to be created
for streamlined assembly.
12.1
MPLAB Integrated Development
Environment Software
• MPASM allows conditional assembly for multi pur-
pose source files.
• MPASM directives allow complete control over the
assembly process.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
12.3
MPLAB-C17 and MPLAB-C18
C Compilers
• Multiple functionality
- editor
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
- simulator
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• On-line help
1999 Microchip Technology Inc.
DS40182C-page 77
PIC16CE62X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
12.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
12.7
PICMASTER/PICMASTER CE
The PICMASTER system from Microchip Technology is
a full-featured, professional quality emulator system.
This flexible in-circuit emulator provides a high-quality,
universal platform for emulating Microchip 8-bit
PICmicro microcontrollers (MCUs). PICMASTER sys-
tems are sold worldwide, with a CE compliant model
available for European Union (EU) countries.
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
12.8
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of
interchangeable personality modules or daughter
boards. The emulator is capable of emulating without
target application circuitry being present.
12.5
MPLAB-SIM Software Simulator
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
12.9
MPLAB-ICD In-Circuit Debugger
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
12.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS40182C-page 78
1999 Microchip Technology Inc.
PIC16CE62X
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
12.10 PRO MATE II Universal Programmer
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
12.14 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
12.11 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
12.12 SIMICE Entry-Level
Hardware Simulator
SIMICE is an entry-level hardware development sys-
tem designed to operate in a PC-based environment
with Microchip’s simulator MPLAB-SIM. Both SIMICE
and MPLAB-SIM run under Microchip Technology’s
MPLAB Integrated Development Environment (IDE)
software. Specifically, SIMICE provides hardware sim-
ulation for Microchip’s PIC12C5XX, PIC12CE5XX, and
PIC16C5X families of PICmicro 8-bit microcontrollers.
SIMICE works in conjunction with MPLAB-SIM to pro-
vide non-real-time I/O port emulation. SIMICE enables
a developer to run simulator code for driving the target
system. In addition, the target system can provide input
to the simulator code. This capability allows for simple
and interactive debugging without having to manually
generate MPLAB-SIM stimulus files. SIMICE is a valu-
able debugging tool for entry-level system develop-
ment.
12.15 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
12.13 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
1999 Microchip Technology Inc.
DS40182C-page 79
PIC16CE62X
12.16 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
12.17 SEEVAL Evaluation and Programming
System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in trade-
off analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
12.18 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS40182C-page 80
1999 Microchip Technology Inc.
PIC16CE62X
TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP
0
2 5 P 1 C M
X X X C R M F
X
H C S X X
X X C 9 3
C 5 X 2 X /
C 4 X 2 X /
2 X X 1 8 C I C P
X X 7 1 7 C I C P
X 4 C 7 C 1 P I
X X 9 1 6 C I C P
X 8 X 6 1 F C I P
X 8 C 6 C 1 P I
X X 7 1 6 C I C P
X 7 C 6 C 1 P I
X 2 6 F 6 C 1 P I
X X C 6 X C 1 P I
X 6 C 6 C 1 P I
X 5 C 6 C 1 P I
0
4 0 1 0 C I P
X X C 2 X C 1 P I
l s o o T e w f a t o r S s o t r a l
E m r u g g b e e u D s r e m m r a g o P r
s
K l a i t E d v n a s d r a B o o m D e
1999 Microchip Technology Inc.
DS40182C-page 81
PIC16CE62X
NOTES:
DS40182C-page 82
1999 Microchip Technology Inc.
PIC16CE62X
13.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings †
Ambient Temperature under bias.............................................................................................................. -40° to +125°C
Storage Temperature ................................................................................................................................ -65° to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR)........................................................-0.6V to VDD +0.6V
Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V
Voltage on RA4 with respect to VSS...........................................................................................................................8.5V
Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V
Voltage on RA4 with respect to VSS...........................................................................................................................8.5V
Total power Dissipation (Note 1) ...............................................................................................................................1.0W
Maximum Current out of VSS pin...........................................................................................................................300 mA
Maximum Current into VDD pin .............................................................................................................................250 mA
Input Clamp Current, IIK (VI <0 or VI> VDD)...................................................................................................................... ±20 mA
Output Clamp Current, IOK (VO <0 or VO>VDD)................................................................................................................ ±20 mA
Maximum Output Current sunk by any I/O pin........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin...................................................................................................25 mA
Maximum Current sunk by PORTA and PORTB ...................................................................................................200 mA
Maximum Current sourced by PORTA and PORTB..............................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100¾ should be used when applying a "low" level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above
those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1999 Microchip Technology Inc.
DS40182C-page 83
PIC16CE62X
FIGURE 13-1: PIC16CE62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 13-2: PIC16CE62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ +125°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS40182C-page 84
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 13-3: PIC16LCE62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < +125°C
6.0
5.5
5.0
4.5
4.0
3.5
VDD
(Volts)
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1999 Microchip Technology Inc.
DS40182C-page 85
PIC16CE62X
13.1
DC CHARACTERISTICS:
PIC16CE62X-04 (Commercial, Industrial, Extended)
PIC16CE62X-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Supply Voltage
Min Typ† Max Units
Conditions
D001
VDD
3.0
–
5.5
–
V
V
See Figure 13-1 through Figure 13-3
Device in SLEEP mode
D002
VDR
RAM Data Retention
Voltage (Note 1)
–
1.5*
D003
D004
VPOR
SVDD
VDD start voltage to
ensure Power-on Reset
–
VSS
–
–
V
See section on power-on reset for details
VDD rise rate to ensure
0.05*
–
V/ms See section on power-on reset for details
Power-on Reset
D005
D010
VBOR
IDD
Brown-out Detect Voltage
Supply Current (Note 2, 4)
3.7
–
4.0 4.35
V
BOREN configuration bit is cleared
1.2
0.4
1.0
4.0
4.0
35
2.0
1.2
2.0
6.0
7.0
70
mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled,
XT osc mode, (Note 4)*
mA FOSC = 4 MHz, VDD = 3.0V, WDT disabled,
XT osc mode, (Note 4)
mA FOSC = 10 MHz, VDD = 3.0V, WDT disabled,
HS osc mode, (Note 6)
mA FOSC = 20 MHz, VDD = 4.5V, WDT disabled,
HS osc mode
mA FOSC = 20 MHz, VDD = 5.5V, WDT disabled*,
HS osc mode
µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled,
LP osc mode
–
–
–
–
–
D020
D022
IPD
Power Down Current (Note 3)
WDT Current (Note 5)
–
–
–
–
–
–
–
–
2.2
5.0
9.0
15
µA VDD = 3.0V
µA VDD = 4.5V*
µA VDD = 5.5V
µA VDD = 5.5V Extended
∆IWDT
–
6.0
10
12
µA VDD = 4.0V
µA (125°C)
D022A ∆IBOR
D023 ∆ICOMP
Brown-out Reset Current (Note 5)
Comparator Current for each
Comparator (Note 5)
–
–
75
30
125
60
µA BOD enabled, VDD = 5.0V
µA VDD = 4.0V
D023A ∆IVREF
VREF Current (Note 5)
–
80
135
µA VDD = 4.0V
∆IEE Write Operating Current
∆IEE Read Operating Current
–
–
–
–
3
1
30
100
mA VCC = 5.5V, SCL = 400 kHz
mA
µA VCC = 3.0V, EE VDD = VCC
µA VCC = 3.0V, EE VDD = VCC
∆IEE
∆IEE
Standby Current
Standby Current
1A
FOSC
LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
–
–
–
–
200 kHz All temperatures
4
4
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for-
mula Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
DS40182C-page 86
1999 Microchip Technology Inc.
PIC16CE62X
13.2
DC CHARACTERISTICS:
PIC16LCE62X-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
–40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
–40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Supply Voltage
Min
Typ† Max Units
Conditions
D001
VDD
2.5
–
5.5
–
V
V
See Figure 13-1 through Figure 13-3
Device in SLEEP mode
D002
VDR
RAM Data Retention
Voltage (Note 1)
–
1.5*
D003
D004
VPOR
SVDD
VDD start voltage to
ensure Power-on Reset
–
VSS
–
–
V
See section on power-on reset for details
VDD rise rate to ensure
Power-on Reset
.05*
–
V/ms See section on power-on reset for details
BOREN configuration bit is cleared
D005
D010
VBOR
IDD
Brown-out Detect Voltage
Supply Current (Note 2)
3.7
–
4.0
1.2
4.35
2.0
V
mA FOSC = 4 MHz, VDD = 5.5V, WDT disabled,
XT osc mode, (Note 4)*
–
–
–
1.1
70
mA FOSC = 4 MHz, VDD = 2.5V, WDT disabled,
XT osc mode, (Note 4)
35
µA
FOSC = 32 kHz, VDD = 2.5V, WDT disabled,
LP osc mode
D020
D022
IPD
Power Down Current (Note 3)
WDT Current (Note 5)
–
–
–
–
–
–
–
–
2.0
2.2
9.0
15
µA
µA
µA
µA
VDD = 2.5V
VDD = 3.0V*
VDD = 5.5V
VDD = 5.5V Extended
∆IWDT
–
–
–
–
6.0
75
30
80
10
12
125
µA
µA
µA
VDD=4.0V
(125°C)
BOD enabled, VDD = 5.0V
D022A ∆IBOR
D023 ∆ICOMP
D023A ∆IVREF
Brown-out Reset Current
(Note 5)
Comparator Current for each
Comparator (Note 5)
VREF Current (Note 5)
60
µA
VDD = 4.0V
135
µA
VDD = 4.0V
∆IEE Write Operating Current
∆IEE Read Operating Current
–
–
–
–
3
1
30
100
mA VCC = 5.5V, SCL = 400 kHz
mA
∆IEE
∆IEE
Standby Current
Standby Current
µA
µA
VCC = 3.0V, EE VDD = VCC
VCC = 3.0V, EE VDD = VCC
1A
FOSC
LP Oscillator Operating Frequency
RC Oscillator Operating Frequency
XT Oscillator Operating Frequency
HS Oscillator Operating Frequency
0
0
0
0
—
—
—
—
200
4
4
kHz All temperatures
MHz All temperatures
MHz All temperatures
MHz All temperatures
20
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is measured with the
part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the for-
mula Ir = VDD/2Rext (mA) with Rext in kΩ.
5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base
IDD or IPD measurement.
6: Commercial temperature range only.
1999 Microchip Technology Inc.
DS40182C-page 87
PIC16CE62X
13.3
DC CHARACTERISTICS:
PIC16CE62X-04 (Commercial, Industrial, Extended)
PIC16CE62X-20 (Commercial, Industrial, Extended)
PIC16LCE62X (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature –40°C ≤ TA ≤ +85°C for industrial and
0°C ≤ TA ≤ +70°C for commercial and
DC CHARACTERISTICS
–40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 13-1
Parm Sym
No.
Characteristic
Min
Typ†
Max
Unit
Conditions
VIL
Input Low Voltage
I/O ports
D030
with TTL buffer
VSS
–
–
0.8V
V
VDD = 4.5V to 5.5V, Otherwise
0.15VDD
0.2VDD
0.2VDD
D031
D032
with Schmitt Trigger input
MCLR, RA4/T0CKI,OSC1 (in RC
mode)
VSS
VSS
V
V
Note1
D033
OSC1 (in XT and HS)
OSC1 (in LP)
VSS
VSS
–
–
0.3VDD
0.6VDD - 1.0
V
V
VIH Input High Voltage
I/O ports
D040
with TTL buffer
2.0V
.25VDD + 0.8V
0.8VDD
0.8VDD
0.7VDD
0.9VDD
50
–
VDD
VDD
V
VDD = 4.5V to 5.5V, Otherwise
D041
D042
D043
D043A
D070
with Schmitt Trigger input
VDD
VDD
VDD
MCLR RA4/T0CKI
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
–
–
V
V
Note1
IPURB PORTB weak pull-up current
Input Leakage Current
200
400
µA VDD = 5.0V, VPIN = VSS
IIL
(Notes 2, 3)
I/O ports (Except PORTA)
PORTA
±1.0
±0.5
±1.0
±5.0
µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD, pin at hi-impedance
µA Vss ≤ VPIN ≤ VDD
D060
D061
D063
–
–
–
–
–
–
RA4/T0CKI
OSC1, MCLR
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
D080
D083
I/O ports
–
–
–
–
–
–
–
–
0.6
0.6
0.6
0.6
V
V
V
V
IOL=8.5 mA, VDD=4.5V, -40° to +85°C
IOL=7.0 mA, VDD=4.5V, +125°C
IOL=1.6 mA, VDD=4.5V, -40° to +85°C
IOL=1.2 mA, VDD=4.5V, +125°C
OSC2/CLKOUT (RC only)
VOH Output High Voltage (Note 3)
D090
D092
*D150
I/O ports (Except RA4)
VDD-0.7
VDD-0.7
VDD-0.7
VDD-0.7
–
–
–
–
–
–
V
V
V
V
V
IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
IOH=-2.5 mA, VDD=4.5V, +125°C
IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
IOH=-1.0 mA, VDD=4.5V, +125°C
RA4 pin
OSC2/CLKOUT (RC only)
–
–
VOD Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
8.5
D100 COSC OSC2 pin
2
15
50
pF In XT, HS and LP modes when external
clock used to drive OSC1.
pF
D101
Cio All I/O pins/OSC2 (in RC mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16CE62X be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS40182C-page 88
1999 Microchip Technology Inc.
PIC16CE62X
TABLE 13-1: COMPARATOR SPECIFICATIONS
Operating Conditions: VDD range as described in Table 12-1, -40°C<TA<+125°C. .
Param No.
Characteristics
Input offset voltage
Sym
Min
Typ
Max
Units
Comments
D300
D301
D302
300
VIOFF
± 5.0
± 10
mV
V
Input common mode voltage
CMRR
VICM
0
VDD - 1.5
CMRR
TRESP
+55*
db
ns
Response Time(1)
150*
400*
10*
PIC16CE62X
301
Comparator Mode Change to
Output Valid
TMC2OV
µs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 13-2: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: VDD range as described in Table 12-1, -40°C<TA<+125°C.
Param
No.
Characteristics
Resolution
Sym
Min
Typ
Max
Units
Comments
D310
VRES
VRAA
VDD/24
VDD/32
LSB
D311
Absolute Accuracy
+1/4
+1/2
LSB
LSB
Low Range (VRR=1)
High Range (VRR=0)
D312
310
Unit Resistor Value (R)
Settling Time(1)
VRUR
TSET
2K*
Ω
Figure 9-1
10*
µs
* These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000to 1111.
1999 Microchip Technology Inc.
DS40182C-page 89
PIC16CE62X
13.4
Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
T
Time
CLKOUT
I/O port
MCLR
osc
t0
OSC1
T0CKI
io
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-Impedance
FIGURE 13-4: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
DS40182C-page 90
1999 Microchip Technology Inc.
PIC16CE62X
13.5
Timing Diagrams and Specifications
FIGURE 13-5: EXTERNAL CLOCK TIMING
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 13-3: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ†
Max
Units Conditions
1A
Fosc External CLKIN Frequency
DC
DC
DC
DC
0.1
1
—
—
—
—
—
—
–
4
20
MHz XT and RC osc mode, VDD=5.0V
MHz HS osc mode
(Note 1)
200
4
kHz LP osc mode
Oscillator Frequency
(Note 1)
MHz RC osc mode, VDD=5.0V
MHz XT osc mode
4
20
MHz HS osc mode
DC
250
50
200
—
kHz LP osc mode
1
Tosc External CLKIN Period
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
µs
ns
ns
ns
µs
ns
ns
µs
ns
ns
ns
ns
XT and RC osc mode
HS osc mode
(Note 1)
—
5
—
LP osc mode
Oscillator Period
(Note 1)
250
250
50
—
RC osc mode
10,000
1,000
—
XT osc mode
HS osc mode
5
LP osc mode
2
TCY
Instruction Cycle Time (Note 1)
200
100*
2*
DC
—
TCY=FOSC/4
3*
TosL, External Clock in (OSC1) High or
TosH Low Time
XT oscillator, TOSC L/H duty cycle
LP oscillator, TOSC L/H duty cycle
HS oscillator, TOSC L/H duty cycle
XT oscillator
—
20*
25*
50*
15*
—
4*
TosR, External Clock in (OSC1) Rise or
TosF Fall Time
—
—
LP oscillator
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1 pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
1999 Microchip Technology Inc.
DS40182C-page 91
PIC16CE62X
FIGURE 13-6: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
22
23
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: All tests must be do with specified capacitance loads (Figure 13-4) 50 pF on I/O pins and CLKOUT
TABLE 13-4: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter # Sym
Characteristic
Min
Typ†
Max
Units
ns
(1)
10*
11*
12*
13*
14*
15*
16*
TosH2ckL
—
75
75
35
35
—
—
—
200
OSC1↑ to CLKOUT↓
OSC1↑ to CLKOUT↑
(1)
TosH2ckH
TckR
—
ns
200
100
(1)
—
ns
CLKOUT rise time
CLKOUT fall time
(1)
TckF
—
100
20
—
ns
(1)
TckL2ioV
TioV2ckH
TckH2ioI
—
ns
CLKOUT ↓ to Port out valid
Port in valid before CLKOUT ↑
(1)
(1)
Tosc +200 ns
0
ns
—
ns
Port in hold after CLKOUT ↑
17*
18*
TosH2ioV
TosH2ioI
OSC1↑ (Q1 cycle) to Port out valid
—
50
—
150
—
ns
ns
OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold
100
time)
19*
20*
21*
22*
23
TioV2osH
TioR
Port input valid to OSC1↑ (I/O in setup time)
Port output rise time
0
—
—
10
10
—
—
—
40
40
—
—
ns
ns
ns
ns
ns
TioF
Port output fall time
—
Tinp
RB0/INT pin high or low time
RB<7:4> change interrupt high or low time
25
TCY
Trbp
*
†
These parameters are characterized but not tested
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS40182C-page 92
1999 Microchip Technology Inc.
PIC16CE62X
FIGURE 13-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 13-8: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 13-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2000
—
—
ns
-40° to +85°C
31
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7*
18
33*
ms
VDD = 5.0V, -40° to +85°C
32
33
34
35
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
132*
2.0
—
—
ms
µs
TOSC = OSC1 period
Tpwrt Power-up Timer Period
28*
72
—
—
VDD = 5.0V, -40° to +85°C
TIOZ
I/O hi-impedance from MCLR low
Brown-out Reset Pulse Width
TBOR
100*
µs 3.7V ≤ VDD ≤ 4.3V
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
1999 Microchip Technology Inc.
DS40182C-page 93
PIC16CE62X
FIGURE 13-9: TIMER0 CLOCK TIMING
RA4/T0CKI
41
40
42
TMR0
TABLE 13-6: TIMER0 CLOCK REQUIREMENTS
Parameter Sym Characteristic
No.
Min
Typ† Max Units Conditions
40
41
42
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20*
10*
TCY + 40*
N = prescale value
(1, 2, 4, ..., 256)
N
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS40182C-page 94
1999 Microchip Technology Inc.
PIC16CE62X
13.6
EEPROM Timing
FIGURE 13-10: BUS TIMING DATA
TR
TF
THIGH
TLOW
SCL
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
THD:STA
SDA
IN
TSP
TAA
THD:STA
TAA
TBUF
SDA
OUT
TABLE 13-7: AC CHARACTERISTICS
STANDARD
MODE
Vcc = 4.5 - 5.5V
FAST MODE
Parameter
Symbol
Units
Remarks
Min.
Max.
Min.
Max.
Clock frequency
FCLK
THIGH
TLOW
TR
—
4000
4700
—
100
—
—
600
1300
—
400
—
kHz
ns
Clock high time
Clock low time
—
—
ns
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
1000
300
—
300
300
—
ns
(Note 1)
(Note 1)
TF
—
—
ns
THD:STA
4000
600
ns
After this period the first
clock pulse is generated
START condition setup time
TSU:STA
4700
—
600
—
ns
Only relevant for repeated
START condition
Data input hold time
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
THD:DAT
TSU:DAT
TSU:STO
TAA
0
—
—
0
—
—
ns
ns
ns
ns
ns
(Note 2)
250
4000
—
100
600
—
—
—
3500
—
900
—
(Note 2)
TBUF
4700
1300
Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
TSP
—
—
—
250
50
20 + 0.1
CB
250
50
ns
ns
(Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins)
—
(Note 3)
Write cycle time
Endurance
TWR
10
—
—
10
—
ms
Byte or Page mode
10M
1M
10M
1M
25°C, VCC = 5.0V, Block
Mode (Note 4)
—
cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns)
of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike sup-
pression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on our website.
1999 Microchip Technology Inc.
DS40182C-page 95
PIC16CE62X
NOTES:
DS40182C-page 96
1999 Microchip Technology Inc.
PIC16CE62X
14.0 PACKAGING INFORMATION
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
D
W2
2
1
n
W1
E
A2
A
c
L
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
22.86
3.49
0.25
1.40
0.47
9.78
3.56
5.08
4.95
A2
A1
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
0.38
7.62
7.24
22.35
3.18
0.20
1.27
0.41
8.76
3.30
4.83
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
eB
W1
W2
Window Length
*Controlling Parameter
JEDEC Equivalent: MO-036
Drawing No. C04-010
1999 Microchip Technology Inc.
DS40182C-page 97
PIC16CE62X
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
L
A
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
eB
α
β
5
10
15
5
10
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS40182C-page 98
1999 Microchip Technology Inc.
PIC16CE62X
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
20
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.66
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
Overall Height
A
.068
.078
1.73
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
1.63
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
1999 Microchip Technology Inc.
DS40182C-page 99
PIC16CE62X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
β
0
12
15
0
12
15
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
DS40182C-page 100
1999 Microchip Technology Inc.
PIC16CE62X
14.1
Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16CE625
-04I/P423
9907CDK
AABBCDE
18-Lead SOIC (.300")
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16CE625
-04I/SO218
AABBCDE
9907CDK
18-Lead CERDIP Windowed
Example
XXXXXXXX
XXXXXXXX
AABBCDE
16CE625
/JW
9907CBA
20-Lead SSOP
Example
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16CE625
-04I/218
9907CBP
Legend: MM...M Microchip part number information
XX...X Customer specific information*
AA
BB
C
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Facility code of the plant at which wafer is manufactured
O = Outside Vendor
C = 5” Line
S = 6” Line
H = 8” Line
D
E
Mask revision number
Assembly code of the plant or country of origin in which
part was assembled
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
1999 Microchip Technology Inc.
DS40182C-page 101
PIC16CE62X
NOTES:
DS40182C-page 102
1999 Microchip Technology Inc.
PIC16CE62X
APPENDIX A: CODE FOR
ACCESSING EEPROM
DATA MEMORY
Please check our web site at www.microchip.com for
code availability.
1999 Microchip Technology Inc.
DS40182C-page 103
PIC16CE62X
NOTES:
DS40182C-page 104
1999 Microchip Technology Inc.
PIC16CE62X
BTFSC........................................................................ 68
BTFSS........................................................................ 69
CALL........................................................................... 69
CLRF .......................................................................... 69
CLRW......................................................................... 69
CLRWDT .................................................................... 70
COMF......................................................................... 70
DECF.......................................................................... 70
DECFSZ ..................................................................... 70
GOTO......................................................................... 71
INCF ........................................................................... 71
INCFSZ....................................................................... 71
IORLW........................................................................ 71
IORWF........................................................................ 72
MOVF ......................................................................... 72
MOVLW...................................................................... 72
MOVWF...................................................................... 72
NOP............................................................................ 73
OPTION...................................................................... 73
RETFIE....................................................................... 73
RETLW....................................................................... 73
RETURN..................................................................... 74
RLF............................................................................. 74
RRF ............................................................................ 74
SLEEP........................................................................ 74
SUBLW....................................................................... 75
SUBWF....................................................................... 75
SWAPF....................................................................... 76
TRIS ........................................................................... 76
XORLW ...................................................................... 76
XORWF ...................................................................... 76
Instruction Set Summary .................................................... 65
INT Interrupt ....................................................................... 60
INTCON Register................................................................ 17
Interrupts ............................................................................ 59
IORLW Instruction .............................................................. 71
IORWF Instruction .............................................................. 72
INDEX
A
ADDLW Instruction ............................................................. 67
ADDWF Instruction ............................................................. 67
ANDLW Instruction ............................................................. 67
ANDWF Instruction ............................................................. 67
Architectural Overview .......................................................... 7
Assembler
MPASM Assembler..................................................... 77
B
BCF Instruction ................................................................... 68
Block Diagram
TIMER0....................................................................... 35
TMR0/WDT PRESCALER .......................................... 38
Brown-Out Detect (BOD) .................................................... 54
BSF Instruction ................................................................... 68
BTFSC Instruction............................................................... 68
BTFSS Instruction............................................................... 69
C
CALL Instruction ................................................................. 69
Clocking Scheme/Instruction Cycle .................................... 10
CLRF Instruction................................................................. 69
CLRW Instruction................................................................ 69
CLRWDT Instruction ........................................................... 70
CMCON Register................................................................ 41
Code Protection .................................................................. 64
COMF Instruction................................................................ 70
Comparator Configuration................................................... 42
Comparator Interrupts......................................................... 45
Comparator Module ............................................................ 41
Comparator Operation ........................................................ 43
Comparator Reference ....................................................... 43
Configuration Bits................................................................ 50
Configuring the Voltage Reference..................................... 47
Crystal Operation ................................................................ 51
D
K
Data Memory Organization ................................................. 12
DECF Instruction................................................................. 70
DECFSZ Instruction ............................................................ 70
Development Support ......................................................... 77
KeeLoq Evaluation and Programming Tools ................... 80
M
MOVF Instruction................................................................ 72
MOVLW Instruction............................................................. 72
MOVWF Instruction ............................................................ 72
MPLAB Integrated Development Environment Software.... 77
E
EEPROM Peripheral Operation .......................................... 29
Errata .................................................................................... 2
External Crystal Oscillator Circuit ....................................... 52
N
NOP Instruction .................................................................. 73
G
O
General purpose Register File ............................................ 12
One-Time-Programmable (OTP) Devices ............................ 5
OPTION Instruction ............................................................ 73
OPTION Register................................................................ 16
Oscillator Configurations..................................................... 51
Oscillator Start-up Timer (OST).......................................... 54
GOTO Instruction................................................................ 71
I
I/O Ports.............................................................................. 23
I/O Programming Considerations........................................ 28
ID Locations........................................................................ 64
INCF Instruction .................................................................. 71
INCFSZ Instruction ............................................................. 71
In-Circuit Serial Programming............................................. 64
Indirect Addressing, INDF and FSR Registers ................... 21
Instruction Flow/Pipelining .................................................. 10
Instruction Set
P
Package Marking Information........................................... 101
Packaging Information........................................................ 97
PCL and PCLATH............................................................... 20
PCON Register................................................................... 19
PICDEM-1 Low-Cost PICmicro Demo Board ..................... 79
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 79
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 79
PICSTART Plus Entry Level Development System......... 79
PIE1 Register ..................................................................... 18
Pinout Description................................................................. 9
PIR1 Register ..................................................................... 18
ADDLW....................................................................... 67
ADDWF....................................................................... 67
ANDLW....................................................................... 67
ANDWF....................................................................... 67
BCF............................................................................. 68
BSF............................................................................. 68
1999 Microchip Technology Inc.
DS40182C-page 105
PIC16CE62X
Port RB Interrupt .................................................................60
PORTA................................................................................23
PORTB................................................................................26
Power Control/Status Register (PCON)..............................55
Power-Down Mode (SLEEP)...............................................63
Power-On Reset (POR) ......................................................54
Power-up Timer (PWRT).....................................................54
Prescaler.............................................................................38
PRO MATE II Universal Programmer...............................79
Program Memory Organization...........................................11
Q
Quick-Turnaround-Production (QTP) Devices ......................5
R
RC Oscillator.......................................................................52
Reset...................................................................................53
RETFIE Instruction..............................................................73
RETLW Instruction..............................................................73
RETURN Instruction............................................................74
RLF Instruction....................................................................74
RRF Instruction ...................................................................74
S
SEEVAL Evaluation and Programming System...............80
Serialized Quick-Turnaround-Production (SQTP) Devices...5
SLEEP Instruction...............................................................74
Software Simulator (MPLAB-SIM).......................................78
Special Features of the CPU...............................................49
Special Function Registers .................................................14
Stack ...................................................................................20
Status Register....................................................................15
SUBLW Instruction..............................................................75
SUBWF Instruction..............................................................75
SWAPF Instruction..............................................................76
T
Timer0
TIMER0.......................................................................35
TIMER0 (TMR0) Interrupt ...........................................35
TIMER0 (TMR0) Module.............................................35
TMR0 with External Clock...........................................37
Timer1
Switching Prescaler Assignment.................................39
Timing Diagrams and Specifications...................................91
TMR0 Interrupt....................................................................60
TRIS Instruction ..................................................................76
TRISA..................................................................................23
TRISB..................................................................................26
V
Voltage Reference Module..................................................47
VRCON Register.................................................................47
W
Watchdog Timer (WDT) ......................................................61
WWW, On-Line Support........................................................2
X
XORLW Instruction .............................................................76
XORWF Instruction .............................................................76
DS40182C-page 106
1999 Microchip Technology Inc.
PIC16CE62X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
981103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are
registered trademarks of Microchip Technology Incorpo-
rated in the U.S.A. and other countries. FlexROM and
fuzzyLAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
1999 Microchip Technology Inc.
DS40182C-page 107
PIC16CE62X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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Reader Response
Total Pages Sent
RE:
From:
Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS40182C
Device:
PIC16CE62X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS40182C-page 108
1998 Microchip Technology Inc.
PIC16CE62X
PIC16CE62X PRODUCT IDENTIFICATION SYSTEM
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO. -XX X /XX XXX
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
Package:
P
=
=
=
=
PDIP
SO
SS
JW*
SOIC (Gull Wing, 300 mil body)
SSOP (209 mil)
Examples:
Windowed CERDIP
a) PIC16CE623-04/P301 =
Commercial temp., PDIP pack-
age, 4 MHz, normal VDD limits,
QTP pattern #301.
b) PIC16CE623-04I/SO =
Industrial temp., SOIC pack-
age, 4MHz, industrial VDD lim-
its.
Temperature
Range:
-
=
=
=
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
I
E
Frequency
Range:
04
04
20
=
=
=
200kHz (LP osc)
4 MHz (XT and RC osc)
20 MHz (HS osc)
Device:
PIC16CE62X :VDD range 3.0V to 5.5V
PIC16CE62XT:VDD range 3.0V to 5.5V (Tape and Reel)
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
1999 Microchip Technology Inc.
DS40182C-page 109
PIC16CE62X
NOTES:
DS40182C-page 110
1999 Microchip Technology Inc.
PIC16CE62X
NOTES:
1999 Microchip Technology Inc.
DS40182C-page 111
®
Note the following details of the code protection feature on PICmicro MCUs.
•
•
The PICmicro family meets the specifications contained in the Microchip Data Sheet.
Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.
The person doing so may be engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable”.
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of
our product.
If you have any further questions about this matter, please contact the local sales office nearest to you.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, FilterLab,
KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,
PICSTART, PRO MATE, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip Tech-
nology Incorporated in the U.S.A. and other countries.
dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode
and Total Endurance are trademarks of Microchip Technology
Incorporated in the U.S.A.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
2002 Microchip Technology Inc.
M
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India
Microchip Technology Inc.
India Liaison Office
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
01/18/02
2002 Microchip Technology Inc.
相关型号:
PIC16CE625-I/JW
8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, CERDIP-18
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PIC16CE625/JW
8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, MS-036, CERDIP-18
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