PIC16CR54-HSISP_技术文档

PIC16C5X

EPROM/ROM-Based 8-Bit CMOS Microcontroller Series

Pin Diagrams

Devices Included in this Data Sheet

• PIC16C54

• PIC16CR54★

• PIC16C55

• PIC16C56

• PIC16C57

PDIP, SOIC, Windowed CERDIP

•1

2

3

4

5

6

7

8

9

18

RA1

RA2

RA3

17

16

15

14

13

12

11

10

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

T0CKI

MCLR/VPP

VSS

High-Performance RISC CPU Features

RB7

RB0

• Only 33 single word instructions to learn

RB6

RB1

RB2

RB5

• All instructions are single cycle (200 ns) except

for program branches which are two-cycle

RB3

RB4

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

PDIP, SOIC, Windowed CERDIP

EPROM/

ROM

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

28

•1

2

T0CKI

VDD

N/C

Device

Pins

I/O

RAM

27

26

25

24

23

22

21

20

19

18

17

16

15

3

PIC16C54

PIC16CR54★

PIC16C55

PIC16C56

PIC16C57

18

28

18

28

12

20

12

20

512

1K

25

24

25

72

4

VSS

RC6

5

N/C

RC5

6

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

RC4

7

RC3

8

2K

RC2

9

• 12-bit wide instructions

• 8-bit wide data path

RC1

10

11

12

13

14

RC0

RB7

• Seven or eight special function hardware

registers

RB6

RB5

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for

data and instructions

CMOS Technology

Peripheral Features

• Low-power, high-speed CMOS EPROM/ROM

technology

• 8-bit real time clock/counter (Timer0) with 8-bit

programmable prescaler

• Fully static design

• Power-On Reset (POR)

• Wide-operating voltage range:

- EPROM Commercial/Industrial 2.5V to 6.25V

- ROM Commercial/Industrial 2.0V to 6.25V

- EPROM/ROM Automotive 2.5V to 6.0V

• Low-power consumption

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

- < 2 mA typical @ 5.0V, 4 MHz

- 15 µA typical @ 3.0V, 32 kHz

• Selectable oscillator options:

- RC: Low-cost RC oscillator

- < 3 µA typical standby current (with WDT

disabled) @ 3.0V, 0°C to 70°C

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

- LP: Power saving, low frequency crystal

★

The PIC16CR54 is not recommended for new designs. The PIC16CR54A is recommended, as found in the

Enhanced PIC16C5X data sheet.

1995 Microchip Technology Inc.

DS30015M-page 1

This document was created with FrameMaker 4 0 4

PIC16C5X

Pin Diagrams (con’t)

SSOP

VSS

•1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MCLR/VPP

OSC1/CLKIN

OSC2/CLKOUT

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RA2

RA3

T0CKI

MCLR/VPP

VSS

•1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

RA1

RA0

OSC1/CLKIN

OSC2/CLKOUT

VDD

RB7

RB6

RB5

RB4

T0CKI

VDD

RA0

RA1

RA2

RA3

RB0

RB1

RB2

RB3

RB4

VSS

RB0

RB1

RB2

RB3

10

RC0

RB7

RB6

RB5

Table of Contents

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

General Description.............................................................................................................................................3

PIC16C5X Device Varieties.................................................................................................................................5

Architectural Overview.........................................................................................................................................7

Memory Organization ........................................................................................................................................13

I/O Ports.............................................................................................................................................................21

Timer0 Module and TMR0 Register...................................................................................................................23

Special Features of the CPU .............................................................................................................................27

Instruction Set Summary ...................................................................................................................................39

Development Support........................................................................................................................................51

10.0 Electrical Characteristics - PIC16C54/55/56/57.................................................................................................57

11.0 DC and AC Characteristics - PIC16C54/55/56/57.............................................................................................71

12.0 Electrical Characteristics - PIC16CR54.............................................................................................................79

13.0 DC and AC Characteristics - PIC16CR54 .........................................................................................................91

14.0 Packaging Information.....................................................................................................................................101

Appendix A: Compatibility................................................................................................................................115

Appendix B: What’s New .................................................................................................................................115

Appendix C: What’s Changed..........................................................................................................................116

Appendix D: PIC16/17 Microcontrollers...........................................................................................................117

Index................................................................................................................................................................125

List of Examples ..............................................................................................................................................126

List of Figures ..................................................................................................................................................126

List of Tables ...................................................................................................................................................127

Connecting to Microchip BBS..........................................................................................................................129

Access to the Internet......................................................................................................................................129

Reader Response............................................................................................................................................130

PIC16C54/55/56/57 Product Identification System..........................................................................................131

PIC16CR54 Product Identification System......................................................................................................131

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional

amount of time to ensure that these documents are correct. However, we realize that we may have missed a few

things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the

back of this data sheet to inform us. We appreciate your assistance in making this a better document.

To assist you in the use of this document, Appendix B contains a list of new information in this data sheet, while

Appendix C contains information that has changed

DS30015M-page 2

1995 Microchip Technology Inc.

PIC16C5X

1.1

Applications

1.0

GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family

of low-cost, high performance, 8-bit, fully static,

EPROM/ROM-based CMOS microcontrollers. This

family is pin and software compatible with the

Enhanced PIC16C5X family of devices. It employs a

RISC architecture with only 33 single word/single

cycle instructions. All instructions are single cycle

(200 ns) except for program branches which take two

cycles. The PIC16C5X delivers performance an order

of magnitude higher than its competitors in the same

price category. The 12-bit wide instructions are highly

symmetrical resulting in 2:1 code compression over

other 8-bit microcontrollers in its class. The easy to

use and easy to remember instruction set reduces

development time signiﬁcantly.

The PIC16C5X series ﬁts perfectly in applications

ranging from high-speed automotive and appliance

motor

control

to

low-power

remote

transmitters/receivers, pointing devices and telecom

processors. The EPROM technology makes

customizing application programs (transmitter codes,

motor speeds, receiver frequencies, etc.) extremely

fast and convenient. The small footprint packages, for

through- hole or surface mounting, make this

microcontroller series perfect for applications with

space limitations. Low-cost, low-power, high

performance, ease of use and I/O ﬂexibility make the

PIC16C5X series very versatile even in areas where

no microcontroller use has been considered before

(e.g., timer functions, replacement of “glue” logic in

larger systems, coprocessor applications).

The PIC16C5X products are equipped with special

features that reduce system cost and power

requirements. The Power-On Reset (POR) and Device

Reset Timer (DRT) eliminate the need for external

reset circuitry. There are four oscillator conﬁgurations

to choose from, including the power-saving LP (Low

Power) oscillator and cost-saving RC oscillator. Power

saving SLEEP mode, Watchdog Timer and code

protection features improve system cost, power

and reliability.

The UV erasable CERDIP packaged versions are

ideal for code development, while the cost effective

One Time Programmable (OTP) versions are suitable

for production in any volume. The customer can take

full advantage of Microchip’s price leadership in OTP

microcontrollers

OTP’s ﬂexibility.

while

beneﬁting

from

the

The PIC16C5X products are supported by

a

full-featured macro assembler, a software simulator,

an in-circuit emulator, a ‘C’ compiler, fuzzy logic

support tools, a low-cost development programmer,

and a full featured programmer. All the tools are

supported on IBM PC-AT and compatible machines.

1995 Microchip Technology Inc.

DS30015M-page 3

This document was created with FrameMaker 4 0 4

PIC16C5X

TABLE 1-1:

PIC16C5X FAMILY OF DEVICES

Clock

Memory

Peripherals

Features

PIC16C54

20 512

—

25

TMR0

12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C54A

(2)

20

—

512 25

PIC16CR54

PIC16CR54A

20

—

512 25

TMR0

12 2.0-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

(1)

PIC16CR54B

PIC16C55

20 512

—

24

25

TMR0

20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

PIC16C56

20

1K

—

(1)

1K

PIC16CR56

PIC16C57

20

2K

—

2K

72

TMR0

20 2.5-6.25 33 28-pin DIP, SOIC, SSOP

PIC16CR57A

(1)

PIC16CR57B

PIC16C58A

PIC16CR58A

20

2K

—

2K

73

TMR0

12 2.5-6.25 33 18-pin DIP, SOIC; 20-pin SSOP

(1)

PIC16CR58B

Legend: Grayed boxes: Devices NOT covered in this data sheet

All PIC16/17 Family devices have Power-On Reset, selectable Watchdog Timer, selectable code protect and

high I/O current capability.

Note 1: Please contact your local sales ofﬁce for availability of these devices.

2: Not recommended for new designs.

DS30015M-page 4

1995 Microchip Technology Inc.

PIC16C5X

2.3

Quick-Turnaround-Production (QTP)

Devices

2.0

PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options

are available. Depending on application and

production requirements, the proper device option can

be selected using the information in this section. When

placing orders, please use the PIC16C5X Product

Identiﬁcation System at the back of this data sheet to

specify the correct part number.

Microchip offers a QTP Programming Service for

factory production orders. This service is made

available for users who choose not to program a

medium to high quantity of units and whose code

patterns have stabilized. The devices are identical to

the OTP devices but with all EPROM locations and

conﬁguration bit options already programmed by the

factory. Certain code and prototype veriﬁcation

procedures apply before production shipments are

available. Please contact your Microchip Technology

sales ofﬁce for more details.

For the PIC16C5X family of devices, there are two

device types, as indicated in the device number:

1. C, as in PIC16C54. These devices have

EPROM program memory and operate over the

standard voltage range.

2. CR, as in PIC16CR54. These devices have

ROM program memory and operate over the

standard voltage range.

2.4

Serialized

Quick-Turnaround-Production

(SQTP) Devices

2.1

UV Erasable Devices

Microchip offers the unique programming service

where a few user-deﬁned locations in each device are

programmed with different serial numbers. The serial

numbers may be random, pseudo-random or

sequential.

The UV erasable versions, offered in CERDIP

packages, are optimal for prototype development and

pilot programs.

UV erasable devices can be programmed for any of

the four oscillator conﬁgurations. Microchip's

PICSTART and PRO MATE programmers both

support programming of the PIC16C5X. Third party

programmers also are available; refer to the Third

Party Guide for a list of sources.

Serial programming allows each device to have a

unique number which can serve as an entry code,

password or ID number.

2.5

Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of

the highest volume parts, giving the customer a low

cost option for high volume, mature products.

2.2

One-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for

customers expecting frequent code changes and

updates.

The OTP devices, packaged in plastic packages,

permit the user to program them once. In addition to

the program memory, the conﬁguration bits must be

programmed.

1995 Microchip Technology Inc.

DS30015M-page 5

This document was created with FrameMaker 4 0 4

PIC16C5X

NOTES:

DS30015M-page 6

1995 Microchip Technology Inc.

PIC16C5X

The PIC16C5X device contains an 8-bit ALU and

working register. The ALU is a general purpose

arithmetic unit. It performs arithmetic and Boolean

functions between data in the working register and any

register ﬁle.

3.0

ARCHITECTURAL OVERVIEW

The high performance of the PIC16C5X family can be

attributed to a number of architectural features

commonly found in RISC microprocessors. To begin

with, the PIC16C5X uses a Harvard architecture in

which program and data are accessed on separate

buses. This improves bandwidth over traditional von

Neumann architecture where program and data are

fetched on the same bus. Separating program and

data memory further allows instructions to be sized

differently than the 8-bit wide data word. Instruction

opcodes are 12-bits wide making it possible to have all

single word instructions. A 12-bit wide program

memory access bus fetches a 12-bit instruction in a

single cycle. A two-stage pipeline overlaps fetch and

The ALU is 8-bits wide and capable of addition,

subtraction, shift and logical operations. Unless

otherwise mentioned, arithmetic operations are two's

complement in nature. In two-operand instructions,

typically one operand is the W (working) register. The

other operand is a ﬁle register or an immediate

constant. In single operand instructions, the operand

is either the W register or a ﬁle register.

The W register is an 8-bit working register used for

ALU operations. It is not an addressable register.

execution

of

instructions.

Consequently,

all

Depending on the instruction executed, the ALU may

affect the values of the Carry (C), Digit Carry (DC),

and Zero (Z) bits in the STATUS register. The C and

DC bits operate as a borrow and digit borrow out bit,

respectively, in subtraction. See the SUBWFand ADDWF

instructions for examples.

instructions (33) execute in a single cycle (200 ns

@ 20 MHz) except for program branches.

The PIC16C54/CR54/C55 address 512 x 12 program

memory, the PIC16C56 addresses 1K x 12, and the

PIC16C57 addresses 2K x 12 of program memory. All

program memory is internal.

A simpliﬁed block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1

and Table 3-2.

The PIC16C5X can directly or indirectly address its

register ﬁles and data memory. All special function

registers including the program counter are mapped in

the data memory. The PIC16C5X has a highly

orthogonal (symmetrical) instruction set that makes it

possible to carry out any operation on any register

using any addressing mode. This symmetrical nature

and lack of ‘special optimal situations’ make

programming with the PIC16C5X simple yet efﬁcient.

In addition, the learning curve is reduced signiﬁcantly.

1995 Microchip Technology Inc.

DS30015M-page 7

This document was created with FrameMaker 4 0 4

PIC16C5X

FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM

9-11

T0CKI

OSC1 OSC2 MCLR

CONFIGURATION WORD

9-11

EPROM/ROM

512 X 12 TO

2048 X 12

STACK 1

STACK2

“DISABLE” “OSC

PC

SELECT”

WATCHDOG

TIMER

12

2

“CODE

OSCILLATOR/

TIMING &

CONTROL

PROTECT”

INSTRUCTION

REGISTER

WDT TIME

OUT

CLKOUT

WDT/TMR0

PRESCALER

9

12

8

“SLEEP”

INSTRUCTION

DECODER

6

“OPTION”

OPTION REG.

FROM W

DIRECT ADDRESS

DIRECT RAM

ADDRESS

GENERAL

PURPOSE

REGISTER

FILE

5

5-7

(SRAM)

8

24, 25 or 72

Bytes

STATUS

TMR0

FSR

8

DATA BUS

W

ALU

FROM W

8

FROM W

4

FROM W

8

4

8

“TRIS 5”

“TRIS 6”

“TRIS 7”

TRISB PORTB

TRISA PORTA

TRISC

PORTC

8

4

8

RC7:RC0

(28 Pin

Devices

Only)

RA3:RA0

RB7:RB0

DS30015M-page 8

1995 Microchip Technology Inc.

PIC16C5X

TABLE 3-1:

Name

PIC16C54/CR54/C56 PINOUT DESCRIPTION

DIP, SOIC SSOP I/O/P

Input

No.

Type Levels

Description

RA0

RA1

RA2

RA3

17

18

1

19

20

1

I/O

TTL Bi-directional I/O port

TTL

2

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

6

7

8

7

8

9

10

11

12

13

14

I/O

TTL Bi-directional I/O port

TTL

9

10

11

12

13

T0CKI

3

I

ST

Clock input to Timer0. Must be tied to VSS or VDD, if not in

use, to reduce current consumption.

MCLR/VPP

4

I

ST

Master clear (reset) input/programming voltage input. This

pin is an active low reset to the device. Voltage on

MCLR/VPP must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN

16

15

18

17

I

ST

—

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

VDD

VSS

14

5

15,16

5,6

P

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used,

TTL = TTL input, ST = Schmitt Trigger input

1995 Microchip Technology Inc.

DS30015M-page 9

PIC16C5X

TABLE 3-2:

PIC16C55/C57 PINOUT DESCRIPTION

DIP, SOIC SSOP I/O/P Input

Name

No.

Type Levels

Description

RA0

RA1

RA2

RA3

6

7

8

9

5

6

7

8

I/O

TTL Bi-directional I/O port

TTL

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

10

11

12

13

14

15

16

17

9

I/O

TTL Bi-directional I/O port

10

11

12

13

15

16

17

TTL

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

18

19

20

21

22

23

24

25

18

19

20

21

22

23

24

25

I/O

TTL Bi-directional I/O port

TTL

T0CKI

1

2

I

ST

Clock input to Timer0. Must be tied to VSS or VDD,

if not in use, to reduce current consumption.

MCLR/VPP

28

I

ST

Master clear (reset) input/programming voltage input. This

pin is an active low reset to the device. Voltage on

MCLR/VPP must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN

27

26

27

26

I

ST

—

Oscillator crystal input/external clock source input.

OSC2/CLKOUT

O

Oscillator crystal output. Connects to crystal or resonator

in crystal oscillator mode. In RC mode, OSC2 pin outputs

CLKOUT which has 1/4 the frequency of OSC1, and

denotes the instruction cycle rate.

VDD

VSS

N/C

2

4

3,4

1,14

—

P

—

Positive supply for logic and I/O pins.

Ground reference for logic and I/O pins.

Unused, do not connect

3,5

—

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used, TTL = TTL input,

ST = Schmitt Trigger input

DS30015M-page 10

1995 Microchip Technology Inc.

PIC16C5X

3.1

Clocking Scheme/Instruction Cycle

3.2

Instruction Flow/Pipelining

The clock input (OSC1/CLKIN pin) is internally divided

by four to generate four non-overlapping quadrature

clocks namely Q1, Q2, Q3 and Q4. Internally, the

program counter (PC) is incremented every Q1, and

the instruction is fetched from program memory and

latched into the instruction register in Q4. It is

decoded and executed during the following Q1

through Q4. The clocks and instruction execution ﬂow

is shown in Figure 3-2 and Example 3-1.

An Instruction Cycle consists of four Q cycles (Q1, Q2,

Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO)

then two cycles are required to complete the

instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the Instruction Register (IR) in cycle Q1.

This instruction is then decoded and executed during

the Q2, Q3, and Q4 cycles. Data memory is read

during Q2 (operand read) and written during Q4

(destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

Q2

Q3

Q4

Q2

Q3

Q4

Q2

Q3

Q4

Q1

OSC1

Q1

Q2

Q3

Q4

Internal

phase

clock

PC

PC+1

PC+2

PC

OSC2/CLKOUT

(RC mode)

Fetch INST (PC)

Execute INST (PC-1)

Fetch INST (PC+1)

Execute INST (PC)

Fetch INST (PC+2)

Execute INST (PC+1)

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h

Fetch 1

Execute 1

Fetch 2

2. MOVWF PORTB

3. CALL SUB_1

Execute 2

Fetch 3

Execute 3

Fetch 4

4. BSF

PORTA, BIT3

Flush

Fetch SUB_1 Execute SUB_1

All instructions are single cycle, except for any program branches. These take two cycles since the fetch

instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1995 Microchip Technology Inc.

DS30015M-page 11

PIC16C5X

NOTES:

DS30015M-page 12

1995 Microchip Technology Inc.

PIC16C5X

FIGURE 4-3: PIC16C57 PROGRAM

4.0

MEMORY ORGANIZATION

MEMORY MAP

AND STACK

4.1

Program Memory Organization

The PIC16C54, PIC16CR54 and PIC16C55 have a

9-bit Program Counter (PC) capable of addressing a

512 x 12 program memory space (Figure 4-1). The

PIC16C56 has a 10-bit program counter capable of

addressing a 1K x 12 program memory space

(Figure 4-2). The PIC16C57 has an 11-bit program

counter capable of addressing a 2K x 12 program

memory space (Figure 4-3). Accessing a location

above the physically implemented address will cause

a wraparound.

PC<10:0>

11

CALL, RETLW

Stack Level 1

Stack Level 2

000h

On-chip Program

Memory (Page 0)

0FFh

100h

1FFh

200h

The reset vector for the PIC16C54/CR54/C55 is at

1FFh, at 3FFh for the PIC16C56, and at 7FFh for

the PIC16C57.

On-chip Program

Memory (Page 1)

2FFh

300h

3FFh

400h

FIGURE 4-1: PIC16C54/CR54/C55

PROGRAM MEMORY MAP

AND STACK

On-chip Program

Memory (Page 2)

4FFh

500h

PC<8:0>

5FFh

600h

9

CALL, RETLW

On-chip Program

Memory (Page 3)

6FFh

700h

Stack Level 1

Stack Level 2

Reset Vector

7FFh

000h

On-chip

Program

Memory

4.2

Data Memory Organization

0FFh

100h

Data memory is composed of registers, or bytes of

RAM. Therefore, data memory for a device is speciﬁed

by its register ﬁle. The register ﬁle is divided into two

functional groups: special function registers and

general purpose registers.

Reset Vector

1FFh

FIGURE 4-2: PIC16C56 PROGRAM

MEMORY MAP

The special function registers include the TMR0

register, the Program Counter (PC), the Status

Register, the I/O registers (ports), and the File Select

Register (FSR). In addition, special purpose registers

are used to control the I/O port conﬁguration and

prescaler options.

AND STACK

PC<9:0>

10

CALL, RETLW

The general purpose registers are used for data and

control information under command of the instructions.

Stack Level 1

Stack Level 2

For the PIC16C54, PIC16CR54 and PIC16C56, the

register ﬁle is composed of seven special function

registers and 25 general purpose registers

(Figure 4-4). For the PIC16C55, the register ﬁle is

composed of eight special function registers and 24

general purpose registers (Figure 4-5). For the

PIC16C57, up to 48 additional general purpose

000h

On-chip Program

Memory (Page 0)

0FFh

100h

1FFh

200h

On-chip Program

Memory (Page 1)

2FFh

300h

registers may be addressed using

scheme (Figure 4-6).

a

banking

Reset Vector

3FFh

4.2.1

GENERAL PURPOSE REGISTER FILE

The register ﬁle is accessed either directly or indirectly

through the ﬁle select register FSR (Section 4.7).

1995 Microchip Technology Inc.

DS30015M-page 13

This document was created with FrameMaker 4 0 4

PIC16C5X

FIGURE 4-4: PIC16C54/CR54/C56

REGISTER FILE MAP

FIGURE 4-5: PIC16C55 REGISTER FILE

MAP

File Address

INDF⁽¹⁾

00h

INDF⁽¹⁾

00h

TMR0

PCL

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

01h

02h

03h

04h

05h

06h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTA

PORTB

07h

08h

PORTC

General

Purpose

Registers

General

Purpose

Registers

0Fh

10h

0Fh

10h

1Fh

Note 1: Not a physical register. See Section 4.7

FIGURE 4-6: PIC16C57 REGISTER FILE MAP

FSR<6:5>

File Address

00h

00

01

10

11

INDF⁽¹⁾

TMR0

PCL

20h

40h

60h

01h

02h

03h

04h

05h

STATUS

FSR

Addresses map back to

addresses in Bank 0.

PORTA

PORTB

06h

07h

08h

PORTC

General

Purpose

Register

0Fh

2Fh

30h

4Fh

50h

6Fh

10h

1Fh

70h

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

General

Purpose

Registers

3Fh

5Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Note 1: Not a physical register. See Section 4.7

DS30015M-page 14

1995 Microchip Technology Inc.

PIC16C5X

4.2.2

SPECIAL FUNCTION REGISTERS

The special registers can be classiﬁed into two sets.

The special function registers associated with the

“core” functions are described in this section. Those

related to the operation of the peripheral features are

described in the section for each peripheral feature.

The Special Function Registers are registers used by

the CPU and peripheral functions to control the

operation of the device (Table 4-1).

TABLE 4-1:

SPECIAL FUNCTION REGISTER SUMMARY

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

00h

01h

TRIS

I/O control registers (TRISA, TRISB, TRISC)

1111 1111 1111 1111

--11 1111 --11 1111

xxxx xxxx uuuu uuuu

OPTION

INDF

Contains control bits to conﬁgure Timer0 and Timer0/WDT prescaler

Uses contents of FSR to address data memory (not a physical register)

8-bit real-time clock/counter

TMR0

(1)

02h

03h

04h

05h

06h

PCL

Low order 8 bits of PC

1111 1111 1111 1111

0001 1xxx 000q quuu

1xxx xxxx 1uuu uuuu

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

STATUS

FSR

PA2

PA1

PA0

TO

PD

Z

DC

C

Indirect data memory address pointer

PORTA

PORTB

—

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB0

RB7

RB6

RB5

RB4

(2)

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)

x= unknown, u= unchanged, q= see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5

for an explanation of how to access these bits.

2: File address 07h is a general purpose register on the PIC16C54/CR54/C56.

1995 Microchip Technology Inc.

DS30015M-page 15

PIC16C5X

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

4.3

STATUS Register

This register contains the arithmetic status of the ALU,

the RESET status, and the page preselect bits for

program memories larger than 512 words.

It is recommended, therefore, that only BCF, BSF and

MOVWF instructions be used to alter the STATUS

register because these instructions do not affect the Z,

DC or C bits from the STATUS register. For other

instructions which do affect STATUS bits, see

Table 8-2, Instruction Set Summary.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to

the device logic. Furthermore, the TO and PD bits are

not writable. Therefore, the result of an instruction

with the STATUS register as destination may be

different than intended.

FIGURE 4-7: STATUS REGISTER (ADDRESS:03h)

R/W-0

PA2

R/W-0

PA1

R/W-0

PA0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7

6

5

4

3

2

1

bit0

bit 7:

PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward

compatibility with future products.

bit 6-5: PA1:PA0: Program page preselect bits (PIC16C56 and PIC16C57 only)

00 = Page 0 (000h - 1FFh) - PIC16C56 and PIC16C57

01 = Page 1 (200h - 3FFh) - PIC16C56 and PIC16C57

10 = Page 2 (400h - 5FFh) - PIC16C57

11 = Page 3 (600h - 7FFh) - PIC16C57

Each page is 512 bytes.

Using the PA1:PA0 bits as general purpose read/write bits in devices which do not use them for program

page preselect is not recommended since this may affect upward compatibility with future products.

bit 4:

bit 3:

bit 2:

bit 1:

TO: Time-out bit

1 = After power-up, CLRWDTinstruction, or SLEEPinstruction

0 = A WDT time-out occurred

PD: Power-down bit

1 = After power-up or by the CLRWDTinstruction

0 = By execution of the SLEEPinstruction

Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred

bit 0:

C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)

ADDWF

SUBWF

RRF or RLF

1 = A carry occurred

0 = A carry did not occur

1 = A borrow did not occur

0 = A borrow occurred

Load bit with LSb or MSb

DS30015M-page 16

1995 Microchip Technology Inc.

PIC16C5X

4.4

OPTION Register

The OPTION register is a 6-bit wide, write-only

register which contains various control bits to

conﬁgure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of

the W register will be transferred to the OPTION

register. A RESET sets the OPTION<5:0> bits.

FIGURE 4-8: OPTION REGISTER

U-0

—

U-0

—

6

W-1

T0CS

5

W-1

T0SE

4

W-1

PSA

3

W-1

PS2

2

W-1

PS1

1

W-1

PS0

W = Writable bit

= Unimplemented bit

- n = Value at POR reset

U

bit7

bit0

bit 7-6: Unimplemented.

bit 5:

bit 4:

bit 3:

T0CS: Timer0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKOUT)

T0SE: Timer0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

PSA: Prescaler Assignment bit

1 = Prescaler assigned to the WDT

0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler Rate Select bits

Bit Value

Timer0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1995 Microchip Technology Inc.

DS30015M-page 17

PIC16C5X

4.5

Program Counter

FIGURE 4-10: LOADING OF PC BRANCH

INSTRUCTIONS - PIC16C56

As a program instruction is executed, the Program

Counter (PC) will contain the address of the next

program instruction to be executed. The PC value is

increased by one every instruction cycle, unless an

instruction changes the PC.

GOTO Instruction

9

8

7

0

PC

PCL

For a GOTOinstruction, bits 8:0 of the PC are provided

by the GOTO instruction word. The PC Latch (PCL) is

mapped to PC<7:0> (Figure 4-9, Figure 4-10 and

Figure 4-11).

Instruction Word

0

PA0

7

For the PIC16C56 and PIC16C57, a page number

must be supplied as well. Bit5 of the STATUS register

provides this to bit9 of the PC for the PIC16C56

(Figure 4-10). Bit5 and bit6 of the STATUS register

provide page information to bit9 and bit10 of the PC

for the PIC16C57 (Figure 4-11).

STATUS

CALL or Modify PCL Instruction

9

8

7

0

PC

PCL

For a CALL instruction, or any instruction where the

PCL is the destination, bits 7:0 of the PC are provided

by the instruction word. However, PC<8> does not

come from the instruction word, but is always cleared

(Figure 4-9, Figure 4-10 and Figure 4-11).

Instruction Word

Reset to '0'

PA0

Instructions where the PCL is the destination, or

Modify PCL instructions, include MOVWF PC, ADDWF

PC,and BSF PC,5.

7

0

STATUS

For the PIC16C56 and PIC16C57, a page number

again must be supplied. Bit5 of the STATUS register

provides this to bit9 of the PC for the PIC16C56

(Figure 4-10). Bit5 and bit6 of the STATUS register

provide page information to bit9 and bit10 of the PC

for the PIC16C57 (Figure 4-11).

FIGURE 4-11: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C57

GOTO Instruction

10

9

8

7

0

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction,

all subroutine calls or computed jumps are

limited to the ﬁrst 256 locations of any

program memory page (512 words long).

PC

PCL

Instruction Word

2

PA1:PA0

FIGURE 4-9: LOADING OF PC

BRANCH INSTRUCTIONS -

PIC16C54/CR54/C55

7

0

STATUS

GOTO Instruction

CALL or Modify PCL Instruction

8

7

0

PCL

PC

10

9

8

7

0

PC

PCL

Instruction Word

CALL or Modify PCL Instruction

Reset to ‘0’

PA1:PA0

8

7

0

2

7

0

PCL

PC

STATUS

Reset to '0'

Instruction Word

DS30015M-page 18

1995 Microchip Technology Inc.

PIC16C5X

For the RETLW instruction, the PC is loaded with the

Top Of Stack (TOS) contents. All of the devices

covered in this data sheet have only two stacks. Each

stack has the same bit width as the device PC.

4.6

Stack

PIC16C5X devices have a 9-bit, 10-bit or 11-bit wide,

two-level hardware push/pop stack (Figure 4-1,

Figure 4-2 and Figure 4-3 respectively).

4.5.1

PAGING CONSIDERATIONS –

PIC16C56/57

A CALLinstruction will push the current value of stack 1

into stack 2 and then push the current program counter

value, incremented by one, into stack level 1. If more

than two sequential CALL’s are executed, only the most

recent two return addresses are stored.

If the Program Counter is pointing to the last address

of a selected memory page, when it increments it will

cause the program to continue in the next higher page.

However, the page preselect bits in the STATUS

register will not be updated. Therefore, the next GOTO,

CALL, or Modify PCL instruction will return the program

to the page speciﬁed by the page preselect bits (PA0

or PA1:PA0).

A RETLW instruction will pop the contents of stack

level 1 into the program counter and then copy stack

level 2 contents into level 1. If more than two sequential

RETLW’s are executed, the stack will be filled with the

address previously stored in level 2.

For example, a NOP at location 1FFh (page 0)

increments the PC to 200h (page 1). A GOTO xxx at

200h will return the program to address xxxh on

page 0 (assuming that PA1:PA0 are clear).

Note: The W register will be loaded with the

literal value speciﬁed in the instruction.

This is particularly useful for the

implementation of data look-up tables

within the program memory.

To prevent this, the page preselect bits must be

updated under program control.

4.5.2

EFFECTS OF RESET

The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the

last page (i.e., the reset vector).

The STATUS register page preselect bits are cleared

upon

a RESET, which means that page 0 is

pre-selected.

Therefore, upon a RESET, a GOTO instruction at the

reset vector location will automatically cause the

program to jump to page 0.

If an inadequate RESET occurs (i.e., POR conditions

are not met, a brown-out occurs, etc.), page preselect

bits in the STATUS register will not be cleared.

Therefore, it is good programming practice to include

the following code before the GOTO instruction at the

reset vector location:

BSF STATUS

BSF FSR

1995 Microchip Technology Inc.

DS30015M-page 19

PIC16C5X

4.7

Indirect Data Addressing; INDF and

FSR Registers

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw 0x10 ;initialize pointer

The INDF register is not

a physical register.

Addressing INDF actually addresses the register

whose address is contained in the FSR register (FSR

is a pointer). This is indirect addressing.

movwf FSR

;

to RAM

incf

INDF ;clear INDF register

FSR,F ;inc pointer

btfsc FSR,4 ;all done?

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

goto

NEXT ;NO, clear next

CONTINUE

:

;YES, continue

The FSR is either a 5-bit (PIC16C54/CR54/C55/C56)

or 7-bit (PIC16C57) wide register. It is used in

conjunction with the INDF register to indirectly address

the data memory area. The last two bits, FSR<6:5>,

are also used on the PIC16C57 for direct

addressing (Figure 4-12).

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

The FSR<4:0> bits are used to select data memory

addresses 00h to 1Fh.

PIC16C54/CR54/C55/C56: Do not use banking.

FSR<6:5> are unimplemented and read as '1's.

A simple program to clear RAM locations 10h-1Fh

using indirect addressing is shown in Example 4-2.

PIC16C57: FSR<6:5> are the bank select bits and are

used to select the bank to be addressed (00= bank 0,

01= bank 1, 10= bank 2, 11= bank 3).

FIGURE 4-12: DIRECT/INDIRECT ADDRESSING

Direct Addressing

Indirect Addressing

(FSR)

4

(opcode)

0

5

(FSR)

0

6

4

5

6

location select

bank select

location select

bank

00

01

10

11

00h

Addresses map back

to addresses in Bank 0.

Data

Memory

0Fh

10h

(1)

1Fh

Bank 0

3Fh

Bank 1

5Fh

Bank 2

7Fh

Bank 3

Note 1: For register map detail see Section 4.2.

DS30015M-page 20

1995 Microchip Technology Inc.

PIC16C5X

5.5

I/O Interfacing

5.0

I/O PORTS

As with any other register, the I/O registers can be

written and read under program control. However,

read instructions (e.g., MOVF PORTB,W) always read

the I/O pins independent of the pin’s input/output

modes. On RESET, all I/O ports are deﬁned as input

(inputs are at hi-impedance) since the I/O control

registers (TRISA, TRISB, TRISC) are all set.

The equivalent circuit for an I/O port pin is shown in

Figure 5-1. All ports may be used for both input and

output operations. For input operations these ports are

non-latching. Any input must be present until read by

an input instruction (e.g., MOVF PORTB, W). The

outputs are latched and remain unchanged until the

output latch is rewritten. To use a port pin as output,

the corresponding direction control bit (in TRISA,

TRISB, TRISC) must be cleared (= 0). For use as an

input, the corresponding TRIS bit must be set. Any I/O

pin can be programmed individually as input or output.

5.1

PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits

are used (RA3:RA0). Bits 7-4 are unimplemented and

read as '0's.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

5.2

PORTB

Data

Bus

PORTB is an 8-bit I/O register (PORTB<7:0>).

D

Q

Data

Latch

5.3

PORTC

VDD

P

WR

Port

CK

PIC16C55/C57: 8-bit I/O register.

PIC16C54/CR54/C56:

General purpose register.

N

I/O

pin⁽¹⁾

W

Reg

5.4

TRIS Registers

D

Q

TRIS

Latch

The output driver control registers are loaded with the

contents of the W register by executing the TRIS f

instruction. A '1' from a TRIS register bit puts the

corresponding output driver in a hi-impedance mode.

A '0' puts the contents of the output data latch on the

selected pins, enabling the output buffer.

VSS

TRIS ‘f’

CK

Reset

Note:

A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of the port will indicate that the pin

is low.

RD Port

Note 1: I/O pins have protection diodes to VDD and VSS.

The TRIS registers are “write-only” and are set (output

drivers disabled) upon RESET.

TABLE 5-1:

SUMMARY OF PORT REGISTERS

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

N/A

05h

06h

TRIS

PORTA

I/O control registers (TRISA, TRISB, TRISC)

1111 1111 1111 1111

---- xxxx ---- uuuu

xxxx xxxx uuuu uuuu

—

RA3

RB3

RA2

RB2

RA1

RB1

RA0

RB0

PORTB

PORTC

RB7

RB6

RB5

RB4

(1)

07h

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented, read as ‘0’,

–= unimplemented, read as '0', x= unknown, u= unchanged

Note 1: File address 07h is a general purpose register on the PIC16C54/CR54/C56.

1995 Microchip Technology Inc.

DS30015M-page 21

This document was created with FrameMaker 4 0 4

PIC16C5X

5.6

I/O Programming Considerations

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN

I/O PORT

5.6.1

BI-DIRECTIONAL I/O PORTS

;Initial PORT Settings

Some instructions operate internally as read followed

by write operations. The BCFand BSFinstructions, for

example, read the entire port into the CPU, execute

the bit operation and re-write the result. Caution must

be used when these instructions are applied to a port

where one or more pins are used as input/outputs. For

example, a BSFoperation on bit5 of PORTB will cause

all eight bits of PORTB to be read into the CPU, bit5 to

be set and the PORTB value to be written to the output

latches. If another bit of PORTB is used as a

bi-directional I/O pin (say bit0) and it is deﬁned as an

input at this time, the input signal present on the pin

itself would be read into the CPU and rewritten to the

data latch of this particular pin, overwriting the

previous content. As long as the pin stays in the input

mode, no problem occurs. However, if bit0 is switched

into output mode later on, the content of the data latch

may now be unknown.

;

PORTB<7:4> Inputs

PORTB<3:0> Outputs

;PORTB<7:6> have external pull-ups and are

;not connected to other circuitry

;

PORT latch PORT pins

---------- ----------

BCF

MOVLW 03Fh

TRIS PORTB

PORTB, 7

PORTB, 6

;01pp pppp

;10pp pppp

;

11pp pppp

;10pp pppp

10pp pppp

;

;Note that the user may have expected the pin

;values to be 00pp pppp. The 2nd BCF caused

;RB7 to be latched as the pin value (High).

5.6.2

SUCCESSIVE OPERATIONS ON I/O

PORTS

The actual write to an I/O port happens at the end of

an instruction cycle, whereas for reading, the data

must be valid at the beginning of the instruction cycle

(Figure 5-2). Therefore, care must be exercised if a

write followed by a read operation is carried out on the

same I/O port. The sequence of instructions should

allow the pin voltage to stabilize (load dependent)

before the next instruction, which causes that ﬁle to be

read into the CPU, is executed. Otherwise, the

previous state of that pin may be read into the CPU

rather than the new state. When in doubt, it is better to

separate these instructions with a NOP or another

instruction not accessing this I/O port.

Example 5-1 shows the effect of two sequential

read-modify-write instructions (e.g., BCF, BSF, etc.) on

an I/O port.

A pin actively outputting a high or a low should not be

driven from external devices at the same time in order

to change the level on this pin (“wired-or”,

“wired-and”). The resulting high output currents may

damage the chip.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

Q4

Q1 Q2

Q4

Q3

Q1 Q2

PC

Q1 Q2

PC + 3

NOP

PC + 1

PC + 2

NOP

This example shows a write to PORTB

followed by a read from PORTB.

Instruction

fetched

MOVWF PORTB MOVF PORTB,W

Data setup time = (0.25 TCY – TPD)

where: TCY = instruction cycle.

TPD = propagation delay

RB7:RB0

Port pin

written here

Port pin

sampled here

Therefore, at higher clock frequencies, a

write followed by a read may be problematic.

Instruction

executed

MOVWF PORTB MOVF PORTB,W

NOP

(Write to

PORTB)

(Read

PORTB)

DS30015M-page 22

1995 Microchip Technology Inc.

PIC16C5X

Counter mode is selected by setting the T0CS bit

(OPTION<5>). In this mode, Timer0 will increment

either on every rising or falling edge of pin T0CKI. The

incrementing edge is determined by the source edge

select bit T0SE (OPTION<4>). Clearing the T0SE bit

selects the rising edge. Restrictions on the external

clock input are discussed in detail in Section 6.1.

6.0

TIMER0 MODULE AND

TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

The prescaler may be used by either the Timer0

module or the Watchdog Timer, but not both. The

prescaler assignment is controlled in software by the

control bit PSA (OPTION<3>). Clearing the PSA bit

will assign the prescaler to Timer0. The prescaler is

not readable or writable. When the prescaler is

assigned to the Timer0 module, prescale values of

1:2, 1:4,..., 1:256 are selectable. Section 6.2 details

the operation of the prescaler.

Figure 6-1 is a simpliﬁed block diagram of the Timer0

module, while Figure 6-2 shows the electrical structure

of the Timer0 input.

Timer mode is selected by clearing the T0CS bit

(OPTION<5>). In timer mode, the Timer0 module will

increment every instruction cycle (without prescaler). If

TMR0 register is written, the increment is inhibited for

the following two cycles (Figure 6-3 and Figure 6-4).

The user can work around this by writing an adjusted

value to the TMR0 register.

A summary of registers associated with the Timer0

module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

Data bus

FOSC/4

0

1

PSout

8

1

0

Sync with

Internal

Clocks

TMR0 reg

T0CKI

Programmable

PSout

Sync

(2)

Prescaler

(1)

(2 cycle delay)

T0SE

3

(1)

PS2, PS1, PS0

PSA

(1)

T0CS

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

RIN

T0CKI

(1)

Schmitt Trigger

Input Buffer

N

(1)

VSS

Note 1: ESD protection circuits

1995 Microchip Technology Inc.

DS30015M-page 23

This document was created with FrameMaker 4 0 4

PIC16C5X

FIGURE 6-3: TIMER0 TIMING:

INTERNAL CLOCK/NO PRESCALE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

Instruction

Fetch

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

T0

T0+1

T0+2

NT0

NT0+1

NT0+2

Timer0

Instruction

Executed

Read TMR0

reads NT0 + 1

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 2

Write TMR0

executed

FIGURE 6-4: TIMER0 TIMING:

INTERNAL CLOCK/PRESCALE 1:2

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

(Program

Counter)

PC-1

PC

PC+1

PC+2

PC+3

PC+4

PC+5

PC+6

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

MOVWF TMR0

Instruction

Fetch

T0

T0+1

NT0+1

T0

NT0

Timer0

Instruction

Execute

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0

Read TMR0

reads NT0 + 1

Write TMR0

executed

TABLE 6-1:

Address

REGISTERS ASSOCIATED WITH TIMER0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Name

Bit 7

Timer0 - 8-bit real-time clock/counter

T0CS T0SE PSA

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01

TMR0

xxxx xxxx uuuu uuuu

N/A

OPTION

—

PS2

PS1

PS0 --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits,

-= unimplemented, x = unknown, u= unchanged,

DS30015M-page 24

1995 Microchip Technology Inc.

PIC16C5X

When a prescaler is used, the external clock input is

divided by the asynchronous ripple counter-type

prescaler so that the prescaler output is symmetrical.

For the external clock to meet the sampling

requirement, the ripple counter must be taken into

account. Therefore, it is necessary for T0CKI to have a

period of at least 4TOSC (and a small RC delay of

40 ns) divided by the prescaler value. The only

requirement on T0CKI high and low time is that they

do not violate the minimum pulse width requirement of

10 ns. Refer to parameters 40, 41 and 42 in the

electrical speciﬁcation of the desired device.

6.1

Using Timer0 with an External Clock

When an external clock input is used for Timer0, it

must meet certain requirements. The external clock

requirement is due to internal phase clock (TOSC)

synchronization. Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.1.1

EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization

of T0CKI with the internal phase clocks is

accomplished by sampling the prescaler output on the

Q2 and Q4 cycles of the internal phase clocks

(Figure 6-5). Therefore, it is necessary for T0CKI to be

high for at least 2TOSC (and a small RC delay of 20 ns)

and low for at least 2TOSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the

desired device.

6.1.2

TIMER0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

external clock edge occurs to the time the Timer0

module is actually incremented. Figure 6-5 shows the

delay from the external clock edge to the timer

incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Small pulse

External Clock Input or

misses sampling

Prescaler Output (2)

(1)

External Clock/Prescaler

Output After Sampling

(3)

Increment Timer0 (Q4)

Timer0

T0

T0 + 1

T0 + 2

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.

2: External clock if no prescaler selected, Prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

1995 Microchip Technology Inc.

DS30015M-page 25

PIC16C5X

following instruction sequence (Example 6-1) must be

executed when changing the prescaler assignment from

Timer0 to the WDT.

6.2

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer (WDT), respectively (Section 6.1.2). For

simplicity, this counter is being referred to as

“prescaler” throughout this data sheet. Note that the

prescaler may be used by either the Timer0 module or

the WDT, but not both. Thus, a prescaler assignment

for the Timer0 module means that there is no

prescaler for the WDT, and vice-versa.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

CLRF

CLRWDT

TMR0

;Clear TMR0

;Clears WDT and

;prescaler

MOVLW 'xxxx1xxx' ;Select new prescale

OPTION ;value

The PSA and PS2:PS0 bits (OPTION<3:0>)

determine prescaler assignment and prescale ratio.

To change prescaler from the WDT to the Timer0

module, use the sequence shown in Example 6-2. This

sequence must be used even if the WDT is disabled. A

CLRWDTinstruction should be executed before switching

the prescaler.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x, etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the WDT. The prescaler is neither

readable nor writable. On a RESET, the prescaler

contains all '0's.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

;prescaler

MOVLW 'xxxx0xxx'

;Select TMR0, new

;prescale value and

;clock source

6.2.1

SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software control

(i.e., it can be changed “on the ﬂy” during program

execution). To avoid an unintended device RESET, the

OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TCY ( = Fosc/4)

Data Bus

8

0

M

U

X

1

M

U

X

T0CKI

1

Sync

2

Cycles

TMR0 reg

0

T0SE

T0CS

PSA

0

1

8-bit Prescaler

M

U

X

8

Watchdog

Timer

8 - to - 1MUX

PS2:PS0

PSA

1

0

WDT Enable bit

MUX

PSA

WDT

Time-Out

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

DS30015M-page 26

1995 Microchip Technology Inc.

PIC16C5X

The SLEEP mode is designed to offer a very low

current power-down mode. The user can wake up

from SLEEP through external reset or through a

Watchdog Timer time-out. Several oscillator options

are also made available to allow the part to ﬁt the

application. The RC oscillator option saves system

cost while the LP crystal option saves power. A set of

conﬁguration bits are used to select various options.

7.0

SPECIAL FEATURES OF THE

CPU

What sets

a

microcontroller apart from other

processors are special circuits to deal with the needs

of real-time applications. The PIC16C5X family of

microcontrollers has a host of such features intended

to maximize system reliability, minimize cost through

elimination of external components, provide power

saving operating modes and offer code protection.

These features are:

7.1

Conﬁguration Bits

The PIC16C5X conﬁguration word consists of 12 bits,

4 of which are implemented. Conﬁguration bits can be

programmed to select various device conﬁgurations.

Two bits are for the selection of the oscillator type, one

bit is the Watchdog Timer enable bit and one bit is the

code protection bit (Figure 7-1).

• Oscillator selection

• Reset

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT)

• SLEEP

OTP, QTP or ROM devices have the oscillator

conﬁguration programmed at the factory and these

parts are tested accordingly (see "Product

Identiﬁcation System" on the inside back cover).

• Code protection

• ID locations

The PIC16C5X has a Watchdog Timer which can be

shut off only through conﬁguration bit WDTE. It runs

off of its own RC oscillator for added reliability. There

is an 18 ms delay provided by the Device Reset Timer

(DRT), intended to keep the chip in reset until the

crystal oscillator is stable. With this timer on-chip, most

applications need no external reset circuitry.

FIGURE 7-1: CONFIGURATION WORD FOR PIC16C54/CR54/C55/C56/C57

—

9

—

8

—

7

—

6

—

5

—

4

CP

3

WDTE FOSC1 FOSC0

bit0

Register: CONFIG

(1)

Address

:

FFFh

bit11

10

2

1

bit 11-4: Unimplemented: Read as ’0’.

bit 3:

CP: Code protection bit

1 = Code protection off

0 = Code protection on

bit 2:

WDTE: Watchdog timer enable bit

1 = WDT enabled

0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Speciﬁcations (literature number DS30190) to

determine how to access the conﬁguration word.

1995 Microchip Technology Inc.

DS30015M-page 27

This document was created with FrameMaker 4 0 4

PIC16C5X

7.2

Oscillator Conﬁgurations

TABLE 7-1:

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16C54/55/56/57

7.2.1

OSCILLATOR TYPES

The PIC16C5X can be operated in four different

oscillator modes. The user can program two

conﬁguration bits (FOSC1:FOSC0) to select one of

these four modes:

Osc

Type

Resonator Cap. Range Cap. Range

Freq

C1

C2

XT

455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-33 pF

10-22 pF

68-100 pF

15-33 pF

10-22 pF

• LP:

• XT:

• HS:

• RC:

Low Power Crystal

Crystal/Resonator

HS

8.0 MHz

16.0 MHz

10-22 pF

10 pF

10-22 pF

10 pF

High Speed Crystal/Resonator

Resistor/Capacitor

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

7.2.2

CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

TABLE 7-2:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16C54/55/56/57

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKIN and OSC2/CLKOUT

pins to establish oscillation (Figure 7-2). The

PIC16C5X oscillator design requires the use of a

parallel cut crystal. Use of a series cut crystal may

give a frequency out of the crystal manufacturers

speciﬁcations. When in XT, LP or HS modes, the

device can have an external clock source drive the

OSC1/CLKIN pin (Figure 7-3).

Osc

Resonator Cap.Range Cap. Range

Type

Freq

C1

C2

(1)

LP

XT

32 kHz

15 pF

100 kHz

200 kHz

455 kHz

1 MHz

15-30 pF

15 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15 pF

FIGURE 7-2: CRYSTAL OPERATION OR

CERAMIC RESONATOR (HS,

XT OR LP OSC

2 MHz

4 MHz

15 pF

CONFIGURATION)

HS

4 MHz

8 MHz

20 MHz

15 pF

(1)

C1

OSC1

PIC16C5X

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30pF is recom-

mended.

SLEEP

XTAL

(3)

RF

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to avoid

overdriving crystals with low drive level speciﬁcation.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external components.

To internal

logic

OSC2

(2)

RS

(1)

C2

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen

(approx. value = 10 MΩ).

FIGURE 7-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

OSC1

OSC2

Clock from

ext. system

PIC16C5X

Open

DS30015M-page 28

1995 Microchip Technology Inc.

PIC16C5X

7.2.3

EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

TABLE 7-3:

CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16CR54

Either a prepackaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Prepackaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used: one with parallel

resonance, or one with series resonance.

Osc

Resonator Cap. Range Cap. Range

Type

Freq

C1

C2

Data not available at this time.

TABLE 7-4:

CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16CR54

Figure 7-4 shows implementation of

a

parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

Osc

Resonator Cap.Range Cap. Range

Type

Freq

C1

C2

(1)

LP

32 kHz

15-33 pF

15-30 pF

15-33 pF

15-30 pF

100 kHz

200 kHz

This

circuit

could

be

used

for

external

oscillator designs.

XT

100 kHz

200 kHz

1 MHz

68-100 pF

15-30 pF

15-47 pF

68-100 pF

15-30 pF

15-47 pF

FIGURE 7-4: EXTERNAL PARALLEL

RESONANT CRYSTAL

2 MHz

4 MHz

OSCILLATOR CIRCUIT

+5V

HS

4 MHz

8 MHz

20 MHz

15-47 pF

To Other

Devices

PIC16C5X

10k

74AS04

4.7k

Note 1: For VDD < 2.5V, C1 = C2 ≈ 15-33pF is

recommended.

CLKIN

74AS04

These values are for design guidance only. Rs may

be required in HS mode as well as XT mode to avoid

overdriving crystals with low drive level speciﬁcation.

Since each crystal has its own characteristics, the

user should consult the crystal manufacturer for

appropriate values of external components.

10k

XTAL

10k

20 pF

Figure 7-5 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inverter performs a

180-degree phase shift in a series resonant oscillator

circuit. The 330Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 7-5: EXTERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

To Other

Devices

330

PIC16C5X

74AS04

CLKIN

0.1 µF

XTAL

1995 Microchip Technology Inc.

DS30015M-page 29

PIC16C5X

7.2.4

RC OSCILLATOR

7.3

Reset

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (Rext) and capacitor (Cext) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency,

especially for low Cext values. The user also needs to

take into account variation due to tolerance of external

R and C components used.

PIC16C5X devices may be reset in one of the

following ways:

• Power-On Reset (POR)

• MCLR reset (normal operation)

• MCLR wake-up reset (from SLEEP)

• WDT reset (normal operation)

• WDT wake-up reset (from SLEEP)

Table 7-5 shows these reset conditions for the PCL

and STATUS registers.

Some registers are not affected in any reset condition.

Their status is unknown on POR and unchanged in

any other reset. Most other registers are reset to a

“reset state” on Power-On Reset (POR), MCLR or

WDT reset. A MCLR or WDT wake-up from SLEEP

also results in a device reset, and not a continuation of

operation before SLEEP.

Figure 7-6 shows how the R/C combination is

connected to the PIC16C5X. For Rext values below

2.2 kΩ, the oscillator operation may become unstable,

or stop completely. For very high Rext values

(e.g., 1 MΩ) the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

Rext between 3 kΩ and 100 kΩ.

The TO and PD bits (STATUS <4:3>) are set or

cleared depending on the different reset conditions

(Section 7.7). These bits may be used to determine

the nature of the reset.

Although the oscillator will operate with no external

capacitor (Cext = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package lead frame capacitance.

Table 7-6 lists a full description of reset states of all

registers. Figure 7-7 shows a simpliﬁed block diagram

of the on-chip reset circuit.

The Electrical Speciﬁcations sections show RC

frequency variation from part to part due to normal

process variation. The variation is larger for larger R

(since leakage current variation will affect RC

frequency more for large R) and for smaller C (since

variation of input capacitance will affect RC

frequency more).

Also, see the Electrical Speciﬁcations sections for

variation of oscillator frequency due to VDD for given

Rext/Cext values as well as frequency variation due to

operating temperature for given R, C, and VDD values.

The oscillator frequency, divided by four, is available

on the OSC2/CLKOUT pin, and can be used for test

purposes or to synchronize other logic.

FIGURE 7-6: RC OSCILLATOR MODE

VDD

Rext

Internal

clock

OSC1

N

PIC16C5X

Cext

VSS

Fosc/4

OSC2/CLKOUT

DS30015M-page 30

1995 Microchip Technology Inc.

PIC16C5X

TABLE 7-5:

RESET CONDITIONS FOR SPECIAL REGISTERS

PCL

Addr: 02h

STATUS

Addr: 03h

Condition

1111 1111

0001 1xxx

Power-On Reset

(1)

000u uuuu

MCLR reset (normal operation)

MCLR wake-up (from SLEEP)

WDT reset (normal operation)

WDT wake-up (from SLEEP)

0001 0uuu

(2)

0000 1uuu

0000 0uuu

Legend: u= unchanged, x= unknown, -= unimplemented read as '0'.

Note 1: TO and PD bits retain their last value until one of the other reset conditions occur.

2: The CLRWDTinstruction will set the TO and PD bits.

TABLE 7-6:

RESET CONDITIONS FOR ALL REGISTERS

Register

W

Address

N/A

Power-On Reset

xxxx xxxx

1111 1111

--11 1111

xxxx xxxx

1111 1111

MCLR or WDT Reset

uuuu uuuu

1111 1111

TRIS

N/A

--11 1111

OPTION

INDF

N/A

uuuu uuuu

00h

uuuu uuuu

TMR0

PCL⁽¹⁾

01h

1111 1111

02h

STATUS⁽¹⁾

0001 1xxx

000q quuu

03h

1xxx xxxx

---- xxxx

xxxx xxxx

1uuu uuuu

---- uuuu

uuuu uuuu

FSR

04h

05h

06h

07h

PORTA

PORTB

PORTC⁽²⁾

xxxx xxxx

uuuu uuuu

General Purpose

register ﬁles

08-7Fh

Legend: u= unchanged, x= unknown, -= unimplemented, read as '0',

q= see tables in Section 7.7 for possible values.

Note 1: See Table 7-5 for reset value for speciﬁc conditions.

2: General purpose register ﬁle on the PIC16C54/CR54/C56.

FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Power-Up

Detect

POR (Power-On Reset)

VDD

MCLR/VPP pin

WDT Time-out

8-bit Asynch

RESET

S

R

Q

On-Chip

RC OSC

Ripple Counter

(Start-Up Timer)

CHIP RESET

1995 Microchip Technology Inc.

DS30015M-page 31

PIC16C5X

7.4

Power-On Reset (POR)

FIGURE 7-8: ELECTRICAL STRUCTURE OF

MCLR/VPP PIN

The PIC16C5X family incorporates on-chip Power-On

Reset (POR) circuitry which provides an internal chip

reset for most power-up situations. To use this feature,

the user merely ties the MCLR/VPP pin (Figure 7-8) to

VDD. A simpliﬁed block diagram of the on-chip

Power-On Reset circuit is shown in Figure 7-7.

RIN

(1)

MCLR

Schmitt Trigger

Input Buffer

N

(1)

The Power-On Reset circuit and the Device Reset

Timer (Section 7.5) circuit are closely related. On

power-up, the reset latch is set and the DRT is reset.

The DRT timer begins counting once it detects MCLR

to be high. After the time-out period, which is typically

18 ms, it will reset the reset latch and thus end the

on-chip reset signal.

VSS

Note 1: ESD protection circuits

FIGURE 7-9: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

A power-up example where MCLR is not tied to VDD is

shown in Figure 7-10. VDD is allowed to rise and

stabilize before bringing MCLR high. The chip will

actually come out of reset TDRT msec after MCLR

goes high.

VDD

In Figure 7-11, the on-chip Power-On Reset feature is

being used (MCLR and VDD are tied together). The

VDD is stable before the start-up timer times out and

there is no problem in getting a proper reset. However,

Figure 7-12 depicts a problem situation where VDD

rises too slowly. The time between when the DRT

senses a high on the MCLR/VPP pin, and when the

MCLR/VPP pin (and VDD) actually reach their full

value, is too long. In this situation, when the start-up

timer times out, VDD has not reached the VDD (min)

value and the chip is, therefore, not guaranteed to

function correctly.

D

R

R1

MCLR

PIC16C5X

C

• External Power-On Reset circuit is required

only if VDD power-up is too slow. The diode D

helps discharge the capacitor quickly when

VDD powers down.

• R < 40 kΩ is recommended to make sure that

voltage drop across R does not exceed 0.2V

(max leakage current spec on MCLR/VPP pin

is 5 µA). A larger voltage drop will degrade

VIH level on MCLR/VPP pin.

On-chip POR is guaranteed to work if the rate of rise

of VDD is no slower than 0.05V/ms and VDD starts from

0V. If the on-chip POR time delay is too short for low

frequency crystals/resonators (which require much

longer than 18 ms to start-up and stabilize) or for high

frequency crystals/resonators (which have to reach a

higher VDD voltage for operation), we recommend that

external RC circuits be used to achieve longer POR

delay times (Figure 7-9).

• R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C

in the event of MCLR pin breakdown due to

ESD or EOS.

DS30015M-page 32

1995 Microchip Technology Inc.

PIC16C5X

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): FAST VDD RISE TIME

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLRTIED TO VDD): SLOW VDD RISETIME

V1

VDD

MCLR

INTERNAL POR

TDRT

DRT TIME-OUT

INTERNAL RESET

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its ﬁnal value. In

this example, the chip will reset properly if, and only if, V1 ≥ VDD min.

1995 Microchip Technology Inc.

DS30015M-page 33

PIC16C5X

7.5

Device Reset Timer (DRT)

7.6

Watchdog Timer (WDT)

The Device Reset Timer (DRT) provides a ﬁxed 18 ms

nominal time-out on reset. The DRT operates on an

internal RC oscillator. The processor is kept in RESET

as long as the DRT is active. The DRT delay allows

VDD to rise above VDD min., and for the oscillator to

stabilize.

The Watchdog Timer (WDT) is a free running on-chip

RC oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins have been stopped, for

example, by execution of a SLEEPinstruction. During

normal operation or SLEEP, a WDT reset or wake-up

reset generates a device RESET.

Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to

establish a stable oscillation. The on-chip DRT keeps

the device in a RESET for approximately 18 ms after

the voltage on the MCLR/VPP pin has reached a logic

high (VIHMC) level. Thus, external RC networks

connected to the MCLR input are not required in most

cases, allowing for savings in cost-sensitive and/or

space restricted applications.

The TO bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset.

The WDT can be permanently disabled by

programming the conﬁguration bit WDTE as a '0'

(Section 7.1).

7.6.1

WDT PERIOD

The Device Reset time delay will vary from chip to chip

due to VDD, temperature, and process variation. See

AC parameters for details.

The WDT has a nominal time-out period of 18 ms,

(with no prescaler). If a longer time-out period is

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT (under software control)

by writing to the OPTION register. Thus, time-out a

period of a nominal 2.3 seconds can be realized.

These periods vary with temperature, VDD and

part-to-part process variations (see DC specs).

The DRT will also be triggered upon a Watchdog

Timer time-out. This is particularly important for

applications using the WDT to wake the PIC16C5X

from SLEEP mode automatically.

Under worst case conditions (VDD = Min., Temperature

= Max., max. WDT prescaler), it may take several

seconds before a WDT time-out occurs.

7.6.2

WDT PROGRAMMING CONSIDERATIONS

The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it

from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the

postscaler, if assigned to the WDT. This gives the

maximum SLEEP time before a WDT wake-up reset.

DS30015M-page 34

1995 Microchip Technology Inc.

PIC16C5X

FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM

From Timer0 Clock Source

(Figure 6-6)

0

M

Postscaler

1

Watchdog

Timer

U

X

8 - to - 1 MUX

PS2:PS0

PSA

WDT Enable

EPROM Bit

To Timer0 (Figure 6-6)

1

0

PSA

MUX

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

WDT

Time-out

TABLE 7-7:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

(2)

FFFh

N/A

Conﬁg. Word

OPTION

—

CP

WDTE FOSC1 FOSC0 ---- uuuu ---- uuuu

PS2 PS1 PS0 --11 1111 --11 1111

T0CS

T0SE

PSA

Legend: Shaded boxes = Not used by Watchdog Timer,

–= unimplemented, read as '0', u= unchanged

Note 1: Refer to the PIC16C5X Programming Speciﬁcations (literature number DS30190) to determine how to access the conﬁgu-

ration word.

2: Only the ﬁrst 8 bits of the Conﬁguration Word are shown. Reset values (for POR, MCLR and WDT) for bits 12:8 are unim-

plemented, read as ’0’. Initial values of bits 3:0 = 1111.

1995 Microchip Technology Inc.

DS30015M-page 35

PIC16C5X

7.7

Time-Out Sequence and Power Down

Status Bits (TO/PD)

7.8

Reset on Brown-Out

A brown-out is a condition where device power (VDD)

dips below its minimum value, but not to zero, and

then recovers. The device should be reset in the event

of a brown-out.

The TO and PD bits in the STATUS register can be

tested to determine if a RESET condition has been

caused by

a power-up condition, a MCLR or

Watchdog Timer (WDT) reset, or a MCLR or WDT

wake-up reset.

To reset PIC16C5X devices when a brown-out occurs,

external brown-out protection circuits may be built

(Figure 7-14 and Figure 7-15).

TABLE 7-8:

TO/PD STATUS AFTER

RESET

FIGURE 7-14: BROWN-OUT PROTECTION

CIRCUIT 1

TO

PD

RESET was caused by

Power-up (POR)

1

u

1

u

VDD

(1)

MCLR reset (normal operation)

VDD

1

0

1

0

MCLR wake-up reset (from SLEEP)

WDT reset (normal operation)

33k

WDT wake-up reset (from SLEEP)

10k

MCLR

Legend: u= unchanged

Note 1: The TO and PD bits maintain their status (u) until

a reset occurs. A low-pulse on the MCLR input

does not change the TO and PD status bits.

40k

PIC16C5X

These STATUS bits are only affected by events listed

in Table 7-9.

This circuit will activate reset when VDD goes below Vz +

0.7V (where Vz = Zener voltage).

TABLE 7-9:

EVENTS AFFECTING TO/PD

STATUS BITS

Event

TO PD

Remarks

FIGURE 7-15: BROWN-OUT PROTECTION

CIRCUIT 2

1

0

1

u

0

1

Power-up

WDT Time-out

No effect on PD

VDD

SLEEPinstruction

CLRWDTinstruction

Legend: u= unchanged

A WDT time-out will occur regardless of the status of the TO

bit. A SLEEPinstruction will be executed, regardless of the

status of the PD bit. Table 7-8 reﬂects the status of TO and

PD after the corresponding event.

VDD

R1

Q1

MCLR

R2

40k

PIC16C5X

Table 7-5 lists the reset conditions for the special

function registers, while Table 7-6 lists the reset

conditions for all the registers.

This brown-out circuit is less expensive, although

less accurate. Transistor Q1 turns off when VDD

is below a certain level such that:

R1

= 0.7V

VDD •

R1 + R2

DS30015M-page 36

1995 Microchip Technology Inc.

PIC16C5X

7.9

Power-Down Mode (SLEEP)

7.10

Code Protection

A device may be powered down (SLEEP) and later

powered up (Wake-up from SLEEP).

The program memory can be code protected by

selecting the code protect option when programming

the device.

7.9.1

SLEEP

In a code protected mode, the conﬁguration word will

not be protected, allowing reading of all bits.

The Power-Down mode is entered by executing a

SLEEPinstruction.

For EPROM devices, program memory locations 40h

and above cannot be further programmed. However,

the ﬁrst 64 locations, 00h-3Fh, may be programmed.

These locations are not considered "secure".

If enabled, the Watchdog Timer will be cleared but

keeps running, the TO bit (STATUS<4>) is set, the PD

bit (STATUS<3>) is cleared and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, driving low, or hi-impedance).

7.11

ID Locations

Four memory locations are designated as ID locations

where the user can store checksum or other

code-identiﬁcation numbers. These locations are not

accessible during normal execution but are readable

and writable during program/verify.

It should be noted that a RESET generated by a WDT

time-out does not drive the MCLR/VPP pin low.

For lowest current consumption while powered down,

the T0CKI input should be at VDD or VSS and the

MCLR/VPP pin must be at a logic high level (VIHMC).

Use only the lower four bits of the ID locations and

always program the upper eight bits as '1's.

7.9.2

WAKE-UP FROM SLEEP

Note: Microchip will assign a unique pattern

number for QTP and SQTP requests and

for ROM devices. This pattern number will

be unique and traceable to the

submitted code.

The device can wake-up from SLEEP through one of

the following events:

1. An external reset input on MCLR/VPP pin.

2. A Watchdog Timer time-out reset (if WDT was

enabled).

Both of these events cause a device reset. The TO

and PD bits can be used to determine the cause of

device reset. The TO bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD bit, which is

set on power-up, is cleared when SLEEPis invoked.

The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

1995 Microchip Technology Inc.

DS30015M-page 37

PIC16C5X

NOTES:

DS30015M-page 38

1995 Microchip Technology Inc.

PIC16C5X

All instructions are executed within one single

instruction cycle, unless a conditional test is true or the

program counter is changed as a result of an

instruction. In this case, the execution takes two

instruction cycles. One instruction cycle consists of

four oscillator periods. Thus, for an oscillator

frequency of 4 MHz, the normal instruction execution

time is 1 µs. If a conditional test is true or the program

counter is changed as a result of an instruction, the

instruction execution time is 2 µs.

8.0

INSTRUCTION SET SUMMARY

Each PIC16C5X instruction is a 12-bit word divided

into an OPCODE, which speciﬁes the instruction type,

and one or more operands which further specify the

operation of the instruction. The PIC16C5X instruction

set summary in Table 8-2 groups the instructions into

byte-oriented, bit-oriented, and literal and control

operations. Table 8-1 shows the opcode ﬁeld

descriptions.

For byte-oriented instructions, 'f' represents a ﬁle

register designator and 'd' represents a destination

designator. The ﬁle register designator is used to

specify which one of the 32 file registers is to be used

by the instruction.

Figure 8-1 shows the three general formats that the

instructions can have. All examples in the ﬁgure use the

following format to represent a hexadecimal number:

0xhhh

where 'h' signiﬁes a hexadecimal digit.

The destination designator speciﬁes where the result

of the operation is to be placed. If 'd' is '0', the result is

placed in the W register. If 'd' is '1', the result is placed

in the ﬁle register speciﬁed in the instruction.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

For bit-oriented instructions, 'b' represents a bit ﬁeld

designator which selects the number of the bit affected

by the operation, while 'f' represents the number of the

ﬁle in which the bit is located.

11

6

5

d

4

0

OPCODE

f (FILE #)

d = 0 for destination W

d = 1 for destination f

For literal and control operations, 'k' represents an

8 or 9-bit constant or literal value.

f = 5-bit ﬁle register address

Bit-oriented ﬁle register operations

11 8 7

b (BIT #)

TABLE 8-1:

OPCODE FIELD

DESCRIPTIONS

5

4

0

OPCODE

f (FILE #)

Field

Description

b = 3-bit bit address

f = 5-bit ﬁle register address

f

W

b

k

Register ﬁle address (0x00 to 0x7F)

Working register (accumulator)

Literal and control operations (except GOTO)

11

Bit address within an 8-bit ﬁle register

Literal ﬁeld, constant data or label

8

7

0

OPCODE

k (literal)

Don't care location (= 0 or 1)

k = 8-bit immediate value

Literal and control operations - GOTOinstruction

11 0

The assembler will generate code with x = 0. It is

the recommended form of use for compatibility

with all Microchip software tools.

x

d

9

8

Destination select;

OPCODE

k (literal)

d = 0 (store result in W)

d = 1 (store result in ﬁle register 'f')

Default is d = 1

k = 9-bit immediate value

label Label name

TOS

PC

Top of Stack

Program Counter

Watchdog Timer Counter

Time-Out bit

WDT

TO

PD

Power-Down bit

Destination, either the W register or the speciﬁed

register ﬁle location

dest

Options

[ ]

( )

→

Contents

Assigned to

Register bit ﬁeld

In the set of

< >

User deﬁned term (font is courier)

italics

1995 Microchip Technology Inc.

DS30015M-page 39

This document was created with FrameMaker 4 0 4

PIC16C5X

TABLE 8-2:

INSTRUCTION SET SUMMARY

12-Bit Opcode

Cycles MSb LSb Affected Notes

Mnemonic,

Operands

Status

Description

0001 11df ffff

C,DC,Z

1,2,4

2,4

4

1

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate left f through Carry

Rotate right f through Carry

Subtract W from f

Swap f

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f,d

f

0001 01df ffff

0000 011f ffff

0000 0100 0000

0010 01df ffff

0000 11df ffff

Z

None

Z

None

Z

–

f, d

f

2,4

1,4

1(2) 0010 11df ffff

0010 10df ffff

1(2) 0011 11df ffff

1

0001 00df ffff

0010 00df ffff

0000 001f ffff

0000 0000 0000

0011 01df ffff

0011 00df ffff

0000 10df ffff

0011 10df ffff

0001 10df ffff

Z

None

C

–

2,4

1,2,4

2,4

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

C

C,DC,Z

None

Z

2,4

Exclusive OR W with f

BIT-ORIENTED FILE REGISTER OPERATIONS

1

0100 bbbf ffff

0101 bbbf ffff

None

2,4

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

BCF

BSF

BTFSC

BTFSS

f, b

1 (2) 0110 bbbf ffff

1 (2) 0111 bbbf ffff

LITERAL AND CONTROL OPERATIONS

1

2

1

2

1

2

1

1110 kkkk kkkk

1001 kkkk kkkk

0000 0000 0100

101k kkkk kkkk

1101 kkkk kkkk

1100 kkkk kkkk

0000 0000 0010

1000 kkkk kkkk

0000 0000 0011

0000 0000 0fff

1111 kkkk kkkk

Z

None

O, PD

None

Z

None

TO, PD

None

Z

AND literal with W

Call subroutine

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

OPTION

RETLW

SLEEP

TRIS

k

–

f

1

3

T

Clear Watchdog Timer

Unconditional branch

Inclusive OR Literal with W

Move Literal to W

Load OPTION register

Return, place Literal in W

Go into standby mode

Load TRIS register

Exclusive OR Literal to W

XORLW

k

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except forGOTO.

(Section 4.5)

2: When an I/O register is modiﬁed as a function of itself (e.g.MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven

low by an external device, the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5, 6, or 7 causes the contents of the W register to be written to the tristate

latches of PORTA, B or C, respectively. A '1' forces the pin to a hi-impedance state and disables the output buff-

ers.

4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared

(if assigned to TMR0).

DS30015M-page 40

1995 Microchip Technology Inc.

PIC16C5X

ADDWF

Syntax:

Add W and f

[ label ] ADDWF f,d

0 ≤ f ≤ 31

ANDWF

Syntax:

AND W with f

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 31

d

[0,1]

d

[0,1]

Operation:

(W) + (f) → (dest)

Operation:

(W) .AND. (f) → (dest)

Status Affected: C, DC, Z

Status Affected:

Encoding:

Z

0001

11df

ffff

0001

01df

ffff

Encoding:

Add the contents of the W register and

register 'f'. If 'd' is 0 the result is stored

in the W register. If 'd' is '1' the result is

stored back in register 'f'.

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

'1' the result is stored back in register 'f'.

Description:

Words:

1

Words:

1

Cycles:

Example:

1

Cycles:

Example:

ADDWF FSR, 0

ANDWF FSR,

1

Before Instruction

W

=

0x17

W

=

0x17

FSR = 0xC2

After Instruction

W

=

0xD9

W

=

0x17

FSR = 0xC2

FSR = 0x02

ANDLW

And literal with W

BCF

Bit Clear f

Syntax:

[ label ] ANDLW

k

Syntax:

Operands:

[ label ] BCF f,b

Operands:

Operation:

Status Affected:

Encoding:

Description:

0 ≤ k ≤ 255

0 ≤ f ≤ 31

0 ≤ b ≤ 7

(W).AND. (k) → (W)

Operation:

0 → (f<b>)

Z

Status Affected: None

1110

kkkk

0100

bbbf

ffff

Encoding:

Description:

Words:

The contents of the W register are

AND’ed with the eight-bit literal 'k'. The

result is placed in the W register.

Bit 'b' in register 'f' is cleared.

1

Words:

1

Cycles:

Example:

1

BCF

FLAG_REG,

7

Example:

ANDLW 0x5F

Before Instruction

FLAG_REG = 0xC7

W

=

0xA3

After Instruction

FLAG_REG = 0x47

W

=

0x03

1995 Microchip Technology Inc.

DS30015M-page 41

PIC16C5X

BSF

Bit Set f

BTFSS

Bit Test f, Skip if Set

Syntax:

Operands:

[ label ] BSF f,b

Syntax:

[ label ] BTFSS f,b

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 31

0 ≤ b < 7

Operation:

1 → (f<b>)

Operation:

skip if (f<b>) = 1

Status Affected: None

0101

bbbf

ffff

0111

bbbf

ffff

Encoding:

Description:

Words:

Encoding:

Bit 'b' in register 'f' is set.

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

Description:

1

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Cycles:

BSF

FLAG_REG,

7

Example:

Before Instruction

FLAG_REG = 0x0A

Words:

1

After Instruction

Cycles:

Example:

1(2)

FLAG_REG = 0x8A

HERE

FALSE GOTO

TRUE

BTFSS FLAG,1

PROCESS_CODE

•

BTFSC

Bit Test f, Skip if Clear

•

Syntax:

[ label ] BTFSC f,b

Operands:

0 ≤ f ≤ 31

0 ≤ b ≤ 7

Before Instruction

PC

=

address (HERE)

After Instruction

If FLAG<1>

PC

Operation:

skip if (f<b>) = 0

=

0,

Status Affected: None

address (FALSE);

1,

address (TRUE)

bbbf

ffff

if FLAG<1>

PC

Encoding:

0110

If bit 'b' in register 'f' is 0 then the next

instruction is skipped.

Description:

If bit 'b' is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words:

1

Cycles:

Example:

1(2)

HERE

FALSE GOTO

TRUE

BTFSC

FLAG,1

PROCESS_CODE

•

Before Instruction

PC

=

address (HERE)

After Instruction

if FLAG<1>

PC

=

0,

address (TRUE);

1,

address(FALSE)

if FLAG<1>

PC

DS30015M-page 42

1995 Microchip Technology Inc.

PIC16C5X

CALL

Subroutine Call

[ label ] CALL k

0 ≤ k ≤ 255

CLRW

Clear W

Syntax:

[ label ] CLRW

None

Operands:

Operation:

Operands:

Operation:

(PC) + 1→ Top of Stack;

k → PC<7:0>;

00h → (W);

1 → Z

(STATUS<6:5>) → PC<10:9>;

0 → PC<8>

Status Affected:

Encoding:

Z

0000

0100

0000

Status Affected: None

The W register is cleared. Zero bit (Z)

is set.

Description:

1001

kkkk

Encoding:

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared. CALLis

a two cycle instruction.

Description:

Words:

1

Cycles:

Example:

1

CLRW

Before Instruction

W

=

0x5A

After Instruction

Words:

1

2

W

=

0x00

Cycles:

Example:

Z

=

1

HERE

CALL

THERE

Before Instruction

CLRWDT

Clear Watchdog Timer

[ label ] CLRWDT

None

PC

=

address (HERE)

Syntax:

After Instruction

PC

=

address (THERE)

Operands:

Operation:

TOS =

address (HERE + 1)

00h → WDT;

0 → WDT prescaler (if assigned);

1 → TO;

1 → PD

CLRF

Clear f

Syntax:

[ label ] CLRF

f

Status Affected: TO, PD

Operands:

Operation:

0 ≤ f ≤ 31

0000

0100

Encoding:

00h → (f);

1 → Z

The CLRWDTinstruction resets the

WDT. It also resets the prescaler, if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Description:

Status Affected:

Encoding:

Z

0000

011f

ffff

The contents of register 'f' are cleared

and the Z bit is set.

Description:

Words:

1

Cycles:

Example:

1

Words:

1

CLRWDT

Cycles:

Example:

Before Instruction

CLRF

FLAG_REG

WDT counter

=

?

Before Instruction

FLAG_REG

After Instruction

WDT counter

=

0x5A

0x00

After Instruction

WDT prescale =

0

1

FLAG_REG

Z

=

0x00

1

TO

PD

=

1995 Microchip Technology Inc.

DS30015M-page 43

PIC16C5X

COMF

Complement f

DECFSZ

Syntax:

Decrement f, Skip if 0

[ label ] DECFSZ f,d

0 ≤ f ≤ 31

Syntax:

Operands:

[ label ] COMF f,d

0 ≤ f ≤ 31

Operands:

d

[0,1]

d

[0,1]

Operation:

(f) → (dest)

Operation:

(f) – 1 → d; skip if result = 0

Status Affected:

Encoding:

Z

Status Affected: None

0010

01df

ffff

0010

11df

ffff

Encoding:

The contents of register 'f' are comple-

mented. If 'd' is 0 the result is stored in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words:

1

Cycles:

Example:

COMF

REG1,0

Words:

1

Before Instruction

REG1

=

0x13

Cycles:

Example:

1(2)

After Instruction

HERE

DECFSZ

GOTO

CONTINUE •

CNT, 1

LOOP

REG1

=

W

=

0xEC

•

DECF

Decrement f

[ label ] DECF f,d

0 ≤ f ≤ 31

Before Instruction

PC

=

address (HERE)

Syntax:

After Instruction

Operands:

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT - 1;

0,

address (CONTINUE);

0,

d

[0,1]

Operation:

(f) – 1 → (dest)

Status Affected:

Encoding:

Z

address (HERE+1)

0000

11df

ffff

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

GOTO

Unconditional Branch

[ label ] GOTO k

0 ≤ k ≤ 511

Syntax:

Words:

1

Operands:

Operation:

Cycles:

Example:

k → PC<8:0>;

STATUS<6:5> → PC<10:9>

DECF

CNT,

1

Before Instruction

Status Affected: None

CNT

=

0x01

0

101k

kkkk

Encoding:

Z

=

GOTOis an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTOis a

two cycle instruction.

Description:

After Instruction

CNT

=

0x00

1

Z

=

Words:

1

Cycles:

Example:

2

GOTO THERE

After Instruction

PC

=

address (THERE)

DS30015M-page 44

1995 Microchip Technology Inc.

PIC16C5X

INCF

Increment f

IORLW

Inclusive OR literal with W

Syntax:

Operands:

[ label ] INCF f,d

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

0 ≤ f ≤ 31

Operands:

Operation:

Status Affected:

Encoding:

Description:

d

[0,1]

(W) .OR. (k) → (W)

Z

Operation:

(f) + 1 → (dest)

Status Affected:

Encoding:

Z

1101

kkkk

0010

10df

ffff

The contents of the W register are

OR’ed with the eight bit literal 'k'. The

result is placed in the W register.

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

1

Cycles:

Example:

1

Words:

1

IORLW 0x35

Cycles:

Example:

Before Instruction

INCF

CNT,

1

W

=

0x9A

Before Instruction

After Instruction

CNT

=

0xFF

0

W

=

0xBF

Z

=

Z

=

0

After Instruction

CNT

Z

=

0x00

1

IORWF

Inclusive OR W with f

[ label ] IORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

INCFSZ

Increment f, Skip if 0

[ label ] INCFSZ f,d

0 ≤ f ≤ 31

d

[0,1]

Syntax:

Operation:

(W).OR. (f) → (dest)

Operands:

Status Affected:

Encoding:

Z

d

[0,1]

0001

00df

ffff

Operation:

(f) + 1 → (dest), skip if result = 0

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Status Affected: None

0011

11df

ffff

Encoding:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Description:

Words:

1

Cycles:

Example:

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

IORWF

RESULT, 0

Before Instruction

RESULT =

0x13

0x91

W

=

After Instruction

RESULT =

Words:

1

0x13

0x93

0

Cycles:

Example:

1(2)

W

Z

=

HERE

INCFSZ

GOTO

CNT,

LOOP

1

CONTINUE •

•

Before Instruction

PC

=

address (HERE)

After Instruction

CNT

if CNT

PC

if CNT

PC

=

≠

=

CNT + 1;

0,

address (CONTINUE);

0,

address (HERE +1)

1995 Microchip Technology Inc.

DS30015M-page 45

PIC16C5X

MOVF

Move f

MOVWF

Syntax:

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 31

Syntax:

Operands:

[ label ] MOVF f,d

f

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

(W) → (f)

Operation:

(f) → (dest)

Status Affected: None

Status Affected:

Encoding:

Z

0000

001f

ffff

Encoding:

0010

00df

ffff

Move data from the W register to regis-

ter 'f'.

Description:

The contents of register 'f' is moved to

destination 'd'. If 'd' is 0, destination is

the W register. If 'd' is 1, the destination

is ﬁle register 'f'. 'd' is 1 is useful to test

a ﬁle register since status ﬂag Z is

affected.

Description:

Words:

1

Cycles:

Example:

1

MOVWF TEMP_REG

Before Instruction

Words:

1

TEMP_REG

W

=

0xFF

0x4F

Cycles:

Example:

MOVF

FSR,

0

After Instruction

TEMP_REG

W

=

0x4F

After Instruction

W

=

value in FSR register

NOP

No Operation

[ label ] NOP

None

MOVLW

Move Literal to W

[ label ] MOVLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

No operation

k → (W)

Status Affected: None

0000

Status Affected: None

Encoding:

Description:

Words:

1100

kkkk

Encoding:

No operation.

The eight bit literal 'k' is loaded into the

W register. The don’t cares will assem-

ble as 0s.

Description:

1

Cycles:

1

NOP

Example:

Words:

1

Cycles:

Example:

1

MOVLW 0x5A

After Instruction

W

=

0x5A

DS30015M-page 46

1995 Microchip Technology Inc.

PIC16C5X

OPTION

Syntax:

Load OPTION Register

[ label ] OPTION

None

RLF

Rotate Left f through Carry

Syntax:

Operands:

[ label ] RLF f,d

Operands:

Operation:

0 ≤ f ≤ 31

d

[0,1]

(W) → OPTION

Status Affected: None

Operation:

See description below

C

0000

0010

Encoding:

Status Affected:

Encoding:

The content of the W register is loaded

into the OPTION register.

Description:

0011

01df

ffff

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is stored

back in register 'f'.

Description:

Words:

Cycles:

Example

1

OPTION

Before Instruction

register 'f'

C

W

=

0x07

After Instruction

OPTION =

Words:

1

Cycles:

Example:

1

RLF

REG1,0

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

Before Instruction

Syntax:

REG1

C

=

1110 0110

0

Operands:

Operation:

After Instruction

k → (W);

TOS → PC

REG1

W

C

=

1110 0110

1100 1100

1

Status Affected: None

1000

kkkk

Encoding:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Description:

RRF

Rotate Right f through Carry

[ label ] RRF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

d

[0,1]

Words:

1

2

Operation:

See description below

C

Cycles:

Example:

Status Affected:

Encoding:

CALL TABLE ;W contains

;table offset

;value.

0011

00df

ffff

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Description:

•

;W now has table

;value.

•

TABLE

ADDWF PC

RETLW k1

RETLW k2

;W = offset

;Begin table

;

register 'f'

C

•

Words:

1

•

Cycles:

Example:

1

RETLW kn

; End of table

RRF

REG1,0

Before Instruction

W

=

0x07

Before Instruction

REG1

C

=

1110 0110

0

After Instruction

W

=

value of k8

After Instruction

REG1

W

C

=

1110 0110

0111 0011

0

1995 Microchip Technology Inc.

DS30015M-page 47

PIC16C5X

SLEEP

Enter SLEEP Mode

SUBWF

Subtract W from f

Syntax:

[label]

None

[label] SUBWF f,d

SLEEP

Operands:

0 ≤ f ≤ 31

Operands:

Operation:

d

[0,1]

00h → WDT;

0 → WDT prescaler;

1 → TO;

Operation:

(f) – (W) → (dest)

Status Affected: C, DC, Z

0 → PD

0000

10df

ffff

Encoding:

Status Affected: TO, PD

Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0011

Encoding:

Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

The WDT and its prescaler are

cleared.

Description:

Words:

1

Cycles:

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

SUBWF

REG1, 1

Example 1:

Before Instruction

Words:

1

REG1

W

C

=

3

2

?

Cycles:

Example:

1

SLEEP

After Instruction

REG1

W

C

=

1

2

1

; result is positive

Example 2:

Before Instruction

REG1

W

C

=

2

?

After Instruction

REG1

W

C

=

0

2

1

; result is zero

Example 3:

Before Instruction

REG1

W

C

=

1

2

?

After Instruction

REG1

W

C

=

FF

2

0

; result is negative

DS30015M-page 48

1995 Microchip Technology Inc.

PIC16C5X

SWAPF

Syntax:

Swap Nibbles in f

[ label ] SWAPF f,d

0 ≤ f ≤ 31

XORLW

Exclusive OR literal with W

Syntax:

[label] XORLW k

0 ≤ k ≤ 255

Operands:

d

[0,1]

Operation:

(W) .XOR. k → (W)

Z

Operation:

(f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>)

Status Affected:

Encoding:

1111

kkkk

Status Affected: None

The contents of the W register are

XOR’ed with the eight bit literal 'k'. The

result is placed in the W register.

Description:

0011

10df

ffff

Encoding:

The upper and lower nibbles of register

'f' are exchanged. If 'd' is 0 the result is

placed in W register. If 'd' is 1 the result

is placed in register 'f'.

Description:

Words:

1

Cycles:

Example:

1

Words:

Cycles:

Example

1

XORLW 0xAF

Before Instruction

W

=

0xB5

SWAPF

REG1,

0

After Instruction

Before Instruction

W

=

0x1A

REG1

=

0xA5

After Instruction

REG1

W

=

0xA5

0X5A

XORWF

Exclusive OR W with f

[ label ] XORWF f,d

0 ≤ f ≤ 31

Syntax:

Operands:

TRIS

Load TRIS Register

d

[0,1]

Syntax:

[ label ] TRIS

f = 5, 6 or 7

f

Operation:

(W) .XOR. (f) → (dest)

Operands:

Operation:

Status Affected:

Encoding:

Z

(W) → TRIS register f

0001

10df

ffff

Status Affected: None

Exclusive OR the contents of the W

register with register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd' is

1 the result is stored back in register 'f'.

Description:

0000

0fff

Encoding:

TRIS register 'f' (f = 5, 6, or 7) is loaded

with the contents of the W register

Description:

Words:

Cycles:

Example

1

Words:

Cycles:

Example

1

TRIS

PORTA

REG,1

XORWF

Before Instruction

W

=

0XA5

REG

=

0xAF

0xB5

W

=

After Instruction

TRISA

=

After Instruction

REG

W

=

0x1A

0xB5

1995 Microchip Technology Inc.

DS30015M-page 49

PIC16C5X

NOTES:

DS30015M-page 50

1995 Microchip Technology Inc.

PIC16C5X

The PICMASTER Emulator System has been

designed as a real-time emulation system with

advanced features that are generally found on more

expensive development tools. The PC compatible 386

9.0

DEVELOPMENT SUPPORT

9.1

Development Tools

The PIC16/17 microcontrollers are supported with a full

range of hardware and software development tools:

(and

better)

machine

platform

and

the

Microsoft Windows 3.x environment was chosen to

best make these features available to you, the

end user.

• PICMASTER Real-Time In-Circuit Emulator

• PRO MATE Universal Programmer

• PICSTART Low-Cost Prototype Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• MPASM Assembler

The PICMASTER Universal Emulator System consists

primarily of four major components:

• Host-Interface Card

• Emulator Control Pod

• Target-Speciﬁc Emulator Probe

• PC-Host Emulation Control Software

• MPSIM Software Simulator

• C Compiler (MP-C)

• Fuzzy logic development system

(fuzzyTECH −MP)

The Windows operating system allows the developer to

take full advantage of the many powerful features and

functions of the PICMASTER system.

9.2

PICMASTER High Performance

Universal In-Circuit Emulator with

MPLAB IDE

PICMASTER emulation can operate in one window,

while a text editor is running in a second window.

PC-Host Emulation Control software takes full advan-

tage of Dynamic Data Exchange (DDE), a feature of

Windows. DDE allows data to be dynamically trans-

ferred between two or more Windows programs. With

this feature, data collected with PICMASTER can be

automatically transferred to a spreadsheet or database

program for further analysis.

The PICMASTER Universal In-Circuit Emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for all

microcontrollers in the PIC16C5X, PIC16CXX and

PIC17CXX families. PICMASTER is supplied with the

MPLAB Integrated Development Environment (IDE),

which allows editing, "make" and download, and

source debugging from a single environment. A

PICMASTER System conﬁguration is shown

in Figure 9-1.

Under Windows, as many as four PICMASTER emula-

tors can be run simultaneously from the same PC mak-

ing development of multi-microcontroller systems

possible (e.g., a system containing a PIC16CXX

processor and a PIC17CXX processor).

Interchangeable target probes allow the system to be

easily reconﬁgured for emulation of different proces-

sors. The universal architecture of the PICMASTER

allows expansion to support all new PIC16C5X,

PIC16CXX and PIC17CXX microcontrollers.

The PICMASTER probes speciﬁcations are shown

in Table 9-1.

FIGURE 9-1: PICMASTER SYSTEM CONFIGURATION

In-Line

5 VDC

Power Supply

(Optional)

90 - 250 VAC

Windows 3.x

Power Switch

Interchangeable

Emulator Probe

Power Connector

PC Bus

PC-Interface

PICMASTER Emulator Pod

Common Interface Card

PC Compatible Computer

Logic Probes

1995 Microchip Technology Inc.

DS30015M-page 51

This document was created with FrameMaker 4 0 4

PIC16C5X

TABLE 9-1:

PICMASTER PROBE

SPECIFICATION

TABLE 9-1:

PICMASTER PROBE

SPECIFICATION

PROBE

PICMASTER

PROBE

PICMASTER

PROBE

Devices

Maximum Operating

Frequency

20 MHz

10 MHz

Voltage

Frequency

10 MHz

20 MHz

Voltage

PIC16C54

PROBE-16D

4.5V - 5.5V

PIC16C65

PIC16C65A

PIC16C620

PIC16C621

PIC16C622

PIC16C70

PIC16C71

PIC16C71A

PIC16C72

PIC16C73

PIC16C73A

PIC16C74

PIC16C74A

PIC16C83

PIC16C84

PIC17C42

PIC17C43

PIC17C44

PROBE-16F

4.5V - 5.5V

(1)

PIC16C54A

PIC16CR54

PIC16CR54A

PIC16CR54B

PIC16C55

PROBE-16F

PROBE-16H

(1)

PROBE-16D

(1)

PROBE-16D

PROBE-16B

(1)

PIC16CR55

PIC16C56

PROBE-16D

(1)

PROBE-16B

PROBE-16F

(1)

PIC16CR56

PIC16C57

PROBE-16D

PROBE-16F

(1)

PIC16CR57A

PIC16CR57B

PIC16C58A

PIC16CR58A

PIC16CR58B

PIC16C61

PROBE-16F

(1)

PROBE-16D

(1)

PROBE-16F

PROBE-16C

PROBE-17B

(1)

PROBE-16D

PROBE-16G

PROBE-16E

PIC16C62

(1)

PIC16C62A

PIC16CR62

PIC16C63

PROBE-16E

PROBE-16F

(1)

Note 1: This PICMASTER probe can be used to

functionally emulate the device listed in the

previous column. Contact your Microchip sales

ofﬁce for details.

PIC16C64

PROBE-16E

(1)

PIC16C64A

PIC16CR64

PROBE-16E

(1)

DS30015M-page 52

1995 Microchip Technology Inc.

PIC16C5X

9.3

PRO MATE Universal Programmer

9.5

PICDEM-1 Low-Cost PIC16/17

Demonstration Board

The PRO MATE Universal Programmer is

a

full-featured programmer capable of operating in

stand-alone mode as well as PC-hosted mode.

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s

microcontrollers. The microcontrollers supported are:

PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61,

PIC16C62X, PIC16C71, PIC16C8X, PIC17C42,

PIC17C43 and PIC17C44. All necessary hardware and

software is included to run basic demo programs. The

users can program the sample microcontrollers

The PRO MATE has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to

enter commands and a modular detachable socket

assembly to support various package types. In stand-

alone mode the PRO MATE can read, verify or program

PIC16C5X, PIC16CXX and PIC17CXX devices. It can

also set conﬁguration and code-protect bits in

this mode.

provided with the PICDEM-1 board, on

a

PRO MATE or PICSTART-16B programmer, and

easily test ﬁrmware. The user can also connect the

PICDEM-1 board to the PICMASTER emulator and

download the ﬁrmware to the emulator for testing.

Additional prototype area is available for the user to

build some additional hardware and connect it to the

microcontroller socket(s). Some of the features include

an RS-232 interface, a potentiometer for simulated

analog input, push-button switches and eight LEDs

connected to PORTB.

In PC-hosted mode, the PRO MATE connects to the

PC via one of the COM (RS-232) ports. PC based

user-interface software makes using the programmer

simple and efﬁcient. The user interface is full-screen

and menu-based. Full screen display and editing of

data, easy selection of bit conﬁguration and part type,

easy selection of VDD min, VDD max and VPP levels,

load and store to and from disk ﬁles (Intel hex format)

are some of the features of the software. Essential

commands such as read, verify, program and blank

check can be issued from the screen. Additionally,

serial programming support is possible where each

part is programmed with a different serial number,

sequential or random.

9.6

PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C64, PIC16C65, PIC16C73 and

PIC16C74 microcontrollers. All the necessary

hardware and software is included to run the basic

demonstration programs. The user can program

the sample microcontrollers provided with the

PICDEM-2 board, on a PRO MATE programmer or

PICSTART-16C, and easily test ﬁrmware. The

PICMASTER emulator may also be used with the

PICDEM-2 board to test ﬁrmware. Additional prototype

area has been provided to the user for adding

additional hardware and connecting it to the

microcontroller socket(s). Some of the features include

The PRO MATE has a modular “programming socket

module”. Different socket modules are required for

different processor types and/or package types.

PRO MATE supports all PIC16C5X, PIC16CXX and

PIC17CXX processors.

9.4

PICSTART Low-Cost Development

System

a

RS-232 interface, push-button switches,

a

The PICSTART programmer is an easy to use, very

low-cost prototype programmer. It connects to the PC

via one of the COM (RS-232) ports. A PC-based user

interface software makes using the programmer simple

and efﬁcient. The user interface is full-screen and

menu-based. PICSTART is not recommended for

production programming.

potentiometer for simulated analog input, a Serial

EEPROM to demonstrate usage of the I C bus and

separate headers for connection to an LCD module

and a keypad.

2

1995 Microchip Technology Inc.

DS30015M-page 53

PIC16C5X

9.7

MPLAB Integrated Development

Environment Software

9.8

MPASM Assembler

The MPASM CrossAssembler is a PC-hosted symbolic

assembler. It supports all microcontroller series

including the PIC16C5X, PIC16CXX, and PIC17CXX

families.

The MPLAB Software brings an ease of software

development previously unseen in the 8-bit

microcontroller market. MPLAB is a windows based

application which contains:

MPASM offers full featured Macro capabilities,

conditional assembly, and several source and listing

formats. It generates various object code formats to

support Microchip's development tools as well as third

party programmers.

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator (available soon)

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

MPASM allows full symbolic debugging from

the

Microchip Universal Emulator System

(PICMASTER).

MPASM has the following features to assist in

developing software for speciﬁc use applications.

• Extensive on-line help

MPLAB allows you to:

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• edit your source ﬁles (either assembly or "C")

• one touch assemble (or compile) and download to

PIC16/17 tools (automatically updates all project

information)

• debug using:

- source ﬁles

- absolute listing ﬁle

• transfer data dynamically via DDE (soon to be

replaced by OLE)

• Macro assembly capability

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with

Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal

source and listing formats.

MPASM provides a rich directive language to support

programming of the PIC16/17. Directives are helpful in

making the development of your assemble source

code shorter and more maintainable.

• run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator

(available soon) allows a consistent platform and the

ability to easily switch from the low cost simulator to the

full featured emulator with minimal retraining due to

development tools.

• Data Directives are those that control the

allocation of memory and provide a way to refer to

data items symbolically (i.e., by meaningful

names).

• Control Directives control the MPASM listing

display. They allow the speciﬁcation of titles and

sub-titles, page ejects and other listing control.

This eases the readability of the printed

output ﬁle.

• Conditional Directives permit sections of

conditionally assembled code. This is most useful

where additional functionality may wished to be

added depending on the product (less

functionality for the low end product, then for the

high end product). Also this is very helpful in the

debugging of a program.

• Macro Directives control the execution and data

allocation within macro body deﬁnitions. This

makes very simple the re-use of functions in a

program as well as between programs.

DS30015M-page 54

1995 Microchip Technology Inc.

PIC16C5X

9.9

MPSIM Software Simulator

9.11

fuzzyTECH-MP Fuzzy Logic

Development System

The MPSIM Software Simulator allows code

development in a PC host environment. It allows the

user to simulate the PIC16/17 series microcontrollers

on an instruction level. On any given instruction, the

user may examine or modify any of the data areas or

provide external stimulus to any of the pins. The

input/output radix can be set by the user and the

execution can be performed in; single step, execute

until break, or in a trace mode. MPSIM fully supports

symbolic debugging using MP-C and MPASM. The

Software Simulator offers the low cost ﬂexibility to

develop and debug code outside of the laboratory

environment making it an excellent multi-project

software development tool.

fuzzyTECH-MP fuzzy logic development tool is

available in two versions - a low cost introductory

version, MP Explorer, for designers to gain

comprehensive working knowledge of fuzzy logic

system design; and full-featured version,

a

fuzzyTECH-MP, edition for implementing more

complex systems.

Both versions include Microchip’s fuzzyLAB

demonstration board for hands-on experience with

fuzzy logic systems implementation.

9.12

Development Systems

For convenience, the development tools are packaged

into comprehensive systems as listed in Table 9-2.

9.10

MP-C C Compiler

The MP-C Code Development System is a complete 'C'

compiler and integrated development environment for

Microchip’s PIC16/17 family of microcontrollers. The

compiler provides powerful integration capabilities and

ease of use not found with other compilers.

For easier source level debugging, the compiler

provides symbol information that is compatible with the

PICMASTER Universal Emulator memory display

(PICMASTER emulator software versions 1.13

and later).

The MP-C Code Development System is supplied

directly by Byte Craft Limited of Waterloo, Ontario,

Canada. If you have any questions, please contact

your regional Microchip FAE or Microchip technical

support personnel at (602) 786-7627.

TABLE 9-2:

Item

DEVELOPMENT SYSTEM PACKAGES

Name

System Description

1.

2.

3.

PICMASTER System

PICMASTER In-Circuit Emulator, PRO MATE Programmer, Assembler, Soft-

ware Simulator, Samples and your choice of Target Probe.

PICSTART System

PRO MATE System

PICSTART Low-Cost Prototype Programmer, Assembler, Software Simulator

and Samples.

PRO MATE Universal Programmer, full featured stand-alone or PC-hosted

programmer, Assembler, Simulator

1995 Microchip Technology Inc.

DS30015M-page 55

PIC16C5X

NOTES:

DS30015M-page 56

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

10.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–55°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ............................................................................................................... 0V to +7.5V

(2)

Voltage on MCLR with respect to VSS ......................................................................................................... 0V to +14V

Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)

(1)

Total Power Dissipation ....................................................................................................................................800 mW

Max. Current out of VSS pin ..................................................................................................................................150 mA

Max. Current into VDD pin .......................................................................................................................................50 mA

Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA

Input Clamp Current, IIK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA

Max. Output Current sunk by any I/O pin................................................................................................................25 mA

Max. Output Current sourced by any I/O pin...........................................................................................................20 mA

Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................40 mA

Max. Output Current sunk by a single I/O port (PORTA, B or C)............................................................................50 mA

Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)

Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,

a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather than

pulling this pin directly to VSS

†

NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1995 Microchip Technology Inc.

DS30015M-page 57

This document was created with FrameMaker 4 0 4

PIC16C5X

PIC16C54/55/56/57

TABLE 10-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

(RC, XT & 10) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

VDD: 3.0 V to 6.2 V

IDD: 3.3 mA max. at 5. V

IPD: 9 µA max. at 3.0 V, WDT dis

Freq: 4 MHz max.

RC

N/A

VDD: 3.0V to 6.25V

IDD: 1.8 mA typ. at 5.5V

IPD: 0.6 µA typ. at 3.0V WDT dis

Freq: 4 MHz max.

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

XT

HS

LP

N/A

VDD: 4.5V to 5.5V

IDD: 9.0 mA typ. at 5.5V

IPD: 0.6 µA typ. at 3.0V WDT dis

Freq: 20 MHz max.

IDD: 10 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 10 MHz max.

N/A

VDD: 2.5V to 6.25V

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

TABLE 10-2: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

(HS, LP & JW) AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

OSC

PIC16C5X-HS

PIC16C5X-LP

PIC16C5X/JW

VDD: 3.0V to 6.25V

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

RC

N/A

VDD: 3.0V to 6.25V

IDD: 3.3 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 4 MHz max.

XT

HS

LP

N/A

VDD: 4.5V to 5.5V

IDD: 20 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 20 MHz max.

IDD: 20 mA max. at 5.5V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 20 MHz max.

VDD: 2.5V to 6.25V

IDD: 15 µA typ. at 3.0V

IPD: 0.6 µA typ. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 32 µA max. at 32 kHz, 3.0V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 40 kHz max.

IDD: 32 µA max. at 32 kHz, 3.0V

IPD: 9 µA max. at 3.0V, WDT dis

Freq: 40 kHz max.

The shaded sections indicate oscillator selections which should work by design, but are not tested. It is recommended

that the user select the device type from information in unshaded sections.

DS30015M-page 58

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

10.1

DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Commercial)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5X-RC

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

VDD

3.0

4.5

2.5

6.25

5.5

6.25

V

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

(2)

RAM Data Retention Voltage

VDR

1.5*

V

Device in SLEEP Mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

VSS

See Section 7.4 for details on

Power-On Reset

VDD Rise Rate to ensure

Power-On Reset

SVDD 0.05*

IDD

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5X-RC

(4)

1.8

4.8

9.0

15

3.3

10

20

32

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.0V,

WDT disabled

PIC16C5X-XT

PIC16C5X-10

PIC16C5X-HS

PIC16C5X-LP

(5)

Power Down Current

IPD

4.0

0.6

12

9

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1995 Microchip Technology Inc.

DS30015M-page 59

PIC16C5X

PIC16C54/55/56/57

10.2

DC Characteristics: PIC16C5XI-RC, XT, 10, HS, LP (Industrial)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +85°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5XI-RC

PIC16C5XI-XT

PIC16C5XI-10

PIC16C5XI-HS

PIC16C5XI-LP

VDD

3.0

4.5

2.5

6.25

5.5

6.25

V

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 20 MHz

FOSC = DC to 40 kHz

(2)

RAM Data Retention Voltage

VDR

1.5*

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

VSS

See Section 7.4 for details on

Power-On Reset

VDD Rise Rate to ensure

Power-On Reset

SVDD 0.05*

IDD

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5XI-RC

(4)

1.8

4.8

9.0

19

3.3

10

20

40

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 20 MHz, VDD = 5.5V

FOSC = 32 kHz, Vdd = 3.0V,

WDT disabled

PIC16C5XI-XT

PIC16C5XI-10

PIC16C5XI-HS

PIC16C5XI-LP

(5)

Power Down Current

IPD

5.0

0.6

14

12

µA

VDD = 3.0V, WDT enabled

VDD = 3.0V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

DS30015M-page 60

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

10.3

DC Characteristics: PIC16C5XE-RC, XT, 10, HS, LP (Automotive)

DC Characteristics

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

(1)

Characteristic

Sym Min

Typ

Max Units

Conditions

Supply Voltage

PIC16C5XE-RC

PIC16C5XE-XT

PIC16C5XE-10

PIC16C5XE-HS

PIC16C5XE-LP

VDD

3.25

4.5

6.0

5.5

6.0

V

FOSC = DC to 4 MHz

FOSC = DC to 10 MHz

FOSC = DC to 16 MHz

FOSC = DC to 40 kHz

4.5

2.5

(2)

RAM Data Retention Voltage

VDR

1.5*

V

Device in SLEEP mode

VDD Start Voltage to ensure

Power-On Reset

VPOR

VSS

See Section 7.4 for details on

Power-On Reset

VDD rise rate to ensure

Power-On Reset

SVDD 0.05*

IDD

V/ms See Section 7.4 for details on

Power-On Reset

(3)

Supply Current

PIC16C5XE-RC

(4)

1.8

4.8

9.0

25

3.3

10

20

55

mA

µA

FOSC = 4 MHz, VDD = 5.5V

FOSC = 10 MHz, VDD = 5.5V

FOSC = 16 MHz, VDD = 5.5V

FOSC = 32 kHz, VDD = 3.25V,

WDT disabled

PIC16C5XE-XT

PIC16C5XE-10

PIC16C5XE-HS

PIC16C5XE-LP

(5)

Power Down Current

IPD

5.0

0.8

22

18

µA

VDD = 3.25V, WDT enabled

VDD = 3.25V, WDT disabled

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on

the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to

Vss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: IR = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

1995 Microchip Technology Inc.

DS30015M-page 61

PIC16C5X

PIC16C54/55/56/57

10.4

DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Commercial)

PIC16C5XI-RC, XT, 10, HS, LP (Industrial)

Standard Operating Conditions (unless otherwise speciﬁed)

DC Characteristics

All Pins Except

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Power Supply Pins

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3.

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL

VSS

0.2 VDD

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs

VHYS

IIL

0.15VDD*

V

(2,3)

Input Leakage Current

For VDD ≤ 5.5V

I/O ports

–1

–5

0.5

+1

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C5X-XT, 10, HS, LP

MCLR

µA

0.5

+5

+3

T0CKI

OSC1

–3

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

(3)

I/O ports

VDD – 0.7

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

DS30015M-page 62

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

10.5

DC Characteristics: PIC16C5X-RC, XT, 10, HS, LP (Automotive)

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature –40°C ≤ TA ≤ +125°C

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3.

DC Characteristics

All Pins Except

Power Supply Pins

(1)

Characteristic

Sym

Min

Typ

Max

Units

Conditions

Input Low Voltage

I/O ports

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

VIL

Vss

0.15 VDD

0.3 VDD

V

Pin at hi-impedance

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Input High Voltage

I/O ports

VIH

(5)

0.45 VDD

2.0

VDD

V

For all VDD

(5)

4.0V < VDD ≤ 5.5V

VDD > 5.5 V

0.36 VDD

0.85 VDD

0.7 VDD

MCLR (Schmitt Trigger)

T0CKI (Schmitt Trigger)

OSC1 (Schmitt Trigger)

(4)

PIC16C5X-RC only

PIC16C5X-XT, 10, HS, LP

Hysteresis of Schmitt

Trigger inputs

VHYS

IIL

0.15VDD*

V

(2,3)

Input Leakage Current

For VDD ≤ 5.5 V

I/O ports

–1

–5

0.5

+1

µA

VSS ≤ VPIN ≤ VDD,

Pin at hi-impedance

VPIN = VSS + 0.25V

VPIN = VDD

VSS ≤ VPIN ≤ VDD

VSS ≤ VPIN ≤ VDD,

PIC16C5X-XT, 10, HS, LP

MCLR

µA

0.5

+5

+3

T0CKI

OSC1

–3

Output Low Voltage

I/O ports

OSC2/CLKOUT

VOL

VOH

0.6

V

IOL = 8.7 mA, VDD = 4.5V

IOL = 1.6 mA, VDD = 4.5V,

PIC16C5X-RC

Output High Voltage

(3)

I/O ports

VDD – 0.7

V

IOH = –5.4 mA, VDD = 4.5V

IOH = –1.0 mA, VDD = 4.5V,

PIC16C5X-RC

OSC2/CLKOUT

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance

only and is not tested.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The speciﬁed

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltage.

3: Negative current is deﬁned as coming out of the pin.

4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C5X be driven with external clock in RC mode.

5: The user may use the better of the two speciﬁcations.

1995 Microchip Technology Inc.

DS30015M-page 63

PIC16C5X

PIC16C54/55/56/57

10.6

Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase subscripts (pp) and their meanings:

pp

T

Time

2

to

mc

osc

os

MCLR

ck

cy

drt

io

CLKOUT

cycle time

device reset timer

I/O port

oscillator

OSC1

t0

T0CKI

wdt

watchdog timer

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (Hi-impedance)

Low

Valid

L

Hi-impedance

FIGURE 10-1: LOAD CONDITIONS - PIC16C54/55/56/57

CL = 50 pF for all pins except OSC2

CL

15 pF for OSC2 in XT, HS or LP

modes when external clock

is used to drive OSC1

VSS

DS30015M-page 64

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

10.7

Timing Diagrams and Speciﬁcations

FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57

Q4

Q3

Q4

4

Q1

Q2

OSC1

1

3

4

2

CLKOUT

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (automotive)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3

Parameter

No.

(1)

Sym

Characteristic

Min Typ

Max Units

Conditions

(2)

FOSC

External CLKIN Frequency

DC

0.1

4

—

4

MHz RC osc mode

MHz XT osc mode

4

10

20

16

40

4

MHz 10 MHz mode

MHz HS osc mode (Com/Indust)

MHz HS osc mode (Automotive)

kHz LP osc mode

(2)

Oscillator Frequency

MHz RC osc mode

4

MHz XT osc mode

10

20

16

40

MHz 10 MHz mode

4

MHz HS osc mode (Com/Indust)

MHz HS osc mode (Automotive)

kHz LP osc mode

4

DC

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

1995 Microchip Technology Inc.

DS30015M-page 65

PIC16C5X

PIC16C54/55/56/57

TABLE 10-3: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON’T)

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (automotive)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3

Parameter

(1)

No.

Sym

Characteristic

Min Typ

Max Units

Conditions

RC osc mode

(2)

1

TOSC

External CLKIN Period

250

100

50

—

ns

µs

ns

µs

—

ns

µs

ns

XT osc mode

—

10 MHz mode

—

HS osc mode (Com/Indust)

HS osc mode (Automotive)

LP osc mode

62.5

25

—

(2)

Oscillator Period

250

100

50

—

RC osc mode

—

10,000

250

—

XT osc mode

—

10 MHz mode

—

HS osc mode (Com/Indust)

HS osc mode (Automotive)

LP osc mode

62.5

25

—

(3)

2

3

TCY

Instruction Cycle Time

—

4/FOSC

—

TosL, TosH Clock in (OSC1) Low or High Time

50*

20*

2*

—

XT oscillator

HS oscillator

LP oscillator

XT oscillator

HS oscillator

LP oscillator

—

4

TosR, TosF Clock in (OSC1) Rise or Fall Time

—

25*

50*

—

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating

conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation

and/or higher than expected current consumption.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (TCY) equals four times the input oscillator time base period.

DS30015M-page 66

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57

Q1

Q2

Q3

Q4

OSC1

10

11

CLKOUT

13

12

16

18

14

19

I/O Pin

(input)

15

17

I/O Pin

(output)

New Value

Old Value

20, 21

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

TABLE 10-4: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (automotive)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3

Parameter

(1)

No.

Sym

Characteristic

(2)

Min

Typ

Max

Units

10

11

12

13

14

15

16

17

18

TosH2ckL

TosH2ckH

TckR

OSC1↑ to CLKOUT↓

—

15

5

30**

15**

40**

—

ns

(2)

OSC1↑ to CLKOUT↑

—

(2)

CLKOUT rise time

—

(2)

TckF

CLKOUT fall time

—

5

(2)

CLKOUT↓ to Port out valid

TckL2ioV

TioV2ckH

TckH2ioI

TosH2ioV

TosH2ioI

—

(2)

Port in valid before CLKOUT↑

(2)

0.25 TCY+30*

Port in hold after CLKOUT↑

OSC1↑ (Q1 cycle) to Port out valid

0*

—

(3)

100*

—

OSC1↑ (Q2 cycle) to Port input invalid (I/O in

TBD

hold time)

19

TioV2osH

Port input valid to OSC1↑

TBD

—

ns

(I/O in setup time)

(3)

20

21

TioR

TioF

Port output rise time

—

10

25**

ns

(3)

Port output fall time

*

These parameters are characterized but not tested.

** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.

3: See Figure 10-1 for loading conditions.

1995 Microchip Technology Inc.

DS30015M-page 67

PIC16C5X

PIC16C54/55/56/57

FIGURE 10-4: RESET, WATCHDOG TIMER, AND

DEVICE RESET TIMER TIMING - PIC16C54/55/56/57

VDD

MCLR

30

Internal

POR

32

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

31

34

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

TABLE 10-5: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature

0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (automotive)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3

Parameter

No.

(1)

Sym Characteristic

Min Typ

Max Units

Conditions

30

31

TmcL MCLR Pulse Width (low)

100*

9*

—

ns VDD = 5.0V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

18*

30*

ms VDD = 5.0V (Commercial)

32

34

TDRT Device Reset Timer Period

9*

—

18*

—

30*

ms VDD = 5.0V (Commercial)

ns

TioZ I/O Hi-impedance from MCLR Low

100*

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design

guidance only and are not tested.

DS30015M-page 68

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57

T0CKI

40

41

42

TABLE 10-6: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57

AC Characteristics

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (automotive)

Operating Voltage VDD range is described in Section 10.1, Section 10.2 and

Section 10.3

Parameter

(1)

Sym Characteristic

Min

Typ

Max Units Conditions

No.

40

Tt0H T0CKI High Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

—

ns

41

42

Tt0L T0CKI Low Pulse Width - No Prescaler

- With Prescaler

0.5 TCY + 20*

10*

Tt0P T0CKI Period

20 or TCY + 40*

N

ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

*

These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25˚C unless otherwise stated. These parameters are for design guidance

only and are not tested.

1995 Microchip Technology Inc.

DS30015M-page 69

PIC16C5X

PIC16C54/55/56/57

NOTES:

DS30015M-page 70

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

11.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some

graphs or tables the data presented are outside speciﬁed operating range (e.g., outside speciﬁed VDD range). This is

for information only and devices will operate properly only within the speciﬁed range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectively, where σ is standard deviation.

FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs.TEMPERATURE

FOSC

Frequency normalized to +25°C

FOSC (25°C)

1.10

Rext ≥ 10 kΩ

Cext = 100 pF

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

VDD = 5.5 V

VDD = 3.5 V

0.92

0.90

0.88

0

10

20

25

30

40

50

60

70

T(°C)

TABLE 11-1: RC OSCILLATOR FREQUENCIES

Average

Fosc @ 5 V, 25°C

Cext

Rext

20 pF

3.3 k

5 k

4.973 MHz

3.82 MHz

2.22 MHz

262.15 kHz

1.63 MHz

1.19 MHz

684.64 kHz

71.56 kHz

660 kHz

± 27%

± 21%

± 31%

± 13%

± 18%

± 25%

± 10%

± 14%

± 15%

± 19%

10 k

100 k

3.3 k

5 k

100 pF

300 pF

10 k

100 k

3.3 k

5.0 k

10 k

160 k

484.1 kHz

267.63 kHz

29.44 kHz

The frequencies are measured on DIP packages.

The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviation from average value for VDD = 5 V.

1995 Microchip Technology Inc.

DS30015M-page 71

This document was created with FrameMaker 4 0 4

PIC16C5X

PIC16C54/55/56/57

FIGURE 11-2: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

FIGURE 11-3: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

CEXT = 20PF

CEXT = 100 PF

5.5

1.8

R = 3.3k

5.0

1.6

4.5

1.4

R = 5k

4.0

1.2

1.0

3.5

3.0

0.8

R = 10k

2.5

0.6

Measured on DIP Packages, T = 25°C

2.0

0.4

Measured on DIP Packages, T = 25°C

0.2

1.5

R = 100k

0.0

1.0

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

R = 100k

0.5

FIGURE 11-4: TYPICAL RC OSCILLATOR

FREQUENCY vs. VDD,

0.0

CEXT = 300 PF

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

800

700

R = 3.3k

600

R = 5k

500

400

300

200

100

0

R = 10k

Measured on DIP Packages, T = 25°C

R = 100k

5.5 6.0

3.0

3.5

4.0

4.5

5.0

VDD (Volts)

DS30015M-page 72

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 11-5: TYPICAL IPD vs. VDD,

FIGURE 11-7: TYPICAL IPD vs. VDD,

WATCHDOG DISABLED

WATCHDOG ENABLED

2.5

2.0

1.5

20

18

16

14

12

T = 25°C

10

8

1.0

0.5

0.0

6

4

2

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

VDD (Volts)

FIGURE 11-6: MAXIMUM IPD vs. VDD,

WATCHDOG DISABLED

FIGURE 11-8: MAXIMUM IPD vs. VDD,

WATCHDOG ENABLED

60

100

50

+125˚C

+85˚C

10

40

–55°C

+70˚C

0˚C

+85°C

30

–40˚C

+125°C

–40°C

+70°C

–55˚C

1

20

10

0

0°C

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

VDD (Volts)

IPD, with WDT enabled, has two components:

The leakage current which increases with higher temperature

and the operating current of the WDT logic which increases

with lower temperature. At –40°C, the latter dominates

explaining the apparently anomalous behavior.

1995 Microchip Technology Inc.

DS30015M-page 73

PIC16C5X

PIC16C54/55/56/57

FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

FIGURE 11-10: VIH, VIL OF MCLR,T0CKI AND OSC1 (IN RC MODE) vs. VDD

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.5

3.0

3.5

4.0

4.5

VDD (Volts)

5.0

5.5

6.0

Note: These input pins have Schmitt Trigger input buffers.

FIGURE 11-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD

3.4

3.2

3.0

2.8

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (Volts)

DS30015M-page 74

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25°C)

10

1.0

0.1

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 11-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)

10

1.0

7.0

6.5

6.0

0.1

5.5

5.0

4.5

4.0

3.5

3.0

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

1995 Microchip Technology Inc.

DS30015M-page 75

PIC16C5X

PIC16C54/55/56/57

FIGURE 11-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55°C TO +125°C)

10

1.0

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

0.1

2.5

0.01

10k

100k

1M

10M

100M

External Clock Frequency (Hz)

FIGURE 11-15: WDT TIMER TIME-OUT

PERIOD vs. VDD

FIGURE 11-16: TRANSCONDUCTANCE (gm)

OF HS OSCILLATOR vs. VDD

50

45

40

9000

8000

Max –40°C

7000

6000

35

30

5000

Max +85°C

Typ +25°C

25

4000

3000

Max +70°C

20

Typ +25°C

Min +85°C

15

2000

MIn 0°C

10

100

0

MIn –40°C

5

2

3

4

5

6

7

2

3

4

5

6

7

VDD (Volts)

DS30015M-page 76

1995 Microchip Technology Inc.

PIC16C54/55/56/57

PIC16C5X

FIGURE 11-17: TRANSCONDUCTANCE (gm)

OF LP OSCILLATOR vs. VDD

FIGURE 11-19: TRANSCONDUCTANCE (gm)

OF XT OSCILLATOR vs. VDD

45

2500

40

Max –40°C

2000

35

30

1500

25

Typ +25°C

20

1000

15

Min +85°C

500

10

Min +85°C

5

0

2

3

4

5

6

7

2

3

4

5

6

7

VDD (Volts)

FIGURE 11-18: IOH vs. VOH, VDD = 3 V

FIGURE 11-20: IOH vs. VOH, VDD = 5 V

0

Min +85°C

–5

–10

Min +85°C

–10

–20

Typ +25°C

–15

Max –40°C

–30

Max –40°C

–20

–40

–25

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0

0.5 1.0 1.5 2.0 2.5 3.0

VOH (Volts)

1995 Microchip Technology Inc.

DS30015M-page 77

PIC16C5X

PIC16C54/55/56/57

FIGURE 11-21: IOL vs. VOL, VDD = 3 V

FIGURE 11-22: IOL vs. VOL, VDD = 5 V

90

80

70

45

Max –40°C

40

35

60

50

30

25

Typ +25°C

Min +85°C

40

20

Min +85°C

30

20

15

10

0

5

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0.0

0.5 1.0 1.5 2.0 2.5 3.0

VOL (Volts)

TABLE 11-2: INPUT CAPACITANCE FOR

PIC16C54/56

TABLE 11-3: INPUT CAPACITANCE FOR

PIC16C55/57

Typical Capacitance (pF)

18L PDIP

18L SOIC

28L PDIP

(600 mil)

28L SOIC

RA port

RB port

5.0

4.3

RA port

RB port

5.2

5.6

5.0

17.0

6.6

4.6

4.5

4.8

4.7

4.1

17.0

3.5

5.0

4.3

MCLR

17.0

4.0

17.0

3.5

RC port

OSC1

MCLR

OSC2/CLKOUT

T0CKI

4.3

3.5

OSC1

3.2

2.8

OSC2/CLKOUT

T0CKI

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

All capacitance values are typical at 25°C. A part-to-part

variation of ±25% (three standard deviations) should be

taken into account.

DS30015M-page 78

1995 Microchip Technology Inc.

PIC16CR54

PIC16C5X

12.0 ELECTRICAL CHARACTERISTICS - PIC16CR54

Absolute Maximum Ratings†

Ambient Temperature under bias...........................................................................................................–55°C to +125°C

Storage Temperature .............................................................................................................................–65°C to +150°C

Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V

(2)

Voltage on MCLR with respect to VSS .........................................................................................................0 to +14.0V

Voltage on all other pins with respect to VSS ................................................................................ –0.6 V to (VDD + 0.6V)