PIC16F1517 [MICROCHIP]
28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology; 28 /40/ 44引脚闪存单片机采用纳瓦XLP技术型号: | PIC16F1517 |
厂家: | MICROCHIP |
描述: | 28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology |
文件: | 总344页 (文件大小:2990K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16(L)F1516/7/8/9
Data Sheet
28/40/44-Pin Flash Microcontrollers
with nanoWatt XLP Technology
2011 Microchip Technology Inc.
Preliminary
DS41452B
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-134-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS41452B-page 2
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
28/40/44-Pin Flash Microcontrollers with nanoWatt XLP Technology
Devices Included In This Data Sheet:
Extreme Low-Power Management
PIC16LF151X with nanoWatt XLP:
PIC16F151X and PIC16LF151X Devices:
• Sleep mode: 20 nA @ 1.8V, typical
• Watchdog Timer: 300 nA @ 1.8V, typical
• Secondary Oscillator: 600 nA @ 32 kHz
• PIC16F1516
• PIC16F1517
• PIC16F1518
• PIC16F1519
• PIC16LF1516
• PIC16LF1517
• PIC16LF1518
• PIC16LF1519
Special Microcontroller Features:
• Operating Voltage Range:
- 2.3V-5.5V (PIC16F151X)
High-Performance RISC CPU:
• C Compiler Optimized Architecture
• Only 49 Instructions
• Up to 28 Kbytes Linear Program Memory
Addressing
• Up to 1024 Bytes Linear Data Memory
Addressing
- 1.8V-3.6V (PIC16LF151X)
• Self-Programmable under Software Control
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Programmable Low-Power Brown-out Reset
(LPBOR)
• Extended Watchdog Timer (WDT)
• In-Circuit Serial Programming™ (ICSP™) via
two pins
• In-Circuit Debug (ICD) via two pins
• Enhanced Low-Voltage Programming (LVP)
• Programmable Code Protection
• Low-Power Sleep Mode
• Operating Speed:
- DC – 20 MHz clock input @ 2.5V
- DC – 16 MHz clock input @ 1.8V
- DC – 200 ns instruction cycle
• Interrupt Capability with Automatic Context
Saving
• 16-Level Deep Hardware Stack with Optional
Overflow/Underflow Reset
• Low-Power BOR (LPBOR)
• Direct, Indirect and Relative Addressing modes:
- Two full 16-bit File Select Registers (FSRs)
- FSRs can read program and data memory
Peripheral Highlights:
• Up to 35 I/O pins and 1 input only pin:
- High current sink/source 25 mA/25 mA
- Individually programmable weak pull-ups
- Individually programmable inter-
rupt-on-change (IOC) pins
• Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler
• Enhanced Timer1:
- 16-bit timer/counter with prescaler
- External Gate Input mode
- Low-power 32 kHz secondary oscillator driver
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two Capture/Compare (CCP) modules:
• Master Synchronous Serial Port (MSSP) with SPI
and I2CTM with:
Flexible Oscillator Structure:
• 16 MHz Internal Oscillator Block:
- Software selectable frequency range from
16 MHz to 31 kHz
• 31 kHz Low-Power Internal Oscillator
• External Oscillator Block with:
- Four crystal/resonator modes up to 20 MHz
- Three external clock modes up to 20 MHz
• Fail-Safe Clock Monitor
- Allows for safe shutdown if peripheral clock
stops
• Two-Speed Oscillator Start-up
• Oscillator Start-up Timer (OST)
- 7-bit address masking
- SMBus/PMBusTM compatibility
Analog Features:
• Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module:
- RS-232, RS-485 and LIN compatible
- Auto-Baud Detect
• Analog-to-Digital Converter (ADC):
- 10-bit resolution
- Up to 28 channels
- Auto acquisition capability
- Conversion available during Sleep
• Voltage Reference module:
- Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V output levels
• Temperature Indicator
- Auto-wake-up on start
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 3
PIC16(L)F1516/7/8/9
PIC16(L)F151X Family
Program
SRAM
10-bitA/D Timers
MSSP
Device
Memory Flash
(words)
I/Os
EUSART
CCP
(bytes)
(ch)
8/16-bit
(I2C™/SPI)
PIC16F1516
PIC16LF1516
8192
8192
512
512
25
36
25
36
17
28
17
28
2/1
2/1
2/1
2/1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2
2
2
2
PIC16F1517
PIC16LF1517
PIC16F1518
PIC16LF1518
16384
16384
1024
1024
PIC16F1519
PIC16LF1519
FIGURE 1:
28-PIN SPDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16F1516/1518 AND
PIC16LF1516/1518
28-Pin SPDIP, SOIC, SSOP
RB7/ICSPDAT/ICDDAT
RB6/ICSPCLK/ICDCLK
RB5/AN13/T1G
28
27
26
25
24
23
1
2
3
4
5
6
VPP/MCLR/RE3
SS(2)/AN0/RA0
AN1/RA1
RB4/AN11
RB3/AN9/CCP2(2)
AN2/RA2
VREF+/AN3/RA3
T0CKI/RA4
RB2/AN8
VCAP/SS(1)/AN4/RA5
VSS
RB1/AN10
22
21
7
8
9
RB0/AN12/INT
VDD
20
19
18
17
16
15
CLKIN/OSC1/RA7
VSS
10
11
CLKOUT/OSC2/RA6
T1CKI/SOSCO/RC0
RC7/AN19/RX/DT
RC6/AN18/TX/CK
RC5/AN17/SDO
RC4/AN16/SDI/SDA
CCP2(1)/SOSCI/RC1
CCP1/AN14/RC2
12
13
14
SCL/SCK/AN15/RC3
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
DS41452B-page 4
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 2:
28-PIN UQFN (4X4) PACKAGE DIAGRAM FOR PIC16F1516/1518 AND
PIC16LF1516/1518
28-Pin UQFN
RB3/AN9/CCP2(2)
RB2/AN8
RB1/AN10
RB0/AN12/INT
VDD
1
2
3
4
5
6
7
21
20
19
18
17
16
15
AN2/RA2
VREF+/AN3/RA3
T0CKI/RA4
PIC16F1516/1518
PIC16LF1516/1518
VCAP/SS(1)/AN4/RA5
VSS
CLKIN/OSC1/RA7
CLKOUT/OSC2/RA6
VSS
RC7/AN19/RX/DT
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 5
PIC16(L)F1516/7/8/9
FIGURE 3:
40-PIN PDIP PACKAGE DIAGRAM FOR PIC16F1517/1519 AND PIC16LF1517/1519
40-Pin PDIP
RB7/ICSPDAT/ICDDAT
RB6/ICSPCLK/ICDCLK
RB5/AN13/T1G
40
39
38
37
36
35
1
2
3
4
5
6
VPP/MCLR/RE3
SS(2)/AN0/RA0
AN1/RA1
RB4/AN11
AN2/RA2
RB3/AN9/CCP2(2)
VREF+/AN3/RA3
T0CKI/RA4
RB2/AN8
VCAP/SS(1)/AN4/RA5
34
33
32
RB1/AN10
7
8
9
RB0/AN12/INT
AN5/RE0
VDD
AN6/RE1
AN7/RE2
VDD
VSS
31
30
10
11
RD7/AN27
RD6/AN26
VSS
29
12
RD5/AN25
CLKIN/OSC1/RA7
28
27
26
25
13
14
15
16
RD4/AN24
CLKOUT/OSC2/RA6
T1CKI/SOSCO/RC0
CCP2(1)/SOSCI/RC1
RC7/AN19/RX/DT
RC6/AN18/TX/CK
RC5/AN17/SDO
RC4/AN16/SDI/SDA
RD3/AN23
24
23
CCP1/AN14/RC2
17
18
SCL/SCK/AN15/RC3
AN20/RD0
AN21/RD1
22
21
19
20
RD2/AN22
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
DS41452B-page 6
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 4:
40-PIN UQFN (5X5) PACKAGE DIAGRAM FOR PIC16F1517/1519 AND
PIC16LF1517/1519
40-Pin UQFN
RC0/SOSCO/T1CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
30
29
28
27
26
25
24
23
22
21
DT/RX/AN19/RC7
1
2
3
4
5
6
7
8
9
10
AN24/RD4
AN25/RD5
AN26/RD6
AN27/RD7
VSS
PIC16F1517/1519
PIC16LF1517/1519
RE1/AN6
VDD
RE0/AN5
INT/AN12/RB0
AN10/RB1
AN8/RB2
RA5/AN4/SS(1)/VCAP
RA4/TOCKI
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 7
PIC16(L)F1516/7/8/9
FIGURE 5:
44-PIN TQFP PACKAGE DIAGRAM FOR PIC16F1517/1519 AND PIC16LF1517/1519
44-Pin TQFP
DT/RX/AN19/RC7
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RC0/SOSCO/T1CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
VSS
VDD
RE2/AN7
RE1/AN6
RE0/AN5
AN24/RD4
AN25/RD5
AN26/RD6
AN27/RD7
PIC16F1517/1519
PIC16LF1517/1519
VSS
VDD
INT/AN12/RB0
AN10/RB1
AN8/RB2
(1)
RA5/AN4/SS /VCAP
RA4/T0CKI
(2)
CCP2 /AN9/RB3
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
DS41452B-page 8
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 1:
28/40/44-PIN ALLOCATION TABLE (PIC16(L)F151X)
(2)
RA0
RA1
RA2
RA3
RA4
RA5
2
3
4
5
6
7
27
28
1
2
3
4
5
6
7
17 19
18 20
19 21
AN0
AN1
AN2
—
—
—
—
—
SS
—
—
—
—
—
—
—
—
—
—
Y
—
—
—
—
—
—
—
—
—
—
—
—
2
20 22 AN3/VREF+
—
—
—
—
—
3
21 23
22 24
—
T0CKI
—
—
—
—
(1)
4
AN4
—
—
—
—
SS
—
VCAP
RA6 10
RA7
7
14 29 31
13 28 30
—
—
—
—
—
—
OSC2/CLKOUT
9
6
—
—
—
—
—
OSC1/CLKIN
RB0 21 18 33
RB1 22 19 34
8
9
8
9
AN12
AN10
AN8
AN9
AN11
AN13
—
—
—
—
—
INT/IOC
IOC
IOC
IOC
IOC
IOC
IOC
IOC
—
—
—
—
—
—
Y
—
RB2 23 20 35 10 10
RB3 24 21 36 11 11
RB4 25 22 37 12 14
RB5 26 23 38 13 15
RB6 27 24 39 14 16
RB7 28 25 40 15 17
—
—
—
—
Y
—
(2)
—
CCP2
—
—
—
Y
—
—
—
—
Y
—
T1G
—
—
—
Y
—
—
—
—
—
Y
ICSPCLK/ICDCLK
—
—
—
—
—
Y
ICSPDAT/ICDDAT
RC0 11
RC1 12
8
9
15 30 32
16 31 35
—
SOSCO/T1CKI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Y
—
(1)
—
SOSCI
—
CCP2
—
—
—
—
RC2 13 10 17 32 36
RC3 14 11 18 33 37
RC4 15 12 23 38 42
RC5 16 13 24 39 43
RC6 17 14 25 40 44
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN5
AN6
AN7
—
CCP1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCK/SCL
SDI/SDA
SDO
—
—
—
—
—
—
—
—
—
—
—
—
TX/CK
RX/DT
—
—
—
RC7 18 15 26
1
1
—
—
—
—
(3)
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
—
—
—
—
—
—
—
—
—
—
—
1
—
—
—
—
—
—
—
—
—
—
—
26
19 34 38
20 35 39
21 36 40
22 37 41
—
—
—
—
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27
28
29
30
8
2
3
4
5
2
3
4
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
23 25
24 26
—
—
—
—
—
9
—
—
—
—
—
10 25 27
16 18
—
—
—
—
—
MCLR/VPP
—
RE3
VDD
1
—
—
—
—
20 17 11, 7, 7,
32 26 28
—
—
—
—
—
—
VSS
NC
8, 5, 12, 6, 6,
19 16 31 27 29
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
12,
13,
33,
34
Note 1: Peripheral pin location selected using APFCON register. Default location.
2: Peripheral pin location selected using APFCON register. Alternate location.
3: PIC16(L)F1517/9 only.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 9
PIC16(L)F1516/7/8/9
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Enhanced Mid-range CPU ......................................................................................................................................................... 19
3.0 Memory Organization................................................................................................................................................................. 21
4.0 Device Configuration .................................................................................................................................................................. 45
5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 51
6.0 Resets ........................................................................................................................................................................................ 67
7.0 Interrupts .................................................................................................................................................................................... 75
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 87
9.0 Low Dropout (LDO) Voltage Regulator ...................................................................................................................................... 91
10.0 Watchdog Timer (WDT) ............................................................................................................................................................. 93
11.0 Flash Program Memory Control ................................................................................................................................................. 97
12.0 I/O Ports ................................................................................................................................................................................... 113
13.0 Interrupt-on-Change................................................................................................................................................................. 133
14.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 137
15.0 Temperature Indicator Module ................................................................................................................................................. 139
16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 141
17.0 Timer0 Module ......................................................................................................................................................................... 155
18.0 Timer1 Module ......................................................................................................................................................................... 159
19.0 Timer2 Modules........................................................................................................................................................................ 171
20.0 Capture/Compare/PWM Module .............................................................................................................................................. 175
21.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 185
22.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)............................................................... 237
23.0 In-Circuit Serial Programming™ (ICSP™) ................................................................................................................................ 265
24.0 Instruction Set Summary.......................................................................................................................................................... 269
25.0 Electrical Specifications............................................................................................................................................................ 283
26.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 311
27.0 Development Support............................................................................................................................................................... 313
28.0 Packaging Information.............................................................................................................................................................. 317
Appendix A: Revision History............................................................................................................................................................. 333
Index .................................................................................................................................................................................................. 335
The Microchip Web Site..................................................................................................................................................................... 341
Customer Change Notification Service .............................................................................................................................................. 341
Customer Support.............................................................................................................................................................................. 341
Reader Response .............................................................................................................................................................................. 342
Product Identification System............................................................................................................................................................. 343
DS41452B-page 10
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TO OUR VALUED CUSTOMERS
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2011 Microchip Technology Inc.
Preliminary
DS41452B-page 11
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 12
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
1.0
DEVICE OVERVIEW
The PIC16(L)F151X are described within this data sheet.
They are available in 8-pin packages. Figure 1-1 shows a
block diagram of the PIC16(L)F151X devices. Table 1-2
shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
TABLE 1-1:
DEVICE PERIPHERAL
SUMMARY
Peripheral
Analog-to-Digital Converter (ADC)
●
●
●
●
●
●
●
●
●
●
●
●
Fixed Voltage Reference (FVR)
Temperature Indicator
Capture/Compare/PWM Modules
CCP1
●
●
●
●
●
●
●
●
CCP2
EUSARTs
EUSART
●
●
●
●
●
●
●
●
Master Synchronous Serial Ports
MSSP
Timers
Timer0
Timer1
Timer2
●
●
●
●
●
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2011 Microchip Technology Inc.
Preliminary
DS41452B-page 13
PIC16(L)F1516/7/8/9
FIGURE 1-1:
PIC16(L)F151X BLOCK DIAGRAM
Program
Flash Memory
PORTA
PORTB
RAM
OSC2/CLKOUT
OSC1/CLKIN
Timing
Generation
CPU
INTRC
Oscillator
PORTC
(Figure 2-1)
PORTD(3)
MCLR
PORTE(4)
Temp.
Indicator
ADC
10-Bit
CCP1
CCP2
Timer0
MSSP
FVR
EUSART
Timer1
Timer2
Note 1:
See applicable chapters for more information on peripherals.
See Table 1-1 for peripherals available on specific devices.
PIC16(L)F1517/9 only.
2:
3:
4:
RE<2:0>, PIC16(L)F1517/9 only.
DS41452B-page 14
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 1-2:
PIC16(L)F151X PINOUT DESCRIPTION
Input Output
Function
Name
Description
Type
Type
(2)
RA0/AN0/SS
RA0
AN0
TTL
AN
ST
CMOS General purpose I/O.
—
—
A/D Channel 0 input.
Slave Select input.
SS
RA1/AN1
RA2/AN2
RA1
TTL
AN
TTL
AN
TTL
AN
AN
TTL
ST
CMOS General purpose I/O.
A/D Channel 1 input.
CMOS General purpose I/O.
A/D Channel 2 input.
CMOS General purpose I/O.
AN1
—
RA2
AN2
—
RA3/AN3/VREF+
RA4/T0CKI
RA3
AN3
—
—
A/D Channel 3 input.
VREF+
RA4
A/D Positive Voltage Reference input.
CMOS General purpose I/O.
Timer0 clock input.
CMOS General purpose I/O.
T0CKI
RA5
—
(1)
TTL
AN
ST
RA5/AN4/SS /VCAP
AN4
—
—
A/D Channel 4 input.
Slave Select input.
SS
VCAP
RA6
Power Power Filter capacitor for Voltage Regulator (PIC16F151X only).
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
RB0/AN12/INT
TTL
—
CMOS General purpose I/O.
XTAL Crystal/Resonator (LP, XT, HS modes).
CMOS FOSC/4 output.
OSC2
CLKOUT
RA7
—
TTL
XTAL
ST
CMOS General purpose I/O.
OSC1
CLKIN
RB0
—
—
Crystal/Resonator (LP, XT, HS modes).
External clock input (EC mode).
TTL
AN
CMOS General purpose I/O with IOC and WPU.
AN12
INT
—
—
A/D Channel 12 input.
External interrupt.
ST
RB1/AN10
RB2/AN8
RB1
TTL
AN
CMOS General purpose I/O with IOC and WPU.
A/D Channel 10 input.
CMOS General purpose I/O with IOC and WPU.
A/D Channel 8 input.
CMOS General purpose I/O with IOC and WPU.
A/D Channel 9 input.
AN10
RB2
—
TTL
AN
AN8
—
(2)
RB3/AN9/CCP2
RB3
TTL
AN
AN9
—
CCP2
RB4
ST
CMOS Capture/Compare/PWM 2.
RB4/AN11
TTL
AN
CMOS General purpose I/O with IOC and WPU.
AN11
RB5
—
A/D Channel 11 input.
RB5/AN13/T1G
TTL
AN
CMOS General purpose I/O with IOC and WPU.
AN13
T1G
—
—
A/D Channel 13 input.
Timer1 Gate input.
ST
RB6/ICSPCLK
RB7/ICSPDAT
RB6
TTL
ST
CMOS General purpose I/O with IOC and WPU.
CMOS In-Circuit Data I/O.
ICSPCLK
RB7
TTL
ST
CMOS General purpose I/O with IOC and WPU.
CMOS ICSP™ Data I/O.
ICSPDAT
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 15
PIC16(L)F1516/7/8/9
TABLE 1-2:
PIC16(L)F151X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
RC0/SOSCO/T1CKI
Function
Description
Type
Type
RC0
SOSCO
T1CKI
RC1
ST
—
CMOS General purpose I/O.
XTAL Secondary oscillator connection.
Timer1 clock input.
ST
ST
—
—
(1)
RC1/SOSCI/CCP2
CMOS General purpose I/O.
SOSCI
CCP2
RC2
XTAL Secondary oscillator connection.
CMOS Capture/Compare/PWM 2.
CMOS General purpose I/O.
ST
ST
AN
ST
ST
AN
ST
RC2/AN14/CCP1
AN14
CCP1
RC3
—
A/D Channel 14 input.
CMOS Capture/Compare/PWM 1.
CMOS General purpose I/O.
RC3/AN15/SCK/SCL
RC4/AN16/SDI/SDA
AN15
SCK
SCL
—
A/D Channel 15 input.
CMOS SPI clock.
2
2
I C™
OD
I C™ clock.
RC4
ST
AN
ST
CMOS General purpose I/O.
AN16
SDI
—
—
A/D Channel 16 input.
SPI data input.
2
2
SDA
RC5
I C™
OD
I C™ data input/output.
RC5/AN17/SDO
ST
AN
—
CMOS General purpose I/O.
A/D Channel 17 input.
AN17
SDO
RC6
—
CMOS SPI data output.
ST
AN
—
CMOS General purpose I/O.
RC6/AN18/TX/CK
AN18
TX
—
A/D Channel 18 input.
CMOS USART asynchronous transmit.
CMOS USART synchronous clock.
CMOS General purpose I/O.
CK
ST
ST
AN
ST
ST
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
ST
AN
RC7
RC7/AN19/RX/DT
AN19
RX
—
—
A/D Channel 19 input.
USART asynchronous input.
DT
CMOS USART synchronous data.
CMOS General purpose I/O.
(3)
RD0 /AN20
RD0
AN20
RD1
—
A/D Channel 20 input.
CMOS General purpose I/O.
A/D Channel 21 input.
CMOS General purpose I/O.
A/D Channel 22 input.
CMOS General purpose I/O.
A/D Channel 23 input.
CMOS General purpose I/O.
A/D Channel 24 input.
CMOS General purpose I/O.
A/D Channel 25 input.
CMOS General purpose I/O.
A/D Channel 26 input.
(3)
RD1 /AN21
AN21
RD2
—
(3)
RD2 /AN22
AN22
RD3
—
(3)
RD3 /AN23
AN23
RD4
—
(3)
RD4 /AN24
AN24
RD5
—
(3)
RD5 /AN25
AN25
RD6
—
(3)
RD6 /AN26
AN26
—
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
DS41452B-page 16
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 1-2:
PIC16(L)F151X PINOUT DESCRIPTION (CONTINUED)
Input Output
Name
Function
Description
Type
Type
(3)
RD7 /AN27
RD7
AN27
RE0
AN5
RE1
AN6
RE2
AN7
RE3
MCLR
VPP
ST
AN
CMOS General purpose I/O.
—
A/D Channel 27 input.
CMOS General purpose I/O.
A/D Channel 5 input.
CMOS General purpose I/O.
A/D Channel 6 input.
CMOS General purpose I/O.
(3)
RE0 /AN5
ST
AN
—
(3)
RE1 /AN6
ST
AN
—
(3)
RE2 /AN7
ST
AN
—
—
—
—
—
—
A/D Channel 7 input.
RE3/MCLR/VPP
ST
General purpose input with WPU.
Master Clear with internal pull-up.
Programming voltage.
ST
HV
VDD
VSS
VDD
Power
Power
Positive supply.
VSS
Ground reference.
Legend: AN = Analog input or output CMOS= CMOS compatible input or output
OD = Open Drain
2
2
TTL = TTL compatible input ST
HV = High Voltage
= Schmitt Trigger input with CMOS levels I C™ = Schmitt Trigger input with I C
levels
XTAL = Crystal
Note 1: Peripheral pin location selected using APFCON register (Register 12-1). Default location.
2: Peripheral pin location selected using APFCON register (Register 12-1). Alternate location.
3: PORTD and RE<2:0> available on PIC16(L)F1517/9 only.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 17
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 18
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
2.0
ENHANCED MID-RANGE CPU
This family of devices contain an enhanced mid-range
8-bit CPU core. The CPU has 49 instructions. Interrupt
capability includes automatic 2011context saving. The
hardware stack is 16 levels deep and has Overflow and
Underflow Reset capability. Direct, Indirect, and
Relative Addressing modes are available. Two File
Select Registers (FSRs) provide the ability to read
program and data memory.
• Automatic Interrupt Context Saving
• 16-level Stack with Overflow and Underflow
• File Select Registers
• Instruction Set
2.1
Automatic Interrupt Context
Saving
During interrupts, certain registers are automatically
saved in shadow registers and restored when returning
from the interrupt. This saves stack space and user
code. See Section 7.5 “Automatic Context Saving”,
for more information.
2.2
16-Level Stack with Overflow and
Underflow
These devices have an external stack memory 15 bits
wide and 16 words deep. A Stack Overflow or Under-
flow will set the appropriate bit (STKOVF or STKUNF)
in the PCON register, and if enabled will cause a soft-
ware Reset. See Section 3.4 “Stack” for more details.
2.3
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs
can access all file registers and program memory,
which allows one Data Pointer for all memory. When an
FSR points to program memory, there is 1 additional
instruction cycle in instructions using INDF to allow the
data to be fetched. General purpose memory can now
also be addressed linearly, providing the ability to
access contiguous data larger than 80 bytes. There are
also new instructions to support the FSRs. See
Section 3.5 “Indirect Addressing” for more details.
2.4
Instruction Set
There are 49 instructions for the enhanced mid-range
CPU to support the features of the CPU. See
Section 24.0 “Instruction Set Summary” for more
details.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 19
PIC16(L)F1516/7/8/9
FIGURE 2-1:
CORE BLOCK DIAGRAM
15
Configuration
15
8
Data Bus
RAM
Program Counter
Flash
Program
Memory
16-LevelStack
(15-bit)
Program
Bus
14
RAM Addr
Program Memory
Read (PMR)
12
Addr MUX
InstructionReg
Indirect
Addr
7
Direct Addr
12
12
5
BSR Reg
15
FSR0 Reg
FSR1 Reg
15
STATUSReg
8
3
MUX
Power-up
Timer
Oscillator
Instruction
Decodeand
Control
Start-up Timer
ALU
Power-on
Reset
OSC1/CLKIN
8
Timing
Generation
Watchdog
Timer
W Reg
OSC2/CLKOUT
Brown-out
Reset
Internal
Oscillator
Block
VDD
VSS
DS41452B-page 20
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.1
Program Memory Organization
3.0
MEMORY ORGANIZATION
The enhanced mid-range core has a 15-bit program
counter capable of addressing a 32K x 14 program
memory space. Table 3-1 shows the memory sizes
implemented for these devices. Accessing a location
above these boundaries will cause a wrap-around within
the implemented memory space. The Reset vector is at
0000h and the interrupt vector is at 0004h (see
Figure 3-1 and Figure 3-2).
These devices contain the following types of memory:
• Program Memory
- Configuration Words
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
TABLE 3-1:
DEVICE SIZES AND ADDRESSES
Device
Program Memory Space (Words)
Last Program Memory Address
PIC16F1516
PIC16LF1516
8,192
1FFFh
PIC16F1517
PIC16LF1517
PIC16F1518
PIC16LF1518
16,384
3FFFh
PIC16F1519
PIC16LF1519
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 21
PIC16(L)F1516/7/8/9
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR
FIGURE 3-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16(L)F1516/7
PIC16(L)F1518/9
PC<14:0>
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
Stack Level 15
Reset Vector
0000h
0000h
Interrupt Vector
Page 0
0004h
0005h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
07FFh
0800h
Page 1
Page 2
Page 1
Page 2
On-chip
Program
Memory
0FFFh
1000h
0FFFh
1000h
On-chip
Program
Memory
17FFh
1800h
17FFh
1800h
Page 3
Page 3
Page 4
1FFFh
2000h
1FFFh
2000h
Rollover to Page 0
Page 7
3FFFh
4000h
Rollover to Page 0
Rollover to Page 3
Rollover to Page 7
7FFFh
7FFFh
DS41452B-page 22
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.1.1
READING PROGRAM MEMORY AS
DATA
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
There are two methods of accessing constants in pro-
gram memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
my_function
;Index0 data
;Index1 data
3.1.1.1
RETLWInstruction
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
LOW constants
FSR1L
HIGH constants
FSR1H
The RETLWinstruction can be used to provide access
to tables of constants. The recommended way to create
such a table is shown in Example 3-1.
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
EXAMPLE 3-1:
RETLW INSTRUCTION
constants
BRW
;Add Index in W to
;program counter to
;select data
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW DATA_INDEX
CALL constants
;… THE CONSTANT IS IN W
The BRWinstruction makes this type of table very sim-
ple to implement. If your code must remain portable
with previous generations of microcontrollers, then the
BRWinstruction is not available so the older table read
method must be used.
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIWinstruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 23
PIC16(L)F1516/7/8/9
3.2.1
CORE REGISTERS
3.2
Data Memory Organization
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-7.
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure 3-3):
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
TABLE 3-2:
CORE REGISTERS
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers (FSR). See Section 3.5 “Indirect
Addressing” for more information.
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
Data Memory uses a 12-bit address. The upper 7-bit of
the address define the Bank address and the lower
5-bits select the registers/RAM in that bank.
WREG
PCLATH
INTCON
x0Ah or x8Ah
x0Bh or x8Bh
DS41452B-page 24
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u= unchanged).
3.2.1.1
STATUS Register
The STATUS register, shown in Register 3-1, contains:
• the arithmetic status of the ALU
• the Reset status
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not
affecting any Status bits (Refer to Section 24.0
“Instruction Set Summary”).
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as Borrow
and Digit Borrow out bits, respectively, in
subtraction.
REGISTER 3-1:
STATUS: STATUS REGISTER
U-0
—
U-0
—
U-0
—
R-1/q
TO
R-1/q
PD
R/W-0/u
Z
R/W-0/u
DC(1)
R/W-0/u
C(1)
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7-5
bit 4
Unimplemented: Read as ‘0’
TO: Time-out bit
1= After power-up, CLRWDTinstruction or SLEEPinstruction
0= A WDT time-out occurred
bit 3
bit 2
bit 1
bit 0
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit Carry/Digit Borrow bit(1)
1= A carry-out from the 4th low-order bit of the result occurred
0= No carry-out from the 4th low-order bit of the result
C: Carry/Borrow bit(1)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 25
PIC16(L)F1516/7/8/9
3.2.2
SPECIAL FUNCTION REGISTER
FIGURE 3-3:
BANKED MEMORY
PARTITIONING
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The Special Function
Registers occupy the 20 bytes after the core registers of
every data memory bank (addresses x0Ch/x8Ch
through x1Fh/x9Fh). The registers associated with the
operation of the peripherals are described in the
appropriate peripheral chapter of this data sheet.
Memory Region
7-bit Bank Offset
00h
Core Registers
(12 bytes)
0Bh
0Ch
3.2.3
GENERAL PURPOSE RAM
Special Function Registers
(20 bytes maximum)
There are up to 80 bytes of GPR in each data memory
bank. The Special Function Registers occupy the 20
bytes after the core registers of every data memory
bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).
1Fh
20h
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
“Linear Data Memory” for more information.
General Purpose RAM
(80 bytes maximum)
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
6Fh
70h
Common RAM
(16 bytes)
7Fh
3.2.5
DEVICE MEMORY MAPS
The memory maps for PIC16(L)F1516/7 and
PIC16(L)F1516/7 are as shown in Table 3-3 and
Table 3-4, respectively.
DS41452B-page 26
Preliminary
2011 Microchip Technology Inc.
TABLE 3-3:
PIC16(L)F1516/7 MEMORY MAP
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
080h
100h
180h
200h
280h
300h
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
08Bh
08Ch
08Dh
08Eh
10Bh
10Ch
10Dh
10Eh
18Bh
18Ch
18Dh
18Eh
20Bh
20Ch
20Dh
20Eh
28Bh
28Ch
28Dh
28Eh
30Bh
30Ch
30Dh
30Eh
38Bh
38Ch
38Dh
38Eh
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
LATA
LATB
LATC
ANSELA
ANSELB
ANSELC
—
WPUB
—
—
—
—
—
—
—
—
—
—
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
090h
091h
092h
093h
094h
TRISE
PIE1
PIE2
—
110h
111h
112h
113h
114h
LATE(1)
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON(2)
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
—
CCPR1L
PIR2
—
CCPR1H
—
—
—
CCP1CON
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
095h OPTION_REG 115h
—
—
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
PCON
WDTCON
—
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
BORCON
—
FVRCON
—
CCPR2L
CCPR2H
CCP2CON
—
—
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
RCREG
TXREG
—
—
—
—
—
—
SPBRG
—
—
T2CON
—
—
SPBRGH
RCSTA
—
—
—
APFCON
—
—
—
—
—
TXSTA
—
—
—
01Fh
020h
—
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCON
21Fh
220h
—
29Fh
2A0h
—
31Fh
320h
—
39Fh
3A0h
—
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
16 Bytes
32Fh
330h
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
2:
= Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1517 only.
PIC16F1516/7 only.
TABLE 3-3:
PIC16(L)F1516/7 MEMORY MAP (CONTINUED)
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
400h
480h
500h
580h
600h
680h
700h
780h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
40Bh
40Ch
48Bh
48Ch
50Bh
50Ch
58Bh
58Ch
60Bh
60Ch
68Bh
68Ch
70Bh
70Ch
78Bh
78Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
4FFh
880h
57Fh
900h
47Fh
800h
5FFh
980h
67Fh
A00h
6FFh
A80h
77Fh
B00h
7FFh
B80h
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
80Bh
80Ch
88Bh
88Ch
90Bh
90Ch
98Bh
98Ch
A0Bh
A0Ch
A8Bh
A8Ch
B0Bh
B0Ch
B8Bh
B8Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
9EFh
9F0h
AEFh
AF0h
BEFh
BF0h
86Fh
870h
8EFh
8F0h
96Fh
970h
A6Fh
A70h
B6Fh
B70h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
87Fh
C00h
8FFh
C80h
97Fh
D00h
9FFh
D80h
A7Fh
E00h
AFFh
E80h
B7Fh
F00h
BFFh
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
C0Bh
C0Ch
C8Bh
C8Ch
D0Bh
D0Ch
D8Bh
D8Ch
E0Bh
E0Ch
E8Bh
E8Ch
F0Bh
F0Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
C6Fh
C70h
CEFh
CF0h
D6Fh
D70h
DEFh
DF0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
CFFh
D7Fh
DFFh
E7Fh
EFFh
F7Fh
C7Fh
Legend:
= Unimplemented data memory locations, read as ‘0’.
TABLE 3-3:
PIC16(L)F1516/7 MEMORY MAP (CONTINUED)
Bank 31
F80h
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
FEFh
FF0h
TOSH
Common RAM
(Accesses
70h – 7Fh)
FFFh
= Unimplemented data memory locations, read as ‘0’,
TABLE 3-4:
PIC16(L)F1518/9 MEMORY MAP
BANK 0
BANK 1
BANK 2
BANK 3
BANK 4
BANK 5
BANK 6
BANK 7
000h
080h
100h
180h
200h
280h
300h
380h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
08Bh
08Ch
08Dh
08Eh
10Bh
10Ch
10Dh
10Eh
18Bh
18Ch
18Dh
18Eh
20Bh
20Ch
20Dh
20Eh
28Bh
28Ch
28Dh
28Eh
30Bh
30Ch
30Dh
30Eh
38Bh
38Ch
38Dh
38Eh
PORTA
PORTB
PORTC
TRISA
TRISB
TRISC
LATA
LATB
LATC
ANSELA
ANSELB
ANSELC
—
WPUB
—
—
—
—
—
—
—
—
—
—
00Fh
PORTD(1)
08Fh
TRISD(1)
10Fh
LATD(1)
18Fh
ANSELD(1)
20Fh
—
28Fh
—
30Fh
—
38Fh
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
PORTE
PIR1
090h
091h
092h
093h
094h
TRISE
PIE1
PIE2
—
110h
111h
112h
113h
114h
LATE(1)
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
ANSELE(1)
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON(2)
—
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
WPUE
SSPBUF
SSPADD
SSPMSK
SSPSTAT
SSPCON1
SSPCON2
SSPCON3
—
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
—
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
—
—
—
CCPR1L
PIR2
—
CCPR1H
—
—
—
CCP1CON
—
—
—
—
—
IOCBP
IOCBN
IOCBF
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
095h OPTION_REG 115h
—
—
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
PCON
WDTCON
—
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
BORCON
—
FVRCON
—
CCPR2L
CCPR2H
CCP2CON
—
—
—
OSCCON
OSCSTAT
ADRESL
ADRESH
ADCON0
ADCON1
—
RCREG
TXREG
—
—
—
—
—
—
SPBRG
—
—
T2CON
—
—
SPBRGH
RCSTA
—
—
—
APFCON
—
—
—
—
—
TXSTA
—
—
—
01Fh
020h
—
09Fh
0A0h
—
11Fh
120h
—
19Fh
1A0h
BAUDCON
21Fh
220h
—
29Fh
2A0h
—
31Fh
320h
—
39Fh
3A0h
—
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
36Fh
370h
3EFh
3F0h
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
2EFh
2F0h
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Accesses
70h – 7Fh
Common RAM
07Fh
0FFh
17Fh
1FFh
27Fh
2FFh
37Fh
3FFh
Legend:
Note 1:
2:
= Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1519 only.
PIC16F1518/9 only.
TABLE 3-5:
PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
BANK 8
BANK 9
BANK 10
BANK 11
BANK 12
BANK 13
BANK 14
BANK 15
400h
480h
500h
580h
600h
680h
700h
780h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
40Bh
40Ch
48Bh
48Ch
50Bh
50Ch
58Bh
58Ch
60Bh
60Ch
68Bh
68Ch
70Bh
70Ch
78Bh
78Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
41Fh
420h
49Fh
4A0h
51Fh
520h
59Fh
5A0h
61Fh
620h
69Fh
6A0h
71Fh
720h
79Fh
7A0h
General Purpose
Register
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
General
Purpose
Register
80 Bytes
48 Bytes
64Fh
650h
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
46Fh
470h
4EFh
4F0h
56Fh
570h
5EFh
5F0h
66Fh
670h
6EFh
6F0h
76Fh
770h
7EFh
7F0h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
4FFh
880h
57Fh
900h
47Fh
800h
5FFh
980h
67Fh
A00h
6FFh
A80h
77Fh
B00h
7FFh
B80h
BANK 16
BANK 17
BANK 18
BANK 19
BANK 20
BANK 21
BANK 22
BANK 23
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
80Bh
80Ch
88Bh
88Ch
90Bh
90Ch
98Bh
98Ch
A0Bh
A0Ch
A8Bh
A8Ch
B0Bh
B0Ch
B8Bh
B8Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
9EFh
9F0h
AEFh
AF0h
BEFh
BF0h
86Fh
870h
8EFh
8F0h
96Fh
970h
A6Fh
A70h
B6Fh
B70h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
87Fh
8FFh
97Fh
9FFh
A7Fh
AFFh
B7Fh
BFFh
TABLE 3-6:
PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
BANK 24
BANK 25
BANK 26
BANK 27
BANK 28
BANK 29
BANK 30
C00h
C80h
D00h
D80h
E00h
E80h
F00h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
C0Bh
C0Ch
C8Bh
C8Ch
D0Bh
D0Ch
D8Bh
D8Ch
E0Bh
E0Ch
E8Bh
E8Ch
F0Bh
F0Ch
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
Read as ‘0’
C6Fh
C70h
CEFh
CF0h
D6Fh
D70h
DEFh
DF0h
E6Fh
E70h
EEFh
EF0h
F6Fh
F70h
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
Common RAM
(Accesses
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
70h – 7Fh)
CFFh
D7Fh
DFFh
E7Fh
EFFh
F7Fh
C7Fh
F80h
Bank 31
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as ‘0’
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
FEFh
FF0h
TOSH
Common RAM
(Accesses
70h – 7Fh)
FFFh
Legend:
= Unimplemented data memory locations, read as ‘0’.
PIC16(L)F1516/7/8/9
3.2.6
CORE FUNCTION REGISTERS
SUMMARY
The Core Function registers listed in Table 3-7 can be
addressed from any Bank.
TABLE 3-7:
CORE FUNCTION REGISTERS SUMMARY
Value on:
POR, BOR other Resets
Value on all
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0-31
x00h or
x80h
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
INDF0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
---1 1000 ---q quuu
0000 0000 uuuu uuuu
0000 0000 0000 0000
0000 0000 uuuu uuuu
0000 0000 0000 0000
---0 0000 ---0 0000
0000 0000 uuuu uuuu
-000 0000 -000 0000
0000 0000 0000 0000
x01h or
x81h
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
INDF1
PCL
x02h or
x82h
Program Counter (PC) Least Significant Byte
x03h or
x83h
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
—
—
—
TO
PD
Z
DC
C
x04h or
x84h
Indirect Data Memory Address 0 Low Pointer
Indirect Data Memory Address 0 High Pointer
Indirect Data Memory Address 1 Low Pointer
Indirect Data Memory Address 1 High Pointer
x05h or
x85h
x06h or
x86h
x07h or
x87h
x08h or
x88h
—
—
—
BSR4
BSR3
BSR2
BSR1
INTF
BSR0
IOCIF
x09h or
x89h
WREG
PCLATH
INTCON
Working Register
x0Ahor
x8Ah
—
Write Buffer for the upper 7 bits of the Program Counter
PEIE TMR0IE INTE IOCIE TMR0IF
x0Bhor
x8Bh
GIE
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 33
PIC16(L)F1516/7/8/9
3.2.7
SPECIAL FUNCTION REGISTERS
SUMMARY
The Special Function registers are listed in Table 3-8 .
TABLE 3-8: SPECIAL FUNCTION REGISTER SUMMARY
Value on all
other
Resets
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 0
00Ch PORTA
00Dh PORTB
00Eh PORTC
00Fh PORTD
010h PORTE
011h PIR1
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
ADIF
—
—
RCIF
—
—
TXIF
—
RE3
RE2(3)
CCP1IF
—
RE1(3)
TMR2IF
—
RE0(3) ---- xxxx ---- uuuu
TMR1IF 0000 0000 0000 0000
CCP2IF 0--- 0--0 0--- 0--0
TMR1GIF
OSFIF
SSPIF
BCLIF
012h PIR2
013h
014h
—
—
Unimplemented
—
—
—
—
Unimplemented
015h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
016h TMR1L
017h TMR1H
018h T1CON
019h T1GCON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
TMR1CS<1:0>
T1CKPS<1:0>
T1GTM T1GSPM
T1OSCEN T1SYNC
—
TMR1ON 0000 00-0 uuuu uu-u
TMR1GE T1GPOL
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
0000 0x00 uuuu uxuu
01Ah TMR2
01Bh PR2
Timer 2 Module Register
Timer 2 Period Register
—
0000 0000 0000 0000
1111 1111 1111 1111
-000 0000 -000 0000
01Ch T2CON
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
01Dh
01Eh
01Fh
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
Bank 1
08Ch TRISA
08Dh TRISB
08Eh TRISC
08Fh TRISD(2)
090h TRISE
091h PIE1
092h PIE2
PORTA Data Direction Register
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
(3)
—
—
ADIE
—
—
RCIE
—
—
TXIE
—
—
TRISE2(2) TRISE1(2) TRISE0(2) ---- 1111 ---- 1111
TMR1GIE
OSFIE
SSPIE
BCLIE
CCP1IE
—
TMR2IE
—
TMR1IE 0000 0000 0000 0000
CCP2IE 0--- 0--0 0--- 0--0
093h
094h
—
—
Unimplemented
Unimplemented
—
—
—
—
095h OPTION_REG
096h PCON
WPUEN
INTEDG TMR0CS
TMR0SE
RWDT
PSA
RMCLR
PS<2:0>
POR
1111 1111 1111 1111
00-1 11qq qq-q qquu
STKOVF STKUNF
—
RI
BOR
097h WDTCON
—
—
WDTPS<4:0>
SWDTEN --01 0110 --01 0110
098h
—
Unimplemented
—
—
099h OSCCON
IRCF<3:0>
—
—
SCS<1:0>
-011 1-00 -011 1-00
—
09Ah OSCSTAT
09Bh ADRESL
09Ch ADRESH
09Dh ADCON0
09Eh ADCON1
SOSCR
—
OSTS
HFIOFR
—
LFIOFR
HFIOFS 0-q0 --00 q-qq --0q
xxxx xxxx uuuu uuuu
A/D Result Register Low
A/D Result Register High
—
xxxx xxxx uuuu uuuu
CHS<4:0>
GO/DONE
ADON
-000 0000 -000 0000
0000 --00 0000 --00
ADFM
ADCS<2:0>
—
—
ADPREF<1:0>
09Fh
—
Unimplemented
—
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F151X only.
Note 1:
2:
3:
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
DS41452B-page 34
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 2
10Ch LATA
10Dh LATB
10Eh LATC
10Fh LATD(2)
110h LATE(2)
111h
PORTA Data Latch
PORTB Data Latch
PORTC Data Latch
PORTD Data Latch
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
—
—
—
LATE2
LATE1
—
LATE0 ---- -xxx ---- -uuu
to
—
Unimplemented
—
—
115h
116h BORCON
117h FVRCON
118h
SBOREN
FVREN
BORFS
—
—
—
—
—
—
BORRDY 10-- ---q uu-- ---u
0q00 --00 0q00 --00
FVRRDY
TSEN
TSRNG
ADFVR<1:0>
to
—
Unimplemented
—
—
11Ch
11Dh APFCON
—
—
—
—
—
—
SSSEL CCP2SEL ---- --00 ---- --00
11Eh
11Fh
—
—
Unimplemented
Unimplemented
—
—
—
—
Bank 3
18Ch ANSELA
18Dh ANSELB
18Eh ANSELC
18Fh ANSELD(2)
190h ANSELE(2)
191h PMADRL
192h PMADRH
193h PMDATL
194h PMDATH
195h PMCON1
196h PMCON2
197h VREGCON(1)
—
—
—
—
ANSA5
ANSB5
ANSC5
ANSD5
—
—
ANSA3
ANSB3
ANSC3
ANSD3
—
ANSA2
ANSB2
ANSC2
ANSD2
ANSE2
ANSA1
ANSB1
—
ANSA0 --1- 1111 --1- 1111
ANSB0 --11 1111 --11 1111
ANSB4
ANSC4
ANSD4
—
ANSC7
ANSD7
—
ANSC6
ANSD6
—
—
1111 11-- 1111 11--
ANSD1
ANSE1
ANSD0 1111 1111 1111 1111
ANSE0 ---- -111 ---- -111
0000 0000 0000 0000
Program Memory Address Register Low Byte
Program Memory Address Register High Byte
Program Memory Data Register Low Byte
—
1000 0000 1000 0000
xxxx xxxx uuuu uuuu
—
—
Program Memory Data Register High Byte
--xx xxxx --uu uuuu
(3)
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
1000 x000 1000 q000
0000 0000 0000 0000
Program Memory control register 2
—
—
—
—
—
—
VREGPM Reserved ---- --01 ---- --01
198h
—
Unimplemented
—
—
199h RCREG
19Ah TXREG
19Bh SPBRG
19Ch SPBRGH
19Dh RCSTA
19Eh TXSTA
19Fh BAUDCON
USART Receive Data Register
USART Transmit Data Register
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 000x 0000 000x
0000 0010 0000 0010
BRG<7:0>
BRG<15:8>
SPEN
CSRC
RX9
TX9
SREN
TXEN
—
CREN
ADDEN
SENDB
BRG16
FERR
BRGH
—
OERR
TRMT
WUE
RX9D
TX9D
SYNC
SCKP
ABDOVF
RCIDL
ABDEN 01-0 0-00 01-0 0-00
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F151X only.
Note 1:
2:
3:
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 35
PIC16(L)F1516/7/8/9
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 4
20Ch
20Dh WPUB
—
Unimplemented
—
—
WPUB7
WPUB6
WPUB5
—
WPUB4
—
WPUB3
WPUE3
WPUB2
—
WPUB1
—
WPUB0 1111 1111 1111 1111
20Eh
20Fh
—
—
Unimplemented
Unimplemented
—
—
—
—
—
210h WPUE
—
—
---- 1--- ---- 1---
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
211h SSPBUF
212h SSPADD
213h SSPMSK
214h SSPSTAT
215h SSPCON1
216h SSPCON2
217h SSPCON3
218h
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port (I2C mode) Address Register
Synchronous Serial Port (I2C mode) Address Mask Register
SMP
WCOL
GCEN
ACKTIM
CKE
D/A
P
S
R/W
UA
BF
SSPOV
SSPEN
CKP
SSPM<3:0>
ACKSTAT ACKDT
PCIE SCIE
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
to
—
Unimplemented
—
—
21Fh
Bank 5
28Ch
to
290h
—
Unimplemented
—
—
291h CCPR1L
292h CCPR1H
293h CCP1CON
294h
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC1B<1:0>
CCP1M<3:0>
to
—
Unimplemented
—
—
297h
298h CCPR2L
299h CCPR2H
29Ah CCP2CON
29Bh
Capture/Compare/PWM Register 2 (LSB)
Capture/Compare/PWM Register 2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
—
—
DC2B<1:0>
CCP2M<3:0>
to
29Fh
—
Unimplemented
—
—
—
—
—
—
Bank 6
30Ch
to
31Fh
—
Unimplemented
Unimplemented
Bank 7
38Ch
to
—
393h
394h IOCBN
395h IOCBN
396h IOCBF
397h
IOCBP<7:0>
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
IOCBN<7:0>
IOCBF<7:0>
to
39Fh
—
Unimplemented
Unimplemented
—
—
Bank 8-30
x0Ch
or
x8Ch
to
—
—
—
x1Fh
or
x9Fh
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F151X only.
Note 1:
2:
3:
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
DS41452B-page 36
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on all
other
Resets
Value on:
POR, BOR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bank 31
F8Ch
to
FE3h
—
Unimplemented
—
—
—
FE4h STATUS_SHAD
FE5h WREG_SHAD
FE6h BSR_SHAD
—
—
—
—
—
Z
DC
C
---- -xxx ---- -uuu
xxxx xxxx uuuu uuuu
---x xxxx ---u uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Working Register Shadow
—
—
—
Bank Select Register Shadow
FE7h PCLATH_SHAD
FE8h FSR0L_SHAD
FE9h FSR0H_SHAD
FEAh FSR1L_SHAD
FEBh FSR1H_SHAD
Program Counter Latch High Register Shadow
Indirect Data Memory Address 0 Low Pointer Shadow
Indirect Data Memory Address 0 High Pointer Shadow
Indirect Data Memory Address 1 Low Pointer Shadow
Indirect Data Memory Address 1 High Pointer Shadow
Unimplemented
FECh
FEDh
FEEh
—
—
—
—
—
—
Current Stack pointer
---1 1111 ---1 1111
xxxx xxxx uuuu uuuu
-xxx xxxx -uuu uuuu
STKPTR
TOSL
TOSH
Top of Stack Low byte
Top of Stack High byte
FEFh
—
Legend:
x= unknown, u= unchanged, q= value depends on condition, - = unimplemented, read as ‘0’, r= reserved.
Shaded locations are unimplemented, read as ‘0’.
PIC16F151X only.
Note 1:
2:
3:
PIC16(L)F1517/9 only.
Unimplemented, read as ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 37
PIC16(L)F1516/7/8/9
3.3.3
COMPUTED FUNCTION CALLS
3.3
PCL and PCLATH
A computed function CALLallows programs to maintain
tables of functions and provide another way to execute
state machines or look-up tables. When performing a
table read using a computed function CALL, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block).
The Program Counter (PC) is 15 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<14:8>) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 3-4 shows the five
situations for the loading of the PC.
If using the CALLinstruction, the PCH<2:0> and PCL
registers are loaded with the operand of the CALL
instruction. PCH<6:3> is loaded with PCLATH<6:3>.
FIGURE 3-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
The CALLWinstruction enables computed calls by com-
bining PCLATH and W to form the destination address.
A computed CALLWis accomplished by loading the W
register with the desired address and executing CALLW.
The PCL register is loaded with the value of W and
PCH is loaded with PCLATH.
14
0
Instruction with
PCL as
Destination
PCH
PCL
PC
8
7
6
0
ALU Result
PCLATH
14
0
PCH
PCL
3.3.4
BRANCHING
GOTO, CALL
PC
The branching instructions add an offset to the PC.
This allows relocatable code and code that crosses
page boundaries. There are two forms of branching,
BRW and BRA. The PC will have incremented to fetch
the next instruction in both cases. When using either
branching instruction, a PCL memory boundary may be
crossed.
4
11
6
0
0
PCLATH
OPCODE <10:0>
14
0
PCH
PCL
CALLW
PC
7
8
6
W
PCLATH
If using BRW, load the W register with the desired
unsigned address and execute BRW. The entire PC will
be loaded with the address PC + 1 + W.
14
0
0
PCH
PCH
PCL
BRW
PC
If using BRA, the entire PC will be loaded with PC + 1 +,
the signed value of the operand of the BRAinstruction.
15
PC + W
14
PCL
BRA
PC
15
PC + OPCODE <8:0>
3.3.1
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program Coun-
ter PC<14:8> bits (PCH) to be replaced by the contents
of the PCLATH register. This allows the entire contents
of the program counter to be changed by writing the
desired upper 7 bits to the PCLATH register. When the
lower 8 bits are written to the PCL register, all 15 bits of
the program counter will change to the values con-
tained in the PCLATH register and those being written
to the PCL register.
3.3.2
COMPUTED GOTO
A computed GOTOis accomplished by adding an offset to
the program counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should
be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to the Application
Note AN556, “Implementing a Table Read” (DS00556).
DS41452B-page 38
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.4.1
ACCESSING THE STACK
3.4
Stack
The stack is available through the TOSH, TOSL and
STKPTR registers. STKPTR is the current value of the
Stack Pointer. TOSH:TOSL register pair points to the
TOP of the stack. Both registers are read/writable. TOS
is split into TOSH and TOSL due to the 15-bit size of the
PC. To access the stack, adjust the value of STKPTR,
which will position TOSH:TOSL, then read/write to
TOSH:TOSL. STKPTR is 5 bits to allow detection of
overflow and underflow.
All devices have a 16-level x 15-bit wide hardware
stack (refer to Figures 3-5 through 3-8). The stack
space is not part of either program or data space. The
PC is PUSHed onto the stack when CALL or CALLW
instructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN,
RETLWor a RETFIEinstruction execution. PCLATH is
not affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN
bit is programmed to ‘0‘ (Configuration Word 2). This
means that after the stack has been PUSHed sixteen
times, the seventeenth PUSH overwrites the value that
was stored from the first PUSH. The eighteenth PUSH
overwrites the second PUSH (and so on). The
STKOVF and STKUNF flag bits will be set on an Over-
flow/Underflow, regardless of whether the Reset is
enabled.
Note:
Care should be taken when modifying the
STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLWand
Interrupts will increment STKPTR while RETLW,
RETURN, and RETFIEwill decrement STKPTR. At any
time STKPTR can be inspected to see how much stack
is left. The STKPTR always points at the currently used
place on the stack. Therefore, a CALL or CALLW will
increment the STKPTR and then write the PC, and a
return will unload the PC and then decrement STKPTR.
Note 1: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, CALLW, RETURN, RETLW and
RETFIE instructions or the vectoring to
an interrupt address.
Reference Figure 3-5 through 3-8 for examples of
accessing the stack.
FIGURE 3-5:
ACCESSING THE STACK EXAMPLE 1
Stack Reset Disabled
STKPTR = 0x1F
TOSH:TOSL
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
(STVREN = 0)
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL registers will return ‘0’. If
the Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL registers will
return the contents of stack address 0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 39
PIC16(L)F1516/7/8/9
FIGURE 3-6:
ACCESSING THE STACK EXAMPLE 2
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
This figure shows the stack configuration
after the first CALLor a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
TOSH:TOSL
Return Address
STKPTR = 0x00
FIGURE 3-7:
ACCESSING THE STACK EXAMPLE 3
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure
on the left. A series of RETURNinstructions
will repeatedly place the return addresses
into the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
DS41452B-page 40
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 3-8:
ACCESSING THE STACK EXAMPLE 4
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALLor
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00
so the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
TOSH:TOSL
STKPTR = 0x10
3.4.2
OVERFLOW/UNDERFLOW RESET
If the STVREN bit in Configuration Word 2 is
programmed to ‘1’, the device will be reset if the stack
is PUSHed beyond the sixteenth level or POPed
beyond the first level, setting the appropriate bits
(STKOVF or STKUNF, respectively) in the PCON
register.
3.5
Indirect Addressing
The INDFn registers are not physical registers. Any
instruction that accesses an INDFn register actually
accesses the register at the address specified by the
File Select Registers (FSR). If the FSRn address
specifies one of the two INDFn registers, the read will
return ‘0’ and the write will not occur (though Status bits
may be affected). The FSRn register value is created
by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an
addressing space with 65536 locations. These locations
are divided into three memory regions:
• Traditional Data Memory
• Linear Data Memory
• Program Flash Memory
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 41
PIC16(L)F1516/7/8/9
FIGURE 3-9:
INDIRECT ADDRESSING
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x0FFF
0x1000
0x1FFF
0x2000
Reserved
Linear
Data Memory
0x29AF
0x29B0
Reserved
0x0000
FSR
Address
Range
0x7FFF
0x8000
Program
Flash Memory
0xFFFF
0x7FFF
Note:
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS41452B-page 42
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
3.5.1
TRADITIONAL DATA MEMORY
The traditional data memory is a region from FSR
address 0x000 to FSR address 0xFFF. The addresses
correspond to the absolute addresses of all SFR, GPR
and common registers.
FIGURE 3-10:
TRADITIONAL DATA MEMORY MAP
Direct Addressing
From Opcode
Indirect Addressing
4
BSR
6
7
FSRxH
0
7
FSRxL
0
0
0
0
0
0
0
Location Select
Bank Select
Bank Select
Location Select
00000 00001 00010
11111
0x00
0x7F
Bank 0 Bank 1 Bank 2
Bank 31
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 43
PIC16(L)F1516/7/8/9
3.5.2
LINEAR DATA MEMORY
3.5.3
PROGRAM FLASH MEMORY
The linear data memory is the region from FSR
address 0x2000 to FSR address 0x29AF. This region is
a virtual region that points back to the 80-byte blocks of
GPR memory in all the banks.
To make constant data access easier, the entire
program Flash memory is mapped to the upper half of
the FSR address space. When the MSB of FSRnH is
set, the lower 15 bits are the address in program
memory which will be accessed through INDF. Only the
lower 8 bits of each memory location is accessible via
INDF. Writing to the program Flash memory cannot be
accomplished via the FSR/INDF interface. All
instructions that access program Flash memory via the
FSR/INDF interface will require one additional
instruction cycle to complete.
Unimplemented memory reads as 0x00. Use of the
linear data memory region allows buffers to be larger
than 80 bytes because incrementing the FSR beyond
one bank will go directly to the GPR memory of the next
bank.
The 16 bytes of common memory are not included in
the linear data memory region.
FIGURE 3-12:
PROGRAM FLASH
MEMORY MAP
FIGURE 3-11:
LINEAR DATA MEMORY
MAP
7
7
0
0
FSRnH
FSRnL
7
1
7
0
0
FSRnH
FSRnL
0
0 1
Location Select
0x8000
0x0000
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Program
Flash
Memory
(low 8
bits)
Bank 2
0x16F
0xF20
Bank 30
0x7FFF
0xFFFF
0xF6F
0x29AF
DS41452B-page 44
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
4.0
DEVICE CONFIGURATION
Device Configuration consists of Configuration Word 1
and Configuration Word 2, Code Protection and Device
ID.
4.1
Configuration Words
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word 1 at
8007h and Configuration Word 2 at 8008h.
Note:
The DEBUG bit in Configuration Word 2 is
managed automatically by device
development tools including debuggers
and programmers. For normal device
operation, this bit should be maintained as
a ‘1’.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 45
PIC16(L)F1516/7/8/9
REGISTER 4-1:
CONFIGURATION WORD 1
R/P-1
R/P-1
IESO
R/P-1
R/P-1
R/P-1
U-1
—
FCMEN
CLKOUTEN
BOREN<1:0>
bit 13
bit 8
R/P-1
CP
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
MCLRE
PWRTE
WDTE<1:0>
FOSC<2:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
‘0’ = Bit is cleared
-n = Value when blank or after Bulk Erase
bit 13
bit 12
bit 11
FCMEN: Fail-Safe Clock Monitor Enable bit
1= Fail-Safe Clock Monitor is enabled
0= Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1= Internal/External Switchover mode is enabled
0= Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
If FOSC Configuration bits are set to LP, XT, HS modes:
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
All other FOSC modes:
1= CLKOUT function is disabled. I/O function on the CLKOUT pin.
0= CLKOUT function is enabled on the CLKOUT pin
bit 10-9
BOREN<1:0>: Brown-out Reset Enable bits
11= BOR enabled
10= BOR enabled during operation and disabled in Sleep
01= BOR controlled by SBOREN bit of the BORCON register
00= BOR disabled
bit 8
bit 7
Unimplemented: Read as ‘1’
CP: Code Protection bit
1= Program memory code protection is disabled
0= Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1= MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0= MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUE3 bit.
bit 5
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
bit 4-3
WDTE<1:0>: Watchdog Timer Enable bit
11= WDT enabled
10= WDT enabled while running and disabled in Sleep
01= WDT controlled by the SWDTEN bit in the WDTCON register
00= WDT disabled
DS41452B-page 46
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 4-1:
CONFIGURATION WORD 1 (CONTINUED)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111= ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin
110= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin
101= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin
100= INTOSC oscillator: I/O function on CLKIN pin
011= EXTRC oscillator: External RC circuit connected to CLKIN pin
010= HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins
001= XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins
000= LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 47
PIC16(L)F1516/7/8/9
REGISTER 4-2:
CONFIGURATION WORD 2
R/P-1
LVP
R/P-1
R/P-1
R/P-1
R/P-1
U-1
—
DEBUG
LPBOR
BORV
STVREN
bit 13
bit 8
U-1
—
U-1
—
U-1
—
R/P-1
VCAPEN(1)
U-1
—
U-1
—
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
‘0’ = Bit is cleared
P = Programmable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘1’
-n = Value when blank or after Bulk Erase
bit 13
bit 12
bit 11
bit 10
bit 9
LVP: Low-Voltage Programming Enable bit
1= Low-voltage programming enabled
0= High-voltage on MCLR must be used for programming
DEBUG: In-Circuit Debugger Mode bit
1= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins
0= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger
LPBOR: Low-Power BOR
1= Low-Power BOR is disabled
0= Low-Power BOR is enabled
BORV: Brown-out Reset Voltage Selection bit
1= Brown-out Reset voltage set to 1.9V (typical)
0= Brown-out Reset voltage set to 2.5V (typical)
STVREN: Stack Overflow/Underflow Reset Enable bit
1= Stack Overflow or Underflow will cause a Reset
0= Stack Overflow or Underflow will not cause a Reset
bit 8-5
bit 4
Unimplemented: Read as ‘1’
VCAPEN: Voltage Regulator Capacitor Enable bits(1)
If PIC16LF151X (regulator disabled):
These bits are ignored. All VCAP pin functions are disabled.
If PIC16F151X (regulator enabled):
0= VCAP functionality is enabled on RA5
1= All VCAP pin functions are disabled
bit 3-2
bit 1-0
Unimplemented: Read as ‘1’
WRT<1:0>: Flash Memory Self-Write Protection bits
8 kW Flash memory (PIC16(L)F1516/7 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 1FFFh may be modified by PMCON control
01= 000h to FFFh write-protected, 1000h to 1FFFh may be modified by PMCON control
00= 000h to 1FFFh write-protected, no addresses may be modified by PMCON control
16 kW Flash memory (PIC16(L)F1518/9 only):
11= Write protection off
10= 000h to 1FFh write-protected, 200h to 3FFFh may be modified by PMCON control
01= 000h to 1FFFh write-protected, 2000h to 3FFFh may be modified by PMCON control
00= 000h to 3FFFh write-protected, no addresses may be modified by PMCON control
Note 1: PIC16F151X only.
DS41452B-page 48
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
4.2
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection is
controlled independently. Internal access to the
program memory is unaffected by any code protection
setting.
4.2.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word 1. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 4.3
“Write
Protection” for more information.
4.3
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as
bootloader software, can be protected while allowing
other regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Word 2 define the
size of the program memory block that is protected.
4.4
User ID
Four memory locations (8000h-8003h) are designated as
ID locations where the user can store checksum or other
code identification numbers. These locations are
readable and writable during normal execution. See
Section 11.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing these
memory locations. For more information on checksum
calculation, see the “PIC16(L)F151X/152X Memory
Programming Specification” (DS41442).
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 49
PIC16(L)F1516/7/8/9
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
4.5
Device ID and Revision ID
The memory location 8006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 11.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
REGISTER 4-3:
DEVICEID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
R
R
DEV<8:3>
bit 13
bit 8
bit 0
R
R
R
R
DEV<2:0>
REV<4:0>
bit 7
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘1’
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
bit 13-5
DEV<8:0>: Device ID bits
DEVICEID<13:0> Values
Device
DEV<8:0>
REV<4:0>
PIC16F1519
PIC16F1518
PIC16F1517
PIC16F1516
PIC16LF1519
PIC16LF1518
PIC16LF1517
PIC16LF1516
01 0110 111
01 0110 110
01 0110 101
01 0110 100
01 0111 111
01 0111 110
01 0111 101
01 0111 100
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
x xxxx
bit 4-0
REV<4:0>: Revision ID bits
These bits are used to identify the revision (see Table under DEV<8:0> above).
DS41452B-page 50
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
The oscillator module can be configured in one of eight
clock modes.
5.0
5.1
OSCILLATOR MODULE (WITH
FAIL-SAFE CLOCK MONITOR)
1. ECL – External Clock Low Power mode
(0 MHz to 0.5 MHz)
Overview
2. ECM – External Clock Medium Power mode
(0.5 MHz to 4 MHz)
The oscillator module has a wide variety of clock
sources and selection features that allow it to be used
in a wide range of applications while maximizing perfor-
mance and minimizing power consumption. Figure 5-1
illustrates a block diagram of the oscillator module.
3. ECH – External Clock High Power mode
(4 MHz to 20 MHz)
4. LP – 32 kHz Low-Power Crystal mode.
5. XT – Medium Gain Crystal or Ceramic Resonator
Oscillator mode (up to 4 MHz)
Clock sources can be supplied from external oscillators,
quartz crystal resonators, ceramic resonators and
Resistor-Capacitor (RC) circuits. In addition, the system
clock source can be supplied from one of two internal
oscillators, with a choice of speeds selectable via
software. Additional clock features include:
6. HS – High Gain Crystal or Ceramic Resonator
mode (4 MHz to 20 MHz)
7. RC – External Resistor-Capacitor (RC).
8. INTOSC – Internal oscillator (31 kHz to 16 MHz).
Clock Source modes are selected by the FOSC<2:0>
bits in the Configuration Word 1. The FOSC bits
determine the type of oscillator that will be used when
the device is first powered.
• Selectable system clock source between external
or internal sources via software.
• Two-Speed Start-up mode, which minimizes
latency between external oscillator start-up and
code execution.
The EC clock mode relies on an external logic level
signal as the device clock source. The LP, XT and HS
clock modes require an external crystal or resonator to
be connected to the device. Each mode is optimized for
a different frequency range. The RC clock mode
requires an external resistor and capacitor to set the
oscillator frequency.
• Fail-Safe Clock Monitor (FSCM) designed to
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.
• Oscillator Start-up Timer (OST) ensures stability
of crystal oscillator sources
The INTOSC internal oscillator block produces a low
and high frequency clock source, designated
LFINTOSC and HFINTOSC. (see Internal Oscillator
Block, Figure 5-1). A wide selection of device clock
frequencies may be derived from these two clock
sources.
• Fast start-up oscillator allows internal circuits to
power up and stabilize before switching to the 16
MHz HFINTOSC
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 51
PIC16(L)F1516/7/8/9
FIGURE 5-1:
SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM
Low Power Mode
Event Switch
(SCS<1:0>)
Primary Oscillator
OSC2
OSC1
Primary
Oscillator
(OSC)
2
Primary Clock
00
01
Secondary Oscillator
SOSCO/
T1CKI
Secondary
Oscillator
(SOSC)
Secondary Clock
SOSCI
INTOSC
1x
Internal Oscillator
IRCF<3:0>
4
4
HF-16 MHz
HF-8 MHz
HF-4 MHz
HF-2 MHz
HF-1 MHz
Startup
Control
Logic
1111
1110
1101
1100
1011
/1
/2
/4
/8
/16
16 MHz
Primary Osc
HF-500 kHz 1010/
0111
/32
/64
HF-250 kHz 1001/
0110
Start-Up Osc
HF-125 kHz 1000/
0101
/128
/256
HF-62.5 kHz
0100
HF-31.25 kHz 0011
0010
/512
LF-31 kHz
LF-INTOSC
(31.25 kHz)
0001
0000
DS41452B-page 52
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up
from Sleep. Because the PIC® MCU design is fully
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.
5.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the
clock source to function. Examples are: oscillator mod-
ules (EC mode), quartz crystal resonators or ceramic
resonators (LP, XT and HS modes) and Resis-
tor-Capacitor (RC) mode circuits.
Internal clock sources are contained internally within the
oscillator module. The internal oscillator block has two
internal oscillators that are used to generate the internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator and the 31 kHz Low-Frequency
Internal Oscillator (LFINTOSC).
FIGURE 5-2:
EXTERNAL CLOCK (EC)
MODE OPERATION
OSC1/CLKIN
PIC® MCU
Clock from
Ext. System
The system clock can be selected between external or
internal clock sources via the System Clock Select
(SCS) bits in the OSCCON register. See Section 5.3
“Clock Switching” for additional information.
OSC2/CLKOUT
(1)
FOSC/4 or
I/O
Note 1: Output depends upon CLKOUTEN bit of the
5.2.1
EXTERNAL CLOCK SOURCES
Configuration Word 1.
An external clock source can be used as the device
system clock by performing one of the following
actions:
5.2.1.2
LP, XT, HS Modes
The LP, XT and HS modes support the use of quartz
crystal resonators or ceramic resonators connected to
OSC1 and OSC2 (Figure 5-3). The three modes select
a low, medium or high gain setting of the internal
inverter-amplifier to support various resonator types
and speed.
• Program the FOSC<2:0> bits in the Configuration
Word 1 to select an external clock source that will
be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to:
LP Oscillator mode selects the lowest gain setting of the
internal inverter-amplifier. LP mode current consumption
is the least of the three modes. This mode is designed to
drive only 32.768 kHz tuning-fork type crystals (watch
crystals).
- Secondary oscillator during run-time, or
- An external clock source determined by the
value of the FOSC bits.
See Section 5.3 “Clock Switching”for more informa-
tion.
XT Oscillator mode selects the intermediate gain
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes.
This mode is best suited to drive resonators with a
medium drive level specification.
5.2.1.1
EC Mode
The External Clock (EC) mode allows an externally
generated logic level signal to be the system clock
source. When operating in this mode, an external clock
source is connected to the OSC1 input.
OSC2/CLKOUT is available for general purpose I/O or
CLKOUT. Figure 5-2 shows the pin connections for EC
mode.
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption
is the highest of the three modes. This mode is best
suited for resonators that require a high drive setting.
Figure 5-3 and Figure 5-4 show typical circuits for
quartz crystal and ceramic resonators, respectively.
EC mode has 3 power modes to select from through
Configuration Word 1:
• High power, 4-20 MHz (FOSC = 111)
• Medium power, 0.5-4 MHz (FOSC = 110)
• Low power, 0-0.5 MHz (FOSC = 101)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 53
PIC16(L)F1516/7/8/9
FIGURE 5-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
FIGURE 5-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC® MCU
PIC® MCU
OSC1/CLKIN
OSC1/CLKIN
C1
C1
To Internal
Logic
To Internal
Logic
Quartz
Crystal
(2)
Sleep
RF
(3)
(2)
RP
RF
Sleep
OSC2/CLKOUT
(1)
C2
RS
OSC2/CLKOUT
(1)
C2
RS
Ceramic
Resonator
Note 1: A series resistor (RS) may be required for
Note 1: A series resistor (RS) may be required for
quartz crystals with low drive level.
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
Note 1: Quartz
crystal
characteristics
vary
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
5.2.1.3
Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR) and when the Power-up Timer
(PWRT) has expired (if configured), or a wake-up from
Sleep. During this time, the program counter does not
increment and program execution is suspended. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
In order to minimize latency between external oscillator
start-up and code execution, the Two-Speed Clock
Start-up mode can be selected (see Section 5.4
“Two-Speed Clock Start-up Mode”).
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
DS41452B-page 54
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
5.2.1.4
Secondary Oscillator
5.2.1.5
External RC Mode
The secondary oscillator is a separate crystal oscillator
that is associated with the Timer1 peripheral. It is opti-
mized for timekeeping operations with a 32.768 kHz
crystal connected between the SOSCO and SOSCI
device pins.
The external Resistor-Capacitor (RC) modes support
the use of an external RC circuit. This allows the
designer maximum flexibility in frequency choice while
keeping costs to a minimum when clock accuracy is not
required.
The secondary oscillator can be used as an alternate
system clock source and can be selected during
run-time using clock switching. Refer to Section 5.3
“Clock Switching” for more information.
The RC circuit connects to OSC1. OSC2/CLKOUT is
available for general purpose I/O or CLKOUT. The
function of the OSC2/CLKOUT pin is determined by the
state of the CLKOUTEN bit in Configuration Word 1.
Figure 5-6 shows the external RC mode connections.
FIGURE 5-5:
QUARTZ CRYSTAL
OPERATION
FIGURE 5-6:
EXTERNAL RC MODES
(SECONDARY
OSCILLATOR)
VDD
PIC® MCU
REXT
PIC® MCU
OSC1/CLKIN
Internal
Clock
SOSCI
CEXT
VSS
C1
C2
To Internal
Logic
32.768 kHz
Quartz
Crystal
OSC2/CLKOUT
(1)
FOSC/4 or I/O
SOSCO
Recommended values: 10 k REXT 100 k, <3V
3 k REXT 100 k, 3-5V
CEXT > 20 pF, 2-5V
Note 1: Output depends upon CLKOUTEN bit of the
Note 1: Quartz
crystal
characteristics
vary
Configuration Word 1.
according to type, package and
manufacturer. The user should consult the
manufacturer data sheets for specifications
and recommended application.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values
and the operating temperature. Other factors affecting
the oscillator frequency are:
2: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
• threshold voltage variation
• component tolerances
• packaging variations in capacitance
3: For oscillator design assistance, reference
the following Microchip Applications Notes:
The user also needs to take into account variation due
to tolerance of the external RC components used.
• AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
Devices” (DS00826)
• AN849, “Basic PIC® Oscillator Design”
(DS00849)
• AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
• AN949, “Making Your Oscillator Work”
(DS00949)
• TB097, “Interfacing a Micro Crystal
MS1V-T1K 32.768 kHz Tuning Fork
Crystal to a PIC16F690/SS” (DS91097)
• AN1288, “Design Practices for
Low-Power External Oscillators”
(DS01288)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 55
PIC16(L)F1516/7/8/9
5.2.2
INTERNAL CLOCK SOURCES
5.2.2.2
LFINTOSC
The device may be configured to use the internal oscil-
lator block as the system clock by performing one of the
following actions:
The Low-Frequency Internal Oscillator (LFINTOSC) is
an uncalibrated 31 kHz internal clock source.
The output of the LFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). Select 31 kHz, via
software, using the IRCF<3:0> bits of the OSCCON
register. See Section 5.2.2.4 “Internal Oscillator
Clock Switch Timing” for more information. The
LFINTOSC is also the frequency for the Power-up Timer
(PWRT), Watchdog Timer (WDT) and Fail-Safe Clock
Monitor (FSCM).
• Program the FOSC<2:0> bits in Configuration
Word 1 to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
• Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run-time. See Section 5.3
“Clock Switching”for more information.
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<3:0> bits of the OSCCON register = 000)as the
system clock source (SCS bits of the OSCCON
register = 1x), or when any of the following are
enabled:
In INTOSC mode, OSC1/CLKIN is available for general
purpose I/O. OSC2/CLKOUT is available for general
purpose I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the state of the CLKOUTEN bit in Configuration
Word 1.
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired LF frequency, and
• FOSC<2:0> = 100, or
The internal oscillator block has two independent
oscillators that provides the internal system clock
source.
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’
Peripherals that use the LFINTOSC are:
1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
16 MHz.
• Power-up Timer (PWRT)
• Watchdog Timer (WDT)
2. The LFINTOSC (Low-Frequency Internal
Oscillator) is uncalibrated and operates at
31 kHz.
• Fail-Safe Clock Monitor (FSCM)
The Low-Frequency Internal Oscillator Ready bit
(LFIOFR) of the OSCSTAT register indicates when the
LFINTOSC is running and can be utilized.
5.2.2.1
HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is
a factory calibrated 16 MHz internal clock source.
The output of the HFINTOSC connects to a postscaler
and multiplexer (see Figure 5-1). The frequency derived
from the HFINTOSC can be selected via software using
the IRCF<3:0> bits of the OSCCON register. See
Section 5.2.2.4 “Internal Oscillator Clock Switch
Timing” for more information.
The HFINTOSC is enabled by:
• Configure the IRCF<3:0> bits of the OSCCON
register for the desired HF frequency, and
• FOSC<2:0> = 100, or
• Set the System Clock Source (SCS) bits of the
OSCCON register to ‘1x’.
The High Frequency Internal Oscillator Ready bit
(HFIOFR) of the OSCSTAT register indicates when the
HFINTOSC is running and can be utilized.
The High Frequency Internal Oscillator Status Stable
bit (HFIOFS) of the OSCSTAT register indicates when
the HFINTOSC is running within 0.5% of its final value.
DS41452B-page 56
Preliminary
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5.2.2.3
Internal Oscillator Frequency
Selection
5.2.2.4
Internal Oscillator Clock Switch
Timing
The system clock speed can be selected via software
using the Internal Oscillator Frequency Select bits
IRCF<3:0> of the OSCCON register.
When switching between the HFINTOSC and the
LFINTOSC, the new oscillator may already be shut
down to save power (see Figure 5-7). If this is the case,
there is a delay after the IRCF<3:0> bits of the
OSCCON register are modified before the frequency
selection takes place. The OSCSTAT register will
reflect the current active status of the HFINTOSC and
LFINTOSC oscillators. The sequence of a frequency
selection is as follows:
The output of the 16 MHz HFINTOSC and 31 kHz
LFINTOSC connects to a postscaler and multiplexer
(see Figure 5-1). The Internal Oscillator Frequency
Select bits IRCF<3:0> of the OSCCON register select
the frequency output of the internal oscillators. One of
the following frequencies can be selected via software:
1. IRCF<3:0> bits of the OSCCON register are
modified.
• 16 MHz
• 8 MHz
2. If the new clock is shut down, a clock start-up
delay is started.
• 4 MHz
• 2 MHz
3. Clock switch circuitry waits for a falling edge of
the current clock.
• 1 MHz
• 500 kHz (Default after Reset)
• 250 kHz
4. The current clock is held low and the clock
switch circuitry waits for a rising edge in the new
clock.
• 125 kHz
5. The new clock is now active.
• 62.5 kHz
6. The OSCSTAT register is updated as required.
7. Clock switch is complete.
• 31.25 kHz
• 31 kHz (LFINTOSC)
See Figure 5-7 for more details.
Note:
Following any Reset, the IRCF<3:0> bits
of the OSCCON register are set to ‘0111’
and the frequency selection is set to
500 kHz. The user can modify the IRCF
bits to select a different frequency.
If the internal oscillator speed is switched between two
clocks of the same source, there is no start-up delay
before the new frequency is selected. Clock switching
time delays are shown in Table 5-1.
The IRCF<3:0> bits of the OSCCON register allow
duplicate selections for some frequencies. These dupli-
cate choices can offer system design trade-offs. Lower
power consumption can be obtained when changing
oscillator sources for a given frequency. Faster transi-
tion times can be obtained between frequency changes
that use the same oscillator source.
Start-up delay specifications are located in the
oscillator tables of Section 25.0 “Electrical
Specifications”
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Preliminary
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PIC16(L)F1516/7/8/9
FIGURE 5-7:
INTERNAL OSCILLATOR SWITCH TIMING
HFINTOSC
LFINTOSC (FSCM and WDT disabled)
HFINTOSC
Start-up Time
2-cycle Sync
Running
LFINTOSC
0
0
IRCF <3:0>
System Clock
HFINTOSC
LFINTOSC (Either FSCM or WDT enabled)
HFINTOSC
2-cycle Sync
Running
LFINTOSC
IRCF <3:0>
0
0
System Clock
LFINTOSC
HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
Running
LFINTOSC
Start-up Time 2-cycle Sync
HFINTOSC
IRCF <3:0>
= 0
0
System Clock
DS41452B-page 58
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
5.3.3
SECONDARY OSCILLATOR
5.3
Clock Switching
The secondary oscillator is a separate crystal oscillator
associated with the Timer1 peripheral. It is optimized
for timekeeping operations with a 32.768 kHz crystal
connected between the SOSCO and SOSCI device
pins.
The system clock source can be switched between
external and internal clock sources via software using
the System Clock Select (SCS) bits of the OSCCON
register. The following clock sources can be selected
using the SCS bits:
The secondary oscillator is enabled using the
T1OSCEN control bit in the T1CON register. See
Section 18.0 “Timer1 Module with Gate Control” for
more information about the Timer1 peripheral.
• Default system oscillator determined by FOSC
bits in Configuration Word 1
• Secondary oscillator 32 kHz crystal
• Internal Oscillator Block (INTOSC)
5.3.4
SECONDARY OSCILLATOR READY
(SOSCR) BIT
5.3.1
SYSTEM CLOCK SELECT (SCS)
BITS
The user must ensure that the secondary oscillator is
ready to be used before it is selected as a system clock
source. The Secondary Oscillator Ready (SOSCR) bit
of the OSCSTAT register indicates whether the
secondary oscillator is ready to be used. After the
SOSCR bit is set, the SCS bits can be configured to
select the secondary oscillator.
The System Clock Select (SCS) bits of the OSCCON
register selects the system clock source that is used for
the CPU and peripherals.
• When the SCS bits of the OSCCON register = 00,
the system clock source is determined by value of
the FOSC<2:0> bits in the Configuration Word 1.
• When the SCS bits of the OSCCON register = 01,
the system clock source is the secondary
oscillator.
• When the SCS bits of the OSCCON register = 1x,
the system clock source is chosen by the internal
oscillator frequency selected by the IRCF<3:0>
bits of the OSCCON register. After a Reset, the
SCS bits of the OSCCON register are always
cleared.
Note:
Any automatic clock switch, which may
occur from Two-Speed Start-up or
Fail-Safe Clock Monitor, does not update
the SCS bits of the OSCCON register. The
user can monitor the OSTS bit of the
OSCSTAT register to determine the current
system clock source.
When switching between clock sources, a delay is
required to allow the new clock to stabilize. These oscil-
lator delays are shown in Table 5-1.
5.3.2
OSCILLATOR START-UP TIME-OUT
STATUS (OSTS) BIT
The Oscillator Start-up Time-out Status (OSTS) bit of
the OSCSTAT register indicates whether the system
clock is running from the external clock source, as
defined by the FOSC<2:0> bits in the Configuration
Word 1, or from the internal clock source. In particular,
OSTS indicates that the Oscillator Start-up Timer
(OST) has timed out for LP, XT or HS modes. The OST
does not reflect the status of the secondary oscillator.
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
5.4.1
TWO-SPEED START-UP MODE
CONFIGURATION
5.4
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device. This mode
allows the application to wake-up from Sleep, perform
a few instructions using the INTOSC internal oscillator
block as the clock source and go back to Sleep without
waiting for the external oscillator to become stable.
Two-Speed Start-up mode is configured by the
following settings:
• IESO (of the Configuration Word 1) = 1; Inter-
nal/External Switchover bit (Two-Speed Start-up
mode enabled).
• SCS (of the OSCCON register) = 00.
• FOSC<2:0> bits in the Configuration Word 1
configured for LP, XT or HS mode.
Two-Speed Start-up mode is entered after:
• Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Two-Speed Start-up provides benefits when the oscil-
lator module is configured for LP, XT or HS modes.
The Oscillator Start-up Timer (OST) is enabled for
these modes and must count 1024 oscillations before
the oscillator can be used as the system clock source.
• Wake-up from Sleep.
If the oscillator module is configured for any mode
other than LP, XT or HS mode, then Two-Speed
Start-up is disabled. This is because the external clock
oscillator does not require any stabilization time after
POR or an exit from Sleep.
If the OST count reaches 1024 before the device
enters Sleep mode, the OSTS bit of the OSCSTAT reg-
ister is set and program execution switches to the
external oscillator. However, the system may never
operate from the external oscillator if the time spent
awake is very short.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCSTAT register to
remain clear.
TABLE 5-1:
OSCILLATOR SWITCHING DELAYS
Switch From
Switch To
Frequency
Oscillator Delay
LFINTOSC
HFINTOSC
31 kHz
31.25 kHz-16 MHz
Sleep/POR
Oscillator Warm-up Delay (TWARM)
Sleep/POR
LFINTOSC
EC, RC
EC, RC
DC – 20 MHz
2 cycles
DC – 20 MHz
1 cycle of each
SecondaryOscillator,
LP, XT, HS
Sleep/POR
32 kHz-20 MHz
1024 Clock Cycles (OST)
Any clock source
Any clock source
Any clock source
HFINTOSC
LFINTOSC
31.25 kHz-16 MHz
31 kHz
2 s (approx.)
1 cycle of each
Secondary Oscillator 32 kHz
1024 Clock Cycles (OST)
DS41452B-page 60
Preliminary
2011 Microchip Technology Inc.
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5.4.2
TWO-SPEED START-UP
SEQUENCE
5.4.3
CHECKING TWO-SPEED CLOCK
STATUS
1. Wake-up from Power-on Reset or Sleep.
Checking the state of the OSTS bit of the OSCSTAT
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word 1, or the
internal oscillator.
2. Instructions begin execution by the internal
oscillator at the frequency set in the IRCF<3:0>
bits of the OSCCON register.
3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
internal oscillator.
5. OSTS is set.
6. System clock held low until the next falling edge
of new clock (LP, XT or HS mode).
7. System clock is switched to external clock
source.
FIGURE 5-8:
TWO-SPEED START-UP
INTOSC
TOST
OSC1
0
1
1022 1023
OSC2
Program Counter
PC - N
PC + 1
PC
System Clock
2011 Microchip Technology Inc.
Preliminary
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5.5.3
FAIL-SAFE CONDITION CLEARING
5.5
Fail-Safe Clock Monitor
The Fail-Safe condition is cleared after a Reset,
executing a SLEEPinstruction or changing the SCS bits
of the OSCCON register. When the SCS bits are
changed, the OST is restarted. While the OST is
running, the device continues to operate from the
INTOSC selected in OSCCON. When the OST times
out, the Fail-Safe condition is cleared and the device
will be operating from the external clock source. The
Fail-Safe condition must be cleared before the OSFIF
flag can be cleared.
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue operating should the external oscillator fail.
The FSCM can detect oscillator failure any time after
the Oscillator Start-up Timer (OST) has expired. The
FSCM is enabled by setting the FCMEN bit in the
Configuration Word 1. The FSCM is applicable to all
external Oscillator modes (LP, XT, HS, EC, RC and
secondary oscillator).
FIGURE 5-9:
FSCM BLOCK DIAGRAM
5.5.4
RESET OR WAKE-UP FROM SLEEP
Clock Monitor
Latch
The FSCM is designed to detect an oscillator failure
after the Oscillator Start-up Timer (OST) has expired.
The OST is used after waking up from Sleep and after
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
soon as the Reset or wake-up has completed. When
the FSCM is enabled, the Two-Speed Start-up is also
enabled. Therefore, the device will always be executing
code while the OST is operating.
External
Clock
S
Q
LFINTOSC
Oscillator
÷ 64
R
Q
31 kHz
(~32 s)
488 Hz
(~2 ms)
Sample Clock
Note:
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
Status bits in the OSCSTAT register to
verify the oscillator start-up and that the
system clock switchover has successfully
completed.
Clock
Failure
Detected
5.5.1
FAIL-SAFE DETECTION
The FSCM module detects a failed oscillator by
comparing the external oscillator to the FSCM sample
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 5-9. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
external clock goes low.
5.5.2
FAIL-SAFE OPERATION
When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<3:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.
DS41452B-page 62
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 5-10:
FSCM TIMING DIAGRAM
Sample Clock
Oscillator
Failure
System
Clock
Output
Clock Monitor Output
(Q)
Failure
Detected
OSCFIF
Test
Test
Test
Note:
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 63
PIC16(L)F1516/7/8/9
5.6
Oscillator Control Registers
REGISTER 5-1:
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-0/0 R/W-1/1 R/W-1/1 R/W-1/1
IRCF<3:0>
U-0
—
U-0
—
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
IRCF<3:0>: Internal Oscillator Frequency Select bits
000x= 31 kHz LF
001x= 31.25 kHz
0100= 62.5 kHz
0101= 125 kHz
0110= 250 kHz
0111= 500 kHz (default upon Reset)
1000= 125 kHz(1)
1001= 250 kHz(1)
1010= 500 kHz(1)
1011= 1 MHz
1100= 2 MHz
1101= 4 MHz
1110= 8 MHz
1111= 16 MHz
bit 2
Unimplemented: Read as ‘0’
bit 1-0
SCS<1:0>: System Clock Select bits
1x= Internal oscillator block
01= Secondary oscillator
00= Clock determined by FOSC<2:0> in Configuration Word 1.
Note 1: Duplicate frequency derived from HFINTOSC.
DS41452B-page 64
Preliminary
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REGISTER 5-2:
OSCSTAT: OSCILLATOR STATUS REGISTER
R-1/q
SOSCR
bit 7
U-0
—
R-q/q
R-0/q
U-0
—
U-0
—
R-0/0
R-0/q
OSTS
HFIOFR
LFIOFR
HFIOFS
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Conditional
bit 7
SOSCR: Secondary Oscillator Ready bit
If T1OSCEN = 1:
1= Secondary oscillator is ready
0= Secondary oscillator is not ready
If T1OSCEN = 0:
1 = Timer1 clock source is always ready
bit 6
bit 5
Unimplemented: Read as ‘0’
OSTS: Oscillator Start-up Time-out Status bit
1= Running from the clock defined by the FOSC<2:0> bits of the Configuration Word 1
0= Running from an internal oscillator (FOSC<2:0> = 100)
bit 4
HFIOFR: High Frequency Internal Oscillator Ready bit
1= HFINTOSC is ready
0= HFINTOSC is not ready
bit 3-2
bit 1
Unimplemented: Read as ‘0’
LFIOFR: Low Frequency Internal Oscillator Ready bit
1= LFINTOSC is ready
0= LFINTOSC is not ready
bit 0
HFIOFS: High Frequency Internal Oscillator Stable bit
1= HFINTOSC 16 MHz Oscillator is stable and is driving the INTOSC
0= HFINTOSC 16 MHz is not stable, the 12 MHz Start-up Oscillator is driving INTOSC
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
OSCSTAT
PIE2
—
IRCF<3:0>
—
—
SCS<1:0>
64
65
SOSCR
OSFIE
OSFIF
—
—
—
OSTS
—
HFIOFR
—
LFIOFR
HFIOFS
CCP2IE
CCP2IF
TMR1ON
—
—
BCLIE
—
—
—
—
82
BCLIF
—
PIR2
—
84
T1CON
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
T1SYNC
167
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
TABLE 5-3:
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
13:8
7:0
—
CONFIG1
46
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 65
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 66
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 6-1.
6.0
RESETS
There are multiple ways to reset this device:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Low-Power Brown-out Reset (LPBOR)
• MCLR Reset
• WDT Reset
• RESETinstruction
• Stack Overflow
• Stack Underflow
• Programming mode exit
To allow VDD to stabilize, an optional power-up timer
can be enabled to extend the Reset time after a BOR
or POR event.
FIGURE 6-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Programming Mode Exit
RESET Instruction
Stack Overflow/Underflow Reset
Stack
Pointer
External Reset
MCLRE
MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
LPBOR
Reset
BOR
Enable
PWRT
64 ms
Zero
LFINTOSC
PWRTEN
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 67
PIC16(L)F1516/7/8/9
6.1
Power-on Reset (POR)
6.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Word 1. The four operating modes are:
• BOR is always on
6.1.1
POWER-UP TIMER (PWRT)
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
The Power-up Timer provides a nominal 64 ms time-
out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word 1.
Refer to Table 6-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Word 2.
A VDD noise rejection filter prevents the BOR from trig-
gering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 6-2 for more information.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 6-1:
BOREN<1:0>
BOR OPERATING MODES
Device Operation
Device Operation
upon release of POR
SBOREN
Device Mode
BOR Mode
upon wake- up from
Sleep
11
10
X
X
X
Active
Active
Waits for BOR ready(1)
Awake
Sleep
Waits for BOR ready
Disabled
Active
1
0
X
Begins immediately
Begins immediately
Begins immediately
01
00
X
X
Disabled
Disabled
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
start-up.
6.2.1
BOR IS ALWAYS ON
6.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word 1 are set
to ‘11’, the BOR is always on. The device start-up will
be delayed until the BOR is ready and VDD is higher
than the BOR threshold.
When the BOREN bits of Configuration Word 1 are set
to ‘01’, the BOR is controlled by the SBOREN bit of the
BORCON register. The device start-up is not delayed
by the BOR ready condition or the VDD level.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
6.2.2
BOR IS OFF IN SLEEP
BOR protection is unchanged by Sleep.
When the BOREN bits of Configuration Word 1 are set
to ‘10’, the BOR is on, except in Sleep. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
DS41452B-page 68
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.
REGISTER 6-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
SBOREN
bit 7
R/W-0/u
BORFS
U-0
—
U-0
—
U-0
—
U-0
—
U-0
R-q/u
—
BORRDY
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
SBOREN: Software Brown-out Reset Enable bit(1)
If BOREN <1:0> 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN <1:0> = 01:
1= BOR Enabled
0= BOR Disabled
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control):
1= Band gap is forced on always (covers sleep/wake-up/operating cases)
0= Band gap operates normally, and may turn off
bit 5-1
bit 0
Unimplemented: Read as ‘0’
BORRDY: Brown-out Reset Circuit Ready Status bit
1= The Brown-out Reset circuit is active
0= The Brown-out Reset circuit is inactive
Note 1: BOREN<1:0> bits are located in Configuration Word 1.
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6.3
Low-Power Brown-out Reset
(LPBOR)
6.5
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDTinstruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer” for more information.
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 6-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 6-2.
6.6
RESET Instruction
A RESETinstruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See Table 6-4
for default conditions after a RESET instruction has
occurred.
6.3.1
ENABLING LPBOR
6.7
Stack Overflow/Underflow Reset
The LPBOR is controlled by the LPBOR bit of
Configuration Word 2. When the device is erased, the
LPBOR module defaults to disabled.
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Word 2. See Section 3.4.2 “Overflow/Underflow
Reset” for more information.
6.3.1.1
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
to be OR’d together with the Reset signal of the BOR
module to provide the generic BOR signal which goes
to the PCON register and to the power control block.
6.8
Programming Mode Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.4
MCLR
6.9
Power-Up Timer
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2 (Register 4-2).
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
TABLE 6-2:
MCLRE
MCLR CONFIGURATION
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
LVP
MCLR
0
1
x
0
0
1
Disabled
Enabled
Enabled
6.10 Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
6.4.1
MCLR ENABLED
2. Oscillator start-up timer runs to completion (if
required for oscillator source).
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
3. MCLR must be released (if enabled).
The total time-out will vary based on oscillator configu-
ration and Power-up Timer configuration. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for more information.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
A Reset does not drive the MCLR pin low.
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see Figure 6-3). This
is useful for testing purposes or to synchronize more
than one device operating in parallel.
6.4.2
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.6 “PORTE Registers”
for more information.
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FIGURE 6-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-Up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
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6.11 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset. Table 6-3 and Table 6-4 show the Reset condi-
tions of these registers.
TABLE 6-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
STKOVF STKUNF RWDT RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
0
0
0
0
u
u
u
u
u
u
1
u
0
0
0
0
u
u
u
u
u
u
u
1
1
1
1
u
0
u
u
u
u
u
u
u
1
1
1
1
u
u
u
0
0
u
u
u
1
1
1
1
u
u
u
u
u
0
u
u
0
0
0
u
u
u
u
u
u
u
u
u
x
x
x
0
u
u
u
u
u
u
u
u
1
0
x
1
0
0
1
u
1
u
u
u
1
x
0
1
u
0
0
u
0
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
u RESETInstruction Executed
u
u
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
TABLE 6-4:
RESET CONDITION FOR SPECIAL REGISTERS(2)
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
0000h
---1 1000
---u uuuu
00-1 110x
uu-u 0uuu
MCLR Reset during normal operation
0000h
MCLR Reset during Sleep
WDT Reset
0000h
0000h
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
uu-u 0uuu
uu-0 uuuu
uu-u uuuu
00-1 11u0
uu-u uuuu
uu-u u0uu
1u-u uuuu
u1-u uuuu
WDT Wake-up from Sleep
Brown-out Reset
PC + 1
0000h
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
PC + 1(1)
0000h
0000h
0000h
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2: If a Status bit is not implemented, that bit will be read as ‘0’.
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6.12 Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Reset Instruction Reset (RI)
• MCLR Reset (RMCLR)
• Watchdog Timer Reset (RWDT)
• Stack Underflow Reset (STKUNF)
• Stack Overflow Reset (STKOVF)
The PCON register bits are shown in Register 6-2.
REGISTER 6-2:
PCON: POWER CONTROL REGISTER
R/W/HS-0/q R/W/HS-0/q
U-0
—
R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u
STKOVF
bit 7
STKUNF
RWDT
RMCLR
RI
POR
BOR
bit 0
Legend:
HC = Bit is cleared by hardware
HS = Bit is set by hardware
U = Unimplemented bit, read as ‘0’
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
-m/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
STKOVF: Stack Overflow Flag bit
1= A Stack Overflow occurred
0= A Stack Overflow has not occurred or set to ‘0’ by firmware
STKUNF: Stack Underflow Flag bit
1= A Stack Underflow occurred
0= A Stack Underflow has not occurred or set to ‘0’ by firmware
Unimplemented: Read as ‘0’
bit 5
bit 4
RWDT: Watchdog Timer Reset Flag bit
1= A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware
0= A Watchdog Timer Reset has occurred (set to ‘0’ in hardware when a Watchdog Timer Reset)
bit 3
bit 2
bit 1
bit 0
RMCLR: MCLR Reset Flag bit
1= A MCLR Reset has not occurred or set to ‘1’ by firmware
0= A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
RI: RESETInstruction Flag bit
1= A RESETinstruction has not been executed or set to ‘1’ by firmware
0= A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
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TABLE 6-5:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BORCON SBOREN BORFS
—
—
—
RWDT
TO
—
—
RI
—
BORRDY
BOR
69
73
25
95
PCON
STKOVF STKUNF
RMCLR
POR
STATUS
—
—
—
—
—
PD
Z
DC
C
WDTCON
WDTPS<4:0>
SWDTEN
Legend: — = unimplemented bit, reads as ‘0’. Shaded cells are not used by Resets.
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7.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
• Operation
• Interrupt Latency
• Interrupts During Sleep
• INT Pin
• Automatic Context Saving
Many peripherals produce Interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 7-1.
FIGURE 7-1:
INTERRUPT LOGIC
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
(TMR1IF) PIR1<0>
IOCIF
IOCIE
Interrupt
to CPU
(TMR1IE) PIE1<0>
PEIE
GIE
PIRn<7>
PIEn<7>
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7.1
Operation
7.2
Interrupt Latency
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is 3 or 4 instruction cycles. For asynchronous
interrupts, the latency is 3 to 5 instruction cycles,
depending on when the interrupt occurs. See Figure 7-2
and Figure 7-3 for more details.
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIEx register)
The INTCON, PIR1 and PIR2 registers record individual
interrupts via interrupt flag bits. Interrupt flag bits will be
set, regardless of the status of the GIE, PEIE and
individual interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• Critical registers are automatically saved to the
shadow registers (See Section 7.5 “Automatic
Context Saving”)
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
should determine the source of the interrupt by polling
the interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, restoring the saved
context from the shadow registers and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
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FIGURE 7-2:
INTERRUPT LATENCY
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
Interrupt Sampled
during Q1
Interrupt
GIE
PC-1
PC
PC+1
0004h
NOP
0005h
PC
1 Cycle Instruction at PC
Execute
Inst(PC)
NOP
Inst(0004h)
Interrupt
GIE
PC+1/FSR
ADDR
New PC/
PC+1
PC-1
PC
0004h
NOP
0005h
PC
Execute
2 Cycle Instruction at PC
Inst(PC)
NOP
Inst(0004h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
NOP
PC+2
NOP
0004h
NOP
0005h
PC
Execute
3 Cycle Instruction at PC
Inst(0004h)
Inst(0005h)
Interrupt
GIE
PC-1
PC
FSR ADDR
INST(PC)
PC+1
NOP
PC+2
0004h
NOP
0005h
PC
NOP
Execute
3 Cycle Instruction at PC
NOP
Inst(0004h)
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FIGURE 7-3:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
INTF
(1)
(1)
(2)
(5)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC – 1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT not available in all oscillator modes.
4: For minimum width of INT pulse, refer to AC specifications in Section 25.0 “Electrical Specifications”.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
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7.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEPinstruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 8.0 “Power-
Down Mode (Sleep)” for more details.
7.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
7.5
Automatic Context Saving
Upon entering an interrupt, the return PC address is
saved on the stack. Additionally, the following registers
are automatically saved in the Shadow registers:
• W register
• STATUS register (except for TO and PD)
• BSR register
• FSR registers
• PCLATH register
Upon exiting the Interrupt Service Routine, these regis-
ters are automatically restored. Any modifications to
these registers during the ISR will be lost. If modifica-
tions to any of these registers are desired, the corre-
sponding Shadow register should be modified and the
value will be restored when exiting the ISR. The
Shadow registers are available in Bank 31 and are
readable and writable. Depending on the user’s
application, other registers may also need to be saved.
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7.6
Interrupt Control Registers
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.
7.6.1
INTCON REGISTER
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, interrupt-on-change and
external INT pin interrupts.
REGISTER 7-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
GIE
R/W-0/0
PEIE
R/W-0/0
TMR0IE
R/W-0/0
INTE
R/W-0/0
IOCIE
R/W-0/0
TMR0IF
R/W-0/0
INTF
R-0/0
IOCIF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1= Enables all active interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all active peripheral interrupts
0= Disables all peripheral interrupts
TMR0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: INT External Interrupt Enable bit
1= Enables the INT external interrupt
0= Disables the INT external interrupt
IOCIE: Interrupt-on-Change Interrupt Enable bit
1= Enables the interrupt-on-change interrupt
0= Disables the interrupt-on-change interrupt
TMR0IF: Timer0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed
0= TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1= The INT external interrupt occurred
0= The INT external interrupt did not occur
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1= When at least one of the interrupt-on-change pins changed state
0= None of the interrupt-on-change pins have changed state
Note 1: The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCBF register
have been cleared by software.
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7.6.2
PIE1 REGISTER
The PIE1 register contains the interrupt enable bits, as
shown in Register 7-2.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0/0
TMR1GIE
bit 7
R/W-0/0
ADIE
R/W-0/0
RCIE
R/W-0/0
TXIE
R/W-0/0
SSPIE
R/W-0/0
CCP1IE
R/W-0/0
TMR2IE
R/W-0/0
TMR1IE
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIE: Timer1 Gate Interrupt Enable bit
1= Enables the Timer1 Gate Acquisition interrupt
0= Disables the Timer1 Gate Acquisition interrupt
ADIE: A/D Converter (ADC) Interrupt Enable bit
1= Enables the ADC interrupt
0= Disables the ADC interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit
1= Enables the MSSP interrupt
0= Disables the MSSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the Timer2 to PR2 match interrupt
0= Disables the Timer2 to PR2 match interrupt
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
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7.6.3
PIE2 REGISTER
The PIE2 register contains the interrupt enable bits, as
shown in Register 7-3.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 7-3:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
R/W-0/0
OSFIE
bit 7
U-0
—
U-0
—
U-0
—
R/W-0/0
BCLIE
U-0
—
U-0
—
R/W-0/0
CCP2IE
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the Oscillator Fail interrupt
0= Disables the Oscillator Fail interrupt
bit 6-4
bit 3
Unimplemented: Read as ‘0’
BCL1IE: MSSP Bus Collision Interrupt Enable bit
1= Enables the MSSP Bus Collision Interrupt
0= Disables the MSSP Bus Collision Interrupt
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
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7.6.4
PIR1 REGISTER
The PIR1 register contains the interrupt flag bits, as
shown in Register 7-4.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-4:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
R/W-0/0
TMR1GIF
bit 7
R/W-0/0
ADIF
R-0/0
RCIF
R-0/0
TXIF
R/W-0/0
SSPIF
R/W-0/0
CCP1IF
R/W-0/0
TMR2IF
R/W-0/0
TMR1IF
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
TMR1GIF: Timer1 Gate Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
ADIF: A/D Converter Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
RCIF: USART Receive Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TXIF: USART Transmit Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
CCP1IF: CCP1 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
TMR1IF: Timer1 Overflow Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
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7.6.5
PIR2 REGISTER
The PIR2 register contains the interrupt flag bits, as
shown in Register 7-5.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 7-5:
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
OSFIF
U-0
—
U-0
—
U-0
—
R/W-0/0
BCLIF
U-0
—
U-0
—
R/W-0/0
CCP2IF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 6-4
bit 3
Unimplemented: Read as ‘0’
BCLIF: MSSP Bus Collision Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
bit 2-1
bit 0
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
1= Interrupt is pending
0= Interrupt is not pending
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TABLE 7-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
OPTION_REG
PIE1
GIE
PEIE
INTEDG
ADIE
—
TMR0IE
INTE
IOCIE
PSA
TMR0IF
INTF
PS<2:0>
TMR2IE
—
IOCIF
80
157
81
WPUEN
TMR1GIE
OSFIE
TMR0CS TMR0SE
RCIE
—
TXIE
—
SSPIE
BCLIE
SSPIF
BCLIF
CCP1IE
—
TMR1IE
CCP2IE
TMR1IF
CCP2IF
PIE2
82
TMR1GIF
OSFIF
ADIF
—
RCIF
—
TXIF
—
CCP1IF
—
TMR2IF
—
PIR1
83
PIR2
84
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
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NOTES:
DS41452B-page 86
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8.1
Wake-up from Sleep
8.0
POWER-DOWN MODE (SLEEP)
The device can wake-up from Sleep through one of the
following events:
The Power-Down mode is entered by executing a
SLEEPinstruction.
1. External Reset input on MCLR pin, if enabled
2. BOR Reset, if enabled
Upon entering Sleep mode, the following conditions
exist:
3. POR Reset
1. WDT will be cleared but keeps running, if
enabled for operation during Sleep.
4. Watchdog Timer, if enabled
5. Any external interrupt
2. PD bit of the STATUS register is cleared.
3. TO bit of the STATUS register is set.
4. CPU clock is disabled.
6. Interrupts by peripherals capable of running dur-
ing Sleep (see individual peripheral for more
information)
5. 31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
The first three events will cause a device Reset. The
last three events are considered a continuation of pro-
gram execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 6.11
“Determining the Cause of a Reset”.
6. Secondary Oscillator is unaffected and periph-
erals that operate from it may continue operation
in Sleep.
7. ADC is unaffected, if the dedicated FRC clock is
selected.
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEPinstruction, the device will call the Interrupt Ser-
vice Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOPafter the SLEEPinstruction.
8. I/O ports maintain the status they had before
SLEEPwas executed (driving high, low or high-
impedance).
9. Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following condi-
tions should be considered:
• I/O pins should not be floating
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
• External circuitry sinking current from I/O pins
• Internal circuitry sourcing current from I/O pins
• Current draw from pins with internal weak pull-ups
• Modules using 31 kHz LFINTOSC
• Modules using secondary oscillator
I/O pins that are high-impedance inputs should be
pulled to VDD or VSS externally to avoid switching
currents caused by floating inputs.
The FVR module is an example of internal circuitry that
might be sourcing current. See Section 14.0 “Fixed
Voltage Reference (FVR)” for more information on this
module.
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• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction
8.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
- SLEEPinstruction will be completely exe-
cuted
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared
• If the interrupt occurs before the execution of a
SLEEPinstruction
- SLEEPinstruction will execute as a NOP
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
- PD bit of the STATUS register will not be
cleared
FIGURE 8-1:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1(1)
(3)
CLKOUT(2)
TOST
Interrupt Latency(4)
Interrupt flag
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
PC + 1
PC + 2
PC + 2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = Sleep
Instruction
Executed
Dummy Cycle
Dummy Cycle
Sleep
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1:
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS or LP Oscillator modes, but shown here for timing reference.
TOST = 1024 TOSC (drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
2:
3:
4:
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8.2.2
PERIPHERAL USAGE IN SLEEP
8.2
Low-Power Sleep Mode
Some peripherals that can operate in Sleep mode will
not operate properly with the Low-Power Sleep mode
selected. The LDO will remain in the normal power
mode when those peripherals are enabled. The Low-
Power Sleep mode is intended for use with these
peripherals:
The PIC16F151X device contains an internal Low
Dropout (LDO) voltage regulator, which allows the
device I/O pins to operate at voltages up to 5.5V while
the internal device logic operates at a lower voltage.
The LDO and its associated reference circuitry must
remain active when the device is in Sleep mode. The
PIC16F151X allows the user to optimize the operating
current in Sleep, depending on the application require-
ments.
• Brown-Out Reset (BOR)
• Watchdog Timer (WDT)
• External interrupt pin/Interrupt-on-change pins
• Timer1 (with external clock source)
• CCP (Capture mode)
A Low-Power Sleep mode can be selected by setting
the VREGPM bit of the VREGCON register. With this
bit set, the LDO and reference circuitry are placed in a
low-power state when the device is in Sleep.
Note:
The PIC16LF151X does not have a con-
figurable Low-Power Sleep mode.
PIC16LF151X is an unregulated device
and is always in the lowest power state
when in Sleep, with no wake-up time pen-
alty. This device has a lower maximum
VDD and I/O voltage than the
PIC16F151X. See Section 25.0 “Electri-
cal Specifications” for more information.
8.2.1
SLEEP CURRENT VS. WAKE-UP
TIME
In the default operating mode, the LDO and reference
circuitry remain in the normal configuration while in
Sleep. The device is able to exit Sleep mode quickly
since all circuits remain active. In Low-Power Sleep
mode, when waking up from Sleep, an extra delay time
is required for these circuits to return to the normal con-
figuration and stabilize.
The Low-Power Sleep mode is beneficial for applica-
tions that stay in Sleep mode for long periods of time.
The normal mode is beneficial for applications that
need to wake from Sleep quickly and frequently.
8.3
Power Control Registers
REGISTER 8-1:
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
VREGPM: Voltage Regulator Power Mode Selection bit
1= Low-Power Sleep mode enabled in Sleep(2)
Draws lowest current in Sleep, slower wake-up
0= Normal Power mode enabled in Sleep(2)
Draws higher current in Sleep, faster wake-up
bit 0
Reserved: Read as ‘1’. Maintain this bit set.
Note 1: PIC16F151X only.
2: See Section 25.0 “Electrical Specifications”.
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TABLE 8-1:
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
IOCBF
IOCBN
IOCBP
PIE1
GIE
IOCBF7
IOCBN7
IOCBP7
TMR1GIE
OSFIE
TMR1GIF
OSFIF
—
PEIE
IOCBF6
IOCBN6
IOCBP6
ADIE
—
TMR0IE
IOCBF5
IOCBN5
IOCBP5
RCIE
—
INTE
IOCBF4
IOCBN4
IOCBP4
TXIE
—
IOCIE
IOCBF3
IOCBN3
IOCBP3
SSPIE
BCLIE
TMR0IF
IOCBF2
IOCBN2
IOCBP2
CCP1IE
—
INTF
IOCBF1
IOCBN1
IOCBP1
TMR2IE
—
IOCIF
IOCBF0
IOCBN0
IOCBP0
TMR1IE
CCP2IE
TMR1IF
CCP2IF
C
80
135
135
135
81
PIE2
82
PIR1
ADIF
—
RCIF
—
TXIF
—
SSPIF
CCP1IF
—
TMR2IF
—
83
PIR2
BCLIF
84
STATUS
—
—
TO
PD
Z
DC
25
(1)
VREGCON
—
—
—
—
—
—
VREGPM
89
Reserved
SWDTEN
WDTPS<4:0>
WDTCON
—
—
95
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
Note 1: PIC16F151X only.
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On power-up, the external capacitor will load the LDO
voltage regulator. To prevent erroneous operation, the
device is held in Reset while a constant current source
charges the external capacitor. After the cap is fully
charged, the device is released from Reset. For more
information on recommended capacitor values and the
constant current rate, refer to the LDO Regulator
Characteristics Table in Section 25.0 “Electrical
Specifications”.
9.0
LOW DROPOUT (LDO)
VOLTAGE REGULATOR
The PIC16F151X has an internal Low Dropout
Regulator (LDO) which provides operation above 3.6V.
The LDO regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. There is no user enable/disable
control available for the LDO, it is always active. The
PIC16LF151X operates at a maximum VDD of 3.6V and
does not incorporate an LDO.
A device I/O pin may be configured as the LDO voltage
output, identified as the VCAP pin. Although not
required, an external low-ESR capacitor may be con-
nected to the VCAP pin for additional regulator stability.
The VCAPEN bit of Configuration Word 2 enables the
VCAP pin. Refer to Table 9-1.
TABLE 9-1:
VCAPEN SELECT BIT
VCAPEN
Pin
0
RA5
TABLE 9-2:
SUMMARY OF CONFIGURATION WORD WITH LDO
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
LVP
—
DEBUG
VCAPEN
LPBOR
—
BORV
—
STVREN
—
CONFIG2
48
—
—
WRT<1:0>
Legend:
— = unimplemented locations read as ‘0’. Shaded cells are not used by LDO.
Note 1: PIC16F151X only.
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NOTES:
DS41452B-page 92
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10.0 WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (nominal)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 10-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> = 01
SWDTEN
23-bit Programmable
WDT Time-out
WDTE<1:0> = 11
LFINTOSC
Prescaler WDT
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
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10.1 Independent Clock Source
10.3 Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 25.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the
time-out period from 1ms to 256 seconds (nominal).
After a Reset, the default time-out period is 2 seconds.
10.4 Clearing the WDT
The WDT is cleared when any of the following condi-
tions occur:
10.2 WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE<1:0> bits in Configuration
Word 1. See Table 10-1.
• Any Reset
• CLRWDTinstruction is executed
• Device enters Sleep
• Device wakes up from Sleep
• Oscillator fail event
• WDT is disabled
10.2.1
WDT IS ALWAYS ON
When the WDTE bits of Configuration Word 1 are set to
‘11’, the WDT is always on.
• OST is running
WDT protection is active during Sleep.
See Table 10-2 for more information.
10.2.2
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word 1 are set to
‘10’, the WDT is on, except in Sleep.
10.5 Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
WDT protection is not active during Sleep.
10.2.3
WDT CONTROLLED BY SOFTWARE
When the device exits Sleep, the WDT is cleared
again. The WDT remains clear until the OST, if
enabled, completes. See Section 5.0 “Oscillator
Module (With Fail-Safe Clock Monitor)” for more
information on the OST.
When the WDTE bits of Configuration Word 1 are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See
Table 10-1 for more details.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See Section 3.0 “Memory Organization” and
The STATUS register (Register 3-1) for more
information.
TABLE 10-1: WDT OPERATING MODES
Device
Mode
WDT
Mode
WDTE<1:0>
SWDTEN
11
10
X
X
X
Active
Active
Awake
Sleep Disabled
1
0
X
Active
X
01
00
Disabled
X
Disabled
TABLE 10-2: WDT CLEARING CONDITIONS
Conditions
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDTCommand
Cleared
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
Cleared until the end of OST
Unaffected
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10.6 Watchdog Control Register
REGISTER 10-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
R/W-0/0
WDTPS<4:0>
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
U = Unimplemented bit, read as ‘0’
-m/n = Value at POR and BOR/Value at all other Resets
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-1
Unimplemented: Read as ‘0’
WDTPS<4:0>: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
00000 = 1:32 (Interval 1 ms nominal)
00001 = 1:64 (Interval 2 ms nominal)
00010 = 1:128 (Interval 4 ms nominal)
00011 = 1:256 (Interval 8 ms nominal)
00100 = 1:512 (Interval 16 ms nominal)
00101 = 1:1024 (Interval 32 ms nominal)
00110 = 1:2048 (Interval 64 ms nominal)
00111 = 1:4096 (Interval 128 ms nominal)
01000 = 1:8192 (Interval 256 ms nominal)
01001 = 1:16384 (Interval 512 ms nominal)
01010 = 1:32768 (Interval 1s nominal)
01011 = 1:65536 (Interval 2s nominal) (Reset value)
01100 = 1:131072 (217) (Interval 4s nominal)
01101 = 1:262144 (218) (Interval 8s nominal)
01110 = 1:524288 (219) (Interval 16s nominal)
01111 = 1:1048576 (220) (Interval 32s nominal)
10000 = 1:2097152 (221) (Interval 64s nominal)
10001 = 1:4194304 (222) (Interval 128s nominal)
10010 = 1:8388608 (223) (Interval 256s nominal)
10011 = Reserved. Results in minimum interval (1:32)
•
•
•
11111 = Reserved. Results in minimum interval (1:32)
bit 0
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE<1:0> = 00:
This bit is ignored.
If WDTE<1:0> = 01:
1= WDT is turned on
0= WDT is turned off
If WDTE<1:0> = 1x:
This bit is ignored.
Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.
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TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OSCCON
STATUS
—
—
—
IRCF<3:0>
—
Z
SCS<1:0>
DC
64
25
95
—
—
—
TO
PD
C
WDTCON
Legend:
WDTPS<4:0>
SWDTEN
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.
TABLE 10-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
—
CONFIG1
46
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
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11.1.1
PMCON1 AND PMCON2
REGISTERS
11.0 FLASH PROGRAM MEMORY
CONTROL
PMCON1 is the control register for Flash program
memory accesses.
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
• PMCON1
• PMCON2
• PMDATL
• PMDATH
• PMADRL
• PMADRH
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 15-bit address of the program memory
location being read.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the
device.
11.2 Flash Program Memory Overview
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Word 1)
and write protection (WRT<1:0> bits in Configuration
Word 2).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT<1:0>. Write protection does not affect
a device programmers ability to read, write or erase the
device.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. How-
ever, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Word 1.
11.1 PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 32K words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
See Table 11-1 for Erase Row size and the number of
write latches for Flash program memory.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 97
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FIGURE 11-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
TABLE 11-1: FLASH MEMORY
ORGANIZATION BY DEVICE
Write
Latches
(words)
Row Erase
(words)
Device
Start
READ Operation
PIC16(L)F1516
PIC16(L)F1517
PIC16(L)F1518
PIC16(L)F1519
32
32
Select
Program or Configuration Memory
(CFGS)
11.2.1
READING THE FLASH PROGRAM
MEMORY
Select
Word Address
(PMADRH:PMADRL)
To read a program memory location, the user must:
1. Write the desired address to the
PMADRH:PMADRL register pair.
2. Clear the CFGS bit of the PMCON1 register.
Initiate READ operation
3. Then, set control bit RD of the PMCON1 register.
(RD = 1)
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
two-cycle instruction on the next
instruction after the RD bit is set.
Data read now in
PMDATH:PMDATL
End
READ Operation
DS41452B-page 98
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 11-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
PC + 1
PMADRH,PMADRL
PC + 3
PC + 4
PC + 5
Flash ADDR
Flash Data
INSTR (PC)
INSTR (PC + 1)
PMDATH,PMDATL
INSTR (PC + 3)
INSTR (PC + 4)
INSTR(PC + 1)
INSTR(PC + 2)
instruction ignored instruction ignored
BSF PMCON1,RD
executed here
INSTR(PC - 1)
executed here
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
Forced NOP
Forced NOP
executed here
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 11-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
*
*
data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; Select Bank for PMCON registers
MOVLW
MOVWF
MOVLW
MOVWL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
; Do not select Configuration Space
; Initiate read
; Ignored (Figure 11-2)
; Ignored (Figure 11-2)
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
2011 Microchip Technology Inc.
Preliminary
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11.2.2
FLASH MEMORY UNLOCK
SEQUENCE
FIGURE 11-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write pro-
gramming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
Start
Unlock Sequence
• Row Erase
• Load program memory write latches
Write 055h to
PMCON2
• Write of program memory write latches to pro-
gram memory
• Write of program memory write latches to User
IDs
Write 0AAh to
PMCON2
The unlock sequence consists of the following steps:
1. Write 55h to PMCON2
Initiate
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
4. NOPinstruction
WRITE or ERASE operation
(WR = 1)
5. NOPinstruction
Instruction Fetched ignored
NOP execution forced
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Instruction Fetched ignored
NOP execution forced
End
Unlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts should be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
DS41452B-page 100
Preliminary
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PIC16(L)F1516/7/8/9
11.2.3
ERASING FLASH PROGRAM
MEMORY
FIGURE 11-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
While executing code, program memory can only be
erased by rows. To erase a row:
1. Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Start
ERASE Operation
2. Clear the CFGS bit of the PMCON1 register.
3. Set the FREE and WREN bits of the PMCON1
register.
Disable Interrupts
(GIE = 0)
4. Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
5. Set control bit WR of the PMCON1 register to
begin the erase operation.
Select
Program or Configuration Memory
(CFGS)
See Example 11-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOPinstructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
Select Row Address
(PMADRH:PMADRL)
Select ERASE Operation
(FREE = 1)
Enable Write/Erase Operation
(WREN = 1)
Unlock Sequence
Figure 11-3
CPU stalls while
ERASE operation completes
(2ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
ERASE Operation
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 101
PIC16(L)F1516/7/8/9
EXAMPLE 11-2:
ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
; Not configuration space
; Specify an erase operation
; Enable writes
BSF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
NOP
NOP
; NOP instructions are forced as processor starts
; row erase of program memory.
;
; The processor stalls until the erase process is complete
; after erase processor continues with 3rd instruction
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
DS41452B-page 102
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
The following steps should be completed to load the
write latches and program a row of program memory.
These steps are divided into two parts. First, each write
latch is loaded with data from the PMDATH:PMDATL
using the unlock sequence with LWLO = 1. When the
last word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
11.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1. Load the address in PMADRH:PMADRL of the
row to be programmed.
2. Load each write latch with data.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Note:
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten. Pro-
gram memory can only be erased one row at a time. No
automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 11-5 (row writes to program memory with 32
write latches) for more details.
1. Set the WREN bit of the PMCON1 register.
2. Clear the CFGS bit of the PMCON1 register.
3. Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
The write latches are aligned to the Flash row address
boundary defined by the upper 10-bits of
PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>)
with the lower 5-bits of PMADRL, (PMADRL<4:0>)
determining the write latch being loaded. Write opera-
tions do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 11.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 11-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 103
FIGURE 11-5:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
7
6
0 7
5 4
0
7
5
0
7
0
-
-
PMADRH
PMADRL
PMDATH
6
PMDATL
8
-
r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 c4 c3 c2 c1 c0
14
Program Memory Write Latches
10
5
14
14
14
14
Write Latch #0
00h
Write Latch #1
01h
Write Latch #30 Write Latch #31
1Eh 1Fh
PMADRL<4:0>
14
14
14
14
Row
000h
001h
002h
Addr
Addr
Addr
Addr
0000h
0020h
0040h
0001h
0021h
0041h
001Eh
003Eh
005Eh
001Fh
003Fh
005Fh
CFGS = 0
3FEh
3FFh
7FC0h
7FE0h
7FC1h
7FE1h
7FDEh
7FFEh
7FDFh
7FFFh
Row
Address
Decode
PMADRH<6:0>
:PMADRL<7:5>
Flash Program Memory
400h
8000h - 8003h
USER ID 0 - 3
8004h - 8005h
reserved
8006h
8007h – 8008h
8009h - 801Fh
reserved
DEVICEID
REVID
Configuration
Words
CFGS = 1
Configuration Memory
PIC16(L)F1516/7/8/9
FIGURE 11-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
WRITE Operation
Determine number of words
to be written into Program or
Configuration Memory.
The number of words cannot
exceed the number of words
per row.
Enable Write/Erase
Operation (WREN = 1)
Load the value to write
(PMDATH:PMDATL)
(word_cnt)
Update the word counter
(word_cnt--)
Write Latches to Flash
Disable Interrupts
(LWLO = 0)
(GIE = 0)
Unlock Sequence
Figure 11-3
Select
Program or Config. Memory
(CFGS)
Yes
Last word to
write ?
CPU stalls while WRITE
operation completes
(2ms typical)
No
Select Row Address
(PMADRH:PMADRL)
Unlock Sequence
Figure 11-3
Select WRITE Operation
(FREE = 0)
Disable
Write/Erase Operation
(WREN = 0)
No delay when writing to
Program Memory Latches
Load Write Latches Only
(LWLO = 1)
Re-enable Interrupts
(GIE = 1)
Increment Address
(PMADRH:PMADRL++)
End
ERASE Operation
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 105
PIC16(L)F1516/7/8/9
EXAMPLE 11-3:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
BCF
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
; Disable ints so required sequences will execute properly
; Bank 3
; Load initial address
;
;
;
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
LOW DATA_ADDR ; Load initial data address
FSR0L
HIGH DATA_ADDR ; Load initial data address
;
FSR0H
;
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
; Not configuration space
; Enable writes
; Only Load Write Latches
BSF
BSF
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
; Load first data byte into lower
;
; Load second data byte into upper
;
MOVF
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
; Check if lower bits of address are '00000'
; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
XORLW
ANDLW
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor
; loads program memory write latches
;
NOP
NOP
INCF
GOTO
PMADRL,F
LOOP
; Still loading latches Increment address
; Write next latches
START_WRITE
BCF
PMCON1,LWLO
; No more loading latches - Actually start Flash program
; memory write
MOVLW
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
; Start of required write sequence:
; Write 55h
;
MOVWF
MOVLW
MOVWF
BSF
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
; to program memory.
NOP
NOP
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
; Disable writes
BCF
BSF
PMCON1,WREN
INTCON,GIE
; Enable interrupts
DS41452B-page 106
Preliminary
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PIC16(L)F1516/7/8/9
FIGURE 11-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
11.3 Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
Start
1. Load the starting address of the row to be
modified.
MODIFY Operation
2. Read the existing data from the row into a RAM
image.
READ Operation
Figure 11-2
3. Modify the RAM image to contain the new data
to be written into program memory.
4. Load the starting address of the row to be
rewritten.
An image of the entire row read
must be stored in RAM
5. Erase the program memory row.
6. Load the write latches with data from the RAM
image.
7. Initiate a programming operation.
Modify Image
The words to be modified are
changed in the RAM image
ERASE Operation
i
Figure 11-4
WRITE Operation
use RAM image
Figure 11-5
End
MODIFY Operation
2011 Microchip Technology Inc.
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DS41452B-page 107
PIC16(L)F1516/7/8/9
11.4 User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Words can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC<15> = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 11-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 11-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 11-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
8000h-8003h
8006h
User IDs
Yes
Yes
Yes
Yes
No
No
Device ID/Revision ID
Configuration Words 1 and 2
8007h-8008h
EXAMPLE 11-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
PROG_DATA_HI, PROG_DATA_LO
BANKSEL PMADRL
; Select correct Bank
;
; Store LSB of address
; Clear MSB of address
MOVLW
MOVWF
CLRF
PROG_ADDR_LO
PMADRL
PMADRH
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
; Select Configuration Space
; Disable interrupts
; Initiate read
; Executed (See Figure 11-2)
; Ignored (See Figure 11-2)
; Restore interrupts
INTCON,GIE
MOVF
PMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
PMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
DS41452B-page 108
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
11.5 Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 11-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
VERIFY Operation
This routine assumes that the last row
of data written was from an image
saved in RAM. This image will be used
to verify the data currently stored in
Flash Program Memory.
READ Operation
Figure 11-2
PMDAT =
RAM image
?
No
Fail
VERIFY Operation
Yes
No
Last
Word ?
Yes
End
VERIFY Operation
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 109
PIC16(L)F1516/7/8/9
11.6 Flash Program Memory Control Registers
REGISTER 11-1: PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMDAT<7:0>: Read/write value for Least Significant bits of program memory
REGISTER 11-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER
U-0
—
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
PMDAT<13:8>: Read/write value for Most Significant bits of program memory
REGISTER 11-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
PMADR<7:0>: Specifies the Least Significant bits for program memory address
REGISTER 11-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER
U-1
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘1’
PMADR<14:8>: Specifies the Most Significant bits for program memory address
bit 6-0
DS41452B-page 110
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 11-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
—
R/W-0/0
CFGS
R/W-0/0
LWLO
R/W/HC-0/0 R/W/HC-x/q(2)
FREE WRERR
R/W-0/0
WREN
R/S/HC-0/0
WR
R/S/HC-0/0
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
Unimplemented: Read as ‘1’
CFGS: Configuration Select bit
1= Access Configuration, User ID and Device ID Registers
0= Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1= Only the addressed program memory write latch is loaded/updated on the next WR command
0= The addressed program memory write latch is loaded/updated and a write of all program memory write latches
will be initiated on the next WR command
bit 4
bit 3
FREE: Program Flash Erase Enable bit
1= Performs an erase operation on the next WR command (hardware cleared upon completion)
0= Performs an write operation on the next WR command
WRERR: Program/Erase Error Flag bit
1= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically
on any set attempt (write ‘1’) of the WR bit).
0= The program or erase operation completed normally.
bit 2
bit 1
WREN: Program/Erase Enable bit
1= Allows program/erase cycles
0= Inhibits programming/erasing of program Flash
WR: Write Control bit
1= Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0= Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit
1= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set
(not cleared) in software.
0= Does not initiate a program Flash read.
Note 1: Unimplemented bit, read as ‘1’.
2: The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1) .
3: The LWLO bit is ignored during a program memory erase operation (FREE = 1).
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 111
PIC16(L)F1516/7/8/9
REGISTER 11-6: PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Program Memory Control Register 2
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
S = Bit can only be set
‘1’ = Bit is set
bit 7-0
Flash memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMCON1
PMCON2
PMADRL
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
—
111
112
110
110
110
110
80
Program Memory Control Register 2
PMADRL<7:0>
PMADRH
PMDATL
—
PMADRH<6:0>
PMDATL<7:0>
PMDATH
INTCON
Legend:
—
—
PMDATH<5:0>
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash Program Memory module.
TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
FCMEN
PWRTE
LVP
IESO
CLKOUTEN
BOREN<1:0>
—
CONFIG1
46
48
CP
—
MCLRE
—
WDTE<1:0>
FOSC<2:0>
STVREN
13:8
7:0
DEBUG
—
—
BORV
—
—
CONFIG2
—
VCAPEN(1)
WRT<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
DS41452B-page 112
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 12-1:
GENERIC I/O PORT
OPERATION
12.0 I/O PORTS
In general, when a peripheral is enabled, that pin may
not be used as a general purpose I/O pin.
Each port has three standard registers for its operation.
These registers are:
Read LATx
TRISx
• TRISx registers (data direction)
D
Q
• PORTx registers (reads the levels on the pins of
the device)
Write LATx
Write PORTx
• LATx registers (output latch)
CK
Data Register
VDD
Some ports may have one or more of the following
additional registers. These registers are:
Data Bus
Read PORTx
• ANSELx (analog select)
• WPUx (weak pull-up)
I/O pin
To peripherals
VSS
TABLE 12-1: PORT AVAILABILITY PER
DEVICE
ANSELx
EXAMPLE 12-1:
INITIALIZING PORTA
Device
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
PIC16(L)F1516/8
PIC16(L)F1517/9
●
●
●
●
●
●
●
●
●
The Data Latch (LATx register) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
BANKSEL PORTA
CLRF PORTA
BANKSEL LATA
CLRF LATA
BANKSEL ANSELA
CLRF ANSELA
BANKSEL TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
A write operation to the LATx register has the same
affect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
MOVLW
MOVWF
B'00111000' ;Set RA<5:3> as inputs
TRISA
;and set RA<2:0> as
;outputs
The port has analog functions and has an ANSELx
register which can disable the digital input and save
power. A simplified model of a generic I/O port, without
the interfaces to other peripherals, is shown in
Figure 12-1.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 113
PIC16(L)F1516/7/8/9
12.1 Alternate Pin Function
The Alternate Pin Function Control (APFCON)
registers are used to steer specific peripheral input and
output functions between different pins. The APFCON
registers are shown in Register 12-1. For this device
family, the following functions can be moved between
different pins.
• SS (Slave Select)
• CCP2
These bits have no effect on the values of any TRIS
register. PORT and TRIS overrides will be routed to the
correct pin. The unselected pin will be unaffected.
REGISTER 12-1: APFCON: ALTERNATE PIN FUNCTION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0/0
SSSEL
R/W-0/0
CCP2SEL
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
bit 1
Unimplemented: Read as ‘0’
SSSEL: Pin Selection bit
0= SS function is on RA5
1= SS function is on RA0
bit 0
CCP2SEL: Pin Selection bit
0= CCP2 function is on RC1
1= CCP2 function is on RB3
DS41452B-page 114
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.2.2
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
12.2 PORTA Registers
PORTA is
a 8-bit wide, bidirectional port. The
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-2.
corresponding data direction register is TRISA
(Register 12-3). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 12-1 shows how to
initialize an I/O port.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input functions, such as ADC, are not shown in
the priority lists. These inputs are active when the I/O
pin is set for Analog mode using the ANSELx registers.
Digital output functions may control the pin when it is in
Analog mode with the priority shown in Table 12-2.
Reading the PORTA register (Register 12-2) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
TABLE 12-2: PORTA OUTPUT PRIORITY
Pin Name
Function Priority(1)
The TRISA register (Register 12-3) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits
in the TRISA register are maintained set when using
them as analog inputs. I/O pins configured as analog
input always read ‘0’.
RA0
RA1
RA2
RA3
RA4
RA5
RA0
RA1
RA2
RA3
RA4
VCAP (PIC16F151X only)
RA5
12.2.1
ANSELA REGISTER
The ANSELA register (Register 12-5) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
RA6
CLKOUT
OSC2
RA6
RA7
RA7
Note 1: Priority listed from highest to lowest.
The state of the ANSELA bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 115
PIC16(L)F1516/7/8/9
REGISTER 12-2: PORTA: PORTA REGISTER
R/W-x/x
RA7
R/W-x/x
RA6
R/W-x/x
RA5
R/W-x/x
RA4
R/W-x/x
RA3
R/W-x/x
RA2
R/W-x/x
RA1
R/W-x/x
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RA<7:0>: PORTA I/O Value bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is the
return of actual I/O pin values.
REGISTER 12-3: TRISA: PORTA TRI-STATE REGISTER
R/W-1/1
TRISA7
R/W-1/1
TRISA6
R/W-1/1
TRISA5
R/W-1/1
TRISA4
R/W-1/1
TRISA3
R/W-1/1
TRISA2
R/W-1/1
TRISA1
R/W-1/1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISA<7:0>: PORTA Tri-State Control bits
1= PORTA pin configured as an input (tri-stated)
0= PORTA pin configured as an output
DS41452B-page 116
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-4: LATA: PORTA DATA LATCH REGISTER
R/W-x/u
LATA7
R/W-x/u
LATA6
R/W-x/u
LATA5
R/W-x/u
LATA4
R/W-x/u
LATA3
R/W-x/u
LATA2
R/W-x/u
LATA1
R/W-x/u
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-4
LATA<7:0>: PORTA Output Latch Value bits(1)
Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is the
return of actual I/O pin values.
REGISTER 12-5: ANSELA: PORTA ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSA5
U-0
—
R/W-1/1
ANSA3
R/W-1/1
ANSA2
R/W-1/1
ANSA1
R/W-1/1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
Unimplemented: Read as ‘0’
ANSA5: Analog Select between Analog or Digital Function on pins RA5, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 4
Unimplemented: Read as ‘0’
bit 3-0
ANSA<3:0>: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 117
PIC16(L)F1516/7/8/9
TABLE 12-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Register
on Page
Name
ANSELA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
ANSA5
—
ANSA3
ANSA2
ANSA1
ANSA0
117
114
117
157
116
116
APFCON
LATA
—
—
—
—
—
—
SSSEL
LATA1
PS<2:0>
RA1
CCP2SEL
LATA0
LATA7
WPUEN
RA7
LATA6
INTEDG
RA6
LATA5
TMR0CS
RA5
LATA4
TMR0SE
RA4
LATA3
PSA
LATA2
OPTION_REG
PORTA
RA3
RA2
RA0
TRISA
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend:
x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH PORTA
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
13:8
7:0
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0.>
FOSC<2:0>
—
CONFIG1
46
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
DS41452B-page 118
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.3.2
PORTB FUNCTIONS AND OUTPUT
PRIORITIES
12.3 PORTB Registers
PORTB is
a 8-bit wide, bidirectional port. The
Each PORTB pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-5.
corresponding data direction register is TRISB
(Register 12-7). Setting a TRISB bit (= 1) will make the
corresponding PORTB pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISB bit (= 0) will make the corresponding
PORTB pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in Table 12-5.
Reading the PORTB register (Register 12-6) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATB).
TABLE 12-5: PORTB OUTPUT PRIORITY
Pin Name
Function Priority(1)
RB0
RB1
RB2
RB3
RB0
RB1
RB2
The TRISB register (Register 12-7) controls the PORTB
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISB register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
CCP2
RB3
RB4
RB5
RB6
RB4
RB5
12.3.1
ANSELB REGISTER
The ANSELB register (Register 12-9) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELB bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
ICDCLK
RB6
RB7
ICDDAT
RB7
Note 1: Priority listed from highest to lowest.
The state of the ANSELB bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSELB set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
Note:
The ANSELB register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 119
PIC16(L)F1516/7/8/9
REGISTER 12-6: PORTB: PORTB REGISTER
R/W-x/u
RB7
R/W-x/u
RB6
R/W-x/u
RB5
R/W-x/u
RB4
R/W-x/u
RB3
R/W-x/u
RB2
R/W-x/u
RB1
R/W-x/u
RB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RB<7:0>: PORTB General Purpose I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the
return of actual I/O pin values.
REGISTER 12-7: TRISB: PORTB TRI-STATE REGISTER
R/W-1/1
TRISB7
R/W-1/1
TRISB6
R/W-1/1
TRISB5
R/W-1/1
TRISB4
R/W-1/1
TRISB3
R/W-1/1
TRISB2
R/W-1/1
TRISB1
R/W-1/1
TRISB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISB<7:0>: PORTB Tri-State Control bits
1= PORTB pin configured as an input (tri-stated)
0= PORTB pin configured as an output
REGISTER 12-8: LATB: PORTB DATA LATCH REGISTER
R/W-x/u
LATB7
R/W-x/u
LATB6
R/W-x/u
LATB5
R/W-x/u
LATB4
R/W-x/u
LATB3
R/W-x/u
LATB2
R/W-x/u
LATB1
R/W-x/u
LATB0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATB<7:0>: PORTB Output Latch Value bits(1)
Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is the
return of actual I/O pin values.
DS41452B-page 120
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-9: ANSELB: PORTB ANALOG SELECT REGISTER
U-0
—
U-0
—
R/W-1/1
ANSB5
R/W-1/1
ANSB4
R/W-1/1
ANSB3
R/W-1/1
ANSB2
R/W-1/1
ANSB1
R/W-1/1
ANSB0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ANSB<5:0>: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
REGISTER 12-10: WPUB: WEAK PULL-UP PORTB REGISTER
R/W-1/1
WPUB7
R/W-1/1
WPUB6
R/W-1/1
WPUB5
R/W-1/1
WPUB4
R/W-1/1
WPUB3
R/W-1/1
WPUB2
R/W-1/1
WPUB1
R/W-1/1
WPUB0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
WPUB<7:0>: Weak Pull-up Register bits
1= Pull-up enabled
0= Pull-up disabled
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
—
—
—
—
ANSB5
—
ANSB4
—
ANSB3
—
ANSB2
—
ANSB1
SSSEL
LATB1
ANSB0
CCP2SEL
LATB0
121
114
120
157
APFCON
LATB
LATB7
WPUEN
LATB6
INTEDG
LATB5
TMR0CS
LATB4
TMR0SE
LATB3
PSA
LATB2
OPTION_REG
PS<2:0>
PORTB
TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
120
120
121
TRISB7
WPUB7
TRISB6
WPUB6
TRISB5
WPUB5
TRISB4
WPUB4
TRISB3
WPUB3
TRISB2
WPUB2
TRISB1
WPUB1
TRISB0
WPUB0
WPUB
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 121
PIC16(L)F1516/7/8/9
12.4.2
PORTC FUNCTIONS AND OUTPUT
PRIORITIES
12.4 PORTC Registers
PORTC is
a 8-bit wide bidirectional port. The
Each PORTC pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 12-7.
corresponding data direction register is TRISC
(Register 12-12). Setting a TRISC bit (= 1) will make the
corresponding PORTC pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISC bit (= 0) will make the corresponding
PORTC pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Analog input and some digital input functions are not
included in the list below. These input functions can
remain active when the pin is configured as an output.
Certain digital input functions override other port
functions and are included in Table 12-7.
Reading the PORTC register (Register 12-11) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATC).
TABLE 12-7: PORTC OUTPUT PRIORITY
Pin Name
Function Priority(1)
RC0
SOSCO
RC0
The TRISC register (Register 12-12) controls the
PORTC pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISC register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
RC1
SOSCI
CCP2
RC1
RC2
RC3
CCP1
RC2
12.4.1
ANSELC REGISTER
SCL
The ANSELC register (Register 12-14) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELC bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
SCK
RC3(2)
RC4
RC5
RC6
SDA
RC4(2)
SDO
RC5
The state of the ANSELC bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSELC set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
CK
TX
RC6
RC7
DT
RC7
Note:
The ANSELC register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
Note 1: Priority listed from highest to lowest.
2: RC3 and RC4 read the I2C ST input when
I2C mode is enabled.
DS41452B-page 122
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-11: PORTC: PORTC REGISTER
R/W-x/u
RC7
R/W-x/u
RC6
R/W-x/u
RC5
R/W-x/u
RC4
R/W-x/u
RC3
R/W-x/u
RC2
R/W-x/u
RC1
R/W-x/u
RC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RC<7:0>: PORTC General Purpose I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the
return of actual I/O pin values.
REGISTER 12-12: TRISC: PORTC TRI-STATE REGISTER
R/W-1/1
TRISC7
R/W-1/1
TRISC6
R/W-1/1
TRISC5
R/W-1/1
TRISC4
R/W-1/1
TRISC3
R/W-1/1
TRISC2
R/W-1/1
TRISC1
R/W-1/1
TRISC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISC<7:0>: PORTC Tri-State Control bits
1= PORTC pin configured as an input (tri-stated)
0= PORTC pin configured as an output
REGISTER 12-13: LATC: PORTC DATA LATCH REGISTER
R/W-x/u
LATC7
R/W-x/u
LATC6
R/W-x/u
LATC5
R/W-x/u
LATC4
R/W-x/u
LATC3
R/W-x/u
LATC2
R/W-x/u
LATC1
R/W-x/u
LATC0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATC<7:0>: PORTC Output Latch Value bits(1)
Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is the
return of actual I/O pin values.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 123
PIC16(L)F1516/7/8/9
REGISTER 12-14: ANSELC: PORTC ANALOG SELECT REGISTER
R/W-1/1
ANSC7
R/W-1/1
ANSC6
R/W-1/1
ANSC3
R/W-1/1
ANSC3
R/W-1/1
ANSC3
R/W-1/1
ANSC2
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
ANSC<7:2>: Analog Select between Analog or Digital Function on pins RC<7:2>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
bit 1-0
Unimplemented: Read as ‘0’
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELC
ANSC7
—
ANSC6
—
ANSC5
—
ANSC4
—
ANSC3
—
ANSC2
—
—
—
CCP2SEL
LATC0
121
114
120
120
120
APFCON
SSSEL
LATC1
RC1
LATC
LATC7
RC7
LATC6
RC6
LATC5
RC5
LATC4
RC4
LATC3
RC3
LATC2
RC2
PORTC
TRISC
Legend:
RC0
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
DS41452B-page 124
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
12.5.2
PORTD FUNCTIONS AND OUTPUT
PRIORITIES
12.5 PORTD Registers
(PIC16F1517/1519 only)
PORTD has no peripheral outputs, so the PORTD
output has no priority function.
PORTD is
a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISD
(Register 12-16). Setting a TRISD bit (= 1) will make the
corresponding PORTD pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISD bit (= 0) will make the corresponding
PORTD pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
Example 12-1 shows how to initialize an I/O port.
Reading the PORTD register (Register 12-15) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then written
to the PORT data latch (LATD).
The TRISD register (Register 12-16) controls the
PORTD pin output drivers, even when they are being
used as analog inputs. The user should ensure the bits in
the TRISD register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
12.5.1
ANSELD REGISTER
The ANSELD register (Register 12-18) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELD bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELD bits has no affect on digital out-
put functions. A pin with TRIS clear and ANSELD set will
still operate as a digital output, but the Input mode will be
analog. This can cause unexpected behavior when exe-
cuting read-modify-write instructions on the affected
port.
Note:
The ANSELD register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 125
PIC16(L)F1516/7/8/9
REGISTER 12-15: PORTD: PORTD REGISTER
R/W-x/u
RD7
R/W-x/u
RD6
R/W-x/u
RD5
R/W-x/u
RD4
R/W-x/u
RD3
R/W-x/u
RD2
R/W-x/u
RD1
R/W-x/u
RD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
RD<7:0>: PORTD General Purpose I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is the
return of actual I/O pin values.
REGISTER 12-16: TRISD: PORTD TRI-STATE REGISTER
R/W-1/1
TRISD7
R/W-1/1
TRISD6
R/W-1/1
TRISD5
R/W-1/1
TRISD4
R/W-1/1
TRISD5
R/W-1/1
TRISD5
R/W-1/1
TRISD5
R/W-1/1
TRISD4
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
TRISD<7:0>: PORTD Tri-State Control bits
1= PORTD pin configured as an input (tri-stated)
0= PORTD pin configured as an output
REGISTER 12-17: LATD: PORTD DATA LATCH REGISTER
R/W-x/u
LATD7
R/W-x/u
LATD6
R/W-x/u
LATD5
R/W-x/u
LATD4
R/W-x/u
LATD3
R/W-x/u
LATD2
R/W-x/u
LATD1
R/W-x/u
LATD0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
LATD<7:0>: PORTD Output Latch Value bits(1)
Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is the
return of actual I/O pin values.
DS41452B-page 126
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-18: ANSELD: PORTD ANALOG SELECT REGISTER
R/W-1/1
ANSD7
R/W-1/1
ANSD6
R/W-1/1
ANSD5
R/W-1/1
ANSD4
R/W-1/1
ANSD3
R/W-1/1
ANSD2
R/W-1/1
ANSD1
R/W-1/1
ANSD0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
ANSD<7:0>: Analog Select between Analog or Digital Function on pins RD<7:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external
control of the voltage on the pin.
TABLE 12-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELD
ANSD7
LATD7
RD7
ANSD6
LATD6
RD6
ANSD5
LATD5
RD5
ANSD4
LATD4
RD4
ANSD3
LATD3
RD3
ANSD2
LATD2
RD2
ANSD1
LATD1
RD1
ANSD0
LATD0
RD0
121
120
120
120
LATD
PORTD
TRISD
TRISD7
TRISD6
TRISB5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
Legend:
x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1:
PIC16F1517/1519 only.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 127
PIC16(L)F1516/7/8/9
12.6.2
PORTE FUNCTIONS AND OUTPUT
PRIORITIES
12.6 PORTE Registers
PORTE is
a 4-bit wide, bidirectional port. The
PORTE has no peripheral outputs, so the PORTE
output has no priority function.
corresponding data direction register is TRISE. Setting a
TRISE bit (= 1) will make the corresponding PORTE pin
an input (i.e., put the corresponding output driver in a
High-Impedance mode). Clearing a TRISE bit (= 0) will
make the corresponding PORTE pin an output (i.e.,
enable the output driver and put the contents of the
output latch on the selected pin). The exception is RE3,
which is input only and its TRIS bit will always read as
‘1’. Example 12-1 shows how to initialize an I/O port.
Reading the PORTE register (Register 12-19) reads
the status of the pins, whereas writing to it will write to
the PORT latch. All write operations are
read-modify-write operations. Therefore, a write to a
port implies that the port pins are read, this value is
modified and then written to the PORT data latch
(LATE). RE3 reads ‘0’ when MCLRE = 1.
Note:
RE<2:0> and TRISE<2:0> pins are
available on PIC16(L)F1517/9 only.
12.6.1
ANSELE REGISTER
The ANSELE register (Register 12-22) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELE bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELE bits has no affect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
The TRISE register (Register 12-20) controls the PORTE
pin output drivers, even when they are being used as
analog inputs. The user should ensure the bits in the
TRISE register are maintained set when using them as
analog inputs. I/O pins configured as analog input always
read ‘0’.
Note:
The ANSELE register must be initialized
to configure an analog channel as a digital
input. Pins configured as analog inputs
will read ‘0’.
DS41452B-page 128
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-19: PORTE: PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-x/u
RE3
R/W-x/u
RE2(1)
R/W-x/u
RE1(1)
R/W-x/u
RE0(1)
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
RE<3:0>: PORTE I/O Pin bits(1)
1= Port pin is > VIH
0= Port pin is < VIL
Note 1: RE<2:0> are not implemented on the PIC16(L)F1516/8. Read as ‘0’. Writes to RE<2:0> are actually writ-
ten to corresponding LATE register. Reads from PORTE register is the return of actual I/O pin values.
REGISTER 12-20: TRISE: PORTE TRI-STATE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-1(2)
—
R/W-1
TRISE2(1)
R/W-1
TRISE1(1)
R/W-1
TRISE0(1)
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
Unimplemented: Read as ‘1’
bit 2-0
TRISE<2:0>: RE<2:0> Tri-State Control bits(1)
1= PORTE pin configured as an input (tri-stated)
0= PORTE pin configured as an output
Note 1: TRISE<2:0> are not implemented on the PIC16(L)F1517/9. Read as ‘0’.
2: Unimplemented, read as ‘1’.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 129
PIC16(L)F1516/7/8/9
REGISTER 12-21: LATE: PORTE DATA LATCH REGISTER(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x/u
LATE2
R/W-x/u
LATE1
R/W-x/u
LATE0
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
LATE<2:0>: PORTE Output Latch Value bits(1)
Note 1: Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is the
return of actual I/O pin values.
2: PIC16(L)F1517/9 only.
REGISTER 12-22: ANSELE: PORTE ANALOG SELECT REGISTER(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
ANSE2
ANSE1
ANSE0
bit 7
bit 0
Legend:
R = Readable bit
u = bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
ANSE<2:0>: Analog Select between Analog or Digital Function on pins RE<2:0>, respectively
0= Digital I/O. Pin is assigned to port or digital special function.
1= Analog input. Pin is assigned as analog input(1). Digital input buffer disabled.
Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to
allow external control of the voltage on the pin.
2: PIC16(L)F1517/9 only.
DS41452B-page 130
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 12-23: WPUE: WEAK PULL-UP PORTE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1/1
WPUE3
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-4
bit 3
Unimplemented: Read as ‘0’
WPUE: Weak Pull-up Register bit
1= Pull-up enabled
0= Pull-up disabled
bit 2-0
Unimplemented: Read as ‘0’
Note 1: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in configured as an output.
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CHS<4:0>
—
147
130
184
130
129
129
131
ADCON0
ANSELE(1)
CCPxCON
LATE
—
—
—
—
—
—
—
GO/DONE ADON
ANSE1 ANSE0
—
—
—
—
—
—
—
—
ANSE2
DCxB<1:0>
CCPxM<3:0>
LATE2(1) LATE1(1) LATE0(1)
RE2(1) RE1(1) RE0(1)
TRISE2(1) TRISE1(1) TRISE0(1)
—
RE3
—
—
—
—
—
—
—
—
PORTE
TRISE
‘1’
WPUE
WPUE3
—
—
—
Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTE.
Note 1: These bits are not implemented on the PIC16(L)F1516/8 devices, read as ‘0’.
TABLE 12-11: SUMMARY OF CONFIGURATION WORD WITH PORTE
Register
on Page
Name
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
Bit 10/2
Bit 9/1
Bit 8/0
FCMEN
PWRTE
IESO
CLKOUTEN
BOREN<1:0>
FOSC<2:0>
13:8
7:0
—
CONFIG1
46
CP
MCLRE
WDTE<1:0>
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.
2010 Microchip Technology Inc.
Preliminary
DS41452B-page 131
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 132
Preliminary
2010 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
13.3 Interrupt Flags
13.0 INTERRUPT-ON-CHANGE
The IOCBFx bits located in the IOCBF register are
status flags that correspond to the Interrupt-on-change
pins of PORTB. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCBFx bits.
The PORTB pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTB pin, or
combination of PORTB pins, can be configured to
generate an interrupt. The interrupt-on-change module
has the following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
13.4 Clearing Interrupt Flags
• Rising and falling edge detection
• Individual pin interrupt flags
The individual status flags, (IOCBFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
Figure 13-1 is a block diagram of the IOC module.
13.1 Enabling the Module
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
To allow individual PORTB pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
EXAMPLE 13-1:
13.2 Individual Pin Configuration
MOVLW 0xff
XORWF IOCBF, W
ANDWF IOCBF, F
For each PORTB pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCBPx bit of the IOCBP
register is set. To enable a pin to detect a falling edge,
the associated IOCBNx bit of the IOCBN register is set.
13.5 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCBPx bit
and the IOCBNx bit of the IOCBP and IOCBN registers,
respectively.
If an edge is detected while in Sleep mode, the IOCBF
register will be updated prior to the first instruction
executed out of Sleep.
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
FIGURE 13-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
Q4Q1
IOCBNx
D
Q
CK
edge
detect
R
RBx
data bus =
0 or 1
S
to data bus
IOCBFx
IOCBPx
D
Q
D
Q
write IOCBFx
CK
CK
IOCIE
R
Q2
from all other
IOCBFx individual
pin detectors
IOC interrupt
to CPU core
Q1
Q1
Q1
Q2
Q3
Q2
Q2
Q3
Q3
Q4
Q4
Q4Q1
Q4
Q4
Q4Q1
Q4Q1
Q4Q1
DS41452B-page 134
Preliminary
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13.6 Interrupt-On-Change Registers
REGISTER 13-1: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER
R/W-0/0
IOCBP7
R/W-0/0
IOCBP6
R/W-0/0
IOCBP5
R/W-0/0
IOCBP4
R/W-0/0
IOCBP3
R/W-0/0
IOCBP2
R/W-0/0
IOCBP1
R/W-0/0
IOCBP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt
flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-2: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER
R/W-0/0
IOCBN7
R/W-0/0
IOCBN6
R/W-0/0
IOCBN5
R/W-0/0
IOCBN4
R/W-0/0
IOCBN3
R/W-0/0
IOCBN2
R/W-0/0
IOCBN1
R/W-0/0
IOCBN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits
1= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt
flag will be set upon detecting an edge.
0= Interrupt-on-Change disabled for the associated pin.
REGISTER 13-3: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER
R/W/HS-0/0
IOCBF7
R/W/HS-0/0
IOCBF6
R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0
R/W/HS-0/0
IOCBF2
R/W/HS-0/0 R/W/HS-0/0
IOCBF1 IOCBF0
bit 0
IOCBF5
IOCBF4
IOCBF3
bit 7
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
-n/n = Value at POR and BOR/Value at all other Resets
HS - Bit is set in hardware
bit 7-0
IOCBF7:0>: Interrupt-on-Change PORTB Flag bits
1= An enabled change was detected on the associated pin.
Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling edge
was detected on RBx.
0= No change was detected, or the user cleared the detected change.
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TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
INTCON
IOCBF
ANSB7
GIE
ANSB6
PEIE
ANSB5
ANSB4
INTE
ANSB3
IOCIE
ANSB2
ANSB1
INTF
ANSB0
IOCIF
117
80
TMR0IE
TMR0IF
IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0
IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0
IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
135
135
135
116
IOCBN
IOCBP
TRISB
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
DS41452B-page 136
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14.1 Independent Gain Amplifiers
14.0 FIXED VOLTAGE REFERENCE
(FVR)
The output of the FVR supplied to the ADC module is
routed through a programmable gain amplifier. The
amplifier can be configured to amplify the reference
voltage by 1x, 2x or 4x, to produce the three possible
voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR<1:0> bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Refer-
ence Section 16.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
• ADC positive reference
• Comparator positive input
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
14.2 FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 25.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 14-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR<1:0>
2
x1
x2
x4
FVR BUFFER1
(To ADC Module)
1.024V Fixed
Reference
+
-
FVREN
FVRRDY
Any peripheral requiring
the Fixed Reference
(See Table 14-1)
TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
Conditions
Description
HFINTOSC
FOSC<2:0> = 100and
IRCF<3:0> = 000x
INTOSC is active and device is not in Sleep
BOREN<1:0> = 11
BOR always enabled
BOR
LDO
BOREN<1:0> = 10and BORFS = 1
BOREN<1:0> = 01and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOR under software control, BOR Fast Start enabled
All PIC16F151X devices, when
VREGPM = 1and not in Sleep
The device runs off of the low-power regulator when in Sleep
mode.
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14.3 FVR Control Registers
REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
FVREN
R-q/q
FVRRDY(1)
R/W-0/0
TSEN
R/W-0/0
TSRNG
U-0
—
U-0
—
R/W-0/0
R/W-0/0
ADFVR<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
bit 6
bit 5
bit 4
FVREN: Fixed Voltage Reference Enable bit
0= Fixed Voltage Reference is disabled
1= Fixed Voltage Reference is enabled
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
0= Fixed Voltage Reference output is not ready or not enabled
1= Fixed Voltage Reference output is ready for use
TSEN: Temperature Indicator Enable bit
0= Temperature Indicator is disabled
1= Temperature Indicator is enabled
TSRNG: Temperature Indicator Range Selection bit
0= VOUT = VDD - 2VT (Low Range)
1= VOUT = VDD - 4VT (High Range)
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
ADFVR<1:0>: ADC Fixed Voltage Reference Selection bits
00= ADC Fixed Voltage Reference Peripheral output is off
01= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
10= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
11= ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
Note 1: FVRRDY is always ‘1’ on PIC16F151X only.
2: Fixed Voltage Reference output cannot exceed VDD.
TABLE 14-2: SUMMARYOF REGISTERS ASSOCIATED WITH THE FIXED VOLTAGE REFERENCE
Register
on page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADFVR<1:0>
138
Legend:
Shaded cells are unused by the Fixed Voltage Reference module.
DS41452B-page 138
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 15-1:
TEMPERATURE CIRCUIT
DIAGRAM
15.0 TEMPERATURE INDICATOR
MODULE
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between of -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
VDD
TSEN
TSRNG
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A one-
point calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
VOUT
ADC
MUX
ADC
n
CHS bits
(ADCON0 register)
15.1 Circuit Operation
15.2 Minimum Operating VDD vs.
Minimum Sensing Temperature
Figure 15-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
Equation 15-1 describes the output characteristics of
the temperature indicator.
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
EQUATION 15-1: VOUT RANGES
High Range: VOUT = VDD - 4VT
Low Range: VOUT = VDD - 2VT
Table 15-1 shows the recommended minimum VDD vs.
range setting.
TABLE 15-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 14.0 “Fixed Voltage Reference (FVR)” for
more information.
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
15.3 Temperature Output
The output of the circuit is measured using the internal
analog to digital converter. A channel is reserved for the
temperature circuit output. Refer to Section 16.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
15.4 ADC Aquisition Time
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
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NOTES:
DS41452B-page 140
Preliminary
2011 Microchip Technology Inc.
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The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
16.0 ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) allows
conversion of an analog input signal to a 10-bit binary
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESH:ADRESL register pair).
Figure 16-1 shows the block diagram of the ADC.
The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
FIGURE 16-1:
ADC BLOCK DIAGRAM
VDD
ADPREF = 0x
FVR ADPREF = 11
VREF+
ADPREF = 10
AN0
AN1
AN2
00000
00001
00010
00011
VREF+/AN3
ADC
10
GO/DONE
AN27
11011
11100
11101
11110
11111
0= Left Justify
ADFM
Reserved
1= Right Justify
ADON(1)
16
Reserved
Temp Indicator
ADRESH ADRESL
VSS
FVR Buffer1
CHS<4:0>(2)
Note 1: When ADON = 0, all multiplexer inputs are disconnected.
2: See ADCON0 register (Register 16-1) for detailed analog channel selection per device.
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16.1.4
CONVERSION CLOCK
16.1 ADC Configuration
The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
are seven possible clock options:
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• FOSC/2
• Channel selection
• FOSC/4
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• FOSC/8
• FOSC/16
• FOSC/32
• Result formatting
• FOSC/64
16.1.1
PORT CONFIGURATION
• FRC (dedicated internal oscillator)
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 12.0 “I/O Ports” for more information.
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD peri-
ods as shown in Figure 16-2.
For correct conversion, the appropriate TAD specifica-
tion must be met. Refer to the A/D conversion require-
ments in Section 25.0 “Electrical Specifications” for
more information. Table 16-1 gives examples of appro-
priate ADC clock selections.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
16.1.2
CHANNEL SELECTION
There are up to 30 channel selections available:
• AN<19:8, 4:0> pins (PIC16(L)F1516/8 only)
• AN<27:0> pins (PIC16(L)F1517/9 only)
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Refer to Section 14.0 “Fixed Voltage Reference
(FVR)” and Section 15.0 “Temperature Indicator
Module” for more information on these channel selec-
tions.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 16.2
“ADC Operation” for more information.
16.1.3
ADC VOLTAGE REFERENCE
The ADPREF bits of the ADCON1 register provides
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR 2.048V
• FVR 4.096V (Not available on LF devices)
See Section 14.0 “Fixed Voltage Reference (FVR)”
for more details on the fixed voltage reference.
DS41452B-page 142
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TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
ADCS<2:0>
Clock Source
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
Fosc/4
Fosc/8
Fosc/16
Fosc/32
Fosc/64
FRC
000
100
001
101
010
110
x11
100 ns(2)
200 ns(2)
400 ns(2)
800 ns
125 ns(2)
250 ns(2)
0.5 s(2)
1.0 s
250 ns(2)
500 ns(2)
1.0 s
500 ns(2)
1.0 s
2.0 s
4.0 s
8.0 s(3)
16.0 s(3)
32.0 s(3)
64.0 s(3)
2.0 s
2.0 s
4.0 s
1.6 s
2.0 s
4.0 s
8.0 s(3)
8.0 s(3)
16.0 s(3)
3.2 s
4.0 s
1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 1.6 s for VDD.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is
derived from the system clock FOSC. However, the FRC clock source must be used when conversions are
to be performed with the device in Sleep mode.
FIGURE 16-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD
TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
TAD1 TAD2 TAD3 TAD4 TAD5
b7
b6
b4
b1
b0
b9
b8
b3
b2
b5
Conversion starts
Holding capacitor is disconnected from analog input (typically 100 ns)
Set GO bit
On the following cycle:
ADRESH:ADRESL is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is connected to analog input.
2011 Microchip Technology Inc.
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16.1.5
INTERRUPTS
16.1.6
RESULT FORMATTING
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 16-3 shows the two output formats.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEPinstruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
FIGURE 16-3:
10-BIT A/D CONVERSION RESULT FORMAT
ADRESH
ADRESL
LSB
(ADFM = 0)
MSB
bit 7
bit 0
bit 0
bit 7
bit 7
bit 0
10-bit A/D Result
Unimplemented: Read as ‘0’
(ADFM = 1)
MSB
LSB
bit 0
bit 7
Unimplemented: Read as ‘0’
10-bit A/D Result
DS41452B-page 144
Preliminary
2011 Microchip Technology Inc.
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16.2.4
ADC OPERATION DURING SLEEP
16.2 ADC Operation
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
16.2.1
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON0 register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON0 register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the ADC.
Refer to Section 16.2.6 “A/D Conver-
sion Procedure”.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
sion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
16.2.2
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
16.2.5
SPECIAL EVENT TRIGGER
• Update the ADRESH and ADRESL registers with
new conversion result
The Special Event Trigger of the CCPx/ECCPX module
allows periodic ADC measurements without software
intervention. When this trigger occurs, the GO/DONE
bit is set by hardware and the Timer1 counter resets to
zero.
16.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRESH and ADRESL registers will be updated with
the partially complete Analog-to-Digital conversion
sample. Incomplete bits will match the last bit
converted.
TABLE 16-2: SPECIAL EVENT TRIGGER
Device
CCP
PIC16(L)F151X
CCP2
Using the Special Event Trigger does not assure proper
ADC timing. It is the user’s responsibility to ensure that
the ADC timing requirements are met.
Note:
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
Refer to Section 20.0 “Capture/Compare/PWM
Modules” for more information.
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
16.2.6
A/D CONVERSION PROCEDURE
EXAMPLE 16-1:
A/D CONVERSION
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
;This code block configures the ADC
;for polling, Vdd and Vss references, Frc
;clock and AN0 input.
;
;Conversion start & polling for completion
; are included.
;
1. Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
BANKSEL
MOVLW
ADCON1
;
B’11110000’ ;Right justify, Frc
;clock
2. Configure the ADC module:
• Select ADC conversion clock
• Configure voltage reference
• Select ADC input channel
• Turn on ADC module
MOVWF
BANKSEL
BSF
BANKSEL
BSF
BANKSEL
MOVLW
MOVWF
CALL
ADCON1
TRISA
TRISA,0
ANSEL
ANSEL,0
ADCON0
;Vdd and Vss Vref
;
;Set RA0 to input
;
;Set RA0 to analog
;
3. Configure ADC interrupt (optional):
• Clear ADC interrupt flag
B’00000001’ ;Select channel AN0
ADCON0
SampleTime
;Turn ADC On
;Acquisiton delay
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
4. Wait the required acquisition time(2)
BSF
BTFSC
GOTO
BANKSEL
MOVF
MOVWF
BANKSEL
MOVF
ADCON0,ADGO ;Start conversion
ADCON0,ADGO ;Is conversion done?
$-1
ADRESH
;No, test again
;
.
5. Start conversion by setting the GO/DONE bit.
ADRESH,W
RESULTHI
ADRESL
;Read upper 2 bits
;store in GPR space
;
6. Wait for ADC conversion to complete by one of
the following:
ADRESL,W
RESULTLO
;Read lower 8 bits
;Store in GPR space
• Polling the GO/DONE bit
MOVWF
• Waiting for the ADC interrupt (interrupts
enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 16.4 “A/D Acquisition
Requirements”.
DS41452B-page 146
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
16.3 ADC Register Definitions
The following registers are used to control the
operation of the ADC.
REGISTER 16-1: ADCON0: A/D CONTROL REGISTER 0
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADON
CHS<4:0>
GO/DONE
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
Unimplemented: Read as ‘0’
bit 6-2
CHS<4:0>: Analog Channel Select bits
00000= AN0
00001= AN1
00010= AN2
00011= AN3
00100= AN4
00101= AN5(3)
00110= AN6(3)
00111= AN7(3)
01000= AN8
01001= AN9
01010= AN10
01011= AN11
01100= AN12
01101= AN13
01110= AN14
01111= AN16
10000= AN16
10001= AN17
10010= AN18
10011= AN19
10100= AN20(3)
•
•
•
11011= AN27(3)
11100= Reserved. No channel connected.
11101= Reserved. No channel connected.
11110= Temperature Indicator(2)
.
11111= FVR (Fixed Voltage Reference) Buffer 1 Output(1)
bit 1
bit 0
GO/DONE: A/D Conversion Status bit
1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0= A/D conversion completed/not in progress
ADON: ADC Enable bit
1= ADC is enabled
0= ADC is disabled and consumes no operating current
Note 1: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information.
2: See Section 15.0 “Temperature Indicator Module” for more information.
3: AN<7:5> and AN<27:20> are PIC16(L)F1517/9 only.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 147
PIC16(L)F1516/7/8/9
REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
R/W-0/0
U-0
—
U-0
—
R/W-0/0
R/W-0/0
ADCS<2:0>
ADPREF<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
ADFM: A/D Result Format Select bit
1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is
loaded.
0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is
loaded.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000= FOSC/2
001= FOSC/8
010= FOSC/32
011= FRC (clock supplied from a dedicated RC oscillator)
100= FOSC/4
101= FOSC/16
110= FOSC/64
111= FRC (clock supplied from a dedicated RC oscillator)
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
ADPREF<1:0>: A/D Positive Voltage Reference Configuration bits
00= VREF is connected to VDD
01= Reserved
10= VREF is connected to external VREF+ pin(1)
11= VREF is connected to internal Fixed Voltage Reference (FVR) module(1)
Note 1: When selecting the FVR or the VREF+ pin as the source of the positive reference, be aware that a
minimum voltage specification exists. See Section 25.0 “Electrical Specifications” for details.
DS41452B-page 148
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 16-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<9:2>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<9:2>: ADC Result Register bits
Upper 8 bits of 10-bit conversion result
REGISTER 16-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0
R/W-x/u
R/W-x/u
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
ADRES<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-0
ADRES<1:0>: ADC Result Register bits
Lower 2 bits of 10-bit conversion result
Reserved: Do not use.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 149
PIC16(L)F1516/7/8/9
REGISTER 16-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
—
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-2
bit 1-0
Reserved: Do not use.
ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result
REGISTER 16-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 0
ADRES<7:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-0
ADRES<7:0>: ADC Result Register bits
Lower 8 bits of 10-bit conversion result
DS41452B-page 150
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 16-1 may be
used. This equation assumes that 1/2 LSb error is used
(1,024 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
16.4 A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 16-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 16-4. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 16-1: ACQUISITION TIME EXAMPLE
Temperature = 50°C and external impedance of 10k 5.0V VDD
Assumptions:
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= TAMP + TC + TCOFF
= 2µs + TC + Temperature - 25°C0.05µs/°C
The value for TC can be approximated with the following equations:
1
;[1] VCHOLD charged to within 1/2 lsb
VAPPLIED1 – -------------------------- = VCHOLD
2n + 1 – 1
–TC
---------
RC
VAPPLIED 1 – e
= VCHOLD
;[2] VCHOLD charge response to VAPPLIED
;combining [1] and [2]
–Tc
--------
RC
1
= VAPPLIED1 – --------------------------
2n + 1 – 1
VAPPLIED 1 – e
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –CHOLDRIC + RSS + RS ln(1/2047)
= –10pF1k + 7k + 10k ln(0.000488)
= 1.37µs
Therefore:
TACQ = 2µs + 1.37µs + 50°C- 25°C0.05µs/°C
= 4.62µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 151
PIC16(L)F1516/7/8/9
FIGURE 16-4:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Sampling
Switch
VT 0.6V
SS
RIC 1k
Rss
Rs
(1)
CPIN
5 pF
VA
I LEAKAGE
CHOLD = 10 pF
VSS/VREF-
VT 0.6V
6V
5V
RSS
VDD 4V
3V
Legend:
CHOLD
CPIN
= Sample/Hold Capacitance
= Input Capacitance
2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 1011
Sampling Switch
RIC
RSS
SS
VT
= Interconnect Resistance
= Resistance of Sampling Switch
= Sampling Switch
(k)
= Threshold Voltage
Note 1: Refer to Section 25.0 “Electrical Specifications”.
FIGURE 16-5:
ADC TRANSFER FUNCTION
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
1.5 LSB
0.5 LSB
Zero-Scale
Transition
VREF-
Full-Scale
Transition
VREF+
DS41452B-page 152
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
147
148
ADCON0
ADCON1
ADRESH
ADRESL
ANSELA
ANSELB
ANSELC
ANSELD(1)
ANSELE(1)
CCP1CON
CCP2CON
FVRCON
INTCON
PIE1
—
CHS<4:0>
GO/DONE
ADON
ADFM
ADCS<2:0>
—
—
ADPREF<1:0>
A/D Result Register High
A/D Result Register Low
149, 150
149, 150
117
ANSA2
ANSB2
ANSC2
ANSD2
ANSE2
ANSA1
ANSB1
ANSA0
ANSB0
—
—
—
ANSA5
ANSB5
ANSC5
ANSD5
—
ANSA3
ANSB3
ANSC3
ANSD3
ANSB4
ANSC4
ANSD4
—
121
ANSC6
ANSD6
ANSC7
ANSD7
—
—
—
124
ANSD1
ANSE1
ANSD0
ANSE0
127
—
—
—
—
130
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
— ADFVR<1:0>
—
—
—
—
184
184
FVREN
GIE
FVRRDY
PEIE
TSEN
TSRNG
INTE
—
138
TMR0IE
RCIE
IOCIE
SSPIE
SSPIF
TRISA3
TRISB3
TRISC3
TRISD3
‘1’
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
TRISC2
TRISD2
INTF
IOCIF
80
TMR1GIE
TMR1GIF
TRISA7
TRISB7
TRISC7
TRISD7
—
ADIE
TXIE
TMR2IE
TMR2IF
TRISA1
TRISB1
TRISC1
TRISD1
TMR1IE
TMR1IF
TRISA0
TRISB0
TRISC0
TRISD0
81
PIR1
ADIF
RCIF
TXIF
83
TRISA
TRISA6
TRISB6
TRISC6
TRISD6
—
TRISA5
TRISB5
TRISC5
TRISD5
—
TRISA4
TRISB4
TRISC4
TRISD4
—
116
TRISB
121
TRISC
TRISD(1)
124
127
TRISE
TRISE2(1) TRISE1(1) TRISE0(1)
130
Legend:
— = unimplemented read as ‘0’. Shaded cells are not used for ADC module.
Note 1: PIC16(L)F1517/9 only.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 153
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 154
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
17.1.2
8-BIT COUNTER MODE
17.0 TIMER0 MODULE
In 8-Bit Counter mode, the Timer0 module will increment
on either the rising or falling edge of the T0CKI pin. The
edge that increments the counter is determined by the
TMR0SE bit in the OPTION_REG register. TMR0SE = 1
selects the falling edge.
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
The 8-Bit Counter mode using the T0CKI pin is selected
by setting the TMR0CS bit in the OPTION_REG register
to ‘1’.
• TMR0 can be used to gate Timer1
Figure 17-1 is a block diagram of the Timer0 module.
17.1 Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
17.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the TMR0CS bit of the
OPTION_REG register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
FIGURE 17-1:
BLOCK DIAGRAM OF THE TIMER0
FOSC/4
Data Bus
0
1
8
T0CKI
1
Sync
TMR0
2 TCY
0
Set Flag bit TMR0IF
on Overflow
PSA
TMR0SE
TMR0CS
8-bit
Prescaler
Overflow to Timer1
8
PS<2:0>
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 155
PIC16(L)F1516/7/8/9
17.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A software programmable prescaler is available for
exclusive use with Timer0. The prescaler is enabled by
clearing the PSA bit of the OPTION_REG register.
Note:
The Watchdog Timer (WDT) uses its own
independent prescaler.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION_REG
register. In order to have a 1:1 prescaler value for the
Timer0 module, the prescaler must be disabled by set-
ting the PSA bit of the OPTION_REG register.
The prescaler is not readable or writable. All instructions
writing to the TMR0 register will clear the prescaler.
17.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
17.1.5
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 25.0 “Electrical
Specifications”.
17.1.6
OPERATION DURING SLEEP
Timer0 cannot operate while the processor is in Sleep
mode. The contents of the TMR0 register will remain
unchanged while the processor is in Sleep mode.
DS41452B-page 156
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
17.2 Timer0 Control Register
REGISTER 17-1: OPTION_REG: OPTION REGISTER
R/W-1/1
WPUEN
R/W-1/1
INTEDG
R/W-1/1
R/W-1/1
R/W-1/1
PSA
R/W-1/1
R/W-1/1
PS<2:0>
R/W-1/1
bit 0
TMR0CS
TMR0SE
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
WPUEN: Weak Pull-up Enable bit
1= All weak pull-ups are disabled (except MCLR, if it is enabled)
0= Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of INT pin
0= Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (FOSC/4)
TMR0SE: Timer0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is not assigned to the Timer0 module
0= Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
Bit Value
Timer0 Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TABLE 17-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Register
on Page
Name
INTCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
TMR0IE
INTE
IOCIE
PSA
TMR0IF
INTF
IOCIF
80
157
155*
116
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE
PS<2:0>
TMR0
TRISA
Timer0 Module Register
TRISA7 TRISA6 TRISA5 TRISA4
TRISA3
TRISA2
TRISA1 TRISA0
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 157
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 158
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
• Gate Toggle mode
• Gate Single-pulse mode
• Gate Value Status
18.0 TIMER1 MODULE WITH GATE
CONTROL
The Timer1 module is a 16-bit timer/counter with the
following features:
• Gate Event Interrupt
Figure 18-1 is a block diagram of the Timer1 module.
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 2-bit prescaler
• 32 kHz secondary oscillator circuit
• Optionally synchronized comparator out
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
Asynchronous mode only)
• Time base for the Capture/Compare function
• Special Event Trigger (with ECCP)
• Selectable Gate Source Polarity
FIGURE 18-1:
T1GSS<1:0>
T1G
TIMER1 BLOCK DIAGRAM
T1GSPM
00
0
From Timer0
Overflow
01
10
11
T1G_IN
D
Data Bus
T1GVAL
0
1
D
Q
Single Pulse
Acq. Control
RD
1
From Timer2
Match PR2
T1GCON
Q1 EN
Q
Q
Reserved
Interrupt
Set
TMR1GIF
T1GGO/DONE
CK
R
TMR1ON
T1GTM
det
T1GPOL
TMR1GE
Set flag bit
TMR1IF on
Overflow
TMR1ON
TMR1(2)
EN
D
Synchronized
clock input
0
T1CLK
TMR1H
TMR1L
Q
1
TMR1CS<1:0>
LFINTOSC
T1SYNC
SOSCO/T1CKI
OUT
11
10
Synchronize(3)
det
Secondary
Oscillator
Prescaler
1, 2, 4, 8
1
0
SOSCI
EN
2
T1CKPS<1:0>
FOSC
Internal
Clock
01
00
FOSC/2
Internal
Clock
T1OSCEN
Sleep input
FOSC/4
Internal
Clock
(1)
To Clock Switching Modules
Note 1: ST Buffer is high speed type when using T1CKI.
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 159
PIC16(L)F1516/7/8/9
18.1 Timer1 Operation
18.2 Clock Source Selection
The Timer1 module is a 16-bit incrementing counter
which is accessed through the TMR1H:TMR1L register
pair. Writes to TMR1H or TMR1L directly update the
counter.
The TMR1CS<1:0> and T1OSCEN bits of the T1CON
register are used to select the clock source for Timer1.
Table 18-2 displays the clock source selections.
18.2.1
INTERNAL CLOCK SOURCE
When used with an internal clock source, the module is
a timer and increments on every instruction cycle.
When used with an external clock source, the module
can be used as either a timer or counter and incre-
ments on every selected edge of the external source.
When the internal clock source is selected the
TMR1H:TMR1L register pair will increment on multiples
of FOSC as determined by the Timer1 prescaler.
When the FOSC internal clock source is selected, the
Timer1 register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB
error in resolution will occur when reading the Timer1
value. To utilize the full resolution of Timer1, an
asynchronous input signal must be used to gate the
Timer1 clock input.
Timer1 is enabled by configuring the TMR1ON and
TMR1GE bits in the T1CON and T1GCON registers,
respectively. Table 18-1 displays the Timer1 enable
selections.
TABLE 18-1: TIMER1 ENABLE
SELECTIONS
The following asynchronous source may be used:
• Asynchronous event on the T1G pin to Timer1
Gate
Timer1
Operation
TMR1ON
TMR1GE
18.2.2
EXTERNAL CLOCK SOURCE
0
0
1
1
0
1
0
1
Off
Off
When the external clock source is selected, the Timer1
module may work as a timer or a counter.
Always On
When enabled to count, Timer1 is incremented on the
rising edge of the external clock input T1CKI. This
external clock source can be synchronized to the
microcontroller system clock and run asynchronously.
Count Enabled
When used as a timer with a clock oscillator, an
external 32.768 kHz crystal can be used in conjunction
with the secondary oscillator circuit.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge after any one or
more of the following conditions:
• Timer1 enabled after POR
• Write to TMR1H or TMR1L
• Timer1 is disabled
• Timer1 is disabled (TMR1ON = 0)
when T1CKI is high then Timer1 is
enabled (TMR1ON=1) when T1CKI is
low.
TABLE 18-2: CLOCK SOURCE SELECTIONS
TMRxCS<1:0>
T1OSCEN
Clock Source
00
01
x
x
0
1
x
Instruction Clock (FOSC/4)
System Clock (FOSC)
External Clocking on T1CKI Pin
Secondary Oscillator Circuit on SOSCI/SOSCO Pins
LFINTOSC
10
11
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18.3 Timer1 Prescaler
18.6 Timer1 Gate
Timer1 has four prescaler options allowing 1, 2, 4 or 8
divisions of the clock input. The T1CKPS bits of the
T1CON register control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write to
TMR1H or TMR1L.
Timer1 can be configured to count freely or the count
can be enabled and disabled using Timer1 Gate
circuitry. This is also referred to as Timer1 Gate Enable.
Timer1 Gate can also be driven by multiple selectable
sources.
18.6.1
TIMER1 GATE ENABLE
18.4 Secondary Oscillator
The Timer1 Gate Enable mode is enabled by setting
the TMR1GE bit of the T1GCON register. The polarity
of the Timer1 Gate Enable mode is configured using
the T1GPOL bit of the T1GCON register.
Timer1 uses the low-power secondary oscillator circuit
on pins SOSCI and SOSCO. The secondary oscillator
is designed to use an external 32.768 kHz crystal.
When Timer1 Gate Enable mode is enabled, Timer1
will increment on the rising edge of the Timer1 clock
source. When Timer1 Gate Enable mode is disabled,
no incrementing will occur and Timer1 will hold the
current count. See Figure 18-3 for timing details.
The secondary oscillator circuit is enabled by setting
the T1OSCEN bit of the T1CON register. The oscillator
will continue to run during Sleep.
Note:
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
TABLE 18-3: TIMER1 GATE ENABLE
SELECTIONS
18.5 Timer1 Operation in
Asynchronous Counter Mode
T1CLK T1GPOL
T1G
Timer1 Operation
0
0
1
1
0
1
0
1
Counts
If control bit T1SYNC of the T1CON register is set, the
external clock input is not synchronized. The timer
increments asynchronously to the internal phase
clocks. If the external clock source is selected then the
timer will continue to run during Sleep and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer (see
Section 18.5.1 “Reading and Writing Timer1 in
Asynchronous Counter Mode”).
Holds Count
Holds Count
Counts
18.6.2
TIMER1 GATE SOURCE
SELECTION
The Timer1 Gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSS bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
Note:
When switching from synchronous to
asynchronous operation, it is possible to
skip an increment. When switching from
asynchronous to synchronous operation,
it is possible to produce an additional
increment.
TABLE 18-4: TIMER1 GATE SOURCES
T1GSS
Timer1 Gate Source
Timer1 Gate Pin
00
01
18.5.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
11
Timer2 match PR2
Reserved
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems, since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the TMR1H:TMR1L register pair.
2011 Microchip Technology Inc.
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18.6.2.1
T1G Pin Gate Operation
18.6.4
TIMER1 GATE SINGLE-PULSE
MODE
The T1G pin is one source for Timer1 Gate Control. It
can be used to supply an external source to the Timer1
Gate circuitry.
When Timer1 Gate Single-Pulse mode is enabled, it is
possible to capture a single-pulse gate event. Timer1
Gate Single-Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/DONE bit in the T1GCON register must be set.
The Timer1 will be fully enabled on the next incrementing
edge. On the next trailing edge of the pulse, the
T1GGO/DONE bit will automatically be cleared. No other
gate events will be allowed to increment Timer1 until the
T1GGO/DONE bit is once again set in software. See
Figure 18-5 for timing details.
18.6.2.2
Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
a
18.6.2.3
Timer2 Match PR2 Operation
When Timer2 increments and matches PR2,
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 Gate circuitry.
a
If the Single-Pulse Gate mode is disabled by clearing the
T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.
18.6.3
TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is possi-
ble to measure the full-cycle length of a Timer1 gate
signal, as opposed to the duration of a single level
pulse.
Enabling the Toggle mode and the Single-Pulse mode
simultaneously will permit both sections to work
together. This allows the cycle times on the Timer1
Gate source to be measured. See Figure 18-6 for
timing details.
The Timer1 Gate source is routed through a flip-flop
that changes state on every incrementing edge of the
signal. See Figure 18-4 for timing details.
18.6.5
TIMER1 GATE VALUE STATUS
When Timer1 Gate Value Status is utilized, it is possible
to read the most current level of the gate control value.
The value is stored in the T1GVAL bit in the T1GCON
register. The T1GVAL bit is valid even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
18.6.6
TIMER1 GATE EVENT INTERRUPT
Note:
Enabling Toggle mode at the same time
as changing the gate polarity may result in
indeterminate operation.
When Timer1 Gate Event Interrupt is enabled, it is pos-
sible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
Gate is not enabled (TMR1GE bit is cleared).
DS41452B-page 162
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18.7 Timer1 Interrupt
18.9 ECCP/CCP Capture/Compare Time
Base
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit of the PIR1 register is
set. To enable the interrupt on rollover, you must set
these bits:
The CCP modules use the TMR1H:TMR1L register
pair as the time base when operating in Capture or
Compare mode.
In Capture mode, the value in the TMR1H:TMR1L
register pair is copied into the CCPR1H:CCPR1L
register pair on a configured event.
• TMR1ON bit of the T1CON register
• TMR1IE bit of the PIE1 register
• PEIE bit of the INTCON register
• GIE bit of the INTCON register
In Compare mode, an event is triggered when the value
CCPR1H:CCPR1L register pair matches the value in
the TMR1H:TMR1L register pair. This event can be a
Special Event Trigger.
The interrupt is cleared by clearing the TMR1IF bit in
the Interrupt Service Routine.
For
more
information,
see
Section 20.0
Note:
The TMR1H:TMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
“Capture/Compare/PWM Modules”.
18.10 CCP Special Event Trigger
When the CCP is configured to trigger a special event,
the trigger will clear the TMR1H:TMR1L register pair.
This special event does not cause a Timer1 interrupt.
The CCP module may still be configured to generate a
CCP interrupt.
18.8 Timer1 Operation During Sleep
Timer1 can only operate during Sleep when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To set up the timer to wake the device:
In this mode of operation, the CCPR1H:CCPR1L
register pair becomes the period register for Timer1.
• TMR1ON bit of the T1CON register must be set
• TMR1IE bit of the PIE1 register must be set
• PEIE bit of the INTCON register must be set
• T1SYNC bit of the T1CON register must be set
Timer1 should be synchronized and FOSC/4 should be
selected as the clock source in order to utilize the Spe-
cial Event Trigger. Asynchronous operation of Timer1
can cause a Special Event Trigger to be missed.
• TMR1CS bits of the T1CON register must be
configured
In the event that a write to TMR1H or TMR1L coincides
with a Special Event Trigger from the CCP, the write will
take precedence.
• T1OSCEN bit of the T1CON register must be
configured
The device will wake-up on an overflow and execute
the next instructions. If the GIE bit of the INTCON
register is set, the device will call the Interrupt Service
Routine.
For more information, see Section 16.2.5 “Special
Event Trigger”.
Timer1 secondary oscillator will continue to operate in
Sleep regardless of the T1SYNC bit setting.
FIGURE 18-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
2011 Microchip Technology Inc.
Preliminary
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FIGURE 18-3:
TIMER1 GATE ENABLE MODE
TMR1GE
T1GPOL
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
N + 3
N + 4
FIGURE 18-4:
TIMER1 GATE TOGGLE MODE
TMR1GE
T1GPOL
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1 N + 2 N + 3 N + 4
N + 5 N + 6 N + 7 N + 8
DS41452B-page 164
Preliminary
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PIC16(L)F1516/7/8/9
FIGURE 18-5:
TIMER1 GATE SINGLE-PULSE MODE
TMR1GE
T1GPOL
T1GSPM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
N
N + 1
N + 2
Cleared by
software
Set by hardware on
falling edge of T1GVAL
Cleared by software
TMR1GIF
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
FIGURE 18-6:
TMR1GE
T1GPOL
TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE
T1GSPM
T1GTM
Cleared by hardware on
falling edge of T1GVAL
T1GGO/
DONE
Set by software
Counting enabled on
rising edge of T1G
T1G_IN
T1CKI
T1GVAL
Timer1
N + 4
N + 2 N + 3
N
N + 1
Set by hardware on
falling edge of T1GVAL
Cleared by
software
Cleared by software
TMR1GIF
DS41452B-page 166
Preliminary
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PIC16(L)F1516/7/8/9
18.11 Timer1 Control Register
The Timer1 Control register (T1CON), shown in
Register 18-1, is used to control Timer1 and select the
various features of the Timer1 module.
REGISTER 18-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
T1SYNC
U-0
—
R/W-0/u
TMR1CS<1:0>
T1CKPS<1:0>
T1OSCEN
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
TMR1CS<1:0>: Timer1 Clock Source Select bits
11=Timer1 clock source is LFINTOSC
10=Timer1 clock source is pin or oscillator:
If T1OSCEN = 0:
External clock from T1CKI pin (on the rising edge)
If T1OSCEN = 1:
Crystal oscillator on SOSCI/SOSCO pins
01=Timer1 clock source is system clock (FOSC)
00=Timer1 clock source is instruction clock (FOSC/4)
bit 5-4
T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: LP Oscillator Enable Control bit
1= Secondary oscillator circuit enabled for Timer1
0= Secondary oscillator circuit disabled for Timer1
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS<1:0> = 1X:
1= Do not synchronize external clock input
0= Synchronize external clock input with system clock (FOSC)
TMR1CS<1:0> = 0X:
This bit is ignored.
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Clears Timer1 Gate flip-flop
2011 Microchip Technology Inc.
Preliminary
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18.12 Timer1 Gate Control Register
The Timer1 Gate Control register (T1GCON), shown in
Register 18-2, is used to control Timer1 Gate.
REGISTER 18-2: T1GCON: TIMER1 GATE CONTROL REGISTER
R/W-0/u
R/W-0/u
T1GPOL
R/W-0/u
T1GTM
R/W-0/u
R/W/HC-0/u
R-x/x
R/W-0/u
R/W-0/u
TMR1GE
T1GSPM
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1= Timer1 counting is controlled by the Timer1 gate function
0= Timer1 counts regardless of Timer1 gate function
bit 6
bit 5
T1GPOL: Timer1 Gate Polarity bit
1= Timer1 gate is active-high (Timer1 counts when gate is high)
0= Timer1 gate is active-low (Timer1 counts when gate is low)
T1GTM: Timer1 Gate Toggle Mode bit
1= Timer1 Gate Toggle mode is enabled
0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared
Timer1 gate flip-flop toggles on every rising edge.
bit 4
T1GSPM: Timer1 Gate Single-Pulse Mode bit
1= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate
0= Timer1 gate Single-Pulse mode is disabled
bit 3
T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit
1= Timer1 gate single-pulse acquisition is ready, waiting for an edge
0= Timer1 gate single-pulse acquisition has completed or has not been started
bit 2
T1GVAL: Timer1 Gate Current State bit
Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.
Unaffected by Timer1 Gate Enable (TMR1GE).
bit 1-0
T1GSS<1:0>: Timer1 Gate Source Select bits
00= Timer1 Gate pin
01= Timer0 overflow output
10= Timer2 Match PR2
11= Reserved
DS41452B-page 168
Preliminary
2011 Microchip Technology Inc.
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TABLE 18-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELB
CCP1CON
CCP2CON
INTCON
PIE1
—
—
—
—
ANSB5
ANSB4
ANSB3
ANSB2
ANSB1
ANSB0
121
184
184
80
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
TMR0IF INTF
—
—
GIE
PEIE
ADIE
ADIF
TMR0IE
INTE
TXIE
TXIF
IOCIE
SSPIE
SSPIF
IOCIF
TMR1GIE
TMR1GIF
RCIE
RCIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
83
TMR1H
TMR1L
TRISB
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
163*
163*
121
124
167
168
TRISB7
TRISC7
TRISB6
TRISC6
TRISB5
TRISC5
TRISB4
TRISC4
TRISB3
TRISC3
TRISB2 TRISB1 TRISB0
TRISC2 TRISC1 TRISC0
TRISC
TMR1CS<1:0>
TMR1GE T1GPOL
T1CKPS<1:0>
T1OSCEN T1SYNC
—
TMR1ON
T1CON
T1GCON
T1GTM T1GSPM T1GGO/ T1GVAL
DONE
T1GSS<1:0>
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 169
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 170
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
19.0 TIMER2 MODULE
The Timer2 module incorporates the following features:
• 8-bit Timer and Period registers (TMR2 and PR2,
respectively)
• Readable and writable (both registers)
• Software programmable prescaler (1:1, 1:4, 1:16,
and 1:64)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMR2 match with PR2, respectively
• Optional use as the shift clock for the MSSP
modules
See Figure 19-1 for a block diagram of Timer2.
FIGURE 19-1:
TIMER2 BLOCK DIAGRAM
Sets Flag
bit TMR2IF
Output
TMR2
Prescaler
Reset
TMR2
FOSC/4
1:1, 1:4, 1:16, 1:64
Postscaler
1:1 to 1:16
2
Comparator
PR2
EQ
T2CKPS<1:0>
4
T2OUTPS<3:0>
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 171
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19.1 Timer2 Operation
19.3 Timer2 Output
The clock input to the Timer2 modules is the system
instruction clock (FOSC/4).
The unscaled output of TMR2 is available primarily to
the CCP1 module, where it is used as a time base for
operations in PWM mode.
TMR2 increments from 00h on each clock edge.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode.
Additional information is provided in Section 21.0
“Master Synchronous Serial Port (MSSP) Module”
A 4-bit counter/prescaler on the clock input allows direct
input, divide-by-4 and divide-by-16 prescale options.
These options are selected by the prescaler control bits,
T2CKPS<1:0> of the T2CON register. The value of
TMR2 is compared to that of the Period register, PR2, on
each clock cycle. When the two values match, the
comparator generates a match signal as the timer
output. This signal also resets the value of TMR2 to 00h
on the next cycle and drives the output
19.4 Timer2 Operation During Sleep
Timer2 cannot be operated while the processor is in
Sleep mode. The contents of the TMR2 and PR2
registers will remain unchanged while the processor is
in Sleep mode.
counter/postscaler
(see
Section 19.2
“Timer2
Interrupt”).
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Watchdog Timer (WDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESETInstruction
Note:
TMR2 is not cleared when T2CON is
written.
19.2 Timer2 Interrupt
Timer2 can also generate an optional device interrupt.
The Timer2 output signal (TMR2-to-PR2 match)
provides the input for the 4-bit counter/postscaler. This
counter generates the TMR2 match interrupt flag which
is latched in TMR2IF of the PIR1 register. The interrupt
is enabled by setting the TMR2 Match Interrupt Enable
bit, TMR2IE of the PIE1 register.
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0>, of the T2CON register.
DS41452B-page 172
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
19.5 Timer2 Control Register
REGISTER 19-1: T2CON: TIMER2 CONTROL REGISTER
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
T2OUTPS<3:0>: Timer2 Output Postscaler Select bits
0000= 1:1 Postscaler
0001= 1:2 Postscaler
0010= 1:3 Postscaler
0011= 1:4 Postscaler
0100= 1:5 Postscaler
0101= 1:6 Postscaler
0110= 1:7 Postscaler
0111= 1:8 Postscaler
1000= 1:9 Postscaler
1001= 1:10 Postscaler
1010= 1:11 Postscaler
1011= 1:12 Postscaler
1100= 1:13 Postscaler
1101= 1:14 Postscaler
1110= 1:15 Postscaler
1111= 1:16 Postscaler
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
10= Prescaler is 16
11= Prescaler is 64
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 173
PIC16(L)F1516/7/8/9
TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CCP1CON
CCP2CON
INTCON
PIE1
—
—
—
DC1B<1:0>
DC2B<1:0>
CCP1M<3:0>
CCP2M<3:0>
TMR0IF INTF
CCP1IE TMR2IE
184
184
80
—
GIE
PEIE
ADIE
ADIF
TMR0IE
INTE
TXIE
TXIF
IOCIE
SSPIE
SSPIF
IOCIF
TMR1IE
TMR1IF
TMR1GIE
TMR1GIF
RCIE
RCIF
81
PIR1
CCP1IF
TMR2IF
83
PR2
Timer2 Module Period Register
T2OUTPS<3:0>
Holding Register for the 8-bit TMR2 Register
171*
173
171*
T2CON
TMR2
—
TMR2ON
T2CKPS<1:0>
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.
Page provides register information.
*
DS41452B-page 174
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.0 CAPTURE/COMPARE/PWM
MODULES
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different
events, and to generate Pulse-Width Modulation
(PWM) signals. In Capture mode, the peripheral allows
the timing of the duration of an event. The Compare
mode allows the user to trigger an external event when
a predetermined amount of time has expired. The
PWM mode can generate Pulse-Width Modulated
signals of varying frequency and duty cycle.
This family of devices contains 2 standard Capture/
Compare/PWM modules (CCP1 and CCP2).
The Capture and Compare functions are identical for all
CCP modules.
Note 1: In devices with more than one CCP
module, it is very important to pay close
attention to the register names used. A
number placed after the module acronym
is used to distinguish between separate
modules. For example, the CCP1CON
and CCP2CON control the same
operational aspects of two completely
different CCP modules.
2: Throughout
this
section,
generic
references to a CCP module in any of its
operating modes may be interpreted as
being equally applicable to CCPx module.
Register names, module signals, I/O pins,
and bit names may use the generic
designator ‘x’ to indicate the use of a
numeral to distinguish a particular module,
when required.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 175
PIC16(L)F1516/7/8/9
20.1.2
TIMER1 MODE RESOURCE
20.1 Capture Mode
Timer1 must be running in Timer mode or Synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
The Capture mode function described in this section is
available and identical for all CCP modules.
Capture mode makes use of the 16-bit Timer1
resource. When an event occurs on the CCPx pin, the
16-bit CCPRxH:CCPRxL register pair captures and
stores the 16-bit value of the TMR1H:TMR1L register
pair, respectively. An event is defined as one of the
following and is configured by the CCPxM<3:0> bits of
the CCPxCON register:
See Section 18.0 “Timer1 Module with Gate
Control” for more information on configuring Timer1.
20.1.3
SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit of the PIEx register clear to
avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIRx register
following any change in Operating mode.
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
When a capture is made, the Interrupt Request Flag bit
CCPxIF of the PIRx register is set. The interrupt flag
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair
is read, the old captured value is overwritten by the new
captured value.
20.1.4
CCP PRESCALER
There are four prescaler settings specified by the
CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Figure 20-1 shows a simplified diagram of the Capture
operation.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Equation 20-1 demonstrates the code to
perform this function.
20.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCPx pin should be configured
as an input by setting the associated TRIS control bit.
Also, the CCP2 pin function can be moved to
alternative pins using the APFCON register. Refer to
Section Register 12-1: “APFCON: Alternate Pin
Function Control Register” for more details.
EXAMPLE 20-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSELCCPxCON
;Set Bank bits to point
;to CCPxCON
;Turn CCP module off
Note:
If the CCPx pin is configured as an output,
a write to the port can cause a capture
condition.
CLRF
CCPxCON
MOVLW
NEW_CAPT_PS;Load the W reg with
;the new prescaler
;move value and CCP ON
;Load CCPxCON with this
;value
FIGURE 20-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
MOVWF
CCPxCON
Set Flag bit CCPxIF
(PIRx register)
Prescaler
1, 4, 16
CCPx
pin
CCPRxH
CCPRxL
Capture
Enable
and
Edge Detect
TMR1H
TMR1L
CCPxM<3:0>
System Clock (FOSC)
DS41452B-page 176
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.1.5
CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
20.1.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 177
PIC16(L)F1516/7/8/9
20.2.2
TIMER1 MODE RESOURCE
20.2 Compare Mode
In Compare mode, Timer1 must be running in either
Timer mode or Synchronized Counter mode. The
compare operation may not work in Asynchronous
Counter mode.
The Compare mode function described in this section
is available and identical for al CCP modules.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMR1H:TMR1L register pair. When a
match occurs, one of the following events can occur:
See Section 18.0 “Timer1 Module with Gate Control”
for more information on configuring Timer1.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Compare
mode. In order for Compare mode to
recognize the trigger event on the CCPx
pin, TImer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Generate a Special Event Trigger
• Generate a Software Interrupt
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set.
20.2.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen
(CCPxM<3:0> = 1010), the CCPx module does not
assert control of the CCPx pin (see the CCPxCON
register).
All Compare modes can generate an interrupt.
Figure 20-2 shows
Compare operation.
a simplified diagram of the
20.2.4
SPECIAL EVENT TRIGGER
FIGURE 20-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
following:
CCPxM<3:0>
Mode Select
• Resets Timer1
• Starts an ADC conversion if ADC is enabled
Set CCPxIF Interrupt Flag
The CCPx module does not assert control of the CCPx
pin in this mode.
(PIRx)
4
CCPx
Pin
CCPRxH CCPRxL
Comparator
The Special Event Trigger output of the CCP occurs
immediately upon a match between the TMR1H,
TMR1L register pair and the CCPRxH, CCPRxL regis-
ter pair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock. The Spe-
cial Event Trigger output starts an A/D conversion (if
the A/D module is enabled). This allows the CCPRxH,
CCPRxL register pair to effectively provide a 16-bit pro-
grammable period register for Timer1.
Q
S
R
Output
Logic
Match
TMR1H TMR1L
TRIS
Output Enable
Special Event Trigger
20.2.1
CCPX PIN CONFIGURATION
TABLE 20-1: SPECIAL EVENT TRIGGER
The user must configure the CCPx pin as an output by
clearing the associated TRIS bit.
Device
CCPx
PIC16(L)F151X
CCP2
The CCP2 pin function can be moved to alternate pins
using the APFCON register (Register 12-1). Refer to
Section 12.1 “Alternate Pin Function” for more
details.
Refer to Section 16.2.5 “Special Event Trigger” for
more information.
Note 1: The Special Event Trigger from the CCP
module does not set interrupt flag bit
TMR1IF of the PIR1 register.
Note:
Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.
2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
clock edge that generates the Special
Event Trigger and the clock edge that
generates the Timer1 Reset, will
preclude the Reset from occurring.
DS41452B-page 178
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.2.5
COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (FOSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
20.2.6
ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function”for
more information.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 179
PIC16(L)F1516/7/8/9
FIGURE 20-3:
CCP PWM OUTPUT SIGNAL
20.3 PWM Overview
Pulse-Width Modulation (PWM) is a scheme that
provides power to a load by switching quickly between
fully on and fully off states. The PWM signal resembles
a square wave where the high portion of the signal is
considered the on state and the low portion of the signal
is considered the off state. The high portion, also known
as the pulse width, can vary in time and is defined in
steps. A larger number of steps applied, which
lengthens the pulse width, also supplies more power to
the load. Lowering the number of steps applied, which
shortens the pulse width, supplies less power. The
PWM period is defined as the duration of one complete
cycle or the total amount of on and off time combined.
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPxCON<5:4>
TMR2 = 0
FIGURE 20-4:
SIMPLIFIED PWM BLOCK
DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers
PWM resolution defines the maximum number of steps
that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse
width time and in turn the power that is applied to the
load.
CCPRxL
CCPRxH(2) (Slave)
Comparator
CCPx
The term duty cycle describes the proportion of the on
time to the off time and is expressed in percentages,
where 0% is fully off and 100% is fully on. A lower duty
cycle corresponds to less power applied and a higher
duty cycle corresponds to more power applied.
R
S
Q
(1)
TMR2
TRIS
Figure 20-3 shows a typical waveform of the PWM
signal.
Comparator
PR2
Clear Timer,
toggle CCPx pin and
latch duty cycle
20.3.1
STANDARD PWM OPERATION
The standard PWM function described in this section is
available and identical for all CCP modules.
Note 1: The 8-bit timer TMR2 register is concatenated
with the 2-bit internal system clock (FOSC), or
2 bits of the prescaler, to create the 10-bit time
base.
The standard PWM mode generates a Pulse-Width
modulation (PWM) signal on the CCPx pin with up to 10
bits of resolution. The period, duty cycle, and resolution
are controlled by the following registers:
2: In PWM mode, CCPRxH is a read-only register.
• PR2 registers
• T2CON registers
• CCPRxL registers
• CCPxCON registers
Figure 20-4 shows a simplified block diagram of PWM
operation.
Note 1: The corresponding TRIS bit must be
cleared to enable the PWM output on the
CCPx pin.
2: Clearing the CCPxCON register will
relinquish control of the CCPx pin.
DS41452B-page 180
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When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
20.3.2
SETUP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for standard PWM operation:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
cycle = 0%, the pin will not be set.)
1. Disable the CCPx pin output driver by setting the
associated TRIS bit.
• The PWM duty cycle is latched from CCPRxL into
CCPRxH.
2. Load the PR2 register with the PWM period
value.
3. Configure the CCP module for the PWM mode
by loading the CCPxCON register with the
appropriate values.
Note:
The Timer postscaler (see Section 19.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
4. Load the CCPRxL register and the DCxBx bits
of the CCPxCON register, with the PWM duty
cycle value.
20.3.5
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPRxL register and
DCxB<1:0> bits of the CCPxCON register. The
CCPRxL contains the eight MSbs and the DCxB<1:0>
bits of the CCPxCON register contain the two LSbs.
CCPRxL and DCxB<1:0> bits of the CCPxCON
register can be written to at any time. The duty cycle
value is not latched into CCPRxH until after the period
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPRxH
register is read-only.
5. Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIRx register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer prescale value.
• Enable the Timer by setting the TMR2ON
bit of the T2CON register.
6. Enable PWM output pin:
• Wait until the Timer overflows and the
TMR2IF bit of the PIR1 register is set. See
Note below.
Equation 20-2 is used to calculate the PWM pulse
width.
• Enable the CCPx pin output driver by clear-
ing the associated TRIS bit.
Equation 20-3 is used to calculate the PWM duty cycle
ratio.
Note:
In order to send a complete duty cycle and
period on the first PWM output, the above
steps must be included in the setup
sequence. If it is not critical to start with a
complete PWM signal on the first output,
then step 6 may be ignored.
EQUATION 20-2: PULSE WIDTH
Pulse Width = CCPRxL:CCPxCON<5:4>
TOSC (TMR2 Prescale Value)
20.3.3
TIMER2 TIMER RESOURCE
The PWM standard mode makes use of the 8-bit
Timer2 timer resources to specify the PWM period.
EQUATION 20-3: DUTY CYCLE RATIO
CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio = ----------------------------------------------------------------------
4PR2 + 1
20.3.4
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 20-1.
The CCPRxH register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
EQUATION 20-1: PWM PERIOD
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (FOSC), or 2 bits of
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
PWM Period = PR2 + 1 4 TOSC
(TMR2 Prescale Value)
Note 1: TOSC = 1/FOSC
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Figure 20-4).
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 181
PIC16(L)F1516/7/8/9
20.3.6
PWM RESOLUTION
EQUATION 20-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
log4PR2 + 1
Resolution = ----------------------------------------- bits
log2
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 20-4.
Note:
If the pulse width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 20-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
TABLE 20-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
Maximum Resolution (bits)
DS41452B-page 182
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
20.3.7
OPERATION IN SLEEP MODE
20.3.10 ALTERNATE PIN LOCATIONS
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the CCPx
pin is driving a value, it will continue to drive that value.
When the device wakes up, TMR2 will continue from its
previous state.
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see Section 12.1 “Alternate Pin Function” for
more information.
20.3.8
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency. Any changes in the system clock frequency
will result in changes to the PWM frequency. See
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)” for additional details.
20.3.9
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
CCP registers to their Reset states.
TABLE 20-4: SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
APFCON
CCP1CON
INTCON
PIE1
SSSEL
CCP2SEL
114
184
80
—
—
—
—
—
—
—
—
DC1B<1:0>
CCP1M<3:0>
GIE
PEIE
TMR0IE
RCIE
—
INTE
TXIE
—
IOCIE
SSPIE
BCLIE
SSPIF
BCLIF
TMR0IF
CCP1IE
—
INTF
TMR2IE
—
IOCIF
TMR1GIE
OSFIE
ADIE
—
TMR1IE
CCP2IE
TMR1IF
CCP2IF
81
PIE2
82
PIR1
TMR1GIF
OSFIF
ADIF
—
RCIF
—
TXIF
—
CCP1IF
—
TMR2IF
—
83
PIR2
84
PR2
Timer2 Period Register
—
171*
T2CON
TMR2
TRISA
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
173
171
116
Timer2 Module Register
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 183
PIC16(L)F1516/7/8/9
20.4 CCP Control Registers
REGISTER 20-1: CCPxCON: CCPx CONTROL REGISTER
U-0
—
U-0
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DCxB<1:0>
CCPxM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Reset
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM<3:0>: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCPx module)
0001= Reserved
0010= Compare mode: toggle output on match
0011= Reserved
0100= Capture mode: every falling edge
0101= Capture mode: every rising edge
0110= Capture mode: every 4th rising edge
0111= Capture mode: every 16th rising edge
1000= Compare mode: set output on compare match (set CCPxIF)
1001= Compare mode: clear output on compare match (set CCPxIF)
1010= Compare mode: generate software interrupt only
1011= Compare mode: Special Event Trigger (sets CCPxIF bit (CCP2), starts A/D conversion if A/D
module is enabled)(1)
11xx= PWM mode
DS41452B-page 184
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
21.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
21.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C™)
The SPI interface supports the following modes and
features:
• Master mode
• Slave mode
• Clock Parity
• Slave Select Synchronization (Slave mode only)
• Daisy-chain connection of slave devices
Figure 21-1 is a block diagram of the SPI interface
module.
FIGURE 21-1:
MSSP BLOCK DIAGRAM (SPI MODE)
Data Bus
Write
Read
SSPBUF Reg
SSPSR Reg
SDI
Shift
Clock
bit 0
SDO
SS
Control
Enable
SS
2 (CKP, CKE)
Clock Select
Edge
Select
SSPM<3:0>
4
TMR2 Output
2
(
)
SCK
TOSC
Prescaler
4, 16, 64
Edge
Select
Baud Rate
Generator
(SSPADD)
TRIS bit
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 185
PIC16(L)F1516/7/8/9
The I2C interface supports the following modes and
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 21-2 is a block diagram of the I2C interface mod-
ule in Master mode. Figure 21-3 is a diagram of the I2C
interface module in Slave mode.
FIGURE 21-2:
MSSP BLOCK DIAGRAM (I2C™ MASTER MODE)
Internal
data bus
[SSPM 3:0]
Read
Write
SSPBUF
SSPSR
Baud Rate
Generator
(SSPADD)
SDA
Shift
Clock
SDA in
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPCON2)
SCL
Start bit detect,
Stop bit detect
SCL in
Bus Collision
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPCON2)
Set SSPIF, BCLIF
end of XMIT/RCV
Address Match detect
DS41452B-page 186
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PIC16(L)F1516/7/8/9
FIGURE 21-3:
MSSP BLOCK DIAGRAM (I2C™ SLAVE MODE)
Internal
Data Bus
Read
Write
SSPBUF Reg
SSPSR Reg
SCL
SDA
Shift
Clock
MSb
LSb
SSPMSK Reg
Match Detect
SSPADD Reg
Addr Match
Set, Reset
S, P bits
(SSPSTAT Reg)
Start and
Stop bit Detect
2011 Microchip Technology Inc.
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its SDO pin) and the slave device is reading this bit and
saving it as the LSb of its shift register, that the slave
device is also sending out the MSb from its shift register
(on its SDO pin) and the master device is reading this
bit and saving it as the LSb of its shift register.
21.2 SPI Mode Overview
The Serial Peripheral Interface (SPI) bus is a
synchronous serial data communication bus that
operates in Full Duplex mode. Devices communicate in
a master/slave environment where the master device
After 8 bits have been shifted out, the master and slave
have exchanged register values.
initiates the communication.
A slave device is
controlled through a Chip Select known as Slave
Select.
If there is more data to exchange, the shift registers are
loaded with new data and the process repeats itself.
The SPI bus specifies four signal connections:
Whether the data is meaningful or not (dummy data),
depends on the application software. This leads to
three scenarios for data transmission:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Slave Select (SS)
• Master sends useful data and slave sends dummy
data.
Figure 21-1 shows the block diagram of the MSSP
module when operating in SPI Mode.
• Master sends useful data and slave sends useful
data.
The SPI bus operates with a single master device and
one or more slave devices. When multiple slave
devices are used, an independent Slave Select con-
nection is required from the master device to each
slave device.
• Master sends dummy data and slave sends useful
data.
Transmissions may involve any number of clock
cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it dese-
lects the slave.
Figure 21-4 shows a typical connection between a
master device and multiple slave devices.
Every slave device connected to the bus that has not
been selected through its slave select line must disre-
gard the clock and transmission signals and must not
transmit out any data of its own.
The master selects only one slave at a time. Most slave
devices have tri-state outputs so their output signal
appears disconnected from the bus when they are not
selected.
Transmissions involve two shift registers, eight bits in
size, one in the master and one in the slave. With either
the master or the slave device, data is always shifted
out one bit at a time, with the Most Significant bit (MSb)
shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 21-5 shows a typical connection between two
processors configured as master and slave devices.
Data is shifted out of both shift registers on the pro-
grammed clock edge and latched on the opposite edge
of the clock.
The master device transmits information out on its SDO
output pin which is connected to, and received by, the
slave’s SDI input pin. The slave device transmits infor-
mation out on its SDO output pin, which is connected
to, and received by, the master’s SDI input pin.
To begin communication, the master device first sends
out the clock signal. Both the master and the slave
devices should be configured for the same clock polar-
ity.
The master device starts a transmission by sending out
the MSb from its shift register. The slave device reads
this bit from that same line and saves it into the LSb
position of its shift register.
During each SPI clock cycle, a full duplex data
transmission occurs. This means that while the master
device is sending out the MSb from its shift register (on
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FIGURE 21-4:
SPI MASTER AND MULTIPLE SLAVE CONNECTION
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
21.2.1 SPI MODE REGISTERS
The MSSP module has five registers for SPI mode
operation. These are:
• MSSP STATUS register (SSPSTAT)
• MSSP Control Register 1 (SSPCON1)
• MSSP Control Register 3 (SSPCON3)
• MSSP Data Buffer register (SSPBUF)
• MSSP Address register (SSPADD)
• MSSP Shift register (SSPSR)
(Not directly accessible)
SSPCON1 and SSPSTAT are the control and STATUS
registers in SPI mode operation. The SSPCON1 regis-
ter is readable and writable. The lower 6 bits of the
SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
In one SPI master mode, SSPADD can be loaded with
a value used in the Baud Rate Generator. More infor-
mation on the Baud Rate Generator is available in
Section 21.7 “Baud Rate Generator”.
SSPSR is the shift register used for shifting data in and
out. SSPBUF provides indirect access to the SSPSR
register. SSPBUF is the buffer register to which data
bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPBUF together
create a buffered receiver. When SSPSR receives a
complete byte, it is transferred to SSPBUF and the
SSPIF interrupt is set.
During transmission, the SSPBUF is not buffered. A
write to SSPBUF will write to both SSPBUF and
SSPSR.
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21.2.2 SPI MODE OPERATION
The MSSP consists of a transmit/receive shift register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8 bits of data
have been received, that byte is moved to the SSPBUF
register. Then, the Buffer Full Detect bit, BF of the
SSPSTAT register, and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the write collision detect bit WCOL
of the SSPCON1 register, will be set. User software
must clear the WCOL bit to allow the following write(s)
to the SSPBUF register to complete successfully.
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
When the application software is expecting to receive
valid data, the SSPBUF should be read before the next
byte of data to transfer is written to the SSPBUF. The
Buffer Full bit, BF of the SSPSTAT register, indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur.
To enable the serial port, SSP Enable bit, SSPEN of the
SSPCON1 register, must be set. To reset or reconfig-
ure SPI mode, clear the SSPEN bit, re-initialize the
SSPCON registers and then set the SSPEN bit. This
configures the SDI, SDO, SCK and SS pins as serial
port pins. For the pins to behave as the serial port func-
tion, some must have their data direction bits (in the
TRIS register) appropriately programmed as follows:
• SDI must have corresponding TRIS bit set
• SDO must have corresponding TRIS bit cleared
• SCK (Master mode) must have corresponding
TRIS bit cleared
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the SSPSTAT register indicates the
various Status conditions.
• SCK (Slave mode) must have corresponding
TRIS bit set
• SS must have corresponding TRIS bit set
Any serial port function that is not desired may be
overridden by programming the corresponding data
direction (TRIS) register to the opposite value.
FIGURE 21-5:
SPI MASTER/SLAVE CONNECTION
SPI Master SSPM<3:0> = 00xx
= 1010
SPI Slave SSPM<3:0> = 010x
SDO
SDI
Serial Input Buffer
Serial Input Buffer
(SSPBUF)
(BUF)
SDI
SDO
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
MSb
MSb
LSb
Serial Clock
SCK
SCK
SS
Slave Select
(optional)
General I/O
Processor 2
Processor 1
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The clock polarity is selected by appropriately
programming the CKP bit of the SSPCON1 register
and the CKE bit of the SSPSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 21-6, Figure 21-8 and Figure 21-9,
where the MSB is transmitted first. In Master mode, the
SPI clock rate (bit rate) is user programmable to be one
of the following:
21.2.3
SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 21-5)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SDO output could be dis-
abled (programmed as an input). The SSPSR register
will continue to shift in the signal present on the SDI pin
at the programmed clock rate. As each byte is
received, it will be loaded into the SSPBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• Fosc/(4 * (SSPADD + 1))
Figure 21-6 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPBUF is loaded with the received
data is shown.
FIGURE 21-6:
SPI MODE WAVEFORM (MASTER MODE)
Write to
SSPBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPIF
SSPSR to
SSPBUF
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21.2.4
SPI SLAVE MODE
21.2.5
SLAVE SELECT
SYNCHRONIZATION
In Slave mode, the data is transmitted and received as
external clock pulses appear on SCK. When the last
bit is latched, the SSPIF interrupt flag bit is set.
The Slave Select can also be used to synchronize com-
munication. The Slave Select line is held high until the
master device is ready to communicate. When the
Slave Select line is pulled low, the slave knows that a
new transmission is starting.
Before enabling the module in SPI Slave mode, the clock
line must match the proper Idle state. The clock line can
be observed by reading the SCK pin. The Idle state is
determined by the CKP bit of the SSPCON1 register.
If the slave fails to receive the communication properly,
it will be reset at the end of the transmission, when the
Slave Select line returns to a high state. The slave is
then ready to receive a new transmission when the
Slave Select line is pulled low again. If the Slave Select
line is not used, there is a risk that the slave will even-
tually become out of sync with the master. If the slave
misses a bit, it will always be one bit off in future trans-
missions. Use of the Slave Select line allows the slave
and master to align themselves at the beginning of
each transmission.
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. The shift register is clocked from the SCK pin
input and when a byte is received, the device will gen-
erate an interrupt. If enabled, the device will wake-up
from Sleep.
21.2.4.1 Daisy-Chain Configuration
The SS pin allows a Synchronous Slave mode. The
SPI must be in Slave mode with SS pin control enabled
(SSPCON1<3:0> = 0100).
The SPI bus can sometimes be connected in a
daisy-chain configuration. The first slave output is con-
nected to the second slave input, the second slave
output is connected to the third slave input, and so on.
The final slave output is connected to the master input.
Each slave sends out, during a second group of clock
pulses, an exact copy of what was received during the
first group of clock pulses. The whole chain acts as
one large communication shift register. The
daisy-chain feature only requires a single Slave Select
line from the master device.
When the SS pin is low, transmission and reception are
enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer
driven, even if in the middle of a transmitted byte and
becomes a floating output. External pull-up/pull-down
resistors may be desirable depending on the applica-
tion.
Note 1: When the SPI is in Slave mode with SS pin
control enabled (SSPCON1<3:0>
=
Figure 21-7 shows the block diagram of a typical
daisy-chain connection when operating in SPI Mode.
0100), the SPI module will reset if the SS
pin is set to VDD.
In a daisy-chain configuration, only the most recent
byte on the bus is required by the slave. Setting the
BOEN bit of the SSPCON3 register will enable writes
to the SSPBUF register, even if the previous byte has
not been read. This allows the software to ignore data
that may not apply to it.
2: When the SPI is used in Slave mode with
CKE set; the user must enable SS pin
control.
3: While operated in SPI Slave mode the
SMP bit of the SSPSTAT register must
remain clear.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
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FIGURE 21-7:
SPI DAISY-CHAIN CONNECTION
SCK
SCK
SPI Master
SDO
SDI
SDI
SDO
SS
SPI Slave
#1
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
FIGURE 21-8:
SLAVE SELECT SYNCHRONOUS WAVEFORM
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Shift register SSPSR
and bit count are reset
SSPBUF to
SSPSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDO
SDI
bit 7
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
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FIGURE 21-9:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
bit 0
bit 7
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
FIGURE 21-10:
SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
bit 0
Input
Sample
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
Write Collision
detection active
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21.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if enabled, will wake the
device.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP inter-
rupts should be disabled.
TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
ANSELC
APFCON
INTCON
PIE1
—
ANSC7
—
—
ANSC6
—
ANSA5
ANSC5
—
—
ANSC4
—
ANSA3
ANSC3
—
ANSA2
ANSC2
—
ANSA1
—
ANSA0
—
117
124
114
80
SSSEL
INTF
CCP2SEL
IOCIF
GIE
PEIE
ADIE
ADIF
TMR0IE
RCIE
INTE
TXIE
TXIF
IOCIE
SSPIE
SSPIF
TMR0IF
CCP1IE
CCP1IF
TMR1GIE
TMR1GIF
TMR2IE
TMR2IF
TMR1IE
TMR1IF
81
PIR1
RCIF
83
SSPBUF
SSPCON1
SSPCON3
SSPSTAT
TRISA
Synchronous Serial Port Receive Buffer/Transmit Register
189*
233
235
233
116
123
WCOL
ACKTIM
SMP
SSPOV
PCIE
SSPEN
SCIE
CKP
BOEN
P
SSPM<3:0>
SDAHT
S
SBCDE
R/W
AHEN
UA
DHEN
BF
CKE
D/A
TRISA7
TRISC7
TRISA6
TRISC6
TRISA5
TRISC5
TRISA4
TRISC4
TRISA3
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
TRISA
Legend:
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
*
Page provides register information.
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I2C MASTER/
21.3 I2C MODE OVERVIEW
FIGURE 21-11:
SLAVE CONNECTION
The Inter-Integrated Circuit Bus (I²C) is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A Slave device is
controlled through addressing.
VDD
SCL
SCL
The I2C bus specifies two signal connections:
VDD
• Serial Clock (SCL)
• Serial Data (SDA)
Master
Slave
SDA
SDA
Figure 21-11 shows the block diagram of the MSSP
module when operating in I2C Mode.
Both the SCL and SDA connections are bidirectional
open-drain lines, each requiring pull-up resistors for the
supply voltage. Pulling the line to ground is considered
a logical zero and letting the line float is considered a
logical one.
The Acknowledge bit (ACK) is an active-low signal,
which holds the SDA line low to indicate to the transmit-
ter that the slave device has received the transmitted
data and is ready to receive more.
Figure 21-11 shows a typical connection between two
processors configured as master and slave devices.
The I2C bus can operate with one or more master
devices and one or more slave devices.
The transition of a data bit is always performed while
the SCL line is held low. Transitions that occur while the
SCL line is held high are used to indicate Start and Stop
bits.
If the master intends to write to the slave, then it repeat-
edly sends out a byte of data, with the slave responding
after each byte with an ACK bit. In this example, the
master device is in Master Transmit mode and the
slave is in Slave Receive mode.
There are four potential modes of operation for a given
device:
• Master Transmit mode
(master is transmitting data to a slave)
• Master Receive mode
If the master intends to read from the slave, then it
repeatedly receives a byte of data from the slave, and
responds after each byte with an ACK bit. In this exam-
ple, the master device is in Master Receive mode and
the slave is Slave Transmit mode.
(master is receiving data from a slave)
• Slave Transmit mode
(slave is transmitting data to a master)
• Slave Receive mode
(slave is receiving data from the master)
On the last byte of data communicated, the master
device may end the transmission by sending a Stop bit.
If the master device is in Receive mode, it sends the
Stop bit in place of the last ACK bit. A Stop bit is indi-
cated by a low-to-high transition of the SDA line while
the SCL line is held high.
To begin communication, a master device starts out in
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a sin-
gle Read/Write bit, which determines whether the mas-
ter intends to transmit to or receive data from the slave
device.
In some cases, the master may want to maintain con-
trol of the bus and re-initiate another transmission. If
so, the master device may send another Start bit in
place of the Stop bit or last ACK bit when it is in receive
mode.
If the requested slave exists on the bus, it will respond
with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Receive mode and the slave continues in the comple-
ment, either in Receive mode or Transmit mode,
respectively.
The I2C bus specifies three message protocols;
• Single message where a master writes data to a
slave.
A Start bit is indicated by a high-to-low transition of the
SDA line while the SCL line is held high. Address and
data bytes are sent out, Most Significant bit (MSb) first.
The Read/Write bit is sent out as a logical one when the
master intends to read data from the slave, and is sent
out as a logical zero when it intends to write data to the
slave.
• Single message where a master reads data from
a slave.
• Combined message where a master initiates a
minimum of two writes, or two reads, or a
combination of writes and reads, to one or more
slaves.
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When one device is transmitting a logical one, or letting
the line float, and a second device is transmitting a log-
ical zero, or holding the line low, the first device can
detect that the line is not a logical one. This detection,
when used on the SCL line, is called clock stretching.
Clock stretching gives slave devices a mechanism to
control the flow of data. When this detection is used on
the SDA line, it is called arbitration. Arbitration ensures
that there is only one master device communicating at
any single time.
21.3.2
ARBITRATION
Each master device must monitor the bus for Start and
Stop bits. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an
Idle state.
However, two master devices may try to initiate a trans-
mission on or about the same time. When this occurs,
the process of arbitration begins. Each transmitter
checks the level of the SDA data line and compares it
to the level that it expects to find. The first transmitter to
observe that the two levels do not match, loses arbitra-
tion, and must stop transmitting on the SDA line.
21.3.1
CLOCK STRETCHING
When a slave device has not completed processing
data, it can delay the transfer of more data through the
process of Clock Stretching. An addressed slave
device may hold the SCL clock line low after receiving
or sending a bit, indicating that it is not yet ready to con-
tinue. The master that is communicating with the slave
will attempt to raise the SCL line in order to transfer the
next bit, but will detect that the clock line has not yet
been released. Because the SCL connection is
open-drain, the slave has the ability to hold that line low
until it is ready to continue communicating.
For example, if one transmitter holds the SDA line to a
logical one (lets it float) and a second transmitter holds
it to a logical zero (pulls it low), the result is that the
SDA line will be low. The first transmitter then observes
that the level of the line is different than expected and
concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one
that loses arbitration and must stop driving the SDA
line. If this transmitter is also a master device, it also
must stop driving the SCL line. It then can monitor the
lines for a Stop condition before trying to reissue its
transmission. In the meantime, the other device that
has not noticed any difference between the expected
and actual levels on the SDA line continues with its
original transmission. It can do so without any compli-
cations, because so far, the transmission appears
exactly as expected with no other transmitter disturbing
the message.
Clock stretching allows receivers that cannot keep up
with a transmitter to control the flow of incoming data.
Slave Transmit mode can also be arbitrated, when a
master addresses multiple slaves, but this is less com-
mon.
If two master devices are sending a message to two dif-
ferent slave devices at the address stage, the master
sending the lower slave address always wins arbitra-
tion. When two master devices send messages to the
same slave address, and addresses can sometimes
refer to multiple slaves, the arbitration process must
continue into the data stage.
Arbitration usually occurs very rarely, but it is a neces-
sary process for proper multi-master support.
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TABLE 21-2: I2C BUS TERMS
21.4 I2C MODE OPERATION
TERM
Description
All MSSP I2C communication is byte oriented and
shifted out MSb first. Six SFR registers and 2 interrupt
flags interface the module with the PIC® microcon-
troller and user software. Two pins, SDA and SCL, are
exercised by the module to communicate with other
external I2C devices.
Transmitter
The device which shifts data out
onto the bus.
Receiver
Master
The device which shifts data in
from the bus.
The device that initiates a transfer,
generates clock signals and termi-
nates a transfer.
21.4.1 BYTE FORMAT
All communication in I2C is done in 9-bit segments. A
byte is sent from a master to a slave or vice-versa, fol-
lowed by an Acknowledge bit sent back. After the 8th
falling edge of the SCL line, the device outputting data
on the SDA changes that pin to an input and reads in
an Acknowledge value on the next clock pulse.
Slave
The device addressed by the mas-
ter.
Multi-master
Arbitration
A bus with more than one device
that can initiate data transfers.
Procedure to ensure that only one
master at a time controls the bus.
Winning arbitration ensures that
the message is not corrupted.
The clock signal, SCL, is provided by the master. Data
is valid to change while the SCL signal is low, and
sampled on the rising edge of the clock. Changes on
the SDA line while the SCL line is high define special
conditions on the bus, explained below.
Synchronization Procedure to synchronize the
clocks of two or more devices on
the bus.
21.4.2 DEFINITION OF I2C TERMINOLOGY
Idle
No master is controlling the bus,
and both SDA and SCL lines are
high.
There is language and terminology in the description
of I2C communication that have definitions specific to
I2C. That word usage is defined below and may be
used in the rest of this document without explanation.
This table was adapted from the Philips I2C
specification.
Active
Any time one or more master
devices are controlling the bus.
Addressed
Slave
Slave device that has received a
matching address and is actively
being clocked by a master.
21.4.3 SDA AND SCL PINS
Matching
Address
Address byte that is clocked into a
slave that matches the value
stored in SSPADD.
Selection of any I2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open-drain. These
pins should be set by the user to inputs by setting the
appropriate TRIS bits.
Write Request
Read Request
Slave receives a matching
address with R/W bit clear, and is
ready to clock in data.
Note: Data is tied to output zero when an I2C
Master sends an address byte with
the R/W bit set, indicating that it
wishes to clock data out of the
Slave. This data is the next and all
following bytes until a Restart or
Stop.
mode is enabled.
21.4.4 SDA HOLD TIME
The hold time of the SDA pin is selected by the SDAHT
bit of the SSPCON3 register. Hold time is the time SDA
is held valid after the falling edge of SCL. Setting the
SDAHT bit selects a longer 300 ns minimum hold time
and may help on buses with large capacitance.
Clock Stretching When a device on the bus hold
SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled
low by the module while it is out-
putting and expected high state.
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21.4.5 START CONDITION
21.4.7 RESTART CONDITION
The I2C specification defines a Start condition as a
transition of SDA from a high to a low state while SCL
line is high. A Start condition is always generated by
the master and signifies the transition of the bus from
an Idle to an Active state. Figure 21-10 shows wave
forms for Start and Stop conditions.
A Restart is valid any time that a Stop would be valid.
A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart
has the same effect on the slave that a Start would,
resetting all slave logic and preparing it to clock in an
address. The master may want to address the same or
another slave.
A bus collision can occur on a Start condition if the
module samples the SDA line low before asserting it
low. This does not conform to the I2C Specification that
states no bus collision can occur on a Start.
In 10-bit Addressing Slave mode a Restart is required
for the master to clock data out of the addressed
slave. Once a slave has been fully addressed, match-
ing both high and low address bytes, the master can
issue a Restart and the high address byte with the
R/W bit set. The slave logic will then hold the clock
and prepare to clock out data.
21.4.6 STOP CONDITION
A Stop condition is a transition of the SDA line from
low-to-high state while the SCL line is high.
After a full match with R/W clear in 10-bit mode, a prior
match flag is set and maintained. Until a Stop condi-
tion, a high address with R/W clear, or high address
match fails.
Note: At least one SCL low time must appear
before a Stop is valid, therefore, if the SDA
line goes low then high again while the SCL
line stays high, only the Start condition is
detected.
21.4.8 START/STOP CONDITION INTERRUPT
MASKING
The SCIE and PCIE bits of the SSPCON3 register can
enable the generation of an interrupt in Slave modes
that do not typically support this function. Slave modes
where interrupt on Start and Stop detect are already
enabled, these bits will have no effect.
FIGURE 21-12:
I2C START AND STOP CONDITIONS
SDA
SCL
S
P
Change of
Change of
Data Allowed
Data Allowed
Stop
Start
Condition
Condition
FIGURE 21-13:
I2C RESTART CONDITION
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
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21.5 I2C SLAVE MODE OPERATION
21.4.9 ACKNOWLEDGE SEQUENCE
The 9th SCL pulse for any transferred byte in I2C is
dedicated as an Acknowledge. It allows receiving
devices to respond back to the transmitter by pulling
the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The
Acknowledge (ACK) is an active-low signal, pulling the
SDA line low indicated to the transmitter that the
device has received the transmitted data and is ready
to receive more.
The MSSP Slave mode operates in one of four modes
selected in the SSPM bits of SSPCON1 register. The
modes can be divided into 7-bit and 10-bit Addressing
mode. 10-bit Addressing modes operate the same as
7-bit with some additional overhead for handling the
larger addresses.
Modes with Start and Stop bit interrupts operated the
same as the other modes with SSPIF additionally get-
ting set upon detection of a Start, Restart, or Stop
condition.
The result of an ACK is placed in the ACKSTAT bit of
the SSPCON2 register.
21.5.1 SLAVE MODE ADDRESSES
Slave software, when the AHEN and DHEN bits are
set, allow the user to set the ACK value sent back to
the transmitter. The ACKDT bit of the SSPCON2 regis-
ter is set/cleared to determine the response.
The SSPADD register (Register 21-6) contains the
Slave mode address. The first byte received after a
Start or Restart condition is compared against the
value stored in this register. If the byte matches, the
value is loaded into the SSPBUF register and an inter-
rupt is generated. If the value does not match, the
module goes Idle and no indication is given to the soft-
ware that anything happened.
Slave hardware will generate an ACK response if the
AHEN and DHEN bits of the SSPCON3 register are
clear.
There are certain conditions where an ACK will not be
sent by the slave. If the BF bit of the SSPSTAT register
or the SSPOV bit of the SSPCON1 register are set
when a byte is received.
The SSP Mask register (Register 21-5) affects the
address matching process. See Section 21.5.9 “SSP
Mask Register” for more information.
When the module is addressed, after the 8th falling
edge of SCL on the bus, the ACKTIM bit of the
SSPCON3 register is set. The ACKTIM bit indicates
the Acknowledge time of the active bus. The ACKTIM
Status bit is only active when the AHEN bit or DHEN
bit is enabled.
21.5.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data
byte is ignored when determining if there is an address
match.
21.5.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is
compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9
and A8 are the two MSb of the 10-bit address and
stored in bits 2 and 1 of the SSPADD register.
After the acknowledge of the high byte the UA bit is set
and SCL is held low until the user updates SSPADD
with the low address. The low address byte is clocked
in and all 8 bits are compared to the low address value
in SSPADD. Even if there is not an address match;
SSPIF and UA are set, and SCL is held low until
SSPADD is updated to receive a high byte again.
When SSPADD is updated the UA bit is cleared. This
ensures the module is ready to receive the high
address byte on the next communication.
A high and low address match as a write request is
required at the start of all 10-bit addressing communi-
cation. A transmission can be initiated by issuing a
Restart once the slave is addressed, and clocking in
the high address with the R/W bit set. The slave hard-
ware will then acknowledge the read request and pre-
pare to clock out data. This is only valid for a slave
after it has received a complete high and low address
byte match.
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21.5.2 SLAVE RECEPTION
21.5.2.2 7-bit Reception with AHEN and DHEN
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF reg-
ister and Acknowledged.
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1 reg-
ister is set. The BOEN bit of the SSPCON3 register
modifies this operation. For more information see
Register 21-4.
This list describes the steps that need to be taken by
slave software to use these options for I2C communi
cation. Figure 21-15 displays a module using both
address and data holding. Figure 21-16 includes the
operation with the SEN bit of the SSPCON2 register
set.
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See Section 21.2.3 “SPI Master Mode”
for more detail.
1. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
2. Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
3. Slave clears the SSPIF.
21.5.2.1 7-bit Addressing Reception
4. Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSPIF
was after or before the ACK.
This section describes a standard sequence of events
for the MSSP module configured as an I2C Slave in
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 21-13 and Figure 21-14 is used as a visual
reference for this description.
5. Slave reads the address value from SSPBUF,
clearing the BF flag.
6. Slave sets ACK value clocked out to the master
by setting ACKDT.
This is a step by step process of what typically must
be done to accomplish I2C communication.
7. Slave releases the clock by setting CKP.
8. SSPIF is set after an ACK, not after a NACK.
1. Start bit detected.
9. If SEN = 1 the slave hardware will stretch the
clock after the ACK.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
10. Slave clears SSPIF.
3. Matching address with R/W bit clear is received.
Note: SSPIF is still set after the 9th falling edge of
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to master is SSPIF not set
4. The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
11. SSPIF set and CKP cleared after 8th falling
edge of SCL for a received data byte.
7. If SEN = 1; Slave software sets CKP bit to
12. Slave looks at ACKTIM bit of SSPCON3 to
determine the source of the interrupt.
release the SCL line.
8. The master clocks out a data byte.
13. Slave reads the received data from SSPBUF
clearing BF.
9. Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
14. Steps 7-14 are the same for each received data
byte.
10. Software clears SSPIF.
15. Communication is ended by either the slave
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
11. Software reads the received byte from SSPBUF
clearing BF.
12. Steps 8-12 are repeated for all received bytes
from the master.
13. Master sends Stop condition, setting P bit of
SSPSTAT, and the bus goes Idle.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 201
PIC16(L)F1516/7/8/9
FIGURE 21-14:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0)
DS41452B-page 202
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 21-15:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 203
PIC16(L)F1516/7/8/9
FIGURE 21-16:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1)
DS41452B-page 204
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FIGURE 21-17:
I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 205
PIC16(L)F1516/7/8/9
21.5.3
SLAVE TRANSMISSION
21.5.3.2
7-bit Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register, and an ACK pulse is
sent by the slave on the ninth bit.
A master device can transmit a read request to a
slave, and then clock data out of the slave. The list
below outlines what software for a slave will need to
do to accomplish
a
standard transmission.
Figure 21-17 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit
and the SCL pin is held low (see Section 21.5.6
“Clock Stretching” for more detail). By stretching the
clock, the master will be unable to assert another clock
pulse until the slave is done preparing the transmit
data.
1. Master sends a Start condition on SDA and
SCL.
2. S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
3. Matching address with R/W bit set is received by
the Slave setting SSPIF bit.
The transmit data must be loaded into the SSPBUF
register which also loads the SSPSR register. Then the
SCL pin should be released by setting the CKP bit of
the SSPCON1 register. The eight data bits are shifted
out on the falling edge of the SCL input. This ensures
that the SDA signal is valid during the SCL high time.
4. Slave hardware generates an ACK and sets
SSPIF.
5. SSPIF bit is cleared by user.
6. Software reads the received address from
SSPBUF, clearing BF.
7. R/W is set so CKP was automatically cleared
after the ACK.
The ACK pulse from the master-receiver is latched on
the rising edge of the ninth SCL input pulse. This ACK
value is copied to the ACKSTAT bit of the SSPCON2
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is
latched by the slave, the slave goes Idle and waits for
another occurrence of the Start bit. If the SDA line was
low (ACK), the next transmit data must be loaded into
the SSPBUF register. Again, the SCL pin must be
released by setting bit CKP.
8. The slave software loads the transmit data into
SSPBUF.
9. CKP bit is set releasing SCL, allowing the
master to clock the data out of the slave.
10. SSPIF is set after the ACK response from the
master is loaded into the ACKSTAT register.
11. SSPIF bit is cleared.
12. The slave software checks the ACKSTAT bit to
see if the master wants to clock out more data.
An MSSP interrupt is generated for each data transfer
byte. The SSPIF bit must be cleared by software and
the SSPSTAT register is used to determine the status
of the byte. The SSPIF bit is set on the falling edge of
the ninth clock pulse.
Note 1: If the master ACKs the clock will be
stretched.
2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
falling.
21.5.3.1
Slave Mode Bus Collision
13. Steps 9-13 are repeated for each transmitted
byte.
A slave receives a Read request and begins shifting
data out on the SDA line. If a bus collision is detected
and the SBCDE bit of the SSPCON3 register is set, the
BCLIF bit of the PIR register is set. Once a bus collision
is detected, the slave goes Idle and waits to be
addressed again. User software can use the BCLIF bit
to handle a slave bus collision.
14. If the master sends a not ACK; the clock is not
held, but SSPIF is still set.
15. The master sends a Restart condition or a Stop.
16. The slave is no longer addressed.
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2011 Microchip Technology Inc.
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FIGURE 21-18:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 207
PIC16(L)F1516/7/8/9
21.5.3.3
7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPCON3 register
enables additional clock stretching and interrupt gen-
eration after the 8th falling edge of a received match-
ing address. Once a matching address has been
clocked in, CKP is cleared and the SSPIF interrupt is
set.
Figure 21-18 displays a standard waveform of a 7-bit
Address Slave Transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPSTAT is set; SSPIF is set if interrupt on Start
detect is enabled.
3. Master sends matching address with R/W bit
set. After the 8th falling edge of the SCL line the
CKP bit is cleared and SSPIF interrupt is gener-
ated.
4. Slave software clears SSPIF.
5. Slave software reads ACKTIM bit of SSPCON3
register, and R/W and D/A of the SSPSTAT reg-
ister to determine the source of the interrupt.
6. Slave reads the address value from the
SSPBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets ACKDT bit
of the SSPCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPIF.
12. Slave loads value to transmit to the master into
SSPBUF setting the BF bit.
Note: SSPBUF cannot be loaded until after the
ACK.
13. Slave sets CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the 9th SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Note: Master must send a not ACK on the last byte
to ensure that the slave releases the SCL
line to receive a Stop.
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2011 Microchip Technology Inc.
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FIGURE 21-19:
I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 209
PIC16(L)F1516/7/8/9
21.5.4 SLAVE MODE 10-BIT ADDRESS
RECEPTION
21.5.5 10-BIT ADDRESSING WITH ADDRESS OR
DATA HOLD
This section describes a standard sequence of events
for the MSSP module configured as an I2C slave in
10-bit Addressing mode.
Reception using 10-bit addressing with AHEN or
DHEN set is the same as with 7-bit modes. The only
difference is the need to update the SSPADD register
using the UA bit. All functionality, specifically when the
CKP bit is cleared and SCL line is held low are the
same. Figure 21-20 can be used as a reference of a
slave in 10-bit addressing with AHEN set.
Figure 21-19 is used as a visual reference for this
description.
This is a step by step process of what must be done by
slave software to accomplish I2C communication.
Figure 21-21 shows a standard waveform for a slave
transmitter in 10-bit Addressing mode.
1. Bus starts Idle.
2. Master sends Start condition; S bit of SSPSTAT
is set; SSPIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPSTAT register is set.
4. Slave sends ACK and SSPIF is set.
5. Software clears the SSPIF bit.
6. Software reads received address from SSPBUF
clearing the BF flag.
7. Slave loads low address into SSPADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPADD register are not
allowed until after the ACK sequence.
9. Slave sends ACK and SSPIF is set.
Note: If the low address does not match, SSPIF
and UA are still set so that the slave soft-
ware can set SSPADD back to the high
address. BF is not set because there is no
match. CKP is unaffected.
10. Slave clears SSPIF.
11. Slave reads the received matching address
from SSPBUF clearing BF.
12. Slave loads high address into SSPADD.
13. Master clocks a data byte to the slave and
clocks out the slaves ACK on the 9th SCL pulse;
SSPIF is set.
14. If SEN bit of SSPCON2 is set, CKP is cleared by
hardware and the clock is stretched.
15. Slave clears SSPIF.
16. Slave reads the received byte from SSPBUF
clearing BF.
17. If SEN is set the slave sets CKP to release the
SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS41452B-page 210
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PIC16(L)F1516/7/8/9
FIGURE 21-20:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 211
PIC16(L)F1516/7/8/9
FIGURE 21-21:
I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0)
DS41452B-page 212
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 21-22:
I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 213
PIC16(L)F1516/7/8/9
21.5.6 CLOCK STRETCHING
21.5.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus
holds the SCL line low effectively pausing communica-
tion. The slave may stretch the clock to allow more
time to handle data or prepare a response for the mas-
ter device. A master device is not concerned with
stretching as anytime it is active on the bus and not
transferring data it is stretching. Any stretching done
by a slave is invisible to the master software and han-
dled by the hardware that generates SCL.
In 10-bit Addressing mode, when the UA bit is set the
clock is always stretched. This is the only time, the
SCL is stretched without CKP being cleared. SCL is
released immediately after a write to SSPADD.
Note: Previous versions of the module did not
stretch the clock if the second address byte
did not match.
21.5.6.3 Byte NACKing
The CKP bit of the SSPCON1 register is used to con-
trol stretching in software. Any time the CKP bit is
cleared, the module will wait for the SCL line to go low
and then hold it. Setting CKP will release SCL and
allow more communication.
When AHEN bit of SSPCON3 is set; CKP is cleared by
hardware after the 8th falling edge of SCL for a
received matching address byte. When DHEN bit of
SSPCON3 is set; CKP is cleared after the 8th falling
edge of SCL for received data.
21.5.6.1 Normal Clock Stretching
Stretching after the 8th falling edge of SCL allows the
slave to look at the received address or data and
decide if it wants to ACK the received data.
Following an ACK if the R/W bit of SSPSTAT is set, a
read request, the slave hardware will clear CKP. This
allows the slave time to update SSPBUF with data to
transfer to the master. If the SEN bit of SSPCON2 is
set, the slave hardware will always stretch the clock
after the ACK sequence. Once the slave is ready; CKP
is set by software and communication resumes.
21.5.7 CLOCK SYNCHRONIZATION AND
THE CKP BIT
Any time the CKP bit is cleared, the module will wait
for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
until the SCL output is already sampled low. There-
fore, the CKP bit will not assert the SCL line until an
external I2C master device has already asserted the
SCL line. The SCL output will remain low until the CKP
bit is set and all other devices on the I2C bus have
released SCL. This ensures that a write to the CKP bit
will not violate the minimum high time requirement for
SCL (see Figure 21-22).
Note 1: The BF bit has no effect on if the clock will
be stretched or not. This is different than
previous versions of the module that
would not stretch the clock, clear CKP, if
SSPBUF was read before the 9th falling
edge of SCL.
2: Previous versions of the module did not
stretch the clock for a transmission if
SSPBUF was loaded before the 9th falling
edge of SCL. It is now always cleared for
read requests.
FIGURE 21-23:
CLOCK SYNCHRONIZATION TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPCON1
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21.5.8 GENERAL CALL ADDRESS SUPPORT
In 10-bit Address mode, the UA bit will not be set on
the reception of the general call address. The slave
will prepare to receive the second byte as data, just as
it would in 7-bit mode.
The addressing procedure for the I2C bus is such that
the first byte after the Start condition usually deter-
mines which device will be the slave addressed by the
master device. The exception is the general call
address which can address all devices. When this
address is used, all devices should, in theory, respond
with an Acknowledge.
If the AHEN bit of the SSPCON3 register is set, just as
with any other address reception, the slave hardware
will stretch the clock after the 8th falling edge of SCL.
The slave must then set its ACKDT value and release
the clock with communication progressing as it would
normally.
The general call address is a reserved address in the
I2C protocol, defined as address 0x00. When the
GCEN bit of the SSPCON2 register is set, the slave
module will automatically ACK the reception of this
address regardless of the value stored in SSPADD.
After the slave clocks in an address of all zeros with
the R/W bit clear, an interrupt is generated and slave
software can read SSPBUF and respond.
Figure 21-23 shows
sequence.
a
general gall reception
FIGURE 21-24:
SLAVE MODE GENERAL CALL ADDRESS SEQUENCE
Address is compared to General Call Address
after ACK, set interrupt
Receiving Data
D5 D4 D3 D2 D1
ACK
R/W = 0
ACK
General Call Address
SDA
D7 D6
D0
8
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
9
S
SSPIF
BF (SSPSTAT<0>)
Cleared by software
SSPBUF is read
GCEN (SSPCON2<7>)
’1’
21.5.9 SSP MASK REGISTER
An SSP Mask (SSPMSK) register (Register 21-5) is
available in I2C Slave mode as a mask for the value
held in the SSPSR register during an address
comparison operation. A zero (‘0’) bit in the SSPMSK
register has the effect of making the corresponding bit
of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset
condition and, therefore, has no effect on standard
SSP operation until written with a mask value.
The SSP Mask register is active during:
• 7-bit Address mode: address compare of A<7:1>.
• 10-bit Address mode: address compare of A<7:0>
only. The SSP mask has no effect during the
reception of the first (high) byte of the address.
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21.6.1 I2C MASTER MODE OPERATION
2
21.6 I C MASTER MODE
The master device generates all of the serial clock
pulses and the Start and Stop conditions. A transfer is
ended with a Stop condition or with a Repeated Start
condition. Since the Repeated Start condition is also
the beginning of the next serial transfer, the I2C bus will
not be released.
Master mode is enabled by setting and clearing the
appropriate SSPM bits in the SSPCON1 register and
by setting the SSPEN bit. In Master mode, the SDA and
SCK pins must be configured as inputs. The MSSP
peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic ‘0’. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. Start and Stop
conditions are output to indicate the beginning and the
end of a serial transfer.
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop con-
ditions. The Stop (P) and Start (S) bits are cleared from
a Reset or when the MSSP module is disabled. Control
of the I2C bus may be taken when the P bit is set, or the
bus is Idle.
In Firmware Controlled Master mode, user code
conducts all I2C bus operations based on Start and
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All
other communication is done by the user software
directly manipulating the SDA and SCL lines.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic ‘1’. Thus, the first byte transmitted is a 7-bit slave
address followed by a ‘1’ to indicate the receive bit.
Serial data is received via SDA, while SCL outputs the
serial clock. Serial data is received 8 bits at a time. After
each byte is received, an Acknowledge bit is transmit-
ted. Start and Stop conditions indicate the beginning
and end of transmission.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP interrupt, if enabled):
• Start condition detected
• Stop condition detected
• Data transfer byte transmitted/received
• Acknowledge transmitted/received
• Repeated Start generated
A Baud Rate Generator is used to set the clock fre-
quency output on SCL. See Section 21.7 “Baud Rate
Generator” for more detail.
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queue-
ing of events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
initiate transmission before the Start con-
dition is complete. In this case, the SSP-
BUF will not be written to and the WCOL
bit will be set, indicating that a write to the
SSPBUF did not occur
2: When in Master mode, Start/Stop detec-
tion is masked and an interrupt is gener-
ated when the SEN/PEN bit is cleared and
the generation is complete.
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21.6.2 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the Baud Rate Gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the Baud Rate Generator is reloaded with
the contents of SSPADD<7:0> and begins counting.
This ensures that the SCL high time will always be at
least one BRG rollover count in the event that the clock
is held low by an external device (Figure 21-25).
FIGURE 21-25:
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SDA
DX
DX ‚ – 1
SCL allowed to transition high
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
21.6.3 WCOL STATUS FLAG
If the user writes the SSPBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPBUF
was attempted while the module was not Idle.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
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21.6.4 I C MASTER MODE START
ister will be automatically cleared by hardware; the
Baud Rate Generator is suspended, leaving the SDA
line held low and the Start condition is complete.
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator is reloaded with the contents of
SSPADD<7:0> and starts its count. If SCL and SDA
are both sampled high when the Baud Rate Generator
times out (TBRG), the SDA pin is driven low. The action
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Gen-
erator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Genera-
tor times out (TBRG), the SEN bit of the SSPCON2 reg-
Note 1: If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition,
the SCL line is sampled low before the
SDA line is driven low, a bus collision
occurs, the Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is
aborted and the I2C module is reset into
its Idle state.
2: The Philips I2C Specification states that a
bus collision cannot occur on a Start.
FIGURE 21-26:
FIRST START BIT TIMING
Set S bit (SSPSTAT<3>)
Write to SEN bit occurs here
At completion of Start bit,
hardware clears SEN bit
and sets SSPIF bit
SDA = 1,
SCL = 1
TBRG
TBRG
Write to SSPBUF occurs here
SDA
2nd bit
1st bit
TBRG
SCL
S
TBRG
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21.6.5 I C MASTER MODE REPEATED
SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
START CONDITION TIMING
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(TBRG). When the Baud Rate Generator times out, if
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one TBRG. This
action is then followed by assertion of the SDA pin
(SDA = 0) for one TBRG while SCL is high. SCL is
asserted low. Following this, the RSEN bit of the
Note 1: If RSEN is programmed while any other
event is in progress, it will not take effect.
2: A bus collision during the Repeated Start
condition occurs if:
• SDA is sampled low when SCL
goes from low-to-high.
• SCL goes low before SDA is
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
FIGURE 21-27:
REPEAT START CONDITION WAVEFORM
S bit set by hardware
Write to SSPCON2
occurs here
SDA = 1,
At completion of Start bit,
hardware clears RSEN bit
and sets SSPIF
SDA = 1,
SCL = 1
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
SCL
Write to SSPBUF occurs here
TBRG
Sr
Repeated Start
TBRG
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21.6.6 I2C MASTER MODE TRANSMISSION
21.6.6.3
ACKSTAT Status Flag
In Transmit mode, the ACKSTAT bit of the SSPCON2
register is cleared when the slave has sent an Acknowl-
edge (ACK = 0) and is set when the slave does not
Acknowledge (ACK = 1). A slave sends an Acknowl-
edge when it has recognized its address (including a
general call), or when the slave has properly received
its data.
Transmission of a data byte, a 7-bit address or the
other half of a 10-bit address is accomplished by simply
writing a value to the SSPBUF register. This action will
set the Buffer Full flag bit, BF and allow the Baud Rate
Generator to begin counting and start the next trans-
mission. Each bit of address/data will be shifted out
onto the SDA pin after the falling edge of SCL is
asserted. SCL is held low for one Baud Rate Generator
rollover count (TBRG). Data should be valid before SCL
is released high. When the SCL pin is released high, it
is held that way for TBRG. The data on the SDA pin
must remain stable for that duration and some hold
time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock),
the BF flag is cleared and the master releases SDA.
This allows the slave device being addressed to
respond with an ACK bit during the ninth bit time if an
address match occurred, or if data was received prop-
erly. The status of ACK is written into the ACKSTAT bit
on the rising edge of the ninth clock. If the master
receives an Acknowledge, the Acknowledge Status bit,
ACKSTAT, is cleared. If not, the bit is set. After the ninth
clock, the SSPIF bit is set and the master clock (Baud
Rate Generator) is suspended until the next data byte
is loaded into the SSPBUF, leaving SCL low and SDA
unchanged (Figure 21-27).
21.6.6.4 Typical transmit sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set by hardware on completion of the
Start.
3. SSPIF is cleared by software.
4. The MSSP module will wait the required start
time before any other operation takes place.
5. The user loads the SSPBUF with the slave
address to transmit.
6. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
7. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
8. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
After the write to the SSPBUF, each bit of the address
will be shifted out on the falling edge of SCL until all
seven address bits and the R/W bit are completed. On
the falling edge of the eighth clock, the master will
release the SDA pin, allowing the slave to respond with
an Acknowledge. On the falling edge of the ninth clock,
the master will sample the SDA pin to see if the address
was recognized by a slave. The status of the ACK bit is
loaded into the ACKSTAT Status bit of the SSPCON2
register. Following the falling edge of the ninth clock
transmission of the address, the SSPIF is set, the BF
flag is cleared and the Baud Rate Generator is turned
off until another write to the SSPBUF takes place, hold-
ing SCL low and allowing SDA to float.
9. The user loads the SSPBUF with eight bits of
data.
10. Data is shifted out the SDA pin until all 8 bits are
transmitted.
11. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
12. Steps 8-11 are repeated for all transmitted data
bytes.
13. The user generates a Stop or Restart condition
by setting the PEN or RSEN bits of the
SSPCON2 register. Interrupt is generated once
the Stop/Restart condition is complete.
21.6.6.1
BF Status Flag
In Transmit mode, the BF bit of the SSPSTAT register
is set when the CPU writes to SSPBUF and is cleared
when all 8 bits are shifted out.
21.6.6.2
WCOL Status Flag
If the user writes the SSPBUF when a transmit is
already in progress (i.e., SSPSR is still shifting out a
data byte), the WCOL is set and the contents of the buf-
fer are unchanged (the write does not occur).
WCOL must be cleared by software before the next
transmission.
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FIGURE 21-28:
I C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS)
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21.6.7.4 Typical Receive Sequence:
21.6.7
I C MASTER MODE RECEPTION
Master mode reception is enabled by programming the
Receive Enable bit, RCEN bit of the SSPCON2
register.
1. The user generates a Start condition by setting
the SEN bit of the SSPCON2 register.
2. SSPIF is set by hardware on completion of the
Start.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
3. SSPIF is cleared by software.
4. User writes SSPBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the con-
tents of the SSPSR are loaded into the SSPBUF, the
BF flag bit is set, the SSPIF flag bit is set and the Baud
Rate Generator is suspended from counting, holding
SCL low. The MSSP is now in Idle state awaiting the
next command. When the buffer is read by the CPU,
the BF flag bit is automatically cleared. The user can
then send an Acknowledge bit at the end of reception
by setting the Acknowledge Sequence Enable, ACKEN
bit of the SSPCON2 register.
5. Address is shifted out the SDA pin until all 8 bits
are transmitted. Transmission begins as soon
as SSPBUF is written to.
6. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPCON2 register.
7. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
8. User sets the RCEN bit of the SSPCON2 register
and the master clocks in a byte from the slave.
9. After the 8th falling edge of SCL, SSPIF and BF
are set.
10. Master clears SSPIF and reads the received
byte from SSPUF, clears BF.
21.6.7.1
BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPBUF from SSPSR. It is
cleared when the SSPBUF register is read.
11. Master sets ACK value sent to slave in ACKDT
bit of the SSPCON2 register and initiates the
ACK by setting the ACKEN bit.
21.6.7.2
SSPOV Status Flag
12. Masters ACK is clocked out to the slave and
SSPIF is set.
In receive operation, the SSPOV bit is set when 8 bits
are received into the SSPSR and the BF flag bit is
already set from a previous reception.
13. User clears SSPIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
21.6.7.3
WCOL Status Flag
15. Master sends a not ACK or Stop to end
communication.
If the user writes the SSPBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
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FIGURE 21-29:
I C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS)
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21.6.8
ACKNOWLEDGE SEQUENCE
TIMING
21.6.9
STOP CONDITION TIMING
A Stop bit is asserted on the SDA pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN bit of the SSPCON2 register. At the end of a
receive/transmit, the SCL line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDA line low. When the SDA
line is sampled low, the Baud Rate Generator is
reloaded and counts down to ‘0’. When the Baud Rate
Generator times out, the SCL pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDA pin will be deasserted. When the SDA
pin is sampled high while SCL is high, the P bit of the
SSPSTAT register is set. A TBRG later, the PEN bit is
cleared and the SSPIF bit is set (Figure 21-30).
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN bit of the
SSPCON2 register. When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate
Generator then counts for one rollover period (TBRG)
and the SCL pin is deasserted (pulled high). When the
SCL pin is sampled high (clock arbitration), the Baud
Rate Generator counts for TBRG. The SCL pin is then
pulled low. Following this, the ACKEN bit is automatically
cleared, the Baud Rate Generator is turned off and the
MSSP module then goes into Idle mode (Figure 21-29).
21.6.9.1
WCOL Status Flag
If the user writes the SSPBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does
not occur).
21.6.8.1
WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write does
not occur).
FIGURE 21-30:
ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
write to SSPCON2
ACKEN automatically cleared
ACKEN = 1, ACKDT = 0
TBRG
ACK
TBRG
SDA
SCL
D0
8
9
SSPIF
Cleared in
SSPIF set at
the end of receive
software
Cleared in
software
SSPIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
FIGURE 21-31:
STOP CONDITION RECEIVE OR TRANSMIT MODE
SCL = 1for TBRG, followed by SDA = 1for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Write to SSPCON2,
set PEN
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
Falling edge of
9th clock
TBRG
SCL
SDA
ACK
P
TBRG
TBRG
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
Note: TBRG = one Baud Rate Generator period.
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21.6.10 SLEEP OPERATION
21.6.13 MULTI -MASTER COMMUNICATION,
BUS COLLISION AND BUS
While in Sleep mode, the I2C slave module can receive
addresses or data and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if the MSSP interrupt is enabled).
ARBITRATION
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a ‘1’ on SDA, by letting SDA float high and
another master asserts a ‘0’. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag, BCLIF and reset the
I2C port to its Idle state (Figure 21-31).
21.6.11 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
21.6.12 MULTI-MASTER MODE
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the
MSSP module is disabled. Control of the I2C bus may
be taken when the P bit of the SSPSTAT register is set,
or the bus is Idle, with both the S and P bits clear. When
the bus is busy, enabling the SSP interrupt will gener-
ate the interrupt when the Stop condition occurs.
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are deasserted and the
SSPBUF can be written to. When the user services the
bus collision Interrupt Service Routine and if the I2C
bus is free, the user can resume communication by
asserting a Start condition.
In multi-master operation, the SDA line must be
monitored for arbitration to see if the signal level is the
expected output level. This check is performed by
hardware with the result placed in the BCLIF bit.
If a Start, Repeated Start, Stop or Acknowledge condi-
tion was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deas-
serted and the respective control bits in the SSPCON2
register are cleared. When the user services the bus col-
lision Interrupt Service Routine and if the I2C bus is free,
the user can resume communication by asserting a Start
condition.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A Start Condition
The master will continue to monitor the SDA and SCL
pins. If a Stop condition occurs, the SSPIF bit will be set.
• A Repeated Start Condition
• An Acknowledge Condition
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of Start and Stop conditions allows the deter-
mination of when the bus is free. Control of the I2C bus
can be taken when the P bit is set in the SSPSTAT
register, or the bus is Idle and the S and P bits are
cleared.
FIGURE 21-32:
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLIF)
BCLIF
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If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 21-34). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to zero; if the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
21.6.13.1 Bus Collision During a Start
Condition
During a Start condition, a bus collision occurs if:
a) SDA or SCL are sampled low at the beginning of
the Start condition (Figure 21-32).
b) SCL is sampled low before SDA is asserted low
(Figure 21-33).
During a Start condition, both the SDA and the SCL
pins are monitored.
Note:
The reason that bus collision is not a fac-
tor during a Start condition is that no two
bus masters can assert a Start condition
at the exact same time. Therefore, one
master will always assert SDA before the
other. This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address fol-
lowing the Start condition. If the address is
the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted,
• the BCLIF flag is set and
•
the MSSP module is reset to its Idle state
(Figure 21-32).
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded and counts down. If the
SCL pin is sampled low while SDA is high, a bus colli-
sion occurs because it is assumed that another master
is attempting to drive a data ‘1’ during the Start
condition.
FIGURE 21-33:
BUS COLLISION DURING START CONDITION (SDA ONLY)
SDA goes low before the SEN bit is set.
Set BCLIF,
S bit and SSPIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSP module reset into Idle state.
SDA sampled low before
Start condition. Set BCLIF.
S bit and SSPIF set because
SDA = 0, SCL = 1.
BCLIF
SSPIF and BCLIF are
cleared by software
S
SSPIF
SSPIF and BCLIF are
cleared by software
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PIC16(L)F1516/7/8/9
FIGURE 21-34:
BUS COLLISION DURING START CONDITION (SCL = 0)
SDA = 0, SCL = 1
TBRG
TBRG
SDA
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL
SEN
SCL = 0before SDA = 0,
bus collision occurs. Set BCLIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLIF.
BCLIF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSPIF
FIGURE 21-35:
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S
Set SSPIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time-out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
BCLIF
S
SSPIF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSPIF
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 227
PIC16(L)F1516/7/8/9
If SDA is low, a bus collision has occurred (i.e., another
master is attempting to transmit a data ‘0’, Figure 21-35).
If SDA is sampled high, the BRG is reloaded and begins
counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two
masters can assert SDA at exactly the same time.
21.6.13.2 Bus Collision During a Repeated
Start Condition
During a Repeated Start condition, a bus collision
occurs if:
a) A low level is sampled on SDA when SCL goes
from low level to high level.
If SCL goes from high-to-low before the BRG times out
and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to
transmit a data ‘1’ during the Repeated Start condition,
see Figure 21-36.
b) SCL goes low before SDA is asserted low,
indicating that another master is attempting to
transmit a data ‘1’.
When the user releases SDA and the pin is allowed to
float high, the BRG is loaded with SSPADD and counts
down to zero. The SCL pin is then deasserted and
when sampled high, the SDA pin is sampled.
If, at the end of the BRG time-out, both SCL and SDA
are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count,
regardless of the status of the SCL pin, the SCL pin is
driven low and the Repeated Start condition is
complete.
FIGURE 21-36:
BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)
SDA
SCL
Sample SDA when SCL goes high.
If SDA = 0, set BCLIF and release SDA and SCL.
RSEN
BCLIF
Cleared by software
’0’
S
’0’
SSPIF
FIGURE 21-37:
BUS COLLISION DURING REPEATED START CONDITION (CASE 2)
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
BCLIF
RSEN
set BCLIF. Release SDA and SCL.
Interrupt cleared
by software
’0’
S
SSPIF
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Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 21-37). If the SCL pin is sampled
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 21-38).
21.6.13.3 Bus Collision During a Stop
Condition
Bus collision occurs during a Stop condition if:
a) After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
b) After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
FIGURE 21-38:
BUS COLLISION DURING A STOP CONDITION (CASE 1)
SDA sampled
low after TBRG,
set BCLIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
FIGURE 21-39:
BUS COLLISION DURING A STOP CONDITION (CASE 2)
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLIF
Assert SDA
SCL
PEN
BCLIF
P
’0’
’0’
SSPIF
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 229
PIC16(L)F1516/7/8/9
TABLE 21-3: SUMMARY OF REGISTERS ASSOCIATED WITH I2C™ OPERATION
Reset
Valueson
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
PIE1
GIE
PEIE
ADIE
—
TMR0IE
RCIE
—
INTE
TXIE
—
IOCIE
SSPIE
BCLIE
SSPIF
BCLIF
TMR0IF
CCP1IE
—
INTF
TMR2IE
—
IOCIF
80
81
TMR1GIE
OSFIE
TMR1IE
CCP2IE
TMR1IF
PIE2
82
TMR1GIF
OSFIF
ADIF
RCIF
TXIF
CCP1IF
—
TMR2IF
—
PIR1
83
PIR2
—
—
—
CCP2IF
84
SSPADD
SSPBUF
SSPCON1
SSPCON2
SSPCON3
SSPMSK
SSPSTAT
TRISA
ADD<7:0>
Synchronous Serial Port Receive Buffer/Transmit Register
236
189*
233
234
235
236
232
116
WCOL
GCEN
ACKTIM
MSK7
SSPOV
ACKSTAT
PCIE
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
MSK4
P
SSPM<3:0>
RCEN
SDAHT
MSK3
S
PEN
SBCDE
MSK2
R/W
RSEN
AHEN
MSK1
UA
SEN
DHEN
MSK0
BF
MSK6
MSK5
D/A
SMP
CKE
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I2C™ mode.
*
Page provides register information.
DS41452B-page 230
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2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
21.7 BAUD RATE GENERATOR
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I2C and SPI Master
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register (Register 21-6).
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Table 21-4 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 21-1:
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
FOSC
FCLOCK = ----------------------------------------------
SSPADD + 14
An internal signal “Reload” in Figure 21-39 triggers the
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 21-40:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM<3:0>
SSPADD<7:0>
SSPM<3:0>
SCL
Reload
Control
Reload
BRG Down Counter
SSPCLK
FOSC/2
Note: Values of 0x00, 0x01 and 0x02 are not valid
for SSPADD when used as a Baud Rate
Generator for I2C. This is an implementation
limitation.
TABLE 21-4: MSSP CLOCK RATE W/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
4 MHz
1 MHz
09h
0Ch
27h
09h
400 kHz(1)
308 kHz
100 kHz
100 kHz
Note 1: The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
100 kHz) in all details, but may be used with care where higher rates are required by the application.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 231
PIC16(L)F1516/7/8/9
21.8 MSSP Control Registers
REGISTER 21-1: SSPSTAT: SSP STATUS REGISTER
R/W-0/0
SMP
R/W-0/0
CKE
R-0/0
D/A
R-0/0
P
R-0/0
S
R-0/0
R/W
R-0/0
UA
R-0/0
BF
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
SMP: SPI Data Input Sample bit
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
In I2C Master or Slave mode:
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
bit 6
CKE: SPI Clock Edge Select bit (SPI mode only)
In SPI Master or Slave mode:
1= Transmit occurs on transition from active to Idle clock state
0= Transmit occurs on transition from Idle to active clock state
In I2C™ mode only:
1= Enable input logic so that thresholds are compliant with SMbus specification
0= Disable SMbus specific inputs
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)
0= Stop bit was not detected last
bit 3
bit 2
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)
0= Start bit was not detected last
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the address match
to the next Start bit, Stop bit, or not ACK bit.
In I2C Slave mode:
1= Read
0= Write
In I2C Master mode:
1= Transmit is in progress
0= Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode.
bit 1
bit 0
UA: Update Address bit (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full
0= Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty
DS41452B-page 232
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PIC16(L)F1516/7/8/9
REGISTER 21-2: SSPCON1: SSP CONTROL REGISTER 1
R/C/HS-0/0
WCOL
R/C/HS-0/0
SSPOV
R/W-0/0
SSPEN
R/W-0/0
CKP
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SSPM<3:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware C = User cleared
bit 7
WCOL: Write Collision Detect bit
Master mode:
1= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started
0= No collision
Slave mode:
1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
0= No collision
bit 6
SSPOV: Receive Overflow Indicator bit(1)
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2)
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3)
0= Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level
0= Idle state for clock is a low level
In I2C Slave mode:
SCL release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
In I2C Master mode:
Unused in this mode
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin, SS pin control enabled
0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1000= I2C Master mode, clock = FOSC / (4 * (SSPADD+1))(4)
1001= Reserved
1010= SPI Master mode, clock = FOSC/(4 * (SSPADD+1))(5)
1011= I2C firmware controlled Master mode (Slave idle)
1100= Reserved
1101= Reserved
1110= I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111= I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Note 1:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
2:
3:
4:
5:
SSPADD values of 0, 1 or 2 are not supported for I2C Mode.
SSPADD value of ‘0’ is not supported. Use SSPM = 0000instead.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 233
PIC16(L)F1516/7/8/9
REGISTER 21-3: SSPCON2: SSP CONTROL REGISTER 2
R/W-0/0
GCEN
R-0/0
R/W-0/0
ACKDT
R/S/HS-0/0 R/S/HS-0/0
ACKEN RCEN
R/S/HS-0/0
PEN
R/S/HS-0/0 R/W/HS-0/0
RSEN SEN
bit 0
ACKSTAT
bit 7
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
-n/n = Value at POR and BOR/Value at all other Resets
HC = Cleared by hardware S = User set
bit 7
bit 6
bit 5
GCEN: General Call Enable bit (in I2C Slave mode only)
1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR
0= General call address disabled
ACKSTAT: Acknowledge Status bit (in I2C mode only)
1= Acknowledge was not received
0= Acknowledge was received
ACKDT: Acknowledge Data bit (in I2C mode only)
In Receive mode:
Value transmitted when the user initiates an Acknowledge sequence at the end of a receive
1= Not Acknowledge
0= Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)
In Master Receive mode:
1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.
Automatically cleared by hardware.
0= Acknowledge sequence Idle
bit 3
bit 2
RCEN: Receive Enable bit (in I2C Master mode only)
1= Enables Receive mode for I2C
0= Receive Idle
PEN: Stop Condition Enable bit (in I2C Master mode only)
SCKMSSP Release Control:
1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.
0= Stop condition Idle
bit 1
bit 0
RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)
1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Repeated Start condition Idle
SEN: Start Condition Enabled bit (in I2C Master mode only)
In Master mode:
1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.
0= Start condition Idle
In Slave mode:
1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0= Clock stretching is disabled
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be
set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled).
DS41452B-page 234
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PIC16(L)F1516/7/8/9
REGISTER 21-4: SSPCON3: SSP CONTROL REGISTER 3
R-0/0
R/W-0/0
PCIE
R/W-0/0
SCIE
R/W-0/0
BOEN
R/W-0/0
SDAHT
R/W-0/0
SBCDE
R/W-0/0
AHEN
R/W-0/0
DHEN
ACKTIM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
bit 4
ACKTIM: Acknowledge Time Status bit (I2C mode only)(3)
1= Indicates the I2C bus is in an Acknowledge sequence, set on 8TH falling edge of SCL clock
0= Not an Acknowledge sequence, cleared on 9TH rising edge of SCL clock
PCIE: Stop Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Stop condition
0= Stop detection interrupts are disabled(2)
SCIE: Start Condition Interrupt Enable bit (I2C mode only)
1= Enable interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled(2)
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:(1)
1= SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
SSPCON1 register is set, and the buffer is not updated
In I2C Master mode and SPI Master mode:
This bit is ignored.
In I2C Slave mode:
1= SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
of the SSPOV bit only if the BF bit = 0.
0= SSPBUF is only updated when SSPOV is clear
bit 3
bit 2
SDAHT: SDA Hold Time Selection bit (I2C mode only)
1= Minimum of 300 ns hold time on SDA after the falling edge of SCL
0= Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes Idle
1= Enable slave bus collision interrupts
0= Slave bus collision interrupts are disabled
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
SSPCON1 register will be cleared and the SCL will be held low.
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
of the SSPCON1 register and SCL is held low.
0= Data holding is disabled
Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 235
PIC16(L)F1516/7/8/9
REGISTER 21-5: SSPMSK: SSP MASK REGISTER
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
MSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7-1
bit 0
MSK<7:1>: Mask bits
1= The received address bit n is compared to SSPADD<n> to detect I2C address match
0= The received address bit n is not used to detect I2C address match
MSK<0>: Mask bit for I2C Slave mode, 10-bit Address
I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111):
1= The received address bit 0 is compared to SSPADD<0> to detect I2C address match
0= The received address bit 0 is not used to detect I2C address match
I2C Slave mode, 7-bit address:
The bit is ignored.
REGISTER 21-6: SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
ADD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
Master mode:
bit 7-0
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat-
tern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are
compared by hardware and are not affected by the value in this register.
bit 2-1
bit 0
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
ADD<7:0>: Eight Least Significant bits of 10-bit address
7-Bit Slave mode:
bit 7-1
bit 0
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
DS41452B-page 236
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
The EUSART module includes the following capabilities:
22.0 ENHANCED UNIVERSAL
SYNCHRONOUS
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
The Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous
modes
• Sleep operation
system.
Full-Duplex
mode
is
useful
for
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in Figure 22-1 and Figure 22-2.
FIGURE 22-1:
EUSART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIE
Interrupt
TXIF
TXREG Register
8
TX/CK pin
MSb
(8)
LSb
0
Pin Buffer
and Control
• • •
Transmit Shift Register (TSR)
TXEN
TRMT
SPEN
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
+ 1
Multiplier x4
x16 x64
TX9D
SYNC
BRGH
BRG16
1
X
X
X
1
1
0
1
0
0
0
1
0
0
0
SPBRGH
SPBRGL
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 237
PIC16(L)F1516/7/8/9
FIGURE 22-2:
EUSART RECEIVE BLOCK DIAGRAM
SPEN
CREN
OERR
RCIDL
RX/DT pin
RSR Register
MSb
Stop (8)
LSb
Start
Pin Buffer
and Control
Data
Recovery
7
1
0
• • •
Baud Rate Generator
FOSC
RX9
÷ n
BRG16
n
+ 1
Multiplier
x4
x16 x64
SYNC
BRGH
BRG16
1
X
1
1
0
1
0
0
0
1
0
0
0
FIFO
SPBRGH
SPBRGL
X
X
RX9D
FERR
RCREG Register
8
Data Bus
RCIF
RCIE
Interrupt
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These registers are detailed in Register 22-1,
Register 22-2 and Register 22-3, respectively.
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
DS41452B-page 238
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.1.1.2
Transmitting Data
22.1 EUSART Asynchronous Mode
A transmission is initiated by writing a character to the
TXREG register. If this is the first character, or the
previous character has been completely flushed from
the TSR, the data in the TXREG is immediately
transferred to the TSR register. If the TSR still contains
all or part of a previous character, the new character
data is held in the TXREG until the Stop bit of the
previous character has been transmitted. The pending
character in the TXREG is then transferred to the TSR
in one TCY immediately following the Stop bit
transmission. The transmission of the Start bit, data bits
and Stop bit sequence commences immediately
following the transfer of the data to the TSR from the
TXREG.
The EUSART transmits and receives data using the
standard non-return-to-zero (NRZ) format. NRZ is
implemented with two levels: a VOH mark state which
represents a ‘1’ data bit, and a VOL space state which
represents a ‘0’ data bit. NRZ refers to the fact that
consecutively transmitted data bits of the same value
stay at the output level of that bit without returning to a
neutral level between each bit transmission. An NRZ
transmission port idles in the mark state. Each character
transmission consists of one Start bit followed by eight
or nine data bits and is always terminated by one or
more Stop bits. The Start bit is always a space and the
Stop bits are always marks. The most common data
format is 8 bits. Each transmitted bit persists for a period
of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate
frequencies from the system oscillator. See Table 22-5
for examples of baud rate configurations.
22.1.1.3
Transmit Interrupt Flag
The TXIF interrupt flag bit of the PIR1 register is set
whenever the EUSART transmitter is enabled and no
character is being held for transmission in the TXREG.
In other words, the TXIF bit is only clear when the TSR
is busy with a character and a new character has been
queued for transmission in the TXREG. The TXIF flag bit
is not cleared immediately upon writing TXREG. TXIF
becomes valid in the second instruction cycle following
the write execution. Polling TXIF immediately following
the TXREG write will return invalid results. The TXIF bit
is read-only, it cannot be set or cleared by software.
The EUSART transmits and receives the LSb first. The
EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud
rate. Parity is not supported by the hardware, but can
be implemented in software and stored as the ninth
data bit.
22.1.1
EUSART ASYNCHRONOUS
TRANSMITTER
The TXIF interrupt can be enabled by setting the TXIE
interrupt enable bit of the PIE1 register. However, the
TXIF flag bit will be set whenever the TXREG is empty,
regardless of the state of TXIE enable bit.
The EUSART transmitter block diagram is shown in
Figure 22-1. The heart of the transmitter is the serial
Transmit Shift Register (TSR), which is not directly
accessible by software. The TSR obtains its data from
the transmit buffer, which is the TXREG register.
To use interrupts when transmitting data, set the TXIE
bit only when there is more data to send. Clear the
TXIE interrupt enable bit upon writing the last character
of the transmission to the TXREG.
22.1.1.1
Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous
operations by configuring the following three control
bits:
• TXEN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the TXEN bit of the TXSTA register enables the
transmitter circuitry of the EUSART. Clearing the SYNC
bit of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART and automatically
configures the TX/CK I/O pin as an output. If the TX/CK
pin is shared with an analog peripheral, the analog I/O
function must be disabled by clearing the corresponding
ANSEL bit.
Note 1: The TXIF Transmitter Interrupt flag is set
when the TXEN enable bit is set.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 239
PIC16(L)F1516/7/8/9
22.1.1.4
TSR Status
22.1.1.6
Asynchronous Transmission Set-up:
The TRMT bit of the TXSTA register indicates the
status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is
cleared when a character is transferred to the TSR
register from the TXREG. The TRMT bit remains clear
until all bits have been shifted out of the TSR register.
No interrupt logic is tied to this bit, so the user has to
poll this bit to determine the TSR status.
1. Initialize the SPBRGH, SPBRGL register pair and
the BRGH and BRG16 bits to achieve the desired
baud rate (see Section 22.4 “EUSART Baud
Rate Generator (BRG)”).
2. Set the RXx/DTx and TXx/CKx TRIS controls to
‘1’.
3. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
4. If 9-bit transmission is desired, set the TX9 con-
trol bit. A set ninth data bit will indicate that the 8
Least Significant data bits are an address when
the receiver is set for address detection.
22.1.1.5
Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions.
When the TX9 bit of the TXSTA register is set, the
EUSART will shift 9 bits out for each character transmit-
ted. The TX9D bit of the TXSTA register is the ninth,
and Most Significant, data bit. When transmitting 9-bit
data, the TX9D data bit must be written before writing
the 8 Least Significant bits into the TXREG. All nine bits
of data will be transferred to the TSR shift register
immediately after the TXREG is written.
5. Enable the transmission by setting the TXEN
control bit. This will cause the TXIF interrupt bit
to be set.
6. If interrupts are desired, set the TXIE interrupt
enable bit of the PIE1 register. An interrupt will
occur immediately provided that the GIE and
PEIE bits of the INTCON register are also set.
7. If 9-bit transmission is selected, the ninth bit
should be loaded into the TX9D data bit.
A special 9-bit Address mode is available for use with
multiple receivers. See Section 22.1.2.7 “Address
Detection” for more information on the address mode.
8. Load 8-bit data into the TXREG register. This
will start the transmission.
FIGURE 22-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
DS41452B-page 240
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-4:
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Write to TXREG
Word 2
Start bit
Word 1
BRG Output
(Shift Clock)
TX/CK
pin
Start bit
Word 2
bit 0
bit 1
bit 7/8
bit 0
Stop bit
Word 2
1 TCY
Word 1
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
1 TCY
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
SCKP
INTE
TXIE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
SPEN
SSPIE
SSPIF
ADDEN
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
RCIF
TXIF
83
RCSTA
SPBRGL
SPBRGH
TRISC
SREN
CREN
FERR
OERR
RX9D
247
249*
249*
123
239*
246
BRG<7:0>
BRG<15:8>
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TRISC7
TXREG
TXSTA
EUSART Transmit Data Register
CSRC TX9 TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 241
PIC16(L)F1516/7/8/9
22.1.2
EUSART ASYNCHRONOUS
RECEIVER
22.1.2.2
Receiving Data
The receiver data recovery circuit initiates character
reception on the falling edge of the first bit. The first bit,
also known as the Start bit, is always a zero. The data
recovery circuit counts one-half bit time to the center of
the Start bit and verifies that the bit is still a zero. If it is
not a zero then the data recovery circuit aborts
character reception, without generating an error, and
resumes looking for the falling edge of the Start bit. If
the Start bit zero verification succeeds then the data
recovery circuit counts a full bit time to the center of the
next bit. The bit is then sampled by a majority detect
circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.
This repeats until all data bits have been sampled and
shifted into the RSR. One final bit time is measured and
the level sampled. This is the Stop bit, which is always
a ‘1’. If the data recovery circuit samples a ‘0’ in the
Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this
character. See Section 22.1.2.4 “Receive Framing
Error” for more information on framing errors.
The Asynchronous mode is typically used in RS-232
systems. The receiver block diagram is shown in
Figure 22-2. The data is received on the RX/DT pin and
drives the data recovery block. The data recovery block
is actually a high-speed shifter operating at 16 times
the baud rate, whereas the serial Receive Shift
Register (RSR) operates at the bit rate. When all 8 or 9
bits of the character have been shifted in, they are
immediately transferred to
a
two character
First-In-First-Out (FIFO) memory. The FIFO buffering
allows reception of two complete characters and the
start of a third character before software must start
servicing the EUSART receiver. The FIFO and RSR
registers are not directly accessible by software.
Access to the received data is via the RCREG register.
22.1.2.1
Enabling the Receiver
The EUSART receiver is enabled for asynchronous
operation by configuring the following three control bits:
Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
to the EUSART receive FIFO and the RCIF interrupt
flag bit of the PIR1 register is set. The top character in
the FIFO is transferred out of the FIFO by reading the
RCREG register.
• CREN = 1
• SYNC = 0
• SPEN = 1
All other EUSART control bits are assumed to be in
their default state.
Setting the CREN bit of the RCSTA register enables the
receiver circuitry of the EUSART. Clearing the SYNC bit
of the TXSTA register configures the EUSART for
asynchronous operation. Setting the SPEN bit of the
RCSTA register enables the EUSART. The programmer
must set the corresponding TRIS bit to configure the
RX/DT I/O pin as an input.
Note:
If the receive FIFO is overrun, no additional
characters will be received until the overrun
condition is cleared. See Section 22.1.2.5
“Receive Overrun Error” for more
information on overrun errors.
22.1.2.3
Receive Interrupts
The RCIF interrupt flag bit of the PIR1 register is set
whenever the EUSART receiver is enabled and there is
an unread character in the receive FIFO. The RCIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
Note 1: If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
RCIF interrupts are enabled by setting all of the
following bits:
• RCIE Interrupt Enable bit of the PIE1 register
• PEIE Peripheral Interrupt Enable bit of the
INTCON register
• GIE Global Interrupt Enable bit of the INTCON
register
The RCIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
DS41452B-page 242
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.1.2.4
Receive Framing Error
22.1.2.7
Address Detection
Each character in the receive FIFO buffer has a
corresponding framing error Status bit. A framing error
indicates that a Stop bit was not seen at the expected
time. The framing error status is accessed via the
FERR bit of the RCSTA register. The FERR bit
represents the status of the top unread character in the
receive FIFO. Therefore, the FERR bit must be read
before reading the RCREG.
A special Address Detection mode is available for use
when multiple receivers share the same transmission
line, such as in RS-485 systems. Address detection is
enabled by setting the ADDEN bit of the RCSTA
register.
Address detection requires 9-bit character reception.
When address detection is enabled, only characters
with the ninth data bit set will be transferred to the
receive FIFO buffer, thereby setting the RCIF interrupt
bit. All other characters will be ignored.
The FERR bit is read-only and only applies to the top
unread character in the receive FIFO. A framing error
(FERR = 1) does not preclude reception of additional
characters. It is not necessary to clear the FERR bit.
Reading the next character from the FIFO buffer will
advance the FIFO to the next character and the next
corresponding framing error.
Upon receiving an address character, user software
determines if the address matches its own. Upon
address match, user software must disable address
detection by clearing the ADDEN bit before the next
Stop bit occurs. When user software detects the end of
the message, determined by the message protocol
used, software places the receiver back into the
Address Detection mode by setting the ADDEN bit.
The FERR bit can be forced clear by clearing the SPEN
bit of the RCSTA register which resets the EUSART.
Clearing the CREN bit of the RCSTA register does not
affect the FERR bit. A framing error by itself does not
generate an interrupt.
Note:
If all receive characters in the receive
FIFO have framing errors, repeated reads
of the RCREG will not clear the FERR bit.
22.1.2.5
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before the FIFO is accessed. When
this happens the OERR bit of the RCSTA register is set.
The characters already in the FIFO buffer can be read
but no additional characters will be received until the
error is cleared. The error must be cleared by either
clearing the CREN bit of the RCSTA register or by
resetting the EUSART by clearing the SPEN bit of the
RCSTA register.
22.1.2.6
Receiving 9-bit Characters
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9 bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth and Most Significant data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 243
PIC16(L)F1516/7/8/9
22.1.2.8
Asynchronous Reception Set-up:
22.1.2.9
9-bit Address Detection Mode Set-up
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
This mode would typically be used in RS-485 systems.
To set up an Asynchronous Reception with Address
Detect Enable:
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
2. Clear the ANSEL bit for the RX pin (if applicable).
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
3. Enable the serial port by setting the SPEN bit.
The SYNC bit must be clear for asynchronous
operation.
5. If 9-bit reception is desired, set the RX9 bit.
6. Enable reception by setting the CREN bit.
4. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
7. The RCIF interrupt flag bit will be set when a
character is transferred from the RSR to the
receive buffer. An interrupt will be generated if
the RCIE interrupt enable bit was also set.
5. Enable 9-bit reception by setting the RX9 bit.
6. Enable address detection by setting the ADDEN
bit.
8. Read the RCSTA register to get the error flags
and, if 9-bit data reception is enabled, the ninth
data bit.
7. Enable reception by setting the CREN bit.
8. The RCIF interrupt flag bit will be set when a
character with the ninth bit set is transferred
from the RSR to the receive buffer. An interrupt
will be generated if the RCIE interrupt enable bit
was also set.
9. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register.
10. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
9. Read the RCSTA register to get the error flags.
The ninth data bit will always be set.
10. Get the received 8 Least Significant data bits
from the receive buffer by reading the RCREG
register. Software determines if this is the
device’s address.
11. If an overrun occurred, clear the OERR flag by
clearing the CREN receiver enable bit.
12. If the device has been addressed, clear the
ADDEN bit to allow all received data into the
receive buffer and generate interrupts.
FIGURE 22-5:
ASYNCHRONOUS RECEPTION
Start
bit
Start
bit
Start
bit
RX/DT pin
bit 7/8
bit 7/8
bit 0 bit 1
Stop
bit
Stop
bit
Stop
bit
bit 0
bit 7/8
Rcv Shift
Reg
Rcv Buffer Reg.
Word 2
RCREG
Word 1
RCREG
RCIDL
Read Rcv
Buffer Reg.
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS41452B-page 244
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
on Page
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
RCIF
83
RCREG
RCSTA
SPBRGL
SPBRGH
TRISC
EUSART Receive Data Register
SREN CREN ADDEN FERR
BRG<7:0>
BRG<15:8>
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
242*
247
249*
249*
123
246
SPEN
RX9
OERR
RX9D
TRISC7
CSRC
TXSTA
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Reception.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 245
PIC16(L)F1516/7/8/9
The method to adjust the value in the Baud Rate
Generator can be done automatically with the
Auto-Baud Detect feature (see Section 22.4.1
“Auto-Baud Detect”). There may not be fine enough
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
22.2 Clock Accuracy with
Asynchronous Operation
The factory calibrates the internal oscillator block out-
put (INTOSC). However, the INTOSC frequency may
drift as VDD or temperature changes, and this directly
affects the asynchronous baud rate. The baud rate
clock can be adjusted, but requires a reference clock
source of some kind.
22.3 EUSART Control Registers
REGISTER 22-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-/0
CSRC
R/W-0/0
TX9
R/W-0/0
TXEN(1)
R/W-0/0
SYNC
R/W-0/0
SENDB
R/W-0/0
BRGH
R-1/1
R/W-0/0
TX9D
TRMT
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (clock generated internally from BRG)
0= Slave mode (clock from external source)
bit 6
bit 5
bit 4
bit 3
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit(1)
1= Transmit enabled
0= Transmit disabled
SYNC: EUSART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1= Send Sync Break on next transmission (cleared by hardware upon completion)
0= Sync Break transmission completed
Synchronous mode:
Don’t care
bit 2
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
Note 1: SREN/CREN overrides TXEN in Sync mode.
DS41452B-page 246
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
REGISTER 22-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER(1)
R/W-0/0
SPEN
R/W-0/0
RX9
R/W-0/0
SREN
R/W-0/0
CREN
R/W-0/0
ADDEN
R-0/0
R-0/0
R-x/x
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (configures RX/DT and TX/CK pins as serial port pins)
0= Serial port disabled (held in Reset)
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode – Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode – Slave
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables receiver
0= Disables receiver
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADDEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1= Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set
0= Disables address detection, all bytes are received and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9 = 0):
Don’t care
bit 2
bit 1
bit 0
FERR: Framing Error bit
1= Framing error (can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (can be cleared by clearing bit CREN)
0= No overrun error
RX9D: Ninth bit of Received Data
This can be address/data bit or a parity bit and must be calculated by user firmware.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 247
PIC16(L)F1516/7/8/9
REGISTER 22-3: BAUDCON: BAUD RATE CONTROL REGISTER
R-0/0
R-1/1
U-0
—
R/W-0/0
SCKP
R/W-0/0
BRG16
U-0
—
R/W-0/0
WUE
R/W-0/0
ABDEN
ABDOVF
RCIDL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged
‘1’ = Bit is set
x = Bit is unknown
‘0’ = Bit is cleared
bit 7
bit 6
ABDOVF: Auto-Baud Detect Overflow bit
Asynchronous mode:
1= Auto-baud timer overflowed
0= Auto-baud timer did not overflow
Synchronous mode:
Don’t care
RCIDL: Receive Idle Flag bit
Asynchronous mode:
1= Receiver is Idle
0= Start bit has been received and the receiver is receiving
Synchronous mode:
Don’t care
bit 5
bit 4
Unimplemented: Read as ‘0’
SCKP: Synchronous Clock Polarity Select bit
Asynchronous mode:
1= Transmit inverted data to the TX/CK pin
0= Transmit non-inverted data to the TX/CK pin
Synchronous mode:
1= Data is clocked on rising edge of the clock
0= Data is clocked on falling edge of the clock
bit 3
BRG16: 16-bit Baud Rate Generator bit
1= 16-bit Baud Rate Generator is used
0= 8-bit Baud Rate Generator is used
bit 2
bit 1
Unimplemented: Read as ‘0’
WUE: Wake-up Enable bit
Asynchronous mode:
1= Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE
will automatically clear after RCIF is set.
0= Receiver is operating normally
Synchronous mode:
Don’t care
bit 0
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1= Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
0= Auto-Baud Detect mode is disabled
Synchronous mode:
Don’t care
DS41452B-page 248
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
EXAMPLE 22-1:
CALCULATING BAUD
RATE ERROR
22.4 EUSART Baud Rate Generator
(BRG)
For a device with FOSC of 16 MHz, desired baud rate
of 9600, Asynchronous mode, 8-bit BRG:
The Baud Rate Generator (BRG) is an 8-bit or 16-bit
timer that is dedicated to the support of both the
asynchronous and synchronous EUSART operation.
By default, the BRG operates in 8-bit mode. Setting the
BRG16 bit of the BAUDCON register selects 16-bit
mode.
FOSC
Desired Baud Rate = -----------------------------------------------------------------------
64[SPBRGH:SPBRGL] + 1
Solving for SPBRGH:SPBRGL:
FOSC
---------------------------------------------
Desired Baud Rate
X = --------------------------------------------- – 1
64
The SPBRGH, SPBRGL register pair determines the
period of the free running baud rate timer. In
Asynchronous mode the multiplier of the baud rate
period is determined by both the BRGH bit of the TXSTA
register and the BRG16 bit of the BAUDCON register. In
Synchronous mode, the BRGH bit is ignored.
16000000
-----------------------
9600
= ----------------------- – 1
64
= 25.042 = 25
Table 22-3 contains the formulas for determining the
baud rate. Example 22-1 provides a sample calculation
for determining the baud rate and baud rate error.
16000000
Calculated Baud Rate = --------------------------
6425 + 1
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 22-3. It may be
advantageous to use the high baud rate (BRGH = 1),
or the 16-bit BRG (BRG16 = 1) to reduce the baud rate
error. The 16-bit BRG mode is used to achieve slow
baud rates for fast oscillator frequencies.
= 9615
Calc. Baud Rate – Desired Baud Rate
Error = --------------------------------------------------------------------------------------------
Desired Baud Rate
9615 – 9600
= ---------------------------------- = 0 . 1 6 %
9600
Writing a new value to the SPBRGH, SPBRGL register
pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow
before outputting the new baud rate.
If the system clock is changed during an active receive
operation, a receive error or data loss may result. To
avoid this problem, check the status of the RCIDL bit to
make sure that the receive operation is Idle before
changing the system clock.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 249
PIC16(L)F1516/7/8/9
TABLE 22-3: BAUD RATE FORMULAS
Configuration Bits
Baud Rate Formula
BRG/EUSART Mode
SYNC
BRG16
BRGH
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
x
x
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[64 (n+1)]
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
Legend:
x= Don’t care, n = value of SPBRGH, SPBRGL register pair.
TABLE 22-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
RCSTA
ABDOVF RCIDL
—
SCKP
CREN
BRG16
ADDEN
—
WUE
ABDEN
RX9D
248
247
SPEN
CSRC
RX9
SREN
FERR
OERR
SPBRGL
SPBRGH
TXSTA
BRG<7:0>
BRG<15:8>
SYNC SENDB
249*
249*
246
TX9
TXEN
BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
Page provides register information.
*
DS41452B-page 250
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 20.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
—
—
—
255
129
32
—
—
—
239
119
29
—
—
—
207
103
25
—
—
—
143
71
17
16
8
1221
2404
9470
10417
19.53k
1.73
0.16
-1.36
0.00
1.73
1200
2400
9600
10286
19.20k
0.00
0.00
0.00
-1.26
0.00
0.00
—
1202
2404
9615
10417
19.23k
0.16
0.16
0.16
0.00
0.16
—
1200
2400
9600
10165
19.20k
0.00
0.00
0.00
-2.42
0.00
0.00
—
2400
9600
10417
19.2k
57.6k
115.2k
29
27
23
15
14
12
2
—
—
—
—
—
—
57.60k
—
7
—
—
—
—
57.60k
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
0.00
0.00
0.00
0.00
—
300
1200
—
1202
2404
9615
10417
—
—
0.16
0.16
0.16
0.00
—
—
103
51
12
11
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
300
1200
2400
9600
—
191
47
23
5
300
1202
—
0.16
0.16
—
51
12
—
—
—
—
—
—
2400
9600
—
—
10417
19.2k
57.6k
115.2k
10417
—
0.00
—
—
2
—
—
—
—
—
—
19.20k
0.00
0.00
—
—
—
—
—
—
—
—
0
—
—
57.60k
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 20.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
1200
2400
9600
10417
19.2k
57.6k
—
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
9615
10417
19.23k
56.82k
0.16
0.00
0.16
-1.36
129
119
64
9600
10378
19.20k
57.60k
115.2k
0.00
-0.37
0.00
0.00
0.00
119
110
59
19
9
9615
10417
19.23k
58.82k
111.1k
0.16
0.00
0.16
2.12
-3.55
103
95
51
16
8
9600
0.00
0.53
0.00
0.00
0.00
10473
19.20k
57.60k
115.2k
21
115.2k 113.64k -1.36
10
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 251
PIC16(L)F1516/7/8/9
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 8.000 MHz
FOSC = 4.000 MHz
FOSC = 3.6864 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
—
—
—
—
—
—
300
1200
—
1202
2404
9615
10417
19.23k
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
0.16
0.16
0.16
0.00
0.16
—
1200
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2400
2404
9615
10417
19231
55556
—
0.16
0.16
0.00
0.16
-3.55
—
207
51
47
25
8
2400
9600
9600
10417
19.2k
57.6k
115.2k
23
10473
19.2k
57.60k
115.2k
10417
—
0.00
—
12
—
—
—
—
—
—
—
—
—
—
1
—
—
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 20.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
value
(decimal)
Error
Error
(decimal)
(decimal)
300
1200
2400
9600
10417
19.2k
57.6k
300.0
1200
-0.01
-0.03
-0.03
0.16
0.00
0.16
-1.36
4166
1041
520
129
119
64
300.0
1200
0.00
0.00
0.00
0.00
-0.37
0.00
0.00
0.00
3839
959
479
119
110
59
300.03
1200.5
2398
0.01
0.04
-0.08
0.16
0.00
0.16
2.12
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
2303
575
287
71
2399
2400
2400
9615
9600
9615
9600
10417
19.23k
56.818
10378
19.20k
57.60k
115.2k
10417
19.23k
58.82k
10473
19.20k
57.60k
115.2k
65
51
35
21
19
16
11
115.2k 113.636 -1.36
10
9
111.11k -3.55
8
5
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
value
SPBRG
value
SPBRG
value
SPBRG
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
Error
Actual
Rate
%
value
(decimal)
Error
(decimal)
(decimal)
(decimal)
300
1200
299.9
1199
-0.02
-0.08
0.16
0.16
0.00
0.16
-3.55
—
1666
416
207
51
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
767
191
95
23
21
11
3
300.5
1202
2404
—
0.16
0.16
0.16
—
207
51
25
—
5
2400
2404
9615
10417
19.23k
55556
—
2400
9600
9600
10417
19.2k
57.6k
115.2k
47
23
10473
19.20k
57.60k
115.2k
10417
—
0.00
—
25
12
—
—
—
8
—
—
—
—
—
—
—
1
—
—
DS41452B-page 252
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 22-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 18.432 MHz FOSC = 16.000 MHz
FOSC = 20.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
-0.01
0.02
-0.03
0.00
0.16
-0.22
0.94
16665
4166
2082
520
479
259
86
300.0
1200
0.00
0.00
0.00
0.00
0.08
0.00
0.00
0.00
15359
3839
1919
479
441
239
79
300.0
1200.1
2399.5
9592
0.00
0.01
-0.02
-0.08
0.00
0.16
0.64
13332
3332
1666
416
383
207
68
300.0
1200
0.00
0.00
0.00
0.00
0.16
0.00
0.00
0.00
9215
2303
1151
287
264
143
47
2400
2400
2400
2400
9600
9597
9600
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.47k
116.3k
10425
19.20k
57.60k
115.2k
10417
19.23k
57.97k
10433
19.20k
57.60k
115.2k
42
39
114.29k -0.79
34
23
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
SPBRG
SPBRG
SPBRG
SPBRG
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
Actual
Rate
%
value
(decimal)
value
(decimal)
value
(decimal)
value
(decimal)
Error
Error
Error
Error
300
1200
300.0
1200
0.00
-0.02
0.04
0.16
0
6666
1666
832
207
191
103
34
300.0
1200
0.01
0.04
0.08
0.16
0.00
0.16
2.12
-3.55
3332
832
416
103
95
300.0
1200
0.00
0.00
0.00
0.00
0.53
0.00
0.00
0.00
3071
767
383
95
300.1
1202
2404
9615
10417
19.23k
—
0.04
0.16
0.16
0.16
0.00
0.16
—
832
207
103
25
2400
2401
2398
2400
9600
9615
9615
9600
10417
19.2k
57.6k
115.2k
10417
19.23k
57.14k
117.6k
10417
19.23k
58.82k
111.1k
10473
19.20k
57.60k
115.2k
87
23
0.16
-0.79
2.12
51
47
12
16
15
—
16
8
7
—
—
—
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 253
PIC16(L)F1516/7/8/9
and SPBRGL registers are clocked at 1/8th the BRG
base clock rate. The resulting byte measurement is the
average bit time when clocked at full speed.
22.4.1
AUTO-BAUD DETECT
The EUSART module supports automatic detection
and calibration of the baud rate.
Note 1: If the WUE bit is set with the ABDEN bit,
auto-baud detection will occur on the byte
following the Break character (see
Section 22.4.3 “Auto-Wake-up on
Break”).
In the Auto-Baud Detect (ABD) mode, the clock to the
BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG.
The Baud Rate Generator is used to time the period of
a received 55h (ASCII “U”) which is the Sync character
for the LIN bus. The unique feature of this character is
that it has five rising edges including the Stop bit edge.
2: It is up to the user to determine that the
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible.
Setting the ABDEN bit of the BAUDCON register starts
the auto-baud calibration sequence (Figure 22-6).
While the ABD sequence takes place, the EUSART
state machine is held in Idle. On the first rising edge of
the receive line, after the Start bit, the SPBRG begins
counting up using the BRG counter clock as shown in
Table 22-6. The fifth rising edge will occur on the RX pin
at the end of the eighth bit period. At that time, an
accumulated value totaling the proper BRG period is
left in the SPBRGH, SPBRGL register pair, the ABDEN
bit is automatically cleared and the RCIF interrupt flag
is set. The value in the RCREG needs to be read to
clear the RCIF interrupt. RCREG content should be
discarded. When calibrating for modes that do not use
the SPBRGH register the user can verify that the
SPBRGL register did not overflow by checking for 00h
in the SPBRGH register.
3: During the auto-baud process, the
auto-baud counter starts counting at 1.
Upon completion of the auto-baud
sequence, to achieve maximum accuracy,
subtract 1 from the SPBRGH:SPBRGL
register pair.
TABLE 22-6:
BRG COUNTER CLOCK RATES
BRG Base
Clock
BRG ABD
Clock
BRG16 BRGH
0
0
0
1
FOSC/64
FOSC/16
FOSC/512
FOSC/128
1
1
0
1
FOSC/16
FOSC/4
FOSC/128
FOSC/32
The BRG auto-baud clock is determined by the BRG16
and BRGH bits as shown in Table 22-6. During ABD,
both the SPBRGH and SPBRGL registers are used as
a 16-bit counter, independent of the BRG16 bit setting.
While calibrating the baud rate period, the SPBRGH
Note:
During the ABD sequence, SPBRGL and
SPBRGH registers are both used as a 16-bit
counter, independent of BRG16 setting.
FIGURE 22-6:
AUTOMATIC BAUD RATE CALIBRATION
XXXXh
0000h
001Ch
BRG Value
Edge #1
bit 1
Edge #2
bit 3
Edge #3
bit 5
Edge #4
bit 7
bit 6
Edge #5
Stop bit
RX pin
Start
bit 0
bit 2
bit 4
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
XXh
XXh
1Ch
00h
SPBRGL
SPBRGH
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS41452B-page 254
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.4.2
AUTO-BAUD OVERFLOW
22.4.3.1
Special Considerations
During the course of automatic baud detection, the
ABDOVF bit of the BAUDCON register will be set if the
baud rate counter overflows before the fifth rising edge
is detected on the RX pin. The ABDOVF bit indicates
that the counter has exceeded the maximum count that
can fit in the 16 bits of the SPBRGH:SPBRGL register
pair. After the ABDOVF has been set, the counter con-
tinues to count until the fifth rising edge is detected on
the RX pin. Upon detecting the fifth RX edge, the hard-
ware will set the RCIF interrupt flag and clear the
ABDEN bit of the BAUDCON register. The RCIF flag
can be subsequently cleared by reading the RCREG
register. The ABDOVF flag of the BAUDCON register
can be cleared by software directly.
Break Character
To avoid character errors or character fragments during
a wake-up event, the wake-up character must be all
zeros.
When the wake-up is enabled the function works
independent of the low time on the data stream. If the
WUE bit is set and a valid non-zero character is
received, the low time from the Start bit to the first rising
edge will be interpreted as the wake-up event. The
remaining bits in the character will be received as a
fragmented character and subsequent characters can
result in framing or overrun errors.
Therefore, the initial character in the transmission must
be all ‘0’s. This must be 10 or more bit times, 13-bit
times recommended for LIN bus, or any number of bit
times for standard RS-232 devices.
To terminate the auto-baud process before the RCIF
flag is set, clear the ABDEN bit then clear the ABDOVF
bit of the BAUDCON register. The ABDOVF bit will
remain set if the ABDEN bit is not cleared first.
Oscillator Start-up Time
Oscillator start-up time must be considered, especially
in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS mode). The Sync Break (or
wake-up signal) character must be of sufficient length,
and be followed by a sufficient interval, to allow enough
time for the selected oscillator to start and provide
proper initialization of the EUSART.
22.4.3
AUTO-WAKE-UP ON BREAK
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper character reception cannot be
performed. The Auto-Wake-up feature allows the
controller to wake-up due to activity on the RX/DT line.
This feature is available only in Asynchronous mode.
WUE Bit
The Auto-Wake-up feature is enabled by setting the
WUE bit of the BAUDCON register. Once set, the normal
receive sequence on RX/DT is disabled, and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the
RX/DT line. (This coincides with the start of a Sync Break
or a wake-up signal character for the LIN protocol.)
The wake-up event causes a receive interrupt by
setting the RCIF bit. The WUE bit is cleared in
hardware by a rising edge on RX/DT. The interrupt
condition is then cleared in software by reading the
RCREG register and discarding its contents.
To ensure that no actual data is lost, check the RCIDL
bit to verify that a receive operation is not in process
before setting the WUE bit. If a receive operation is not
occurring, the WUE bit may then be set just prior to
entering the Sleep mode.
The EUSART module generates an RCIF interrupt
coincident with the wake-up event. The interrupt is
generated synchronously to the Q clocks in normal CPU
operating modes (Figure 22-7), and asynchronously if
the device is in Sleep mode (Figure 22-8). The interrupt
condition is cleared by reading the RCREG register.
The WUE bit is automatically cleared by the low-to-high
transition on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this
point, the EUSART module is in Idle mode waiting to
receive the next character.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 255
PIC16(L)F1516/7/8/9
FIGURE 22-7:
AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4
OSC1
Auto Cleared
Bit set by user
WUE bit
RX/DT Line
RCIF
Cleared due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 22-8:
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q4
Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3
Q1
Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
Auto Cleared
OSC1
Bit Set by User
WUE bit
RX/DT Line
Note 1
RCIF
Cleared due to User Read of RCREG
Sleep Command Executed
Sleep Ends
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
DS41452B-page 256
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
22.4.4
BREAK CHARACTER SEQUENCE
22.4.5
RECEIVING A BREAK CHARACTER
The EUSART module has the capability of sending the
special Break character sequences that are required by
the LIN bus standard. A Break character consists of a
Start bit, followed by 12 ‘0’ bits and a Stop bit.
The Enhanced EUSART module can receive a Break
character in two ways.
The first method to detect a Break character uses the
FERR bit of the RCSTA register and the Received data
as indicated by RCREG. The Baud Rate Generator is
assumed to have been initialized to the expected baud
rate.
To send a Break character, set the SENDB and TXEN
bits of the TXSTA register. The Break character trans-
mission is then initiated by a write to the TXREG. The
value of data written to TXREG will be ignored and all
‘0’s will be transmitted.
A Break character has been received when;
• RCIF bit is set
• FERR bit is set
• RCREG = 00h
The SENDB bit is automatically reset by hardware after
the corresponding Stop bit is sent. This allows the user
to preload the transmit FIFO with the next transmit byte
following the Break character (typically, the Sync
character in the LIN specification).
The second method uses the Auto-Wake-up feature
described in Section 22.4.3 “Auto-Wake-up on
Break”. By enabling this feature, the EUSART will
sample the next two transitions on RX/DT, cause an
RCIF interrupt, and receive the next data byte followed
by another interrupt.
The TRMT bit of the TXSTA register indicates when the
transmit operation is active or Idle, just as it does during
normal transmission. See Figure 22-9 for the timing of
the Break character sequence.
Note that following a Break character, the user will
typically want to enable the Auto-Baud Detect feature.
For both methods, the user can set the ABDEN bit of
the BAUDCON register before placing the EUSART in
Sleep mode.
22.4.4.1
Break and Sync Transmit Sequence
The following sequence will start a message frame
header made up of a Break, followed by an auto-baud
Sync byte. This sequence is typical of a LIN bus
master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the
Break sequence.
3. Load the TXREG with a dummy character to
initiate transmission (the value is ignored).
4. Write ‘55h’ to TXREG to load the Sync character
into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is
reset by hardware and the Sync character is
then transmitted.
When the TXREG becomes empty, as indicated by the
TXIF, the next data byte can be written to TXREG.
FIGURE 22-9:
SEND BREAK CHARACTER SEQUENCE
Write to TXREG
Dummy Write
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here
Auto Cleared
SENDB
(send Break
control bit)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 257
PIC16(L)F1516/7/8/9
Clearing the SCKP bit sets the Idle state as low. When
the SCKP bit is cleared, the data changes on the rising
edge of each clock.
22.5 EUSART Synchronous Mode
Synchronous serial communications are typically used
in systems with a single master and one or more
slaves. The master device contains the necessary cir-
cuitry for baud rate generation and supplies the clock
for all devices in the system. Slave devices can take
advantage of the master clock by eliminating the inter-
nal clock generation circuitry.
22.5.1.3
Synchronous Master Transmission
Data is transferred out of the device on the RX/DT pin.
The RX/DT and TX/CK pin output drivers are automat-
ically enabled when the EUSART is configured for syn-
chronous master transmit operation.
There are two signal lines in Synchronous mode: a bidi-
rectional data line and a clock line. Slaves use the
external clock supplied by the master to shift the serial
data into and out of their respective receive and trans-
mit shift registers. Since the data line is bidirectional,
synchronous operation is half-duplex only. Half-duplex
refers to the fact that master and slave devices can
receive and transmit data but not both simultaneously.
The EUSART can operate as either a master or slave
device.
A transmission is initiated by writing a character to the
TXREG register. If the TSR still contains all or part of a
previous character the new character data is held in the
TXREG until the last bit of the previous character has
been transmitted. If this is the first character, or the pre-
vious character has been completely flushed from the
TSR, the data in the TXREG is immediately transferred
to the TSR. The transmission of the character com-
mences immediately following the transfer of the data
to the TSR from the TXREG.
Start and Stop bits are not used in synchronous trans-
missions.
Each data bit changes on the leading edge of the mas-
ter clock and remains valid until the subsequent leading
clock edge.
22.5.1
SYNCHRONOUS MASTER MODE
Note:
The TSR register is not mapped in data
memory, so it is not available to the user.
The following bits are used to configure the EUSART
for Synchronous Master operation:
• SYNC = 1
22.5.1.4
Synchronous Master Transmission
Set-up:
• CSRC = 1
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
1. Initialize the SPBRGH, SPBRGL register pair
and the BRGH and BRG16 bits to achieve the
desired baud rate (see Section 22.4 “EUSART
Baud Rate Generator (BRG)”).
Setting the SYNC bit of the TXSTA register configures
the device for synchronous operation. Setting the CSRC
bit of the TXSTA register configures the device as a
master. Clearing the SREN and CREN bits of the RCSTA
register ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Disable Receive mode by clearing bits SREN
and CREN.
4. Enable Transmit mode by setting the TXEN bit.
5. If 9-bit transmission is desired, set the TX9 bit.
6. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
22.5.1.1
Master Clock
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device config-
ured as a master transmits the clock on the TX/CK line.
The TX/CK pin output driver is automatically enabled
when the EUSART is configured for synchronous
transmit or receive operation. Serial data bits change
on the leading edge to ensure they are valid at the trail-
ing edge of each clock. One clock cycle is generated
for each data bit. Only as many clock cycles are gener-
ated as there are data bits.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in the TX9D bit.
8. Start transmission by loading data to the TXREG
register.
22.5.1.2
Clock Polarity
A clock polarity option is provided for Microwire
compatibility. Clock polarity is selected with the SCKP
bit of the BAUDCON register. Setting the SCKP bit sets
the clock Idle state as high. When the SCKP bit is set,
the data changes on the falling edge of each clock.
DS41452B-page 258
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-10:
SYNCHRONOUS TRANSMISSION
RX/DT
pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
‘1’
‘1’
TXEN bit
Note:
Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words.
FIGURE 22-11:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RX/DT pin
bit 0
bit 2
bit 1
bit 6
bit 7
TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 22-7: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
SCKP
INTE
TXIE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
CCP1IE
CCP1IF
FERR
TMR1GIE
TMR1GIF
SPEN
SSPIE
SSPIF
ADDEN
TMR2IE
TMR2IF
OERR
TMR1IE
TMR1IF
RX9D
81
PIR1
RCIF
TXIF
83
RCSTA
SPBRGL
SPBRGH
TRISC
SREN
CREN
247
249*
249*
123
239*
246
BRG<7:0>
BRG<15:8>
TRISC4 TRISC3
TRISC7
CSRC
TRISC6
TX9
TRISC5
TRISC2
TRISC1
TRMT
TRISC0
TX9D
TXREG
TXSTA
EUSART Transmit Data Register
TXEN SYNC SENDB BRGH
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Transmission.
*
Page provides register information.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 259
PIC16(L)F1516/7/8/9
buffer can be read, however, no additional characters
will be received until the error is cleared. The OERR bit
can only be cleared by clearing the overrun condition.
If the overrun error occurred when the SREN bit is set
and CREN is clear then the error is cleared by reading
RCREG. If the overrun occurred when the CREN bit is
set then the error condition is cleared by either clearing
the CREN bit of the RCSTA register or by clearing the
SPEN bit which resets the EUSART.
22.5.1.5
Synchronous Master Reception
Data is received at the RX/DT pin. The RX/DT pin
output driver is automatically disabled when the
EUSART is configured for synchronous master receive
operation.
In Synchronous mode, reception is enabled by setting
either the Single Receive Enable bit (SREN of the
RCSTA register) or the Continuous Receive Enable bit
(CREN of the RCSTA register).
22.5.1.8
Receiving 9-bit Characters
When SREN is set and CREN is clear, only as many
clock cycles are generated as there are data bits in a
single character. The SREN bit is automatically cleared
at the completion of one character. When CREN is set,
clocks are continuously generated until CREN is
cleared. If CREN is cleared in the middle of a character
the CK clock stops immediately and the partial charac-
ter is discarded. If SREN and CREN are both set, then
SREN is cleared at the completion of the first character
and CREN takes precedence.
The EUSART supports 9-bit character reception. When
the RX9 bit of the RCSTA register is set the EUSART
will shift 9-bits into the RSR for each character
received. The RX9D bit of the RCSTA register is the
ninth, and Most Significant, data bit of the top unread
character in the receive FIFO. When reading 9-bit data
from the receive FIFO buffer, the RX9D data bit must
be read before reading the 8 Least Significant bits from
the RCREG.
To initiate reception, set either SREN or CREN. Data is
sampled at the RX/DT pin on the trailing edge of the
TX/CK clock pin and is shifted into the Receive Shift
Register (RSR). When a complete character is
received into the RSR, the RCIF bit is set and the char-
acter is automatically transferred to the two character
receive FIFO. The Least Significant eight bits of the top
character in the receive FIFO are available in RCREG.
The RCIF bit remains set as long as there are unread
characters in the receive FIFO.
22.5.1.9
Synchronous Master Reception
Set-up:
1. Initialize the SPBRGH, SPBRGL register pair for
the appropriate baud rate. Set or clear the
BRGH and BRG16 bits, as required, to achieve
the desired baud rate.
2. Clear the ANSEL bit for the RX pin (if applicable).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
Note:
If the RX/DT function is on an analog pin,
the corresponding ANSEL bit must be
cleared for the receiver to function.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
22.5.1.6
Slave Clock
6. If 9-bit reception is desired, set bit RX9.
Synchronous data transfers use a separate clock line,
which is synchronous with the data. A device configured
as a slave receives the clock on the TX/CK line. The
TX/CK pin output driver is automatically disabled when
the device is configured for synchronous slave transmit
or receive operation. Serial data bits change on the
leading edge to ensure they are valid at the trailing edge
of each clock. One data bit is transferred for each clock
cycle. Only as many clock cycles should be received as
there are data bits.
7. Start reception by setting the SREN bit or for
continuous reception, set the CREN bit.
8. Interrupt flag bit RCIF will be set when reception
of a character is complete. An interrupt will be
generated if the enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
10. Read the 8-bit received data by reading the
RCREG register.
Note:
If the device is configured as a slave and
the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be
cleared.
11. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
22.5.1.7
Receive Overrun Error
The receive FIFO buffer can hold two characters. An
overrun error will be generated if a third character, in its
entirety, is received before RCREG is read to access
the FIFO. When this happens the OERR bit of the
RCSTA register is set. Previous data in the FIFO will
not be overwritten. The two characters in the FIFO
DS41452B-page 260
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 22-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RX/DT
pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK pin
(SCKP = 0)
TX/CK pin
(SCKP = 1)
Write to
bit SREN
SREN bit
‘0’
‘0’
CREN bit
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.
TABLE 22-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
RCIF
83
RCREG
RCSTA
SPBRGL
SPBRGH
TRISC
EUSART Receive Data Register
SREN CREN ADDEN FERR
BRG<7:0>
BRG<15:8>
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
242*
247
249*
249*
123
246
SPEN
RX9
OERR
RX9D
TRISC7
CSRC
TXSTA
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 261
PIC16(L)F1516/7/8/9
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
22.5.2
SYNCHRONOUS SLAVE MODE
The following bits are used to configure the EUSART
for Synchronous slave operation:
1. The first character will immediately transfer to
the TSR register and transmit.
• SYNC = 1
2. The second word will remain in TXREG register.
3. The TXIF bit will not be set.
• CSRC = 0
• SREN = 0(for transmit); SREN = 1(for receive)
• CREN = 0(for transmit); CREN = 1(for receive)
• SPEN = 1
4. After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
5. If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
22.5.2.2
Synchronous Slave Transmission
Set-up:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
22.5.2.1
EUSART Synchronous Slave
Transmit
2. Clear the ANSEL bit for the CK pin (if applicable).
3. Clear the CREN and SREN bits.
The operation of the Synchronous Master and Slave
modes are identical (see Section 22.5.1.3
“Synchronous Master Transmission”), except in the
4. If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
case of the Sleep mode.
5. If 9-bit transmission is desired, set the TX9 bit.
6. Enable transmission by setting the TXEN bit.
7. If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
8. Start transmission by writing the Least
Significant 8 bits to the TXREG register.
TABLE 22-9: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
RX9
—
SCKP
INTE
TXIE
BRG16
IOCIE
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
SSPIE
SSPIF
ADDEN
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
RCIF
TXIF
83
SREN
CREN
FERR
OERR
RX9D
RCSTA
TRISC
TXREG
TXSTA
SPEN
247
123
239*
246
TRISC7
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
EUSART Transmit Data Register
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
Page provides register information.
*
DS41452B-page 262
Preliminary
2011 Microchip Technology Inc.
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22.5.2.3
EUSART Synchronous Slave
Reception
22.5.2.4
Synchronous Slave Reception
Set-up:
The operation of the Synchronous Master and Slave
modes is identical (Section 22.5.1.5 “Synchronous
Master Reception”), with the following exceptions:
1. Set the SYNC and SPEN bits and clear the
CSRC bit.
2. Clear the ANSEL bit for both the CK and DT pins
(if applicable).
• Sleep
3. If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• CREN bit is always set, therefore the receiver is
never Idle
• SREN bit, which is a “don’t care” in Slave mode
4. If 9-bit reception is desired, set the RX9 bit.
5. Set the CREN bit to enable reception.
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
6. The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
7. If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
8. Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
9. If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TABLE 22-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
RECEPTION
Register
on Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BAUDCON
INTCON
PIE1
ABDOVF
GIE
RCIDL
PEIE
ADIE
ADIF
—
SCKP
INTE
TXIE
TXIF
BRG16
IOCIE
SSPIE
SSPIF
—
WUE
INTF
ABDEN
IOCIF
248
80
TMR0IE
RCIE
TMR0IF
TMR1GIE
TMR1GIF
CCP1IE TMR2IE TMR1IE
CCP1IF TMR2IF TMR1IF
81
PIR1
RCIF
83
RCREG
RCSTA
TRISC
TXSTA
EUSART Receive Data Register
SREN CREN ADDEN FERR
242*
247
123
246
RX9
OERR
RX9D
SPEN
TRISC7
CSRC
TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.
Page provides register information.
*
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 263
PIC16(L)F1516/7/8/9
22.6.2
SYNCHRONOUS TRANSMIT
DURING SLEEP
22.6 EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the
Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the neces-
sary signals to run the Transmit or Receive Shift regis-
ters during Sleep.
To transmit during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Transmission
(see Section 22.5.2.2 “Synchronous Slave
Transmission Set-up:”).
Synchronous Slave mode uses an externally generated
clock to run the Transmit and Receive Shift registers.
•
The TXIF interrupt flag must be cleared by writing
the output data to the TXREG, thereby filling the
TSR and transmit buffer.
22.6.1
SYNCHRONOUS RECEIVE DURING
SLEEP
• If interrupts are desired, set the TXIE bit of the
PIE1 register and the PEIE bit of the INTCON reg-
ister.
To receive during Sleep, all the following conditions
must be met before entering Sleep mode:
• RCSTA and TXSTA Control registers must be
configured for Synchronous Slave Reception (see
Section 22.5.2.4 “Synchronous Slave
Reception Set-up:”).
• Interrupt enable bits TXIE of the PIE1 register and
PEIE of the INTCON register must set.
Upon entering Sleep mode, the device will be ready to
accept clocks on TX/CK pin and transmit data on the
RX/DT pin. When the data word in the TSR has been
completely clocked out by the external device, the
pending byte in the TXREG will transfer to the TSR and
the TXIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXREG is available to
accept another character for transmission, which will
clear the TXIF flag.
• If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
• The RCIF interrupt flag must be cleared by read-
ing RCREG to unload any pending characters in
the receive buffer.
Upon entering Sleep mode, the device will be ready to
accept data and clocks on the RX/DT and TX/CK pins,
respectively. When the data word has been completely
clocked in by the external device, the RCIF interrupt
flag bit of the PIR1 register will be set. Thereby, waking
the processor from Sleep.
Upon waking from Sleep, the instruction following the
SLEEP instruction will be executed. If the Global
Interrupt Enable (GIE) bit is also set then the Interrupt
Service Routine at address 0004h will be called.
Upon waking from Sleep, the instruction following the
SLEEPinstruction will be executed. If the Global Inter-
rupt Enable (GIE) bit of the INTCON register is also set,
then the Interrupt Service Routine at address 004h will
be called.
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23.0 IN-CIRCUIT SERIAL
PROGRAMMING™ (ICSP™)
ICSP™ programming allows customers to manufacture
circuit boards with unprogrammed devices. Programming
can be done after the assembly process allowing the
device to be programmed with the most recent firmware
or a custom firmware. Five pins are needed for ICSP™
programming:
• ICSPCLK
• ICSPDAT
• MCLR/VPP
• VDD
• VSS
In Program/Verify mode the program memory, user IDs
and the Configuration Words are programmed through
serial communications. The ICSPDAT pin is a bidirec-
tional I/O used for transferring the serial data and the
ICSPCLK pin is the clock input. For more information on
ICSP™ refer to the “PIC16(L)F151X/152X Memory
Programming Specification”, (DS41442).
23.1 High-Voltage Programming Entry
Mode
The device is placed into High-Voltage Programming
Entry mode by holding the ICSPCLK and ICSPDAT
pins low then raising the voltage on MCLR/VPP to VIHH.
Some programmers produce VPP greater than VIHH
(9.0V), an external circuit is required to limit the VPP
voltage. See Figure 23-1 for example circuit.
FIGURE 23-1:
VPP LIMITER EXAMPLE CIRCUIT
RJ11-6PIN
6
5
4
3
2
1
VPP
2
VDD
3
VSS
4
ICSP_DATA
ICSP_CLOCK
NC
5
6
1
RJ11-6PIN
R1
To MPLAB® ICD 2
To Target Board
270 Ohm
LM431BCMX
1
2
K
A
A
A
A
U1
3
6
7
4
5
NC
NC
VREF
8
R2
R3
10k 1%
24k 1%
Note:
The MPLAB® ICD 2 produces a VPP
voltage greater than the maximum VPP
specification of the PIC16(L)F151X.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 265
PIC16(L)F1516/7/8/9
FIGURE 23-2:
ICD RJ-11 STYLE
CONNECTOR INTERFACE
23.2 Low-Voltage Programming Entry
Mode
The Low-Voltage Programming Entry mode allows the
PIC16(L)F151X devices to be programmed using VDD
only, without high voltage. When the LVP bit of
Configuration Word 2 is set to ‘1’, the low-voltage ICSP
programming entry is enabled. To disable the
Low-Voltage ICSP mode, the LVP bit must be
programmed to ‘0’.
ICSPDAT
NC
2 4 6
VDD
ICSPCLK
1 3
5
Target
PC Board
Bottom Side
Entry into the Low-Voltage Programming Entry mode
requires the following steps:
VPP/MCLR
VSS
1. MCLR is brought to VIL.
2.
A
32-bit key sequence is presented on
Pin Description*
ICSPDAT, while clocking ICSPCLK.
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
Once the key sequence is complete, MCLR must be
held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the
MCLR Reset function is automatically enabled and
cannot be disabled. See Section 6.3 “Low-Power
Brown-out Reset (LPBOR)” for more information.
5 = ICSPCLK
6 = No Connect
The LVP bit can only be reprogrammed to ‘0’ by using
the High-Voltage Programming mode.
Another connector often found in use with the PICkit™
programmers is a standard 6-pin header with 0.1 inch
spacing. Refer to Figure 23-3.
23.3 Common Programming Interfaces
Connection to a target device is typically done through
an ICSP™ header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6 pin, 6
connector) configuration. See Figure 23-2.
FIGURE 23-3:
PICkit™ STYLE CONNECTOR INTERFACE
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
1
2
3
4
5
6
5 = ICSPCLK
6 = No Connect
*
The 6-pin header (0.100" spacing) accepts 0.025" square pins.
DS41452B-page 266
Preliminary
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For additional interface recommendations, refer to your
specific device programmer manual prior to PCB
design.
It is recommended that isolation devices be used to
separate the programming pins from other circuitry.
The type of isolation is highly dependent on the specific
application and may include devices such as resistors,
diodes, or even jumpers. See Figure 23-4 for more
information.
FIGURE 23-4:
TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
*
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 268
Preliminary
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24.1 Read-Modify-Write Operations
24.0 INSTRUCTION SET SUMMARY
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruc-
tion, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
Each PIC16 instruction is a 14-bit word containing the
operation code (opcode) and all required operands.
The opcodes are broken into three broad categories.
• Byte Oriented
• Bit Oriented
• Literal and Control
The literal and control category contains the most var-
ied instruction word format.
TABLE 24-1: OPCODE FIELD
DESCRIPTIONS
Table 24-3 lists the instructions recognized by the
MPASMTM assembler.
Field
Description
All instructions are executed within a single instruction
cycle, with the following exceptions, which may take
two or three cycles:
f
W
b
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
• Subroutine takes two cycles (CALL, CALLW)
• Returns from interrupts or subroutines take two
cycles (RETURN, RETLW, RETFIE)
k
x
Don’t care location (= 0or 1).
• Program branching takes two cycles (GOTO, BRA,
BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
• One additional instruction cycle will be used when
any instruction references an indirect file register
and the file select register is pointing to program
memory.
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
One instruction cycle consists of 4 oscillator cycles; for
an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
n
FSR or INDF number. (0-1)
mm
Pre-post increment-decrement mode
selection
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
TABLE 24-2: ABBREVIATION
DESCRIPTIONS
Field
Description
PC
TO
C
Program Counter
Time-out bit
Carry bit
DC
Z
Digit carry bit
Zero bit
PD
Power-down bit
2011 Microchip Technology Inc.
Preliminary
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FIGURE 24-1:
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8
7
6
0
OPCODE
d
f (FILE #)
d = 0for destination W
d = 1for destination f
f = 7-bit file register address
Bit-oriented file register operations
13 10 9
7 6
0
OPCODE
b (BIT #)
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
0
OPCODE
k (literal)
k = 8-bit immediate value
CALLand GOTOinstructions only
13 11 10
OPCODE
0
k (literal)
k = 11-bit immediate value
MOVLPinstruction only
13
7
6
0
0
OPCODE
k (literal)
k = 7-bit immediate value
MOVLBinstruction only
13
5 4
OPCODE
k (literal)
k = 5-bit immediate value
BRAinstruction only
13
9
8
0
OPCODE
k (literal)
k = 9-bit immediate value
FSR Offset instructions
13
7
6
5
0
0
OPCODE
n
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSRIncrement instructions
13
3
2
n
1
OPCODE
m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
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TABLE 24-3:
INSTRUCTION SET
14-Bit Opcode
Status
Mnemonic,
Operands
Description
Cycles
Notes
Affected
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ADDWFC f, d
ANDWF
ASRF
LSLF
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00 0111 dfff ffff C, DC, Z
11 1101 dfff ffff C, DC, Z
00 0101 dfff ffff Z
11 0111 dfff ffff C, Z
11 0101 dfff ffff C, Z
11 0110 dfff ffff C, Z
2
2
2
2
2
2
2
f, d
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB f, d
SWAPF
XORWF
00 0001 lfff ffff
00 0001 0000 00xx
00 1001 dfff ffff
00 0011 dfff ffff
00 1010 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 1fff ffff
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Z
Z
–
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
2
2
2
2
2
2
2
2
2
2
2
2
C
C
00 0010 dfff ffff C, DC, Z
11 1011 dfff ffff C, DC, Z
00 1110 dfff ffff
f, d
f, d
00 0110 dfff ffff
Z
BYTE ORIENTED SKIP OPERATIONS
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
1(2)
1(2)
00
00
1011 dfff ffff
1111 dfff ffff
1, 2
1, 2
DECFSZ
INCFSZ
BIT-ORIENTED FILE REGISTER OPERATIONS
f, b
f, b
Bit Clear f
Bit Set f
1
1
01
01
00bb bfff ffff
01bb bfff ffff
2
2
BCF
BSF
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
01
01
10bb bfff ffff
11bb bfff ffff
1, 2
1, 2
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Inclusive OR literal with W
Move literal to BSR
Move literal to PCLATH
Move literal to W
1
1
1
1
1
1
1
1
11
11
11
00
11
11
11
11
1110 kkkk kkkk C, DC, Z
1001 kkkk kkkk
1000 kkkk kkkk
0000 001k kkkk
0001 1kkk kkkk
0000 kkkk kkkk
Z
Z
Subtract W from literal
Exclusive OR literal with W
1100 kkkk kkkk C, DC, Z
1010 kkkk kkkk
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
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TABLE 24-3:
INSTRUCTION SET (CONTINUED)
14-Bit Opcode
Mnemonic,
Operands
Status
Affected
Description
Cycles
Notes
MSb
LSb
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
–
k
–
k
k
k
–
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k kkkk kkkk
0000 0000 1011
0kkk kkkk kkkk
0000 0000 1010
1kkk kkkk kkkk
0000 0000 1001
0100 kkkk kkkk
0000 0000 1000
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
–
–
–
–
–
f
Clear Watchdog Timer
No Operation
Load OPTION_REG register with W
Software device Reset
Go into Standby mode
Load TRIS register with W
1
1
1
1
1
1
00
00
00
00
00
00
0000 0110 0100 TO, PD
0000 0000 0000
0000 0110 0010
0000 0000 0001
0000 0110 0011 TO, PD
0000 0110 0fff
C-COMPILER OPTIMIZED
ADDFSR n, k
Add Literal k to FSRn
Move Indirect FSRn to W with pre/post inc/dec
modifier, mm
1
1
11 0001 0nkk kkkk
00 0000 0001 0nmm
MOVIW
n mm
Z
Z
2, 3
k[n]
n mm
Move INDFn to W, Indexed Indirect.
Move W to Indirect FSRn with pre/post inc/dec
modifier, mm
1
1
11 1111 0nkk kkkk
00 0000 0001 1nmm
2
2, 3
MOVWI
k[n]
Move W to INDFn, Indexed Indirect.
1
11 1111 1nkk kkkk
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See Table in the MOVIW and MOVWI instruction descriptions.
DS41452B-page 272
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PIC16(L)F1516/7/8/9
24.2 Instruction Descriptions
ADDFSR
Add Literal to FSRn
ANDLW
AND literal with W
Syntax:
[ label ] ADDFSR FSRn, k
Syntax:
[ label ] ANDLW
0 k 255
k
Operands:
-32 k 31
n [ 0, 1]
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) (W)
Operation:
FSR(n) + k FSR(n)
Z
Status Affected:
Description:
None
The contents of W register are
AND’ed with the eight-bit literal ‘k’.
The result is placed in the W register.
The signed 6-bit literal ‘k’ is added to
the contents of the FSRnH:FSRnL
register pair.
FSRn is limited to the range 0000h -
FFFFh. Moving beyond these bounds
will cause the FSR to wrap-around.
ANDWF
AND W with f
ADDLW
Add literal and W
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDLW
0 k 255
k
Operands:
0 f 127
d 0,1
Operands:
Operation:
Status Affected:
Description:
(W) + k (W)
C, DC, Z
Operation:
(W) .AND. (f) (destination)
Status Affected:
Description:
Z
The contents of the W register are
added to the eight-bit literal ‘k’ and the
result is placed in the W register.
AND the W register with register ‘f’. If
‘d’ is ‘0’, the result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
ASRF
Arithmetic Right Shift
ADDWF
Add W and f
Syntax:
[ label ] ASRF f {,d}
Syntax:
[ label ] ADDWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d 0,1
Operation:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Operation:
(W) + (f) (destination)
Status Affected:
Description:
C, DC, Z
Add the contents of the W register
with register ‘f’. If ‘d’ is ‘0’, the result is
stored in the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. The MSb remains unchanged. If
‘d’ is ‘0’, the result is placed in W. If ‘d’
is ‘1’, the result is stored back in reg-
ister ‘f’.
ADDWFC
ADD W and CARRY bit to f
C
register f
Syntax:
[ label ] ADDWFC
f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(W) + (f) + (C) dest
Status Affected:
Description:
C, DC, Z
Add W, the Carry flag and data mem-
ory location ‘f’. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed in data memory location ‘f’.
2011 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
BTFSC
Bit Test f, Skip if Clear
BCF
Bit Clear f
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] BCF f,b
Operands:
0 f 127
0 b 7
Operands:
0 f 127
0 b 7
Operation:
skip if (f<b>) = 0
Operation:
0 (f<b>)
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘1’, the next
instruction is executed.
Bit ‘b’ in register ‘f’ is cleared.
If bit ‘b’, in register ‘f’, is ‘0’, the next
instruction is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
BTFSS
Bit Test f, Skip if Set
BRA
Relative Branch
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] BRA label
[ label ] BRA $+k
Operands:
0 f 127
0 b < 7
Operands:
-256 label - PC + 1 255
-256 k 255
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
Description:
None
Status Affected:
Description:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next
instruction is executed.
If bit ‘b’ is ‘1’, then the next
instruction is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
Add the signed 9-bit literal ‘k’ to the
PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + k.
This instruction is a two-cycle instruc-
tion. This branch has a limited range.
BRW
Relative Branch with W
Syntax:
[ label ] BRW
None
Operands:
Operation:
Status Affected:
Description:
(PC) + (W) PC
None
Add the contents of W (unsigned) to
the PC. Since the PC will have incre-
mented to fetch the next instruction,
the new address will be PC + 1 + (W).
This instruction is a two-cycle instruc-
tion.
BSF
Bit Set f
Syntax:
[ label ] BSF f,b
Operands:
0 f 127
0 b 7
Operation:
1 (f<b>)
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
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CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL
0 k 2047
k
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
00h WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
Description:
None
Status Affected:
Description:
TO, PD
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALLis a two-cycle instruc-
tion.
CLRWDTinstruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
CALLW
Subroutine Call With W
Syntax:
[ label ] COMF f,d
Syntax:
[ label ] CALLW
Operands:
0 f 127
d [0,1]
Operands:
Operation:
None
(PC) +1 TOS,
(W) PC<7:0>,
Operation:
(f) (destination)
(PCLATH<6:0>) PC<14:8>
Status Affected:
Description:
Z
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
Status Affected:
Description:
None
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLWis a two-cycle
instruction.
DECF
Decrement f
CLRF
Clear f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ] CLRF
0 f 127
f
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h (f)
1 Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
The contents of register ‘f’ are cleared
and the Z bit is set.
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
Operation:
None
00h (W)
1 Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is
set.
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DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
Description:
None
Status Affected:
Description:
None
The contents of register ‘f’ are decre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, then a
NOPis executed instead, making it a
2-cycle instruction.
If the result is ‘1’, the next instruction is
executed. If the result is ‘0’, a NOPis
executed instead, making it a 2-cycle
instruction.
GOTO
Unconditional Branch
IORLW
Inclusive OR literal with W
Syntax:
[ label ] GOTO
0 k 2047
k
Syntax:
[ label ] IORLW
0 k 255
(W) .OR. k (W)
Z
k
Operands:
Operation:
Operands:
Operation:
Status Affected:
Description:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Status Affected:
Description:
None
The contents of the W register are
OR’ed with the eight-bit literal ‘k’. The
result is placed in the W register.
GOTOis an unconditional branch. The
eleven-bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] IORWF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
(W) .OR. (f) (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ‘f’ are incre-
mented. If ‘d’ is ‘0’, the result is placed
in the W register. If ‘d’ is ‘1’, the result
is placed back in register ‘f’.
Inclusive OR the W register with regis-
ter ‘f’. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
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LSLF
Logical Left Shift
MOVF
Move f
Syntax:
[ label ] LSLF f {,d}
Syntax:
[ label ] MOVF f,d
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
Operation:
(f) (dest)
(f<6:0>) dest<7:1>
0 dest<0>
Status Affected:
Description:
Z
The contents of register f is moved to
a destination dependent upon the
status of d. If d = 0,
destination is W register. If d = 1, the
destination is file register f itself. d = 1
is useful to test a file register since
status flag Z is affected.
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,
the result is placed in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.
Words:
1
1
C
register f
0
Cycles:
Example:
MOVF
FSR, 0
After Instruction
LSRF
Logical Right Shift
W
Z
=
=
value in FSR register
1
Syntax:
[ label ] LSLF f {,d}
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
Description:
C, Z
The contents of register ‘f’ are shifted
one bit to the right through the Carry
flag. A ‘0’ is shifted into the MSb. If ‘d’ is
‘0’, the result is placed in W. If ‘d’ is ‘1’,
the result is stored back in register ‘f’.
0
C
register f
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MOVIW
Move INDFn to W
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
[ label ] MOVLP
0 k 127
k PCLATH
None
k
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
The seven-bit literal ‘k’ is loaded into the
PCLATH register.
INDFn W
Effective address is determined by
MOVLW
Move literal to W
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Syntax:
[ label ] MOVLW
0 k 255
k (W)
k
Operands:
Operation:
Status Affected:
Description:
After the Move, the FSR value will be
either:
None
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
The eight-bit literal ‘k’ is loaded into W
register. The “don’t cares” will assem-
ble as ‘0’s.
Status Affected:
Z
Words:
1
1
Cycles:
Example:
Mode
Syntax
mm
00
01
10
11
MOVLW
0x5A
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
After Instruction
W
=
0x5A
MOVWF
Move W to f
[ label ] MOVWF
0 f 127
(W) (f)
Syntax:
f
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Operands:
Operation:
Status Affected:
Description:
None
Move data from W register to register
‘f’.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
Words:
1
1
Cycles:
Example:
MOVWF
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
OPTION_REG
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to wrap
around.
After Instruction
OPTION_REG = 0x4F
W = 0x4F
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB
0 k 15
k BSR
None
k
Operands:
Operation:
Status Affected:
Description:
The five-bit literal ‘k’ is loaded into the
Bank Select Register (BSR).
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NOP
No Operation
MOVWI
Move W to INDFn
Syntax:
[ label ] NOP
Syntax:
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Operands:
Operation:
Status Affected:
Description:
Words:
None
No operation
None
No operation.
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
1
Cycles:
1
W INDFn
Effective address is determined by
Example:
NOP
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
Load OPTION_REG Register
with W
OPTION
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Syntax:
[ label ] OPTION
None
Unchanged
Operands:
Operation:
Status Affected:
Description:
Status Affected:
None
(W) OPTION_REG
None
Mode
Syntax
mm
00
01
10
11
Move data from W register to
OPTION_REG register.
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
Words:
1
Cycles:
Example:
1
OPTION
Before Instruction
OPTION_REG = 0xFF
W = 0x4F
After Instruction
OPTION_REG = 0x4F
W = 0x4F
Description:
This instruction is used to move data
between W and one of the indirect
registers (INDFn). Before/after this
move, the pointer (FSRn) is updated by
pre/post incrementing/decrementing it.
Note: The INDFn registers are not
physical registers. Any instruction that
accesses an INDFn register actually
accesses the register at the address
specified by the FSRn.
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
Operation:
None
FSRn is limited to the range 0000h -
FFFFh. Incrementing/decrementing it
beyond these bounds will cause it to
wrap-around.
Execute a device Reset. Resets the
nRI flag of the PCON register.
Status Affected:
Description:
None
This instruction provides a way to
execute a hardware Reset by soft-
ware.
The increment/decrement operation on
FSRn WILL NOT affect any Status bits.
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RETURN
Return from Subroutine
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE
None
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
TOS PC
None
TOS PC,
1 GIE
Status Affected:
Description:
None
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter.
This is a two-cycle instruction.
Return from Interrupt. Stack is POPed
and Top-of-Stack (TOS) is loaded in
the PC. Interrupts are enabled by
setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-cycle
instruction.
Words:
1
Cycles:
Example:
2
RETFIE
After Interrupt
PC
=
TOS
GIE =
1
RLF
Rotate Left f through Carry
RETLW
Syntax:
Return with literal in W
Syntax:
Operands:
[ label ]
RLF f,d
[ label ] RETLW
0 k 255
k
0 f 127
d [0,1]
Operands:
Operation:
k (W);
TOS PC
Operation:
See description below
C
Status Affected:
Description:
Status Affected:
Description:
None
The contents of register ‘f’ are rotated
one bit to the left through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
The W register is loaded with the eight
bit literal ‘k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
C
Register f
Words:
1
2
Cycles:
Example:
Words:
1
1
CALL TABLE;W contains table
;offset value
Cycles:
Example:
•
•
•
;W now has table value
RLF
REG1,0
TABLE
Before Instruction
REG1
C
=
=
1110 0110
0
ADDWF PC ;W = offset
RETLW k1 ;Begin table
After Instruction
RETLW k2
;
REG1
W
C
=
=
=
1110 0110
1100 1100
1
•
•
•
RETLW kn ; End of table
Before Instruction
W
=
0x07
After Instruction
W
=
value of k8
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SUBLW
Subtract W from literal
RRF
Rotate Right f through Carry
Syntax:
[ label ] SUBLW
0 k 255
k
Syntax:
[ label ] RRF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 f 127
d [0,1]
k - (W) W)
C, DC, Z
Operation:
See description below
C
The W register is subtracted (2’s com-
plement method) from the eight-bit
literal ‘k’. The result is placed in the W
register.
Status Affected:
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in
the W register. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
C = 0
W k
C = 1
W k
C
Register f
DC = 0
DC = 1
W<3:0> k<3:0>
W<3:0> k<3:0>
SUBWF
Subtract W from f
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
[ label ] SUBWF f,d
Syntax:
Operands:
0 f 127
d [0,1]
Operands:
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
Operation:
(f) - (W) destination)
Status Affected:
Description:
C, DC, Z
0 PD
Subtract (2’s complement method) W
register from register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f.
Status Affected:
Description:
TO, PD
The power-down Status bit, PD is
cleared. Time-out Status bit, TO is
set. Watchdog Timer and its pres-
caler are cleared.
C = 0
W f
The processor is put into Sleep mode
with the oscillator stopped.
C = 1
W f
DC = 0
DC = 1
W<3:0> f<3:0>
W<3:0> f<3:0>
SUBWFB
Subtract W from f with Borrow
Syntax:
SUBWFB f {,d}
Operands:
0 f 127
d [0,1]
Operation:
(f) – (W) – (B) dest
Status Affected:
Description:
C, DC, Z
Subtract W and the BORROW flag
(CARRY) from register ‘f’ (2’s comple-
ment method). If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
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SWAPF
Swap Nibbles in f
XORLW
Exclusive OR literal with W
Syntax:
[ label ] SWAPF f,d
Syntax:
[ label ] XORLW
0 k 255
k
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) .XOR. k W)
Z
Operation:
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
The contents of the W register are
XOR’ed with the eight-bit
literal ‘k’. The result is placed in the
W register.
Status Affected:
Description:
None
The upper and lower nibbles of regis-
ter ‘f’ are exchanged. If ‘d’ is ‘0’, the
result is placed in the W register. If ‘d’
is ‘1’, the result is placed in register ‘f’.
XORWF
Exclusive OR W with f
TRIS
Load TRIS Register with W
Syntax:
[ label ] XORWF f,d
Syntax:
[ label ] TRIS f
5 f 7
Operands:
0 f 127
d [0,1]
Operands:
Operation:
Status Affected:
Description:
(W) TRIS register ‘f’
None
Operation:
(W) .XOR. (f) destination)
Status Affected:
Description:
Z
Move data from W register to TRIS
register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
When ‘f’ = 7, TRISC is loaded.
Exclusive OR the contents of the W
register with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If ‘d’
is ‘1’, the result is stored back in regis-
ter ‘f’.
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25.0 ELECTRICAL SPECIFICATIONS
(†)
Absolute Maximum Ratings
Ambient temperature under bias....................................................................................................... -40°C to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS, PIC16F151X ............................................................................. -0.3V to +6.5V
Voltage on VDD with respect to VSS, PIC16LF151X ........................................................................... -0.3V to +4.0V
Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total power dissipation(1) ...............................................................................................................................800 mW
Maximum current out of VSS pin, -40°C TA +85°C for industrial............................................................... 340 mA
Maximum current out of VSS pin, -40°C TA +125°C for extended ............................................................ 140 mA
Maximum current into VDD pin, -40°C TA +85°C for industrial.................................................................. 255 mA
Maximum current into VDD pin, -40°C TA +125°C for extended............................................................... 105 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD)20 mA
Maximum output current sunk by any I/O pin....................................................................................................25 mA
Maximum output current sourced by any I/O pin .............................................................................................. 25 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL).
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
2011 Microchip Technology Inc.
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PIC16(L)F1516/7/8/9
FIGURE 25-1:
PIC16F151X VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
5.5
2.5
2.3
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
FIGURE 25-2:
PIC16LF151X VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C
3.6
2.5
1.8
0
4
10
16
20
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 25-1 for each Oscillator mode’s supported frequencies.
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25.1 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param.
No.
Sym.
Characteristic
Supply Voltage
Min.
Typ† Max. Units
Conditions
D001
VDD
PIC16LF151X
1.8
2.5
—
—
3.6
3.6
V
V
FOSC 16 MHz:
FOSC 20 MHz
D001
PIC16F151X
2.3
2.5
—
—
5.5
5.5
V
V
FOSC 16 MHz:
FOSC 20 MHz
D002*
VDR
RAM Data Retention Voltage(1)
PIC16LF151X
PIC16F151X
Power-on Reset Release Voltage
Power-on Reset Rearm Voltage
PIC16LF151X
1.5
1.7
—
—
—
—
—
—
V
V
V
Device in Sleep mode
Device in Sleep mode
D002*
D003
VPOR*
1.6
VPORR*
—
—
0.8
1.7
—
—
V
V
Device in Sleep mode
Device in Sleep mode
PIC16F151X
VADFVR
Fixed Voltage Reference Voltage for
ADC, Initial Accuracy
-7
-8
-7
-8
-7
-8
6
6
6
6
6
6
%
1.024V, VDD 2.5V, 85°C (NOTE 2)
1.024V, VDD 2.5V, 125°C (NOTE 2)
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
D003A VCDAFVR
Fixed Voltage Reference Voltage for
Comparator and DAC, Initial Accu-
racy
-11
-11
-11
-11
-11
-11
7
7
7
7
7
7
%
1.024V, VDD 2.5V, 85°C
1.024V, VDD 2.5V, 125°C
2.048V, VDD 2.5V, 85°C
2.048V, VDD 2.5V, 125°C
4.096V, VDD 4.75V, 85°C
4.096V, VDD 4.75V, 125°C
D004*
SVDD
VDD Rise Rate to ensure internal
Power-on Reset signal
0.05
—
—
V/ms See Section 6.1 “Power-on Reset
(POR)” for details.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: For proper operation, the minimum value of the ADC positive voltage reference must be 1.8V or greater. When selecting
the FVR or the VREF+ pin as the source of the ADC positive voltage reference, be aware that the voltage must be 1.8V or
greater.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 285
PIC16(L)F1516/7/8/9
FIGURE 25-3:
POR AND POR REARM WITH SLOW RISING VDD
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
(3)
(2)
TPOR
TVLOW
Note 1: When NPOR is low, the device is held in Reset.
2: TPOR 1 s typical.
3: TVLOW 2.7 s typical.
DS41452B-page 286
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.2 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
D010
D010
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
8.0
12.0
11
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FOSC = 32 kHz
LP Oscillator mode
FOSC = 32 kHz
LP Oscillator mode
13
14
D011
D011
60
FOSC = 1 MHz
XT Oscillator mode
110
92
FOSC = 1 MHz
XT Oscillator mode
135
170
145
260
190
305
365
118
210
D012
D012
FOSC = 4 MHz
XT Oscillator mode
FOSC = 4 MHz
XT Oscillator mode
D014
D014
FOSC = 4 MHz
EC Oscillator mode,
Medium-power mode
—
—
—
—
—
—
—
—
156
260
330
2.0
4.0
18
A
A
A
A
A
A
A
A
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
FOSC = 4 MHz
EC Oscillator mode
Medium-power mode
—
—
—
—
—
—
—
—
D015
D015
FOSC = 31 kHz
LFINTOSC mode
FOSC = 31 kHz
LFINTOSC mode
24
25
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 287
PIC16(L)F1516/7/8/9
25.2 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
PIC16F151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
D016
D016
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
110
150
A
A
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
FOSC = 500 kHz
HFINTOSC mode
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
150
A
FOSC = 500 kHz
HFINTOSC mode
210
A
335
A
D017*
D017*
0.25
0.45
0.35
0.69
0.75
0.47
0.84
0.70
1.00
1.17
1.15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
FOSC = 8 MHz
HFINTOSC mode
FOSC = 8 MHz
HFINTOSC mode
D018
D018
FOSC = 16 MHz
HFINTOSC mode
FOSC = 16 MHz
HFINTOSC mode
D019A
D019A
FOSC = 20 MHz
ECH mode
—
—
—
—
—
—
—
—
—
—
1.15
1.3
8
mA
mA
A
A
A
A
A
A
A
A
3.0
5.0
1.8
3.0
3.0
5.0
1.8
3.0
3.0
5.0
FOSC = 20 MHz
ECH mode
—
—
—
—
—
—
—
—
—
—
D019B
D019B
D019C
D019C
FOSC = 32 kHz
ECL mode
10
10
11
FOSC = 32 kHz
ECL mode
25
35
35
40
FOSC = 500 kHz
ECL mode
FOSC = 500 kHz
ECL mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
DS41452B-page 288
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.2 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Param
No.
Device
Characteristics
Min.
Typ†
Max.
Units
VDD
Note
(1, 2)
Supply Current (IDD)
D020
D020
D021
D021
—
—
—
—
—
—
—
—
—
1.0
1.2
mA
mA
mA
mA
A
A
A
A
A
3.0
3.6
3.0
5.0
1.8
3.0
2.3
3.0
5.0
FOSC = 20 MHz
HS Oscillator mode
—
—
—
—
—
—
—
—
—
1.4
FOSC = 20 MHz
HS Oscillator mode
1.7
300
500
165
280
350
FOSC = 4 MHz
EXTRC mode (Note 5)
FOSC = 4 MHz
EXTRC mode (Note 5)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current
consumption.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended
by the formula IR = VDD/2REXT (mA) with REXT in k.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 289
PIC16(L)F1516/7/8/9
25.3 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Power-Down)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F151X
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D022
—
—
—
—
20
30
—
—
—
—
—
—
—
—
nA
nA
nA
nA
1.8
3.0
3.0
5.0
WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive
D022
300
470
WDT, BOR, FVR, and SOSC
disabled, all Peripherals Inactive,
Low-power regulator active
D023
D023
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
300
750
500
770
850
8.5
8.5
18
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
nA
nA
nA
nA
nA
A
A
A
A
A
A
A
A
nA
nA
nA
A
A
A
A
A
A
A
nA
nA
nA
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
3.0
3.0
5.0
3.0
3.0
5.0
1.8
3.0
2.3
3.0
5.0
1.8
3.0
2.3
3.0
5.0
LPWDT Current (Note 1)
LPWDT Current (Note 1)
D023A
D023A
FVR current (Note 1)
FVR current (Note 1)
18.5
19
D024
D024
8.0
7
BOR Current (Note 1)
BOR Current (Note 1)
9
D024A
D024A
300
300
450
0.6
1.8
0.7
3
LPBOR Current
LPBOR Current
D025
D025
SOSC Current (Note 1)
SOSC Current (Note 1)
6
D026
D026
0.1
0.1
160
400
500
A/D Current (Note 1, Note 3), no
conversion in progress
A/D Current (Note 1, Note 3), no
conversion in progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
DS41452B-page 290
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.3 DC Characteristics: PIC16(L)F1516/7/8/9-I/E (Power-Down) (Continued)
Standard Operating Conditions (unless otherwise stated)
PIC16LF151X
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Standard Operating Conditions (unless otherwise stated)
PIC16F151X
Param
Operating temperature
-40°C TA +85°C for industrial
-40°C TA +125°C for extended
Conditions
Max.
Max.
Device Characteristics
Min.
Typ†
Units
No.
+85°C +125°C
VDD
Note
(2)
Power-down Base Current (IPD)
D026A*
D026A*
—
—
—
—
—
250
250
280
280
280
—
—
—
—
—
—
—
—
—
—
A
A
A
A
A
1.8
3.0
2.3
3.0
5.0
A/D Current (Note 1, Note 3),
conversion in progress
A/D Current (Note 1, Note 3),
conversion in progress
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is
enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max
values should be used when calculating total current consumption.
2: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with
the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.
3: A/D oscillator source is FRC.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 291
PIC16(L)F1516/7/8/9
25.4 DC Characteristics: PIC16(L)F1516/7/8/9-I/E
Standard Operating Conditions (unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for industrial
-40°C TA +125°C for extended
Param
No.
Sym.
Characteristic
Min.
Typ†
Max.
Units
Conditions
VIL
Input Low Voltage
I/O PORT:
D030
D030A
D031
with TTL buffer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.8
V
V
V
V
V
V
V
4.5V VDD 5.5V
0.15 VDD
0.2 VDD
0.3 VDD
0.8
1.8V VDD 4.5V
2.0V VDD 5.5V
with Schmitt Trigger buffer
with I2C™ levels
with SMBus levels
MCLR, OSC1 (RC mode)(1)
OSC1 (HS mode)
Input High Voltage
I/O ports:
2.7V VDD 5.5V
D032
D033
0.2 VDD
0.3 VDD
VIH
—
—
—
—
—
—
D040
with TTL buffer
2.0
V
V
4.5V VDD 5.5V
1.8V VDD 4.5V
D040A
0.25 VDD +
0.8
D041
with Schmitt Trigger buffer
with I2C™ levels
with SMBus levels
MCLR
0.8 VDD
0.7 VDD
2.1
—
—
—
—
—
—
—
—
—
—
—
—
V
V
V
V
V
V
2.0V VDD 5.5V
2.7V VDD 5.5V
D042
0.8 VDD
0.7 VDD
0.9 VDD
D043A
D043B
OSC1 (HS mode)
OSC1 (RC mode)
(Note 1)
(2)
IIL
Input Leakage Current
D060
I/O ports
—
—
± 5
± 125
nA
VSS VPIN VDD, Pin at high-
impedance at 85°C
± 5
± 1000
± 200
nA 125°C
D061
MCLR(3)
± 50
nA
A
V
VSS VPIN VDD at 85°C
IPUR
VOL
Weak Pull-up Current
D070*
25
25
100
140
200
300
VDD = 3.3V, VPIN = VSS
VDD = 5.0V, VPIN = VSS
(4)
Output Low Voltage
D080
D090
D101*
I/O ports
IOL = 8mA, VDD = 5V
IOL = 6mA, VDD = 3.3V
IOL = 1.8mA, VDD = 1.8V
—
—
—
0.6
—
(4)
VOH
Output High Voltage
I/O ports
IOH = 3.5mA, VDD = 5V
IOH = 3mA, VDD = 3.3V
IOH = 1mA, VDD = 1.8V
VDD - 0.7
V
Capacitive Loading Specs on Output Pins
COSC2 OSC2 pin
—
—
—
15
50
pF
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
D101A* CIO
All I/O pins
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external
clock in RC mode.
2: Negative current is defined as current sourced by the pin.
3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent
normal operating conditions. Higher leakage current may be measured at different input voltages.
4: Including OSC2 in CLKOUT mode.
DS41452B-page 292
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.5 Memory Programming Requirements
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
DC CHARACTERISTICS
Param
Sym.
No.
Characteristic
Program Memory
Min.
Typ†
Max.
Units
Conditions
Programming Specifications
D110
D111
VIHH
IDDP
Voltage on MCLR/VPP/RA5 pin
8.0
—
—
—
9.0
10
V
(Note 2, Note 3)
Supply Current during
Programming
mA
VDD for Bulk Erase
2.7
—
—
VDD
max.
V
V
D112
D113
VPEW
VDD for Write or Row Erase
VDD
min.
VDD
max.
IPPPGM Current on MCLR/VPP during Erase/
Write
—
—
1.0
mA
mA
D114
D115
IDDPGM Current on VDD during Erase/Write
—
5.0
Program Flash Memory
D121
D122
EP
Cell Endurance
VDD for Read
10K
—
—
—
E/W -40C to +85C (Note 1)
VDD
min.
VDD
max.
VPR
V
D123
D124
TIW
Self-timed Write Cycle Time
—
2
2.5
—
ms
TRETD Characteristic Retention
40
—
Year Provided no other
specifications are violated
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Self-write and Block Erase.
2: Required only if single-supply programming is disabled.
®
3: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be
placed between the ICD 2 and target system when programming or debugging with the ICD 2.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 293
PIC16(L)F1516/7/8/9
25.6 Thermal Considerations
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Typ.
Units
Conditions
28-pin SOIC package
TH01
JA
Thermal Resistance Junction to Ambient
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
C/W
C/W
C/W
C/W
C/W
C/W
C/W
C/W
28-pin SPDIP package
28-pin SSOP package
28-pin UQFN package
40-pin PDIP package
40-pin UQFN package
44-pin TQFP package
TH02
JC
Thermal Resistance Junction to Case
28-pin SOIC package
28-pin SPDIP package
28-pin SSOP package
28-pin UQFN package
40-pin PDIP package
40-pin UQFN package
44-pin TQFP package
TBD
TBD
TBD
TBD
TBD
TBD
150
—
C/W
C/W
C/W
C/W
C/W
C/W
C
TH03
TH04
TH05
TH06
TH07
Legend:
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
W
PD = PINTERNAL + PI/O
PINTERNAL = IDD x VDD
(1)
PINTERNAL Internal Power Dissipation
—
W
PI/O
I/O Power Dissipation
Derated Power
—
W
PI/O = (IOL * VOL) + (IOH * (VDD - VOH))
(2)
PDER
—
W
PDER = PDMAX (TJ - TA)/JA
TBD = To Be Determined
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature.
3: TJ = Junction Temperature.
DS41452B-page 294
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
25.7
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCKx
SS
SDIx
do
dt
SDO
Data in
I/O PORT
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (High-impedance)
Low
Valid
L
High-impedance
FIGURE 25-4:
LOAD CONDITIONS
Load Condition
Pin
CL
VSS
Legend: CL = 50 pF for all pins, 15 pF for
OSC2 output
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 295
PIC16(L)F1516/7/8/9
25.8 AC Characteristics: PIC16(L)F151X-I/E
FIGURE 25-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1/CLKIN
OS02
OS04
OS04
OS03
OSC2/CLKOUT
(LP,XT,HS Modes)
OSC2/CLKOUT
(CLKOUT Mode)
TABLE 25-1: CLOCK OSCILLATOR TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max.
Units
Conditions
OS01
FOSC
TOSC
TCY
External CLKIN Frequency(1)
DC
DC
DC
—
—
—
0.5
4
MHz EC Oscillator mode (low)
MHz EC Oscillator mode (medium)
MHz EC Oscillator mode (high)
—
20
—
4
Oscillator Frequency(1)
32.768
—
kHz
LP Oscillator mode
0.1
1
MHz XT Oscillator mode
—
4
MHz HS Oscillator mode, VDD 2.7V
MHz HS Oscillator mode, VDD > 2.7V
MHz RC Oscillator mode
1
—
20
4
DC
27
250
50
50
—
—
OS02
External CLKIN Period(1)
Oscillator Period(1)
—
s
ns
ns
ns
s
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
EC Oscillator mode
LP Oscillator mode
XT Oscillator mode
HS Oscillator mode
RC Oscillator mode
TCY = FOSC/4
—
—
—
30.5
—
—
10,000
1,000
—
DC
—
—
—
250
50
250
125
2
—
—
OS03
Instruction Cycle Time(1)
—
OS04*
TosH,
TosL
External CLKIN High,
External CLKIN Low
—
LP oscillator
100
20
0
—
XT oscillator
—
HS oscillator
OS05*
TosR,
TosF
External CLKIN Rise,
External CLKIN Fall
—
LP oscillator
0
—
XT oscillator
0
—
HS oscillator
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external
clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
DS41452B-page 296
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 25-2: OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param
Sym.
No.
Freq.
Tolerance
Characteristic
Min. Typ† Max. Units
Conditions
OS08
HFOSC
Internal Calibrated HFINTOSC
Frequency(2)
10%
—
—
—
16.0
31
5
—
—
8
MHz 0°C TA +85°C
OS09
LFOSC
Internal LFINTOSC Frequency
—
kHz
OS10* TIOSC ST HFINTOSC
Wake-up from Sleep Start-up Time
—
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con-
sumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an exter-
nal clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
3: By design.
FIGURE 25-6:
CLKOUT AND I/O TIMING
Cycle
Write
Q4
Fetch
Q1
Read
Q2
Execute
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS13
OS18
OS16
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 297
PIC16(L)F1516/7/8/9
TABLE 25-3: CLKOUT AND I/O TIMING PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
OS11 TosH2ckL FOSC to CLKOUT (1)
OS12 TosH2ckH FOSC to CLKOUT (1)
OS13 TckL2ioV CLKOUT to Port out valid(1)
—
—
—
—
—
—
70
72
20
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
ns
OS14 TioV2ckH Port input valid before CLKOUT(1)
OS15 TosH2ioV Fosc (Q1 cycle) to Port out valid
TOSC + 200 ns
—
50
—
—
70*
—
ns
—
ns VDD = 3.3-5.0V
ns VDD = 3.3-5.0V
OS16 TosH2ioI
Fosc (Q2 cycle) to Port input invalid
50
(I/O in hold time)
OS17 TioV2osH Port input valid to Fosc(Q2 cycle)
20
—
—
ns
(I/O in setup time)
OS18 TioR
OS19 TioF
Port output rise time(2)
—
—
40
15
72
32
ns
ns
VDD = 1.8V
VDD = 3.3-5.0V
Port output fall time(2)
—
—
28
15
55
30
VDD = 1.8V
VDD = 3.3-5.0V
OS20* Tinp
OS21* Tioc
INT pin input high or low time
25
25
—
—
—
—
ns
ns
Interrupt-on-change new input level
time
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
2: Includes OSC2 in CLKOUT mode.
FIGURE 25-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Start-Up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
31
34
34
I/O pins
Note 1: Asserted low.
DS41452B-page 298
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-8:
BROWN-OUT RESET TIMING AND CHARACTERISTICS
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
37
Reset
33(1)
(due to BOR)
Note 1: 64 ms delay only if PWRTE bit in the Configuration Word 1 is programmed to ‘0’.
2 ms delay if PWRTE = 0and VREGEN = 1.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 299
PIC16(L)F1516/7/8/9
TABLE 25-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TMCL
Characteristic
Min. Typ† Max. Units
Conditions
30
MCLR Pulse Width (low)
2
5
—
—
—
—
s VDD = 3.3-5V, -40°C to +85°C
s VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
10
16
27
ms VDD = 3.3V-5V,
1:16 Prescaler used
32
TOST
Oscillator Start-up Timer Period(1), (2)
—
1024
65
—
140
2.0
Tosc (Note 3)
33*
34*
TPWRT Power-up Timer Period, PWRTE = 0 40
ms
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
—
—
s
35
VBOR
Brown-out Reset Voltage
2.38
1.80
2.5
1.9
2.65
2.05
V
BORV=2.5V
BORV=1.9V
36*
37*
VHYST
Brown-out Reset Hysteresis
0
1
25
3
50
5
mV -40°C to +85°C
TBORDC Brown-out Reset DC Response
Time
s VDD VBOR
38
VLPBOR Low-Power Brown-out Reset
Voltage
TBD TBD TBD
V
LPBOR = 1
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Legend: TBD = To Be Determined
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2: By design.
3: Period of the slower clock.
4: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1 F and 0.01 F values in parallel are recommended.
DS41452B-page 300
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
TABLE 25-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
TT0H
Characteristic
T0CKI High Pulse Width
Min.
Typ†
Max.
Units
Conditions
40*
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
10
0.5 TCY + 20
10
41*
42*
TT0L
TT0P
T0CKI Low Pulse Width
T0CKI Period
Greater of:
20 or TCY + 40
N
ns N = prescale value
(2, 4, ..., 256)
45*
TT1H
T1CKI High Synchronous, No Prescaler
0.5 TCY + 20
15
—
—
—
—
ns
ns
Time
Synchronous,
with Prescaler
Asynchronous
30
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
46*
47*
TT1L
TT1P
T1CKI Low Synchronous, No Prescaler
0.5 TCY + 20
Time
Synchronous, with Prescaler
Asynchronous
15
30
T1CKI Input Synchronous
Period
Greater of:
30 or TCY + 40
N
ns N = prescale value
(1, 2, 4, 8)
Asynchronous
60
—
—
ns
48
FT1
Secondary Oscillator Input Frequency Range
(oscillator enabled by setting bit T1OSCEN)
32.4
32.768
33.1
kHz
49*
TCKEZTMR1 Delay from External Clock Edge to Timer
Increment
2 TOSC
—
7 TOSC
—
Timers in Sync
mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 301
PIC16(L)F1516/7/8/9
FIGURE 25-10:
CAPTURE/COMPARE/PWM TIMINGS (CCP)
CCP
(Capture mode)
CC01
CC02
CC03
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ† Max. Units
Conditions
CC01* TccL CCP Input Low Time
CC02* TccH CCP Input High Time
CC03* TccP CCP Input Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
20
0.5TCY + 20
20
3TCY + 40
N
N = prescale value (1, 4 or 16)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
TABLE 25-7: PIC16(L)F151X A/D CONVERTER (ADC) CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD01 NR
AD02 EIL
AD03 EDL
Resolution
—
—
—
—
—
—
10
±1.7
±1
bit
Integral Error
LSb VREF = 3.0V
Differential Error
LSb No missing codes
VREF = 3.0V
AD04 EOFF Offset Error
—
—
—
—
—
—
—
±2
±1.5
VDD
VREF
10
LSb VREF = 3.0V
LSb VREF = 3.0V
AD05 EGN Gain Error
AD06 VREF Reference Voltage(3)
1.8
VSS
—
V
V
VREF = (VREF+ minus VREF-) (NOTE 5)
AD07 VAIN Full-Scale Range
AD08 ZAIN Recommended Impedance of
Analog Voltage Source
k Can go higher if external 0.01F capacitor is
present on input pin.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Total Absolute Error includes integral, differential, offset and gain errors.
2: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
3: ADC VREF is from external VREF, VDD pin or FVREF, whichever is selected as reference input.
4: When ADC is off, it will not consume any current other than leakage current. The power-down current specification
includes any such leakage from the ADC module.
5: FVR voltage selected must be 2.048V or 4.096V.
DS41452B-page 302
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 25-8: PIC16(L)F151X A/D CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C TA +125°C
Param
Sym.
No.
Characteristic
Min.
Typ†
Max. Units
Conditions
AD130* TAD
A/D Clock Period
1.0
1.0
—
9.0
6.0
s
s
TOSC-based
ADCS<1:0> = 11(ADRC mode)
A/D Internal RC Oscillator
Period
1.6
AD131 TCNV Conversion Time (not including
Acquisition Time)(1)
—
—
11
—
—
TAD Set GO/DONE bit to conversion
complete
AD132* TACQ Acquisition Time
5.0
s
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: The ADRES register may be read on the following TCY cycle.
FIGURE 25-11:
PIC16(L)F151X A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
1 TCY
AD134
Q4
(TOSC/2(1)
)
AD131
AD130
A/D CLK
7
6
5
4
3
2
1
0
A/D Data
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 303
PIC16(L)F1516/7/8/9
FIGURE 25-12:
PIC16(L)F151X A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
AD134
Q4
(1)
(TOSC/2 + TCY
1 TCY
)
AD131
AD130
A/D CLK
A/D Data
7
6
5
3
2
1
0
4
NEW_DATA
1 TCY
OLD_DATA
ADRES
ADIF
GO
DONE
Sampling Stopped
AD132
Sample
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 25-9: PIC16(L)F151X LOW DROPOUT (LDO) REGULATOR CHARACTERISTICS:
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ†
Max. Units
Conditions
LD001
LD002
LDO Regulation Voltage
LDO External Capacitor
—
3.2
—
—
1
V
0.1
F
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 25-13:
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
CK
DT
US121
US121
US122
US120
Refer to Figure 25-4 for load conditions.
Note:
DS41452B-page 304
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
TABLE 25-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
Symbol
No.
Characteristic
Min.
Max.
Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
3.0-5.5V
1.8-5.5V
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
US121 TCKRF
Clock out rise time and fall time
(Master mode)
50
US122 TDTRF
Data-out rise time and fall time
45
50
FIGURE 25-14:
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
CK
DT
US125
US126
Note: Refer to Figure 25-4 for load conditions.
TABLE 25-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C TA +125°C
Param.
Symbol
No.
Characteristic
Min.
Max. Units
Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK (DT hold time)
10
15
—
—
ns
ns
US126 TCKL2DTL Data-hold after CK (DT hold time)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 305
PIC16(L)F1516/7/8/9
FIGURE 25-15:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SSx
SP70
SCKx
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCKx
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDOx
SDIx
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note: Refer to Figure 25-4 for load conditions.
FIGURE 25-16:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SSx
SP81
SCKx
(CKP = 0)
SP71
SP73
SP72
SP79
SCKx
(CKP = 1)
SP80
SP78
LSb
MSb
bit 6 - - - - - -1
SDOx
SDIx
SP75, SP76
bit 6 - - - -1
MSb In
SP74
Note: Refer to Figure 25-4 for load conditions.
LSb In
DS41452B-page 306
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-17:
SPI SLAVE MODE TIMING (CKE = 0)
SSx
SP70
SCKx
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SCKx
(CKP = 1)
SP78
LSb
SP80
MSb
SDOx
SDIx
bit 6 - - - - - -1
SP75, SP76
bit 6 - - - -1
SP77
MSb In
SP74
SP73
LSb In
Note: Refer to Figure 25-4 for load conditions.
FIGURE 25-18:
SPI SLAVE MODE TIMING (CKE = 1)
SP82
SP70
SSx
SP83
SCKx
(CKP = 0)
SP72
SP71
SCKx
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDOx
SDIx
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note: Refer to Figure 25-4 for load conditions.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 307
PIC16(L)F1516/7/8/9
TABLE 25-12: SPI MODE REQUIREMENTS
Param
No.
Symbol
Characteristic
Min.
Typ† Max. Units Conditions
SP70* TSSL2SCH, SSx to SCKx or SCKx input
TCY
—
—
ns
TSSL2SCL
SP71* TSCH
SP72* TSCL
SCKx input high time (Slave mode)
SCKx input low time (Slave mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
SP73* TDIV2SCH, Setup time of SDIx data input to SCKx edge
TDIV2SCL
SP74* TSCH2DIL, Hold time of SDIx data input to SCKx edge
TSCL2DIL
100
—
—
ns
SP75* TDOR
SDO data output rise time
3.0-5.5V
1.8-5.5V
—
—
—
10
—
—
—
—
—
Tcy
10
25
10
—
10
25
10
—
—
—
25
50
25
50
25
50
25
50
145
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP76* TDOF
SDOx data output fall time
SP77* TSSH2DOZ SSx to SDOx output high-impedance
SP78* TSCR
SCKx output rise time
(Master mode)
3.0-5.5V
1.8-5.5V
SP79* TSCF
SCKx output fall time (Master mode)
SP80* TSCH2DOV, SDOx data output valid after
TSCL2DOV SCKx edge
3.0-5.5V
1.8-5.5V
SP81* TDOV2SCH, SDOx data output setup to SCKx edge
TDOV2SCL
SP82* TSSL2DOV SDOx data output valid after SS edge
—
—
—
50
—
ns
ns
SP83* TSCH2SSH, SSx after SCKx edge
1.5TCY + 40
TSCL2SSH
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 25-19:
I2C™ BUS START/STOP BITS TIMING
SCLx
SP93
SP91
SP90
SP92
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 25-4 for load conditions.
DS41452B-page 308
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
FIGURE 25-20:
I2C™ BUS DATA TIMING
SP100
SP103
SP102
SP101
SCLx
SP90
SP106
SP107
SP92
SP91
SDAx
In
SP110
SP109
SP109
SDAx
Out
Note: Refer to Figure 25-4 for load conditions.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 309
PIC16(L)F1516/7/8/9
TABLE 25-13: I2C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min.
Max. Units
Conditions
SP100* THIGH
Clock high time
100 kHz mode
4.0
—
—
s
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
4.7
—
—
—
SP101* TLOW
Clock low time
100 kHz mode
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
SSP module
1.5TCY
—
—
—
ns
ns
SP102* TR
SP103* TF
SDAx and SCLx
rise time
100 kHz mode
400 kHz mode
1000
20 + 0.1CB 300
CB is specified to be from
10-400 pF
SDAx and SCLx fall 100 kHz mode
time
—
250
ns
ns
400 kHz mode
20 + 0.1CB 250
CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode
400 kHz mode
0
—
0.9
—
ns
s
ns
ns
ns
ns
s
s
0
SP107* TSU:DAT Data input setup
time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
—
(Note 2)
(Note 1)
—
SP109* TAA
Output valid from
clock
3500
—
—
SP110* TBUF
Bus free time
4.7
1.3
—
Time the bus must be free
before a new transmission
can start
—
SP111 CB
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C™ bus device can be used in a Standard mode (100 kHz) I2C bus system, but
the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does
not stretch the low period of the SCLx signal. If such a device does stretch the low period of the SCLx sig-
nal, it must output the next data bit to the SDAx line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according
to the Standard mode I2C bus specification), before the SCLx line is released.
DS41452B-page 310
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
26.0 DC AND AC
CHARACTERISTICS GRAPHS
AND CHARTS
Graphs and charts are not available at this time.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 311
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 312
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
27.1 MPLAB Integrated Development
Environment Software
27.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 313
PIC16(L)F1516/7/8/9
27.2 MPLAB C Compilers for Various
Device Families
27.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
27.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
27.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
27.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS41452B-page 314
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
27.7 MPLAB SIM Software Simulator
27.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
27.10 PICkit 3 In-Circuit Debugger/
Programmer and
27.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 315
PIC16(L)F1516/7/8/9
27.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
27.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
27.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS41452B-page 316
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
28.0 PACKAGING INFORMATION
28.1 Package Marking Information
28-Lead SOIC (.300”)
Example
e
3
PIC16F1516-E/SO
1048017
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SPDIP (.300”)
Example
e
3
PIC16F1516-E/SP
1048017
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead SSOP (.209”)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F1516
-E/SS
1048017
e
3
YYWWNNN
28-Lead UQFN (4x4x0.5 mm)
Example
XXXXX
XXXXXX
XXXXXX
YWWNNN
PIC16
F1516
e
3
E/MV
048017
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 317
PIC16(L)F1516/7/8/9
Package Marking Information (Continued)
40-Lead PDIP (.600”)
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
e
3
PIC16F1517-E/P
1048017
40-Lead UQFN (5x5x0.5 mm)
Example
PIN 1
PIC16
LF1517
e
3
-E/MV
1048017
44-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F1517
-E/PT
1048017
e
3
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS41452B-page 318
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
28.2 Package Details
The following sections give the technical details of the packages.
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ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢀꢤꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢤꢢꢁ
ꢨꢛꢝꢩ ꢨꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢪꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢫꢠꢬꢩ ꢫꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢪꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢿꢣꢤꢙꢨ
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 319
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41452B-page 320
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
ꢀꢁꢂꢃꢄꢅꢆꢇꢎꢥꢌꢒꢒꢞꢇꢈꢉꢅꢊꢋꢌꢍꢇꢦꢑꢅꢉꢇꢠꢒꢂꢃꢌꢒꢄꢇꢓꢎꢈꢔꢇꢕꢇꢧꢛꢛꢇꢏꢌꢉꢇꢜꢝꢆꢞꢇꢟꢎꢈꢦꢠꢈꢢ
ꢣꢝꢋꢄꢤ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢩꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
ꢯꢄꢃꢏꢇ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢱꢃꢑꢃꢏꢇ
ꢰꢲꢝꢷꢠꢛ
ꢲꢳꢢ
ꢙꢵ
ꢁꢀꢣꢣꢅꢨꢛꢝ
ꢸ
ꢢꢰꢲ
ꢢꢦꢴ
ꢲꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢲ
ꢌ
ꢦ
ꢪꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢸ
ꢁꢙꢣꢣ
ꢁꢀꢤꢣ
ꢸ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢨꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢺꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢱꢌꢄꢜꢏꢘ
ꢪꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢱꢌꢉꢋꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢯꢡꢡꢌꢐꢅꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢱ
ꢖ
ꢔꢀ
ꢔ
ꢌꢨ
ꢁꢀꢙꢣ
ꢁꢣꢀꢤ
ꢁꢙꢻꢣ
ꢁꢙꢥꢣ
ꢀꢁꢞꢥꢤ
ꢁꢀꢀꢣ
ꢁꢣꢣꢵ
ꢁꢣꢥꢣ
ꢁꢣꢀꢥ
ꢸ
ꢁꢀꢞꢤ
ꢸ
ꢁꢞꢀꢣ
ꢁꢙꢵꢤ
ꢀꢁꢞꢹꢤ
ꢁꢀꢞꢣ
ꢁꢣꢀꢣ
ꢁꢣꢤꢣ
ꢁꢣꢀꢵ
ꢸ
ꢁꢞꢞꢤ
ꢁꢙꢻꢤ
ꢀꢁꢥꢣꢣ
ꢁꢀꢤꢣ
ꢁꢣꢀꢤ
ꢁꢣꢶꢣ
ꢁꢣꢙꢙ
ꢁꢥꢞꢣ
ꢱꢕꢗꢌꢐꢅꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢫꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ
ꢣꢝꢋꢄꢊꢤ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꣀꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢤꢢꢁ
ꢨꢛꢝꢩ ꢨꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢪꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢪꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢿꢣꢶꢣꢨ
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 321
PIC16(L)F1516/7/8/9
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢨꢩꢌꢒꢥꢇꢎꢏꢅꢉꢉꢇꢐꢑꢋꢉꢌꢒꢄꢇꢓꢎꢎꢔꢇꢕꢇꢚꢙꢧꢛꢇꢏꢏꢇꢜꢝꢆꢞꢇꢟꢎꢎꢐꢈꢢ
ꢣꢝꢋꢄꢤ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢩꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
D
N
E
E1
1
2
b
NOTE 1
e
c
A2
A
φ
A1
L
L1
ꢯꢄꢃꢏꢇ
ꢢꢰꢱꢱꢰꢢꢠꢪꢠꢫꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢱꢃꢑꢃꢏꢇ
ꢢꢰꢲ
ꢲꢳꢢ
ꢢꢦꢴ
ꢲꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢲ
ꢌ
ꢙꢵ
ꢣꢁꢹꢤꢅꢨꢛꢝ
ꢳꢆꢌꢐꢉꢊꢊꢅꢷꢌꢃꢜꢘꢏ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅ
ꢳꢆꢌꢐꢉꢊꢊꢅꢺꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢱꢌꢄꢜꢏꢘ
ꢬꢕꢕꢏꢅꢱꢌꢄꢜꢏꢘ
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ
ꢱꢌꢉꢋꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ
ꢦ
ꢸ
ꢸ
ꢀꢁꢶꢤ
ꢸ
ꢶꢁꢵꢣ
ꢤꢁꢞꢣ
ꢀꢣꢁꢙꢣ
ꢣꢁꢶꢤ
ꢀꢁꢙꢤꢅꢫꢠꢬ
ꢸ
ꢙꢁꢣꢣ
ꢀꢁꢵꢤ
ꢸ
ꢵꢁꢙꢣ
ꢤꢁꢹꢣ
ꢀꢣꢁꢤꢣ
ꢣꢁꢻꢤ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢱ
ꢱꢀ
ꢖ
ꢀꢁꢹꢤ
ꢣꢁꢣꢤ
ꢶꢁꢥꢣ
ꢤꢁꢣꢣ
ꢻꢁꢻꢣ
ꢣꢁꢤꢤ
ꢣꢁꢣꢻ
ꢣꢾ
ꢣꢁꢙꢤ
ꢵꢾ
ꢀ
ꢥꢾ
ꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢔ
ꢣꢁꢙꢙ
ꢸ
ꢣꢁꢞꢵ
ꢣꢝꢋꢄꢊꢤ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢣꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢤꢢꢁ
ꢨꢛꢝꢩ ꢨꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢪꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢫꢠꢬꢩ ꢫꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢪꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢿꢣꢶꢞꢨ
DS41452B-page 322
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 323
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41452B-page 324
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 325
PIC16(L)F1516/7/8/9
ꢪꢛꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢦꢑꢅꢉꢇꢠꢒꢂꢃꢌꢒꢄꢇꢓꢈꢔꢇꢕꢇꢫꢛꢛꢇꢏꢌꢉꢇꢜꢝꢆꢞꢇꢟꢈꢦꢠꢈꢢ
ꢣꢝꢋꢄꢤ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢩꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
N
NOTE 1
E1
1 2 3
D
E
A2
A
L
c
b1
b
A1
e
eB
ꢯꢄꢃꢏꢇ
ꢰꢲꢝꢷꢠꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢱꢃꢑꢃꢏꢇ
ꢢꢰꢲ
ꢲꢳꢢ
ꢢꢦꢴ
ꢲꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
ꢂꢃꢏꢖꢘ
ꢲ
ꢌ
ꢥꢣ
ꢁꢀꢣꢣꢅꢨꢛꢝ
ꢪꢕꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢨꢉꢇꢌꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢛꢘꢕꢈꢊꢋꢌꢐꢅꢏꢕꢅꢛꢘꢕꢈꢊꢋꢌꢐꢅꢺꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢱꢌꢄꢜꢏꢘ
ꢪꢃꢡꢅꢏꢕꢅꢛꢌꢉꢏꢃꢄꢜꢅꢂꢊꢉꢄꢌ
ꢱꢌꢉꢋꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢯꢡꢡꢌꢐꢅꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢦ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢸ
ꢁꢙꢤꢣ
ꢁꢀꢻꢤ
ꢸ
ꢦꢙ
ꢦꢀ
ꢠ
ꢠꢀ
ꢟ
ꢱ
ꢖ
ꢔꢀ
ꢔ
ꢌꢨ
ꢁꢀꢙꢤ
ꢁꢣꢀꢤ
ꢁꢤꢻꢣ
ꢁꢥꢵꢤ
ꢀꢁꢻꢵꢣ
ꢁꢀꢀꢤ
ꢁꢣꢣꢵ
ꢁꢣꢞꢣ
ꢁꢣꢀꢥ
ꢸ
ꢁꢹꢙꢤ
ꢁꢤꢵꢣ
ꢙꢁꢣꢻꢤ
ꢁꢙꢣꢣ
ꢁꢣꢀꢤ
ꢁꢣꢶꢣ
ꢁꢣꢙꢞ
ꢁꢶꢣꢣ
ꢱꢕꢗꢌꢐꢅꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢫꢕꢗꢅꢛꢡꢉꢖꢃꢄꢜꢅꢅꢚ
ꢣꢝꢋꢄꢊꢤ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢚꢅꢛꢃꢜꢄꢃꢎꢃꢖꢉꢄꢏꢅꢝꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢁꢣꢀꢣꣀꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢤꢢꢁ
ꢨꢛꢝꢩ ꢨꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢪꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢪꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢿꢣꢀꢹꢨ
DS41452B-page 326
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 327
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS41452B-page 328
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 329
PIC16(L)F1516/7/8/9
ꢪꢪꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢬꢨꢌꢒꢇꢭꢑꢅꢆꢇꢮꢉꢅꢋꢯꢅꢍꢥꢇꢓꢈꢬꢔꢇꢕꢇꢰꢛꢱꢰꢛꢱꢰꢇꢏꢏꢇꢜꢝꢆꢞꢗꢇꢀꢙꢛꢛꢇꢏꢏꢇꢟꢬꢭꢮꢈꢢ
ꢣꢝꢋꢄꢤ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢩꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
D
D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
α
A
c
φ
A2
β
A1
L
L1
ꢯꢄꢃꢏꢇ
ꢢꢰꢱꢱꢰꢢꢠꢪꢠꢫꢛ
ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢅꢱꢃꢑꢃꢏꢇ
ꢢꢰꢲ
ꢲꢳꢢ
ꢥꢥ
ꢣꢁꢵꢣꢅꢨꢛꢝ
ꢸ
ꢀꢁꢣꢣ
ꢸ
ꢢꢦꢴ
ꢲꢈꢑꢔꢌꢐꢅꢕꢎꢅꢱꢌꢉꢋꢇ
ꢱꢌꢉꢋꢅꢂꢃꢏꢖꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢷꢌꢃꢜꢘꢏ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢛꢏꢉꢄꢋꢕꢎꢎꢅꢅ
ꢬꢕꢕꢏꢅꢱꢌꢄꢜꢏꢘ
ꢲ
ꢌ
ꢦ
ꢦꢙ
ꢦꢀ
ꢱ
ꢸ
ꢀꢁꢙꢣ
ꢀꢁꢣꢤ
ꢣꢁꢀꢤ
ꢣꢁꢶꢤ
ꢣꢁꢻꢤ
ꢣꢁꢣꢤ
ꢣꢁꢥꢤ
ꢣꢁꢹꢣ
ꢬꢕꢕꢏꢡꢐꢃꢄꢏ
ꢬꢕꢕꢏꢅꢦꢄꢜꢊꢌ
ꢱꢀ
ꢀ
ꢀꢁꢣꢣꢅꢫꢠꢬ
ꢞꢁꢤꢾ
ꢣꢾ
ꢶꢾ
ꢳꢆꢌꢐꢉꢊꢊꢅꢺꢃꢋꢏꢘ
ꢳꢆꢌꢐꢉꢊꢊꢅꢱꢌꢄꢜꢏꢘ
ꢠ
ꢟ
ꢠꢀ
ꢟꢀ
ꢖ
ꢀꢙꢁꢣꢣꢅꢨꢛꢝ
ꢀꢙꢁꢣꢣꢅꢨꢛꢝ
ꢀꢣꢁꢣꢣꢅꢨꢛꢝ
ꢀꢣꢁꢣꢣꢅꢨꢛꢝ
ꢸ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢺꢃꢋꢏꢘ
ꢢꢕꢊꢋꢌꢋꢅꢂꢉꢖꢭꢉꢜꢌꢅꢱꢌꢄꢜꢏꢘ
ꢱꢌꢉꢋꢅꢪꢘꢃꢖꢭꢄꢌꢇꢇ
ꢱꢌꢉꢋꢅꢺꢃꢋꢏꢘ
ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢪꢕꢡ
ꢢꢕꢊꢋꢅꢟꢐꢉꢎꢏꢅꢦꢄꢜꢊꢌꢅꢨꢕꢏꢏꢕꢑ
ꢣꢁꢣꢻ
ꢣꢁꢞꢣ
ꢀꢀꢾ
ꢣꢁꢙꢣ
ꢣꢁꢥꢤ
ꢀꢞꢾ
ꢔ
ꢁ
ꢣꢁꢞꢶ
ꢀꢙꢾ
ꢀꢙꢾ
ꢂ
ꢀꢀꢾ
ꢀꢞꢾ
ꢣꢝꢋꢄꢊꢤ
ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃꢇꢈꢉꢊꢅꢃꢄꢋꢌꢍꢅꢎꢌꢉꢏꢈꢐꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢓꢅꢔꢈꢏꢅꢑꢈꢇꢏꢅꢔꢌꢅꢊꢕꢖꢉꢏꢌꢋꢅꢗꢃꢏꢘꢃꢄꢅꢏꢘꢌꢅꢘꢉꢏꢖꢘꢌꢋꢅꢉꢐꢌꢉꢁ
ꢙꢁ ꢝꢘꢉꢑꢎꢌꢐꢇꢅꢉꢏꢅꢖꢕꢐꢄꢌꢐꢇꢅꢉꢐꢌꢅꢕꢡꢏꢃꢕꢄꢉꢊYꢅꢇꢃZꢌꢅꢑꢉꢒꢅꢆꢉꢐꢒꢁ
ꢞꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅꢟꢀꢅꢉꢄꢋꢅꢠꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅꢢꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢡꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅꢣꢁꢙꢤꢅꢑꢑꢅꢡꢌꢐꢅꢇꢃꢋꢌꢁ
ꢥꢁ ꢟꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢜꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢜꢅꢡꢌꢐꢅꢦꢛꢢꢠꢅꢧꢀꢥꢁꢤꢢꢁ
ꢨꢛꢝꢩ ꢨꢉꢇꢃꢖꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅꢪꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
ꢫꢠꢬꢩ ꢫꢌꢎꢌꢐꢌꢄꢖꢌꢅꢟꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅꢡꢈꢐꢡꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
ꢢꢃꢖꢐꢕꢖꢘꢃꢡ ꢪꢌꢖꢘꢄꢕꢊꢕꢜꢒ ꢟꢐꢉꢗꢃꢄꢜ ꢝꢣꢥꢿꢣꢶꢹꢨ
DS41452B-page 330
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
ꢪꢪꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢬꢨꢌꢒꢇꢭꢑꢅꢆꢇꢮꢉꢅꢋꢯꢅꢍꢥꢇꢓꢈꢬꢔꢇꢕꢇꢰꢛꢱꢰꢛꢱꢰꢇꢏꢏꢇꢜꢝꢆꢞꢗꢇꢀꢙꢛꢛꢇꢏꢏꢇꢟꢬꢭꢮꢈꢢ
ꢣꢝꢋꢄꢤ ꢬꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅꢡꢉꢖꢭꢉꢜꢌꢅꢋꢐꢉꢗꢃꢄꢜꢇꢓꢅꢡꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅꢢꢃꢖꢐꢕꢖꢘꢃꢡꢅꢂꢉꢖꢭꢉꢜꢃꢄꢜꢅꢛꢡꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏꢡꢩꢮꢮꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃꢡꢁꢖꢕꢑꢮꢡꢉꢖꢭꢉꢜꢃꢄꢜ
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 331
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 332
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
APPENDIX A: DATA SHEET
REVISION HISTORY
Revision A
Original release (12/2010)
Revision B
Initial public release of device family (05/2011)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 333
PIC16(L)F1516/7/8/9
NOTES:
DS41452B-page 334
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
INDEX
EUSART Receive..................................................... 238
EUSART Transmit.................................................... 237
External RC Mode ...................................................... 55
Fail-Safe Clock Monitor (FSCM)................................. 62
Generic I/O Port........................................................ 113
Interrupt Logic............................................................. 75
On-Chip Reset Circuit................................................. 67
PIC16C74..................................................................... 4
PIC16C74A................................................................... 4
Resonator Operation .................................................. 54
Timer0 ...................................................................... 155
Timer1 ...................................................................... 159
Timer1 Gate.............................................. 164, 165, 166
Timer2 ...................................................................... 171
Voltage Reference.................................................... 137
BORCON Register.............................................................. 69
BRA .................................................................................. 274
Break Character (12-bit) Transmit and Receive ............... 257
Brown-out Reset (BOR)...................................................... 69
Specifications ........................................................... 300
Timing and Characteristics....................................... 299
A
A/D
Specifications.................................................... 302, 303
Absolute Maximum Ratings .............................................. 283
AC Characteristics
Industrial and Extended ............................................ 296
Load Conditions........................................................ 295
ACKSTAT ......................................................................... 220
ACKSTAT Status Flag ...................................................... 220
ADC .................................................................................. 141
Acquisition Requirements ......................................... 151
Associated registers.................................................. 153
Block Diagram........................................................... 141
Calculating Acquisition Time..................................... 151
Channel Selection..................................................... 142
Configuration............................................................. 142
Configuring Interrupt ................................................. 146
Conversion Clock...................................................... 142
Conversion Procedure .............................................. 146
Internal Sampling Switch (RSS) IMPEDANCE .............. 151
Interrupts................................................................... 144
Operation .................................................................. 145
Operation During Sleep ............................................ 145
Port Configuration..................................................... 142
Reference Voltage (VREF)......................................... 142
Source Impedance.................................................... 151
Special Event Trigger................................................ 145
Starting an A/D Conversion ...................................... 144
ADCON0 Register....................................................... 34, 147
ADCON1 Register....................................................... 34, 148
ADDFSR ........................................................................... 273
ADDWFC .......................................................................... 273
ADRESH Register............................................................... 34
ADRESH Register (ADFM = 0)......................................... 149
ADRESH Register (ADFM = 1)......................................... 150
ADRESL Register ............................................................... 34
ADRESL Register (ADFM = 0).......................................... 149
ADRESL Register (ADFM = 1).......................................... 150
Alternate Pin Function....................................................... 114
Analog-to-Digital Converter. See ADC
C
C Compilers
MPLAB C18.............................................................. 314
CALL................................................................................. 275
CALLW ............................................................................. 275
Capture Module. See Capture/Compare/PWM(CCP)
Capture/Compare/PWM ................................................... 175
Capture/Compare/PWM (CCP) ........................................ 176
Associated Registers w/ PWM ................................. 183
Capture Mode........................................................... 176
CCPx Pin Configuration............................................ 176
Compare Mode......................................................... 178
CCPx Pin Configuration.................................... 178
Software Interrupt Mode........................... 176, 178
Special Event Trigger....................................... 178
Timer1 Mode Resource............................ 176, 178
Prescaler .................................................................. 176
PWM Mode
Duty Cycle ........................................................ 181
Effects of Reset................................................ 183
Example PWM Frequencies and
Resolutions, 20 MHZ................................ 182
Example PWM Frequencies and
ANSELA Register ............................................................. 117
ANSELB Register ............................................................. 121
ANSELC Register ............................................................. 124
ANSELD Register ............................................................. 127
ANSELE Register ............................................................. 130
APFCON Register....................................................... 35, 114
Assembler
Resolutions, 8 MHz .................................. 182
Operation in Sleep Mode.................................. 183
Resolution ........................................................ 182
System Clock Frequency Changes .................. 183
PWM Operation........................................................ 180
PWM Overview......................................................... 180
PWM Period ............................................................. 181
PWM Setup .............................................................. 181
Specifications ........................................................... 302
CCP. See Capture/Compare/PWM
CCP1CON Register............................................................ 36
CCPR1H Register............................................................... 36
CCPR1L Register ............................................................... 36
CCPxCON (CCPx) Register ............................................. 184
Clock Accuracy with Asynchronous Operation................. 246
Clock Sources
MPASM Assembler................................................... 314
B
BAUDCON Register.......................................................... 248
BF ............................................................................. 220, 222
BF Status Flag .......................................................... 220, 222
Block Diagrams
.............................................................................. 14, 20
(CCP) Capture Mode Operation ............................... 176
ADC .......................................................................... 141
ADC Transfer Function ............................................. 152
Analog Input Model................................................... 152
CCP PWM................................................................. 180
Clock Source............................................................... 52
Compare ................................................................... 178
Crystal Operation.................................................. 54, 55
External Modes........................................................... 53
EC ...................................................................... 53
HS ...................................................................... 53
2011 Microchip Technology Inc.
Preliminary
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PIC16(L)F1516/7/8/9
LP........................................................................53
OST.....................................................................54
RC.......................................................................55
XT .......................................................................53
Internal Modes ............................................................56
HFINTOSC..........................................................56
Internal Oscillator Clock Switch Timing...............57
LFINTOSC ..........................................................56
Clock Switching...................................................................59
Code Examples
A/D Conversion.........................................................146
Changing Between Capture Prescalers....................176
Initializing PORTA.....................................................113
Writing to Flash Program Memory ............................106
Comparators
High Baud Rate Select (BRGH Bit) .................. 249
Synchronous Master Mode............................... 258, 262
Associated Registers
Receive .................................................... 261
Transmit.................................................... 259
Reception ......................................................... 260
Transmission .................................................... 258
Synchronous Slave Mode
Associated Registers
Receive .................................................... 263
Transmit.................................................... 262
Reception ......................................................... 263
Transmission .................................................... 262
Extended Instruction Set
ADDFSR................................................................... 273
C2OUT as T1 Gate...................................................161
Compare Module. See Capture/Compare/PWM (CCP)
CONFIG1 Register..............................................................46
CONFIG2 Register..............................................................48
Core Function Register .......................................................33
Customer Change Notification Service .............................341
Customer Notification Service...........................................341
Customer Support.............................................................341
F
Fail-Safe Clock Monitor ...................................................... 62
Fail-Safe Condition Clearing....................................... 62
Fail-Safe Detection ..................................................... 62
Fail-Safe Operation..................................................... 62
Reset or Wake-up from Sleep .................................... 62
Firmware Instructions ....................................................... 269
Fixed Voltage Reference (FVR)........................................ 137
Associated Registers................................................ 138
Flash Program Memory ...................................................... 97
Associated Registers................................................ 112
Configuration Word w/ Flash Program Memory........ 112
Erasing ..................................................................... 101
Modifying .................................................................. 107
Write Verify............................................................... 109
Writing ...................................................................... 103
FSR Register ...................................................................... 33
FVRCON (Fixed Voltage Reference Control) Register..... 138
D
Data Memory.......................................................................24
DC and AC Characteristics ...............................................311
DC Characteristics
Extended and Industrial ............................................292
Industrial and Extended ............................................285
Development Support .......................................................313
Device Configuration...........................................................45
Code Protection ..........................................................49
Configuration Word.....................................................45
User ID..................................................................49, 50
Device ID Register ..............................................................50
Device Overview ........................................................... 13, 93
I
I2C Mode (MSSP)
Acknowledge Sequence Timing ............................... 224
Bus Collision
E
EEDATL Register..............................................................110
Effects of Reset
During a Repeated Start Condition................... 228
During a Stop Condition ................................... 229
Effects of a Reset ..................................................... 225
I2C Clock Rate w/BRG.............................................. 231
Master Mode
Operation.......................................................... 216
Reception ......................................................... 222
Start Condition Timing.............................. 218, 219
Transmission .................................................... 220
Multi-Master Communication, Bus Collision and
Arbitration ......................................................... 225
Multi-Master Mode.................................................... 225
Read/Write Bit Information (R/W Bit)........................ 201
Slave Mode
PWM mode ...............................................................183
Electrical Specifications ....................................................283
Enhanced Mid-range CPU ..................................................19
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART)...............................237
Errata ..................................................................................11
EUSART............................................................................237
Associated Registers
Baud Rate Generator........................................250
Asynchronous Mode .................................................239
12-bit Break Transmit and Receive...................257
Associated Registers
Receive.....................................................245
Transmit....................................................241
Auto-Wake-up on Break....................................255
Baud Rate Generator (BRG).............................249
Clock Accuracy .................................................246
Receiver............................................................242
Setting up 9-bit Mode with Address Detect.......244
Transmitter........................................................239
Baud Rate Generator (BRG)
Transmission .................................................... 206
Sleep Operation........................................................ 225
Stop Condition Timing .............................................. 224
INDF Register..................................................................... 33
Indirect Addressing............................................................. 41
Instruction Format............................................................. 270
Instruction Set................................................................... 269
ADDLW..................................................................... 273
ADDWF..................................................................... 273
ADDWFC.................................................................. 273
ANDLW..................................................................... 273
ANDWF..................................................................... 273
BRA .......................................................................... 274
Auto Baud Rate Detect .....................................254
Baud Rate Error, Calculating ............................249
Baud Rates, Asynchronous Modes...................251
Formulas...........................................................250
DS41452B-page 336
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2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
CALL......................................................................... 275
CALLW...................................................................... 275
LSLF ......................................................................... 277
LSRF......................................................................... 277
MOVF........................................................................ 277
MOVIW ..................................................................... 278
MOVLB ..................................................................... 278
MOVWI ..................................................................... 279
OPTION .................................................................... 279
RESET...................................................................... 279
SUBWFB................................................................... 281
TRIS.......................................................................... 282
BCF........................................................................... 274
BSF........................................................................... 274
BTFSC ...................................................................... 274
BTFSS ...................................................................... 274
CALL......................................................................... 275
CLRF......................................................................... 275
CLRW ....................................................................... 275
CLRWDT................................................................... 275
COMF ....................................................................... 275
DECF ........................................................................ 275
DECFSZ.................................................................... 276
GOTO ....................................................................... 276
INCF.......................................................................... 276
INCFSZ..................................................................... 276
IORLW ...................................................................... 276
IORWF...................................................................... 276
MOVLW .................................................................... 278
MOVWF .................................................................... 278
NOP .......................................................................... 279
RETFIE ..................................................................... 280
RETLW ..................................................................... 280
RETURN................................................................... 280
RLF ........................................................................... 280
RRF........................................................................... 281
SLEEP ...................................................................... 281
SUBLW ..................................................................... 281
SUBWF..................................................................... 281
SWAPF ..................................................................... 282
XORLW..................................................................... 282
XORWF..................................................................... 282
INTCON Register................................................................ 80
Internal Oscillator Block
Load Conditions................................................................ 295
Low-Power Brown-out Reset (LPBOR) .............................. 70
LSLF ................................................................................. 277
LSRF ................................................................................ 277
M
Master Synchronous Serial Port. See MSSP
MCLR ................................................................................. 70
Internal........................................................................ 70
Memory Organization ......................................................... 21
Data............................................................................ 24
Program...................................................................... 21
Microchip Internet Web Site.............................................. 341
MOVIW ............................................................................. 278
MOVLB ............................................................................. 278
MOVWI............................................................................. 279
MPLAB ASM30 Assembler, Linker, Librarian................... 314
MPLAB Integrated Development Environment Software.. 313
MPLAB PM3 Device Programmer .................................... 316
MPLAB REAL ICE In-Circuit Emulator System ................ 315
MPLINK Object Linker/MPLIB Object Librarian................ 314
MSSP ............................................................................... 185
I2C Mode .................................................................. 196
I2C Mode Operation.................................................. 198
SPI Mode.................................................................. 188
SSPBUF Register..................................................... 191
SSPSR Register....................................................... 191
O
OPCODE Field Descriptions............................................. 269
OPTION............................................................................ 279
OPTION_REG Register.................................................... 157
OSCCON Register.............................................................. 64
Oscillator
Associated Registers.................................................. 65
Oscillator Module................................................................ 51
ECH............................................................................ 51
ECL............................................................................. 51
ECM............................................................................ 51
HS............................................................................... 51
INTOSC...................................................................... 51
LP ............................................................................... 51
RC .............................................................................. 51
XT............................................................................... 51
Oscillator Parameters ....................................................... 297
Oscillator Specifications.................................................... 296
Oscillator Start-up Timer (OST)
INTOSC
Specifications.................................................... 297
Internal Sampling Switch (RSS) IMPEDANCE ...................... 151
Internet Address................................................................ 341
Interrupt-On-Change......................................................... 133
Associated Registers ................................................ 136
Interrupts............................................................................. 75
ADC .......................................................................... 146
Associated registers w/ Interrupts............................... 85
Configuration Word w/ Clock Sources ........................ 65
Configuration Word w/ LDO........................................ 91
TMR1 ........................................................................ 163
INTOSC Specifications ..................................................... 297
IOCAF Register................................................................. 135
IOCAN Register ................................................................ 135
IOCAP Register ................................................................ 135
Specifications ........................................................... 300
Oscillator Switching
Fail-Safe Clock Monitor .............................................. 62
Two-Speed Clock Start-up ......................................... 60
OSCSTAT Register ............................................................ 65
P
Packaging......................................................................... 317
Marking............................................................. 317, 318
PDIP Details ............................................................. 319
PCL and PCLATH............................................................... 20
PCL Register ...................................................................... 33
PCLATH Register ............................................................... 33
PCON Register............................................................. 34, 73
PIE1 Register ............................................................... 34, 81
PIE2 Register ............................................................... 34, 82
Pinout Descriptions
L
LATA Register........................................................... 117, 123
LATB Register................................................................... 120
LATD Register .................................................................. 126
LATE Register................................................................... 130
.................................................................................... 15
PIR1 Register ............................................................... 34, 83
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 337
PIC16(L)F1516/7/8/9
PIR2 Register................................................................34, 84
PMADR Registers...............................................................97
PMADRH Registers ............................................................97
PMADRL Register.............................................................110
PMADRL Registers.............................................................97
PMCON1 Register ...................................................... 97, 111
PMCON2 Register ...................................................... 97, 112
PMDATH Register.............................................................110
PORTA..............................................................................115
ANSELA Register .....................................................115
Associated Registers ................................................118
Configuration Word w/ PORTA.................................118
PORTA Register ................................................... 34, 35
Specifications............................................................298
PORTA Register ...............................................................116
PORTB..............................................................................119
ANSELB Register .....................................................119
Associated Registers ................................................121
PORTB Register ................................................... 34, 35
PORTB Register ...............................................................120
PORTC..............................................................................122
ANSELC Register .....................................................122
Associated Registers ................................................124
PORTC Register................................................... 34, 35
PORTC Register ...............................................................123
PORTD..............................................................................125
ANSELD Register .....................................................125
Associated Registers ................................................127
PORTD Register................................................... 34, 35
PORTD Register ...............................................................126
PORTE..............................................................................128
ANSELE Register .....................................................128
Associated Registers ................................................131
Configuration Word w/PORTE..................................131
PORTE Register ................................................... 34, 35
PORTE Register ...............................................................129
Power-Down Mode (Sleep).................................................87
Associated Registers ..................................................90
Power-on Reset ..................................................................68
Power-up Time-out Sequence ............................................70
Power-up Timer (PWRT).....................................................68
Specifications............................................................300
PR2 Register.......................................................................34
Precision Internal Oscillator Parameters...........................297
Program Memory ................................................................21
....................................................................................22
Map and Stack (PIC12F/LF1840) ......................... 21, 22
Programming, Device Instructions ....................................269
ANSELE (PORTE Analog Select)............................. 130
APFCON (Alternate Pin Function Control) ............... 114
BAUDCON (Baud Rate Control)............................... 248
BORCON Brown-out Reset Control) .......................... 69
CCPxCON (CCPx Control)....................................... 184
Configuration Word 1.................................................. 46
Configuration Word 2.................................................. 48
Core Function, Summary............................................ 33
Device ID .................................................................... 50
EEDATL (EEPROM Data)........................................ 110
FVRCON................................................................... 138
INTCON (Interrupt Control)......................................... 80
IOCAF (Interrupt-on-Change PORTA Flag).............. 135
IOCAN (Interrupt-on-Change PORTA
Negative Edge)................................................. 135
IOCAP (Interrupt-on-Change PORTA
Positive Edge) .................................................. 135
LATA (Data Latch PORTA)....................................... 117
LATB (Data Latch PORTB)....................................... 120
LATC (Data Latch PORTC) ...................................... 123
LATD (Data Latch PORTD) ...................................... 126
LATE (Data Latch PORTE)....................................... 130
OPTION_REG (OPTION)......................................... 157
OSCCON (Oscillator Control)..................................... 64
OSCSTAT (Oscillator Status) ..................................... 65
PCON (Power Control) ............................................... 73
PIE1 (Peripheral Interrupt Enable 1)........................... 81
PIE2 (Peripheral Interrupt Enable 2)........................... 82
PIR1 (Peripheral Interrupt Register 1) ........................ 83
PIR2 (Peripheral Interrupt Request 2) ........................ 84
PMADRL (Program Memory Address) ..................... 110
PMCON1 (Program Memory Control 1).................... 111
PMCON2 (Program Memory Control 2).................... 112
PMDATH (Program Memory Data)........................... 110
PORTA ..................................................................... 116
PORTB ..................................................................... 120
PORTC ..................................................................... 123
PORTD ..................................................................... 126
PORTE ..................................................................... 129
RCREG..................................................................... 254
RCSTA (Receive Status and Control) ...................... 247
SPBRGH .................................................................. 249
SPBRGL................................................................... 249
Special Function, Summary........................................ 34
SSPADD (MSSP Address and Baud Rate,
I2C Mode) ......................................................... 236
SSPCON1 (MSSP Control 1) ................................... 233
SSPCON2 (SSP Control 2) ...................................... 234
SSPCON3 (SSP Control 3) ...................................... 235
SSPMSK (SSP Mask)............................................... 236
SSPSTAT (SSP Status)............................................ 232
STATUS ..................................................................... 25
T1CON (Timer1 Control) .......................................... 167
T1GCON (Timer1 Gate Control)............................... 168
T2CON ..................................................................... 173
TRISA (Tri-State PORTA)......................................... 116
TRISB (Tri-State PORTB)......................................... 120
TRISC (Tri-State PORTC) ........................................ 123
TRISD (Tri-State PORTD) ........................................ 126
TRISE (Tri-State PORTE)......................................... 129
TXSTA (Transmit Status and Control)...................... 246
VREGCON (Voltage Regulator Control)..................... 89
WDTCON (Watchdog Timer Control) ......................... 95
WPUB (Weak Pull-up PORTB)................................. 121
RESET.............................................................................. 279
R
RCREG .............................................................................244
RCREG Register.................................................................35
RCSTA Register.......................................................... 35, 247
Reader Response .............................................................342
Read-Modify-Write Operations..........................................269
Registers
ADCON0 (ADC Control 0) ........................................147
ADCON1 (ADC Control 1) ........................................148
ADRESH (ADC Result High) with ADFM = 0)...........149
ADRESH (ADC Result High) with ADFM = 1)...........150
ADRESL (ADC Result Low) with ADFM = 0)............149
ADRESL (ADC Result Low) with ADFM = 1)............150
ANSELA (PORTA Analog Select).............................117
ANSELB (PORTB Analog Select).............................121
ANSELC (PORTC Analog Select) ............................124
ANSELD (PORTD Analog Select) ............................127
DS41452B-page 338
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
Reset................................................................................... 67
Reset Instruction................................................................. 70
Resets................................................................................. 67
Associated Registers .................................................. 74
Revision History ................................................................ 333
T1CON ............................................................. 167
T1GCON........................................................... 168
Timer2
T2CON ............................................................. 173
Timing Diagrams
A/D Conversion ........................................................ 303
A/D Conversion (Sleep Mode).................................. 304
Acknowledge Sequence........................................... 224
Asynchronous Reception.......................................... 244
Asynchronous Transmission .................................... 240
Asynchronous Transmission (Back to Back)............ 241
Auto Wake-up Bit (WUE) During Normal Operation. 256
Auto Wake-up Bit (WUE) During Sleep.................... 256
Automatic Baud Rate Calibration ............................. 254
Baud Rate Generator with Clock Arbitration............. 217
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 227
Brown-out Reset (BOR)............................................ 299
Brown-out Reset Situations........................................ 69
Bus Collision During a Repeated Start Condition
(Case 1)............................................................ 228
Bus Collision During a Repeated Start Condition
S
Software Simulator (MPLAB SIM)..................................... 315
SPBRG Register ................................................................. 35
SPBRGH Register ............................................................ 249
SPBRGL Register............................................................. 249
Special Event Trigger........................................................ 145
Special Function Registers (SFRs)..................................... 34
SPI Mode (MSSP)
Associated Registers ................................................ 195
SPI Clock .................................................................. 191
SSPADD Register....................................................... 36, 236
SSPBUF Register ............................................................... 36
SSPCON Register .............................................................. 36
SSPCON1 Register .......................................................... 233
SSPCON2 Register .......................................................... 234
SSPCON3 Register .......................................................... 235
SSPMSK Register............................................................. 236
SSPOV.............................................................................. 222
SSPOV Status Flag .......................................................... 222
SSPSTAT Register ..................................................... 36, 232
R/W Bit...................................................................... 201
Stack................................................................................... 39
Accessing.................................................................... 39
Reset........................................................................... 41
Stack Overflow/Underflow................................................... 70
STATUS Register ............................................................... 25
SUBWFB........................................................................... 281
(Case 2)............................................................ 228
Bus Collision During a Start Condition (SCL = 0)..... 227
Bus Collision During a Stop Condition (Case 1)....... 229
Bus Collision During a Stop Condition (Case 2)....... 229
Bus Collision During Start Condition (SDA only)...... 226
Bus Collision for Transmit and Acknowledge ........... 225
Capture/Compare/PWM (CCP) ................................ 302
CLKOUT and I/O ...................................................... 297
Clock Synchronization.............................................. 214
Clock Timing............................................................. 296
Fail-Safe Clock Monitor (FSCM)................................. 63
First Start Bit Timing................................................. 218
I2C Bus Data............................................................. 309
I2C Bus Start/Stop Bits ............................................. 308
I2C Master Mode (7 or 10-Bit Transmission)............ 221
I2C Master Mode (7-Bit Reception) .......................... 223
I2C Stop Condition Receive or Transmit Mode......... 224
INT Pin Interrupt ......................................................... 78
Internal Oscillator Switch Timing ................................ 58
Repeat Start Condition ............................................. 219
Reset Start-up Sequence ........................................... 71
Reset, WDT, OST and Power-up Timer................... 298
Send Break Character Sequence............................. 257
SPI Master Mode (CKE = 1, SMP = 1)..................... 306
SPI Mode (Master Mode) ......................................... 191
SPI Slave Mode (CKE = 0)....................................... 307
SPI Slave Mode (CKE = 1)....................................... 307
Synchronous Reception (Master Mode, SREN)....... 261
Synchronous Transmission ...................................... 259
Synchronous Transmission (Through TXEN)........... 259
Timer0 and Timer1 External Clock........................... 301
Timer1 Incrementing Edge ....................................... 163
Two Speed Start-up.................................................... 61
USART Synchronous Receive (Master/Slave)......... 305
USART Synchronous Transmission (Master/Slave). 304
Wake-up from Interrupt............................................... 88
Timing Parameter Symbology .......................................... 295
Timing Requirements
T
T1CON Register ......................................................... 34, 167
T1GCON Register............................................................. 168
T2CON (Timer2) Register................................................. 173
T2CON Register ................................................................. 34
Temperature Indicator Module.......................................... 139
Thermal Considerations.................................................... 294
Timer0............................................................................... 155
Associated Registers ................................................ 157
Operation .................................................................. 155
Specifications............................................................ 301
Timer1............................................................................... 159
Associated registers.................................................. 169
Asynchronous Counter Mode ................................... 161
Reading and Writing ......................................... 161
Clock Source Selection............................................. 160
Interrupt..................................................................... 163
Operation .................................................................. 160
Operation During Sleep ............................................ 163
Prescaler................................................................... 161
Secondary Oscillator................................................. 161
Specifications............................................................ 301
Timer1 Gate
Selecting Source............................................... 161
TMR1H Register ....................................................... 159
TMR1L Register........................................................ 159
Timer2............................................................................... 171
Associated registers.................................................. 174
Timer2/4/6
I2C Bus Data............................................................. 310
SPI Mode.................................................................. 308
TMR0 Register.................................................................... 34
TMR1H Register................................................................. 34
TMR1L Register.................................................................. 34
Associated registers.................................................. 174
Timers
Timer1
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 339
PIC16(L)F1516/7/8/9
TMR2 Register....................................................................34
TRIS..................................................................................282
TRISA Register ........................................................... 34, 116
TRISB................................................................................119
TRISB Register ........................................................... 34, 120
TRISC ...............................................................................122
TRISC Register........................................................... 34, 123
TRISD ...............................................................................125
TRISD Register........................................................... 34, 126
TRISE................................................................................128
TRISE Register ........................................................... 34, 129
Two-Speed Clock Start-up Mode........................................60
TXREG..............................................................................239
TXREG Register .................................................................35
TXSTA Register .......................................................... 35, 246
BRGH Bit ..................................................................249
U
USART
Synchronous Master Mode
Requirements, Synchronous Receive...............305
Requirements, Synchronous Transmission ......305
Timing Diagram, Synchronous Receive............305
Timing Diagram, Synchronous Transmission ...304
V
VREF. SEE ADC Reference Voltage
VREGCON Register............................................................89
W
Wake-up on Break ............................................................255
Wake-up Using Interrupts ...................................................88
Watchdog Timer (WDT) ......................................................70
Associated Registers ..................................................96
Configuration Word w/ Watchdog Timer.....................96
Modes .........................................................................94
Specifications............................................................300
WCOL .......................................................217, 220, 222, 224
WCOL Status Flag ....................................217, 220, 222, 224
WDTCON Register..............................................................95
WPUB Register.................................................................121
Write Protection...................................................................49
WWW Address..................................................................341
WWW, On-Line Support......................................................11
DS41452B-page 340
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
THE MICROCHIP WEB SITE
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Preliminary
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FAX: (______) _________ - _________
Literature Number: DS41452B
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Device: PIC16(L)F1516/7/8/9
Questions:
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2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
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DS41452B-page 342
Preliminary
2011 Microchip Technology Inc.
PIC16(L)F1516/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
PART NO.
X
/XX
XXX
-
Examples:
Device Tape and Reel
Option
Temperature
Range
Package
Pattern
a)
PIC16F1516T - I/MV 301
Tape and Reel,
Industrial temperature,
UQFN package,
QTP pattern #301
b)
c)
PIC16F1519 - I/P
Industrial temperature
PDIP package
Device:
PIC16F1516, PIC16LF1516
PIC16F1517, PIC16LF1517
PIC16F1518, PIC16LF1518
PIC16F1519, PIC16LF1519
PIC16F1518 - E/SS
Extended temperature,
SSOP package
Tape and Reel
Option:
Blank = Standard packaging (tube or tray)
T
= Tape and Reel(1)
Temperature
Range:
I
E
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
Pattern:
MV
P
PT
SO
SP
SS
=
=
=
=
=
=
Ultra Thin Quad Flat, no lead (UQFN)
Plastic DIP (PDIP)
TQFP
SOIC
Skinny Plastic DIP (SPDIP)
SSOP
QTP, SQTP, Code or Special Requirements
(blank otherwise)
2011 Microchip Technology Inc.
Preliminary
DS41452B-page 343
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Web Address:
www.microchip.com
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3180
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Fax: 886-7-330-9305
Los Angeles
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Toronto
Mississauga, Ontario,
Canada
China - Xiamen
Tel: 905-673-0699
Fax: 905-673-6509
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
05/02/11
DS41452B-page 344
Preliminary
2011 Microchip Technology Inc.
相关型号:
PIC16F1517-I/MV
8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQCC40, 5 X 5 MM, 0.50 MM HEIGHT, LEAD FREE, PLASTIC, UQFN-40
MICROCHIP
PIC16F1517-I/P
8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDIP40, 0.600 INCH, LEAD FREE, PLASTIC, DIP-40
MICROCHIP
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