PIC16F15245 [MICROCHIP]
PIC16F15213/14/23/24/43/44 Full-Featured 8/14/20-Pin Microcontrollers;
| 型号： | PIC16F15245 |
| 厂家： | 
MICROCHIP |
| 描述： | PIC16F15213/14/23/24/43/44 Full-Featured 8/14/20-Pin Microcontrollers 微控制器 |
| 文件： | 总420页 (文件大小：7227K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F15213/14/23/24/43/44
PIC16F15213/14/23/24/43/44 Full-Featured 8/14/20-Pin
Microcontrollers
Introduction
The PIC16F152 microcontroller family is available in 8/14/16/20/28/40/44-pin packages for cost-sensitive sensor and
real-time control applications. The PIC16F152 family’s simplified feature set includes a 10-bit Analog-to-Digital
Converter (ADC), Peripheral Pin Select (PPS), digital communication peripherals, timers, and waveform generators.
This microcontroller family also provides memory features, such as the Memory Access Partition (MAP) to support
users in data protection and bootloader applications, and a Device Information Area (DIA), which stores Fixed
Voltage Reference (FVR) offset values to help improve ADC accuracy.
PIC16F152 Family Types
Table 1.ꢀ Devices included in this data sheet
PIC16F15213
PIC16F15214
PIC16F15223
PIC16F15224
PIC16F15243
PIC16F15244
3.5k
7k
256
512
256
512
256
512
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
6/Y
6/Y
1/2
1/2
1/2
1/2
1/2
1/2
2/2
2/2
2/2
2/2
2/2
2/2
5/2
5/2
1
1
1
1
1
1
1
1
1
1
1
1
N
N
Y
Y
Y
Y
1
1
1
1
1
1
6
Y
Y
Y
Y
Y
Y
6
3.5k
7k
12/Y
12/Y
18/Y
18/Y
9/2
12
12
18
18
9/2
3.5k
7k
12/2
12/2
DS40002195A-page 1
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Table 2.ꢀ Devices not included in this data sheet
PIC16F15225
PIC16F15245
PIC16F15254
PIC16F15255
PIC16F15256
PIC16F15274
PIC16F15275
PIC16F15276
14k
14k
7k
1024
1024
512
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
Y/Y
12/Y
18/Y
25/Y
25/Y
25/Y
36/Y
36/Y
36/Y
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
2/2
9/2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
1
1
1
1
1
1
1
1
12
18
25
25
25
36
36
36
Y
Y
Y
Y
Y
Y
Y
Y
12/2
17/2
17/2
17/2
28/2
28/2
28/2
14k
28k
7k
1024
2048
512
14k
28k
1024
2048
Note:ꢀ
1. Total I/O count includes one pin (MCLR) that is input-only.
2. Timer0 can be configured as either an 8 or 16-bit timer.
Core Features
•
•
C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 32 MHz clock input
– 125 ns minimum instruction time
16-Level Deep Hardware Stack
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
•
•
•
•
•
Watchdog Timer (WDT)
Memory
•
•
•
Up to 28 KB of Program Flash Memory
Up to 2 KB of Data SRAM Memory
Memory Access Partition (MAP): The Program Flash Memory can be partitioned into:
– Application Block
– Boot Block
– Storage Area Flash (SAF) Block
•
•
Programmable Code Protection and Write Protection
Device Information Area (DIA) Stores:
– Fixed Voltage Reference (FVR) measurement data
– Microchip unique identifier
•
Device Characteristics Area (DCI) Stores:
DS40002195A-page 2
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
– Program/erase row sizes
– Pin count details
•
Direct, Indirect, and Relative Addressing Modes
Operating Characteristics
•
Operating Voltage Range:
– 1.8V to 5.5V
•
Temperature Range:
– Industrial: -40°C to 85°C
– Extended: -40°C to 125°C
Power-Saving Functionality
•
Sleep:
– Reduce device power consumption
– Reduce system electrical noise while performing ADC conversions
•
Low-Power Mode Features:
– Sleep:
•
•
< 900nA typical @ 3V/25°C (WDT enabled)
< 600nA typical @ 3V/25°C (WDT disabled)
– Operating Current:
•
•
48µA typical @ 32 kHz, 3V/25°C
< 1mA typical @ 4 MHz, 5V/25°C
Digital Peripherals
•
Two Capture/Compare/PWM (CCP) modules:
– 16-bit resolution for Capture/Compare modes
– 10-bit resolution for PWM mode
•
Two Pulse-Width Modulators (PWM):
– 10-bit resolution
– Independent pulse outputs
•
•
•
•
One Configurable 8/16-Bit Timer (TMR0)
One 16-Bit Timer (TMR1) with Gate Control
One 8-Bit Timer (TMR2) with Hardware Limit Timer (HLT)
One Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART):
– RS-232, RS-485, LIN compatible
– Auto-wake-up on Start
•
One Master Synchronous Serial Port (MSSP):
– Serial Peripheral Interface (SPI) mode
•
Slave Select Synchronization
– Inter-Integrated Circuit (I2C) mode
7/10-bit addressing modes
•
•
•
Peripheral Pin Select (PPS):
– Enables pin mapping of digital I/O
Device I/O Port Features:
– Up to 35 I/O pins
– 1 input-only pin
DS40002195A-page 3
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
– Individual I/O direction, open-drain, input threshold, slew rate, and weak pull-up control
– Interrupt-on-Change (IOC) on all pins
– One External Interrupt pin
Analog Peripherals
•
Analog-to-Digital Converter (ADC):
– 10-bit resolution
– Up to 28 external input channels
– Two internal input channels
– Internal ADC oscillator (ADCRC)
– Operates in Sleep
– Selectable Auto-Conversion Trigger sources
Fixed Voltage Reference (FVR):
– Selectable 1.024V, 2.048V, and 4.096V output levels
– Internally connected to ADC
•
Clocking Structure
•
High-Precision Internal Oscillator Block (HFINTOSC):
– Selectable frequencies up to 32 MHz
– ±2% at calibration
•
•
Internal 31 kHz Oscillator (LFINTOSC)
External High-Frequency Clock Input:
– Two External Clock (EC) power modes
Programming/Debug Features
™
™
•
•
•
In-Circuit Serial Programming (ICSP ) via Two Pins
In-Circuit Debug (ICD) with One Breakpoint via Two Pins
Debug Integrated On-Chip
DS40002195A-page 4
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Block Diagram
Figure 1.ꢀPIC16F15213/14/23/24/43/44 Block Diagram
Ports
PORTA
PORTB
PORTC
PPS Module
Peripherals
Memory
Data Memory
(RAM)
Data Bus
MSSP1
Timers
CCP
EUSART
ADC
Program
Flash Memory
PWM
Instruction Bus
FVR
Program, Debug and
Supervisory Modules
Single-Supply
Programming
In-Circuit
Debugger
MCLR
Power-up
Timer
Brown-out
Reset
CPU
Power-on
Reset
WDT
Oscillator and Clock
HFINTOSC
with
Active Clock
Tuning
OSC1
ECIN
Precision Band Gap Reference
EXTOSC
LFINTOSC
DS40002195A-page 5
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Table of Contents
Introduction.....................................................................................................................................................1
PIC16F152 Family Types...............................................................................................................................1
Core Features................................................................................................................................................ 2
Memory................................................................................................................................................... 2
Operating Characteristics........................................................................................................................3
Power-Saving Functionality.....................................................................................................................3
Digital Peripherals...................................................................................................................................3
Analog Peripherals..................................................................................................................................4
Clocking Structure...................................................................................................................................4
Programming/Debug Features................................................................................................................4
Block Diagram.........................................................................................................................................5
1. Packages.............................................................................................................................................. 12
2. Pin Diagrams.........................................................................................................................................13
3. Pin Allocation Tables.............................................................................................................................15
4. Guidelines for Getting Started with PIC16F152 Microcontrollers..........................................................18
4.1. Basic Connection Requirements................................................................................................18
4.2. Power Supply Pins..................................................................................................................... 18
4.3. Master Clear (MCLR) Pin...........................................................................................................19
4.4. In-Circuit Serial Programming™ (ICSP™) Pins............................................................................19
4.5. Unused I/Os............................................................................................................................... 20
5. Register and Bit Naming Conventions.................................................................................................. 21
5.1. Register Names..........................................................................................................................21
5.2. Bit Names...................................................................................................................................21
5.3. Register and Bit Naming Exceptions..........................................................................................22
6. Register Legend....................................................................................................................................23
7. Enhanced Mid-Range CPU...................................................................................................................24
7.1. Automatic Interrupt Context Saving............................................................................................24
7.2. 16-Level Stack with Overflow and Underflow.............................................................................25
7.3. File Select Registers.................................................................................................................. 25
7.4. Instruction Set............................................................................................................................ 25
8. Device Configuration.............................................................................................................................26
8.1. Configuration Words...................................................................................................................26
8.2. Code Protection..........................................................................................................................26
8.3. Write Protection..........................................................................................................................26
8.4. User ID....................................................................................................................................... 26
8.5. Device ID and Revision ID......................................................................................................... 26
8.6. Register Definitions: Configuration Settings...............................................................................26
8.7. Register Definitions: Device ID and Revision ID........................................................................ 33
DS40002195A-page 6
Preliminary Datasheet
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9. Memory Organization............................................................................................................................36
9.1. Program Memory Organization.................................................................................................. 36
9.2. Data Memory Organization........................................................................................................ 42
9.3. STATUS Register....................................................................................................................... 48
9.4. PCL and PCLATH...................................................................................................................... 49
9.5. Stack.......................................................................................................................................... 50
9.6. Indirect Addressing.....................................................................................................................53
9.7. Register Definitions: Memory Organization................................................................................55
9.8. Register Summary: Memory Organization................................................................................. 65
10. Resets...................................................................................................................................................66
10.1. Power-on Reset (POR).............................................................................................................. 66
10.2. Brown-out Reset (BOR)............................................................................................................. 67
10.3. MCLR Reset...............................................................................................................................68
10.4. Watchdog Timer (WDT) Reset................................................................................................... 69
10.5. RESETInstruction.......................................................................................................................69
10.6. Stack Overflow/Underflow Reset................................................................................................69
10.7. Power-up Timer (PWRT)............................................................................................................69
10.8. Start-up Sequence..................................................................................................................... 69
10.9. Memory Execution Violation.......................................................................................................70
10.10. Determining the Cause of a Reset.............................................................................................70
10.11. Power Control (PCONx) Register...............................................................................................72
10.12. Register Definitions: Power Control........................................................................................... 72
10.13. Register Summary: Power Control.............................................................................................77
11. OSC - Oscillator Module....................................................................................................................... 78
11.1. Oscillator Module Overview........................................................................................................78
11.2. Clock Source Types................................................................................................................... 79
11.3. Register Definitions: Oscillator Control.......................................................................................81
11.4. Register Summary: Oscillator Control........................................................................................87
12. Interrupts...............................................................................................................................................88
12.1. INTCON Register....................................................................................................................... 88
12.2. PIE Registers............................................................................................................................. 88
12.3. PIR Registers............................................................................................................................. 88
12.4. Operation....................................................................................................................................88
12.5. Interrupt Latency........................................................................................................................ 89
12.6. Interrupts During Sleep.............................................................................................................. 90
12.7. INT Pin....................................................................................................................................... 90
12.8. Automatic Context Saving..........................................................................................................90
12.9. Register Definitions: Interrupt Control........................................................................................ 91
12.10. Register Summary: Interrupt Control....................................................................................... 100
13. Sleep Mode.........................................................................................................................................101
13.1. Sleep Mode Operation............................................................................................................. 101
14. WDT - Watchdog Timer.......................................................................................................................103
14.1. Selectable Clock Sources........................................................................................................ 103
14.2. WDT Operating Modes.............................................................................................................103
DS40002195A-page 7
Preliminary Datasheet
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14.3. WDT Time-out Period...............................................................................................................104
14.4. Clearing the WDT.....................................................................................................................104
14.5. WDT Operation During Sleep...................................................................................................104
14.6. Register Definitions: WDT Control........................................................................................... 104
14.7. Register Summary - WDT Control............................................................................................106
15. NVM - Nonvolatile Memory Control ....................................................................................................107
15.1. Program Flash Memory............................................................................................................107
15.2. FSR and INDF Access............................................................................................................. 108
15.3. NVMREG Access.....................................................................................................................108
15.4. Register Definitions: Nonvolatile Memory Control....................................................................121
15.5. Register Summary: NVM Control.............................................................................................127
16. I/O Ports..............................................................................................................................................128
16.1. Overview.................................................................................................................................. 128
16.2. PORTx - Data Register............................................................................................................ 128
16.3. LATx - Output Latch................................................................................................................. 129
16.4. TRISx - Direction Control......................................................................................................... 130
16.5. ANSELx - Analog Control.........................................................................................................130
16.6. WPUx - Weak Pull-Up Control................................................................................................. 130
16.7. INLVLx - Input Threshold Control.............................................................................................130
16.8. SLRCONx - Slew Rate Control................................................................................................ 130
16.9. ODCONx - Open-Drain Control................................................................................................131
16.10. Edge Selectable Interrupt-on-Change......................................................................................131
16.11. I2C Pad Control........................................................................................................................ 131
16.12. I/O Priorities............................................................................................................................. 131
16.13. MCLR/VPP/RA3 Pin..................................................................................................................132
16.14. Register Definitions: Port Control.............................................................................................132
16.15. Register Summary - IO Ports...................................................................................................142
17. IOC - Interrupt-on-Change.................................................................................................................. 143
17.1. Overview.................................................................................................................................. 143
17.2. Enabling the Module.................................................................................................................143
17.3. Individual Pin Configuration......................................................................................................144
17.4. Interrupt Flags.......................................................................................................................... 144
17.5. Clearing Interrupt Flags............................................................................................................144
17.6. Operation in Sleep....................................................................................................................144
17.7. Register Definitions: Interrupt-on-Change Control................................................................... 144
17.8. Register Summary: Interrupt-on-Change................................................................................. 148
18. PPS - Peripheral Pin Select Module................................................................................................... 149
18.1. Overview.................................................................................................................................. 149
18.2. PPS Inputs............................................................................................................................... 149
18.3. PPS Outputs.............................................................................................................................150
18.4. Bidirectional Pins......................................................................................................................151
18.5. PPS Lock..................................................................................................................................151
18.6. Operation During Sleep............................................................................................................152
18.7. Effects of a Reset.....................................................................................................................152
18.8. Register Definitions: Peripheral Pin Select (PPS)....................................................................152
DS40002195A-page 8
Preliminary Datasheet
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PIC16F15213/14/23/24/43/44
18.9. Register Summary: Peripheral Pin Select Module................................................................... 156
19. TMR0 - Timer0 Module....................................................................................................................... 157
19.1. Timer0 Operation......................................................................................................................157
19.2. Clock Selection.........................................................................................................................158
19.3. Timer0 Output and Interrupt..................................................................................................... 159
19.4. Operation During Sleep............................................................................................................159
19.5. Register Definitions: Timer0 Control.........................................................................................159
19.6. Register Summary: Timer0.......................................................................................................164
20. TMR1 - Timer1 Module with Gate Control...........................................................................................165
20.1. Timer1 Operation......................................................................................................................166
20.2. Clock Source Selection............................................................................................................ 167
20.3. Timer1 Prescaler...................................................................................................................... 168
20.4. Timer1 Operation in Asynchronous Counter Mode.................................................................. 168
20.5. Timer1 16-Bit Read/Write Mode...............................................................................................168
20.6. Timer1 Gate..............................................................................................................................169
20.7. Timer1 Interrupt........................................................................................................................172
20.8. Timer1 Operation During Sleep................................................................................................173
20.9. CCP Capture/Compare Time Base.......................................................................................... 173
20.10. CCP Special Event Trigger...................................................................................................... 173
20.11. Register Definitions: Timer1 Control.........................................................................................173
20.12. Register Summary Timer 1...................................................................................................... 179
21. TMR2 - Timer2 Module....................................................................................................................... 180
21.1. Timer2 Operation......................................................................................................................181
21.2. Timer2 Output...........................................................................................................................181
21.3. External Reset Sources............................................................................................................182
21.4. Timer2 Interrupt........................................................................................................................182
21.5. PSYNC bit................................................................................................................................ 182
21.6. CSYNC bit................................................................................................................................182
21.7. Operating Modes......................................................................................................................183
21.8. Operation Examples.................................................................................................................184
21.9. Timer2 Operation During Sleep................................................................................................194
21.10. Register Definitions: Timer2 Control........................................................................................ 194
21.11. Register Summary - Timer2..................................................................................................... 202
22. CCP - Capture/Compare/PWM Module.............................................................................................. 203
22.1. CCP Module Configuration.......................................................................................................203
22.2. Capture Mode...........................................................................................................................203
22.3. Compare Mode.........................................................................................................................205
22.4. PWM Overview.........................................................................................................................206
22.5. Register Definitions: CCP Control............................................................................................ 211
22.6. Register Summary - CCP Control............................................................................................ 215
23. PWM - Pulse-Width Modulation.......................................................................................................... 216
23.1. Fundamental Operation............................................................................................................217
23.2. PWM Output Polarity................................................................................................................217
23.3. PWM Period............................................................................................................................. 217
DS40002195A-page 9
Preliminary Datasheet
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23.4. PWM Duty Cycle...................................................................................................................... 218
23.5. PWM Resolution.......................................................................................................................218
23.6. Operation in Sleep Mode..........................................................................................................219
23.7. Changes in System Clock Frequency...................................................................................... 219
23.8. Effects of Reset........................................................................................................................219
23.9. Setup for PWM Operation using PWMx Output Pins............................................................... 219
23.10. Setup for PWM Operation to Other Device Peripherals...........................................................220
23.11. Register Definitions: PWM Control...........................................................................................220
23.12. Register Summary - PWM....................................................................................................... 223
24. EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter.......................... 224
24.1. EUSART Asynchronous Mode.................................................................................................226
24.2. Clock Accuracy with Asynchronous Operation.........................................................................231
24.3. EUSART Baud Rate Generator (BRG).................................................................................... 232
24.4. EUSART Synchronous Mode...................................................................................................239
24.5. EUSART Operation During Sleep............................................................................................ 244
24.6. Register Definitions: EUSART Control.....................................................................................245
24.7. Register Summary - EUSART..................................................................................................253
25. MSSP - Master Synchronous Serial Port Module............................................................................... 254
25.1. SPI Mode Overview..................................................................................................................254
25.2. I2C Mode Overview.................................................................................................................. 263
25.3. Baud Rate Generator............................................................................................................... 300
25.4. Register Definitions: MSSP Control......................................................................................... 301
25.5. Register Summary: MSSP Control...........................................................................................313
26. FVR - Fixed Voltage Reference.......................................................................................................... 314
26.1. Independent Gain Amplifiers....................................................................................................314
26.2. FVR Stabilization Period.......................................................................................................... 314
26.3. Register Definitions: FVR.........................................................................................................314
26.4. Register Summary - FVR ........................................................................................................ 316
27. ADC - Analog-to-Digital Converter......................................................................................................317
27.1. ADC Configuration................................................................................................................... 318
27.2. ADC Operation.........................................................................................................................321
27.3. ADC Acquisition Requirements................................................................................................324
27.4. Register Definitions: ADC Control............................................................................................326
27.5. Register Summary - ADC.........................................................................................................331
28. Charge Pump......................................................................................................................................332
28.1. Manually Enabled.....................................................................................................................332
28.2. Automatically Enabled..............................................................................................................332
28.3. Disabled................................................................................................................................... 332
28.4. Charge Pump Threshold.......................................................................................................... 332
28.5. Charge Pump Ready................................................................................................................332
28.6. Register Definitions: Charge Pump..........................................................................................333
29. Instruction Set Summary.....................................................................................................................335
29.1. Read-Modify-Write Operations.................................................................................................335
DS40002195A-page 10
Preliminary Datasheet
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29.2. Standard Instruction Set...........................................................................................................336
™
™
30. ICSP - In-Circuit Serial Programming ........................................................................................... 355
30.1. High-Voltage Programming Entry Mode...................................................................................355
30.2. Low-Voltage Programming Entry Mode....................................................................................355
30.3. Common Programming Interfaces........................................................................................... 355
31. Register Summary.............................................................................................................................. 358
32. Electrical Specifications...................................................................................................................... 363
32.1. Absolute Maximum Ratings(†).................................................................................................. 363
32.2. Standard Operating Conditions................................................................................................363
32.3. DC Characteristics................................................................................................................... 364
32.4. AC Characteristics....................................................................................................................369
33. DC and AC Characteristics Graphs and Tables..................................................................................387
34. Packaging Information........................................................................................................................ 388
34.1. Package Details....................................................................................................................... 391
35. APPENDIX A: Revision History...........................................................................................................416
The Microchip Website...............................................................................................................................417
Product Change Notification Service..........................................................................................................417
Customer Support...................................................................................................................................... 417
Product Identification System.....................................................................................................................418
Microchip Devices Code Protection Feature..............................................................................................418
Legal Notice............................................................................................................................................... 418
Trademarks................................................................................................................................................ 419
Quality Management System..................................................................................................................... 419
Worldwide Sales and Service.....................................................................................................................420
DS40002195A-page 11
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Table 1-1.ꢀPackages
Devicerotatethispage90
8-Pin 8-Pin 14-Pin
SOIC DFN TSSOP
14-
Pin
16-Pin
VQFN
20-
Pin
20-Pin
SSOP
20-
Pin
20-Pin
VQFN
28-
Pin
28-Pin 28-Pin
SSOP VQFN
40-
Pin
40-Pin
VQFN
44-Pin
TQFP
SOIC 3x3x0.9 PDIP
SOIC 3x3x0.9 SOIC
6x6x1 PDIP 5x5x0.9 10x10x1
PIC16F15213
PIC16F15214
PIC16F15223
PIC16F15224
PIC16F15225
PIC16F15243
PIC16F15244
PIC16F15245
PIC16F15254
PIC16F15255
PIC16F15256
PIC16F15274
PIC16F15275
PIC16F15276
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PIC16F15213/14/23/24/43/44
Pin Diagrams
2.
Pin Diagrams
Figure 2-1.ꢀ
8-Pin SOIC
8-Pin DFN
8
7
6
5
VDD
RA5
1
2
3
4
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
RA4
MCLR/VPP/RA3
Figure 2-2.ꢀ
14-Pin SOIC
14-Pin TSSOP
14
13
12
11
10
9
VDD
1
2
3
4
5
6
7
VSS
RA5
RA4
RA0/ICSPDAT
RA1/ICSPCLK
RA2
MCLR/VPP/RA3
RC5
RC0
RC4
RC1
8
RC3
RC2
Figure 2-3.ꢀ
16-Pin VQFN
16
15
14
13
12
RA5
RA4
1
2
3
4
RA0/ICSPDAT
RA1/ICSPCLK
RA2
11
10
9
MCLR/VPP/RA3
RC5
RC0
5
6
8
7
Note:ꢀ It is recommended that the exposed bottom pad be connected to VSS, however, it must not be the only VSS
connection to the device.
Figure 2-4.ꢀ
20-Pin PDIP
20-Pin SOIC
20-Pin SSOP
DS40002195A-page 13
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Pin Diagrams
VDD
RA5
RA4
1
2
3
4
5
6
7
8
9
20 VSS
19 RA0/ICSPDAT
18
RA1/ICSPCLK
MCLR/VPP/RA3
17 RA2
16 RC0
RC5
RC4
RC3
RC6
RC7
15
RC1
14 RC2
13 RB4
12 RB5
11
RB7 10
RB6
Figure 2-5.ꢀ
20-Pin VQFN
20 19 18 17 16
15
MCLR/VPP/RA3
RA1/ICSPCLK
1
2
3
4
14
RC5
RC4
RC3
RC6
RA2
13 RC0
12
11
RC1
RC2
5
6
7
8
9
10
Note:ꢀ It is recommended that the exposed bottom pad be connected to VSS, however, it must not be the only VSS
connection to the device.
DS40002195A-page 14
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Pin Allocation Tables
3.
Pin Allocation Tables
Table 3-1.ꢀ8-Pin Allocation Table
8-Pin
10-Bit
PWM
I/O
SOIC
DFN
ADC
ANA0
ANA1
ANA2
—
Reference
Timers
—
CCP
—
MSSP
EUSART
IOC
Interrupt
Basic
(1)
RA0
RA1
RA2
RA3
7
6
5
4
—
—
—
—
—
—
RX1
IOCA0
IOCA1
IOCA2
IOCA3
—
—
ICSPDAT
ICDDAT
(1,3)
DT1
(1,3)
(1,3)
CK1
V
+ (ADC)
—
—
SCL1
SCK1
ICSPCLK
ICDCLK
REF
(1,3)
(1)
(1,3)
(1)
—
—
T0CKI
—
—
SDA1
—
—
INT
—
(1,3)
SDI1
(1)
—
SS1
—
MCLR
V
PP
(1)
RA4
RA5
3
2
ANA4
ANA5
—
—
T1G
—
—
—
—
—
—
—
IOCA4
IOCA5
—
—
CLKOUT
CLKIN
(1)
(1)
T1CKI
CCP1
(1)
CCP2
(1)
(1)
ADACT
T2IN
V
1
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DD
DD
V
—
—
V
SS
SS
(2)
OUT
—
—
TMR0
CCP1
CCP2
PWM3
PWM4
SCL1
SCK1
SDA1
SDO1
TX1
DT1
CK1
—
Note:ꢀ
1.
2.
3.
This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
All output signals shown in this row are PPS remappable.
This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
Table 3-2.ꢀ14/16-Pin Allocation Table
I/O
14-Pin
SOIC
16-Pin
VQFN
ADC
Reference
Timers
CCP
10-Bit
PWM
MSSP
EUSART
IOC
Interrupt
Basic
TSSOP
RA0
RA1
13
12
12
11
ANA0
ANA1
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
—
—
ICSPDAT
ICDDAT
V
+ (ADC)
ICSPCLK
ICDCLK
REF
(1)
(1)
RA2
RA3
11
4
10
3
ANA2
—
—
—
T0CKI
—
—
—
—
—
—
—
—
IOCA2
IOCA3
INT
—
—
—
MCLR
V
PP
(1)
RA4
RA5
3
2
2
1
ANA4
ANA5
—
—
T1G
—
—
—
—
—
—
—
—
IOCA4
IOCA5
—
—
CLKOUT
CLKIN
(1)
T1CKI
(1)
T2IN
(1,3,4)
RC0
RC1
RC2
10
9
9
8
7
—
—
—
—
—
—
—
—
—
—
—
—
SCL1
SCK1
—
—
—
—
IOCC0
IOCC1
IOCC2
—
—
—
—
—
—
(1,3,4)
(1,3,4)
—
—
SDA1
(1,3,4)
SDI1
8
ANC2
—
(1)
ADACT
ANC3
ANC4
(1)
(1)
RC3
RC4
7
6
6
5
—
—
—
—
CCP2
—
—
—
SS1
IOCC3
IOCC4
—
—
—
—
(1,3)
CK1
—
DS40002195A-page 15
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Pin Allocation Tables
...........continued
I/O
14-Pin
16-Pin
VQFN
ADC
Reference
Timers
CCP
10-Bit
PWM
MSSP
EUSART
IOC
Interrupt
Basic
SOIC
TSSOP
(1)
(1)
RC5
5
4
ANC5
—
—
CCP1
—
—
RX1
IOCC5
—
—
(1,3)
DT1
V
1
16
13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DD
DD
V
14
—
V
SS
SS
(2)
OUT
TMR0
CCP1
CCP2
PWM3
PWM4
SCL1
SCK1
SDA1
SDO1
TX1
DT1
CK1
—
Note:ꢀ
1.
2.
3.
4.
This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
All output signals shown in this row are PPS remappable.
This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
2
These pins can be configured for I C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected
operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
Table 3-3.ꢀ20-Pin Allocation Table
I/O
20-Pin
PDIP
20-Pin
VQFN
ADC
Reference
Timers
CCP
10-Bit
PWM
MSSP
EUSART
IOC
Interrupt
Basic
SSOP
SOIC
RA0
RA1
19
16
15
ANA0
ANA1
—
—
—
—
—
—
—
—
—
—
—
IOCA0
IOCA1
—
—
ICSPDAT
ICDDAT
18
V
+ (ADC)
ICSPCLK
ICDCLK
REF
(1)
(1)
RA2
RA3
17
4
14
1
ANA2
—
—
—
T0CKI
—
—
—
—
—
—
—
—
—
IOCA2
IOCA3
INT
—
—
MCLR
V
PP
(1)
RA4
RA5
3
2
20
19
ANA4
ANA5
—
—
T1G
—
—
—
—
—
—
—
—
IOCA4
IOCA5
—
—
CLKOUT
CLKIN
(1)
T1CKI
(1)
T2IN
(1,3,4)
RB4
RB5
RB6
13
12
11
10
9
—
—
—
—
—
—
—
—
—
—
—
SDA1
(1,3,4)
—
IOCB4
IOCB5
IOCB6
—
—
—
—
—
—
SDI1
(1)
ANB5
ANB6
—
—
—
RX1
(1,3)
DT1
(1,3,4)
8
SCL1
SCK1
—
(1,3,4)
(1,3)
CK1
RB7
RC0
RC1
RC2
10
16
15
14
7
ANB7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCB7
IOCC0
IOCC1
IOCC2
—
—
—
—
—
—
—
—
13
12
11
—
—
—
—
—
—
—
ANC2
(1)
ADACT
ANC3
ANC4
ANC5
—
(1)
RC3
RC4
RC5
RC6
RC7
7
6
5
8
9
4
3
2
5
6
—
—
—
—
—
—
—
—
—
—
CCP2
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCC3
IOCC4
IOCC5
IOCC6
IOCC7
—
—
—
—
—
—
—
—
—
—
—
(1)
CCP1
(1)
—
SS1
—
—
—
DS40002195A-page 16
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Pin Allocation Tables
...........continued
I/O 20-Pin
20-Pin
VQFN
ADC
Reference
Timers
CCP
10-Bit
PWM
MSSP
EUSART
IOC
Interrupt
Basic
PDIP
SSOP
SOIC
V
1
18
17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
V
DD
DD
V
20
—
V
SS
SS
(2)
OUT
TMR0
CCP1
CCP2
PWM3
PWM4
SCL1
SCK1
SDA1
SDO1
TX1
DT1
CK1
—
Note:ꢀ
1.
2.
3.
4.
This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin.
All output signals shown in this row are PPS remappable.
This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.
2
These pins can be configured for I C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected
operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.
DS40002195A-page 17
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Guidelines for Getting Started with PIC16F152 Micr...
4.
Guidelines for Getting Started with PIC16F152 Microcontrollers
4.1
Basic Connection Requirements
Getting started with the PIC16F152 family of 8-bit microcontrollers requires attention to a minimal set of device pin
connections before proceeding with development.
The following pins must always be connected:
•
•
All VDD and VSS pins (see “Power Supply Pins”)
MCLR pin (see “Master Clear (MCLR) Pin”
These pins must also be connected if they are being used in the end application:
•
PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see “In-Circuit Serial
Programming (ICSP) Pins”)
•
CLKIN pin when an external clock source is used.
Additionally, the following may be required:
VREF+/VREF- pins are used when external voltage reference for analog modules is implemented
•
The minimum recommended connections are shown in Figure 4-1.
Figure 4-1.ꢀMinimum Recommended Connections
C2
VDD
R1
R2
MCLR
C1
PIC MCU
Vss
Key (all values are recommendations):
C1: 10 nF, 16V ceramic
C2: 0.1 F, 16V ceramic
R1: 10 kΩ
R2: 100Ω to 470Ω
4.2
Power Supply Pins
4.2.1
Decoupling Capacitors
The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling capacitors:
•
•
Value and type of capacitor: A 0.1 μF (100 nF), 10-25V capacitor is recommended. The capacitor should be a
low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are
recommended.
Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as
possible. It is recommended to place the capacitors on the same side of the board as the device. If space is
constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater than 0.25 inch (6 mm).
DS40002195A-page 18
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Guidelines for Getting Started with PIC16F152 Micr...
•
•
Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a
second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second
capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary
decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as
close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF).
Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to
the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first
in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a
minimum, thereby reducing PCB trace inductance.
4.2.2
Tank Capacitors
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for
integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should
be determined based on the trace resistance that connects the power supply source to the device, and the maximum
current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable
voltage sag at the device. Typical values range from 4.7 μF to 47 μF.
4.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If
programming and debugging are not required in the end application, a direct connection to VDD may be all that is
required. The addition of other components, to help increase the application’s resistance to spurious Resets from
voltage sags, may be beneficial. A typical configuration is shown in Figure 4-1. Other circuit designs may be
implemented, depending on the application’s requirements.
During programming and debugging, the resistance and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and
VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be
adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be
isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 4-2). The
jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin.
Figure 4-2.ꢀExample of MCLR Pin Connections
Rev. 30-000058A
4/5/2017
VDD
R1
R2
MCLR
PIC MCU
JP
C1
Note:ꢀ
1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL
specifications are met.
2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of MCLR pin
breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace
length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
DS40002195A-page 19
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Guidelines for Getting Started with PIC16F152 Micr...
Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they
can interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they should be removed from the circuit during programming and debugging. Alternatively,
refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming
specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL)
requirements.
For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed
into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool.
4.5
Unused I/Os
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10
kΩ resistor to VSS on unused pins to drive the output to logic low.
DS40002195A-page 20
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register and Bit Naming Conventions
5.
Register and Bit Naming Conventions
5.1
Register Names
When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted
as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section
will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This
naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device
to maintain compatibility with other devices in the family that contain more than one.
5.2
Bit Names
There are two variants for bit names:
•
•
Short name: Bit function abbreviation
Long name: Peripheral abbreviation + short name
5.2.1
Short Bit Names
Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit.
The bit names shown in the registers are the short name variant.
Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short
name is RegisterNamebits.ShortName. For example, the enable bit, ON, in the ADCON0 register can be set in C
programs with the instruction ADCON0bits.ON = 1.
Short names are generally not useful in assembly programs because the same name may be used by different
peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit
name are appended with an underscore plus the name of the register in which the bit resides to avoid naming
contentions.
5.2.2
5.2.3
Long Bit Names
Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to
the peripheral, thereby making every long bit name unique. The long bit name for the ADC enable bit is the ADC
prefix, AD, appended with the enable bit short name, ON, resulting in the unique bit name ADON.
Long bit names are useful in both C and assembly programs. For example, in C the ADCON0 enable bit can be set
with the ADON = 1instruction. In assembly, this bit can be set with the BSF ADCON0,ADONinstruction.
Bit Fields
Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention.
For example, the three Least Significant bit of the ADCON2 register contain the ADC Operating Mode Selection bit.
The short name for this field is MD and the long name is ADMD. Bit field access is only possible in C programs. The
following example demonstrates a C program instruction for setting the ADC to operate in Accumulate mode:
ADCON2bits.MD = 0b001;
Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended
with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name
MD2 and the long bit name is ADMD2. The following two examples demonstrate assembly program sequences for
setting the ADC to operate in Accumulate mode:
Example 1:
MOVLW ~(1<<MD2 | 1<<MD1)
ANDWF ADCON2,F
MOVLW 1<<MD0
IORWF ADCON2,F
DS40002195A-page 21
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register and Bit Naming Conventions
Example 2:
BCF
BCF
BSF
ADCON2,ADMD2
ADCON2,ADMD1
ADCON2,ADMD0
5.3
Register and Bit Naming Exceptions
5.3.1
Status, Interrupt, and Mirror Bits
Status, interrupt enables, Interrupt flags, and Mirror bits are contained in registers that span more than one
peripheral. In these cases, the bit name shown is unique so there is no prefix or short name variant.
DS40002195A-page 22
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register Legend
6.
Register Legend
Table 6-1.ꢀRegister Legend
Symbol
Definition
Readable bit
R
W
HS
HC
S
Writable bit
Hardware settable bit
Hardware clearable bit
Set only bit
C
Clear only bit
Unimplemented bit, read as ‘0’
Bit value is set
U
‘1’
‘0’
x
Bit value is cleared
Bit value is unknown
Bit value is unchanged
Bit value depends on condition
Bit value is predefined
u
q
m
DS40002195A-page 23
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Enhanced Mid-Range CPU
7.
Enhanced Mid-Range CPU
This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 50 instructions. Interrupt
capability includes automatic context saving. The hardware stack is 16-levels deep and has Overflow and Underflow
Reset capability. Direct, Indirect and Relative Addressing modes are available. Two File Select Registers (FSRs)
provide the ability to read program and data memory.
Figure 7-1.ꢀCore Data Path Diagram
Data Bus
PCLATH
PCL
Data Latch
Program Counter
Data Memory
Address Latch
MUX
16-Level Stack
STKPTR
Address Latch
Data Address
Program Memory
Data Latch
BSR
FSR0
FSR1
Instruction
Latch
Instruction Bus
inc/dec
logic
Address
Decode
STATUS
Register
Instruction
Decode and
Control
State Machine
Control Signals
MUX
ALU
W Register
7.1
Automatic Interrupt Context Saving
During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the
interrupt. This saves stack space and user code.
DS40002195A-page 24
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Enhanced Mid-Range CPU
7.2
7.3
16-Level Stack with Overflow and Underflow
These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will
set the appropriate bit (STKOVF or STKUNF), and if enabled, will cause a software Reset.
File Select Registers
There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which
allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction
cycle in instructions using INDF to allow the data to be fetched. General purpose memory can also be addressed
linearly, providing the ability to access contiguous data larger than 80 bytes.
7.4
Instruction Set
There are 50 instructions for the enhanced mid-range CPU to support the features of the CPU. See the “Instruction
Set Summary” chapter for more details.
DS40002195A-page 25
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
8.
Device Configuration
Device configuration consists of the Configuration Words, User ID, Device ID, Device Information Area (DIA) and the
Device Configuration Information (DCI) regions.
8.1
Configuration Words
There are five Configuration Words that allow the user to select the device oscillator, reset and memory protection
options. These are implemented at addresses 0x8007 - 0x800B.
Note:ꢀ The DEBUG bit in the Configuration Words is managed automatically by device development tools, including
debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’.
8.2
Code Protection
Code protection allows the device to be protected from unauthorized access. Internal access to the program memory
is unaffected by any code protection setting.
The entire program memory space is protected from external reads and writes by the CP bit. When CP = 0, external
reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read
program memory, regardless of the protection bit settings. Self-writing the program memory is dependent upon the
write protection setting.
8.3
8.4
Write Protection
Write protection allows the device to be protected from unintended self-writes. Applications, such as bootloader
software, can be protected while allowing other regions of the program memory to be modified.
The WRT bits determine which of the program memory blocks are protected.
User ID
Four words in the memory space (8000h-8003h) are designated as ID locations where the user can store checksum
or other code identification numbers. These locations are readable and writable during normal execution. See the
“VMREG Access to DIA, DCI, User ID, DEV/REV ID, and Configuration Words” section for more information on
accessing these memory locations. For more information on checksum calculation, see “Memory Programming
Specification” section in the “Electrical Specifications” chapter for more information on accessing these memory
locations. For more information on checksum calculation, see the “Family Programming Specification”.
8.5
8.6
Device ID and Revision ID
The 14-bit Device ID word is located at address 8006h and the 14-bit Revision ID is located at 8005h. These
locations are read-only and cannot be erased or modified.
Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision ID
and Configuration Words. Refer to the “NVM - Nonvolatile Memory Control” chapter for more information on
accessing these locations.
Register Definitions: Configuration Settings
DS40002195A-page 26
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
8.6.1
CONFIG1
Name:ꢀ
CONFIG1
Address:ꢀ 0x8007
Configuration Word 1
Bit
15
7
14
13
5
12
VDDAR
R/W
1
11
3
10
2
9
1
8
CLKOUTEN
Access
Reset
R/W
1
Bit
6
4
0
RSTOSC[1:0]
FEXTOSC[1:0]
Access
Reset
R/W
0
R/W
1
R/W
0
R/W
1
Bit 12 – VDDARꢀ VDD Analog Range Calibration Selection(1)
Value
Description
1
0
Internal analog systems are calibrated for operation between VDD = 2.3V - 5.5V
Internal analog systems are calibrated for operation between VDD = 1.8V - 3.6V
Bit 8 – CLKOUTENꢀClock Out Enable
Value
Description
1
0
CLKOUT function is disabled; I/O function on CLKOUT pin
CLKOUT function is enabled; FOSC/4 clock appears on CLKOUT pin
Bits 5:4 – RSTOSC[1:0]ꢀPower-up Default Value for COSC bits
Selects the oscillator source used by user software. Refer to COSC operation.
Value
11
10
Description
EXTOSC operating per the FEXTOSC bits
HFINTOSC with FRQ = 1 MHz
LFINTOSC
01
00
HFINTOSC with FRQ = 32 MHz
Bits 1:0 – FEXTOSC[1:0]ꢀExternal Oscillator Mode Selection
Value
11
10
01
00
Description
ECH (16 MHz and higher)
ECL (below 16 MHz)
Oscillator not enabled
Reserved
Note:ꢀ
1. For the PIC16F152 family, this bit only affects the SMBus 3.0 (1.35V) input threshold. If the SMBus 3.0
threshold is selected (see the RxyI2C registers for details), this bit should be configured according to the
device’s expected VDD range.
DS40002195A-page 27
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
8.6.2
CONFIG2
Name:ꢀ
CONFIG2
Address:ꢀ 0x8008
Configuration Word 2
Bit
15
7
14
13
DEBUG
R/W
1
12
STVREN
R/W
11
PPS1WAY
R/W
10
2
9
BORV
R/W
1
8
Access
Reset
1
1
Bit
6
5
4
3
1
0
MCLRE
R/W
1
BOREN[1:0]
WDTE[1:0]
PWRTS[1:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bit 13 – DEBUGꢀ Debugger Enable(1)
Value
Description
1
0
Background debugger disabled
Background debugger enabled
Bit 12 – STVRENꢀStack Overflow/Underflow Reset Enable
Value
Description
1
Stack Overflow or Underflow will cause a Reset
0
Stack Overflow or Underflow will not cause a Reset
Bit 11 – PPS1WAYꢀPPSLOCKED One-Way Set Enable
Value
Description
1
The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once
PPSLOCKED is set, all future changes to PPS registers are prevented
0
The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)
Bit 9 – BORVꢀ Brown-out Reset (BOR) Voltage Selection(2)
Value
Description
1
0
Brown-out Reset voltage (VBOR) set to 1.9V
Brown-out Reset voltage (VBOR) set to 2.85V
Bits 7:6 – BOREN[1:0]ꢀ Brown-out Reset (BOR) Enable(3)
Value
11
10
01
00
Description
Brown-out Reset enabled, SBOREN bit is ignored
Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored
Brown-out Reset enabled according to SBOREN
Brown-out Reset disabled
Bits 4:3 – WDTE[1:0]ꢀWatchdog Timer (WDT) Enable
Value
11
10
01
00
Description
WDT enabled regardless of Sleep; SEN bit of WDTCON is ignored
WDT enabled while Sleep = 0, suspended when Sleep = 1; SEN bit if WDTCON is ignored
WDT enabled/disabled by the SEN bit of WDTCON
WDT disabled, SEN bit of WDTCON is ignored
Bits 2:1 – PWRTS[1:0]ꢀPower-Up Timer (PWRT) Selection
Value
11
10
Description
PWRT disabled
PWRT is set at 64 ms
DS40002195A-page 28
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
Value
01
00
Description
PWRT is set at 16 ms
PWRT is set at 1 ms
Bit 0 – MCLREꢀ Master Clear (MCLR) Enable
Value
x
1
0
Condition
If LVP = 1
If LVP = 0
If LVP = 0
Description
MCLR pin is MCLR
MCLR pin is MCLR
MCLR pin function is port-defined function
Note:ꢀ
1. The DEBUG bit is managed automatically by device development tools including debuggers and
programmers. For normal device operation, this bit should be maintained as a ‘1’.
2. The higher voltage selection is recommended for operation at or above 16 MHz.
3. When enabled, Brown-out Reset voltage (VBOR) is set by the BORV bit.
DS40002195A-page 29
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
8.6.3
CONFIG3
Name:ꢀ
CONFIG3
Address:ꢀ 0x8009
Configuration Word 3
Note:ꢀ This register is reserved.
Bit
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
0
Access
Reset
Bit
Access
Reset
DS40002195A-page 30
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Device Configuration
8.6.4
CONFIG4
Name:ꢀ
CONFIG4
Address:ꢀ 0x800A
Configuration Word 4
Bit
15
14
13
LVP
R/W
1
12
11
WRTSAF
R/W
10
2
9
WRTC
R/W
1
8
WRTB
R/W
1
Access
Reset
1
Bit
7
WRTAPP
R/W
6
5
4
SAFEN
R/W
1
3
BBEN
R/W
1
1
0
BBSIZE[2:0]
Access
Reset
R/W
1
R/W
1
R/W
1
1
Bit 13 – LVPꢀ Low-Voltage Programming Enable(1)
Value
Description
1
0
Low-Voltage Programming is enabled. MCLR/VPP pin function is MCLR. The MCLRE bit is ignored.
High voltage (HV) on MCLR/VPP must be used for programming.
Bit 11 – WRTSAFꢀ Storage Area Flash (SAF) Write Protection(2,3)
Value
Description
1
0
SAF is NOT write-protected
SAF is write-protected
Bit 9 – WRTCꢀ Configuration Registers Write-Protection(2)
Value
Description
1
0
Configuration registers are NOT write-protected
Configuration registers are write-protected
Bit 8 – WRTBꢀ Boot Block Write-Protection(2,4)
Value
Description
1
0
Boot Block is NOT write-protected
Boot Block is write-protected
Bit 7 – WRTAPPꢀ Application Block Write-Protection(2)
Value
Description
1
0
Application Block is NOT write-protected
Application Block is write-protected
Bit 4 – SAFENꢀ Storage Area Flash (SAF) Enable(2)
Value
Description
1
0
SAF is disabled
SAF is enabled
Bit 3 – BBENꢀ Boot Block Enable(2)
Value
Description
1
0
Boot Block is disabled
Boot Block is enabled
DS40002195A-page 31
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Device Configuration
Bits 2:0 – BBSIZE[2:0]ꢀ Boot Block Size Selection(5,6)
Table 8-1.ꢀBoot Block Size
Boot Block Size (words)
End Address
of Boot Block
BBEN
BBSIZE
PIC16F152x3 PIC16F152x4 PIC16F152x5 PIC16F152x6
1
0
0
0
0
0
0
0
0
xxx
111
110
101
100
011
010
001
000
–
–
512
1024
01FFh
03FFh
07FFh
0FFFh
1FFFh
3FFFh
3FFFh
3FFFh
(6)
–
2048
(6)
–
4096
(6)
–
8192
(6)
(6)
(6)
–
–
–
Note:ꢀ
1. The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of
this rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or
accidentally eliminating LVP mode from the Configuration state.
™
2. Once protection is enabled through ICSP or a self-write, it can only be reset through a Bulk Erase.
3. Applicable only if SAFEN = 0.
4. Applicable only if BBEN = 0.
5. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed
through a Bulk Erase.
6. The maximum Boot Block size is half of the user program memory size. Any selection that will exceed the half
of a device’s program memory will default to a maximum Boot Block size of half PFM. For example, all settings
of BBSIZE from ‘110’ to ‘000’ for a PIC16F15213 (Max PFM = 2048 words) will result in a maximum Boot
Block size of 1024 words.
DS40002195A-page 32
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Device Configuration
8.6.5
CONFIG5
Name:ꢀ
CONFIG5
Address:ꢀ 0x800B
Configuration Word 5(1)
Bit
15
7
14
6
13
5
12
4
11
3
10
2
9
1
8
Access
Reset
Bit
0
CP
R/W
1
Access
Reset
Bit 0 – CPꢀ User Program Flash Memory (PFM) Code Protection(2)
Value
Description
1
0
User PFM code protection is disabled
User PFM code protection is enabled
Note:ꢀ
1. Since device code protection takes effect immediately, this Configuration Word should be written last.
2. Once code protection is enabled it can only be removed through a Bulk Erase.
8.7
Register Definitions: Device ID and Revision ID
DS40002195A-page 33
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Device Configuration
8.7.1
Device ID
Name:ꢀ
DEVICEID
Address:ꢀ 8006h
Device ID Register
15
Bit
14
6
13
12
11
10
9
8
Reserved
Reserved
DEV[11:8]
Access
Reset
R
1
R
1
R
q
R
q
R
q
R
q
Bit
7
5
4
3
2
1
0
DEV[7:0]
Access
Reset
R
q
R
q
R
q
R
q
R
q
R
q
R
q
R
q
Bit 13 – Reservedꢀ Reserved - Read as 1
Bit 12 – Reservedꢀ Reserved - Read as 1
Bits 11:0 – DEV[11:0]ꢀDevice ID
Device
Device ID
PIC16F15213
PIC16F15214
PIC16F15223
PIC16F15224
PIC16F15225
PIC16F15243
PIC16F15244
PIC16F15245
PIC16F15254
PIC16F15255
PIC16F15256
PIC16F15274
PIC16F15275
PIC16F15276
30E3h
30E6h
30E4h
30E7h
30E9h
30E5h
30E8h
30EAh
30F0h
30EFh
30EBh
30EEh
30EDh
30ECh
DS40002195A-page 34
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Device Configuration
8.7.2
Revision ID
Name:ꢀ
REVISIONID
Address:ꢀ 8005h
Revision ID Register
15
Bit
14
6
13
12
11
10
9
8
Reserved
Reserved
MJRREV[5:2]
Access
Reset
R
1
R
0
R
q
R
q
R
q
R
q
Bit
7
5
4
3
2
1
0
MJRREV[1:0]
MNRREV[5:0]
Access
Reset
R
q
R
q
R
q
R
q
R
q
R
q
R
q
R
q
Bit 13 – Reservedꢀ Reserved - Read as 1
Bit 12 – Reservedꢀ Reserved - Read as 0
Bits 11:6 – MJRREV[5:0]ꢀMajor Revision ID
These bits are used to identify a major revision. (A0, B0, C0, etc.).
Bits 5:0 – MNRREV[5:0]ꢀMinor Revision ID
These bits are used to identify a minor revision.
DS40002195A-page 35
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
9.
Memory Organization
These devices contain the following types of memory:
•
Program Memory
– Configuration Words
– Device ID
– User ID
– Program Flash Memory
– Device Information Area (DIA)
– Device Configuration Information (DCI)
– Revision ID
•
Data Memory
– Core Registers
– Special Function Registers
– General Purpose RAM
– Common RAM
The following features are associated with access and control of program memory and data memory:
•
•
•
•
PCL and PCLATH
Stack
Indirect Addressing
NVMREG access
9.1
Program Memory Organization
The enhanced mid-range core has a 15-bit Program Counter capable of addressing 32K x 14 program memory
space. The table below shows the memory sizes implemented. Accessing a location above these boundaries will
cause a wrap-around within the implemented memory space.
The Reset vector is at 0000h and the interrupt vector is at 0004h. Refer to the “Interrupts” chapter for more details.
Table 9-1.ꢀDevice Sizes and Addresses
Device
Program Memory Size (Words)
Last Program Memory Address
PIC16F15213
PIC16F15214
PIC16F15223
PIC16F15224
PIC16F15243
PIC16F15244
2048
4096
2048
4096
2048
4096
07FFh
0FFFh
07FFh
0FFFh
07FFh
0FFFh
DS40002195A-page 36
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
Figure 9-1.ꢀProgram Memory and Stack (PIC16F15213/23/43)
PC[14:0]
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
0000h
Interrupt Vector 0004h
0005h
On-chip
Program
Memory
07FFh
0800h
Unimplemented
7FFFh
DS40002195A-page 37
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
Figure 9-2.ꢀProgram Memory and Stack (PIC16F15214/24/44)
PC[14:0]
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
15
Stack Level 0
Stack Level 1
Stack Level 15
Reset Vector
0000h
Interrupt Vector 0004h
0005h
On-chip
Program
Memory
0FFFh
1000h
Unimplemented
7FFFh
9.1.1
Reading Program Memory as Data
There are three methods of accessing constants in program memory. The first method is to use tables of RETLW
instructions. The second method is to set an FSR to point to the program memory. The third method is to use the
NVMREG interface to access the program memory.
9.1.1.1 RETLW Instruction
The RETLWinstruction can be used to provide access to tables of constants. The recommended way to create such a
table is shown in the following example.
Example 9-1.ꢀAccessing table of constants using RETLW instruction
constants
BRW
;Add Index in W to
;program counter to
;select data
DS40002195A-page 38
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW
DATA_INDEX
call constants
;… THE CONSTANT IS IN W
The BRWinstruction makes this type of table very simple to implement.
9.1.1.2 Indirect Read with FSR
The program memory can be accessed as data by setting bit 7 of an FSRxH register and reading the matching
INDFx register. The MOVIWinstruction will place the lower eight bits of the addressed word in the W register. Writes to
the program memory cannot be performed via the INDFx registers. Instructions that read the program memory via the
FSR require one extra instruction cycle to complete. The following example demonstrates reading the program
memory via an FSR.
The high directive will set bit 7 if a label points to a location in the program memory. This applies to the assembly
code shown below.
Example 9-2.ꢀRead of Program Memory using FSR Register
constants
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;Index0 data
;Index1 data
my_function
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW
LOW constants
FSR1L
HIGH constants
FSR1H
2[FSR1]
;DATA2 IS IN W
9.1.2
Memory Access Partition (MAP)
User Flash is partitioned into:
•
•
•
Application Block
Boot Block
Storage Area Flash (SAF) Block
The user can allocate the memory usage by setting the BBEN bit, selecting the size of the partition defined by
BBSIZE bits and enabling the Storage Area Flash by the SAFEN bit.
9.1.2.1 Application Block
Default settings of the Configuration bits (BBEN = 1and SAFEN = 1) assign all memory in the user Flash area to the
application block.
9.1.2.2 Boot Block
If BBEN = 1, the Boot Block is enabled and a specific address range is allotted as the Boot Block, based on the value
of the BBSIZE bits.
9.1.2.3 Storage Area Flash
Storage Area Flash (SAF) is enabled by clearing the SAFEN bit. If enabled, the SAF block is placed at the end of
memory and spans 128 words. If the Storage Area Flash (SAF) is enabled, the SAF area is not available for program
execution.
DS40002195A-page 39
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
9.1.2.4 Memory Write Protection
All the memory blocks have corresponding write protection bits (WRTAPP, WRTB and WRTC). If write-protected
locations are written from NVMCON registers, the memory is not changed and the WRERR bit of the NVMCON1
register is set as explained in the “WRERR Bit” section in the “NVM - Nonvolatile Memory Control” chapter.
9.1.2.5 Memory Violation
A Memory Execution Violation Reset occurs while executing an instruction that has been fetched from outside a valid
execution area, clearing the MEMV bit. Refer to the “Memory Execution Violation” section in the “Resets” chapter
for the available valid program execution areas and the PCON1 register definition for MEMV bit conditions.
Table 9-2.ꢀMemory Access Partition
Partition
REG
Address
BBEN = 1
BBEN = 1
BBEN = 0
BBEN = 0
SAFEN = 1
SAFEN = 0
SAFEN = 1
SAFEN = 0
00 0000h ... Last Block
Memory Address
Boot Block(4)
Boot Block(4)
Application
Block(4)
Last Boot Block Memory
Address + 1(1) ... Last
Program Memory
Application
Block(4)
Application
Block(4)
PFM
Address - 80h
Application
Block(4)
Last Program Memory
Address - 7Fh(2) ... Last
Program Memory
Address
SAF(4)
SAF(4)
Config Memory
Address(3)
CONFIG
CONFIG
Note:ꢀ
1. Last Boot Block Memory Address is based on BBSIZE.
2. Last Program Memory Address is the Flash size given in the “Program Memory Organization” section in the
“NVM - Nonvolatile Memory Control” chapter.
3. Config Memory Address are the address locations of the Configuration Words given in the “NVMREG Access
to DIA, DCI, User ID, DEV/REV ID, and Configuration Words” section in the “NVM - Nonvolatile Memory
Control” chapter.
4. Each memory block has a corresponding write protection fuse defined by the WRTAPP, WRTB, and WRTC
bits.
9.1.3
Device Information Area (DIA)
The Device Information Area (DIA) is a dedicated region in the Program Flash Memory. The data is mapped from
address 8100h to 811Fh. These locations are read-only and cannot be erased or modified. The DIA contains the
Microchip Unique Identifier words, and the Fixed Voltage Reference (FVR) voltage readings in millivolts (mV). Table
9-3 holds the DIA information for the PIC16F152 family of microcontrollers.
DS40002195A-page 40
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
Table 9-3.ꢀDevice Information Area
Address Range
Name of Region
Standard Device Information
MUI0
MUI1
MUI2
MUI3
8100h - 8108h
MUI4
Microchip Unique Identifier (9 Words)
MUI5
MUI6
MUI7
MUI8
8109h
MUI9
Reserved (1 Word)
EUI0
EUI1
EUI2
EUI3
810Ah - 8111h
Optional External Unique Identifier (8 Words)
EUI4
EUI5
EUI6
EUI7
8112h - 8117h
8118h
Reserved
FVRA1X
FVRA2X
FVRA4X
Reserved
Reserved (6 Words)
ADC FVR1 output voltage for 1x setting (in mV)
ADC FVR1 output voltage for 2x setting (in mV)
ADC FVR1 output voltage for 4x setting (in mV)
Reserved (5 Words)
8119h
811Ah
811Bh - 811Fh
9.1.3.1 Microchip Unique Identifier (MUI)
The PIC16F152 devices are individually encoded during final manufacturing with a Microchip Unique Identifier (MUI).
The MUI cannot be erased by a Bulk Erase command or any other user-accessible means. This feature allows for
manufacturing traceability of Microchip Technology devices in applications where this is required. It may also be used
by the application manufacturer for a number of functions that require unverified unique identification, such as:
•
•
Tracking the device
Unique serial number
The MUI consists of nine program words. When taken together, these fields form a unique identifier. The MUI is
stored in read-only locations, located between 8100h to 8108h in the DIA space. Table 9-3 lists the addresses of the
identifier words.
Important:ꢀ For applications that require verified unique identification, contact your Microchip Technology
sales office to create a serialized quick turn programming option.
DS40002195A-page 41
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
9.1.3.2 External Unique Identifier (EUI)
The EUI data is stored at locations 810Ah to 8111h in the program memory region. This region is an optional space
for placing application specific information. The data is coded per customer requirements during manufacturing. The
EUI cannot be erased by a Bulk Erase command.
Important:ꢀ Data is stored in this address range on receiving a request from the customer. The customer
may contact the local sales representative or Field Applications Engineer, and provide them the unique
identifier information that is required to be stored in this region.
9.1.3.3 Fixed Voltage Reference Data
The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V
selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following:
•
•
ADC input channel
ADC positive reference
For more information on the FVR, refer to the “FVR - Fixed Voltage Reference” chapter.
The DIA stores measured FVR voltages for this device in mV for the different buffer settings of 1x, 2x or 4x.
•
•
•
FVRA1X stores the value of ADC FVR1 Output Voltage for 1x setting (in mV)
FVRA2X stores the value of ADC FVR1 Output Voltage for 2x setting (in mV)
FVRA4X stores the value of ADC FVR1 Output Voltage for 4x setting (in mV)
9.1.4
Device Configuration Information (DCI)
The Device Configuration Information (DCI) is a dedicated region in the memory that holds information about the
device, which is useful for programming and bootloader applications. The data stored in this region is read-only and
cannot be modified/erased. Refer to Table 9-4 for complete DCI table addresses and description.
Table 9-4.ꢀDevice Configuration Information
Value
PIC16F15213
PIC16F15223
PIC16F15224
PIC16F15214
PIC16F15224
PIC16F15244
Address
Name
Description
Units
8200h
8201h
ERSIZ
WLSIZ
Erase row size
32
32
Words
Words
Number of write
latches per row
Number of user
erasable rows
8202h
URSIZ
64
128
Rows
Data EEPROM
memory size
8203h
8204h
EESIZ
PCNT
0
Bytes
Pins
Pin Count
8/14/20
8/14/20
9.1.4.1 DIA and DCI Access
The DIA and DCI data are read-only and cannot be erased or modified. See “NVMREG Access to DIA, DCI, User
ID, DEV/REV ID, and Configuration Words” section in the “NVM - Nonvolatile Memory Control” chapter for more
information on accessing these memory locations.
Development tools, such as device programmers and debuggers, may be used to read the DIA and DCI regions,
similar to the Device ID and Revision ID.
9.2
Data Memory Organization
The data memory is partitioned into up to 64 memory banks with 128 bytes in each bank. Each bank consists of:
DS40002195A-page 42
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
•
•
•
•
12 core registers
Up to 20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
Figure 9-3.ꢀBanked Memory Partition
Rev. 10-000 041C
11/8/201 7
7-bit Bank Offset
Typical Memory Bank
00h
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(up to 20 bytes maximum)
1Fh
20h
Special Function Registers
or
General Purpose RAM
(80 bytes maximum)
6Fh
70h
Common RAM
(16 bytes)
7Fh
9.2.1
9.2.2
Bank Selection
The active bank is selected by writing the bank number into the Bank Select Register (BSR). All data memory can be
accessed either directly via instructions that use the file registers, or indirectly via the two File Select Registers
(FSRs). Data memory uses a 13-bit address. The upper six bits of the address define the Bank Address and the
lower seven bits select the registers/RAM in that bank.
Core Registers
The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12
addresses of every data memory bank. These registers are listed in Table 9-5.
Table 9-5.ꢀCore Registers
Addresses in BANKx
x00h or x80h
Core Registers
INDF0
x01h or x81h
INDF1
DS40002195A-page 43
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
...........continued
Addresses in BANKx
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
Core Registers
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
9.2.3
9.2.4
Special Function Register
The Special Function Registers (SFR) are registers used by the application to control the desired operation of
peripheral functions in the device. The SFRs occupy the first 20 bytes of the data banks 0-59 and the first 100 bytes
of the data banks 60-63, after the core registers.
The SFRs associated with the operation of the peripherals are described in the appropriate peripheral chapter of this
data sheet.
General Purpose RAM
There are up to 80 bytes of GPR in each data memory bank. The general purpose RAM can be accessed in a non-
banked method via the FSRs. This can simplify access to large memory structures.
Refer to the “Linear Data Memory” section in the “Memory Organization” chapter for details about linear memory
accessing.
9.2.5
9.2.6
Common RAM
There are 16 bytes of common RAM accessible from all banks.
Device Memory Maps
The memory maps for the devices in this data sheet are listed in the following figures.
DS40002195A-page 44
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-4.ꢀMemory Map - Banks 0 - 15
BANKꢀ0
BANKꢀ1
BANKꢀ2
BANKꢀ3
BANKꢀ4
BANKꢀ5
BANKꢀ6
BANKꢀ7
000h
080h
100h
180h
200h
280h
300h
380h
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
00Bh
00Ch
00Dh
00Eh
00Fh
08Bh
08Ch
08Dh
08Eh
08Fh
10Bh
10Ch
10Dh
10Eh
10Fh
18Bh
18Ch
18Dh
18Eh
18Fh
20Bh
20Ch
20Dh
20Eh
20Fh
28Bh
28Ch
28Dh
28Eh
28Fh
30Bh
30Ch
30Dh
30Eh
30Fh
38Bh
38Ch
38Dh
38Eh
38Fh
PORTA
PORTB(1)
PORTC
—
—
—
—
—
RB4I2C(1)
RB6I2C(1)
RC0I2C(2)
SSP1BUF
SSP1ADD
SSP1MASK
SSP1STAT
SSP1CON1
TMR1L
TMR1H
T1CON
T1GCON
T1GATE
T1CLK
—
—
—
—
—
T2TMR
T2PR
T2CON
T2HLT
T2CLKCON
T2RST
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CCPR1L
CCPR1H
CCP1CON
CCP1CAP
CCPR2L
—
—
—
—
—
—
—
—
—
—
—
—
—
RC1I2C(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020hꢀꢀꢀ
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2AFhꢀꢀꢀ
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
—
—
—
—
—
—
—
—
—
SSP1CON2
SSP1CON3
CCPR2H
TRISA
TRISB
TRISCꢀ
—
—
—
LATA
LATB(1)
LATCꢀ
—
—
—
CCP2CON
CCP2CAP
PWM3DCL
PWM3DCH
PWM3CON
—
PWM4DCL
PWM4DCH
PWM4CON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RC1REG
TX1REG
SP1BRGL
SP1BRGH
RC1STA
TX1STA
BAUD1CON
—
—
—
—
—
—
—
CPCON
ADRESL
ADRESH
ADCON0
ADCON1
ADACT
—
—
GeneralꢀPurposeꢀ
Registerꢀ16ꢀBytes(3)
General
Purpose
Register
80ꢀBytes(3)
General
Purpose
Register
80ꢀBytes(3)
General
Purpose
Register
80ꢀBytes
General
Purpose
Register
80ꢀBytes
General
Purpose
Register
80ꢀBytes
32Fhꢀꢀꢀ
330hꢀꢀ
Unimplementedꢀꢀꢀ
Readꢀasꢀ'0'
Unimplementedꢀꢀꢀ
Readꢀasꢀ'0'
Unimplementedꢀꢀ
Readꢀasꢀ'0'
06Fh
070h
0EFh
0F0h
16Fh
170h
1EFh
1F0h
26Fh
270h
36Fh
370h
3EFh
3F0h
36Fh
2F0h
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
CommonꢀRAM
(Accesses
07Fh
70hͲ7Fh)
0FFh
70hͲ7Fh)
17Fh
70hͲ7Fh)
1FFh
70hͲ7Fh)
27Fh
70hͲ7Fh)
2FFh
70hͲ7Fh)
73Fh
70hͲ7Fh)
3FFh
70hͲ7Fh)
Note:ꢀ
1. AvailableꢀonꢀPIC16F15243/44ꢀdevicesꢀonly
2.ꢀNotꢀavailableꢀonꢀPIC16F15213/14ꢀdevices
3. AvailableꢀonꢀPIC16F15214/24/44ꢀdevicesꢀonly
Legend:
Unimplementedꢀdataꢀmemoryꢀlocations,ꢀreadꢀasꢀ'0'
ꢀꢁE<ꢂϴ
ꢀꢁE<ꢂϵ
ꢀꢁE<ꢂϭϬ
ꢀꢁE<ꢂϭϭ
ꢀꢁE<ꢂϭϮ
ꢀꢁE<ꢂϭϯ
ꢀꢁE<ꢂϭϰ
ꢀꢁE<ꢂϭϱ
ϰϬϬŚ
ϰϴϬŚ
ϱϬϬŚ
ϱϴϬŚ
ϲϬϬŚ
ϲϴϬŚ
ϳϬϬŚ
ϳϴϬŚ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
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ϰϬꢁŚ
ϰϬꢃŚ
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ϰϬ&Ś
ϰϭϬŚ
ϰϭϭŚ
ϰϭϮŚ
ϰϭϯŚ
ϰϭϰŚ
ϰϭϱŚ
ϰϭϲŚ
ϰϭϳŚ
ϰϭϴŚ
ϰϭϵŚ
ϰϭꢅŚ
ϰϭꢀŚ
ϰϭꢁŚ
ϰϭꢃŚ
ϰϭꢄŚ
ϰϭ&Ś
ϰϮϬŚ
ϰϴꢀŚ
ϰϴꢁŚ
ϰϴꢃŚ
ϰϴꢄŚ
ϰϴ&Ś
ϰϵϬŚ
ϰϵϭŚ
ϰϵϮŚ
ϰϵϯŚ
ϰϵϰŚ
ϰϵϱŚ
ϰϵϲŚ
ϰϵϳŚ
ϰϵϴŚ
ϰϵϵŚ
ϰϵꢅŚ
ϰϵꢀŚ
ϰϵꢁŚ
ϰϵꢃŚ
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ϰϵ&Ś
ϰꢅϬŚ
ϱϬꢀŚ
ϱϬꢁŚ
ϱϬꢃŚ
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ϱϬ&Ś
ϱϭϬŚ
ϱϭϭŚ
ϱϭϮŚ
ϱϭϯŚ
ϱϭϰŚ
ϱϭϱŚ
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ϱϭϳŚ
ϱϭϴŚ
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ϱϵϭŚ
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ϱϵϯŚ
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ϱϵϱŚ
ϱϵϲŚ
ϱϵϳŚ
ϱϵϴŚ
ϱϵϵŚ
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ϱϵꢀŚ
ϱϵꢁŚ
ϱϵꢃŚ
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ϱϵ&Ś
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ϲϬ&Ś
ϲϭϬŚ
ϲϭϭŚ
ϲϭϮŚ
ϲϭϯŚ
ϲϭϰŚ
ϲϭϱŚ
ϲϭϲŚ
ϲϭϳŚ
ϲϭϴŚ
ϲϭϵŚ
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ϲϭꢀŚ
ϲϭꢁŚ
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ϲϭ&Ś
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ϲϴ&Ś
ϲϵϬŚ
ϲϵϭŚ
ϲϵϮŚ
ϲϵϯŚ
ϲϵϰŚ
ϲϵϱŚ
ϲϵϲŚ
ϲϵϳŚ
ϲϵϴŚ
ϲϵϵŚ
ϲϵꢅŚ
ϲϵꢀŚ
ϲϵꢁŚ
ϲϵꢃŚ
ϲϵꢄŚ
ϲϵ&Ś
ϲꢅϬŚ
ϳϬꢀŚ
ϳϬꢁŚ
ϳϬꢃŚ
ϳϬꢄŚ
ϳϬ&Ś
ϳϭϬŚ
ϳϭϭŚ
ϳϭϮŚ
ϳϭϯŚ
ϳϭϰŚ
ϳϭϱŚ
ϳϭϲŚ
ϳϭϳŚ
ϳϭϴŚ
ϳϭϵŚ
ϳϭꢅŚ
ϳϭꢀŚ
ϳϭꢁŚ
ϳϭꢃŚ
ϳϭꢄŚ
ϳϭ&Ś
ϳϮϬŚ
ϳϴꢀŚ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
W/ZϬ
W/Zϭ
W/ZϮ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
W/ꢄϬ
W/ꢄϭ
W/ꢄϮ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
ϳϴꢁŚ
ϳϴꢃŚ
ϳϴꢄŚ
ϳϴ&Ś
ϳϵϬŚ
ϳϵϭŚ
ϳϵϮŚ
ϳϵϯŚ
ϳϵϰŚ
ϳϵϱŚ
ϳϵϲŚ
ϳϵϳŚ
ϳϵϴŚ
ϳϵϵŚ
ϳϵꢅŚ
ϳϵꢀŚ
ϳϵꢁŚ
ϳϵꢃŚ
ϳϵꢄŚ
ϳϵ&Ś
ϳꢅϬŚ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
dDZϬ>
dDZϬ,
dϬꢁKEϬ
dϬꢁKEϭ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
ϰϲ&Ś
ϰϳϬŚ
ϰꢄ&Ś
ϰ&ϬŚ
ϱϲ&Ś
ϱϳϬŚ
ϱꢄ&Ś
ϱ&ϬŚ
ϲϲ&Ś
ϲϳϬŚ
ϲꢄ&Ś
ϲ&ϬŚ
ϳϲ&Ś
ϳϳϬŚ
ϳꢄ&Ś
ϳ&ϬŚ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢅD
;ꢅĐĐĞƐƐĞƐ
ϰϳ&Ś
ϳϬŚͲϳ&ŚͿ
ϰ&&Ś
ϳϬŚͲϳ&ŚͿ
ϱϳ&Ś
ϳϬŚͲϳ&ŚͿ
ϱ&&Ś
ϳϬŚͲϳ&ŚͿ
ϲϳ&Ś
ϳϬŚͲϳ&ŚͿ
ϲ&&Ś
ϳϬŚͲϳ&ŚͿ
ϳϯ&Ś
ϳϬŚͲϳ&ŚͿ
ϳ&&Ś
ϳϬŚͲϳ&ŚͿ
>ĞŐĞŶĚ͗
ꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂhŶŝŵƉůĞŵĞŶƚĞĚꢂĚĂƚĂꢂŵĞŵŽƌLJꢂůŽĐĂƚŝŽŶƐ͕ꢂƌĞĂĚꢂĂƐꢂΖϬΖ
DS40002195A-page 45
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-5.ꢀMemory Map - Banks 16 - 23; Banks 56 - 63
ꢀꢁE<ꢂϭϲ
ꢀꢁE<ꢂϭϳ
ꢀꢁE<ꢂϭϴ
ꢀꢁE<ꢂϭϵ
ꢀꢁE<ꢂϮϬ
ꢀꢁE<ꢂϮϭ
ꢀꢁE<ꢂϮϮ
ꢀꢁE<ꢂϮϯ
ϴϬϬŚ
ϴϴϬŚ
ϵϬϬŚ
ϵϴϬŚ
ꢃϬϬŚ
ꢃϴϬŚ
ꢀϬϬŚ
ꢀϴϬŚ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ϴϬꢀŚ
ϴϬꢁŚ
ϴϬꢄŚ
ϴϬꢅŚ
ϴϬ&Ś
ϴϭϬŚ
ϴϭϭŚ
ϴϭϮŚ
ϴϭϯŚ
ϴϭϰŚ
ϴϭϱŚ
ϴϭϲŚ
ϴϭϳŚ
ϴϭϴŚ
ϴϭϵŚ
ϴϭꢃŚ
ϴϭꢀŚ
ϴϭꢁŚ
ϴϭꢄŚ
ϴϭꢅŚ
ϴϭ&Ś
ϴϮϬŚ
ϴϴꢀŚ
ϴϴꢁŚ
ϴϴꢄŚ
ϴϴꢅŚ
ϴϴ&Ś
ϴϵϬŚ
ϴϵϭŚ
ϴϵϮŚ
ϴϵϯŚ
ϴϵϰŚ
ϴϵϱŚ
ϴϵϲŚ
ϴϵϳŚ
ϴϵϴŚ
ϴϵϵŚ
ϴϵꢃŚ
ϴϵꢀŚ
ϴϵꢁŚ
ϴϵꢄŚ
ϴϵꢅŚ
ϴϵ&Ś
ϴꢃϬŚ
ϵϬꢀŚ
ϵϬꢁŚ
ϵϬꢄŚ
ϵϬꢅŚ
ϵϬ&Ś
ϵϭϬŚ
ϵϭϭŚ
ϵϭϮŚ
ϵϭϯŚ
ϵϭϰŚ
ϵϭϱŚ
ϵϭϲŚ
ϵϭϳŚ
ϵϭϴŚ
ϵϭϵŚ
ϵϭꢃŚ
ϵϭꢀŚ
ϵϭꢁŚ
ϵϭꢄŚ
ϵϭꢅŚ
ϵϭ&Ś
ϵϮϬŚ
ϵϴꢀŚ
ϵϴꢁŚ
ϵϴꢄŚ
ϵϴꢅŚ
ϵϴ&Ś
ϵϵϬŚ
ϵϵϭŚ
ϵϵϮŚ
ϵϵϯŚ
ϵϵϰŚ
ϵϵϱŚ
ϵϵϲŚ
ϵϵϳŚ
ϵϵϴŚ
ϵϵϵŚ
ϵϵꢃŚ
ϵϵꢀŚ
ϵϵꢁŚ
ϵϵꢄŚ
ϵϵꢅŚ
ϵϵ&Ś
ϵꢃϬŚ
ꢃϬꢀŚ
ꢃϬꢁŚ
ꢃϬꢄŚ
ꢃϬꢅŚ
ꢃϬ&Ś
ꢃϭϬŚ
ꢃϭϭŚ
ꢃϭϮŚ
ꢃϭϯŚ
ꢃϭϰŚ
ꢃϭϱŚ
ꢃϭϲŚ
ꢃϭϳŚ
ꢃϭϴŚ
ꢃϭϵŚ
ꢃϭꢃŚ
ꢃϭꢀŚ
ꢃϭꢁŚ
ꢃϭꢄŚ
ꢃϭꢅŚ
ꢃϭ&Ś
ꢃϮϬŚ
ꢃϴꢀŚ
ꢃϴꢁŚ
ꢃϴꢄŚ
ꢃϴꢅŚ
ꢃϴ&Ś
ꢃϵϬŚ
ꢃϵϭŚ
ꢃϵϮŚ
ꢃϵϯŚ
ꢃϵϰŚ
ꢃϵϱŚ
ꢃϵϲŚ
ꢃϵϳŚ
ꢃϵϴŚ
ꢃϵϵŚ
ꢃϵꢃŚ
ꢃϵꢀŚ
ꢃϵꢁŚ
ꢃϵꢄŚ
ꢃϵꢅŚ
ꢃϵ&Ś
ꢃꢃϬŚ
ꢀϬꢀŚ
ꢀϬꢁŚ
ꢀϬꢄŚ
ꢀϬꢅŚ
ꢀϬ&Ś
ꢀϭϬŚ
ꢀϭϭŚ
ꢀϭϮŚ
ꢀϭϯŚ
ꢀϭϰŚ
ꢀϭϱŚ
ꢀϭϲŚ
ꢀϭϳŚ
ꢀϭϴŚ
ꢀϭϵŚ
ꢀϭꢃŚ
ꢀϭꢀŚ
ꢀϭꢁŚ
ꢀϭꢄŚ
ꢀϭꢅŚ
ꢀϭ&Ś
ꢀϮϬŚ
ꢀϴꢀŚ
ꢀϴꢁŚ
tꢄdꢁKE
Ͷ
Ͷ
Ͷ
Ͷ
ꢀKZꢁKE
Ͷ
WꢁKEϬ
WꢁKEϭ
Ͷ
Ͷ
Ͷ
K^ꢁꢁKE
Ͷ
K^ꢁ^dꢃd
K^ꢁꢅE
K^ꢁdhEꢅ
K^ꢁ&ZY
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
&sZꢁKE
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
hŶŝŵƉůĞŵĞŶƚĞĚ
ZĞĂĚꢂĂƐꢂΖϬΖ
EsDꢃꢄZ>
EsDꢃꢄZ,
EsDꢄꢃd>
EsDꢄꢃd,
EsDꢁKEϭ
EsDꢁKEϮ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
hŶŝŵƉůĞŵĞŶƚĞĚꢂꢂꢂ
ZĞĂĚꢂĂƐꢂΖϬΖ
ϴϲ&Ś
ϴϳϬŚ
ϴꢅ&Ś
ϴ&ϬŚ
ϵϲ&Ś
ϵϳϬŚ
ϵꢅ&Ś
ϵ&ϬŚ
ꢃϲ&Ś
ꢃϳϬŚ
ꢃꢅ&Ś
ꢃ&ϬŚ
ꢀϲ&Ś
ꢀϳϬŚ
ꢀꢅ&Ś
ꢀ&ϬŚ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ꢁŽŵŵŽŶꢂZꢃD
;ꢃĐĐĞƐƐĞƐ
ϴϳ&Ś
ϳϬŚͲϳ&ŚͿ
ϴ&&Ś
ϳϬŚͲϳ&ŚͿ
ϵϳ&Ś
ϳϬŚͲϳ&ŚͿ
ϵ&&Ś
ϳϬŚͲϳ&ŚͿ
ꢃϳ&Ś
ϳϬŚͲϳ&ŚͿ
ꢃ&&Ś
ϳϬŚͲϳ&ŚͿ
ꢀ&&Ś
ϳϬŚͲϳ&ŚͿ
ꢀ&&Ś
ϳϬŚͲϳ&ŚͿ
>ĞŐĞŶĚ͗
ꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂꢂhŶŝŵƉůĞŵĞŶƚĞĚꢂĚĂƚĂꢂŵĞŵŽƌLJꢂůŽĐĂƚŝŽŶƐ͕ꢂƌĞĂĚꢂĂƐꢂΖϬΖ
BANKꢀ56
BANKꢀ57
BANKꢀ58
BANKꢀ59
BANKꢀ60
BANKꢀ61
BANKꢀ62
BANKꢀ63
1C00h
1C80h
1D00h
1D80h
1E00h
1E80h
1F00h
1F80h
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
CoreꢀRegisters
ꢀꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀ
ꢀꢀꢀ
ꢀꢀꢀ
1C0Bh
1C0Ch
1C8Bh
1C8Ch
1D0Bh
1D0Ch
1D8Bh
1D8Ch
1E0Bh
1E0Ch
1E8Bh
1E8Ch
1F0Bh
1F0Ch
1F8Bh
1F8Ch
Unimplemented
Readꢀasꢀ'0'
SeeꢀFigureꢀ9Ͳ6ꢀfor
registerꢀmappingꢀ
details
SeeꢀFigureꢀ9Ͳ7ꢀfor
registerꢀmappingꢀ
details
Unimplemented
Readꢀasꢀ'0'
Unimplemented
Readꢀasꢀ'0'
Unimplemented
Readꢀasꢀ'0'
Unimplemented
Readꢀasꢀ'0'
Unimplemented
Readꢀasꢀ'0'
1FE3h
1FE4h
1FE5h
1FE6h
STATUS_SHAD
WREG_SHAD
BSR_SHAD
1FE7h PCLATH_SHAD
1FE8h
1FE9h
1FEAh
1FEBh
1FECh
1FEDh
1FEEh
1FEFh
1FF0h
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
—
STKPTR
TOSL
TOSH
1C6Fh
1CEFh
1D6Fh
1E6Fh
1EEFh
1F6Fh
1C70h CommonꢀRAM
1CF0h CommonꢀRAM
1D70h CommonꢀRAM
1DF0h CommonꢀRAM
1E70h CommonꢀRAM
1EF0h CommonꢀRAM
1F70h CommonꢀRAM
CommonꢀRAM
(Accesses
70hͲ7Fh)
(Accesses
(Accesses
(Accesses
(Accesses
(Accesses
(Accesses
(Accesses
1C7Fh
70hͲ7Fh)
1CFFh
70hͲ7Fh)
1D7Fh
70hͲ7Fh)
1DFFh
70hͲ7Fh)
1E7Fh
70hͲ7Fh)
1EFFh
70hͲ7Fh)
1F7Fh
70hͲ7Fh)
1FFFh
Legend:
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀUnimplementedꢀdataꢀmemoryꢀlocations,ꢀreadꢀasꢀ'0'
DS40002195A-page 46
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-6.ꢀMemory Map - Bank 61
ϭꢀꢁϲŚ
ϭꢀꢁϳŚ
ϭꢀꢁϴŚ
ϭꢀꢁϵŚ
ϭꢀꢁꢅŚ
ϭꢀꢁꢁŚ
ϭꢀꢁꢂŚ
ϭꢀꢁꢄŚ
ϭꢀꢁꢀŚ
ϭꢀꢁ&Ś
ϭꢀꢂϬŚ
ϭꢀꢂϭŚ
ϭꢀꢂϮŚ
ϭꢀꢂϯŚ
ϭꢀꢂϰŚ
ϭꢀꢂϱŚ
ϭꢀꢂϲŚ
ϭꢀꢂϳŚ
ϭꢀꢂϴŚ
ϭꢀꢂϵŚ
ϭꢀꢂꢅŚ
ϭꢀꢂꢁŚ
ϭꢀꢂꢂŚ
ϭꢀꢂꢄŚ
ϭꢀꢂꢀŚ
ϭꢀꢂ&Ś
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
ꢀꢁE<ꢂϲϭ
ϭꢀϴϬŚ
ꢂŽƌĞꢃZĞŐŝƐƚĞƌƐ
ϭꢀϴꢁŚ
Ͷ
Ͷ
Ͷ
ϭꢀϴꢂŚ
ϭꢀϴꢄŚ
ϭꢀϴꢀŚ
ϭꢀϴ&Ś
ϭꢀϵϬŚ
ϭꢀϵϭŚ
ϭꢀϵϮŚ
ϭꢀϵϯŚ
ϭꢀϵϰŚ
ϭꢀϵϱŚ
ϭꢀϵϲŚ
ϭꢀϵϳŚ
ϭꢀϵϴŚ
ϭꢀϵϵŚ
ϭꢀϵꢅŚ
ϭꢀϵꢁŚ
ϭꢀϵꢂŚ
ϭꢀϵꢄŚ
ϭꢀϵꢀŚ
ϭꢀϵꢃ&Ś
ϭꢀꢅϬŚ
ϭꢀꢅϭŚ
ϭꢀꢅϮŚ
ϭꢀꢅϯŚ
ϭꢀꢅϰŚ
ϭꢀꢅϱŚ
ϭꢀꢅϲŚ
ϭꢀꢅϳŚ
ϭꢀꢅϴŚ
ϭꢀꢅϵŚ
ϭꢀꢅꢅŚ
ϭꢀꢅꢁŚ
ϭꢀꢅꢂŚ
ϭꢀꢅꢄŚ
ϭꢀꢅꢀŚ
ϭꢀꢅ&Ś
ϭꢀꢁϬŚ
ϭꢀꢁϭŚ
ϭꢀꢁϮŚ
ϭꢀꢁϯŚ
ϭꢀꢁϰŚ
ϭꢀꢁϱŚ
WW^>Kꢂ<
/EdWW^
dϬꢂ</WW^
dϭꢂ</WW^
dϭ'WW^
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
dϮ/EWW^
Ͷ
Ͷ
Ͷ
Ͷ
ꢂꢂWϭWW^
ꢂꢂWϮWW^
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
ꢅꢄꢅꢂdWW^
Ͷ
^^Wϭꢂ><WW^
^^WϭꢄꢅdWW^
^^Wϭ^^WW^
Ͷ
Ͷ
Ͷ
ZyϭWW^
dyϭWW^
Ͷ
Ͷ
hŶŝŵƉůĞŵĞŶƚĞĚ
ZĞĂĚꢃĂƐꢃΖϬΖ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
Ͷ
ϭꢀ&ϬŚ
ϭꢀ&&Ś
ꢂŽŵŵŽŶꢃZꢅD
;ꢅĐĐĞƐƐĞƐ
ϳϬŚͲϳ&ŚͿ
>ĞŐĞŶĚ͗
ꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃꢃhŶŝŵƉůĞŵĞŶƚĞĚꢃĚĂƚĂꢃŵĞŵŽƌLJꢃůŽĐĂƚŝŽŶƐ͕ꢃƌĞĂĚꢃĂƐꢃΖϬΖ
DS40002195A-page 47
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-7.ꢀMemory Map - Bank 62
ꢀꢁE<ꢂϲϮ
ϭ&ϬϬŚ
ꢁŽƌĞꢂZĞŐŝƐƚĞƌƐ
ϭ&ϬꢀŚ
Ͷ
Ͷ
Ͷ
ϭ&ϬꢁŚ
ϭ&ϬꢃŚ
ϭ&ϬꢄŚ
ϭ&Ϭ&Ś
ϭ&ϭϬŚ
ϭ&ϭϭŚ
ϭ&ϭϮŚ
ϭ&ϭϯŚ
Ͷ
INLVLB(1)
1F47h
ZꢅϬWW^
ZꢅϭWW^
ZꢅϮWW^
ZꢅϯWW^;ϮͿ
ZꢅϰWW^
ZꢅϱWW^
IOCBP(1)
1F48h
IOCBN(1)
1F49h
IOCBF(1)
ϭ&ϭϰŚ
ϭ&ϭϱŚ
ϭ&ϭϲŚ
Ͳ
1F4Ah
—
—
—
1F4Bh
1F4Ch
1F4Dh
1F4Eh
1F4Fh
1F50h
1F51h
1F52h
1F53h
1F54h
1F55h
1F56h
Ͳ
ZĞƐĞƌǀĞĚ
ϭ&ϭꢀŚ
ϭ&ϭꢁŚ
ZꢀϰWW^;ϭͿ
ZꢀϱWW^;ϭͿ
ANSELC
WPUC
ODCONC
SLRCONC
INLVLC
IOCCP
IOCCN
IOCCF
ϭ&ϭꢃŚ
ϭ&ϭꢄŚ
ϭ&ϭ&Ś
ZꢀϲWW^;ϭͿ
ZꢀϳWW^;ϭͿ
ZꢁϬWW^
ZꢁϭWW^
ZꢁϮWW^
ZꢁϯWW^
ZꢁϰWW^
ZꢁϱWW^
ϭ&ϮϬŚ
ϭ&ϮϭŚ
ϭ&ϮϮŚ
ϭ&ϮϯŚ
ϭ&ϮϰŚ
ϭ&ϮϱŚ
ϭ&ϮϲŚ
ZꢁϲWW^;ϭͿ
ZꢁϳWW^;ϭͿ
Reserved
ϭ&ϮϳŚ
1F6Fh
ϭ&ϮϴŚ
Ͳ
ZĞƐĞƌǀĞĚ
1F70h CommonꢀRAM
ϭ&ϯϳŚ
ϭ&ϯϴŚ
ϭ&ϯϵŚ
ϭ&ϯꢅŚ
ϭ&ϯꢀŚ
ϭ&ϯꢁŚ
ϭ&ϯꢃŚ
ϭ&ϯꢄŚ
ϭ&ϯ&Ś
ϭ&ϰϬŚ
ϭ&ϰϭŚ
ϭ&ϰϮŚ
ϭ&ϰϯŚ
(Accesses
70hͲ7Fh)
ꢅE^ꢄ>ꢅ
tWhꢅ
KꢃꢁKEꢅ
^>ZꢁKEꢅ
/E>s>ꢅ
/KꢁꢅW
/KꢁꢅE
/Kꢁꢅ&
Ͷ
1F7Fh
Noteꢀ1:ꢀꢀAvailableꢀonꢀPIC16F15243/44ꢀonly.
Legend:
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀUnimplementedꢀdataꢀmemoryꢀlocations,ꢀreadꢀasꢀ'0'
Ͷ
Ͷ
ꢅE^ꢄ>ꢀ;ϭͿ
tWhꢀ;ϭͿ
KꢃꢁKEꢀ;ϭͿ
^>ZꢁKEꢀ;ϭͿ
ϭ&ϰϰŚ
ϭ&ϰϱŚ
ϭ&ϰϲŚ
9.3
STATUS Register
The STATUS register contains:
•
•
the arithmetic status of the ALU
the Reset status
The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the
destination for an instruction that affects the Z, DC or C bits, then writes to these three bits are disabled. These bits
are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the
result of an instruction with the STATUS register as destination may be different than intended.
For example, CLRF STATUSwill clear bits [4:3] and [1:0], and set the Z bit. This leaves the STATUS register as
‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF, SWAPFand MOVWFinstructions are used to alter the STATUS
register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits,
refer to the “Instruction Set Summary” chapter.
Important:ꢀ The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction.
DS40002195A-page 48
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
9.4
PCL and PCLATH
The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and
writable register. The high byte (PC[14:8]) is not directly readable or writable and comes from PCLATH. On any Reset
the PC is cleared. Figure 9-8 shows the five situations for the loading of the PC.
Figure 9-8.ꢀLoading of PC in Different Situations
Rev. 10-000042A
7/30/2013
PCH
7
14
6
PCL
0
0
Instruction
with PCL as
Destination
PC
8
0
0
0
PCLATH
ALU result
PCH
14
6
PCL
GOTO,
CALL
PC
4
11
OPCODE [10:0]
PCLATH
PCH
7
14
6
PCL
0
PC
CALLW
8
PCLATH
W
14
14
PCL
PCL
0
0
PCH
PCH
PC
PC
BRW
BRA
15
PC + W
15
PC + OPCODE [8:0]
9.4.1
Modifying PCL
Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter
PC[14:8] bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the
Program Counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower
eight bits are written to the PCL register, all 15 bits of the Program Counter will change to the values contained in the
PCLATH register and those being written to the PCL register.
9.4.2
9.4.3
Computed GOTO
A computed GOTOis accomplished by adding an offset to the Program Counter (ADDWF PCL). When performing a
table read using a computed GOTOmethod, care should be exercised if the table location crosses a PCL memory
boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556).
Computed Function Calls
A computed function CALLallows programs to maintain tables of functions and provide another way to execute state
machines or look-up tables. When performing a table read using a computed function CALL, care should be
exercised if the table location crosses a PCL memory boundary (each 256-byte block).
If using the CALLinstruction, the PCH[2:0] and PCL registers are loaded with the operand of the CALLinstruction.
PCH[6:3] is loaded with PCLATH[6:3].
DS40002195A-page 49
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
The CALLWinstruction enables computed calls by combining PCLATH and W to form the destination address. A
computed CALLWis accomplished by loading the W register with the desired address and executing CALLW. The PCL
register is loaded with the value of W and PCH is loaded with PCLATH.
9.4.4
Branching
The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page
boundaries. There are two forms of branching, BRWand BRA. The PC will have incremented to fetch the next
instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.
If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded
with the address PC + 1 + W.
If using BRA, the entire PC will be loaded with PC + 1 + the signed value of the operand of the BRAinstruction.
9.5
Stack
All devices have a 16-level by 15-bit wide hardware stack. The stack space is not part of either program or data
space. The PC is PUSHed onto the stack when CALLor CALLWinstructions are executed or an interrupt causes a
branch. The stack is POPed in the event of a RETURN, RETLWor a RETFIEinstruction execution. PCLATH is not
affected by a PUSH or POP operation.
The stack operates as a circular buffer if the STVREN Configuration bit is programmed to ‘0’. This means that after
the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first
PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be
set on an Overflow/Underflow, regardless of whether the Reset is enabled.
If the STVREN bit is programmed to ‘1’, the device will be Reset if the stack is PUSHed beyond the sixteenth level or
POPed beyond the fist level, setting the appropriate bits (STKOVF or STKUNF, respectively).
Important:ꢀ There are no instructions/mnemonics called PUSH or POP. These are actions that occur from
the execution of the CALL, CALLW, RETURN, RETLWand RETFIEinstructions or the vectoring to an
interrupt address.
9.5.1
Accessing the Stack
The stack is accessible through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack
Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into
TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will
position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and
underflow.
Important:ꢀ Care should be taken when modifying the STKPTR while interrupts are enabled.
During normal program operation, CALL, CALLWand interrupts will increment STKPTR while RETLW, RETURN, and
RETFIEwill decrement STKPTR. STKPTR can be monitored to obtain the value of stack memory left at any given
time. The STKPTR always points at the currently used place on the stack. Therefore, a CALLor CALLWwill increment
the STKPTR and then write the PC, and a return will unload the PC value from the stack and then decrement the
STKPTR.
Reference the following figures for examples of accessing the stack.
DS40002195A-page 50
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-9.ꢀAccessing the Stack Example 1
Rev. 10-000043A
7/30/2013
Stack Reset Disabled
STKPTR = 0x1F
TOSH:TOSL
0x0F
(STVREN = 0)
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x1F
Initial Stack Configuration:
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return ‘0’. If the
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
Stack Reset Enabled
STKPTR = 0x1F
TOSH:TOSL
0x0000
(STVREN = 1)
Figure 9-10.ꢀAccessing the Stack Example 2
Rev. 10-000043B
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURNinstruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
STKPTR = 0x00
TOSH:TOSL
0x00
Return Address
DS40002195A-page 51
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Memory Organization
Figure 9-11.ꢀAccessing the Stack Example 3
Rev. 10-000043C
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
After seven CALLs or six CALLs and an
interrupt, the stack looks like the figure on
the left. A series of RETURN instructions will
repeatedly place the return addresses into
the Program Counter and pop the stack.
STKPTR = 0x06
TOSH:TOSL
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Figure 9-12.ꢀAccessing the Stack Example 4
Rev. 10-000043D
7/30/2013
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
Return Address
When the stack is full, the next CALL or
an interrupt will set the Stack Pointer to
0x10. This is identical to address 0x00 so
the stack will wrap and overwrite the
return address at 0x00. If the Stack
Overflow/Underflow Reset is enabled, a
Reset will occur and location 0x00 will
not be overwritten.
STKPTR = 0x10
TOSH:TOSL
0x00
DS40002195A-page 52
Preliminary Datasheet
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Memory Organization
9.5.2
Overflow/Underflow Reset
If the STVREN bit is programmed to ‘1’, the device will be Reset if the stack is PUSHed beyond the sixteenth level or
POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively).
9.6
Indirect Addressing
The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the
register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two
INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn
register value is created by the pair FSRnH and FSRnL.
The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are
divided into three memory regions:
•
•
•
Traditional/Banked Data Memory
Linear Data Memory
Program Flash Memory
Figure 9-13.ꢀIndirect Addressing PIC16F152
Rev. 10-000044F
1/13/2017
0x0000
0x0000
Traditional
Data Memory
0x1FFF
0x2000
Linear
Data Memory
0X2FEF
0X2FF0
Reserved
0x7FFF
FSR
Address
0x8000
PC value = 0x000
Range
Program
Flash Memory
0x87FF
PC value = 0x7FF
DS40002195A-page 53
Preliminary Datasheet
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Memory Organization
9.6.1
Traditional/Banked Data Memory
The traditional or banked data memory is a region from FSR address 0x0000 to FSR address 0x1FFF. The
addresses correspond to the absolute addresses of all SFR, GPR and common registers.
Figure 9-14.ꢀTraditional/Banked Data Memory Map
Rev. 10-000056B
12/14/2016
Direct Addressing
From Opcode
Indirect Addressing
BSR
5
0
6
0
7
FSRxH
0
7
FSRxL
0
0 0 0
Bank Select Location Select
000000 000001 000010
Bank Select
111111
Location Select
0x00
0x7F
Bank 63
Bank 0 Bank 1 Bank 2
9.6.2
Linear Data Memory
The linear data memory is the region from FSR address 0x2000 to FSR address 0x2FEF. This region is a virtual
region that points back to the 80-byte blocks of GPR memory in all the banks. Refer to Figure 9-15 for the Linear
Data Memory Map.
Figure 9-15.ꢀLinear Data Memory Map
Rev. 10-000057B
8/24/2016
7
FSRnH
0
7
FSRnL
0
Location Select
0x2000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
0x120
Bank 2
0x16F
0x1920
Bank 50
0x196F
0x2FEF
DS40002195A-page 54
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Memory Organization
Important:ꢀ The address range 0x2000 to 0x2FEF represents the complete addressable Linear Data
Memory for PIC® devices (up to Bank 50). The actual implemented Linear Data Memory will differ from one
device to the other in a family.
Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80
bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.
The 16 bytes of common memory are not included in the linear data memory region.
9.6.3
Program Flash Memory
To make constant data access easier, the entire Program Flash Memory is mapped to the upper half of the FSR
address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be
accessed through INDF. Only the lower eight bits of each memory location are accessible via INDF. Writing to the
Program Flash Memory cannot be accomplished via the FSR/INDF interface. All instructions that access Program
Flash Memory via the FSR/INDF interface will require one additional instruction cycle to complete.
Figure 9-16.ꢀProgram Flash Memory Map
Rev. 10-000058A
7/31/2013
7
1
FSRnH
0
7
FSRnL
0
Location Select
0x8000
0x0000
Program
Flash
Memory
(low 8 bits)
0x7FFF
0xFFFF
9.7
Register Definitions: Memory Organization
DS40002195A-page 55
Preliminary Datasheet
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Memory Organization
9.7.1
INDF0
Name:ꢀ
INDF0
Address:ꢀ 0x000
Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR0 register is the target
for all operations involving the INDF0 register.
Bit
7
6
5
4
3
2
1
0
INDF0[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INDF0[7:0]
Indirect data pointed to by the FSR0 register
DS40002195A-page 56
Preliminary Datasheet
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Memory Organization
9.7.2
INDF1
Name:ꢀ
INDF1
Address:ꢀ 0x001
Indirect Data Register. This is a virtual register. The GPR/SFR register addressed by the FSR1 register is the target
for all operations involving the INDF1 register.
Bit
7
6
5
4
3
2
1
0
INDF1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INDF1[7:0]
Indirect data pointed to by the FSR1 register
DS40002195A-page 57
Preliminary Datasheet
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Memory Organization
9.7.3
PCL
Name:ꢀ
PCL
Address:ꢀ 0x002
Low byte of the Program Counter
Bit
7
6
5
4
3
2
1
0
PCL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PCL[7:0]
Provides direct read and write access to the Program Counter
DS40002195A-page 58
Preliminary Datasheet
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Memory Organization
9.7.4
STATUS
Name:ꢀ
STATUS
Address:ꢀ 0x003
Status Register
7
Bit
6
5
4
TO
R
3
PD
R
2
Z
1
DC
R/W
0
0
C
Access
Reset
R/W
0
R/W
0
1
1
Bit 4 – TOꢀTime-Out
Reset States: POR/BOR = 1
All Other Resets = q
Description
Value
1
Set at power-up or by execution of CLRWDTor SLEEPinstruction
0
A WDT time-out occurred
Bit 3 – PDꢀPower-Down
Reset States: POR/BOR = 1
All Other Resets = q
Description
Value
1
Set at power-up or by execution of CLRWDTinstruction
0
Cleared by execution of the SLEEPinstruction
Bit 2 – ZꢀZero
Reset States: POR/BOR = 0
All Other Resets = u
Description
Value
1
0
The result of an arithmetic or logic operation is zero
The result of an arithmetic or logic operation is not zero
Bit 1 – DCꢀ Digit Carry/Borrow(1)
ADDWF, ADDLW, SUBLW, SUBWFinstructions
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
A carry-out from the 4th low-order bit of the result occurred
No carry-out from the 4th low-order bit of the result
Bit 0 – Cꢀ Carry/Borrow(1)
ADDWF, ADDLW, SUBLW, SUBWFinstructions
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
A carry-out from the Most Significant bit of the result occurred
No carry-out from the Most Significant bit of the result occurred
Note:ꢀ
1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the
Source register.
DS40002195A-page 59
Preliminary Datasheet
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Memory Organization
9.7.5
FSR0
Name:ꢀ
FSR0
Address:ꢀ 0x004
Indirect Address Register
The FSR0 value is the address of the data to which the INDF0 register points.
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
FSR0H: Accesses the high byte FSR0[15:8]
FSR0L: Accesses the low byte FSR0[7:0]
Bit
15
14
13
12
11
10
9
8
FSR0[15:8]
FSR0[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – FSR0[15:0]ꢀAddress of INDF0 data
DS40002195A-page 60
Preliminary Datasheet
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Memory Organization
9.7.6
FSR1
Name:ꢀ
FSR1
Address:ꢀ 0x006
Indirect Address Register
The FSR1 value is the address of the data to which the INDF1 register points.
Bit
15
14
13
12
11
10
9
8
FSR1[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
FSR1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – FSR1[15:0]
Address of INDF1 data
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
FSR1H: Accesses the high byte FSR1[15:8]
FSR1L: Accesses the low byte FSR1[7:0]
DS40002195A-page 61
Preliminary Datasheet
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Memory Organization
9.7.7
BSR
Name:ꢀ
BSR
Address:ꢀ 0x008
Bank Select Register
The BSR indicates the data memory bank by writing the bank number into the register. All data memory can be
accessed directly via instructions, or indirectly via FSRs.
Bit
7
6
5
4
3
2
1
0
BSR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 5:0 – BSR[5:0]
Six Most Significant bits of the data memory address
DS40002195A-page 62
Preliminary Datasheet
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Memory Organization
9.7.8
WREG
Name:ꢀ
WREG
Address:ꢀ 0x009
Working Data Register
Bit
7
6
5
4
3
2
1
0
WREG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – WREG[7:0]
DS40002195A-page 63
Preliminary Datasheet
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Memory Organization
9.7.9
PCLATH
Name:ꢀ
PCLATH
Address:ꢀ 0x00A
Program Counter Latches.
Write Buffer for the upper 7 bits of the Program Counter
Bit
7
6
5
4
3
2
1
0
PCLATH[6:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 6:0 – PCLATH[6:0]ꢀHigh PC Latch Register
Holding register for Program Counter bits [6:0]
DS40002195A-page 64
Preliminary Datasheet
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Memory Organization
9.8
Register Summary: Memory Organization
Address
Name
Bit Pos.
0x00
0x01
0x02
0x03
INDF0
INDF1
PCL
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
INDF0[7:0]
INDF1[7:0]
PCL[7:0]
STATUS
TO
PD
Z
DC
C
FSR0[7:0]
FSR0[15:8]
FSR1[7:0]
FSR1[15:8]
0x04
0x06
FSR0
FSR1
0x08
0x09
0x0A
BSR
BSR[5:0]
WREG
PCLATH
WREG[7:0]
PCLATH[6:0]
DS40002195A-page 65
Preliminary Datasheet
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Resets
10.
Resets
There are multiple ways to reset this device:
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
MCLR Reset
WDT Reset
• RESETinstruction
•
•
•
Stack Overflow
Stack Underflow
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR
event.
A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 10-1.
Figure 10-1.ꢀSimplified Block Diagram of On-Chip Reset Circuit
ICSP ꢀProgramming Mode Exit
RESET Instruction
Memory Violation
Stack Underflow
Stack Overflow
VPP/MCLR
MCLRE
WDT Time-out
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
Power-up
Timer
LFINTOSC
PWRTS[1:0]
2
10.1
Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow
rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or
MCLR features can be used to extend the start-up period until all device operation conditions have been met.
10.1.1 Programming Mode Exit
Upon exit of Programming mode, the device will behave as if a POR had just occurred.
DS40002195A-page 66
Preliminary Datasheet
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Resets
10.2
Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and
BOR, complete voltage range coverage for execution protection can be implemented.
The Brown-out Reset module has four operating modes controlled by the BOREN bits. The four operating modes are:
•
•
•
•
BOR is always ON
BOR is OFF when in Sleep
BOR is controlled by software
BOR is always OFF
Refer to Table 10-1 for more information.
The Brown-out Reset voltage level is selectable by configuring the BORV bits.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration
greater than parameter TBORDC, the device will reset and the BOR bit will be cleared, indicating the Brown-out Reset
condition occurred. See Figure 10-2.
10.2.1 BOR is Always ON
When the BOREN bits are programmed to ‘11’, the BOR is always ON. The device start-up will be delayed until the
BOR is ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.
10.2.2 BOR is OFF in Sleep
When the BOREN bits are programmed to ‘10’, the BOR is on, except in Sleep. BOR protection is not active during
Sleep, but device wake-up will be delayed until the BOR can determine that VDD is higher than the BOR threshold.
The device wake-up will be delayed until the BOR is ready.
10.2.3 BOR Controlled by Software
When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit.
The device start-up is not delayed by the BOR ready condition or the VDD level.
BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY
bit.
BOR protection is unchanged by Sleep.
Table 10-1.ꢀBOR Operating Modes
Instruction Execution upon:
BOREN
SBOREN
Device Mode
BOR Mode
Wake-up from
Sleep
Release of POR
Wait for release of BOR
Begins
immediately
11(1)
X
X
Active
Active
(BORRDY = 1)
Wait for release of BOR
Awake
N/A
(BORRDY = 1)
10
X
Wait for release
of BOR
Sleep
Hibernate
N/A
(BORRDY = 1)
1
0
X
X
X
X
Active
Wait for release of BOR
Begins
immediately
01
00
(BORRDY = 1)
Hibernate
Disabled
Begins immediately
DS40002195A-page 67
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Resets
Note:ꢀ
1. In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit
is forced on by the BOREN bits.
Figure 10-2.ꢀBrown-out Situations
Rev. 30-000092A
4/12/2017
VDD
VBOR
Internal
Reset
(1)
TPWRT
VDD
VBOR
Internal
Reset
< TPWRT
(1)
TPWRT
VDD
VBOR
Internal
Reset
(1)
TPWRT
Note:ꢀ TPWRT delay when the PWRTS bits are enabled (PWRTS != 00).
10.2.4 BOR is Always OFF
When the BOREN bits are programmed to ‘00’, the BOR is always disabled. In the configuration, setting the
SBOREN bit will have no affect on BOR operations.
10.3
MCLR Reset
The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit
and the LVP bit (see Table 10-2). The RMCLR bit will be set to ‘0’ if a MCLR has occurred.
Table 10-2.ꢀMCLR Configuration
MCLRE
LVP
1
MCLR
Enabled
Enabled
Disabled
x
1
0
0
0
10.3.1 MCLR Enabled
When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD
through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.
Important:ꢀ An internal Reset event (RESETinstruction, BOR, WDT, POR, STKOVF, STKUNF) does not
drive the MCLR pin low.
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Resets
10.3.2 MCLR Disabled
When MCLR is disabled, the MCLR becomes input-only and pin functions such as internal weak pull-ups are under
software control.
10.4
10.5
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDTinstruction within the time-out
period. The TO, PD and RWDT bits are changed to indicate a WDT Reset caused by the timer overflowing.
RESET Instruction
A RESETinstruction will cause a device Reset. The RI bit will be set to ‘0’. See Table 10-4 for default conditions after
a RESETinstruction has occurred.
10.6
10.7
Stack Overflow/Underflow Reset
The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits indicate the Reset
condition. These Resets are enabled by setting the STVREN bit.
Power-up Timer (PWRT)
The Power-up Timer provides up to a 64 ms time-out period on POR or Brown-out Reset. The device is held in Reset
as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level.
The Power-up Timer is controlled by the PWRTS bits.
The Power-up Timer starts after the release of the POR and BOR.
For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00000607).
10.8
Start-up Sequence
Upon the release of a POR or BOR, the following must occur before the device will begin executing:
1. Power-up Timer runs to completion (if enabled).
2. MCLR must be released (if enabled).
The Power-up Timer runs independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer will
expire. Upon bringing MCLR high, the device will begin execution after ten FOSC cycles (see Figure 10-3). This is
useful for testing purposes or for synchronizing more than one device operating in parallel.
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Resets
Figure 10-3.ꢀReset Start-up Sequence
VDD
Internal POR
Power-up Timer
MCLR
TPWRT
Internal RESET
Int. Oscillator
FOSC
Begin Execution
code execution (1)
code execution (1)
Internal Oscillator, PWRTS = 00
Internal Oscillator, PWRTS ꢀ00
VDD
Internal POR
Power-up Timer
MCLR
TPWRT
Internal RESET
Ext. Clock (EC)
FOSC
Begin Execution
code execution (1)
code execution (1)
External Clock (EC modes), PWRTS = 00
External Clock (EC modes), PWRTS ꢀ00
Note:ꢀ
1. Code execution begins 10 FOSC cycles after the FOSC clock is released.
10.9
Memory Execution Violation
A memory execution violation Reset occurs if executing an instruction being fetched from outside the valid execution
area. The invalid execution areas are:
1. Addresses outside implemented program memory. Refer to the “Memory Organization” chapter for details
about available Flash size.
2. Storage Area Flash (SAF) inside program memory, if it is enabled
When a memory execution violation is generated, the device is reset and the MEMV bit is cleared to signal the cause
of the Reset. The MEMV bit must be set in the user code after a memory execution violation Reset has occurred to
detect further violation Resets.
10.10 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS, PCON0 and PCON1 registers are updated to indicate the cause of the
Reset. The following tables show the Reset conditions of these registers.
Table 10-3.ꢀReset Status Bits and Their Significance
STKOVF STKUNF RWDT RMCLR
RI
POR
BOR
TO
PD
MEMV
Condition
0
0
0
0
1
1
1
1
1
0
x
1
1
1
Power-on Reset
Illegal, TO is set on
POR
1
1
0
0
x
x
0
x
x
0
u
u
Illegal, PD is set on
POR
0
0
1
1
DS40002195A-page 70
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Resets
...........continued
STKOVF STKUNF RWDT RMCLR
RI
1
POR
BOR
TO
1
PD
1
MEMV
Condition
Brown-out Reset
WDT Reset
0
u
0
u
u
0
1
u
u
u
0
u
u
u
u
0
u
WDT Wake-up
from Sleep
u
u
u
u
u
u
u
u
u
u
u
u
u
u
0
1
0
0
u
u
Interrupt Wake-up
from Sleep
MCLR Reset
during normal
operation
u
u
u
0
u
u
u
u
u
1
MCLR Reset
during Sleep
u
u
u
u
u
u
0
u
u
0
u
u
u
u
1
u
0
u
u
u
RESETInstruction
Executed
Stack Overflow
Reset (STVREN =
1)
1
u
u
u
u
u
u
u
u
u
Stack Underflow
Reset (STVREN =
1)
u
u
1
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
u
0
Memory Violation
Reset
Table 10-4.ꢀReset Conditions for Special Registers
Program
Counter
STATUS
Register
PCON1
Register
Condition
PCON0 Register
0
0
0
0
0
---1 1000
---1 1000
-uuu uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
-uuu uuuu
0011 110x
0011 11u0
uuuu 0uuu
uuuu 0uuu
uuu0 uuuu
uuuu uuuu
uuuu uuuu
uuuu u0uu
1uuu uuuu
u1uu uuuu
uuuu uuuu
---- --1-
---- --u-
---- --1-
---- --u-
---- --u-
---- --u-
---- --u-
---- --u-
Power-on Reset
Brown-out Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Time-out Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
RESETInstruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Memory Violation Reset
PC + 1
PC + 1(1)
0
0
0
0
---- --u-
---- --u-
---- --0-
Legend: u= unchanged, x= unknown, — = unimplemented bit, reads as ‘0’.
Note:ꢀ
1. When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
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Resets
10.11 Power Control (PCONx) Register
The Power Control (PCONx) registers contain flag bits to differentiate between a:
•
•
•
•
•
•
•
•
Brown-out Reset (BOR)
Power-on Reset (POR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
Memory Violation Reset (MEMV)
Hardware will change the corresponding register bit during the Reset process; if the Reset was not caused by the
condition, the bit remains unchanged.
Software should reset the bit to the Inactive state after restart (hardware will not reset the bit).
Software may also set any PCONx bit to the Active state, so that user code may be tested, but no Reset action will
be generated.
10.12 Register Definitions: Power Control
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Resets
10.12.1 BORCON
Name:ꢀ
BORCON
Address:ꢀ 0x811
Brown-out Reset Control Register
Bit
7
SBOREN
R/W
6
5
4
3
2
1
0
BORRDY
Access
Reset
R
q
1
Bit 7 – SBORENꢀSoftware Brown-out Reset Enable
Reset States: POR/BOR = 1
All Other Resets = u
Value
Condition
Description
—
1
0
If BOREN ≠ 01
If BOREN = 01
If BOREN = 01
SBOREN is read/write, but has no effect on the BOR.
BOR Enabled
BOR Disabled
Bit 0 – BORRDYꢀBrown-out Reset Circuit Ready Status
Reset States: POR/BOR = q
All Other Resets = u
Value
Description
1
0
The Brown-out Reset circuit is active and armed
The Brown-out Reset circuit is disabled or is warming up
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Resets
10.12.2 PCON0
Name:ꢀ
PCON0
Address:ꢀ 0x813
Power Control Register 0
Bit
7
6
5
4
3
2
1
POR
R/W/HC
0
0
BOR
R/W/HC
q
STKOVF
R/W/HS
0
STKUNF
R/W/HS
0
RWDT
R/W/HC
1
RMCLR
R/W/HC
1
RI
R/W/HC
1
Access
Reset
Bit 7 – STKOVFꢀStack Overflow Flag
Reset States: POR/BOR = 0
All Other Resets = q
Value
Description
1
A Stack Overflow occurred (more CALLs than fit on the stack)
0
A Stack Overflow has not occurred or set to ‘0’ by firmware
Bit 6 – STKUNFꢀStack Underflow Flag
Reset States: POR/BOR = 0
All Other Resets = q
Value
Description
1
A Stack Underflow occurred (more RETURNs than CALLs)
0
A Stack Underflow has not occurred or set to ‘0’ by firmware
Bit 4 – RWDTꢀWDT Reset Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
1
0
Description
A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware
A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset occurs)
Bit 3 – RMCLRꢀ MCLR Reset Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A MCLR Reset has not occurred or set to ‘1’ by firmware
0
A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
Bit 2 – RIꢀ RESETInstruction Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A RESETinstruction has not been executed or set to ‘1’ by firmware
0
A RESETinstruction has been executed (set to ‘0’ in hardware upon executing a RESETinstruction)
Bit 1 – PORꢀPower-on Reset Status
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
No Power-on Reset occurred or set to ‘1’ by firmware
0
A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)
Bit 0 – BORꢀBrown-out Reset Status
Reset States: POR/BOR = q
DS40002195A-page 74
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Resets
All Other Resets = u
Value
Description
1
No Brown-out Reset occurred or set to ‘1’ by firmware
0
A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)
DS40002195A-page 75
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Resets
10.12.3 PCON1
Name:ꢀ
PCON1
Address:ꢀ 0x814
Power Control Register 1
Bit
7
6
5
4
3
2
1
0
MEMV
R/W/HC
1
Access
Reset
Bit 1 – MEMVꢀMemory Violation Flag
Reset States: POR/BOR = 1
All Other Resets = u
Value
1
0
Description
No Memory Violation Reset occurred or set to ‘1’ by firmware.
A Memory Violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs)
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Resets
10.13 Register Summary: Power Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x0810
0x0811
0x0812
0x0813
0x0814
BORCON
Reserved
PCON0
7:0
SBOREN
STKOVF
BORRDY
7:0
7:0
STKUNF
RWDT
RMCLR
RI
POR
BOR
PCON1
MEMV
DS40002195A-page 77
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OSC - Oscillator Module
11.
OSC - Oscillator Module
11.1
Oscillator Module Overview
The oscillator module contains multiple clock sources and selection features that allow it to be used in a wide range
of applications while maximizing performance and minimizing power consumption.
Clock sources can be supplied either internally or externally. External sources include:
•
External Clock (EC) oscillators
Internal sources include:
•
•
•
High-Frequency Internal Oscillator (HFINTOSC)
Low-Frequency Internal Oscillator (LFINTOSC)
Analog-to-Digital Converter RC Oscillator (ADCRC)
Special features of the oscillator module include:
HFINTOSC Frequency Adjustment: Provides the ability to adjust the HFINTOSC frequency.
•
The Reset Oscillator (RSTOSC) Configuration bits determine the type of oscillator that will be used when the device
runs after a Reset, including when the device is first powered up (see Table 11-1).
Table 11-1.ꢀRSTOSC Selection Table
SFR Reset Values
RSTOSC
Clock Source
COSC
11
OSCFRQ
11
10
01
00
EXTOSC per FEXTOSC
HFINTOSC @ 1 MHz
LFINTOSC
10
100(16 MHz)
01
00
HFINTOSC @ 32 MHz
If an external clock source is selected by the RSTOSC bits, the External Oscillator Mode Select (FEXTOSC)
Configuration bits must be used to select the external clock mode. These modes include:
•
•
ECL: External Clock Low-Power mode
ECH: External Clock High-Power mode
The ECH and ECL modes rely on an external logic-level signal as the device clock source. Each mode is optimized
for a specific frequency range. The internal oscillator block produces both low-frequency and high-frequency clock
signals, designated LFINTOSC and HFINTOSC, respectively. Multiple system operating frequencies may be derived
from these clock sources.
Figure 11-1 illustrates a block diagram of the oscillator module.
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OSC - Oscillator Module
Figure 11-1.ꢀClock Source Block Diagram
COSC[1:0]
CLKIN
ECIN
External
Oscillator
(EXTOSC)
11
10
01
00
Sleep
System Clock
LFINTOSC
Peripheral
SYSCMD
Clock
31kHz
Oscillator
Sleep
2x PLL Mode
HFINTOSC
FRQ[2:0]
1 – 32 MHz
MFINTOSC
Oscillator
500 kHz
To Peripherals
To Peripherals
To Peripherals
31.25 kHz
11.2
Clock Source Types
Clock sources can be classified as external or internal.
External clock sources rely on external circuitry for the clock source to function. Examples of external clock sources
include:
•
Digital oscillator modules
Internal clock sources are contained within the oscillator module. The internal oscillator block features two internal
oscillators that are used to generate internal system clock sources. The High-Frequency Internal Oscillator
(HFINTOSC) can produce a wide range of frequencies which are determined via the HFINTOSC Frequency Selection
(OSCFRQ) register. The Low-Frequency Internal Oscillator (LFINTOSC) generates a fixed nominal 31 kHz clock
signal. The internal oscillator block also features an RC oscillator (ADCRC) which is dedicated to the Analog-to-
Digital Converter (ADC).
The instruction clock (FOSC/4) can be routed to the CLKOUT pin when the pin is not in use. The Clock Out Enable
(CLKOUTEN) Configuration bit controls the functionality of the CLKOUT signal. When CLKOUTEN is clear
(CLKOUTEN = 0), the CLKOUT signal is routed to the CLKOUT pin. When CLKOUTEN is set (CLKOUTEN = 1), the
CLKOUT pin functions as an I/O pin.
11.2.1
External Clock Sources
An external clock source can be used as the device system clock by performing the following actions:
•
•
Program the RSTOSC Configuration bits to select an external clock source that will be used as the default
system clock upon a device Reset.
Program the FEXTOSC Configuration bits to select either the ECH (16 MHz and higher) or ECL (below 16 MHz)
mode based on the frequency of the external clock.
11.2.1.1 EC Mode
The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When
operating in EC mode, an external clock source is connected to the CLKIN input pin. The CLKOUT pin is available as
a general purpose I/O pin or as the CLKOUT signal pin.
DS40002195A-page 79
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OSC - Oscillator Module
EC mode provides two power mode selections:
•
•
ECH: High-power mode
ECL: Low-power mode
When EC mode is selected, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep.
Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device
while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had
elapsed.
Figure 11-2 shows the pin connections for EC mode.
Figure 11-2.ꢀExternal Clock (EC) Mode Operation
External Clock
PIC® MCU
Source
CLKIN
CLKOUT (FOSC / 4)
or I/O(1)
CLKOUT
Note:ꢀ
1. Output depends on the setting of the CLKOUTEN Configuration bit.
11.2.2
Internal Clock Sources
The internal oscillator block contains two independent oscillators that can produce two internal system clock sources:
•
•
High-Frequency Internal Oscillator (HFINTOSC)
Low-Frequency Internal Oscillator (LFINTOSC)
An internal oscillator source can be used as the device system clock by programming the RSTOSC Configuration bits
to select one of the INTOSC sources.
In INTOSC mode, the CLKIN and CLKOUT pins are available for use as general purpose I/Os, provided that no
external oscillator is connected. The function of the CLKOUT pin is determined by the CLKOUTEN Configuration bit.
When CLKOUTEN is set (CLKOUTEN = 1), the pin functions as a general purpose I/O. When CLKOUTEN is clear
(CLKOUTEN = 0), the system instruction clock (FOSC/4) is available as an output signal on the pin.
11.2.2.1 HFINTOSC
The High-Frequency Internal Oscillator (HFINTOSC) is a factory-calibrated, precision digitally-controlled internal
clock source that produces a wide range of stable clock frequencies. The HFINTOSC can be enabled by
programming the RSTOSC Configuration bits to select the one of two HFINTOSC options upon device Reset or
power-up.
The HFINTOSC frequency is selected via the HFINTOSC Frequency Selection (FRQ) bits. Fine-tuning of the
HFINTOSC is done via the HFINTOSC Frequency Tuning (TUN) bits.
11.2.2.1.1 HFINTOSC Frequency Tuning
The HFINTOSC frequency can be fine-tuned via the HFINTOSC Tuning Register (OSCTUNE). The OSCTUNE
register provides small adjustments to the HFINTOSC nominal frequency.
The OSCTUNE register contains the HFINTOSC Frequency Tuning (TUN) bits. The TUN bits default to a 6-bit, two’s
compliment value of 0x00, which indicates that the oscillator is operating at the selected frequency. When a value
between 0x01 and 0x1F is written to the TUN bits, the HFINTOSC frequency is increased. When a value between
0x3F and 0x20 is written to the TUN bits, the HFINTOSC frequency is decreased.
When the OSCTUNE register is modified, the oscillator will begin to shift to the new frequency. Code execution
continues during this shift. There is no indication that the frequency shift occurred.
DS40002195A-page 80
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OSC - Oscillator Module
Important:ꢀ OSCTUNE tuning does not affect the LFINTOSC frequency.
11.2.2.1.2 MFINTOSC
The Medium-Frequency Internal Oscillator (MFINTOSC) generates two constant clock outputs (500 kHz and 31.25
kHz). The MFINTOSC clock signals are created from the HFINTOSC using dynamic divider logic, which provides
constant MFINTOSC clock rates regardless of selected HFINTOSC frequency.
The MFINTOSC cannot be used as the system clock, but can be used as a clock source for certain peripherals, such
as a Timer.
11.2.2.2 LFINTOSC
The Low-Frequency Internal Oscillator (LFINTOSC) is a factory-calibrated 31 kHz internal clock source.
The LFINTOSC can be used as a system clock source, and may be used by certain peripheral modules as a clock
source. Additionally, the LFINTOSC provides a time base for the following:
•
•
Power-up Timer (PWRT)
Watchdog Timer (WDT)
The LFINTOSC is enabled by programming the RSTOSC Configuration bits to select LFINTOSC.
11.3
Register Definitions: Oscillator Control
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OSC - Oscillator Module
11.3.1
OSCCON
Name:ꢀ
OSCCON
Address:ꢀ 0x88E
Oscillator Control Register
Bit
7
6
5
4
3
2
1
0
COSC[1:0]
Access
Reset
R
q
R
q
Bits 5:4 – COSC[1:0]ꢀCurrent Oscillator Source Select
Indicates the current oscillator source per the RSTOSC Configuration bits
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OSC - Oscillator Module
11.3.2
OSCSTAT
Name:ꢀ
OSCSTAT
Address:ꢀ 0x890
Oscillator Status Register
Bit
7
6
HFOR
R
5
MFOR
R
4
LFOR
R
3
2
ADOR
R
1
SFOR
R
0
Access
Reset
0
0
0
0
0
Bit 6 – HFORꢀHFINTOSC Ready
Value
1
0
Description
The HFINTOSC is ready for use
The HFINTOSC is not enabled, or it is not ready for use
Bit 5 – MFORꢀMFINTOSC Ready
Value
Description
1
0
The MFINTOSC is ready for use
The MFINTOSC is not enabled, or it is not ready for use
Bit 4 – LFORꢀLFINTOSC Ready
Value
Description
1
0
The LFINTOSC is ready for use
The LFINTOSC is not enabled, or is not ready for use
Bit 2 – ADORꢀADCRC Oscillator Ready
Value
Description
1
0
The ADCRC oscillator is ready for use
The ADCRC oscillator is not enabled, or is not ready for use
Bit 1 – SFORꢀSpecial Frequency Oscillator is Ready
Value
Description
1
0
The SFINTOSC is ready for use
The SFINTOSC is not ready for use
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OSC - Oscillator Module
11.3.3
OSCEN
Name:ꢀ
OSCEN
Address:ꢀ 0x891
Oscillator Enable Register
Bit
7
6
HFOEN
R/W
0
5
MFOEN
R/W
0
4
LFOEN
R/W
0
3
2
ADOEN
R/W
0
1
0
Access
Reset
Bit 6 – HFOENꢀHFINTOSC Enable
Value
Description
1
0
HFINTOSC is explicitly enabled, operating as specified by the OSCFRQ register
HFINTOSC can be enabled by a peripheral request
Bit 5 – MFOENꢀMFINTOSC Enable
Value
Description
1
0
MFINTOSC is explicitly enabled
MFINTOSC can be enabled by a peripheral request
Bit 4 – LFOENꢀLFINTOSC Enable
Value
Description
1
0
LFINTOSC is explicitly enabled
LFINTOSC can be enabled by a peripheral request
Bit 2 – ADOENꢀADCRC Oscillator Enable
Value
Description
1
0
ADCRC is explicitly enabled
ADCRC may be enabled by a peripheral request
DS40002195A-page 84
Preliminary Datasheet
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OSC - Oscillator Module
11.3.4
OSCFRQ
Name:ꢀ
OSCFRQ
Address:ꢀ 0x893
HFINTOSC Frequency Selection Register
Bit
7
6
5
4
3
2
1
FRQ[2:0]
R/W
0
Access
Reset
R/W
0
R/W
0
0
Bits 2:0 – FRQ[2:0]ꢀHFINTOSC Frequency Selection
FRQ
Nominal Freq (MHz)
111-110
101
Reserved
32
16
8
100
011
010
4
001
2
000
1
DS40002195A-page 85
Preliminary Datasheet
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OSC - Oscillator Module
11.3.5
OSCTUNE
Name:ꢀ
OSCTUNE
Address:ꢀ 0x892
HFINTOSC Frequency Tuning Register
Bit
7
6
5
4
3
2
1
0
TUN[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 5:0 – TUN[5:0]ꢀHFINTOSC Frequency Tuning
TUN
Condition
01 1111
Maximum frequency
•
•
•
•
•
•
00 0000
Center frequency. Oscillator is operating at the selected nominal frequency. (Default value)
•
•
•
•
•
•
10 0000
Minimum frequency
DS40002195A-page 86
Preliminary Datasheet
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OSC - Oscillator Module
11.4
Register Summary: Oscillator Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x088D
0x088E
0x088F
0x0890
0x0891
0x0892
0x0893
OSCCON
Reserved
OSCSTAT
OSCEN
7:0
COSC[1:0]
7:0
7:0
7:0
7:0
HFOR
MFOR
MFOEN
LFOR
ADOR
SFOR
HFOEN
LFOEN
ADOEN
OSCTUNE
OSCFRQ
TUN[5:0]
FRQ[2:0]
DS40002195A-page 87
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Interrupts
12.
Interrupts
The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the
source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode.
Many peripherals can produce interrupts. Refer to the corresponding chapters for details.
A block diagram of the interrupt logic is shown in Figure 12-1.
Figure 12-1.ꢀInterrupt Logic
TMR0IF
TMR0IE
Wake-up
(If in Sleep mode)
INTF
INTE
Peripheral Interrupts
PIR0
PIE0
IOCIF
IOCIE
Interrupt
to CPU
PEIE
GIE
PIRn
PIEn
12.1
12.2
12.3
12.4
INTCON Register
The Interrupt Control (INTCON) register is readable and writable, and contains the Global Interrupt Enable (GIE),
Peripheral Interrupt Enable (PEIE), and External Interrupt Edge Select (INTEDG) bits.
PIE Registers
The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts. Due to
the number of peripheral interrupt sources, there are three PIE registers in the PIC16F152 family.
PIR Registers
The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts. Due to
the number of peripheral interrupt sources, there are three PIR registers.
Operation
Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:
•
•
•
GIE bit
PEIE bit (if the Interrupt Enable bit of the interrupt event is contained in the PIE registers)
Interrupt Enable bit(s) for the specific interrupt event(s)
The PIR registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the
status of the GIE, PEIE and individual interrupt enable bits.
DS40002195A-page 88
Preliminary Datasheet
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Interrupts
The following events happen when an interrupt event occurs while the GIE bit is set:
•
•
•
•
•
Current prefetched instruction is flushed
GIE bit is cleared
Current Program Counter (PC) is pushed onto the stack
Critical registers are automatically saved to the shadow registers (see “Automatic Context Saving”)
PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the
interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because
the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but
will not cause the processor to redirect to the interrupt vector.
The RETFIEinstruction exits the ISR by popping the previous address from the stack, restoring the saved context
from the shadow registers and setting the GIE bit.
For additional information on a specific interrupts operation, refer to its peripheral chapter.
Important:ꢀ
1. Individual interrupt flag bits are set, regardless of the state of any other enable bits.
2. All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is
clear will be serviced when the GIE bit is set again.
12.5
Interrupt Latency
Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the
interrupt vector begins. The interrupt is sampled during Q1 of the instruction cycle. The actual interrupt latency then
depends on the instruction that is executing at the time the interrupt is detected. See the following figures for more
details.
Figure 12-2.ꢀInterrupt Latency
Rev. 10-000269E
8/31/2016
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT
INT
pin
Valid Interrupt
window(1)
1 Cycle Instruction at PC
PC = 0x0004
NOP
PC - 1
PC - 2
PC
PC + 1
PC
PC = 0x0005 PC = 0x0006
PC = 0x0004 PC = 0x0005
Fetch
PC - 1
NOP
Execute
Indeterminate
Latency(2)
Latency
DS40002195A-page 89
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Interrupts
Figure 12-3.ꢀINT Pin Interrupt Timing
Rev. 30-000150A
6/27/2017
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(4)
INT pin
INTF
(1)
(1)
(2)
(5)
Interrupt Latency
GIE
INSTRUCTION FLOW
PC
PC + 1
—
0004h
0005h
PC
Inst (PC)
PC + 1
Instruction
Fetched
Inst (0004h)
Inst (PC + 1)
Inst (0005h)
Inst (0004h)
Instruction
Executed
For ced NOP
For ced NOP
Inst (PC)
Inst (PC – 1)
Note:ꢀ
1. INTF flag is sampled here (every Q1).
2. Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3. For minimum width of INT pulse, refer to AC specifications in the “Electrical Specifications” chapter.
4. INTF may be set any time during the Q4-Q1 cycles.
12.6
12.7
Interrupts During Sleep
Interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the
system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the
processor will continue executing instructions after the SLEEPinstruction. The instruction directly after the SLEEP
instruction will always be executed before branching to the ISR.
INT Pin
The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting
the External Interrupt Enable (INTE) bit. The External Interrupt Edge Select (INTEDG) bit determines on which edge
the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is
clear, the falling edge will cause the interrupt. The External Interrupt Flag (INTF) bit will be set when a valid edge
appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the
interrupt vector.
12.8
Automatic Context Saving
Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are
automatically saved in the shadow registers:
•
•
•
WREG register
STATUS register (except for TO and PD)
BSR register
DS40002195A-page 90
Preliminary Datasheet
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Interrupts
•
•
FSR registers
PCLATH register
Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these
registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow
register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in
Bank 63 and are readable and writable. Depending on the user’s application, other registers may also need to be
saved.
12.9
Register Definitions: Interrupt Control
DS40002195A-page 91
Preliminary Datasheet
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Interrupts
12.9.1 INTCON
Name:ꢀ
INTCON
Address:ꢀ 0x00B
Interrupt Control Register
Bit
7
GIE
R/W
0
6
PEIE
R/W
0
5
4
3
2
1
0
INTEDG
R/W
1
Access
Reset
Bit 7 – GIEꢀGlobal Interrupt Enable
Value
Description
1
0
Enables all active interrupts
Disables all interrupts
Bit 6 – PEIEꢀPeripheral Interrupt Enable
Value
Description
1
0
Enables all active peripheral interrupts
Disables all peripheral interrupts
Bit 0 – INTEDGꢀExternal Interrupt Edge Select
Value
Description
1
0
Interrupt on rising edge of INT pin
Interrupt on falling edge of INT pin
Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt. This feature allows for software polling.
DS40002195A-page 92
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Interrupts
12.9.2 PIE0
Name:ꢀ
PIE0
Address:ꢀ 0x716
Peripheral Interrupt Enable Register 0
Bit
7
6
5
TMR0IE
R/W
0
4
IOCIE
R/W
0
3
2
1
0
INTE
R/W
0
Access
Reset
Bit 5 – TMR0IEꢀTimer0 Interrupt Enable
Value
Description
1
0
TMR0 interrupts are enabled
TMR0 interrupts are disabled
Bit 4 – IOCIEꢀInterrupt-on-Change Enable
Value
Description
1
0
IOC interrupts are enabled
IOC interrupts are disabled
Bit 0 – INTEꢀ External Interrupt Enable(1)
Value
Description
1
0
External interrupts are enabled
External interrupts are disabled
Note:ꢀ
1. The External Interrupt INT pin is selected by INTPPS.
2. Bit PEIE in the INTCON register must be set to enable any peripheral interrupt controlled by the PIE1 and
PIE2 registers. Interrupt sources controlled by the PIE0 register do not require the PEIE bit to be set in order to
allow interrupt vectoring (when the GIE bit in the INTCON register is set).
DS40002195A-page 93
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Interrupts
12.9.3 PIE1
Name:ꢀ
PIE1
Address:ꢀ 0x717
Peripheral Interrupt Enable Register 1
Bit
7
CCP1IE
R/W
0
6
TMR2IE
R/W
0
5
TMR1IE
R/W
0
4
RC1IE
R/W
0
3
TX1IE
R/W
0
2
BCL1IE
R/W
0
1
SSP1IE
R/W
0
0
ADIE
R/W
0
Access
Reset
Bit 7 – CCP1IEꢀCCP1 Interrupt Enable
Value
Description
1
0
CCP1 interrupts are enabled
CCP1 interrupts are disabled
Bit 6 – TMR2IEꢀTMR2 Interrupt Enable
Value
Description
1
0
TMR2 interrupts are enabled
TMR2 interrupts are disabled
Bit 5 – TMR1IEꢀTMR1 Interrupt Enable
Value
Description
1
0
TMR1 interrupts are enabled
TMR1 interrupts are disabled
Bit 4 – RC1IEꢀEUSART1 Receive Interrupt Enable
Value
Description
1
0
EUSART1 receive interrupts are enabled
EUSART1 receive interrupts are disabled
Bit 3 – TX1IEꢀEUSART1 Transmit Interrupt Enable
Value
Description
1
0
EUSART1 transmit interrupts are enabled
EUSART1 transmit interrupts are disabled
Bit 2 – BCL1IEꢀMSSP1 Bus Collision Interrupt Enable
Value
Description
1
0
MSSP1 bus collision interrupts are enabled
MSSP1 bus collision interrupts are disabled
Bit 1 – SSP1IEꢀMSSP1 Interrupt Enable
Value
Description
1
0
MSSP1 interrupts are enabled
MSSP1 interrupts are disabled
Bit 0 – ADIEꢀADC Interrupt Enable
Value
Description
1
0
ADC interrupts are enabled
ADC interrupts are disabled
Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1
and PIE2.
DS40002195A-page 94
Preliminary Datasheet
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Interrupts
12.9.4 PIE2
Name:ꢀ
PIE2
Address:ꢀ 0x718
Peripheral Interrupt Enable Register 2
Bit
7
CCP2IE
R/W
0
6
NVMIE
R/W
0
5
TMR1GIE
R/W
4
3
2
1
0
Access
Reset
0
Bit 7 – CCP2IEꢀCCP2 Interrupt Enable
Value
Description
1
0
CCP2 interrupts are enabled
CCP2 interrupts are disabled
Bit 6 – NVMIEꢀNVM Interrupt Enable
Value
Description
1
0
NVM interrupts are enabled
NVM interrupts are disabled
Bit 5 – TMR1GIEꢀTMR1 Gate Interrupt Enable
Value
Description
1
0
TMR1 Gate interrupts are enabled
TMR1 Gate interrupts are disabled
Note:ꢀ Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1
and PIE2.
DS40002195A-page 95
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Interrupts
12.9.5 PIR0
Name:ꢀ
PIR0
Address:ꢀ 0x70C
Peripheral Interrupt Request Register 0
Bit
7
6
5
4
IOCIF
R
3
2
1
0
INTF
R/W/HS
0
TMR0IF
R/W/HS
0
Access
Reset
0
Bit 5 – TMR0IFꢀTimer0 Interrupt Flag
Value
Description
1
0
TMR0 register has overflowed (must be cleared by software)
TMR0 register has not overflowed
Bit 4 – IOCIFꢀ Interrupt-on-Change Flag(2)
Value
Description
1
One or more of the IOCAF-IOCCF register bits are currently set, indicating an enabled edge was
detected by the IOC module.
0
None of the IOCAF-IOCCF register bits are currently set
Bit 0 – INTFꢀ External Interrupt Flag(1)
Value
Description
1
0
External Interrupt has occurred
External Interrupt has not occurred
Note:ꢀ
1. The External Interrupt INT pin is selected by INTPPS.
2. The IOCIF bit is the logical OR of all the IOCAF-IOCCF flags. Therefore, to clear the IOCIF flag, application
firmware must clear all of the lower level IOCAF-IOCCF register bits.
3. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable (GIE) bit. User software should ensure the appropriate interrupt flag bits are
cleared before enabling an interrupt.
DS40002195A-page 96
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Interrupts
12.9.6 PIR1
Name:ꢀ
PIR1
Address:ꢀ 0x70D
Peripheral Interrupt Request Register 1
Bit
7
6
5
4
RC1IF
R
3
TX1IF
R
2
1
0
ADIF
R/W/HS
0
CCP1IF
R/W/HS
0
TMR2IF
R/W/HS
0
TMR1IF
R/W/HS
0
BCL1IF
R/W/HS
0
SSP1IF
R/W/HS
0
Access
Reset
0
0
Bit 7 – CCP1IFꢀCCP1 Interrupt Flag
CCP Mode
Compare
Value
Capture
PWM
1
0
Capture occurred (must be
cleared in software)
Compare match occurred (must be Output trailing edge occurred (must
cleared in software)
be cleared in software)
Capture did not occur
Compare match did not occur
Output trailing edge did not occur
Bit 6 – TMR2IFꢀTMR2 Interrupt Flag
Value
Description
1
0
Interrupt has occurred (must be cleared in software)
Interrupt event has not occurred
Bit 5 – TMR1IFꢀTMR1 Interrupt Flag
Value
Description
1
0
Interrupt has occurred (must be cleared in software)
Interrupt event has not occurred
Bit 4 – RC1IFꢀ EUSART1 Receive Interrupt Flag(1)
Value
Description
1
0
The EUSART1 receive buffer (RC1REG) is not empty (contains at least one byte)
The EUSART1 receive buffer is empty
Bit 3 – TX1IFꢀ EUSART1 Transmit Interrupt Flag(2)
Value
Description
1
0
The EUSART1 transmit buffer (TX1REG) is empty
The EUSART1 transmit buffer is not empty
Bit 2 – BCL1IFꢀMSSP1 Bus Collision Interrupt Flag
Value
Description
1
0
A bus collision was detected (must be cleared in software)
No bus collision was detected
Bit 1 – SSP1IFꢀMSSP1 Interrupt Flag
Value
Description
1
0
Interrupt has occurred (must be cleared in software)
Interrupt event has not occurred
Bit 0 – ADIFꢀADC Interrupt Flag
Value
Description
1
0
Interrupt has occurred (must be cleared in software)
Interrupt event has not occurred
DS40002195A-page 97
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Interrupts
Note:ꢀ
1. RC1IF is read-only. User software must read RC1REG to clear RC1IF.
2. TX1IF is read-only. User software must load TX1REG to clear TX1IF. TX1IF does not indicate a completed
transmission (use TMRT for this purpose instead).
3. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable (GIE) bit. User software should ensure the appropriate interrupt flag bits are
cleared before enabling an interrupt.
DS40002195A-page 98
Preliminary Datasheet
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Interrupts
12.9.7 PIR2
Name:ꢀ
PIR2
Address:ꢀ 0x70E
Peripheral Interrupt Request Register 2
Bit
7
6
5
4
3
2
1
0
CCP2IF
R/W/HS
0
NVMIF
R/W/HS
0
TMR1GIF
R/W/HS
0
Access
Reset
Bit 7 – CCP2IFꢀCCP2 Interrupt Flag
CCP Mode
Compare
Value
Capture
PWM
1
0
Capture occurred (must be
cleared in software)
Compare match occurred (must be Output trailing edge occurred (must
cleared in software)
be cleared in software)
Capture did not occur
Compare match did not occur
Output trailing edge did not occur
Bit 6 – NVMIFꢀNonvolatile Memory (NVM) Interrupt Flag
Value
Description
1
0
The requested NVM operation has completed (must be cleared in software)
Interrupt event has not occurred
Bit 5 – TMR1GIFꢀTMR1 Gate Interrupt Flag
Value
Description
1
0
The TMR1 Gate has gone inactive (must be cleared in software)
TMR1 Gate is active
Note:ꢀ Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable (GIE) bit. User software should ensure the appropriate interrupt flag bits are cleared
before enabling an interrupt.
DS40002195A-page 99
Preliminary Datasheet
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Interrupts
12.10 Register Summary: Interrupt Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x070B
0x070C
0x070D
0x070E
0x070F
...
PIR0
PIR1
PIR2
7:0
7:0
7:0
TMR0IF
TMR1IF
IOCIF
RC1IF
INTF
ADIF
CCP1IF
CCP2IF
TMR2IF
NVMIF
TX1IF
TX1IE
BCL1IF
BCL1IE
SSP1IF
SSP1IE
TMR1GIF
Reserved
0x0715
0x0716
0x0717
0x0718
PIE0
PIE1
PIE2
7:0
7:0
7:0
TMR0IE
TMR1IE
IOCIE
RC1IE
INTE
ADIE
CCP1IE
CCP2IE
TMR2IE
NVMIE
TMR1GIE
DS40002195A-page 100
Preliminary Datasheet
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Sleep Mode
13.
Sleep Mode
13.1
Sleep Mode Operation
Sleep mode is entered by executing the SLEEPinstruction.
Upon entering Sleep mode, the following conditions exist:
1. Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for
operation during Sleep.
2. The PD bit is cleared.
3. The TO bit is set.
4. The CPU and the System clocks are disabled.
5. LFINTOSC and/or HFINTOSC will remain enabled if any peripheral has requested them as a clock source or if
the HFOEN, MFOEN or LFOEN bits are set.
6. ADC is unaffected if the ADCRC oscillator is selected. When the ADC clock is something other than ADCRC,
a SLEEPinstruction causes the present conversion to be aborted and the ADC module is turned off, although
the ADON bit remains active.
7. I/O ports maintain the status they had before SLEEPwas executed (driving high, low, or high-impedance) only
if no peripheral connected to the I/O port is active.
Refer to individual chapters for more details on peripheral operation during Sleep.
To minimize current consumption, the following conditions should be considered:
•
•
•
•
•
I/O pins should not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using any oscillator
I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused
by floating inputs.
13.1.1 Wake-up from Sleep
The device can wake-up from Sleep through one of the following events:
1. External Reset input on MCLR pin, if enabled.
2. BOR Reset, if enabled.
3. POR Reset.
4. Watchdog Timer, if enabled.
5. Any external interrupt.
6. Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information).
The first three events will cause a device Reset. The last three events are considered a continuation of program
execution. To determine whether a device Reset or wake-up event occurred, refer to the “Determining the Cause of
a Reset” section in the “Resets” chapter.
When the SLEEPinstruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up
through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of
the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP
instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEPinstruction, the device will
then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEPis not
desirable, the user should have a NOPafter the SLEEPinstruction.
The WDT is cleared when the device wakes-up from Sleep, regardless of the source of wake-up.
DS40002195A-page 101
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Sleep Mode
13.1.2 Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and
interrupt flag bit set, one of the following will occur:
•
If the interrupt occurs before the execution of a SLEEPinstruction
– SLEEPinstruction will execute as a NOP
– WDT and WDT prescaler will not be cleared
– TO bit will not be set
– PD bit will not be cleared
•
If the interrupt occurs during or after the execution of a SLEEPinstruction
– SLEEPinstruction will be completely executed
– Device will immediately wake-up from Sleep
– WDT and WDT prescaler will be cleared
– TO bit will be set
– PD bit will be cleared
Even if the flag bits were checked before executing a SLEEPinstruction, it may be possible for flag bits to become set
before the SLEEPinstruction completes. To determine whether a SLEEPinstruction executed, test the PD bit. If the
PD bit is set, the SLEEPinstruction was executed as a NOP.
DS40002195A-page 102
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WDT - Watchdog Timer
14.
WDT - Watchdog Timer
The Watchdog Timer (WDT) is a system timer that generates a Reset event if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog Timer is typically used to reset the processor in the event of a
software malfunction, but can also be used to wake the device when in Sleep mode.
The WDT has the following features:
•
•
Selectable clock sources
Multiple operating modes:
– WDT is always on
– WDT is off when in Sleep
– WDT is controlled by software
– WDT is always off
•
•
•
Configurable time-out period from 1 ms to 256 seconds (nominal)
Multiple Reset conditions
Operation during Sleep
Figure 14-1.ꢀWatchdog Timer (WDT) Block Diagram
WDTE[1:0] = 11
WDTE[1:0] = 10
Sleep
1
0
WDT
Time-out
23-bit WDT Prescaler
Counter
WDTE[1:0] = 01
SEN
CS
PS[4:0]
WDTE[1:0] = 00
14.1
Selectable Clock Sources
The WDT can derive its time base from either the 31.25 kHz MFINTOSC or the 31 kHz LFINTOSC as selected by the
WDT Clock Source Select (CS) bit.
Important:ꢀ Time intervals detailed in this chapter are based on a minimum nominal interval of 1 ms
generated from the LFINTOSC clock source.
14.2
WDT Operating Modes
The WDT module has four operating modes controlled by the Watchdog Timer Enable (WDTE) bits. See Table 14-1.
Table 14-1.ꢀWDT Operating Modes
WDTE[1:0]
SEN
Device Mode
WDT Mode
11
x
X
Active
DS40002195A-page 103
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WDT - Watchdog Timer
...........continued
WDTE[1:0]
SEN
Device Mode
WDT Mode
Active
Awake
10
x
Sleep
Disabled
Active
1
0
x
X
X
X
01
00
Disabled
Disabled
14.2.1 WDT is Always On
When the WDTE bits are set to ‘11’, the WDT is always on. WDT protection is active during Sleep mode.
14.2.2 WDT is Off During Sleep
When the WDTE bits are set to ‘10’, the WDT is on except during Sleep mode. During Sleep mode, WDT protection
is disabled.
14.2.3 WDT Controlled By Software
When the WDTE bits are set to ‘01’, the WDT is controlled by the Software Watchdog Timer Enable (SEN) bit. When
SEN is set (SEN = 1), WDT protection is active. When SEN is clear (SEN = 0), WDT protection is disabled.
14.2.4 WDT is Off
When the WDTE bits are set to ‘00’, the WDT is disabled. In this mode, the SEN bit is ignored.
14.3
14.4
WDT Time-out Period
The Watchdog Timer Prescale Select (PS) bits set the time-out period from 1 ms to 256 seconds (nominal). After a
Reset, the default time-out period is two seconds.
Clearing the WDT
The WDT is cleared when any of the following conditions occur:
•
•
•
•
•
Any Reset
Valid CLRWDTinstruction is executed
Device enters Sleep
Devices wakes up from Sleep
Any write to the WDTCON register
14.5
14.6
WDT Operation During Sleep
When the WDT enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.
When the WDT exits Sleep, the WDT is cleared again.
When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and
resumes operation. The Time-out (TO) and Power-down (PD) bits are cleared to indicate the event. Additionally, the
Watchdog Timer Reset Flag (RWDT) bit is cleared, indicating a WDT Reset event occurred.
Register Definitions: WDT Control
DS40002195A-page 104
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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WDT - Watchdog Timer
14.6.1 WDTCON
Name:ꢀ
WDTCON
Address:ꢀ 0x80C
Watchdog Timer Control Register
Bit
7
CS
R/W
0
6
5
4
3
PS[4:0]
R/W
0
2
1
0
SEN
R/W
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7 – CSꢀWatchdog Timer Clock Source Selection
Value
Description
1
0
MFINTOSC (31.25 kHz)
LFINTOSC (31 kHz)
Bits 5:1 – PS[4:0]ꢀ Watchdog Timer Prescale Selection(1)
Value
Description
11111 -
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved. Results in minimum interval (1:32)
1:8388608 (Interval 256s nominal)
1:4194304 (Interval 128s nominal)
1:2097152 (Interval 64s nominal)
1:1048576 (Interval 32s nominal)
1:524288 (Interval 16s nominal)
1:262144 (Interval 8s nominal)
1:131072 (Interval 4s nominal)
1:65536 (Interval 2s nominal) (Reset value)
1:32768 (Interval 1s nominal)
1:16384 (Interval 512 ms nominal)
1:8192 (Interval 256 ms nominal)
1:4096 (Interval 128 ms nominal)
1:2048 (Interval 64 ms nominal)
1:1024 (Interval 32 ms nominal)
1:512 (Interval 16 ms nominal)
1:256 (Interval 8 ms nominal)
1:128 (Interval 4 ms nominal)
1:64 (Interval 2 ms nominal)
1:32 (Interval 1 ms nominal)
Bit 0 – SENꢀSoftware WDT Enable/Disable
Value
Condition
Description
x
1
0
If WDTE[1:0] ≠ 01
If WDTE[1:0] = 01
If WDTE[1:0] = 01
This bit is ignored
WDT is enabled
WDT is disabled
Note:ꢀ
1. Times are approximate and based on the 31 kHz LFINTOSC clock source.
DS40002195A-page 105
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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WDT - Watchdog Timer
14.7
Register Summary - WDT Control
Address
Name
Bit Pos.
0x00
...
Reserved
WDTCON
0x080B
0x080C
7:0
CS
PS[4:0]
SEN
DS40002195A-page 106
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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NVM - Nonvolatile Memory Control
15.
NVM - Nonvolatile Memory Control
Nonvolatile Memory (NVM) consists of the Program Flash Memory (PFM).
NVM is accessible by using both the FSR and INDF registers, or through the NVMREG register interface.
The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the device.
NVM can be protected in two ways, by either code protection or write protection.
Code protection (CP bit in the Configuration Words) disables access, both reading and writing, to the PFM via
external device programmers. Code protection does not affect the self-write and erase functionality. Code protection
can only be reset by a device programmer performing a Bulk Erase to the device, clearing all nonvolatile memory,
Configuration bits and User IDs.
Write protection prohibits self-write and erase to a portion or all of the NVM, as defined by the WRTSAF, WRTC,
WRTB and WRTAPP bits of the Configuration Words. Write protection does not affect a device programmer’s ability
to read, write or erase the device.
15.1
Program Flash Memory
Program Flash memory consists of an array of 14-bit words as user memory, with additional words for User ID
information, Configuration words and interrupt vectors. Program memory provides storage locations for:
•
•
User program instructions
User defined data
Program memory data can be read and/or written to through:
•
•
•
•
CPU instruction fetch (read-only)
FSR/INDF indirect access (read-only)
NVMREG access
In-Circuit Serial Programming™ (ICSP™)
Read operations return a single word of memory. When write and erase operations are done on a row basis, the row
size is defined. Program memory will erase to a logic ‘1’ and program to a logic ‘0’.
It is important to understand the program memory structure for erase and programming operations. Program memory
is arranged in rows. A row consists of 32 14-bit program memory words. A row is the minimum size that can be
erased by user software.
All or a portion of a row can be programmed. Data to be written into the program memory row is written to 14-bit wide
data write latches. These latches are not directly accessible, but may be loaded via sequential writes to the
NVMDATH:NVMDATL register pair.
Important:ꢀ To modify only a portion of a previously programmed row, the contents of the entire row must
be read. Then, the new data and retained data can be written into the write latches to reprogram the row of
program memory. However, any unprogrammed locations can be written without first erasing the row. In
this case, it is not necessary to save and rewrite the other previously programmed locations.
15.1.1 Program Memory Voltages
The program memory is readable and writable during normal operation over the full VDD range.
15.1.1.1 Programming Externally
The program memory cell and control logic support write and Bulk Erase operations down to the minimum device
operating voltage. Special BOR operation is enabled during Bulk Erase.
DS40002195A-page 107
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NVM - Nonvolatile Memory Control
15.1.1.2 Self-Programming
The program memory cell and control logic will support write and row erase operations across the entire VDD range.
Bulk Erase is not available when self-programming.
15.2
FSR and INDF Access
The FSR and INDF registers allow indirect access to the Program Flash Memory.
15.2.1 FSR Read
With the intended address loaded into an FSR register a MOVIWinstruction or read of INDF will read data from the
program memory.
Reading from NVM requires one instruction cycle. The CPU operation is suspended during the read, and resumes
immediately after. Read operations return a single byte of memory.
15.2.2 FSR Write
Writing/erasing the NVM through the FSR registers (ex. MOVWIinstruction) is not supported in the PIC16F152
devices.
15.3
NVMREG Access
The NVMREG interface allows read/write access to all the locations accessible by FSRs, read/write access to the
User ID locations, and read-only access to the device identification, revision, and configuration data.
Writing or erasing of NVM via the NVMREG interface is prevented when the device is write-protected.
15.3.1 NVMREG Read Operation
To read a NVM location using the NVMREG interface, the user must:
1. Clear the NVMREGS bit if the user intends to access program memory locations, or set NMVREGS if the user
intends to access User ID or configuration locations.
2. Write the desired address into the NVMADRH:NVMADRL register pair.
3. Set the RD bit to initiate the read.
Once the read control bit is set, the CPU operation is suspended during the read, and resumes immediately after.
The data is available in the very next cycle, in the NVMDATH:NVMDATL register pair; therefore, it can be read as two
bytes in the following instructions.
NVMDATH:NVMDATL register pair will hold this value until another read or until it is written to by the user.
Upon completion, the RD bit is cleared by hardware.
DS40002195A-page 108
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
Figure 15-1.ꢀProgram Flash Memory Read Sequence
Rev. 10-000046E
5/17/2017
Start
Read Operation
Select Memory:
Program Memory, DIA, DCI,
Config Words, User ID (NVMREGS)
Select
Word Address
(NVMADRH:NVMADRL)
Data read now in
NVMDATH:NVMDATL
End
Read Operation
Example 15-1.ꢀProgram Memory read
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI : PROG_ADDR_LO
data will be returned in the variables:
PROG_DATA_HI, PROG_DATA_LO
*
*
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
NVMADRL
PROG_ADDR_LO
NVMADRL
PROG_ADDR_HI
NVMADRH
; Select Bank for NVMCON registers
; Store LSB of address
; Store MSB of address
BCF
BSF
NVMCON1,NVMREGS
NVMCON1,RD
; Do not select Configuration Space
; Initiate read
MOVF
NVMDATL,W
; Get LSB of word
MOVWF
MOVF
PROG_DATA_LO
NVMDATH,W
; Store in user location
; Get MSB of word
MOVWF
PROG_DATA_HI
; Store in user location
15.3.2 NVM Unlock Sequence
The unlock sequence is a mechanism that protects the NVM from unintended self-write programming or erasing. The
sequence must be executed and completed without interruption to successfully complete any of the following
operations:
•
•
•
•
PFM Row Erase
Write of PFM write latches to PFM memory
Write of PFM write latches to User IDs
Write to Configuration Words
The unlock sequence consists of the following steps and must be completed in order:
DS40002195A-page 109
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
•
•
•
Write 55h to NVMCON2
Write AAh to NMVCON2
Set the WR bit
Once the WR bit is set, the processor will stall internal operations until the operation is complete and then resume
with the next instruction.
Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence
and re-enabled after the unlock sequence is completed.
Figure 15-2.ꢀNVM Unlock Sequence
Rev. 10-000047B
8/24/2015
Start
Unlock Sequence
Write 0x55 to
NVMCON2
Write 0xAA to
NVMCON2
Initiate
Write or Erase operation
(WR = 1)
End
Unlock Sequence
Example 15-2.ꢀNVM Unlock Sequence
BCF
BANKSEL
BSF
INTCON,GIE
NVMCON1
NVMCON1,WREN
55h
NVMCON2
AAh
NVMCON2
NVMCON1,WR
INTCON,GIE
; Recommended so sequence is not interrupted
; Bank to NVMCON1 register
; Enable write/erase
MOVLW
MOVWF
MOVLW
MOVWF
BSF
; Load 55h
; Step 1: Load 55h into NVMCON2
; Step 2: Load W with AAh
; Step 3: Load AAh into NVMCON2
; Step 4: Set WR bit to begin write/erase
; Re-enable interrupts
BSF
Note:ꢀ
1. Sequence begins when NVMCON2 is written; the following four steps must occur in the
cycle-accurate order shown. If the timing of the four steps is corrupted by an interrupt or a
debugger Halt, the action will not take place.
2. Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
15.3.3 NVMREG Erase of Program Memory
Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program
memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write to program
memory. To erase a program memory row:
DS40002195A-page 110
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
1. Clear the NVMREGS bit to erase program memory locations, or set the NMVREGS bit to erase User ID
locations.
2. Write the desired address into the NVMADRH:NVMADRL register pair.
3. Set the FREE and WREN bits.
4. Perform the unlock sequence as described in the “NVM Unlock Sequence” section.
If the program memory address is write-protected, the WR bit will be cleared and the erase operation will not take
place.
While erasing program memory, CPU operation is suspended, and resumes when the operation is complete. Upon
completion, the NVMIF bit is set, and an interrupt will occur if the NVMIE bit is also set.
Write latch data is not affected by erase operations, and WREN will remain unchanged.
DS40002195A-page 111
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
Figure 15-3.ꢀNVM Erase Sequence
Rev. 10-000048B
8/24/2015
Start
Erase Operation
Select Memory:
PFM, Config Words, User ID
(NVMREGS)
Select Word Address
(NVMADRH:NVMADRL)
Select Erase Operation
(FREE=1)
Enable Write/Erase Operation
(WREN=1)
Disable Interrupts
(GIE=0)
Unlock Sequence
(See Note 1)
CPU stalls while
Erase operation completes
(2 ms typical)
Disable Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
Note:ꢀ
1. See Figure 15-2.
DS40002195A-page 112
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
Example 15-3.ꢀErasing One Row of Program Flash Memory
; This sample row erase routine assumes the following:
; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL
; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
NVMADRL
ADDRL,W
NVMADRL
; Load lower 8 bits of erase address boundary
ADDRH,W
NVMADRH
; Load upper 6 bits of erase address boundary
; Choose PFM memory area
; Specify an erase operation
; Enable writes
; Disable interrupts during unlock sequence
NVMCON1,NVMREGS
NVMCON1,FREE
NVMCON1,WREN
INTCON,GIE
BSF
BSF
BCF
; ---------------------REQUIRED UNLOCK SEQUENCE:--------------------
MOVLW
MOVWF
MOVLW
MOVWF
BSF
0x55
NVMCON2
0xAA
NVMCON2
NVMCON1,WR
; Load 0x55 to get ready for unlock sequence
; First step is to load 0x55 into NVMCON2
; Second step is to load 0xAA into W
; Third step is to load 0xAA into NVMCON2
; Final step is to set WR bit
; ------------------------------------------------------------------
BSF
BCF
INTCON,GIE
NVMCON1,WREN
; Re-enable interrupts, erase is complete
; Disable writes
Table 15-1.ꢀNVM Organization and Access Information
Master Values
Program
NVMREG Access
FSR Access
Memory
Function
Counter
(PC), ICSP
Address
NVMREGS bit
(NVMCON1)
Allowed
Operations
FSR
Address
FSR Programming
Access
Memory Type
NVMADR[14:0]
™
0
0
0
0
Reset Vector
User Memory
INT Vector
0x0000
0x0001
0x0003
0x0004
0x0005
0x3FFF(1)
0x8000
0x8003
—
0x0000
0x0001
0x0003
0x0004
0x0005
0x3FFF(1)
0x0000
0x0003
0x0004
0x0005
0x8000
0x8001
0x8003
0x8004
0x8005
0xFFFF
Program Flash
Memory
Read/Write
Read-Only
User Memory
Program Flash
Memory
1
User ID
Read/Write
—
Reserved
—
—
1
Revision ID
Hard Coded in
Program Flash
Memory
0x8005
Read
1
Device ID
0x8006
0x0006
1
1
1
1
1
1
1
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
0x8007
0x8008
0x8009
0x800A
0x800B
0x8100
0x82FF
0x0007
0x0008
0x0009
0x000A
0x000B
0x0100
0x02FF
No Access
Program Flash
Memory
Read/Write
Hard Coded in
Program Flash
Memory
DIA and DCI
Reserved
Read
—
0xF000
0xF0FF
0x7000
0x7FFF
0x7000
0x7FFF
—
—
—
DS40002195A-page 113
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NVM - Nonvolatile Memory Control
Note:ꢀ
1. The maximum Program Flash Memory address for the PIC16F152 family is 0x3FFF. The maximum address
for the PIC16F15213/23/43 devices is 0x07FF, and the maximum address for the PIC16F15214/24/44 devices
is 0x0FFF.
15.3.4 NVMREG Write to Program Memory
Program memory is programmed using the following steps:
1. Load the address of the row to be programmed into NVMADRH:NVMADRL.
2. Load each write latch with data via the NMVDATH:NVMDATL registers.
3. Initiate a programming operation.
4. Repeat steps 1 through 3 until all data is written.
Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program
memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.
Program memory can be written one or more words at a time. The maximum number of words written at one time is
equal to the number of write latches. See Figure 15-4 for more details.
The write latches are aligned to the Flash row address boundary defined by the upper ten bits of
NVMADRH:NVMADRL, (NVMADRH[6:0]:NVMADRL[7:5]) with the lower five bits of NVMADRL, (NVMADRL[4:0])
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a
program memory write operation, the data in the write latches is reset to contain 0x3FFF.
The following steps should be completed to load the write latches and program a row of program memory. These
steps are divided into two parts. First, each write latch is loaded with data from the NVMDATH:NVMDATL using the
unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is
cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash
program memory.
Important:ꢀ The special unlock sequence is required to load a write latch with data or initiate a Flash
programming operation. If the unlock sequence is interrupted, writing to the latches or program memory
will not be initiated.
1. Set the WREN bit.
2. Clear the NVMREGS bit.
3. Set the LWLO bit. When the LWLO bit is set (LWLO = 1), the write sequence will only load the write latches
and will not initiate the write to Program Flash Memory.
4. Load the NVMADRH:NVMADRL register pair with the address of the location to be written.
5. Load the NVMDATH:NVMDATL register pair with the program memory data to be written.
6. Execute the unlock sequence. The write latch is now loaded.
7. Increment the NVMADRH:NVMADRL register pair to point to the next location.
8. Repeat steps 5 through 7 until all but the last write latch has been loaded.
9. Clear the LWLO bit. When the LWLO bit is clear (LWLO = 0), the write sequence will initiate the write to
Program Flash Memory.
10. Load the NVMDATH:NVMDATL register pair with the program memory data to be written.
11. Execute the unlock sequence. The entire program memory latch content is now written to Flash program
memory.
Important:ꢀ The program memory write latches are reset to the blank state (0x3FFF) at the completion of
every write or erase operation. As a result, it is not necessary to load all the program memory write
latches. Unloaded latches will remain in the blank state.
An example of the complete write sequence is shown in Example 15-4. The initial address is loaded into the
NVMADRH:NVMADRL register pair; the data is loaded using indirect addressing.
DS40002195A-page 114
Preliminary Datasheet
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NVM - Nonvolatile Memory Control
Figure 15-4.ꢀNVMREG Writes to Program Flash Memory with 32 Write Latches
7
6
0
7
5
4
0
7
5
0
7
0
-
-
NVMADRH
NVMADRL
NVMDATH
6
NVMDATL
8
-
r9
r8
r7
r6
r5
r4
r3
r2
r1
r0
c4
c3
c2
c1
c0
14
Program Memory Write Latches
10
5
14
14
14
14
Write Latch #0
00h
Write Latch #1
01h
Write Latch #30
1Eh
Write Latch #31
1Fh
NVMADRL[4:0]
14
14
14
14
Addr
Addr
001Fh
003Fh
005Fh
Row
Addr
0000h
0010h
0020h
Addr
0001h
0011h
0021h
000h
001h
002h
001Eh
003Eh
005Eh
NVMREGS=0
End
Addr
Row
Address
Decode
End Addr
NVMADRH[6:0]
NVMADRL[7:5]
Program Flash Memory
Configuration Memory
User ID, Device ID, Revision ID, Configuration Words, DIA, DCI
NVMREGS = 1
DS40002195A-page 115
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NVM - Nonvolatile Memory Control
Figure 15-5.ꢀProgram Flash Memory Write Sequence
Start Write Operation
Load the value to write
(NVMDATH:NVMDATL)
Determine number of
words to be written into
PFM or Configuration
Memory. The number of
words cannot exceed the
number of words per row
(word_cnt)
Update the word counter
(word_cnt--)
Write Latches to PFM
(LWLO = 0)
Select
PFM or Config. Memory
(NVMREGS)
Yes
Last word to write?
No
Disable interrupts
(GIE = 0)
Select Row Address
(NVMADRH:NVMADRL)
Disable interrupts
(GIE = 0)
Unlock Sequence(1)
Select Write Operation
(FREE = 0)
Unlock Sequence(1)
CPU stalls while Write
operation completes
(2ms typical)
Load Write Latches Only
(LWLO = 1)
No delay when writing to
PFM Latches
Enable Write/Erase
Operation (WREN = 1)
Re-enable interrupts
(GIE = 1)
Re-enable interrupts
(GIE = 1)
Disable Write/Erase
Operation (WREN = 0)
Increment Address
(NVMADRH:NVMADRL++)
End Write Operation
DS40002195A-page 116
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NVM - Nonvolatile Memory Control
Note:ꢀ
1. See Figure 15-2.
Example 15-4.ꢀWriting to Program Flash Memory
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (LSb’s = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
NVMADRH
ADDRH,W
NVMADRH
; Load initial address
ADDRL,W
NVMADRL
LOW DATA_ADDR
FSR0L
; Load initial data address
HIGH DATA_ADDR
FSR0H
NVMCON1,NVMREGS ; Set Program Flash Memory as write location
NVMCON1,WREN
NVMCON1,LWLO
BSF
BSF
; Enable writes
; Load only write latches
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
MOVF
FSR0++
NVMDATL
FSR0++
; Load first data byte
; Load second data byte
NVMDATH
NVMADRL,W
0x1F
XORLW
ANDLW
BTFSC
GOTO
; Check if lower bits of address are 00000
; and if on last of 32 addresses
; Last of 32 words?
; If so, go write latches into memory
; If not, go load latch
; Increment address
0x1F
STATUS,Z
START_WRITE
UNLOCK_SEQ
NVMADRL,F
LOOP
CALL
INCF
GOTO
START_WRITE
BCF
NVMCON1,LWLO
UNLOCK_SEQ
NVMCON1,WREN
; Latch writes complete, now write memory
; Perform required unlock sequence
; Disable writes
CALL
BCF
UNLOCK_SEQ
MOVLW
BCF
55h
INTCON,GIE
NVMCON2
AAh
; Disable interrupts
MOVWF
MOVLW
MOVWF
BSF
BSF
return
; Begin unlock sequence
NVMCON2
NVMCON1,WR
INTCON,GIE
; Unlock sequence complete, re-enable interrupts
15.3.5 Modifying Flash Program Memory
When modifying existing data in a program memory, data within the memory row must be read and saved in a RAM
image. Program memory is modified using the following steps:
1. Load the starting address of the row to be modified.
2. Read the existing data from the row into a RAM image.
3. Modify the RAM image to contain the new data to be written into program memory.
4. Load the starting address of the row to be rewritten.
5. Erase the program memory row.
6. Load the write latches with data from the RAM image.
7. Initiate a programming operation.
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NVM - Nonvolatile Memory Control
Figure 15-6.ꢀProgram Flash Memory Modify Sequence
Rev. 10-000050B
8/21/2015
Start
Modify Operation
Read Operation
(See Note 1)
An image of the entire row
read must be stored in RAM
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation
Note:ꢀ
1. See Figure 15-1.
2. See Figure 15-3.
3. See Figure 15-5.
15.3.6 NVMREG Access to DIA, DCI, User ID, Device ID, Revision ID and Configuration Words
NVMREGS can be used to access the following memory regions:
•
•
•
•
•
Device Information Area (DIA)
Device Configuration Information (DCI)
User ID region
Device ID and Revision ID
Configuration Words
The value of NVMREGS is set to ‘1’ to access these regions. The memory regions listed above would be pointed to
by PC[15] = 1, but not all addresses reference valid data. Different access may exist for reads and writes. Refer to
the table below. When read access is initiated on an address outside the parameters listed in the following table, the
NVMDATH: NVMDATL register pair is cleared, reading back ‘0’s.
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Table 15-2.ꢀNVMREG Access to DIA, DCI, User ID, Device ID, Revision ID and Configuration Words
(NVMREGS = 1)
Address
Function
User IDs
Read Access
Write Access
0x8000 - 0x8003
0x8005 - 0x8006
0x8007 - 0x800B
0x8100 - 0x82FF
Yes
Yes
Yes
Yes
Yes
No
Device ID/Revision ID
Configuration Words 1-5
DIA and DCI
Yes
No
Example 15-5.ꢀDevice ID Access
; This write routine assumes the following:
; 1. A full row of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in
DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the LSb’s = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)
; 5. NVM interrupts are not taken into account
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
NVMADRH
ADDRH,W
NVMADRH
; Load initial address
ADDRL,W
NVMADRL
LOW DATA_ADDR
FSR0L
; Load initial data address
HIGH DATA_ADDR
FSR0H
NVMCON1,NVMREGS
NVMCON1,WREN
NVMCON1,LWLO
; Set PFM as write location
; Enable writes
; Load only write latches
BSF
BSF
LOOP
MOVIW
MOVWF
MOVIW
MOVWF
CALL
INCF
MOVF
FSR0++
NVMDATL
FSR0++
; Load first data byte
NVMDATH
UNLOCK_SEQ
NVMADRL,F
NVMADRL,W
0x1F
; Load second data byte
; If not, go load latch
; Increment address
XORLW
ANDLW
BTFSC
GOTO
; Check if lower bits of address are 00000
; and if on last of 32 addresses
; Last of 32 words?
0x1F
STATUS,Z
START_WRITE
LOOP
; If so, go write latches into memory
GOTO
START_WRITE
BCF
NVMCON1,LWLO
UNLOCK_SEQ
NVMCON1,LWLO
; Latch writes complete, now write memory
; Perform required unlock sequence
; Disable writes
CALL
BCF
UNLOCK_SEQ
MOVLW
BCF
0x55
INTCON,GIE
NVMCON2
0xAA
; Disable interrupts
MOVWF
MOVLW
MOVWF
BSF
; Begin unlock sequence
NVMCON2
NVMCON1,WR
INTCON,GIE
BSF
; Unlock sequence complete, re-enable
interrupts
RETURN
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NVM - Nonvolatile Memory Control
15.3.7 Write Verify
It is considered good programming practice to verify that program memory writes agree with the intended value.
Since program memory is stored as a full row then the stored program memory contents are compared with the
intended data stored in RAM after the last write is complete.
Figure 15-7.ꢀProgram Flash Memory Write Verify Sequence
Rev. 10-000051B
12/4/2015
Start
Verify Operation
This routine assumes that the last
row of data written was from an
image saved on RAM. This image
will be used to verify the data
currently stored in PFM
Read Operation(1)
NVMDAT =
No
RAM image ?
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
Note:ꢀ
1. See Figure 15-1.
15.3.8 WRERR Bit
The WRERR bit can be used to determine if a write error occurred. WRERR will be set if one of the following
conditions occurs:
•
•
•
If WR is set while the NVMADRH:NMVADRL points to a write-protected address
A Reset occurs while a self-write operation was in progress
An unlock sequence was interrupted
The WRERR bit is normally set by hardware, but can be set by the user for test purposes. Once set, WRERR must
be cleared in software.
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Table 15-3.ꢀActions for PFM When WR = 1
Actions for PFM when WR = 1
Free LWLO
Comments
•
•
•
If WP is enabled, WR is cleared and WRERR is set
All 32 words are erased
Erase the 32-word row of
NVMADRH:NVMADRL location.
1
0
0
x
1
0
NVMDATH:NVMDATL is ignored
•
•
Write protection is ignored
No memory access occurs
Copy NVMDATH:NVMDATL to the write
latch corresponding to NVMADR LSBs.
•
•
•
If WP is enabled, WR is cleared and WRERR is set
Write latches are reset to 0x3FFF
Write the write-latch data to PFM row.
NVMDATH:NVMDATL is ignored
15.4
Register Definitions: Nonvolatile Memory Control
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15.4.1 NVMADR
Name:ꢀ
NVMADR
Address:ꢀ 0x81A
Nonvolatile Memory Address Register
Bit
15
7
14
13
12
11
10
9
8
NVMADR[14:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
6
5
4
3
2
1
0
NVMADR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 14:0 – NVMADR[14:0]ꢀNVM Address Bits
Note:ꢀ
1. The individual bytes in this multi-byte register can be accessed with the following register names:
– NVMADRH: Accesses the high byte NVMADR[15:8]
– NVMADRL: Accesses the low byte NVMADR[7:0]
2. Bit [15] is undefined while WR = 1.
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NVM - Nonvolatile Memory Control
15.4.2 NVMDAT
Name:ꢀ
NVMDAT
Address:ꢀ 0x81C
Nonvolatile Memory Data Register
Bit
15
7
14
6
13
12
11
10
9
8
NVMDAT[13:8]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
5
4
3
2
1
0
NVMDAT[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bits 13:0 – NVMDAT[13:0]ꢀNVM Data bits
Reset States: POR/BOR = xxxxxxxxxxxxxx
All Other Resets = uuuuuuuuuuuuuu
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
NVMDATH: Accesses the high byte NVMDAT[13:8]
NVMDATL: Accesses the low byte NVMDAT[7:0]
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NVM - Nonvolatile Memory Control
15.4.3 NVMCON1
Name:ꢀ
NVMCON1
Address:ꢀ 0x81E
Nonvolatile Memory Control 1 Register
Bit
7
6
NVMREGS
R/W
5
LWLO
R/W
0
4
FREE
R/S/HC
0
3
2
WREN
R/W
0
1
WR
0
RD
WRERR
R/W/HS
0
Access
Reset
R/S/HC
0
R/S/HC
0
0
Bit 6 – NVMREGSꢀNVM Region Selection bit
Value
Description
1
0
Access DIA, DCI, Configuration, User ID, Revision ID, and Device ID Registers
Access Program Flash Memory
Bit 5 – LWLOꢀLoad Write Latches Only bit
Value
Condition
Description
1
When FREE = 0 The next WR command updates the write latch for this word within the row; no
memory operation is initiated.
0
-
When FREE = 0 The next WR command writes data or erases
Otherwise:
This bit is ignored.
Bit 4 – FREEꢀProgram Flash Memory Erase Enable bit
Value
Description
1
Performs an erase operation with the next WR command; the 32-word pseudo-row containing the
indicated address is erased (to all 1s) to prepare for writing.
The next WR command writes without erasing.
0
Bit 3 – WRERR
Write-Reset Error Flag bit(1,2,3)
Value
Description
1
A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one
while NVMADR points to a write-protected address.
All write operations have completed normally.
0
Bit 2 – WRENꢀProgram/Erase Enable bit
Value
Description
1
0
Allows program/erase cycles
Inhibits programming/erasing of program Flash
Bit 1 – WRꢀ Write Control bit(4,5,6)
Value
Description
1
0
Initiates the operation indicated by table in “WRERR Bit” section.
NVM program/erase operation is complete and inactive.
Bit 0 – RDꢀ Read Control bit
Value
Description
1
Initiates a read at address = NVMADR, and loads data to NVMDAT Read takes one instruction cycle
and the bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.
NVM read operation is complete and inactive
0
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NVM - Nonvolatile Memory Control
Note:ꢀ
1. Bit is undefined while WR = 1.
2. Bit must be cleared by software; hardware will not clear this bit.
3. Bit may be written to ‘1’ by the user in order to implement test sequences.
4. This bit can only be set by following the sequence described in the “NVM Unlock Sequence” section.
5. Operations are self-timed and the WR bit is cleared by hardware when complete.
6. Once a write operation is initiated, setting this bit to zero will have no effect.
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15.4.4 NVMCON2
Name:ꢀ
NVMCON2
Address:ꢀ 0x81F
Nonvolatile Memory Control 2 Register
Bit
7
6
5
4
3
2
1
0
NVMCON2[7:0]
Access
Reset
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
WO
0
Bits 7:0 – NVMCON2[7:0]ꢀFlash Memory Unlock Pattern bits
Note:ꢀ To unlock writes, a 0x55 must be written first followed by an 0xAA before setting the WR bit of the NVMCON1
register. The value written to this register is used to unlock the writes.
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15.5
Register Summary: NVM Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x0819
7:0
15:8
7:0
NVMADR[7:0]
NVMADR[14:8]
NVMDAT[7:0]
NVMDAT[13:8]
0x081A
0x081C
NVMADR
NVMDAT
15:8
7:0
0x081E
0x081F
NVMCON1
NVMCON2
NVMREGS
LWLO
FREE
WRERR
WREN
WR
RD
7:0
NVMCON2[7:0]
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I/O Ports
16.
I/O Ports
16.1
Overview
Table 16-1.ꢀPort Availability per Device
Device
8-pin devices
PORTA
PORTB
PORTC
●
●
●
14/16-pin devices
20-pin devices
●
●
●
Each port has eight registers to control the operation. These registers are:
•
•
•
•
•
•
•
•
PORTx registers (reads the levels on the pins of the device)
LATx registers (output latch)
TRISx registers (data direction)
ANSELx registers (analog select)
WPUx registers (weak pull-up)
INLVLx (input level control)
SLRCONx registers (slew rate control)
ODCONx registers (open-drain control)
In this chapter the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB,
PORTC, etc., depending on availability per device.
A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in the following figure:
Figure 16-1.ꢀGeneric I/O Port Operation
Re v. 10 -00 00 52A
2/11 /20 19
Read LATx
TRISx
D
Q
Write LATx
Write PORTx
VDD
CK
Data Register
Data bus
I/O pin
Read PORTx
To digital peripherals
ANSELx
To analog peripherals
VSS
16.2
PORTx - Data Register
PORTx is a bidirectional port, and its corresponding data direction register is TRISx.
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I/O Ports
Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the PORT pins are read, and this
value is modified, then written to the PORT data latch (LATx). The PORT data latch LATx holds the output port data
and contains the latest value of a LATx or PORTx write. The example below shows how to initialize PORTA.
Example 16-1.ꢀInitializing PORTA in assembly
; This code example illustrates initializing the PORTA register.
; The other ports are initialized in the same manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
;
;Clear PORTA
;
LATA
;Clear Data Latch
ANSELA
ANSELA
TRISA
;
;Enable digital drivers
;
B'00111000' ;Set RA[5:3] as inputs
TRISA ;and set others as outputs
Example 16-2.ꢀInitializing PORTA in C
// This code example illustrates initializing the PORTA register.
// The other ports are initialized in the same manner.
PORTA = 0x00;
LATA = 0x00;
ANSELA = 0x00;
TRISA = 0x38;
// Clear PORTA
// Clear Data Latch
// Enable digital drivers
// Set RA[5:3] as inputs and set others as outputs
Important:ꢀ Most PORT pins share functions with device peripherals, both analog and digital. In general,
when a peripheral is enabled on a PORT pin, that pin cannot be used as a general purpose output;
however, the pin can still be read.
16.3
LATx - Output Latch
The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving.
A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of
the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the
actual I/O pin value.
Important:ꢀ As a general rule, output operations to a port should use the LAT register to avoid read-
modify-write issues. For example, a bit set or clear operation reads the port, modifies the bit, and writes
the result back to the port. When two bit operations are executed in succession, output loading on the
changed bit may delay the change at the output in which case the bit will be misread in the second bit
operation and written to an unexpected level. The LAT registers are isolated from the port loading and
therefore changes are not delayed.
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I/O Ports
16.4
16.5
TRISx - Direction Control
The TRISx register controls the PORTx pin output drivers, even when the pins are being used as analog inputs. The
user should ensure the bits in the TRISx register are set when using the pins as analog inputs. I/O pins configured as
analog inputs always read ‘0’.
Setting a TRISx bit (TRISx = 1) will make the corresponding PORTx pin an input (i.e., disable the output driver).
Clearing a TRISx bit (TRISx = 0) will make the corresponding PORTx pin an output (i.e., it enables output driver and
puts the contents of the output latch on the selected pin).
ANSELx - Analog Control
Ports that support analog inputs have an associated ANSELx register. The ANSELx register is used to configure the
input mode of an I/O pin to analog. Setting an ANSELx bit high will disable the digital input buffer associated with that
bit and cause the corresponding input value to always read ‘0’, whether the value is read in PORTx register or
selected by PPS as a peripheral input.
Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing
excessive current in the logic input circuitry.
The state of the ANSELx bits has no effect on digital or analog output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the input mode will be analog. This can cause unexpected behavior when
executing read-modify-write instructions on the PORTx register.
Important:ꢀ The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general
purpose or peripheral inputs, the corresponding ANSEL bits must be changed to ‘0’ by user.
16.6
16.7
WPUx - Weak Pull-Up Control
The WPUx register controls the individual weak pull-ups for each PORT pin. When a WPUx bit is set (WPUx = 1), the
weak pull-up will be enabled for the corresponding pin. When a WPUx bit is cleared (WPUx = 0), the weak pull-up will
be disabled for the corresponding pin.
INLVLx - Input Threshold Control
The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A selection
between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. If that feature is enabled, the input
threshold is important in determining the value of a read of the PORTx register and also all other peripherals which
are connected to the input. Refer to the I/O Ports table in the “Electrical Specifications” chapter for more details on
threshold levels.
Important:ꢀ Changing the input threshold selection should be performed while all peripheral modules are
disabled. Changing the threshold level during the time a module is active may inadvertently generate a
transition associated with an input pin, regardless of the actual voltage level on that pin.
16.8
SLRCONx - Slew Rate Control
The SLRCONx register controls the slew rate option for each PORT pin. Slew rate for each PORT pin can be
controlled independently. When a SLRCONx bit is set (SLRCONx = 1), the corresponding PORT pin drive is slew
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I/O Ports
rate limited. When a SLRCONx bit is cleared (SLRCONx = 0), The corresponding PORT pin drive slews at the
maximum rate possible.
16.9
ODCONx - Open-Drain Control
The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently selected for
each pin. When a ODCONx bit is set (ODCONx = 1), the corresponding port output becomes an open-drain driver
capable of sinking current only. When a ODCONx bit is cleared (ODCONx = 0), the corresponding port output pin is
the standard push-pull drive capable of sourcing and sinking current.
Important:ꢀ It is necessary to set open-drain control when using the pin for I2C.
16.10 Edge Selectable Interrupt-on-Change
An interrupt can be generated by detecting a signal at the PORT pin that has either a rising edge or a falling edge.
Individual pins can be independently configured to generate an interrupt. Refer to the “IOC - Interrupt-on-Change”
chapter for more details.
16.11 I2C Pad Control
For this family of devices, the I2C specific pads are available on RB4, RB6, RC0 and RC1 pins. The I2C
characteristics of each of these pins is controlled by the RxyI2C registers. These characteristics include enabling I2C
specific slew rate (over standard GPIO slew rate), selecting internal pull-ups for I2C pins, and selecting appropriate
input threshold as per SMBus specifications.
Important:ꢀ Any peripheral using the I2C pins reads the I2C input levels when enabled via RxyI2C.
16.12 I/O Priorities
Each pin defaults to the data latch after Reset. Other functions are selected with the peripheral pin select logic. Refer
to the “PPS - Peripheral Pin Select Module” chapter for more details.
Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These
inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may
continue to control the pin when it is in Analog mode.
Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a high-
impedance state.
The pin function priorities are as follows:
1. Port functions determined by the Configuration bits
2. Analog outputs (input buffers should be disabled)
3. Analog inputs
4. Port inputs and outputs from PPS
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16.13 MCLR/VPP/RA3 Pin
The MCLR/VPP pin is an input-only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as
a PORT pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRISx and LATx bits
associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, the
MCLR/VPP pin also functions as the programming voltage input pin during high voltage programming.
The MCLR/VPP pin is a read-only bit and will read ‘1’ when MCLRE = 1(i.e., Master Clear enabled).
Important:ꢀ On a Power-on Reset, the MCLR/VPP pin is enabled as a digital input-only if Master Clear
functionality is disabled.
The MCLR/VPP pin has an individually controlled internal weak pull-up. When set, the corresponding WPU bit
enables the pull-up. When the MCLR/VPP pin is configured as MCLR, (MCLRE = 1and, LVP = 0), or configured for
Low-Voltage Programming, (MCLRE = x and LVP = 1), the pull-up is always enabled and the WPU bit has no effect.
16.14 Register Definitions: Port Control
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I/O Ports
16.14.1 PORTx
Name:ꢀ
PORTx
PORTx Register
Bit
7
6
Rx6
R/W
x
5
Rx5
R/W
x
4
Rx4
R/W
x
3
Rx3
R/W
x
2
Rx2
R/W
x
1
Rx1
R/W
x
0
Rx0
R/W
x
Rx7
R/W
x
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – RxnꢀPort I/O Value
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
1
0
PORT pin is ≥ VIH
PORT pin is ≤ VIL
Important:ꢀ
•
Writes to PORTx are actually written to the corresponding LATx register.
Reads from PORTx register return actual I/O pin values.
•
The PORT bit associated with the MCLR pin is Read-Only and will read ‘1’ when MCLR function is
enabled (LVP = 1or (LVP = 0and MCLRE = 1)).
•
Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port.
DS40002195A-page 133
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I/O Ports
16.14.2 LATx
Name:ꢀ
LATx
Output Latch Register
Bit
7
LATx7
R/W
x
6
5
LATx5
R/W
x
4
LATx4
R/W
x
3
LATx3
R/W
x
2
LATx2
R/W
x
1
LATx1
R/W
x
0
LATx0
R/W
x
LATx6
R/W
x
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATxnꢀOutput Latch Value
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Important:ꢀ
•
Writes to LATx are equivalent with writes to the corresponding PORTx register. Reads from LATx
register return register values, not I/O pin values.
•
Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 134
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I/O Ports
16.14.3 TRISx
Name:ꢀ
TRISx
Tri-State Control Register
Bit
7
TRISx7
R/W
1
6
TRISx6
R/W
1
5
TRISx5
R/W
1
4
TRISx4
R/W
1
3
TRISx3
R/W
1
2
TRISx2
R/W
1
1
TRISx1
R/W
1
0
TRISx0
R/W
1
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISxnꢀPort I/O Tri-state Control
Value
Description
1
0
PORTx output driver is disabled. PORTx pin configured as an input (tri-stated)
PORTx output driver is enabled. PORTx pin configured as an output
Important:ꢀ
•
•
The TRIS bit associated with the MCLR pin is Read-Only and the value is 1.
Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port.
DS40002195A-page 135
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I/O Ports
16.14.4 ANSELx
Name:ꢀ
ANSELx
Analog Select Register
Bit
7
ANSELx7
R/W
6
ANSELx6
R/W
5
ANSELx5
R/W
4
ANSELx4
R/W
3
ANSELx3
R/W
2
ANSELx2
R/W
1
ANSELx1
R/W
0
ANSELx0
R/W
Access
Reset
1
1
1
1
1
1
1
1
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELxnꢀAnalog Select on Rx Pin
Value
Description
1
0
Analog input. Pin is assigned as analog input. Digital input buffer disabled.
Digital I/O. Pin is assigned to port or digital special function.
Important:ꢀ
•
When setting a pin as an analog input, the corresponding TRIS bit must be set to Input mode in order
to allow external control of the voltage on the pin.
•
Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 136
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I/O Ports
16.14.5 WPUx
Name:ꢀ
WPUx
Weak pull-up Register
Bit
7
WPUx7
R/W
0
6
5
WPUx5
R/W
0
4
WPUx4
R/W
0
3
WPUx3
R/W
0
2
WPUx2
R/W
0
1
WPUx1
R/W
0
0
WPUx0
R/W
0
WPUx6
R/W
0
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUxnꢀWeak Pull-up PORTx Control
Value
Description
1
0
Weak pull-up enabled
Weak pull-up disabled
Important:ꢀ
•
•
•
The weak pull-up device is automatically disabled if the pin is configured as an output but this register
remains unchanged.
If MCLRE = 1, the weak pull-up on MCLR pin is always enabled and the corresponding WPU bit is
not affected.
Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 137
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I/O Ports
16.14.6 INLVLx
Name:ꢀ
INLVLx
Input Level Control Register
Bit
7
INLVLx7
R/W
1
6
INLVLx6
R/W
1
5
INLVLx5
R/W
1
4
INLVLx4
R/W
1
3
INLVLx3
R/W
1
2
INLVLx2
R/W
1
1
INLVLx1
R/W
1
0
INLVLx0
R/W
1
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLxnꢀInput Level Select on Rx Pin
Value
Description
1
0
ST input used for port reads and interrupt-on-change
TTL input used for port reads and interrupt-on-change
Important:ꢀ Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 138
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I/O Ports
16.14.7 SLRCONx
Name:ꢀ
SLRCONx
Slew Rate Control Register
Bit
7
SLRx7
R/W
1
6
SLRx6
R/W
1
5
SLRx5
R/W
1
4
SLRx4
R/W
1
3
SLRx3
R/W
1
2
SLRx2
R/W
1
1
SLRx1
R/W
1
0
SLRx0
R/W
1
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRxnꢀSlew Rate Control on Rx Pin
Value
Description
1
0
PORT pin slew rate is limited
PORT pin slews at maximum rate
Important:ꢀ Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 139
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I/O Ports
16.14.8 ODCONx
Name:ꢀ
ODCONx
Open-Drain Control Register
Bit
7
ODCx7
R/W
0
6
ODCx6
R/W
0
5
ODCx5
R/W
0
4
ODCx4
R/W
0
3
ODCx3
R/W
0
2
ODCx2
R/W
0
1
ODCx1
R/W
0
0
ODCx0
R/W
0
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCxnꢀOpen-Drain Configuration on Rx Pin
Value
Description
1
PORT pin operates as open-drain drive (sink current only)
0
PORT pin operates as standard push-pull drive (source and sink current)
Important:ꢀ Refer to the “Pin Allocation Table” for details about pin availability per port.
DS40002195A-page 140
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I/O Ports
16.14.9 RxyI2C
Name:ꢀ
RxyI2C
I2C Pad Rxy Control Register
Bit
7
6
5
4
3
2
1
0
SLEW[1:0]
PU[1:0]
TH[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:6 – SLEW[1:0]ꢀ I2C Specific Slew Rate Limiting Control
Value
11
10
01
00
Description
I2C fast-mode-plus (1 MHz) slew rate enabled. The SLRxy bit is ignored.
Reserved
I2C fast-mode (400 kHz) slew rate enabled. The SLRxy bit is ignored.
Standard GPIO Slew Rate; enabled/disabled via SLRxy bit
Bits 5:4 – PU[1:0]ꢀ I2C Pull-up Selection
Value
11
Description
Reserved
10
01
00
10x current of standard weak pull-up
2x current of standard weak pull-up
Standard GPIO weak pull-up, enabled via WPUxy bit
Bits 1:0 – TH[1:0]ꢀ I2C Input Threshold Selection
Value
11
10
Description
SMBus 3.0 (1.35V) input threshold
SMBus 2.0 (2.1 V) input threshold
I2C-specific input thresholds
01
00
Standard GPIO Input pull-up, enabled via INLVLxy registers
Important:ꢀ Refer to the “Pin Allocation Table” for details about I2C compatible pins.
DS40002195A-page 141
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I/O Ports
16.15 Register Summary - IO Ports
Address
Name
Bit Pos.
0x00
...
Reserved
0x0B
0x0C
PORTA
PORTB
PORTC
7:0
7:0
7:0
RA5
RB5
RC5
RA4
RB4
RC4
RA3
RC3
RA2
RC2
RA1
RC1
RA0
RC0
0x0D
RB7
RC7
RB6
RC6
0x0E
0x0F
...
Reserved
0x11
0x12
TRISA
TRISB
TRISC
7:0
7:0
7:0
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
Reserved
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
0x13
TRISB7
TRISC7
TRISB6
TRISC6
0x14
0x15
...
Reserved
0x17
0x18
LATA
LATB
LATC
7:0
7:0
7:0
LATA5
LATB5
LATC5
LATA4
LATB4
LATC4
LATA2
LATC2
LATA1
LATC1
LATA0
LATC0
0x19
LATB7
LATC7
LATB6
LATC6
0x1A
LATC3
0x1B
...
Reserved
0x010B
0x010C
0x010D
0x010E
0x010F
0x0110
...
RB4I2C
RB6I2C
RC0I2C
RC1I2C
7:0
7:0
7:0
7:0
SLEW[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
SLEW[1:0]
SLEW[1:0]
SLEW[1:0]
Reserved
0x1F37
0x1F38
0x1F39
0x1F3A
0x1F3B
0x1F3C
0x1F3D
...
ANSELA
WPUA
7:0
7:0
7:0
7:0
7:0
ANSELA5
WPUA5
ODCA5
SLRA5
ANSELA4
WPUA4
ODCA4
SLRA4
ANSELA2
WPUA2
ODCA2
SLRA2
ANSELA1
WPUA1
ODCA1
SLRA1
ANSELA0
WPUA0
ODCA0
SLRA0
WPUA3
ODCONA
SLRCONA
INLVLA
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
Reserved
0x1F42
0x1F43
0x1F44
0x1F45
0x1F46
0x1F47
0x1F48
...
ANSELB
WPUB
7:0
7:0
7:0
7:0
7:0
ANSELB7
ANSELB6
WPUB6
ODCB6
SLRB6
ANSELB5
WPUB5
ODCB5
SLRB5
ANSELB4
WPUB4
ODCB4
SLRB4
WPUB7
ODCB7
SLRB7
ODCONB
SLRCONB
INLVLB
INLVLB7
INLVLB6
INLVLB5
INLVLB4
Reserved
0x1F4D
0x1F4E
0x1F4F
0x1F50
0x1F51
0x1F52
ANSELC
WPUC
7:0
7:0
7:0
7:0
7:0
ANSELC7
WPUC7
ODCC7
SLRC7
ANSELC6
WPUC6
ODCC6
SLRC6
ANSELC5
WPUC5
ODCC5
SLRC5
ANSELC4
WPUC4
ODCC4
SLRC4
ANSELC3
WPUC3
ODCC3
SLRC3
ANSELC2
WPUC2
ODCC2
SLRC2
ANSELC1
WPUC1
ODCC1
SLRC1
ANSELC0
WPUC0
ODCC0
SLRC0
ODCONC
SLRCONC
INLVLC
INLVLC7
INLVLC6
INLVLC5
INLVLC4
INLVLC3
INLVLC2
INLVLC1
INLVLC0
DS40002195A-page 142
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IOC - Interrupt-on-Change
17.
IOC - Interrupt-on-Change
17.1
Overview
The pins denoted in the table below can be configured to operate as Interrupt-on-Change (IOC) pins for this device.
An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual
PORT pin, or combination of PORT pins, can be configured to generate an interrupt.
Table 17-1.ꢀIOC Pin Availability per Device
Device
28-pin devices
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
(1)
●
●
●
●
●
●
●
●
●
●
(1)
40/44-pin devices
48-pin devices
●
(1)
●
Note:ꢀ
1. Pin RE3 only
Important:ꢀ If MCLRE = 1or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is
not available
The Interrupt-on-Change module has the following features:
•
•
•
•
Interrupt-on-Change enable (Master Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
The following figure is a block diagram of the IOC module.
Figure 17-1.ꢀInterrupt-on-Change Block Diagram (PORTA Example)
Positive
Edge
Detect
IOC
Flag
IOCAPx
Write to IOCAFx flag
IOCIE
RAx
Set/Reset
Logic
IOC interrupt
to CPU core
Negative
Edge
Detect
IOCANx
From all other
IOCnFx flags
17.2
Enabling the Module
In order for individual PORT pins to generate an interrupt, the IOC Interrupt Enable bit (IOCIE) of the Peripheral
Interrupt Enable register (PIEx) must be set. If the IOC Interrupt Enable bit is disabled, the edge detection on the pin
will still occur, but an interrupt will not be generated.
DS40002195A-page 143
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IOC - Interrupt-on-Change
17.3
17.4
Individual Pin Configuration
A rising edge detector and a falling edge detector are present for each PORT pin. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register must be set. To enable a pin to detect a falling edge, the associated bit
of the IOCxN register must be set. A PORT pin can be configured to detect rising and falling edges simultaneously by
setting both associated bits of the IOCxP and IOCxN registers, respectively.
Interrupt Flags
The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If
an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an
interrupt will be generated if the IOCIE bit is set. The IOCIF bit located in the corresponding Peripheral Interrupt
Request register (PIRx), is all the IOCxF bits ORd together. The IOCIF bit is read-only. All of the IOCxF Status bits
must be cleared to clear the IOCIF bit.
17.5
Clearing Interrupt Flags
The individual status flags, (IOCxF register bits), will be cleared by resetting them to zero. If another edge is detected
during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the
value actually being written.
In order to ensure that no detected edge is lost while clearing flags, only ANDoperations masking out known changed
bits should be performed. The following sequence is an example of clearing an IOC interrupt flag using this method.
Example 17-1.ꢀClearing Interrupt Flags
(PORTA Example)
MOVLW
XORWF
ANDWF
0xff
IOCAF, W
IOCAF, F
17.6
17.7
Operation in Sleep
An interrupt-on-change interrupt event will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is
detected while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep.
Register Definitions: Interrupt-on-Change Control
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IOC - Interrupt-on-Change
17.7.1 IOCxF
Name:ꢀ
IOCxF
Interrupt-on-Change Flag Register
Bit
7
6
5
4
3
2
1
0
IOCxF7
R/W/HS
0
IOCxF6
R/W/HS
0
IOCxF5
R/W/HS
0
IOCxF4
R/W/HS
0
IOCxF3
R/W/HS
0
IOCxF2
R/W/HS
0
IOCxF1
R/W/HS
0
IOCxF0
R/W/HS
0
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxFnꢀInterrupt-on-Change Flag
Value
Condition
Description
1
IOCxP[n] = 1
A positive edge was detected on the Rx[n] pin
1
0
IOCxN[n] = 1
A negative edge was detected on the Rx[n] pin
IOCxP[n] = xand IOCxN[n] = x No change was detected, or the user cleared the detected change
Important:ꢀ
•
If MCLRE = 1or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
•
Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
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IOC - Interrupt-on-Change
17.7.2 IOCxN
Name:ꢀ
IOCxN
Interrupt-on-Change Negative Edge Register Example
Bit
7
IOCxN7
R/W
0
6
IOCxN6
R/W
0
5
IOCxN5
R/W
0
4
IOCxN4
R/W
0
3
IOCxN3
R/W
0
2
IOCxN2
R/W
0
1
IOCxN1
R/W
0
0
IOCxN0
R/W
0
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxNnꢀInterrupt-on-Change Negative Edge Enable
Value
Description
1
Interrupt-on-Change enabled on the IOCx pin for a negative-going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0
Falling edge Interrupt-on-Change disabled for the associated pin
Important:ꢀ
•
If MCLRE = 1or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
•
Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
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IOC - Interrupt-on-Change
17.7.3 IOCxP
Name:ꢀ
IOCxP
Interrupt-on-Change Positive Edge Register
Bit
7
IOCxP7
R/W
0
6
IOCxP6
R/W
0
5
IOCxP5
R/W
0
4
IOCxP4
R/W
0
3
IOCxP3
R/W
0
2
IOCxP2
R/W
0
1
IOCxP1
R/W
0
0
IOCxP0
R/W
0
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxPnꢀInterrupt-on-Change Positive Edge Enable
Value
Description
1
Interrupt-on-Change enabled on the IOCx pin for a positive-going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0
Rising edge Interrupt-on-Change disabled for the associated pin.
Important:ꢀ
•
If MCLRE = 1or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
•
Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
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IOC - Interrupt-on-Change
17.8
Register Summary: Interrupt-on-Change
Address
Name
Bit Pos.
0x00
...
Reserved
0x1F3C
0x1F3D
0x1F3E
0x1F3F
0x1F40
...
IOCAP
IOCAN
IOCAF
7:0
7:0
7:0
IOCAP5
IOCAN5
IOCAF5
IOCAP4
IOCAN4
IOCAF4
IOCAP3
IOCAN3
IOCAF3
IOCAP2
IOCAN2
IOCAF2
IOCAP1
IOCAN1
IOCAF1
IOCAP0
IOCAN0
IOCAF0
Reserved
0x1F47
0x1F48
0x1F49
0x1F4A
0x1F4B
...
IOCBP
IOCBN
IOCBF
7:0
7:0
7:0
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBN6
IOCBF6
IOCBP5
IOCBN5
IOCBF5
IOCBP4
IOCBN4
IOCBF4
Reserved
0x1F52
0x1F53
0x1F54
0x1F55
IOCCP
IOCCN
IOCCF
7:0
7:0
7:0
IOCCP7
IOCCN7
IOCCF7
IOCCP6
IOCCN6
IOCCF6
IOCCP5
IOCCN5
IOCCF5
IOCCP4
IOCCN4
IOCCF4
IOCCP3
IOCCN3
IOCCF3
IOCCP2
IOCCN2
IOCCF2
IOCCP1
IOCCN1
IOCCF1
IOCCP0
IOCCN0
IOCCF0
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PPS - Peripheral Pin Select Module
18.
PPS - Peripheral Pin Select Module
18.1
Overview
The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital
signals are included in the selections.
Important:ꢀ All analog inputs and outputs remain fixed to their assigned pins and cannot be changed
through PPS.
Input and output selections are independent as shown in the figure below.
Figure 18-1.ꢀPPS Block Diagram
abcPPS
RA0PPS
RA0
Peripheral abc
RA0
Rxy
Peripheral xyz
Rxy
RxyPPS
xyzPPS
Input selections
Output selections
18.2
PPS Inputs
Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to
the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while
devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the PPS Input Selection
Table below).
Important:ꢀ The notation “xxx” in the generic register name is a place holder for the peripheral identifier.
For example, xxx = T0CKI for the T0CKIPPS register.
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PPS - Peripheral Pin Select Module
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level
regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must
be cleared to enable the digital input buffer.
Table 18-1.ꢀPPS Input Selection Table
Default Pin Location
Input Signal
INT
PPS Input Selection Register
PIC16F15213/14
RA2
PIC16F15223/24
RA2
PIC16F15243/44
RA2
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
T0CKI
RA2
RA2
RA2
T1CKI
RA5
RA5
RA5
T1G
RA4
RA4
RA4
T2IN
T2INPPS
RA5
RA5
RA5
CCP1
CCP1PPS
CCP2PPS
SSP1CLKPPS(1)
SSP1DATPPS(1)
SS1PPS
RA5
RC5
RC5
CCP2
RA5
RC3
RC3
SCL1/SCK1
SDA1/SDI1
SS1
RA1
RC0
RB4
RA2
RC1
RB6
RA3
RC3
RC6
RX1/DT1
TX1/CK1
ADACT
RX1PPS(1)
TX1PPS(1)
ADACTPPS
RA1
RC5
RB5
RA0
RC4
RB7
RA5
RC2
RC2
Note:ꢀ
1. Bidirectional pin. The corresponding output must select the same pin.
18.3
PPS Outputs
Each digital peripheral has a dedicated Pin Rxy Output Source Selection (RxyPPS) register with which the pin output
source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin
output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS
control as needed. The I2C module is an example of such a peripheral.
Important:ꢀ The notation “Rxy” is a place holder for the pin identifier. The ‘x’ holds the place of the PORT
letter and the ‘y’ holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register.
The PPS Output Selection Table below shows the output codes for each peripheral, as well as the available Port
selections.
Table 18-2.ꢀPPS Output Selection Table
RxyPPS
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Output Source
TMR0
SDA1/SDO1(1)
SCL1/SCK1(1)
DT1(1)
TX1/CK1(1)
PWM4
PWM3
CCP2
CCP1
LATxy
DS40002195A-page 150
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PPS - Peripheral Pin Select Module
Note:ꢀ
1. Bidirectional pin. The corresponding input must select the same pin.
18.4
Bidirectional Pins
PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS
output select the same pin. The I2C Serial Clock (SCL) and Serial Data (SDA) are examples of such pins.
Important:ꢀ The I2C default pins, and a limited number of other alternate pins, are I2C and SMBus
compatible. SDA and SCL signals can be routed to any pin; however, pins without I2C compatibility will
operate at standard TTL/ST logic levels as selected by the port’s INLVL register.
18.5
PPS Lock
The PPS module provides an extra layer of protection to prevent inadvertent changes to the PPS selection registers.
The PPSLOCKED bit is used in combination with specific code execution blocks to lock/unlock the PPS selection
registers.
Important:ꢀ The PPSLOCKED bit is clear by default (PPSLOCKED = 0), which allows the PPS selection
registers to be modified without an unlock sequence.
PPS selection registers are locked when the PPSLOCKED bit is set (PPSLOCKED = 1). Setting the PPSLOCKED bit
requires a specific lock sequence as shown in the examples below in both C and assembly languages.
PPS selection registers are unlocked when the PPSLOCKED bit is clear (PPSLOCKED = 0). Clearing the
PPSLOCKED bit requires a specific unlock sequence as shown in the examples below in both C and assembly
languages.
Important:ꢀ All interrupts should be disabled before starting the lock/unlock sequence to ensure proper
execution.
Example 18-1.ꢀPPS Lock Sequence (Assembly language)
; suspend interrupts
BCF
INTCON0,GIE
BANKSEL PPSLOCK
; required sequence, next 5 instructions
MOVLW
MOVWF
MOVLW
MOVWF
0x55
PPSLOCK
0xAA
PPSLOCK
; Set PPSLOCKED bit
BSF
PPSLOCK,PPSLOCKED
; restore interrupts
BSF
INTCON0,GIE
Example 18-2.ꢀPPS Lock Sequence (C language)
INTCON0bits.GIE = 0;
PPSLOCK = 0x55;
//Suspend interrupts
//Required sequence
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PPS - Peripheral Pin Select Module
PPSLOCK = 0xAA;
PPSLOCKbits.PPSLOCKED = 1;
INTCON0bits.GIE = 1;
//Required sequence
//Set PPSLOCKED bit
//Restore interrupts
Example 18-3.ꢀPPS Unlock Sequence (Assembly language)
; suspend interrupts
BCF
INTCON0,GIE
BANKSEL PPSLOCK
; required sequence, next 5 instructions
MOVLW
MOVWF
MOVLW
MOVWF
0x55
PPSLOCK
0xAA
PPSLOCK
; Clear PPSLOCKED bit
BCF
PPSLOCK,PPSLOCKED
; restore interrupts
BSF
INTCON0,GIE
Example 18-4.ꢀPPS Unlock Sequence (C language)
INTCON0bits.GIE = 0;
PPSLOCK = 0x55;
//Suspend interrupts
//Required sequence
//Required sequence
//Clear PPSLOCKED bit
//Restore interrupts
PPSLOCK = 0xAA;
PPSLOCKbits.PPSLOCKED = 0;
INTCON0bits.GIE = 1;
18.5.1 PPS One-Way Lock
The PPS1WAY Configuration bit can also be used to prevent inadvertent modification to the PPS selection registers.
When the PPS1WAY bit is set (PPS1WAY = 1), the PPSLOCKED bit can only be set one time after a device Reset.
Once the PPSLOCKED bit has been set, it cannot be cleared again unless a device Reset is executed.
When the PPS1WAY bit is clear (PPS1WAY = 0), the PPSLOCKED bit can be set or cleared as needed; however, the
PPS lock/unlock sequences must be executed.
18.6
18.7
Operation During Sleep
PPS input and output selections are unaffected by Sleep.
Effects of a Reset
A device Power-on Reset (POR) or Brown-out Reset (BOR) returns all PPS input selection registers to their default
values, and clears all PPS output selection registers. All other Resets leave the selections unchanged. Default input
selections are shown in the PPS input register details table. The PPSLOCKED bit is cleared in all Reset conditions.
18.8
Register Definitions: Peripheral Pin Select (PPS)
DS40002195A-page 152
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PPS - Peripheral Pin Select Module
18.8.1 xxxPPS
Name:ꢀ
xxxPPS
Peripheral Input Selection Register
Bit
7
6
5
4
3
2
1
PIN[2:0]
R/W
m
0
PORT[1:0]
Access
Reset
R/W
m
R/W
m
R/W
m
R/W
m
Bits 4:3 – PORT[1:0]ꢀ Peripheral Input PORT Selection(1)
See the PPS Input Selection Table for the list of available Ports and default pin locations.
Reset States: POR = mm
All other Resets = uu
Value
010
Description
PORTC
001
PORTB
000
PORTA
Bits 2:0 – PIN[2:0]ꢀ Peripheral Input PORT Pin Selection(2)
Reset States: POR = mmm
All other Resets = uuu
Value
111
110
101
100
011
010
001
000
Description
Peripheral input is from PORTx Pin 7 (Rx7)
Peripheral input is from PORTx Pin 6 (Rx6)
Peripheral input is from PORTx Pin 5 (Rx5)
Peripheral input is from PORTx Pin 4 (Rx4)
Peripheral input is from PORTx Pin 3 (Rx3)
Peripheral input is from PORTx Pin 2 (Rx2)
Peripheral input is from PORTx Pin 1 (Rx1)
Peripheral input is from PORTx Pin 0 (Rx0)
Note:ꢀ
1. The Reset value ‘m’ is determined by device default locations for that input.
2. Refer to the Pin Allocation Table for details about available pins per port.
DS40002195A-page 153
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PPS - Peripheral Pin Select Module
18.8.2 RxyPPS
Name:ꢀ
RxyPPS
Pin Rxy Output Source Selection Register
Bit
7
6
5
4
3
2
1
0
RxyPPS[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 5:0 – RxyPPS[5:0]ꢀPin Rxy Output Source Selection
See the PPS Output Selection Table for the list of RxyPPS Output Source codes
Reset States: POR = 000000
All other Resets = uuuuuu
DS40002195A-page 154
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PPS - Peripheral Pin Select Module
18.8.3 PPSLOCK
Name:ꢀ
PPSLOCK
PPS Lock Register
Bit
7
6
5
4
3
2
1
0
PPSLOCKED
Access
Reset
R/W
0
Bit 0 – PPSLOCKEDꢀPPS Locked
Reset States: POR = 0
All other Resets = 0
Value
1
0
Description
PPS is locked. PPS selections cannot be changed. Writes to any PPS register are ignored.
PPS is not locked. PPS selections can be changed, but may require the PPS lock/unlock sequence.
DS40002195A-page 155
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PPS - Peripheral Pin Select Module
18.9
Register Summary: Peripheral Pin Select Module
Address
Name
Bit Pos.
0x00
...
Reserved
0x1E8F
0x1E90
0x1E91
0x1E92
0x1E93
0x1E94
...
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
7:0
7:0
7:0
7:0
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
Reserved
T2INPPS
Reserved
0x1E9B
0x1E9C
0x1E9D
...
7:0
PORT[1:0]
PIN[2:0]
0x1EA0
0x1EA1
0x1EA2
0x1EA3
...
CCP1PPS
CCP2PPS
7:0
7:0
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
Reserved
0x1EC2
0x1EC3
0x1EC4
0x1EC5
0x1EC6
0x1EC7
0x1EC8
...
ADACTPPS
Reserved
7:0
PORT[1:0]
PIN[2:0]
SSP1CLKPPS
SSP1DATPPS
SSP1SSPPS
7:0
7:0
7:0
PORT[1:0]
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
Reserved
0x1ECA
0x1ECB
0x1ECC
0x1ECD
...
RX1PPS
TX1PPS
7:0
7:0
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
Reserved
0x1F0F
0x1F10
0x1F11
0x1F12
0x1F13
0x1F14
0x1F15
0x1F16
...
RA0PPS
RA1PPS
RA2PPS
Reserved
RA4PPS
RA5PPS
7:0
7:0
7:0
RA0PPS[5:0]
RA1PPS[5:0]
RA2PPS[5:0]
7:0
7:0
RA4PPS[5:0]
RA5PPS[5:0]
Reserved
0x1F1B
0x1F1C
0x1F1D
0x1F1E
0x1F1F
0x1F20
0x1F21
0x1F22
0x1F23
0x1F24
0x1F25
0x1F26
0x1F27
RB4PPS
RB5PPS
RB6PPS
RB7PPS
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS
RC7PPS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RB4PPS[5:0]
RB5PPS[5:0]
RB6PPS[5:0]
RB7PPS[5:0]
RC0PPS[5:0]
RC1PPS[5:0]
RC2PPS[5:0]
RC3PPS[5:0]
RC4PPS[5:0]
RC5PPS[5:0]
RC6PPS[5:0]
RC7PPS[5:0]
DS40002195A-page 156
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TMR0 - Timer0 Module
19.
TMR0 - Timer0 Module
The Timer0 module has the following features:
•
•
•
•
•
•
•
•
•
8-bit timer with programmable period
16-bit timer
Selectable clock sources
Synchronous and asynchronous operation
Programmable prescaler (Independent of Watchdog Timer)
Programmable postscaler
Interrupt on match or overflow
Output on I/O pin (via PPS) or to other peripherals
Operation during Sleep
Figure 19-1.ꢀTimer0 Block Diagram
Rev. Timer0 Blo
2/12/201 9
Peripherals
See T0CON1
TMR0
body
T0CKPS
T0OUTPS
Register
T0IF
1
0
Prescaler
IN
OUT
T0_out
Postscaler
SYNC
TMR0
FOSC/4
T016BIT
PPS
T0CKIPPS
T0ASYNC
Q
Q
D
PPS
RxyPPS
CK
T0CS
16-bit TMR0 Body Diagram (T016BIT = 1)
8-bit TMR0 Body Diagram (T016BIT = 0)
Clear
IN
Timer 0 High
OUT
IN
R
TMR0L
TMR0L
Byte
8
Read TMR0L
COMPARATOR
OUT
Write TMR0L
T0_match
8
8
TMR0H
Timer 0 High
Byte
Latch
8
Enable
TMR0H
8
Internal Data Bus
19.1
Timer0 Operation
Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the MD16 bit.
DS40002195A-page 157
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TMR0 - Timer0 Module
19.1.1 8-Bit Mode
In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives
several prescale options (see prescaler control bits, CKPS). In this mode, as shown in Figure 19-1, a buffered version
of TMR0H is maintained.
This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match,
the following events occur:
•
•
TMR0L is reset
The contents of TMR0H are copied to the TMR0H buffer for next comparison
19.1.2 16-Bit Mode
In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives
several prescale options (see prescaler control bits, CKPS). In this mode TMR0H:TMR0L form the 16-bit timer value.
As shown in Figure 19-1, reads and writes of the TMR0H register are buffered. The TMR0H register is updated with
the contents of the high byte of Timer0 when the TMR0L register is read. Similarly, writing the TMR0L register causes
a transfer of the TMR0H register value to the Timer0 high byte.
This buffering allows all 16 bits of Timer0 to be read and written at the same time. Timer0 rolls over to 0x0000 on
incrementing past 0xFFFF. This makes the timer free-running. While actively operating in 16-bit mode, the Timer0
value can be read but not written.
19.2
Clock Selection
Timer0 has several options for clock source selections, the option to operate synchronously/asynchronously and an
available programmable prescaler. The CS bits are used to select the clock source for Timer0.
19.2.1 Synchronous Mode
When the ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When operating in
Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode the system clock is not
available and Timer0 cannot operate.
19.2.2 Asynchronous Mode
When the ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the prescaler, if
used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the selected clock
source operates during Sleep.
19.2.3 Programmable Prescaler
Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected
using the CKPS bits. The prescaler counter is not directly readable or writable. The prescaler counter is cleared on
the following events:
•
•
•
A write to the TMR0L register
A write to either the T0CON0 or T0CON1 registers
Any device Reset
19.2.4 Programmable Postscaler
Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected
using the OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio. The postscaler counter is not
directly readable or writable. The postscaler counter is cleared on the following events:
•
•
•
A write to the TMR0L register
A write to either the T0CON0 or T0CON1 registers
Any device Reset
DS40002195A-page 158
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TMR0 - Timer0 Module
19.3
Timer0 Output and Interrupt
19.3.1 Timer0 Output
TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in
16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. The Timer0 output can be
routed to an I/O pin via the RxyPPS output selection register, or internally to a number of Core Independent
Peripherals. The Timer0 output can be monitored through software via the OUT output bit.
19.3.2 Timer0 Interrupt
The Timer0 Interrupt Flag bit (TMR0IF) is set when the TMR0_out toggles. If the Timer0 interrupt is enabled
(TMR0IE), the CPU will be interrupted when the TMR0IF bit is set. When the postscaler bits (T0OUTPS) are set to
1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag
bit will be set every T0OUTPS +1 matches or rollovers.
19.3.3 Timer0 Example
Timer0 Configuration:
•
•
•
•
•
Timer0 mode = 16-bit
Clock Source = FOSC/4 (250 kHz)
Synchronous operation
Prescaler = 1:1
Postscaler = 1:2 (T0OUTPS = 1)
In this case the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e.,
(0xFFFF)*2*(1/250kHz) = 524.28 ms
19.4
19.5
Operation During Sleep
When operating synchronously, Timer0 will halt when the device enters Sleep mode. When operating asynchronously
and the selected clock source is active, Timer0 will continue to increment and wake the device from Sleep mode if the
Timer0 interrupt is enabled.
Register Definitions: Timer0 Control
DS40002195A-page 159
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TMR0 - Timer0 Module
19.5.1 T0CON0
Name:ꢀ
T0CON0
Address:ꢀ 0x59E
Timer0 Control Register 0
Bit
7
EN
R/W
0
6
5
OUT
R
4
MD16
R/W
0
3
2
1
0
OUTPS[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – ENꢀTMR0 Enable
Value
Description
1
0
The module is enabled and operating
The module is disabled
Bit 5 – OUTꢀTMR0 Output
Bit 4 – MD16ꢀ16-Bit Timer Operation Select
Value
Description
1
0
TMR0 is a 16-bit timer
TMR0 is an 8-bit timer
Bits 3:0 – OUTPS[3:0]ꢀTMR0 Output Postscaler (Divider) Select
Value
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
1:16 Postscaler
1:15 Postscaler
1:14 Postscaler
1:13 Postscaler
1:12 Postscaler
1:11 Postscaler
1:10 Postscaler
1:9 Postscaler
1:8 Postscaler
1:7 Postscaler
1:6 Postscaler
1:5 Postscaler
1:4 Postscaler
1:3 Postscaler
1:2 Postscaler
1:1 Postscaler
DS40002195A-page 160
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TMR0 - Timer0 Module
19.5.2 T0CON1
Name:ꢀ
T0CON1
Address:ꢀ 0x59F
Timer0 Control Register 1
Bit
7
6
CS[2:0]
R/W
0
5
4
ASYNC
R/W
0
3
2
1
0
CKPS[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:5 – CS[2:0]ꢀTimer0 Clock Source Select
Table 19-1.ꢀTimer0 Clock Source Selections
T0CS
Clock Source
111-110
101
Reserved
MFINTOSC(500 kHz)
LFINTOSC
100
011
HFINTOSC
010
FOSC/4
001
Pin selected by T0CKIPPS (Inverted)
000
Pin selected by T0CKIPPS (Non-inverted)
Bit 4 – ASYNCꢀTMR0 Input Asynchronization Enable
Value
Description
1
0
The input to the TMR0 counter is not synchronized to system clocks
The input to the TMR0 counter is synchronized to Fosc/4
Bits 3:0 – CKPS[3:0]ꢀPrescaler Rate Select
Value
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
1:32768
1:16384
1:8192
1:4096
1:2048
1:1024
1:512
1:256
1:128
1:64
1:32
1:16
1:8
1:4
1:2
1:1
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TMR0 - Timer0 Module
19.5.3 TMR0H
Name:ꢀ
TMR0H
Address:ꢀ 0x59D
Timer0 Period/Count High Register
Bit
7
6
5
4
3
2
1
0
TMR0H[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – TMR0H[7:0]ꢀTMR0 Most Significant Counter
Value
Condition Description
0 to 255
MD16 = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value is reached.
0 to 255
MD16 = 1 16-bit Timer0 Most Significant Byte
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TMR0 - Timer0 Module
19.5.4 TMR0L
Name:ꢀ
TMR0L
Address:ꢀ 0x59C
Timer0 Period/Count Low Register
Bit
7
6
5
4
3
2
1
0
TMR0L[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TMR0L[7:0]ꢀTMR0 Least Significant Counter
Value
0 to 255
0 to 255
Condition
MD16 = 0
MD16 = 1
Description
8-bit Timer0 Counter bits
16-bit Timer0 Least Significant Byte
DS40002195A-page 163
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TMR0 - Timer0 Module
19.6
Register Summary: Timer0
Address
Name
Bit Pos.
0x00
...
Reserved
0x059B
0x059C
0x059D
0x059E
0x059F
TMR0L
TMR0H
T0CON0
T0CON1
7:0
7:0
7:0
7:0
TMR0L[7:0]
TMR0H[7:0]
EN
OUT
MD16
OUTPS[3:0]
CKPS[3:0]
CS[2:0]
ASYNC
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TMR1 - Timer1 Module with Gate Control
20.
TMR1 - Timer1 Module with Gate Control
The Timer1 module is a 16-bit timer/counter with the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMRxH:TMRxL)
Programmable internal or external clock source
2-bit prescaler
Clock source for optional comparator synchronization
Multiple Timer1 gate (count enable) sources
Interrupt-on-overflow
Wake-up on overflow (external clock, Asynchronous mode only)
16-bit read/write operation
Time base for the capture/compare function with the CCP modules
Special event trigger (with CCP)
Selectable gate source polarity
Gate Toggle mode
Gate Single-Pulse mode
Gate value status
Gate event interrupt
Important:ꢀ References to the module Timer1 apply to all the odd numbered timers on this device.
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TMR1 - Timer1 Module with Gate Control
Figure 20-1.ꢀTimer1 Block Diagram
TxGATE
4
TxGPPS
GSPM
0000
PPS
1
D
Q
GVAL
0
1
Single Pulse
Acq. Control
NOTE (5)
0
1111
Q1
D
Q
Q
GPOL
ON
GGO/DONE
CK
R
Interrupt
det
set bit
TMRxGIF
GTM
GE
set flag bit
TMRxIF
ON
EN
D
To Comparators (6)
Synchronized Clock Input
TMRx(2)
Tx_overflow
Q
TMRxH
TMRxL
0
1
TxCLK
SYNC
TxCLK
4
TxCKIPPS
PPS
(1)
0000
Prescaler
1,2,4,8
Synchronize(3)
det
Note (4)
1111
2
Fosc/2
Internal
Clock
CKPS
Sleep
Input
Note:ꢀ
1. This signal comes from the pin selected by Timer1 PPS register.
2. TMRx register increments on rising edge.
3. Synchronize does not operate while in Sleep.
4. See TxCLK for clock source selections.
5. See TxGATE for gate source selections.
6. Synchronized comparator output should not be used in conjunction with synchronized input clock.
20.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRx register. Writes to TMRx
directly update the counter. When used with an internal clock source, the module is a timer that increments on every
instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and
increments on every selected edge of the external source.
Timer1 is enabled by configuring the ON and GE bits. Table 20-1 displays the possible Timer1 enable selections.
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TMR1 - Timer1 Module with Gate Control
Table 20-1.ꢀTimer1 Enable Selections
ON
1
GE
1
Timer1 Operation
Count Enabled
Always On
Off
1
0
0
1
0
0
Off
20.2
Clock Source Selection
The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and
asynchronous clock sources.
20.2.1 Internal Clock Source
When the internal clock source is selected the TMRx register will increment on multiples of FOSC as determined by
the Timer1 prescaler.
When the FOSC internal clock source is selected, the TMRx register value will increment by four counts every
instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the TMRx value. To
utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.
Important:ꢀ In Counter mode, a falling edge must be registered by the counter prior to the first
incrementing rising edge after any one or more of the following conditions:
•
•
•
•
Timer1 enabled after POR
Write to TMRxH or TMRxL
Timer1 is disabled
Timer1 is disabled (ON = 0) when TxCKI is high then Timer1 is enabled (ON = 1) when TxCKI is low.
Refer to the figure below.
Figure 20-2.ꢀTimer1 Incrementing Edge
TxCKI = 1
When TMRx
Enabled
TxCKI = 0
When TMRx
Enabled
Note:ꢀ
1. Arrows indicate counter increments.
2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
20.2.2 External Clock Source
When the external clock source is selected, the TMRx module may work as a timer or a counter. When enabled to
count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock
source can be synchronized to the system clock or it can run asynchronously.
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TMR1 - Timer1 Module with Gate Control
20.3
20.4
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale
counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a
write to TMRx.
Timer1 Operation in Asynchronous Counter Mode
When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously
to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep
and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in
software are needed to read/write the timer.
Important:ꢀ When switching from synchronous to asynchronous operation, it is possible to skip an
increment. When switching from asynchronous to synchronous operation, it is possible to produce an
additional increment.
20.4.1 Reading and Writing TMRx in Asynchronous Counter Mode
Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read
(taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values
itself, poses certain problems, since there may be a carry out of TMRxL to TMRxH between the reads.
For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may
occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in
the TMRxH:TMRxL register pair.
20.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured to read and write all 16 bits of data to and from the 8-bit TMRxL and TMRxH registers,
simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit. To accomplish this function,
the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the
TMRxH register is not directly readable or writable and all read and write operations take place through the use of
this TMRxH buffer register.
When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the
TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH
buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from a
single instance in time. Refer to the figure below for more details. In contrast, when not in 16-Bit mode, the user must
read each register separately and determine if the values have become invalid due to a rollover that may have
occurred between the read operations.
When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with
the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to
the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRx register
at the same time. Any requests to write to TMRxH directly does not clear the Timer1 prescaler value. The prescaler
value is only cleared through write requests to the TMRxL register.
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TMR1 - Timer1 Module with Gate Control
Figure 20-3.ꢀTimer1 16-Bit Read/Write Mode Block Diagram
From
TMRx
Circuitry
TMRx
High Byte
Set TMRxIF
on Overflow
TMRxL
8
Read TMRxL
Write TMRxL
8
8
TMRxH
8
8
Internal Data Bus
20.6
Timer1 Gate
Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is
also referred to as Timer1 gate enable. Timer1 gate can also be driven by multiple selectable sources.
20.6.1 Timer1 Gate Enable
The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is
configured using the GPOL bit.
When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source.
When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is
disabled, no incrementing will occur and Timer1 will hold the current count. See figure below for timing details.
Table 20-2.ꢀTimer1 Gate Enable Selections
TMRxCLK
GPOL
TxG
1
Timer1 Operation
Counts
1
1
0
0
↑
↑
↑
↑
0
Holds Count
Holds Count
Counts
1
0
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TMR1 - Timer1 Module with Gate Control
Figure 20-4.ꢀTimer1 Gate Enable Mode
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1
20.6.2 Timer1 Gate Source Selection
The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by
the GPOL bit.
20.6.3 Timer1 Gate Toggle Mode
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 Gate signal, as
opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes
state on every incrementing edge of the signal. See figure below for timing details.
Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and
held clear. This is necessary in order to control which edge is measured.
Important:ꢀ Enabling Toggle mode at the same time as changing the gate polarity may result in
indeterminate operation.
Figure 20-5.ꢀTimer1 Gate Toggle Mode
TMRxGE
TxGPOL
TxGTM
TxTxG_IN
TxCKI
TxGVAL
Timer1
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TMR1 - Timer1 Module with Gate Control
20.6.4 Timer1 Gate Single Pulse Mode
When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate
Single Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be set. The Timer1 will be
fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will
automatically be cleared. No other gate events will be allowed to increment Timer1 until the GGO/DONE bit is once
again set in software.
Figure 20-6.ꢀTimer1 Gate Single Pulse Mode
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
Set by software
falling edge of TxGVAL
TxGGO/
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1
Cleared by
software
Set by hardware on
falling edge of TxGVAL
Cleared by software
TMRxGIF
Clearing the GSPM bit will also clear the GGO/DONE bit. See the figure below for timing details. Enabling the Toggle
mode and the Single Pulse mode simultaneously will permit both sections to work together. This allows the cycle
times on the Timer1 gate source to be measured. See figure below for timing details.
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TMR1 - Timer1 Module with Gate Control
Figure 20-7.ꢀTimer1 Gate Single Pulse and Toggle Combined Mode
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
falling edge of TxGVAL
Set by software
TxGGO/
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1
Cleared by
software
Set by hardware on
falling edge of TxGVAL
Cleared by software
TMRxGIF
20.6.5 Timer1 Gate Value Status
When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The
value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not
enabled (GE bit is cleared).
20.6.6 Timer1 Gate Event Interrupt
When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate
event. When the falling edge of GVAL occurs, the TMRxGIF flag bit will be set. If the TMRxGIE bit in the
corresponding PIE register is set, then an interrupt will be recognized.
The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared).
20.7
Timer1 Interrupt
The TMRx register increments to FFFFh and rolls over to 0000h. When TMRx rolls over, the TMRx interrupt flag
(TMRxIF) bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set:
•
•
•
ON bit of the TxCON register
TMRxIE bits of the PIEx register
Global interrupts must be enabled
The interrupt is cleared by clearing the TMRxIF bit as a task in the Interrupt Service Routine.
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TMR1 - Timer1 Module with Gate Control
Important:ꢀ The TMRx register and the TMRxIF bit should be cleared before enabling interrupts.
20.8
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when configured as an asynchronous counter. In this mode, many clock
sources can be used to increment the counter. To set up the timer to wake the device:
•
•
•
•
•
ON bit must be set
TMRxIE bit of the PIEx register must be set
Global interrupts must be enabled
SYNC bit must be set
Configure the TxCLK register for using any clock source other than FOSC and FOSC/4
The device will wake-up on an overflow and execute the next instruction. If global interrupts are enabled, the device
will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the
SYNC bit setting.
20.9
CCP Capture/Compare Time Base
The CCP modules use TMRx as the time base when operating in Capture or Compare mode. In Capture mode, the
value in TMRx is copied into the CCPRx register on a capture event. In Compare mode, an event is triggered when
the value in the CCPRx register matches the value in TMRx. This event can be a Special Event Trigger. For more
information, see the “CCP - Capture/Compare/PWM Module” chapter.
20.10 CCP Special Event Trigger
When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRx register. This special
event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this
mode of operation, the CCPRx register becomes the period register for Timer1. Timer1 should be synchronized and
FOSC/4 should be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation
of Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides
with a Special Event Trigger from the CCP, the write will take precedence.
20.11 Register Definitions: Timer1 Control
Long bit name prefixes for the System Arbiter Priority Registers are shown in the table below where “x” refers to the
Priority Register instance number. Refer to the “Long Bit Names” section in the “Register and Bit Naming
Conventions” chapter for more information.
Table 20-3.ꢀTimer1 Register Bit Name Prefixes
Peripheral
Bit Name Prefix
Timer1
T1
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TMR1 - Timer1 Module with Gate Control
20.11.1 TxCON
Name:ꢀ
TxCON
Address:ꢀ 0x20E
Timer Control Register
Bit
7
6
5
4
3
2
SYNC
R/W
0
1
RD16
R/W
0
0
ON
R/W
0
CKPS[1:0]
Access
Reset
R/W
0
R/W
0
Bits 5:4 – CKPS[1:0]ꢀTimer Input Clock Prescaler Select
Reset States: POR/BOR = 00
All Other Resets = uu
Value
11
10
01
00
Description
1:8 Prescaler value
1:4 Prescaler value
1:2 Prescaler value
1:1 Prescaler value
Bit 2 – SYNCꢀTimer External Clock Input Synchronization Control
Reset States: POR/BOR = 0
All Other Resets = u
Value
Condition
Description
x
1
0
CS = FOSC/4 or FOSC
All other clock sources
All other clock sources
This bit is ignored. Timer uses the incoming clock as is.
Do not synchronize external clock input
Synchronize external clock input with system clock
Bit 1 – RD16ꢀ16-Bit Read/Write Mode Enable
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
Enables register read/write of Timer in one 16-bit operation
Enables register read/write of Timer in two 8-bit operations
Bit 0 – ONꢀTimer On
Reset States: POR/BOR = 0
All Other Resets = u
Description
Value
1
0
Enables Timer
Disables Timer
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TMR1 - Timer1 Module with Gate Control
20.11.2 TxGCON
Name:ꢀ
TxGCON
Address:ꢀ 0x20F
Timer Gate Control Register
Bit
7
GE
R/W
0
6
GPOL
R/W
0
5
GTM
R/W
0
4
GSPM
R/W
0
3
2
GVAL
R
1
0
GGO/DONE
Access
Reset
R/W
0
x
Bit 7 – GEꢀTimer Gate Enable
Reset States: POR/BOR = 0
All Other Resets = u
Value
1
Condition
ON = 1
Description
Timer counting is controlled by the Timer gate function
0
X
ON = 1
ON = 0
Timer is always counting
This bit is ignored
Bit 6 – GPOLꢀTimer Gate Polarity
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
Timer gate is active-high (Timer counts when gate is high)
Timer gate is active-low (Timer counts when gate is low)
Bit 5 – GTMꢀTimer Gate Toggle Mode
Timer Gate Flip-Flop Toggles on every rising edge when Toggle mode is enabled.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
Timer Gate Toggle mode is enabled
Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared
Bit 4 – GSPMꢀTimer Gate Single Pulse Mode
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
Timer Gate Single Pulse mode is enabled and is controlling Timer gate
Timer Gate Single Pulse mode is disabled
Bit 3 – GGO/DONEꢀTimer Gate Single Pulse Acquisition Status
This bit is automatically cleared when TxGSPM is cleared.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
0
Timer Gate Single Pulse Acquisition is ready, waiting for an edge
Timer Gate Single Pulse Acquisition has completed or has not been started
Bit 2 – GVALꢀTimer Gate Current State
Indicates the current state of the timer gate that could be provided to TMRxH:TMRxL
Unaffected by Timer Gate Enable (GE bit)
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TMR1 - Timer1 Module with Gate Control
20.11.3 TxCLK
Name:ꢀ
TxCLK
Address:ꢀ 0x211
Timer Clock Source Selection Register
Bit
7
6
5
4
3
2
CS[4:0]
R/W
0
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 4:0 – CS[4:0]ꢀTimer Clock Source Selection
Table 20-4.ꢀTimer Clock Sources
CS
11111-01001
01000
Clock Source
Reserved
TMR0_OUT
00111
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
SFINTOSC (1 MHz)
LFINTOSC
00110
00101
00100
00011
HFINTOSC
00010
FOSC
00001
FOSC/4
00000
Pin selected by T1CKIPPS
Reset States: POR/BOR = 00000
All Other Resets = uuuuu
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TMR1 - Timer1 Module with Gate Control
20.11.4 TxGATE
Name:ꢀ
TxGATE
Address:ꢀ 0x210
Timer Gate Source Selection Register
Bit
7
6
5
4
3
2
GSS[4:0]
R/W
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bits 4:0 – GSS[4:0]ꢀTimer Gate Source Selection
Table 20-5.ꢀTimer Gate Sources
GSS
11111-00111
00110
Gate Source
Reserved
PWM4_OUT
PWM3_OUT
CCP2_OUT
CCP1_OUT
00101
00100
00011
00010
TMR2_Postscaler_OUT
TMR0_OUT
00001
00000
Pin selected by T1GPPS
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TMR1 - Timer1 Module with Gate Control
20.11.5 TMRx
Name:ꢀ
TMRx
Address:ꢀ 0x20C
Timer Register
15
Bit
14
13
12
11
10
9
8
TMRx[15:8]
TMRx[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRx[15:0]ꢀTimer Register Value
Reset States: POR/BOR = 0000000000000000
All Other Resets = uuuuuuuuuuuuuuuu
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
TMRxH: Accesses the high byte TMRx[15:8]
TMRxL: Accesses the low byte TMRx[7:0]
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TMR1 - Timer1 Module with Gate Control
20.12 Register Summary Timer 1
Address
Name
Bit Pos.
0x00
...
Reserved
0x020B
7:0
15:8
7:0
7:0
7:0
7:0
TMR1[7:0]
0x020C
TMRx
TMR1[15:8]
0x020E
0x020F
0x0210
0x0211
TxCON
TxGCON
TxGATE
TxCLK
CKPS[1:0]
GTM GSPM
SYNC
GVAL
RD16
ON
GE
GPOL
GGO/DONE
GSS[4:0]
CS[4:0]
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TMR2 - Timer2 Module
21.
TMR2 - Timer2 Module
The Timer2 module is a 8-bit timer that incorporates the following features:
•
•
•
•
•
•
•
•
•
•
•
8-bit timer and period registers
Readable and writable
Software programmable prescaler (1:1 to 1:128)
Software programmable postscaler (1:1 to 1:16)
Interrupt on T2TMR match with T2PR
One-shot operation
Full asynchronous operation
Includes Hardware Limit Timer (HLT)
Alternate clock sources
External timer Reset signal sources
Configurable timer Reset operation
See Figure 21-1 for a block diagram of Timer2.
Important:ꢀ References to module Timer2 apply to all the even numbered timers on this device. (Timer2,
Timer4, etc.)
Figure 21-1.ꢀTimer2 with Hardware Limit Timer (HLT) Block Diagram
RSEL
Rev. 10-000168D
4/29/2019
TxINPPS
TxIN
PPS
MODE
MODE[3]
External
Reset
TMRx_ers
reset
Edge Detector
Level Detector
Mode Control
(2 clock Sync)
CCP_pset(1)
Sources(2)
MODE[4:3]=’b01
enable
CKPOL
CS
Clear ON
D
Q
MODE[4:1]=’b1011
TMRx_clk
TxINPPS
TxIN
PPS
Prescaler
CKPS
0
R
TxTMR
Set flag bit
TMRxIF
Sync
Fosc/4
1
See
TxCLKCON
register(3)
PSYNC
TMRx_postscaled
Comparator
TxPR
Postscaler
Sync
(2 Clocks)
1
0
OUTPS
ON
CSYNC
Note:ꢀ
1. Signal to the CCP peripheral for PWM pulse trigger in PWM mode.
2. See RSEL for external Reset sources.
3. See CS for clock source selections.
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TMR2 - Timer2 Module
21.1
Timer2 Operation
Timer2 operates in three major modes:
•
•
•
Free-Running Period
One-shot
Monostable
Within each operating mode there are several options for starting, stopping, and Reset. Table 21-1 lists the options.
In all modes, the T2TMR count register increments on the rising edge of the clock signal from the programmable
prescaler. When T2TMR equals T2PR, a high level output to the postscaler counter is generated. T2TMR is cleared
on the next clock input.
An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset.
In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes
the T2TMR count is reset on either the level or edge from the external source.
The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the
T2PR register initializes to 0xFF on any device Reset. Both the prescaler and postscaler counters are cleared on the
following events:
•
•
•
•
A write to the T2TMR register
A write to the T2CON register
Any device Reset
External Reset source event that resets the timer.
Important:ꢀ T2TMR is not cleared when T2CON is written.
21.1.1 Free-Running Period Mode
The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two values
match, the comparator resets the value of T2TMR to 0x00 on the next cycle and increments the output postscaler
counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register then a one clock
period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared.
21.1.2 One-Shot Mode
The One-Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and the timer is
stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS)
values other than zero are ignored in this mode because the timer is stopped at the first period event and the
postscaler is reset when the timer is restarted.
21.1.3 Monostable Mode
Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be
restarted by an external Reset event.
21.2
Timer2 Output
The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each
match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time
the T2TMR value matches the T2PR value. This signal can also be selected as an input to other Core Independent
Peripherals:
In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See “PWM Overview”
and “PWM Period” sections in the “CCP - Capture/Compare/PWM Module” chapter for more details on setting up
Timer2 for use with the CCP and PWM modules.
DS40002195A-page 181
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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TMR2 - Timer2 Module
21.3
21.4
External Reset Sources
In addition to the clock source, the Timer2 can also be driven by an external Reset source input. This external Reset
input is selected for each timer with the corresponding TxRST register. The external Reset input can control starting
and stopping of the timer, as well as resetting the timer, depending on the mode used.
Timer2 Interrupt
Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches the
selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt
enable bit. Interrupt timing is illustrated in the figure below.
Figure 21-2.ꢀTimer2 Prescaler, Postscaler, and Interrupt Timing Diagram
Rev. 10-000 205B
3/6/201 9
CKPS
TxPR
b010
1
OUTPS
b0001
TMRx_clk
TxTMR
0
1
0
1
0
1
0
TMRx_postscaled
TMRxIF
(1)
(2)
(1)
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
21.5
21.6
PSYNC bit
Setting the PSYNC bit synchronizes the prescaler output to FOSC/4. Setting this bit is required for reading the Timer2
counter register while the selected Timer clock is asynchronous to FOSC/4.
Note:ꢀ Setting PSYNC requires that the output of the prescaler is slower than FOSC/4. Setting PSYNC when the
output of the prescaler is greater than or equal to FOSC/4 may cause unexpected results.
CSYNC bit
All bits in the Timer2 SFRs are synchronized to FOSC/4 by default, not the Timer2 input clock. As such, if the Timer2
input clock is not synchronized to FOSC/4, it is possible for the Timer2 input clock to transition at the same time as the
ON bit is set in software, which may cause undesirable behavior and glitches in the counter. Setting the CSYNC bit
remedies this problem by synchronizing the ON bit to the Timer2 input clock instead of FOSC/4. However, as this
synchronization uses an edge of the TMR2 input clock, up to one input clock cycle will be consumed and not counted
by the Timer2 when CSYNC is set. Conversely, clearing the CSYNC bit synchronizes the ON bit to FOSC/4, which
does not consume any clock edges, but has the previously stated risk of glitches.
DS40002195A-page 182
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TMR2 - Timer2 Module
21.7
Operating Modes
The mode of the timer is controlled by the MODE bits. Edge-Triggered modes require six Timer clock periods
between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods
long. External triggers are ignored while in Debug mode.
Table 21-1.ꢀOperating Modes Table
MODE
[4:3] [2:0]
000
Output
Operation
Timer Control
Mode
Operation
Start
Reset
—
Stop
Software gate (Figure 21-3)
ON = 1
ON = 0
ON = 1and
TMRx_ers = 1
—
ON = 0or
TMRx_ers = 0
Hardware gate, active-high
(Figure 21-4)
001
010
Period Pulse
ON = 1and
TMRx_ers = 0
—
ON = 0or
TMRx_ers = 1
Hardware gate, active-low
Free-
Running Period
011
00
Rising or falling edge Reset
Rising edge Reset (Figure 21-5)
Falling edge Reset
TMRx_ers ↕
TMRx_ers ↑
TMRx_ers ↓
Period
Pulse
100
ON = 0
101
110
with
Hardware
Reset
ON = 0or
TMRx_ers = 0
ON = 1
ON = 1
TMRx_ers = 0
Low level Reset
High level Reset (Figure 21-6)
ON = 0or
TMRx_ers = 1
111
000
001
TMRx_ers = 1
One-shot
Software start (Figure 21-7)
—
—
ON = 1and
TMRx_ers ↑
Rising edge start (Figure 21-8)
Edge-
Triggered Start
ON = 1and
TMRx_ers ↓
010
011
Falling edge start
Any edge start
—
(Note 1)
ON = 0
ON = 1and
TMRx_ers ↕
—
or
Next clock after
TxTMR = TxPR
(Note 2)
ON = 1and
TMRx_ers ↑
01
Rising edge start and
Rising edge Reset (Figure 21-9)
One-shot
100
TMRx_ers ↑
TMRx_ers ↓
TMRx_ers = 0
TMRx_ers = 1
Edge-
Triggered Start
ON = 1and
TMRx_ers ↓
Falling edge start and
Falling edge Reset
101
110
111
and
ON = 1and
TMRx_ers ↑
Rising edge start and
Low level Reset (Figure 21-10)
Hardware Reset
(Note 1)
ON = 1and
TMRx_ers ↓
Falling edge start and
High level Reset
DS40002195A-page 183
Preliminary Datasheet
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TMR2 - Timer2 Module
...........continued
Mode
MODE
[4:3] [2:0]
000
Output
Operation
Timer Control
Operation
Start
Reset
Stop
Reserved
ON = 1and
TMRx_ers ↑
Rising edge start
(Figure 21-11)
ON = 0
001
010
011
—
—
—
Edge-
Triggered
or
ON = 1and
TMRx_ers ↓
Monostable
Next clock after
TxTMR = TxPR
(Note 3)
Falling edge start
Any edge start
Start
(Note 1)
ON = 1and
TMRx_ers ↕
10
100
Reserved
Reserved
Reserved
Reserved
101
Level
Triggered
ON = 1and
TMRx_ers = 1
High level start and
Low level Reset (Figure 21-12)
110
TMRx_ers = 0
TMRx_ers = 1
ON = 0or
Start
and
Held in Reset
One-shot
ON = 1and
TMRx_ers = 0
Low level start and
High level Reset
(Note 2)
111
Hardware Reset
11 xxx
Reserved
Reserved
Note:ꢀ
1. If ON = 0then an edge is required to restart the timer after ON = 1.
2. When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h.
3. When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON.
21.8
Operation Examples
Unless otherwise specified, the following notes apply to the following timing diagrams:
•
•
Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits.)
The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both
ON and TMRx_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for TMRx_ers;
ON applies in the next instruction period.
•
•
ON and TMRx_ers are somewhat generalized, and clock-sync delays may produce results that are slightly
different than illustrated.
The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of
the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module.
21.8.1 Software Gate Mode
This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1and
does not increment when ON = 0. When the TxTMR count equals the TxPR period count the timer resets on the next
clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 21-3. With
TxPR = 5, the counter advances until TxTMR = 5, and goes to zero with the next clock.
DS40002195A-page 184
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TMR2 - Timer2 Module
Figure 21-3.ꢀSoftware Gate Mode Timing Diagram (MODE = ‘b00000)
Rev. 10-000 195C
3/6/201 9
TMRx_clk
Instruction(1)
ON
BSF
BCF
BSF
TxPR
5
3
TxTMR
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 185
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TMR2 - Timer2 Module
21.8.2 Hardware Gate Mode
The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can
also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the
PWM output is high, then the duty cycle is also extended.
When MODE = ‘b00001then the timer is stopped when the external signal is high. When MODE = ‘b00010, then
the timer is stopped when the external signal is low.
Figure 21-4 illustrates the Hardware Gating mode for MODE = ‘b00001in which a high input level starts the counter.
Figure 21-4.ꢀHardware Gate Mode Timing Diagram (MODE = ‘b00001)
Rev. 10-000 196C
3/6/201 9
TMRx_clk
TMRx_ers
TxPR
TxTMR
5
3
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
PWM Output
DS40002195A-page 186
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.3 Edge-Triggered Hardware Limit Mode
In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period
count. Three types of Resets are possible:
•
•
•
Reset on rising or falling edge (MODE= ‘b00011)
Reset on rising edge (MODE = ‘b00100)
Reset on falling edge (MODE = ‘b00101)
When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and
restarts the PWM pulse after a two clock delay. Refer to Figure 21-5.
Figure 21-5.ꢀEdge-Triggered Hardware Limit Mode Timing Diagram
(MODE = ‘b00100)
Rev. 10-000197C
3/6/2019
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BCF BSF
TMRx_ers
TxTMR
0
1
2
0
1
2
3
4
3
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
PWM Output
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by
the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous
to the timer clock input.
Note
DS40002195A-page 187
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TMR2 - Timer2 Module
21.8.4 Level-Triggered Hardware Limit Mode
In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal
TMRx_ers, as shown in Figure 21-6. Selecting MODE = ‘b00110will cause the timer to reset on a low level external
signal. Selecting MODE = ‘b00111will cause the timer to reset on a high level external signal. In the example, the
counter is reset while TMRx_ers = 1. ON is controlled by BSFand BCFinstructions. When ON = 0the external signal
is ignored.
When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts
counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the
timer count matches the TxPR value or two clock periods after the external Reset signal goes true and stays true.
The timer starts counting, and the PWM output is set high, on either the clock following the TxPR match or two clocks
after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to
match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the
PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx
value.
Figure 21-6.ꢀLevel-Triggered Hardware Limit Mode Timing Diagram
(MODE = ‘b00111)
Rev. 10-000 198C
3/5/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BCF
BSF
TMRx_ers
TxTMR
0
1
2
0
1
2
3
4
5
0
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 188
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.5 Software Start One-Shot Mode
In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the TxPR period value.
The ON bit must be set by software to start another timer cycle. Setting MODE = ‘b01000selects One-Shot mode
which is illustrated in Figure 21-7. In the example, ON is controlled by BSFand BCFinstructions. In the first case, a
BSFinstruction sets ON and the counter runs to completion and clears ON. In the second case, a BSFinstruction
starts the cycle, BCF/BSFinstructions turn the counter off and on during the cycle, and then it runs to completion.
When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent
with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive
will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until
software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the
TxPR match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing
cycle can only be initiated by setting the ON bit after it has been cleared by a TxPR period count match.
Figure 21-7.ꢀSoftware Start One-Shot Mode Timing Diagram (MODE = ‘b01000)
Rev. 10-000 199C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BSF
BCF
BSF
TxTMR
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU
to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 189
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.6 Edge-Triggered One-Shot Mode
The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set,
and clear the ON bit when the timer matches the TxPR period value. The following edges will start the timer:
•
•
•
Rising edge (MODE = ‘b01001)
Falling edge (MODE = ‘b01010)
Rising or Falling edge (MODE = ‘b01011)
If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume
counting. Figure 21-8 illustrates operation in the rising edge One-Shot mode.
When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the
PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay
deactivated when the timer halts at the TxPR period count match.
Figure 21-8.ꢀEdge-Triggered One-Shot Mode Timing Diagram (MODE = ‘b01001)
Rev. 10-000 200C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BSF
BCF
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
CCP_pset
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 190
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TMR2 - Timer2 Module
21.8.7 Edge-Triggered Hardware Limit One-Shot Mode
In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit
is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The
counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are
as follows:
•
•
Rising edge start and Reset (MODE = ‘b01100)
Falling edge start and Reset (MODE = ‘b01101)
The timer resets and clears the ON bit when the timer value matches the TxPR period value. External signal edges
will have no effect until after software sets the ON bit. Figure 21-9 illustrates the rising edge hardware limit one-shot
operation.
When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset
edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse width
value and stay deactivated until the timer halts at the TxPR period match unless an external signal edge resets the
timer before the match occurs.
Figure 21-9.ꢀEdge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = ‘b01100)
Rev. 10-000 201C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BSF
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 191
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes
In Level-Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the
rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are
selected as follows:
•
•
Low Reset level (MODE = ‘b01110)
High Reset level (MODE = ‘b01111)
When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit
is cleared by either a TxPR match or by software control, a new external signal edge is required after the ON bit is set
to start the counter.
When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation, the PWM drive
goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count
equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the TxPR
period count match.
Figure 21-10.ꢀLow Level Reset, Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE =
‘b01110)
Rev. 10-000 202C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BSF
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 192
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.9 Edge-Triggered Monostable Modes
The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON
bit is set, and stop incrementing the timer when the timer matches the TxPR period value. The following edges will
start the timer:
•
•
•
Rising edge (MODE = ‘b10001)
Falling edge (MODE = ‘b10010)
Rising or Falling edge (MODE = ‘b10011)
When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive
goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the
TxPR value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP
PWM.
Figure 21-11.ꢀRising Edge-Triggered Monostable Mode Timing Diagram (MODE = ‘b10001)
Rev. 10-000203B
3/6/2019
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BCF
BSF
BCF
BSF
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40002195A-page 193
Preliminary Datasheet
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TMR2 - Timer2 Module
21.8.10 Level-Triggered Hardware Limit One-Shot Modes
The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start
counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external
signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels
are selected as follows:
•
•
Low Reset level (MODE = ‘b10110)
High Reset level (MODE = ‘b10111)
When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit
is cleared by either a TxPR match or by software control, the timer will stay in Reset until both the ON bit is set and
the external signal is not at the Reset level.
When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation, the
PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts
the timer.
Figure 21-12.ꢀLevel-Triggered hardware Limit One-Shot Mode Timing Diagram (MODE = ‘b10110)
Rev. 10-000 204B
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
ON
5
BSF
BSF
BCF
BSF
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
3
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
D3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
21.9
Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and
T2PR registers will remain unchanged while processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any
internal oscillator is selected as the clock source, it will stay active during Sleep mode.
21.10 Register Definitions: Timer2 Control
Long bit name prefixes for the Timer2 peripherals are shown in table below. Refer to Section “Long Bit Names” for
more information.
Table 21-2.ꢀTimer2 Long Bit Name Prefixes
Peripheral
Bit Name Prefix
Timer2
T2
DS40002195A-page 194
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TMR2 - Timer2 Module
Notice:ꢀ References to module Timer2 apply to all the even numbered timers on this device. (Timer2,
Timer4, etc.)
DS40002195A-page 195
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TMR2 - Timer2 Module
21.10.1 TxTMR
Name:ꢀ
TxTMR
Address:ꢀ 0x28C
Timer Counter Register
Bit
7
6
5
4
3
2
1
0
TxTMR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TxTMR[7:0]ꢀTimerx Counter
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TMR2 - Timer2 Module
21.10.2 TxPR
Name:ꢀ
TxPR
Address:ꢀ 0x28D
Timer Period Register
Bit
7
6
5
4
3
2
1
0
TxPR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – TxPR[7:0]ꢀTimer Period Register
Value
0 - 255
Description
The timer restarts at ‘0’ when TxTMR reaches TxPR value
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TMR2 - Timer2 Module
21.10.3 TxCON
Name:ꢀ
TxCON
Address:ꢀ 0x28E
Timerx Control Register
Bit
7
ON
6
5
CKPS[2:0]
R/W
4
3
2
1
0
OUTPS[3:0]
Access
Reset
R/W/HC
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – ONꢀ Timer On(1)
Value
Description
1
Timer is on
0
Timer is off: all counters and state machines are reset
Bits 6:4 – CKPS[2:0]ꢀTimer Clock Prescale Select
Value
111
110
101
100
011
010
001
000
Description
1:128 Prescaler
1:64 Prescaler
1:32 Prescaler
1:16 Prescaler
1:8 Prescaler
1:4 Prescaler
1:2 Prescaler
1:1 Prescaler
Bits 3:0 – OUTPS[3:0]ꢀTimer Output Postscaler Select
Value
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
1:16 Postscaler
1:15 Postscaler
1:14 Postscaler
1:13 Postscaler
1:12 Postscaler
1:11 Postscaler
1:10 Postscaler
1:9 Postscaler
1:8 Postscaler
1:7 Postscaler
1:6 Postscaler
1:5 Postscaler
1:4 Postscaler
1:3 Postscaler
1:2 Postscaler
1:1 Postscaler
Note:ꢀ
1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 21-1.
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TMR2 - Timer2 Module
21.10.4 TxHLT
Name:ꢀ
TxHLT
Address:ꢀ 0x28F
Timer Hardware Limit Control Register
Bit
7
PSYNC
R/W
0
6
CPOL
R/W
0
5
CSYNC
R/W
0
4
3
2
MODE[4:0]
R/W
1
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
0
Bit 7 – PSYNCꢀ Timer Prescaler Synchronization Enable(1, 2)
Value
Description
1
Timer Prescaler Output is synchronized to FOSC/4
0
Timer Prescaler Output is not synchronized to FOSC/4
Bit 6 – CPOLꢀ Timer Clock Polarity Selection(3)
Value
Description
1
0
Falling edge of input clock clocks timer/prescaler
Rising edge of input clock clocks timer/prescaler
Bit 5 – CSYNCꢀ Timer Clock Synchronization Enable(4, 5)
Value
Description
1
0
ON bit is synchronized to timer clock input
ON bit is not synchronized to timer clock input
Bits 4:0 – MODE[4:0]ꢀ Timer Control Mode Selection(6, 7)
Value
Description
00000 to
See Table 21-1
11111
Note:ꢀ
1. Setting this bit ensures that reading TxTMR will return a valid data value.
2. When this bit is ‘1’, Timer cannot operate in Sleep mode.
3. CKPOL should not be changed while ON = 1.
4. Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5. When this bit is set then the timer operation will be delayed by two input clocks after the ON bit is set.
6. Unless otherwise indicated, all modes start upon ON = 1and stop upon ON = 0(stops occur without affecting
the value of TxTMR).
7. When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.
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TMR2 - Timer2 Module
21.10.5 TxCLKCON
Name:ꢀ
TxCLKCON
Address:ꢀ 0x290
Timer Clock Source Selection Register
Bit
7
6
5
4
3
2
1
CS[2:0]
R/W
0
0
Access
Reset
R/W
0
R/W
0
Bits 2:0 – CS[2:0]ꢀTimer Clock Source Selection
Table 21-3.ꢀClock Source Selection
CS
Clock Source
Reserved
111
110
101
100
011
010
001
000
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
FOSC/4
Pin selected by T2INPPS
DS40002195A-page 200
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TMR2 - Timer2 Module
21.10.6 TxRST
Name:ꢀ
TxRST
Address:ꢀ 0x291
Timer External Reset Signal Selection Register
Bit
7
6
5
4
3
2
1
0
RSEL[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 3:0 – RSEL[3:0]ꢀExternal Reset Source Selection
Table 21-4.ꢀExternal Reset Sources
RSEL
1111-0101
0100
Reset Source
Reserved
PWM4_OUT
PWM3_OUT
CCP2_OUT
CCP1_OUT
0011
0010
0001
0000
Pin selected by T2INPPS
DS40002195A-page 201
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TMR2 - Timer2 Module
21.11 Register Summary - Timer2
Address
Name
Bit Pos.
0x00
...
Reserved
0x028B
0x028C
0x028D
0x028E
0x028F
0x0290
0x0291
TxTMR
TxPR
7:0
7:0
7:0
7:0
7:0
7:0
T2TMR[7:0]
T2PR[7:0]
OUTPS[3:0]
MODE[4:0]
CS[2:0]
TxCON
TxHLT
ON
CKPS[2:0]
CSYNC
PSYNC
CPOL
TxCLKCON
TxRST
RSEL[3:0]
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CCP - Capture/Compare/PWM Module
22.
CCP - Capture/Compare/PWM Module
The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to
generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of
an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has
expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
The Capture and Compare functions are identical for all CCP modules.
Important:ꢀ In devices with more than one CCP module, it is very important to pay close attention to the
register names used. Throughout this section, the prefix “CCPx” is used as a generic replacement for
specific numbering. A number placed where the “x” is in the prefix is used to distinguish between separate
modules. For example, CCP1CON and CCP2CON control the same operational aspects of two completely
different CCP modules.
22.1
CCP Module Configuration
Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection
register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers:
CCPRxL (low byte) and CCPRxH (high byte).
22.1.1 CCP Modules and Timer Resources
The CCP modules utilize Timers 1 and 2 that vary with the selected mode. Various timers are available to the CCP
modules in Capture, Compare or PWM modes, as shown in the table below.
Table 22-1.ꢀCCP Mode - Timer Resources
CCP Mode
Capture
Compare
PWM
Timer Resource
Timer1
Timer2
All of the modules may be active at once and may share the same timer resource if they are configured to operate in
the same mode (Capture/Compare or PWM) at the same time.
22.1.2 Open-Drain Output Option
When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the output to communicate with external circuits without the need for
additional level shifters.
22.2
Capture Mode
Capture mode makes use of the 16-bit odd numbered timer resources (Timer1) . When an event occurs on the
capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event is
defined as one of the following and is configured by the MODE bits:
•
•
•
•
Every falling edge of CCPx input
Every rising edge of CCPx input
Every 4th rising edge of CCPx input
Every 16th rising edge of CCPx input
DS40002195A-page 203
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CCP - Capture/Compare/PWM Module
•
Every edge of CCPx input (rising or falling)
When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be
cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value
is overwritten by the new captured value. The following figure shows a simplified diagram of the capture operation.
Important:ꢀ If an event occurs during a 2-byte read, the high and low-byte data will be from different
events. It is recommended while reading the CCPRx register pair to either disable the module or read the
register pair twice for data integrity.
Figure 22-1.ꢀCapture Mode Operation Block Diagram
Rev. 10-000158E
3/11/2019
RxyPPS
CCPx
PPS
CTS
TRIS
CCPRx
16
Capture Trigger Sources
See CCPxCAP register
set CCPxIF
Prescaler
1,4,16
and
Edge Detect
16
CCPx
PPS
MODE
TMR1
CCPxPPS
22.2.1 Capture Sources
The capture source is selected with the CTS bits.
In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit.
Important:ꢀ If the CCPx pin is configured as an output, a write to the port can cause a capture condition.
22.2.2 Timer1 Mode for Capture
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture operation may not work.
See the “TMR1 - Timer1 Module with Gate Control” chapter for more information on configuring Timer1.
22.2.3 Software Interrupt Mode
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE
Interrupt Priority bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF
Interrupt Flag bit of the PIRx register following any change in Operating mode.
Important:ꢀ Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order
for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an external clock source.
DS40002195A-page 204
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CCP - Capture/Compare/PWM Module
22.2.4 CCP Prescaler
There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the
prescaler. The example below demonstrates the code to perform this function.
Example 22-1.ꢀChanging Between Capture Prescalers
BANKSEL CCP1CON
CLRF
CCP1CON
;Turn CCP module off
MOVLW
MOVWF
NEW_CAPT_PS
CCP1CON
;CCP ON and Prescaler select → W
;Load CCP1CON with this value
22.2.5 Capture During Sleep
Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1
module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep,
Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.
22.3
Compare Mode
The Compare mode function described in this section is available and identical for all CCP modules.
Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1). The 16-bit value of the CCPRx
register is constantly compared against the 16-bit value of the TMR1 register. When a match occurs, one of the
following events can occur:
•
•
•
•
•
•
Toggle the CCPx output and clear TMR1
Toggle the CCPx output without clearing TMR1
Set the CCPx output
Clear the CCPx output
Generate a Pulse output
Generate a Pulse output and clear TMR1
The action on the pin is based on the value of the MODE control bits.
All Compare modes can generate an interrupt. When MODE = 'b0001or 'b1011, the CCP resets the TMR1
register.
The following figure shows a simplified diagram of the compare operation.
DS40002195A-page 205
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CCP - Capture/Compare/PWM Module
Figure 22-2.ꢀCompare Mode Operation Block Diagram
MODE
Auto-conversion Trigger
CCPRx
CCPx
Q
S
R
PPS
Output
Logic
Comparator
TMR1
RxyPPS
TRIS
Set CCPxIF Interrupt Flag
22.3.1 CCPx Pin Configuration
The CCPx pin must be configured as an output in software by clearing the associated TRIS bit and defining the
appropriate output pin through the RxyPPS registers. See the “PPS - Peripheral Pin Select Module” chapter for
more details.
The CCP output can also be used as an input for other peripherals.
Important:ꢀ Clearing the CCPxCON register will force the CCPx compare output latch to the default low
level. This is not the PORT I/O data latch.
22.3.2 Timer1 Mode for Compare
In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare
operation may not work in Asynchronous Counter mode.
See the “TMR1 - Timer1 Module with Gate Control” chapter for more information on configuring Timer1.
Important:ꢀ Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order
for Compare mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an external clock source.
22.3.3 Compare During Sleep
Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the
timer is running. The device will wake on interrupt (if enabled).
22.4
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that controls power to a load by switching quickly between fully ON and
fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the
ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse
width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width,
also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies
less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF
time combined.
DS40002195A-page 206
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CCP - Capture/Compare/PWM Module
PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load.
The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where
0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle
corresponds to more power applied. The figure below shows a typical waveform of the PWM signal.
Figure 22-3.ꢀCCP PWM Output Signal
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRx
TMR2 = 0
22.4.1 Standard PWM Operation
The standard PWM function described in this section is available and identical for all CCP modules. It generates a
Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
•
•
•
•
Even numbered TxPR registers (T2PR)
Even numbered TxCON registers (T2CON)
16-bit CCPRx registers
CCPxCON registers
It is required to have FOSC/4 as the clock input to T2TMR for correct PWM operation. The following figure shows a
simplified block diagram of PWM operation.
DS40002195A-page 207
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CCP - Capture/Compare/PWM Module
Figure 22-4.ꢀSimplified PWM Block Diagram
Rev. 10-000 157C
2/20/201 9
Duty cycle registers
CCPRxH
CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
R
S
Q
Comparator
PPS
CCPx
RxyPPS
TRIS Control
TMR2 Module
TMR2
R
(1)
ERS logic
CCPx_pset
Comparator
PR2
Notes:
1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.
Important:ꢀ The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin.
22.4.2 Timer2 Timer Resource
The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period.
22.4.3 PWM Period
The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in
the equation below.
Equation 22-1.ꢀPWM Period
ꢀꢁꢂꢀꢃꢄꢅꢆꢇ = ꢈ2ꢀꢉ + 1 • 4 • ꢈ
• ꢈꢂꢉ2Prꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ
ꢊꢋꢌ
where TOSC = 1/FOSC
When T2TMR is equal to T2PR, the following three events occur on the next increment event:
•
•
•
T2TMR is cleared
The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)
The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer.
DS40002195A-page 208
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CCP - Capture/Compare/PWM Module
Important:ꢀ The Timer postscaler (see “Timer2 Interrupt”) is not used in the determination of the PWM
frequency.
22.4.4 PWM Duty Cycle
The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-bit value is
determined by the FMT bit (see Figure 22-5). The CCPRx register can be written to at any time. However, the duty
cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR.
The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.
Figure 22-5.ꢀPWM 10-Bit Alignment
CCPRxH
CCPRxL
FMT = 0
7
6
5
4
3
2
1
7
0
6
7
6
5
4
3
2
1
7
0
6
CCPRxH
CCPRxL
FMT = 1
5
4
3
2
1
0
5 4 3 2 1 0
10-bit Duty Cycle
9
8
7
6
5
4
3
2
1
0
Equation 22-2.ꢀPulse Width
ꢀꢒꢐꢍꢃ ꢁꢅꢇꢓℎ = ꢌꢌꢀꢉꢔꢕ:ꢌꢌꢀꢉꢔꢖ ꢄꢃꢗꢅꢍꢓꢃꢄ ꢘꢏꢐꢒꢃ • ꢈ
•
ꢈꢂꢉ2 Prꢃꢍꢎꢏꢐꢃ ꢑꢏꢐꢒꢃ
ꢊꢋꢌ
Equation 22-3.ꢀDuty Cycle
ꢌꢌꢀꢉꢔꢕ:ꢌꢌꢀꢉꢔꢖ ꢄꢃꢗꢅꢍꢓꢃꢄ ꢘꢏꢐꢒꢃ
ꢙꢒꢓꢚꢌꢚꢎꢐꢃꢉꢏꢓꢅꢆ =
4 ꢈ2ꢀꢉ + 1
The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless
PWM operation.
The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the
prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 22-4).
22.4.5 PWM Resolution
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will
result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when T2PR is 0xFF. The resolution is a function of the T2PR register value
as shown below.
Equation 22-4.ꢀPWM Resolution
log 4 ꢈ2ꢀꢉ + 1
Reꢍꢆꢐꢒꢓꢅꢆꢛ =
ꢜꢅꢓꢍ
log 2
Important:ꢀ If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain
unchanged.
DS40002195A-page 209
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CCP - Capture/Compare/PWM Module
Table 22-2.ꢀExample PWM Frequencies and Resolutions (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
16
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
4
1
1
0x3F
8
1
0x1F
7
1
T2PR Value
0xFF
10
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
Table 22-3.ꢀExample PWM Frequencies and Resolutions (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
T2PR Value
Maximum Resolution (bits)
22.4.6 Operation in Sleep Mode
In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is
driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous
state.
22.4.7 Changes in System Clock Frequency
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will
result in changes to the PWM frequency. See the “OSC - Oscillator Module” chapter for additional details.
22.4.8 Effects of Reset
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
22.4.9 Setup for PWM Operation
The following steps illustrate how to configure the CCP module for standard PWM operation:
1. Select the desired output pin with the RxyPPS control to select CCPx as the source. Disable the selected pin
output driver by setting the associated TRIS bit. The output will be enabled later at the end of the PWM setup.
2. Load the timer period register T2PR with the PWM period value.
3. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values.
4. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register
alignment.
5. Configure and start the Timer:
– Clear the TMR2IF Interrupt Flag bit of the PIRx register. See Note below.
– Select the timer clock source to be as FOSC/4. This is required for correct operation of the PWM module.
– Configure the CKPS bits of the T2CON register with the desired Timer prescale value.
– Enable the Timer by setting the ON bit of the T2CON register.
6. Enable the PWM output:
– Wait until the Timer overflows and the TMR2IF bit of the PIRx register is set. See Note below.
– Enable the CCPx pin output driver by clearing the associated TRIS bit.
Important:ꢀ In order to send a complete duty cycle and period on the first PWM output, the
above steps must be included in the setup sequence. If it is not critical to start with a complete
PWM signal on the first output, then step 6 may be ignored.
DS40002195A-page 210
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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CCP - Capture/Compare/PWM Module
22.5
Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 22-4.ꢀCCP Long bit name prefixes
Peripheral
CCP1
Bit Name Prefix
CCP1
CCP2
CCP2
DS40002195A-page 211
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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CCP - Capture/Compare/PWM Module
22.5.1 CCPxCON
Name:ꢀ
CCPxCON
Address:ꢀ 0x30E,0x312
CCP Control Register
Bit
7
EN
R/W
0
6
5
OUT
R
4
3
2
1
0
FMT
R/W
0
MODE[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
x
Bit 7 – ENꢀCCP Module Enable
Value
Description
1
0
CCP is enabled
CCP is disabled
Bit 5 – OUTꢀCCP Output Data (read-only)
Bit 4 – FMTꢀCCPW (pulse-width) Value Alignment
Value
Condition
Description
Not used
Not used
Left-aligned format
Right-aligned format
x
x
1
0
Capture mode
Compare mode
PWM mode
PWM mode
Bits 3:0 – MODE[3:0]ꢀCCP Mode Select
Table 22-5.ꢀCCPx Mode Select
MODE Value
Operating Mode
Operation
Set CCPxIF
11xx
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
PWM
PWM operation
Pulse output; clear TMR1(2)
Pulse output
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Compare
Capture
Clear output(1)
Set output(1)
Every 16th rising edge of CCPx input
Every 4th rising edge of CCPx input
Every rising edge of CCPx input
Every falling edge of CCPx input
Every edge of CCPx input
Toggle output
Toggle output; clear TMR1(2)
Compare
Disabled
Note:ꢀ
1. The set and clear operations of the Compare mode are reset by setting MODE = 'b0000or EN = 0.
2. When MODE = 'b0001or 'b1011, then the timer associated with the CCP module is cleared. TMR1 is the
default selection for the CCP module, so it is used for indication purposes only.
DS40002195A-page 212
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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CCP - Capture/Compare/PWM Module
22.5.2 CCPxCAP
Name:ꢀ
CCPxCAP
Address:ꢀ 0x30F,0x313
Capture Trigger Input Selection Register
Bit
7
6
5
4
3
2
1
0
CTS[1:0]
Access
Reset
R/W
0
R/W
0
Bits 1:0 – CTS[1:0]ꢀCapture Trigger Input Selection
Table 22-6.ꢀCapture Trigger Sources
CTS Value
11-10
01
Source
Reserved
IOC Interrupt
00
Pin selected by CCPxPPS
DS40002195A-page 213
Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
22.5.3 CCPRx
Name:ꢀ
CCPRx
Address:ꢀ 0x30C,0x310
Capture/Compare/Pulse Width Register
Bit
15
14
13
12
11
10
9
8
CCPR[15:8]
CCPR[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bits 15:0 – CCPR[15:0]ꢀCapture/Compare/Pulse Width
Reset States: POR/BOR = xxxxxxxxxxxxxxxx
All other Resets = uuuuuuuuuuuuuuuu
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
When MODE = Capture or Compare
– CCPRxH: Accesses the high byte CCPR[15:8]
– CCPRxL: Accesses the low byte CCPR[7:0]
When MODE = PWM and FMT = 0
•
– CCPRx[15:10]: Not used
– CCPRxH[1:0]: Accesses the two Most Significant bits CCPR[9:8]
– CCPRxL: Accesses the eight Least Significant bits CCPR[7:0]
When MODE = PWM and FMT = 1
•
– CCPRxH: Accesses the eight Most Significant bits CCPR[9:2]
– CCPRxL[7:6]: Accesses the two Least Significant bits CCPR[1:0]
– CCPRx[5:0]: Not used
DS40002195A-page 214
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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CCP - Capture/Compare/PWM Module
22.6
Register Summary - CCP Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x030B
7:0
15:8
7:0
CCPR[7:0]
0x030C
CCPR1
CCPR[15:8]
0x030E
0x030F
CCP1CON
CCP1CAP
EN
EN
OUT
OUT
FMT
MODE[3:0]
MODE[3:0]
7:0
CTS[1:0]
CTS[1:0]
7:0
CCPR[7:0]
CCPR[15:8]
FMT
0x0310
CCPR2
15:8
7:0
0x0312
0x0313
CCP2CON
CCP2CAP
7:0
DS40002195A-page 215
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
PWM - Pulse-Width Modulation
23.
PWM - Pulse-Width Modulation
The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution
that are configured by the following registers:
•
•
•
•
T2PR
T2CON
PWMxDC
PWMxCON
Important:ꢀ The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin.
Each PWM module uses the same timer source, Timer2, to control each module.
Figure 23-1 shows a simplified block diagram of PWM operation.
Figure 23-2 shows a typical waveform of the PWM signal.
Figure 23-1.ꢀSimplified PWM Block Diagram
PWMxDCL[7:6]
Duty cycle registers
PWMxDCH
PWMx_out
To Peripherals
10-bit Latch
(Not visible to user)
R
S
Q
Q
Comparator
0
1
PPS
PWMx
TMR2 Module
RxyPPS
TRIS Control
R
POL
(1)
T2TMR
Comparator
T2PR
T2_match
Note:ꢀ
1. 8-bit timer is concatenated with two bits generated by FOSC or two bits of the internal prescaler to create 10-bit
time base.
DS40002195A-page 216
Preliminary Datasheet
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PWM - Pulse-Width Modulation
Figure 23-2.ꢀPWM Output
Period
Pulse Width
T2TMR = T2PR
T2TMR reloaded with 0
T2TMR = Duty Cycle =
PWMxDCH[7:0]:PWMxDCL[7:6]
T2TMR = T2PR
T2TMR reloaded with 0
For a step-by-step procedure on how to set up this module for PWM operation, refer to “Setup for PWM Operation
using PWMx Output Pins”.
23.1
Fundamental Operation
The PWM module produces a 10-bit resolution output. The timer selection for PWMx is TMR2. T2TMR and T2PR set
the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to
all PWM modules, whereas the duty cycle is independently controlled.
Important:ꢀ The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler
could be used to have a servo update rate at a different frequency than the PWM output.
All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when T2TMR is
equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL[7:6] (2 LSb) registers. When
the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle).
Important:ꢀ The PWMxDCH and PWMxDCL registers are double-buffered. The buffers are updated when
T2TMR matches T2PR. Care should be taken to update both registers before the timer match occurs.
23.2
23.3
PWM Output Polarity
The output polarity is inverted by setting the POL bit.
PWM Period
The PWM period is specified by the T2PR register The PWM period can be calculated using the formula of Equation
23-1. It is required to have FOSC/4 as the selected clock input to the timer for correct PWM operation.
Equation 23-1.ꢀPWM Period
ꢀꢁꢂꢀꢃꢄꢅꢆꢇ = ꢈ2ꢀꢉ + 1 • 4 • ꢈꢆꢍꢎ • ꢈꢂꢉ2 ꢀꢄꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ
Note:ꢀ TOSC = 1/FOSC
When T2TMR is equal to T2PR, the following three events occur on the next increment cycle:
•
T2TMR is cleared
DS40002195A-page 217
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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PWM - Pulse-Width Modulation
•
•
The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.)
The PWMxDCH and PWMxDCL register values are latched into the buffers.
Important:ꢀ The Timer2 postscaler has no effect on the PWM operation.
23.4
PWM Duty Cycle
The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The
PWMxDCH register contains the eight MSbs and the PWMxDCL[7:6], the two LSbs. The PWMxDCH and PWMxDCL
registers can be written to at any time.
The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.
Equation 23-2.ꢀPulse Width
ꢀꢒꢐꢍꢃꢁꢅꢇꢓℎ = ꢀꢁꢂꢔꢙꢌꢕ:ꢀꢁꢂꢔꢙꢌꢖ 7:6 • ꢈꢆꢍꢎ • ꢈꢂꢉ2Prꢃꢍꢎꢏꢐꢃꢑꢏꢐꢒꢃ
Note:ꢀ TOSC = 1/FOSC
Equation 23-3.ꢀDuty Cycle Ratio
ꢀꢁꢂꢔꢙꢌꢕ:ꢀꢁꢂꢔꢙꢌꢖ 7:6
ꢙꢒꢓꢚꢌꢚꢎꢐꢃꢉꢏꢓꢅꢆ =
4 ꢈ2ꢀꢉ + 1
The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2
prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.
23.5
PWM Resolution
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will
result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value
as shown below.
Equation 23-4.ꢀPWM Resolution
log 4 ꢈ2ꢀꢉ + 1
ꢉꢃꢍꢆꢐꢒꢓꢅꢆꢛ =
ꢜꢅꢓꢍ
log 2
Important:ꢀ If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain
unchanged.
Table 23-1.ꢀExample PWM Frequencies and Resolutions (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
0.31 kHz
64
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
4
1
1
0x3F
8
1
0x1F
7
1
T2PR Value
0xFF
10
0xFF
10
0xFF
10
0x17
6.6
Maximum Resolution (bits)
DS40002195A-page 218
Preliminary Datasheet
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PWM - Pulse-Width Modulation
Table 23-2.ꢀExample PWM Frequencies and Resolutions (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
0.31 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
0x65
8
4
0x65
8
1
0x65
8
1
0x19
6
1
0x0C
5
1
0x09
5
T2PR Value
Maximum Resolution (bits)
23.6
23.7
Operation in Sleep Mode
In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the PWMx pin is
driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from its previous
state.
Changes in System Clock Frequency
The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency
will result in changes to the PWM frequency.
23.8
23.9
Effects of Reset
Any Reset will force all ports to Input mode and the PWM registers to their Reset states.
Setup for PWM Operation using PWMx Output Pins
The following steps should be taken when configuring the module for PWM operation using the PWMx pins:
1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the T2PR register with the PWM period value.
4. Load the PWMxDCH register and bits [7:6] of the PWMxDCL register with the PWM duty cycle value.
5. Configure and start Timer2:
– Clear the TMR2IF Interrupt Flag bit of the PIRx register.(1)
– Select the timer clock source to be as FOSC/4 using the T2CLKCON register. This is required for correct
operation of the PWM module.
– Configure the CKPS bits of the T2CON register with the Timer2 prescale value.
– Enable Timer2 by setting the ON bit of the T2CON register.
6. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(2)
7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS
control bits.
8. Configure the PWM module by loading the PWMxCON register with the appropriate values.
Note:ꢀ
1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed
in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4.
2. For operation with other peripherals only, disable PWMx pin outputs.
23.9.1 PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing
the associated TRIS bits.
DS40002195A-page 219
Preliminary Datasheet
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PWM - Pulse-Width Modulation
23.10 Setup for PWM Operation to Other Device Peripherals
The following steps should be taken when configuring the module for PWM operation to be used by other device
peripherals:
1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s).
2. Clear the PWMxCON register.
3. Load the T2PR register with the PWM period value.
4. Load the PWMxDCH register and bits [7:6] of the PWMxDCL register with the PWM duty cycle value.
5. Configure and start Timer2:
– Clear the TMR2IF Interrupt Flag bit of the PIRx register.(1)
– Select the timer clock source to be as FOSC/4 using the T2CLKCON register. This is required for correct
operation of the PWM module.
– Configure the CKPS bits of the T2CON register with the Timer2 prescale value.
– Enable Timer2 by setting the ON bit of the T2CON register.
6. Wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(1)
7. Configure the PWM module by loading the PWMxCON register with the appropriate values.
Note:ꢀ
1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included
in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then Step 6
may be ignored.
23.11 Register Definitions: PWM Control
Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the "Long Bit Names Section"
for more information.
Table 23-3.ꢀPWM Bit Name Prefixes
Peripheral
PWM3
Bit Name Prefix
PWM3
PWM4
PWM4
DS40002195A-page 220
Preliminary Datasheet
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PWM - Pulse-Width Modulation
23.11.1 PWMxCON
Name:ꢀ
PWMxCON
Address:ꢀ 0x316,0x31A
PWM Control Register
Bit
7
EN
R/W
0
6
5
OUT
R
4
3
2
1
0
POL
R/W
0
Access
Reset
0
Bit 7 – ENꢀPWM Module Enable bit
Value
Description
1
0
PWM module is enabled
PWM module is disabled
Bit 5 – OUTꢀPWM Module Output Level
Indicates PWM module output level when bit is read
Bit 4 – POLꢀPWM Output Polarity Select bit
Value
Description
1
0
PWM output is inverted
PWM output is normal
DS40002195A-page 221
Preliminary Datasheet
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PWM - Pulse-Width Modulation
23.11.2 PWMxDC
Name:ꢀ
PWMxDC
Address:ꢀ 0x314,0x318
PWM Duty Cycle Register
Bit
15
14
13
12
11
10
9
8
DCH[7:0]
Access
Reset
x
x
x
x
x
x
x
x
Bit
7
6
5
4
3
2
1
0
DCL[1:0]
Access
Reset
x
x
Bits 15:8 – DCH[7:0]ꢀPWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle.
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Bits 7:6 – DCL[1:0]ꢀPWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle.
Reset States: POR/BOR = xx
All Other Resets = uu
DS40002195A-page 222
Preliminary Datasheet
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PWM - Pulse-Width Modulation
23.12 Register Summary - PWM
Address
Name
Bit Pos.
0x00
...
Reserved
0x0313
7:0
15:8
7:0
DCL[1:0]
DCL[1:0]
0x0314
PWM3DC
DCH[7:0]
POL
0x0316
0x0317
PWM3CON
Reserved
EN
EN
OUT
OUT
7:0
15:8
7:0
0x0318
0x031A
PWM4DC
DCH[7:0]
POL
PWM4CON
DS40002195A-page 223
Preliminary Datasheet
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EUSART - Enhanced Universal Synchronous Asyn...
24.
EUSART - Enhanced Universal Synchronous Asynchronous Receiver
Transmitter
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O
communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform
an input or output serial data transfer independent of device program execution. The EUSART, also known as a
Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex
synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals
and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices,
such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not
have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous
device.
The EUSART module includes the following capabilities:
•
•
•
•
•
•
•
•
•
•
•
Full-Duplex Asynchronous Transmit and Receive
Two-Character Input Buffer
One-Character Output Buffer
Programmable 8-Bit or 9-Bit Character Length
Address Detection in 9-bit Mode
Input Buffer Overrun Error Detection
Received Character Framing Error Detection
Half-Duplex Synchronous Master
Half-Duplex Synchronous Slave
Programmable Clock Polarity in Synchronous Modes
Sleep Operation
The EUSART module implements the following additional features, making it ideally suited for use in Local
Interconnect Network (LIN) bus systems:
•
•
•
Automatic detection and calibration of the baud rate
Wake-up on Break reception
13-bit Break character transmit
Block diagrams of the EUSART transmitter and receiver are shown in Figure 24-1 and Figure 24-2.
The operation of the EUSART module consists of six registers:
•
•
•
•
•
•
Transmit Status and Control (TXxSTA)
Receive Status and Control (RCxSTA)
Baud Rate Control (BAUDxCON)
Baud Rate Value (SPxBRG)
Receive Data Register (RCxREG)
Transmit Data Register (TXxREG)
The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx,
and DTx output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output
in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating
in Synchronous mode. The EUSART control logic will control the data direction drivers automatically.
DS40002195A-page 224
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EUSART - Enhanced Universal Synchronous Asyn...
Figure 24-1.ꢀEUSART Transmit Block Diagram
Rev. 10-000 113C
2/15/201 7
Data bus
TXIE
TXIF
8
Interrupt
TXREG register
SYNC
CSRC
8
RxyPPS(1)
RXx/DTx Pin
TXEN
CKx Pin
MSb
(8)
LSb
0
Pin Buffer
and Control
PPS
1
0
PPS
Transmit Shift Register (TSR)
CKPPS(2)
TX_out
TRMT
Baud Rate Generator
BRG16
FOSC
÷ n
TX9
n
TXx/CKx Pin
TX9D
0
1
+ 1
Multiplier
SYNC
x4
x16
x64
PPS
1
x
1
1
0
0
0
1
0
0
0
RxyPPS(2)
BRGH
x
x
1
0
SPBRGH SPBRGL
SYNC
CSRC
BRG16
Note 1: In Synchronous mode, the DT output and RX input PPS
selections should enable the same pin.
2: In Master Synchronous mode the TX output and CK input
PPS selections should enable the same pin.
DS40002195A-page 225
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EUSART - Enhanced Universal Synchronous Asyn...
Figure 24-2.ꢀEUSART Receive Block Diagram
Rev. 10-000 114B
2/15/201 7
CREN
OERR
RCIDL
SPEN
RXPPS(1)
PPS
RSR Register
MSb
LSb
RXx/DTx pin
Pin Buffer
and Control
Data
Recovery
Stop (8)
7
1
0
Start
SYNC
CSRC
RX9
PPS
1
0
CKx Pin
CKPPS(2)
Baud Rate Generator
BRG16
FIFO
FOSC
÷ n
FERR
RX9D
RCREG Register
8
n
Data Bus
+ 1
Multiplier
x4
x16
x64
SYNC
BRGH
BRG16
1
x
x
x
1
1
0
1
0
0
0
1
0
0
0
RCxIF
RCxIE
Interrupt
SPBRGH SPBRGL
Note 1: In Synchronous mode, the DT output and RX input PPS
selections should enable the same pin.
2: In Master Synchronous mode the TX output and CK input
PPS selections should enable the same pin.
24.1
EUSART Asynchronous Mode
The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented
with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data
bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit
without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state.
Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by
one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data
format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud
Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 24-2 for
examples of baud rate configurations.
The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally
independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be
implemented in software and stored as the ninth data bit.
24.1.1 EUSART Asynchronous Transmitter
Figure 24-1 is a simplified representation of the transmitter. The heart of the transmitter is the serial Transmit Shift
Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which
is the TXxREG register.
24.1.1.1 Enabling the Transmitter
The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits:
•
•
The Transmit Enable (TXEN) bit is set to ‘1’ to enable the transmitter circuitry of the EUSART
The EUSART Mode Select (SYNC) bit is set to ‘0’ to configure the EUSART for asynchronous operation
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•
The Serial Port Enable (SPEN) bit is set to ‘1’ to enable the EUSART interface and to enable automatically the
output drivers for the RxyPPS selected as the TXx/CKx output
All other EUSART control bits are assumed to be in their default state.
If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the
corresponding ANSEL bit.
Important:ꢀ The TXxIF Transmitter Interrupt Flag in the PIRx register is set when the TXEN enable bit is
set and the Transmit Shift register (TSR) is Idle.
24.1.1.2 Transmitting Data
A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous
character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR
register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until
the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred
to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and
Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG.
24.1.1.3 Transmit Data Polarity
The polarity of the transmit data can be controlled with the Clock/Transmit Polarity Select (SCKP) bit. The default
state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the
transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous
mode only. In Synchronous mode, the SCKP bit has a different function. See the “Clock Polarity” section for more
details.
24.1.1.4 Transmit Interrupt Flag
The EUSART Transmit Interrupt Flag (TXxIF) bit of the PIRx register is set whenever the EUSART transmitter is
enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only cleared
when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The
TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle
following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The
TXxIF bit is read-only, it cannot be set or cleared by software.
The TXxIF interrupt can be enabled by setting the EUSART Transmit Interrupt Enable (TXxIE) bit of the PIEx register.
However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit.
To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE
interrupt enable bit upon writing the last character of the transmission to the TXxREG.
24.1.1.5 TSR Status
The Transmit Shift Register Status (TRMT) bit indicates the status of the TSR register. This is a read-only bit. The
TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register
from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt
logic is tied to this bit, so the user needs to poll this bit to determine the TSR status.
Important:ꢀ The TSR register is not mapped in data memory, so it is not available to the user.
24.1.1.6 Transmitting 9-Bit Characters
The EUSART supports 9-bit character transmissions. When the 9-Bit Transmit Enable (TX9) bit is set, the EUSART
will shift nine bits out for each character transmitted. The TX9D bit is the ninth, and Most Significant data bit. When
transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the
TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written.
DS40002195A-page 227
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A special 9-bit Address mode is available for use with multiple receivers. See the “Address Detection” section for
more information on the Address mode.
24.1.1.7 Asynchronous Transmission Setup
1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud
rate (see section “EUSART Baud Rate Generator (BRG)”).
2. Select the transmit output pin by writing the appropriate value to the RxyPPS register.
3. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit.
4. If 9-bit transmission is desired, set the TX9 control bit. That will indicate that the eight Least Significant data
bits are an address when the receiver is set for address detection.
5. Set SCKP bit if inverted transmit is desired.
6. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set.
7. If interrupts are desired, set the TXxIE interrupt enable bit of the PIEx register.
8. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set.
9. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit.
10. Load 8-bit data into the TXxREG register. This will start the transmission.
Figure 24-3.ꢀAsynchronous Transmission
Rev. 10-000 115A
2/7/201 7
Word 1
Write to TXxREG
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXxIF bit
(Transmit Buffer
Reg Empty Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg Empty Flag)
Figure 24-4.ꢀAsynchronous Transmission (Back-to-Back)
Rev. 10-000 116A
2/7/201 7
Word 1
Word 2
Write to TXxREG
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
Start bit
bit 0
Word 2
TXxIF bit
(Transmit Buffer
Reg Empty Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg Empty Flag)
24.1.2 EUSART Asynchronous Receiver
The Asynchronous mode is typically used in RS-232 systems. A simplified representation of the receiver is shown in
Figure 24-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is
actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR)
operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately
transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete
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characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and
RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register.
24.1.2.1 Enabling the Receiver
The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits:
•
•
•
The Continuous Receive Enable (CREN) bit is set to ‘1’ to enables the receiver circuitry of the EUSART
The EUSART Mode Select (SYNC) bit is set to ‘0’ to configure the EUSART for asynchronous operation
The Serial Port Enable (SPEN) bit is set to ‘1’ to enable the EUSART interface
All other EUSART control bits are assumed to be in their default state.
The user must set the RXxPPS register to select the RXx/DTx I/O pin and set the corresponding TRIS bit to configure
the pin as an input.
Important:ꢀ If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for
the receiver to function.
24.1.2.2 Receiving Data
The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also
known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit
and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception,
without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification
succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a
majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been
sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is
always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this
character, otherwise the framing error is cleared for this character. See the “Receive Framing Error” section for more
information on framing errors.
Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the
EUSART receive FIFO and the EUSART Receive Interrupt Flag (RCxIF) bit of the PIRx register is set. The top
character in the FIFO is transferred out of the FIFO by reading the RCxREG register.
Important:ꢀ If the receive FIFO is overrun, no additional characters will be received until the overrun
condition is cleared. See the “Receive Overrrun Error” section for more information.
24.1.2.3 Receive Interrupts
The EUSART Receive Interrupt Flag (RCxIF) bit of the PIRx register is set whenever the EUSART receiver is
enabled and there is an unread character in the receive FIFO. The RCxIF Interrupt Flag bit is read-only, it cannot be
set or cleared by software.
RCxIF interrupts are enabled by setting all of the following bits:
•
•
•
RCxIE, Interrupt Enable bit of the PIEx register
PEIE, Peripheral Interrupt Enable bit of the INTCON register
GIE, Global Interrupt Enable bit of the INTCON register
The RCxIF Interrupt Flag bit will be set when there is an unread character in the FIFO, regardless of the state of
interrupt enable bits.
24.1.2.4 Receive Framing Error
Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that
a Stop bit was not seen at the expected time. The framing error status is accessed via the Framing Error (FERR) bit.
The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be
read before reading the RCxREG.
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The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR =
1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next
character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error.
The FERR bit can be forced clear by clearing the SPEN bit, which resets the EUSART. Clearing the CREN bit does
not affect the FERR bit. A framing error by itself does not generate an interrupt.
Important:ꢀ If all receive characters in the receive FIFO have framing errors, repeated reads of the
RCxREG will not clear the FERR bit.
24.1.2.5 Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety,
is received before the FIFO is accessed. When this happens the Overrun Error (OERR) bit is set. The characters
already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The
error must be cleared by either clearing the CREN bit or by resetting the EUSART by clearing the SPEN bit.
24.1.2.6 Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When the 9-Bit Receive Enable (RX9) bit is set, the EUSART will
shift nine bits into the RSR for each character received. The RX9D bit is the ninth and Most Significant data bit of the
top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit
must be read before reading the eight Least Significant bits from the RCxREG.
24.1.2.7 Address Detection
A special Address Detection mode is available for use when multiple receivers share the same transmission line,
such as in RS-485 systems. Address detection is enabled by setting the Address Detect Enable (ADDEN) bit.
Address detection requires 9-bit character reception. When address detection is enabled, only characters with the
ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other
characters will be ignored.
Upon receiving an address character, user software determines if the address matches its own. Upon address match,
user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user
software detects the end of the message, determined by the message protocol used, software places the receiver
back into the Address Detection mode by setting the ADDEN bit.
24.1.2.8 Asynchronous Reception Setup
1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud
rate (see the “EUSART Baud Rate Generator (BRG)” section).
2. Set the RXxPPS register to select the RXx/DTx input pin.
3. Clear the ANSEL bit for the RXx pin (if applicable).
4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation.
5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
6. If 9-bit reception is desired, set the RX9 bit.
7. Enable reception by setting the CREN bit.
8. The RCxIF Interrupt Flag bit will be set when a character is transferred from the RSR to the receive buffer. An
interrupt will be generated if the RCxIE interrupt enable bit was also set.
9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit.
10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register.
11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
24.1.2.9 9-Bit Address Detection Mode Setup
This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect
Enable follow these steps:
1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud
rate (see the “EUSART Baud Rate Generator (BRG)” section).
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2. Set the RXxPPS register to select the RXx input pin.
3. Clear the ANSEL bit for the RXx pin (if applicable).
4. Enable the serial port by setting the SPEN bit. The SYNC bit must be cleared for asynchronous operation.
5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
6. Enable 9-bit reception by setting the RX9 bit.
7. Enable address detection by setting the ADDEN bit.
8. Enable reception by setting the CREN bit.
9. The RCxIF Interrupt Flag bit will be set when a character with the ninth bit set is transferred from the RSR to
the receive buffer. An interrupt will be generated if the RCxIE Interrupt Enable bit is also set.
10. Read the RCxSTA register to get the error flags. The ninth data bit will always be set.
11. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register.
Software determines if this is the device’s address.
12. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit.
13. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and
generate interrupts.
Figure 24-5.ꢀAsynchronous Reception
Rev. 10-000 117A
2/8/201 7
Start
bit
Start
bit
Start
bit
Stop
bit
Stop
bit
Stop
bit
RXx/DTx
pin
bit 0
Word 1
bit 7/8
bit 0
Word 2
bit 7/8
bit 0
Word 3
bit 7/8
Rcv Shift Reg
Rcv Buffer Reg
Word 1
Word 2
RCxREG
RCxREG
RCIDL
Read
RCxREG
RCxIF
(Interrupt flag)
OERR Flag
CREN
(software clear)
Note: This timing diagram shows three bytes appearing on the RXx input. The OERR flag is set because the
RCxREG is not read before the third word is received.
24.2
Clock Accuracy with Asynchronous Operation
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as
VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to
adjust the baud rate clock, but both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the
OSCTUNE register allows for fine resolution changes to the system clock source.
The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud
Detect feature (see “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate
Generator to compensate for a gradual change in the peripheral clock frequency.
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24.3
EUSART Baud Rate Generator (BRG)
The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous
and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit selects 16-
bit mode.
The SPxBRGH:SPxBRGL register pair determines the period of the free-running baud rate timer. In Asynchronous
mode the multiplier of the baud rate period is determined by both the BRGH and the BRG16 bits. In Synchronous
mode, the BRGH bit is ignored.
Table 24-1 contains the formulas for determining the baud rate. Equation 24-1 provides a sample calculation for
determining the baud rate and baud rate error.
Typical baud rates and error values for various asynchronous modes have been computed and are shown in Table
24-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the
baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH
bit is used to achieve very high baud rates.
Writing a new value to the SPxBRGH:SPxBRGL register pair causes the BRG timer to be reset (or cleared). This
ensures that the BRG does not wait for a timer overflow before outputting the new baud rate.
If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid
this problem, check the status of the Receive Idle Flag (RCIDL) bit to make sure that the receive operation is idle
before changing the system clock.
Equation 24-1.ꢀCalculating Baud Rate Error
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
ꢞ
ꢊꢋꢌ
ꢙꢃꢍꢅꢄꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ =
64 × ꢋꢀꢔꢝꢉꢟ + 1
Solving for SPxBRG:
ꢞ
ꢊꢋꢌ
ꢋꢀꢔꢝꢉꢟ =
− 1
64 × ꢙꢃꢍꢅꢄꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ
16000000
− 1
ꢋꢀꢔꢝꢉꢟ =
64 × 9600
ꢋꢀꢔꢝꢉꢟ = 25.042 ≃ 25
ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ =
16000000
64 × 25 + 1
ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ = 9615
ꢌꢏꢐꢎꢒꢐꢏꢓꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ − ꢙꢃꢍꢅꢄꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ
ꢠꢄꢄꢆꢄ =
ꢠꢄꢄꢆꢄ =
ꢙꢃꢍꢅꢄꢃꢇꢝꢏꢒꢇꢄꢏꢓꢃ
9615 − 9600
9600
ꢠꢄꢄꢆꢄ = 0.16 %
Table 24-1.ꢀBaud Rate Formulas
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
FOSC/[64 (n+1)]
SYNC
BRG16
BRGH
0
0
0
0
0
1
0
1
0
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
FOSC/[16 (n+1)]
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...........continued
Configuration Bits
BRG/EUSART Mode
Baud Rate Formula
SYNC
BRG16
BRGH
0
1
1
1
0
1
1
x
x
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[4 (n+1)]
Note: x = Don’t care, n = value of SPxBRGH:SPxBRGL register pair.
Table 24-2.ꢀSample Baud Rates for Asynchronous Modes
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 20.000 MHz FOSC = 18.432 MHz
SPBRG Actual SPBRG Actual
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
Actual
%
%
%
SPBRG Actual
%
SPBRG
value
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
239
119
29
27
14
7
—
—
—
143
71
17
16
8
1200
2400
9600
1221 1.73
2404 0.16
9470 -1.36
10417 0.00
19.53k 1.73
255
129
32
1200 0.00
2400 0.00
9600 0.00
10286 -1.26
19.20k 0.00
57.60k 0.00
1200 0.00
2400 0.00
9600 0.00
10165 -2.42
19.20k 0.00
57.60k 0.00
2404 0.16
9615 0.16
207
51
47
25
3
10417 10417 0.00
19.2k 19.23k 0.16
57.6k 55.55k -3.55
29
15
—
—
—
—
—
2
115.2k
—
—
—
—
—
—
—
—
—
—
SYNC = 0, BRGH = 0, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
SPBRG Actual SPBRG Actual SPBRG Actual
FOSC = 8.000 MHz
Actual
FOSC = 1.000 MHz
BAUD
RATE
%
%
%
%
SPBRG
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
value
(decimal)
(decimal)
(decimal)
(decimal)
300
—
—
—
103
51
12
11
300
0.16
207
51
25
—
5
300
0.00
191
47
23
5
300
0.16
51
12
—
—
—
—
—
—
1200
2400
9600
1202 0.16
2404 0.16
9615 0.16
1202 0.16
2404 0.16
1200 0.00
2400 0.00
9600 0.00
1202 0.16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10417 10417 0.00
10417 0.00
—
—
—
2
19.2k
57.6k
115.2k
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
19.20k 0.00
57.60k 0.00
—
0
—
—
—
—
DS40002195A-page 233
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EUSART - Enhanced Universal Synchronous Asyn...
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 32.000 MHz
FOSC = 20.000 MHz
FOSC = 18.432 MHz
FOSC = 11.0592 MHz
BAUD
RATE
Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG
value
Rate
Error
value
Rate
Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
71
65
35
11
5
1200
2400
9600
—
—
—
—
—
—
—
9615
0.16
207
191
103
34
9615
0.16
129
119
64
9600 0.00
10378 -0.37
19.20k 0.00
57.60k 0.00
115.2k 0.00
119
110
59
19
9
9600 0.00
10473 0.53
19.20k 0.00
57.60k 0.00
115.2k 0.00
10417 10417 0.00
19.2k 19.23k 0.16
57.6k 57.14k -0.79
115.2k 117.64k 2.12
10417 0.00
19.23k 0.16
56.82k -1.36
113.64k -1.36
21
16
10
SYNC = 0, BRGH = 1, BRG16 = 0
FOSC = 4.000 MHz FOSC = 3.6864 MHz
SPBRG Actual SPBRG Actual SPBRG Actual
FOSC = 8.000 MHz
Actual
FOSC = 1.000 MHz
BAUD
RATE
%
%
%
%
SPBRG
value
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
—
—
—
—
—
—
—
—
—
207
103
25
—
—
—
191
95
23
21
11
3
300
0.16
207
51
25
—
5
1200
2400
9600
1202 0.16
2404 0.16
9615 0.16
10417 0.00
19.23k 0.16
1200 0.00
2400 0.00
9600 0.00
10473 0.53
19.2k 0.00
57.60k 0.00
115.2k 0.00
1202 0.16
2404 0.16
2404 0.16
9615 0.16
207
51
47
25
8
—
—
10417 10417 0.00
19.2k 19231 0.16
57.6k 55556 -3.55
23
10417 0.00
12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
115.2k
—
—
—
—
1
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
SPBRG Actual SPBRG Actual
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
Actual
%
SPBRG
value
Actual
Rate
%
%
%
SPBRG
value
Rate Error
Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
300.0 0.00
1200 -0.02
2401 -0.04
9615 0.16
6666
3332
832
300.0 -0.01
1200 -0.03
2399 -0.03
4166
1041
520
129
119
64
300.0 0.00
1200 0.00
2400 0.00
9600 0.00
10378 -0.37
19.20k 0.00
3839
959
479
119
110
59
300.0 0.00
1200 0.00
2400 0.00
9600 0.00
10473 0.53
19.20k 0.00
2303
575
287
71
1200
2400
9600
207
9615
0.16
10417 10417 0.00
19.2k 19.23k 0.16
191
10417 0.00
19.23k 0.16
65
103
35
DS40002195A-page 234
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
EUSART - Enhanced Universal Synchronous Asyn...
57.6k 57.14k -0.79
115.2k 117.6k 2.12
34
16
56.818 -1.36
113.636 -1.36
21
10
57.60k 0.00
115.2k 0.00
19
9
57.60k 0.00
115.2k 0.00
11
5
SYNC = 0, BRGH = 0, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
FOSC = 1.000 MHz
BAUD
RATE
Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
value
(decimal)
(decimal)
(decimal)
(decimal)
300
299.9 -0.02
1199 -0.08
2404 0.16
9615 0.16
1666
416
207
51
300.1 0.04
1202 0.16
2404 0.16
9615 0.16
10417 0.00
19.23k 0.16
832
207
103
25
300.0 0.00
1200 0.00
2400 0.00
9600 0.00
10473 0.53
19.20k 0.00
57.60k 0.00
115.2k 0.00
767
191
95
23
21
11
3
300.5 0.16
1202 0.16
2404 0.16
207
51
25
—
5
1200
2400
9600
—
—
10417 10417 0.00
19.2k 19.23k 0.16
57.6k 55556 -3.55
47
23
10417 0.00
25
12
—
—
—
—
—
—
—
—
—
8
—
—
—
—
—
115.2k
—
—
—
—
1
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 20.000 MHz FOSC = 18.432 MHz
FOSC = 32.000 MHz
FOSC = 11.0592 MHz
BAUD
RATE
Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG
value
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
300.0 0.00
1200 0.00
2400 0.01
9604 0.04
26666
6666
3332
832
300.0 0.00
1200 -0.01
2400 0.02
9597 -0.03
10417 0.00
19.23k 0.16
57.47k -0.22
116.3k 0.94
16665
4166
2082
520
479
259
86
300.0 0.00
1200 0.00
2400 0.00
9600 0.00
10425 0.08
19.20k 0.00
57.60k 0.00
115.2k 0.00
15359
3839
1919
479
441
239
79
300.0 0.00
1200 0.00
2400 0.00
9600 0.00
10433 0.16
19.20k 0.00
57.60k 0.00
115.2k 0.00
9215
2303
1151
287
264
143
47
1200
2400
9600
10417 10417 0.00
19.2k 19.18k -0.08
57.6k 57.55k -0.08
115.2k 115.9k 0.64
767
416
138
68
42
39
23
SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1
FOSC = 4.000 MHz FOSC = 3.6864 MHz
FOSC = 8.000 MHz
Actual SPBRG Actual
FOSC = 1.000 MHz
BAUD
RATE
%
%
SPBRG Actual
%
SPBRG Actual
%
SPBRG
value
Rate Error
value
Rate Error
value
Rate Error
value
Rate Error
(decimal)
(decimal)
(decimal)
(decimal)
300
1200
2400
300.0 0.00
1200 -0.02
2401 0.04
6666
1666
832
300.0 0.01
1200 0.04
2398 0.08
3332
832
300.0 0.00
1200 0.00
2400 0.00
3071
767
300.1 0.04
1202 0.16
2404 0.16
832
207
103
416
383
DS40002195A-page 235
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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EUSART - Enhanced Universal Synchronous Asyn...
9600
9615 0.16
207
191
103
34
9615 0.16
10417 0.00
19.23k 0.16
58.82k 2.12
111.1k -3.55
103
95
51
16
8
9600 0.00
10473 0.53
19.20k 0.00
57.60k 0.00
115.2k 0.00
95
87
47
15
7
9615 0.16
10417 0.00
19.23k 0.16
25
23
12
—
—
10417 10417
0
19.2k 19.23k 0.16
57.6k 57.14k -0.79
115.2k 117.6k 2.12
—
—
—
—
16
24.3.1 Auto-Baud Detect
The EUSART module supports automatic detection and calibration of the baud rate.
In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming
RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h
(ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising
edges including the Stop bit edge.
Setting the Auto-Baud Detect Enable (ABDEN) bit starts the auto-baud calibration sequence. While the ABD
sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the
Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 24-6. The fifth rising edge
will occur on the RXx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper
BRG period is left in the SPxBRGH:SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCxIF
interrupt flag is set. The value in the RCxREG needs to be read to clear the RCxIF interrupt. RCxREG content should
be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the
SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register.
The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 24-3. During ABD, both the
SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While
calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at 1/8th the BRG base clock rate.
The resulting byte measurement is the average bit time when clocked at full speed.
Note:ꢀ
1. If the Wake-up Enable (WUE) bit is set with the ABDEN bit, auto-baud detection will occur on the byte
following the Break character (see “Auto-Wake-up on Break”).
2. It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG
clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible.
3. During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-
baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair.
Table 24-3.ꢀBRG Counter Clock Rates
BRG16
BRGH
BRG Base Clock
FOSC/4
BRG ABD Clock
FOSC/32
1
1
0
0
1
0
1
0
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/64
FOSC/512
Note:ꢀ During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter,
independent of the BRG16 setting.
DS40002195A-page 236
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
EUSART - Enhanced Universal Synchronous Asyn...
Figure 24-6.ꢀAutomatic Baud Rate Calibration
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ꢋꢋꢋꢋꢣ
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ꢚꢙꢘꢁ d5
ꢚꢙꢘꢁ d6
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ꢚꢙꢘꢁ dꢦ
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ꢥꢖꢈꢗꢖ ꢕꢐꢖ s ꢕꢐꢖ 4 ꢕꢐꢖ 5 ꢕꢐꢖ 6 ꢕꢐꢖ y ꢕꢐꢖ ꢦ ꢕꢐꢖ ꢧ ꢕꢐꢖ ꢄ
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24.3.2 Auto-Baud Overflow
During the course of automatic baud detection, the Auto-Baud Detect Overflow (ABDOVF) bit will be set if the baud
rate counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit indicates that the
counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After
the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx pin.
Upon detecting the fifth RX edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit. The RCxIF
flag can be subsequently cleared by reading the RCxREG register. The ABDOVF bit can be cleared by software
directly.
To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit. The
ABDOVF bit will remain set if the ABDEN bit is not cleared first.
24.3.3 Auto-Wake-up on Break
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive
and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up
due to activity on the RX/DT line. This feature is available only in Asynchronous mode.
The Auto-Wake-up feature is enabled by setting the WUE bit. Once set, the normal receive sequence on RX/DT is
disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or
a wake-up signal character for the LIN protocol.)
The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated
synchronously to the Q clocks in normal CPU operating modes as shown in Figure 24-7, and asynchronously if the
device is in Sleep mode, as shown in Figure 24-8. The interrupt condition is cleared by reading the RCxREG register.
The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals
to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next
character.
24.3.3.1 Special Considerations
Break Character
To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros.
When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is
set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted
as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent
characters can result in framing or overrun errors.
DS40002195A-page 237
Preliminary Datasheet
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EUSART - Enhanced Universal Synchronous Asyn...
Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times
recommended for LIN bus, or any number of bit times for standard RS-232 devices.
WUE Bit
The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in hardware by a
rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and
discarding its contents.
To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before
setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the
Sleep mode.
Figure 24-7.ꢀAuto-Wake-up Bit (WUE) Timing During Normal Operation
Rev. 10-000 326A
2/13/201 7
q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4
FOSC
Bit set by user
Auto cleared
WUE bit
RXx/DTx
line
RCxIF
Cleared due to user read of RCxREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
Figure 24-8.ꢀAuto-Wake-up Bit (WUE) Timings During Sleep
Rev. 10-000 327A
2/13/201 7
q1 q2 q3 q4 q1 q2 q3 q4
q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4
q1
FOSC
Bit set by user
Auto cleared
WUE bit
RXx/DTx
line
RCxIF
Cleared due to user read of RCxREG
Sleep command executed
Sleep ends
Note 1: The EUSART remains in Idle while the WUE bit is set.
24.3.4 Break Character Sequence
The EUSART module has the capability of sending the special Break character sequences that are required by the
LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit.
To send a Break character, set the Send Break Character (SENDB) and Transmit Enable (TXEN) bits. The Break
character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be
ignored and all ‘0’s will be transmitted.
The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to
preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in
the LIN specification).
The Transmit Shift Register Status (TRMT) bit indicates when the transmit operation is active or idle, just as it does
during normal transmission. See Figure 24-9 for more details.
DS40002195A-page 238
Preliminary Datasheet
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EUSART - Enhanced Universal Synchronous Asyn...
24.3.4.1 Break and Sync Transmit Sequence
The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte.
This sequence is typical of a LIN bus master.
1. Configure the EUSART for the desired mode.
2. Set the TXEN and SENDB bits to enable the Break sequence.
3. Load the TXxREG with a dummy character to initiate transmission (the value is ignored).
4. Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer.
5. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted.
When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG.
24.3.5 Receiving a Break Character
The EUSART module can receive a Break character in two ways.
The first method to detect a Break character uses the Framing Error (FERR) bit and the received data as indicated by
RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate.
A Break character has been received when all three of the following conditions are true:
•
•
•
RCxIF bit is set
FERR bit is set
RCxREG = 00h
The second method uses the Auto-Wake-up feature described in “Auto-Wake-up on Break”. By enabling this feature,
the EUSART will sample the next two transitions on RX/DT, cause an RCxIF interrupt, and receive the next data byte
followed by another interrupt.
Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both
methods, the user can set the ABDEN bit before placing the EUSART in Sleep mode.
Figure 24-9.ꢀSend Break Character Sequence
Dummy
Rev. 10-000 118A
2/13/201 7
Write
Write to TXxREG
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Break
bit 11
Stop bit
TXxIF bit
(Transmit Buffer
Reg Empty Flag)
TRMT bit
(Transmit Shift
Reg Empty Flag)
SENDB
(send break
control bit)
Auto cleared
SENDB sampled here
24.4
EUSART Synchronous Mode
Synchronous serial communications are typically used in systems with a single master and one or more slaves. The
master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the
system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry.
There are two signal lines in Synchronous mode: a bidirectional data line (DT) and a clock line (CK). The slaves use
the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit
DS40002195A-page 239
Preliminary Datasheet
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EUSART - Enhanced Universal Synchronous Asyn...
shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the
fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can
operate as either a master or slave device.
Start and Stop bits are not used in synchronous transmissions.
24.4.1 Synchronous Master Mode
The following bits are used to configure the EUSART for synchronous master operation:
•
•
•
The SYNC bit is set to ‘1’ to configure the EUSART for synchronous operation
The Clock Source Select (CSRC) bit is set to ‘1’ to configure the EUSART as the master
The Single Receive Enable (SREN) bit is set to ‘0’ for transmit; SREN = 1for receive (recommended setting to
receive 1 byte)
•
•
The Continuous Receive Enable (CREN) bit is set to ‘0’ for transmit; CREN = 1to receive continuously
The SPEN bit is set to ‘1’ to enable the EUSART interface
Important:ꢀ Clearing the SREN and CREN bits ensure that the device is in the Transmit mode, otherwise
the device will be configured to receive.
24.4.1.1 Master Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a
master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is automatically enabled when the
EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to
ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many
clock cycles are generated as there are data bits.
24.4.1.2 Clock Polarity
A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the Clock/Transmit
Polarity Select (SCKP) bit. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data
changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is
cleared, the data changes on the rising edge of each clock.
24.4.1.3 Synchronous Master Transmission
Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are
automatically enabled when the EUSART is configured for synchronous master transmit operation.
A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a
previous character the new character data is held in the TXxREG until the last bit of the previous character has been
transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data
in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately
following the transfer of the data to the TSR from the TXxREG.
Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock
edge.
Note:ꢀ The TSR register is not mapped in data memory, so it is not available to the user.
24.4.1.4 Synchronous Master Transmission Setup
1. Initialize the SPxBRGH;SPxBRGL register pair and the BRG16 bit to achieve the desired baud rate (see
section “EUSART Baud Rate Generator (BRG)”).
2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register.
Both selections should enable the same pin.
3. Select the clock output pin by writing the appropriate values to the RxyPPS register and TXxPPS register. Both
selections should enable the same pin.
4. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.
5. Disable Receive mode by clearing the SREN and CREN bits.
DS40002195A-page 240
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EUSART - Enhanced Universal Synchronous Asyn...
6. Enable Transmit mode by setting the TXEN bit.
7. If 9-bit transmission is desired, set the TX9 bit.
8. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
9. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit.
10. Start transmission by loading data to the TXxREG register.
Figure 24-10.ꢀSynchronous Transmission
Rev. 10-000 115A
2/7/201 7
Word 1
Write to TXxREG
BRG Output
(Shift Clock)
TXx/CKx pin
Start bit
bit 0
bit 1
Word 1
bit 7/8
Stop bit
TXxIF bit
(Transmit Buffer
Reg Empty Flag)
1 TCY
TRMT bit
(Transmit Shift
Reg Empty Flag)
24.4.1.5 Synchronous Master Reception
Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the EUSART is
configured for synchronous master receive operation.
In Synchronous mode, reception is enabled by setting either the Single Receive Enable (SREN) bit or the Continuous
Receive Enable (CREN) bit.
When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single
character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are
continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops
immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the
completion of the first character and CREN takes precedence.
To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TX/CK
clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR,
the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least
Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as
long as there are unread characters in the receive FIFO.
Note:ꢀ If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to
function.
24.4.1.6 Slave Clock
Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a
slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is automatically disabled when the device
is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to
ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many
clock cycles should be received as there are data bits.
Important:ꢀ If the device is configured as a slave and the TX/CK function is on an analog pin, the
corresponding ANSEL bit must be cleared.
DS40002195A-page 241
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24.4.1.7 Receive Overrun Error
The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety,
is received before the FIFO is accessed. When this happens the Overrun Error (OERR) bit is set. The characters
already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The
error must be cleared by either clearing the CREN bit or by resetting the EUSART by clearing the SPEN bit.
24.4.1.8 Receiving 9-Bit Characters
The EUSART supports 9-bit character reception. When the 9-Bit Receive Enable (RX9) bit is set, the EUSART will
shift nine bits into the RSR for each character received. The RX9D bit is the ninth and Most Significant data bit of the
top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit
must be read before reading the eight Least Significant bits from the RCxREG.
24.4.1.9 Synchronous Master Reception Setup
1. Initialize the SPxBRGH:SPxBRGL register pair and set or clear the BRG16 bit, as required, to achieve the
desired baud rate.
2. Select the receive input pin by writing the appropriate values to the RxyPPS register and RXxPPS register.
Both selections should enable the same pin.
3. Select the clock output pin by writing the appropriate values to the RxyPPS register and TXxPPS register. Both
selections should enable the same pin.
4. Clear the ANSEL bit for the RXx pin (if applicable).
5. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.
6. Ensure that CREN and SREN bits are cleared.
7. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
8. If 9-bit reception is desired, set bit RX9.
9. Start reception by setting the SREN bit or for continuous reception, set the CREN bit.
10. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if
the enable bit RCxIE was set.
11. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.
12. Read the 8-bit received data by reading the RCxREG register.
13. If an overrun error occurs, clear the error by either clearing the CREN bit or by clearing the SPEN bit which
resets the EUSART.
Figure 24-11.ꢀSynchronous Reception (Master Mode, SREN)
Rev. 10-000 121A
2/13/201 7
RXx/DTx pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TXx/CKx pin
SCKP = 0
TXx/CKx pin
SCKP = 1
Write to SREN
SREN bit
CREN bit
‘0’
‘0’
RCxIF
(Interrupt)
Read
RCxREG
DS40002195A-page 242
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24.4.2 Synchronous Slave Mode
The following bits are used to configure the EUSART for synchronous slave operation:
•
•
•
•
•
SYNC = 1(configures the EUSART for synchronous operation.)
CSRC = 0(configures the EUSART as a slave)
SREN = 0(for transmit); SREN = 1(for single byte receive)
CREN = 0(for transmit); CREN = 1(recommended setting for continuous receive)
SPEN = 1(enables the EUSART)
Important:ꢀ Clearing the SREN and CREN bits ensure that the device is in Transmit mode, otherwise the
device will be configured to receive.
24.4.2.1 EUSART Synchronous Slave Transmit
The operation of the Synchronous Master and Slave modes are identical (see “Synchronous Master Transmission”),
except in the case of the Sleep mode.
If two words are written to the TXxREG and then the SLEEPinstruction is executed, the following will occur:
1. The first character will immediately transfer to the TSR register and transmit.
2. The second word will remain in the TXxREG register.
3. The TXxIF bit will not be set.
4. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to
the TSR and the TXxIF bit will now be set.
5. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next
instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine.
24.4.2.2 Synchronous Slave Transmission Setup
1. Set the SYNC and SPEN bits and clear the CSRC bit.
2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register.
Both selections should enable the same pin.
3. Select the clock input pin by writing the appropriate value to the TXxPPS register.
4. Clear the ANSEL bit for the CKx pin (if applicable).
5. Clear the CREN and SREN bits.
6. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
7. If 9-bit transmission is desired, set the TX9 bit.
8. Enable transmission by setting the TXEN bit.
9. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit.
10. Prepare for transmission by writing the Least Significant eight bits to the TXxREG register. The word will be
transmitted in response to the Master clocks at the CKx pin.
24.4.2.3 EUSART Synchronous Slave Reception
The operation of the Synchronous Master and Slave modes is identical (see “Synchronous Master Reception”), with
the following exceptions:
•
•
•
Sleep
CREN bit is always set, therefore the receiver is never Idle
SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is
received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt
generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will
branch to the interrupt vector.
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24.4.2.4 Synchronous Slave Reception Setup:
1. Set the SYNC and SPEN bits and clear the CSRC bit.
2. Select the receive input pin by writing the appropriate value to the RXxPPS register.
3. Select the clock input pin by writing the appropriate values to the TXxPPS register.
4. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable).
5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
6. If 9-bit reception is desired, set the RX9 bit.
7. Set the CREN bit to enable reception.
8. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set.
9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit.
10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register.
11. If an overrun error occurs, clear the error by either clearing the CREN bit or by clearing the SPEN bit which
resets the EUSART.
24.5
EUSART Operation During Sleep
The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the
system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers
during Sleep.
Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers.
24.5.1 Synchronous Receive During Sleep
To receive during Sleep, all the following conditions must be met before entering Sleep mode:
•
•
•
RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see
“Synchronous Slave Reception Setup”).
If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON
register.
The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive
buffer.
Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and TXx/CKx pins,
respectively. When the data word has been completely clocked in by the external device, the RCxIF Interrupt Flag bit
of the PIRx register will be set. Thereby, waking the processor from Sleep.
Upon waking from Sleep, the instruction following the SLEEPinstruction will be executed. If the Global Interrupt
Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine (ISR) will be called.
24.5.2 Synchronous Transmit During Sleep
To transmit during Sleep, all the following conditions must be met before entering Sleep mode:
•
The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see
“Synchronous Slave Transmission Setup”).
•
The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and
transmit buffer.
•
•
The TXxIE interrupt enable bits of the PIEx register and PEIE of the INTCON register must be written to ‘1’.
If interrupts are desired, set the GIE bit of the INTCON register.
Upon entering Sleep mode, the device will be ready to accept clocks on the TXx/CKx pin and transmit data on the
RXx/DTx pin. When the data word in the TSR register has been completely clocked out by the external device, the
pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor
from Sleep. At this point, the TXxREG is available to accept another character for transmission. Writing TXxREG will
clear the TXxIF flag.
Upon waking from Sleep, the instruction following the SLEEPinstruction will be executed. If the Global Interrupt
Enable (GIE) bit is also set then the Interrupt Service Routine (ISR) will be called.
DS40002195A-page 244
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24.6
Register Definitions: EUSART Control
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24.6.1 TXxSTA
Name:ꢀ
TXxSTA
Address:ꢀ 0x011E
Transmit Status and Control Register
Bit
7
CSRC
R/W
0
6
5
TXEN
R/W
0
4
SYNC
R/W
0
3
SENDB
R/W
0
2
BRGH
R/W
0
1
TRMT
R
0
TX9D
R/W
0
TX9
R/W
0
Access
Reset
1
Bit 7 – CSRCꢀClock Source Select
Value
1
0
X
Condition
SYNC = 1
SYNC = 1
SYNC = 0
Description
Master mode (clock generated internally from BRG)
Slave mode (clock from external source)
Don’t care
Bit 6 – TX9ꢀ9-bit Transmit Enable
Value
Description
1
0
Selects 9-bit transmission
Selects 8-bit transmission
Bit 5 – TXENꢀTransmit Enable
Enables transmitter(1)
Value
Description
1
0
Transmit enabled
Transmit disabled
Bit 4 – SYNCꢀEUSART Mode Select
Value
Description
1
0
Synchronous mode
Asynchronous mode
Bit 3 – SENDBꢀSend Break Character
Value
Condition Description
1
0
X
SYNC = 0
SYNC = 0
SYNC = 1
Send Sync Break on next transmission (cleared by hardware upon completion)
Sync Break transmission disabled or completed
Don’t care
Bit 2 – BRGHꢀHigh Baud Rate Select
Value
1
0
X
Condition
SYNC = 0
SYNC = 0
SYNC = 1
Description
High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16
Low speed
Don’t care
Bit 1 – TRMTꢀTransmit Shift Register (TSR) Status
Value
Description
1
0
TSR is empty
TSR is not empty
Bit 0 – TX9DꢀNinth bit of Transmit Data
Can be address/data bit or a parity bit.
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Note:ꢀ
1. SREN and CREN bits override TXEN in Sync mode.
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24.6.2 RCxSTA
Name:ꢀ
RCxSTA
Address:ꢀ 0x011D
Receive Status and Control Register
Bit
7
SPEN
R/W
0
6
5
SREN
R/W/HC
0
4
CREN
R/W
0
3
ADDEN
R/W
0
2
FERR
R
1
0
RX9
R/W
0
OERR
R/HC
0
RX9D
R/HC
0
Access
Reset
0
Bit 7 – SPENꢀSerial Port Enable
Value
Description
1
Serial port enabled
0
Serial port disabled (held in Reset)
Bit 6 – RX9ꢀ9-Bit Receive Enable
Value
Description
1
0
Selects 9-bit reception
Selects 8-bit reception
Bit 5 – SRENꢀSingle Receive Enable
Controls reception. This bit is cleared by hardware when reception is complete
Value
Condition
Description
1
0
X
SYNC = 1AND CSRC = 1
SYNC = 1AND CSRC = 1
SYNC = 0OR CSRC = 0
Start single receive
Single receive is complete
Don’t care
Bit 4 – CRENꢀContinuous Receive Enable
Value
Condition Description
1
SYNC = 1 Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0
1
0
SYNC = 1 Disables continuous receive
SYNC = 0 Enables receiver
SYNC = 0 Disables receiver
Bit 3 – ADDENꢀAddress Detect Enable
Value
Condition
Description
1
SYNC = 0AND RX9 = 1 The receive buffer is loaded and the interrupt occurs only when the ninth
received bit is set
0
X
SYNC = 0AND RX9 = 1 All bytes are received and interrupt always occurs. Ninth bit can be used as
parity bit
RX9 = 0OR SYNC = 1 Don't care
Bit 2 – FERRꢀFraming Error
Value
Description
1
0
Unread byte in RCxREG has a framing error
Unread byte in RCxREG does not have a framing error
Bit 1 – OERRꢀOverrun Error
Value
Description
1
0
Overrun error (can be cleared by clearing either SPEN or CREN bit)
No overrun error
Bit 0 – RX9DꢀNinth bit of Received Data
This can be address/data bit or a parity bit which is determined by user firmware.
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24.6.3 BAUDxCON
Name:ꢀ
BAUDxCON
Address:ꢀ 0x011F
Baud Rate Control Register
Bit
7
6
RCIDL
R
5
4
SCKP
R/W
0
3
BRG16
R/W
0
2
1
WUE
R/W
0
0
ABDEN
R/W
0
ABDOVF
Access
Reset
R
0
0
Bit 7 – ABDOVFꢀAuto-Baud Detect Overflow
Value
1
0
X
Condition
SYNC = 0
SYNC = 0
SYNC = 1
Description
Auto-baud timer overflowed
Auto-baud timer did not overflow
Don’t care
Bit 6 – RCIDLꢀReceive Idle Flag
Value
1
0
X
Condition
SYNC = 0
SYNC = 0
SYNC = 1
Description
Receiver is Idle
Start bit has been received and the receiver is receiving
Don’t care
Bit 4 – SCKPꢀClock/Transmit Polarity Select
Value
1
0
1
0
Condition
SYNC = 0
SYNC = 0
SYNC = 1
SYNC = 1
Description
Idle state for transmit (TX) is a low level (transmit data inverted)
Idle state for transmit (TX) is a high level (transmit data is non-inverted)
Data is clocked on rising edge of the clock
Data is clocked on falling edge of the clock
Bit 3 – BRG16ꢀ16-bit Baud Rate Generator Select
Value
Description
1
0
16-bit Baud Rate Generator is used
8-bit Baud Rate Generator is used
Bit 1 – WUEꢀWake-up Enable
Value
Condition Description
1
SYNC = 0 Receiver is waiting for a falling edge. Upon falling edge no character will be received and
flag RCxIF will be set. WUE will automatically clear after RCxIF is set.
SYNC = 0 Receiver is operating normally
0
X
SYNC = 1 Don’t care
Bit 0 – ABDENꢀAuto-Baud Detect Enable
Value
1
0
X
Condition
SYNC = 0
SYNC = 0
SYNC = 1
Description
Auto-Baud Detect mode is enabled (clears when auto-baud is complete)
Auto-Baud Detect is complete or mode is disabled
Don’t care
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24.6.4 RCxREG
Name:ꢀ
RCxREG
Address:ꢀ 0x0119
Receive Data Register
Bit
7
6
5
4
3
2
1
0
RCREG[7:0]
Access
Reset
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Bits 7:0 – RCREG[7:0]ꢀReceive data
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24.6.5 TXxREG
Name:ꢀ
TXxREG
Address:ꢀ 0x011A
Transmit Data Register
Bit
7
6
5
4
3
2
1
0
TXREG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TXREG[7:0]ꢀTransmit Data
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24.6.6 SPxBRG
Name:ꢀ
SPxBRG
Address:ꢀ 0x011B
EUSART Baud Rate Generator
Bit
15
14
13
12
11
10
9
8
SPBRG[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
SPBRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – SPBRG[15:0]ꢀBaud Rate Register
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
SPxBRGH: Accesses the high byte SPBRG[15:8]
SPxBRGL: Accesses the low byte SPBRG[7:0]
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24.7
Register Summary - EUSART
Address
Name
Bit Pos.
0x00
...
Reserved
0x0118
0x0119
0x011A
RC1REG
TX1REG
7:0
7:0
7:0
15:8
7:0
7:0
7:0
RCREG[7:0]
TXREG[7:0]
SPBRG[7:0]
SPBRG[15:8]
0x011B
SP1BRG
0x011D
0x011E
0x011F
RC1STA
TX1STA
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
SYNC
SCKP
ADDEN
SENDB
BRG16
FERR
BRGH
OERR
TRMT
WUE
RX9D
TX9D
BAUD1CON
ABDOVF
RCIDL
ABDEN
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MSSP - Master Synchronous Serial Port Module
25.
MSSP - Master Synchronous Serial Port Module
The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other
peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, Shift registers, display
drivers, A/D converters, etc. The MSSP module can operate in one of two modes:
•
•
Serial Peripheral Interface (SPI)
Inter-Integrated Circuit (I2C)
The SPI interface can operate in Master or Slave mode and supports the following features:
•
•
•
Selectable Clock Parity
Slave Select Synchronization (Slave Mode Only)
Daisy-Chain Connection of Slave Devices
The I2C interface can operate in Master or Slave mode and supports the following modes and features:
•
•
•
•
•
•
•
•
•
•
•
Byte NACKing (Slave Mode)
Limited Multi-Master Support
7-Bit and 10-Bit Addressing
Start and Stop Interrupts
Interrupt Masking
Clock Stretching
Bus Collision Detection
General Call Address Matching
Address Masking
Address Hold and Data Hold Modes
Selectable SDA Hold Times
25.1
SPI Mode Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication bus that operates in Full-Duplex
mode. Devices communicate in a master/slave environment where the master device initiates the communication. A
slave device is selected for communication using the Slave Select feature.
The SPI bus specifies four signal connections:
•
•
•
•
Serial Clock (SCK)
Serial Data Out (SDO)
Serial Data In (SDI)
Slave Select (SS)
Figure 25-1 shows the block diagram of the MSSP module when operating in SPI mode.
DS40002195A-page 254
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MSSP - Master Synchronous Serial Port Module
Figure 25-1.ꢀMSSP Block Diagram (SPI mode)
Data bus
Read
8
Write
8
SSPxBUF
8
SSPxDATPPS
PPS
SDI
SSPxSR
SDO_out
Bit 0
Shift clock
SDO
PPS
RxyPPS(1)
2
SSPxSSPPS
PPS
(CKP, CKE)
clock select
Control
Enable
SSx
SSPM[3:0]
4
Edge
select
PPS
SCK_out
(T2_match)
2
SSPxCLKPPS(2)
Edge
select
Prescaler
4, 16, 64
SCK
PPS
TOSC
TRIS bit
RxyPPS
Baud Rate
Generator
(SSPxADD)
Note 1: Output selection for Master mode
2: Input selection for Slave and Master modes
The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are
used, an independent Slave Select connection is required from the master device to each slave device. The master
selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears
disconnected from the bus when they are not selected.
Figure 25-2 shows a typical connection between a master device and multiple slave devices.
DS40002195A-page 255
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MSSP - Master Synchronous Serial Port Module
Figure 25-2.ꢀSPI Master and Multiple Slave Connection
Rev. 30-000012A
3/31/2017
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
General I/O
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
Transmissions involve two Shift registers, eight bits in size, one in the master and one in the slave. Data is always
shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least
Significant bit (LSb) is shifted into the same register.
Figure 25-3 shows a typical connection between two processors configured as master and slave devices.
Figure 25-3.ꢀSPI Master/Slave Connection
Rev/ 30-000013A
3/31/2017
SPI Slave SSPM[3:0] =
SPI Master SSPM[3:0] =
010x
00xx
= 1010
SDO
SDI
Serial Input Buffer
Serial Input Buffer
(SSPxBUF)
(BUF)
SDO
SDI
Shift Register
(SSPSR)
Shift Register
(SSPSR)
LSb
LSb
MSb
MSb
Serial Clock
SCK
SCK
SS
Slave Select
(optional)
General I/O
Processor 2
Processor 1
Data is shifted out of both Shift registers on the programmed clock edge and latched on the opposite edge of the
clock.
The master device transmits information out on its SDO output pin, which is connected to and received by the slave’s
SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to and received
by the master’s SDI input pin.
DS40002195A-page 256
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
To begin communication, the master device transmits both the MSb from its Shift register the clock signal. Both the
master and the slave devices should be configured for the same clock polarity. During each SPI clock cycle, a full-
duplex data transmission occurs. This means that while the master device is sending out the MSb from its Shift
register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its Shift register, the slave
device is also sending out the MSb from its Shift register (on its SDO pin) and the master device is reading this bit
and saving it as the LSb of its Shift register.
After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to
exchange, the Shift registers are loaded with new data and the process repeats itself.
Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three
scenarios for data transmission:
•
•
•
Master sends useful data and slave sends dummy data.
Master sends useful data and slave sends useful data.
Master sends dummy data and slave sends useful data.
Transmissions must be performed in multiples of eight clock cycles. When there is no more data to be transmitted,
the master stops sending the clock signal and it deselects the slave.
Every slave device connected to the bus that has not been selected through its slave select line must disregard the
clock and transmission signals and must not transmit out any data of its own.
25.1.1 SPI Mode Registers
The MSSP module has six registers for SPI mode operation. These are:
•
•
•
•
•
•
MSSP STATUS register (SSPxSTAT)
MSSP Control register 1 (SSPxCON1)
MSSP Control register 3 (SSPxCON3)
MSSP Data Buffer register (SSPxBUF)
MSSP Address register (SSPxADD)
MSSP Shift register (SSPSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and status registers for SPI mode operation. The SSPxCON1 register is
readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are
read/write.
One of the five SPI Master modes uses the SSPxADD value to determine the Baud Rate Generator clock frequency.
More information on the Baud Rate Generator is available in the “Baud Rate Generator” section.
SSPSR is the Shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR
register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read.
In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete
byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR.
25.1.2 SPI Mode Operation
When initializing the SPI several options need to be specified. This is done by programming the appropriate control
bits (SSPxCON1[5:0] and SSPxSTAT[7:6]). These control bits allow the following to be specified:
•
•
•
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Data Input Sample Phase (middle or end of data output time)
Clock Edge (output data on rising/falling edge of SCK)
Clock Rate (Master mode only)
Slave Select mode (Slave mode only)
DS40002195A-page 257
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
To enable the serial port, the SSP Enable bit (SSPEN) must be set. To reset or reconfigure SPI mode, clear the
SSPEN bit, re-initialize the SSPxCONy registers and then set the SSPEN bit. The SDI, SDO, SCK and SS serial port
pins are selected with the PPS controls. For the pins to behave as the serial port function, some must have their data
direction bits (in the TRIS register) appropriately programmed as follows:
•
•
•
•
•
•
SDI must have corresponding TRIS bit set.
SDO must have corresponding TRIS bit cleared.
SCK (Master mode) must have corresponding TRIS bit cleared.
SCK (Slave mode) must have corresponding TRIS bit set.
The RxyPPS and SSPxCLKPPS controls must select the same pin.
SS must have corresponding TRIS bit set.
Any serial port function that is not desired may be overridden by programming the corresponding data direction
(TRIS) register to the opposite value.
The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts
the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the
received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register.
Then, the Buffer Full Status (BF) bit and the MSSP Interrupt Flag (SSPxIF) bit are set. This double-buffering of the
received data allows the next byte to start reception before reading the data that was just received. Any write to the
SSPxBUF register during transmission/reception of data will be ignored and the Write Collision Detect (WCOL) bit will
be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete
successfully.
When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte
of data to transfer is written to the SSPxBUF. The BF bit, indicates when SSPxBUF has been loaded with the
received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be
irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/
reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure
that a write collision does not occur.
Important:ꢀ The SSPSR is not directly readable or writable and can only be accessed by addressing the
SSPxBUF register.
25.1.2.1 SPI Master Mode
The master can initiate the data transfer at any time because it controls the SCK line. The master determines when
the slave (Processor 2, Figure 25-3) is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only
going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to
shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into
the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set).
The clock polarity is selected by appropriately programming the Clock Polarity Select (CKP) and SPI Clock Edge
Select (CKE) bits. Figure 25-4 shows the four clocking configurations. When the CKE bit is set, the SDO data is valid
one half of a clock cycle before a clock edge appears on SCK, and transmission occurs on the transition from the
Active to Idle clock state. When CKE is clear, the SDO data is valid at the same time as the clock edge appears on
SCK, and transmission occurs on the transition from the Idle to Active clock states.
The SPI Data Input Sample (SMP) bit determines when the SDI input is sampled. When SMP is set, input data is
sampled at the end of the data output time. When SMP is clear, input data is sampled at the middle of the data output
time.
The SPI clock rate (bit rate) is user programmable to be one of the following:
•
•
•
FOSC/4 (or TCY
FOSC/16 (or 4 * TCY
FOSC/64 (or 16 * TCY
)
)
)
DS40002195A-page 258
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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MSSP - Master Synchronous Serial Port Module
•
•
Timer2 output/2
FOSC/(4 * (SSPxADD + 1))
Important:ꢀ In Master mode the clock signal output to the SCK pin is also the clock signal input to the
peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral
input with the SSPxCLKPPS register. The pin that is selected using the SSPxCLKPPS register should also
be made a digital I/O. This is done by clearing the corresponding ANSEL bit.
Figure 25-4.ꢀSPI Mode Waveform (Master Mode)
Rev. 30-000014A
3/13/2017
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
Modes
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
bit 6
bit 6
bit 2
bit 2
bit 5
bit 5
bit 4
bit 4
bit 1
bit 1
bit 0
bit 0
SDO
(CKE = 0)
bit 7
bit 7
bit 3
bit 3
SDO
(CKE = 1)
SDI
(SMP = 0)
bit 0
bit 7
Input
Sample
(SMP = 0)
SDI
(SMP = 1)
bit 0
bit 7
Input
Sample
(SMP = 1)
SSPxIF
SSPSR to
SSPxBUF
25.1.2.2 SPI Slave Mode
In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is
latched, the SSPxIF Interrupt Flag bit is set.
Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be
observed by reading the SCK pin. The Idle state is determined by the CKP bit.
While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock
must meet the minimum high and low times as specified in the “Electrical Specifications” chapter.
While in Sleep mode, the slave can transmit/receive data. The Shift register is clocked from the SCK pin input and
when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep.
DS40002195A-page 259
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
25.1.2.3 Daisy-Chain Configuration
The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the
second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is
connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what
was received during the first group of clock pulses. The whole chain acts as one large communication shift register.
The daisy-chain feature only requires a single Slave Select line from the master device.
In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the Buffer
Overwrite Enable (BOEN) bit will enable writes to the SSPxBUF register, even if the previous byte has not been read.
This allows the software to ignore data that may not apply to it.
Figure 25-5 shows the block diagram of a typical daisy-chain connection when operating in SPI mode.
Figure 25-5.ꢀSPI Daisy-Chain Connection
Rev. 30-000015A
3/31/2017
SCK
SDO
SCK
SDI
SDO
SS
SPI Master
SPI Slave
#1
SDI
General I/O
SCK
SDI
SDO
SS
SPI Slave
#2
SCK
SDI
SDO
SS
SPI Slave
#3
25.1.2.4 Slave Select Synchronization
The Slave Select can also be used to synchronize communication (see Figure 25-6). The Slave Select line is held
high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a
new transmission is starting.
If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave
Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is
pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync
with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select
line allows the slave and master to align themselves at the beginning of each transmission.
The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (MSSP
Mode Select (SSPM) bits = 0100).
When the SS pin is low, transmission and reception are enabled and the SDO pin is driven.
When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes
a floating output. External pull-up/pull-down resistors may be desirable depending on the application.
When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high
level or clearing the SSPEN bit.
DS40002195A-page 260
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MSSP - Master Synchronous Serial Port Module
Important:ꢀ
1. When the SPI is in Slave mode with SS pin control enabled (SSPM = 0100), the SPI module will
reset if the SS pin is set to VDD
.
2. When the SPI is used in Slave mode with CKE set; the user must enable SS pin control (see Figure
25-8. If CKE is clear, SS pin control is optional (see Figure 25-7).
3. While operated in SPI Slave mode the SMP bit must remain clear.
Figure 25-6.ꢀSlave Select Synchronous Waveform
Rev. 30-000016A
4/10/2017
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPSR
and bit count are reset
SSPxBUF to
SSPSR
bit 6
bit 6
bit 7
bit 7
bit 0
SDO
SDI
bit 7
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
DS40002195A-page 261
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
Figure 25-7.ꢀSPI Mode Waveform (Slave Mode with CKE = 0)
Rev. 30-000017A
4/3/2017
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
bit 6
bit 2
bit 5
bit 4
bit 3
bit 1
bit 0
SDO
bit 7
SDI
bit 0
bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
Figure 25-8.ꢀSPI Mode Waveform (Slave Mode with CKE = 1)
Rev. 30-000018A
4/1/2017
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
bit 6
bit 3
bit 2
bit 5
bit 4
bit 1
bit 0
SDO
bit 7
bit 7
SDI
bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
DS40002195A-page 262
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
25.1.2.5 SPI Operation in Sleep Mode
In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception
will remain in that state until the device wakes. After the device returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight
bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device.
25.2
I2C Mode Overview
The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a
master/slave environment where the master devices initiate the communication. A slave device is controlled through
addressing. Figure 25-9 and Figure 25-10 show block diagrams of the I2C Master and Slave modes, respectively.
Figure 25-9.ꢀMSSP Block Diagram (I2C Master mode)
Rev. 30-000019A
4/3/2017
Internal
data bus
[SSPM[3:0]]
SSPxDATPPS(1)
Read
Write
SDA
SDA in
PPS
SSPxBUF
SSPSR
Generator
(SSPxADD)
Shift
Clock
RxyPPS(1)
PPS
MSb
LSb
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
SSPxCLKPPS(2)
PPS
SCL
PPS
Start bit detect,
Stop bit detect
RxyPPS(2)
Write collision detect
Clock arbitration
State counter for
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSP1IF, BCL1IF
SCL in
end of XMIT/RCV
Address Match detect
Bus Collision
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.
DS40002195A-page 263
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
Figure 25-10.ꢀMSSP Block Diagram (I2C Slave mode)
Rev. 30-000020A
4/3/2017
Internal
Data Bus
Read
Write
SSPxCLKPPS(2)
SSPxBUF Reg
SSPSR Reg
SCL
PPS
PPS
Shift
Clock
Clock
Stretching
MSb
LSb
RxyPPS(2)
SSPxMSK Reg
Match Detect
SSPxADD Reg
SSPxDATPPS(1)
SDA
Addr Match
PPS
PPS
Set, Reset
S, P bits
(SSPxSTAT Reg)
Start and
Stop bit Detect
RxyPPS(1)
Note 1: SDA pin selections must be the same for input and output.
2: SCL pin selections must be the same for input and output.
The I2C bus specifies two signal connections:
•
•
Serial Clock (SCL)
Serial Data (SDA)
Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply
voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one.
Figure 25-11 shows a typical connection between two processors configured as master and slave devices.
Figure 25-11.ꢀI2C Master/Slave Connection
Rev. 30-000021A
4/3/2017
VDD
SCL
SDA
SCL
SDA
VDD
Master
Slave
The I2C bus can operate with one or more master devices and one or more slave devices.
There are four potential modes of operation for a given device:
•
•
•
Master Transmit mode
(master is transmitting data to a slave)
Master Receive mode
(master is receiving data from a slave)
Slave Transmit mode
(slave is transmitting data to a master)
DS40002195A-page 264
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MSSP - Master Synchronous Serial Port Module
•
Slave Receive mode
(slave is receiving data from the master)
To begin communication, the master device transmits a Start condition followed by the address byte of the slave it
intends to communicate with. A Start condition is indicated by a high-to-low transition of the SDA line while the SCL
line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. This is followed by a single
Read/Write Information (R/W) bit, which determines whether the master intends to transmit to or receive data from
the slave device. The R/W bit is sent out as a logical one when the master intends to read data from the slave, and is
sent out as a logical zero when it intends to write data to the slave.
If the requested slave exists on the bus, it will respond with an Acknowledge sequence, otherwise known as an ACK.
The Acknowledge sequence is an active-low signal, which holds the SDA line low to indicate to the transmitter that
the slave device has received the transmitted data and is ready to receive more. The master then continues to either
transmit to or receive data from the slave.
The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL
line is held high are used to indicate Start and Stop conditions.
If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after
each byte with an ACK sequence. In this example, the master device is in Master Transmit mode and the slave is in
Slave Receive mode.
If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds
after each byte with an ACK sequence. In this example, the master device is in Master Receive mode and the slave
is in Slave Transmit mode.
On the last byte of data communicated, the master device may end the transmission by sending a Stop condition. If
the master device is in Receive mode, it sends the Stop condition in place of the last ACK sequence. A Stop
condition is indicated by a low-to-high transition of the SDA line while the SCL line is held high.
In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the
master device may send Restart condition in place of the Stop condition or last ACK sequence when it is in Receive
mode.
The I2C bus specifies three message protocols:
•
•
•
Single message where a master writes data to a slave.
Single message where a master reads data from a slave.
Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes
and reads, to one or more slaves.
25.2.1 I2C Mode Registers
The MSSP module has eight registers for I2C operation.
These are:
•
•
•
•
•
•
•
•
MSSP Status register (SSPxSTAT)
MSSP Control register 1 (SSPxCON1)
MSSP Control register 2 (SSPxCON2)
MSSP Control register 3 (SSPxCON3)
Serial Receive/Transmit Buffer register (SSPxBUF)
MSSP Address register (SSPxADD)
I2C Slave Address Mask register (SSPxMSK)
MSSP Shift register (SSPSR) – not directly accessible
SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and Status registers in I2C mode operation.
The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower six bits of the
SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxMSK holds the slave address
mask value used in address comparison. SSPxADD contains the slave device address when the MSSP is configured
in I2C Slave mode. When the MSSP is configured in Master mode, SSPxADD acts as the Baud Rate Generator
reload value.
DS40002195A-page 265
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MSSP - Master Synchronous Serial Port Module
SSPSR is the Shift register used for shifting data in or out. SSPxBUF is the Buffer register to which data bytes are
written to or read from. In receive operations, SSPSR and SSPxBUF together, create a double-buffered receiver.
When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During
transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR.
25.2.2 I2C Mode Operation
All MSSP I2C communication is byte oriented and shifted out MSb first. Eight SFR registers and two interrupt flags
interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the
module to communicate with other external I2C devices.
25.2.2.1 Definition of I2C Terminology
There is language and terminology in the description of I2C communication that have definitions specific to I2C. That
word usage is defined below and may be used in the rest of this document without explanation. This table was
adapted from the Philips/NXP I2C Specification.
TERM
Transmitter
Receiver
Master
Description
The device that shifts data out onto the bus.
The device that shifts data in from the bus.
The device that initiates a transfer, generates clock signals and terminates a transfer.
The device addressed by the master.
Slave
Multi-master
Arbitration
A bus with more than one device that can initiate data transfers.
Procedure to ensure that only one master at a time controls the bus. Winning arbitration
ensures that the message is not corrupted.
Synchronization
Idle
Procedure to synchronize the clocks of two or more devices on the bus.
No master is controlling the bus, and both SDA and SCL lines are high.
Any time one or more master devices are controlling the bus.
Active
Addressed Slave Slave device that has received a matching address and is actively being clocked by a master.
Matching Address Address byte that is clocked into a slave that matches the value stored in SSPxADD.
Write Request
Read Request
Slave receives a matching address with R/W bit clear, and is ready to clock in data.
Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of
the Slave. This data is the next and all following bytes until a Restart or Stop.
Clock Stretching When a device on the bus hold SCL low to stall communication.
Bus Collision
Any time the SDA line is sampled low by the module while it is outputting and expected high
state.
25.2.2.2 Byte Format
All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice versa, followed by
an Acknowledge sequence sent back. After the eighth falling edge of the SCL line, the device outputting data on the
SDA changes that pin to an input and reads the Acknowledge value on the next clock pulse.
The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on
the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus,
such as a Start or Stop condition.
25.2.2.3 SDA and SCL Pins
Selection of any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be open-drain. These pins must
be configured as inputs by setting the appropriate TRIS bits.
DS40002195A-page 266
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
Important:ꢀ Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These
functions are bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL input is
selected with the SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s
responsibility to make the selections so that both the input and the output for each function is on the same
pin.
25.2.2.4 SDA Hold Time
The hold time of the SDA pin is selected by the SDA Hold Time Selection (SDAHT) bit. Hold time is the time SDA is
held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may
help buses with large capacitance.
25.2.2.5 Clock Stretching
Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The
slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master
device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any
stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL.
The CKP bit is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL
line to go low and then hold it. Setting CKP will release SCL and allow more communication.
25.2.2.6 Arbitration
Each master device must monitor the bus for Start and Stop conditions. If the device detects that the bus is busy, it
cannot begin a new message until the bus returns to an Idle state.
However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the
process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that
it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop
transmitting on the SDA line.
For example, if one transmitter holds the SDA line to a logical one (lets SDA float) and a second transmitter holds it to
a logical zero (pulls SDA low), the result is that the SDA line will be low. The first transmitter then observes that the
level of the line is different than expected and concludes that another transmitter is communicating.
The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this
transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop
condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any
difference between the expected and actual levels on the SDA line continues with its original transmission. It can do
so without any complications, because so far, the transmission appears exactly as expected with no other transmitter
disturbing the message.
Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common.
25.2.2.7 Start Condition
The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high.
A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active
state. Figure 25-12 shows wave forms for Start and Stop conditions.
A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This
does not conform to the I2C Specification that states no bus collision can occur on a Start.
25.2.2.8 Stop Condition
A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high.
Important:ꢀ At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes
low then high again while the SCL line stays high, only the Start condition is detected.
DS40002195A-page 267
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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MSSP - Master Synchronous Serial Port Module
Figure 25-12.ꢀI2C Start and Stop Conditions
Rev. 30-000022A
4/3/2017
SDA
SCL
S
P
Change of
Data Allowed
Change of
Data Allowed
Start
Stop
Condition
Condition
25.2.2.9 Start/Stop Condition Interrupt Masking
The Start Condition Interrupt Enable (SCIE) and Stop Condition Interrupt Enable (PCIE) bits can enable the
generation of an interrupt in Slave modes that do not typically support this function. These bits will have no effect in
Slave modes where interrupt on Start and Stop detect are already enabled.
25.2.2.10 Restart Condition
A Restart condition is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the
bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all
slave logic and preparing it to clock in an address. The master may want to address the same or another slave.
Figure 25-13 shows the waveform for a Restart condition.
In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a
slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the
high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data.
Figure 25-13.ꢀI2C Restart Condition
Rev. 30-000023A
4/3/2017
Sr
Change of
Change of
Data Allowed
Data Allowed
Restart
Condition
25.2.2.11 Acknowledge Sequence
The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge sequence (ACK). It allows
receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control
of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA
line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more.
The result of an ACK is placed in the Acknowledge Status (ACKSTAT) bit.
The slave software, when the Address Hold Enable (AHEN) and Data Hold Enable (DHEN) bits are set, allows the
user to select the ACK value sent back to the transmitter. The Acknowledge Data (ACKDT) bit is set/cleared to
determine the response.
The slave hardware will generate an ACK response under most circumstances. However, if the BF bit or the Receive
Overflow Indicator (SSPOV) bit are set when a byte is received then the ACK will not be sent by the slave.
DS40002195A-page 268
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
When the module is addressed, after the eighth falling edge of SCL on the bus, the Acknowledge Time Status
(ACKTIM) bit is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM bit is only active
when either the AHEN bit or DHEN bit is enabled.
25.2.3 I2C Slave Mode Operation
The MSSP Slave mode operates in one of four modes selected by the MSSP Mode Select (SSPM) bits. The modes
can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some
additional overhead for handling the larger addresses.
Modes with Start and Stop condition interrupts operate the same as the other modes with SSPxIF additionally getting
set upon detection of a Start, Restart, or Stop condition.
25.2.3.1 Slave Mode Addresses
The SSPxADD register contains the Slave mode address. The first byte received after a Start or Restart condition is
compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register
and an interrupt is generated. If the value does not match, the module goes Idle and no indication is given to the
software that anything happened.
The SSPxMSK register affects the address matching process. See the “SSP Mask Register” section for more
information.
25.2.3.1.1 I2C Slave 7-bit Addressing Mode
In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address
match.
25.2.3.1.2 I2C Slave 10-bit Addressing Mode
In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8
are the two MSbs of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register.
After the acknowledge of the high byte the Update Address (UA) bit is set and SCL is held low until the user updates
SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low
address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL is held low until
SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures
the module is ready to receive the high address byte on the next communication.
A high and low address match as a write request is required at the start of all 10-bit addressing communication. A
transmission can be initiated by issuing a Restart once the slave is addressed and clocking in the high address with
the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is
only valid for a slave after it has received a complete high and low address byte match.
25.2.3.2 Clock Stretching
When a slave device has not completed processing data, it can delay the transfer of more data through the process
of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit,
indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the
SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the
SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue
communicating.
Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.
25.2.3.2.1 Normal Clock Stretching
Following an ACK if the R/W bit is set (a read request), the slave hardware will clear CKP. This allows the slave time
to update SSPxBUF with data to transfer to the master. If the Stretch Enable (SEN) bit is set, the slave hardware will
always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and
communication resumes.
25.2.3.2.2 10-bit Addressing Mode
In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is
stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD.
25.2.3.2.3 Byte NACKing
When the AHEN bit is set, CKP is cleared by hardware after the eighth falling edge of SCL for a received matching
address byte. When the DHEN bit is set, CKP is cleared after the eighth falling edge of SCL for received data.
DS40002195A-page 269
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it
wants to acknowledge (ACK) the received address or data, or not acknowledge (NACK) the address or data.
25.2.3.3 Clock Synchronization and the CKP bit
Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the
CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not
assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain
low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the
CKP bit will not violate the minimum high time requirement for SCL (see Figure 25-14).
Figure 25-14.ꢀClock Synchronization Timing
Rev. 30-000033A
4/3/2017
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA
SCL
DX
DX ‚ – 1
Master device
asserts clock
CKP
Master device
releases clock
WR
SSPxCON1
25.2.3.4 General Call Address Support
The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which
device will be the slave addressed by the master device. The exception is the General Call address that can address
all devices. When this address is used, all devices should, in theory, respond with an ACK.
The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the General Call
Enable (GCEN) bit is set, the slave module will automatically ACK the reception of this address regardless of the
value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is
generated and slave software can read SSPxBUF and respond. Figure 25-15 shows a general call reception
sequence.
Figure 25-15.ꢀSlave Mode General Call Address Sequence
Receiving Data
SDA
SCL
General Call Address
ACK
9
D7
1
D6
2
D5
3
D4
D3
D2
6
D1
7
D0
8
1
2
3
6
7
8
4
5
4
5
9
Start
SSPxIF
BF
Cleared by software
SSPxBUF is read
In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare
to receive the second byte as data, just as it would in 7-bit mode.
DS40002195A-page 270
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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MSSP - Master Synchronous Serial Port Module
If the AHEN bit is set, just as with any other address reception, the slave hardware will stretch the clock after the
eighth falling edge of SCL. The slave must then set its Acknowledge Sequence Enable (ACKEN) bit and release the
clock with communication progressing as it would normally.
25.2.3.5 SSP Mask Register
The MSSP Mask register (SSPxMSK) is available in I2C Slave mode as a mask for the value held in the SSPSR
register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making
the corresponding bit of the received address a “don’t care”.
This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard MSSP operation
until written with a mask value.
SSPxMSK is active during:
•
•
7-bit Address mode: address compare of A[7:1].
10-bit Address mode: address compare of A[7:0] only. The MSSP mask has no effect during the reception of the
first (high) byte of the address.
25.2.3.6 Slave Reception
When the R/W bit of a matching received address byte is clear, the R/W bit is cleared. The received address is
loaded into the SSPxBUF register and acknowledged.
When the overflow condition exists for a received address, a Not Acknowledge (NACK) is transmitted and the
Receive Overflow Indicator (SSPOV) bit is set. The Buffer Override Enable (BOEN) bit modifies this operation.
An MSSP interrupt is generated for each transferred data byte. The SSPxIF flag bit must be cleared by software.
When the SEN bit is set, SCL will be held low (clock stretch) following each received byte. The clock must be
released by setting the CKP bit, except sometimes in 10-bit mode. See “10-Bit Addressing Mode” for more details.
25.2.3.6.1 7-bit Addressing Reception
This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit
Addressing mode. Figure 25-16 and Figure 25-17 are used as a visual reference for this description.
This is a step by step process of what typically must be done to accomplish I2C communication.
1. Start condition detected.
2. The Start (S) bit is set; SSPxIF is set if the Start Condition Interrupt Enable (SCIE) bit is set.
3. Matching address with R/W bit clear is received.
4. The slave pulls SDA low, sending an ACK to the master, and sets SSPxIF bit.
5. Software clears the SSPxIF bit.
6. Software reads received address from SSPxBUF, clearing the BF flag.
7. If SEN = 1; Slave software sets the CKP bit to release the SCL line.
8. The master clocks out a data byte.
9. Slave drives SDA low, sending an ACK to the master, and sets SSPxIF bit.
10. Software clears SSPxIF.
11. Software reads the received byte from SSPxBUF, clearing BF.
12. Steps 8-12 are repeated for all received bytes from the master.
13. Master sends Stop condition, setting the Stop (P) bit, and the bus goes Idle.
DS40002195A-page 271
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-16.ꢀI2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)rotatethispage90
Rev. 30-000024A
4/10/2017
Bus Master sends
Stop condition
From Slave to Master
Receiving Address
Receiving Data
Receiving Data
ACK = 1
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
ACK
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
S
P
SSPxIF
BF
SSPxIF set on 9th
falling edge of
SCL
Cleared by software
Cleared by software
First byte
of data is
available
SSPxBUF is read
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
Figure 25-17.ꢀI2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)rotatethispage90
Rev. 30-000025A
4/3/2017
Bus Master sends
Stop condition
Receive Address
Receive Data
Receive Data
ACK
R/W=0
ACK
9
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
SEN
SEN
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
P
1
2
3
4
5
6
7
8
S
Clock is held low until CKP is set to ‘1’
SSPxIF
SSPxIF set on 9th
falling edge of SCL
Cleared by software
Cleared by software
SSPxBUF is read
BF
First byte
of data is
available
in SSPxBUF
SSPOV
SSPOV set because
SSPxBUF is still full.
ACK is not sent.
CKP
SCL is not held
low because
CKP is written to ‘1’ in software,
releasing SCL
CKP is written to ‘1’ in software,
releasing SCL
= 1
ACK
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
25.2.3.6.2 7-bit Reception with AHEN and DHEN
Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and
clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to
decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds
™
support for PMBus that was not present on previous versions of this module.
This list describes the steps that need to be taken by slave software to use these options for I2C communication.
Figure 25-18 displays a module using both address and data holding. Figure 25-19 includes the operation with the
SEN bit set.
1. The Start (S) bit is set; SSPxIF is set if SCIE is set.
2. Matching address with the R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling
edge of SCL.
3. Software clears the SSPxIF.
4. Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK.
5. Slave reads the address value from SSPxBUF, clearing the BF flag.
6. Slave transmits an ACK to the master by clearing ACKDT.
7. Slave releases the clock by setting CKP.
8. SSPxIF is set after an ACK, not after a NACK.
9. If SEN = 1, the slave hardware will stretch the clock after the ACK.
10. Slave clears SSPxIF.
Important:ꢀ SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching
and BF has been cleared. Only if a NACK is sent to the master is SSPxIF not set.
11. SSPxIF is set and CKP cleared after eighth falling edge of SCL for a received data byte.
12. Slave looks at the ACKTIM bit to determine the source of the interrupt.
13. Slave reads the received data from SSPxBUF, clearing BF.
14. Steps 7-14 are the same for each received data byte.
15. Communication is ended by either the slave sending a NACK, or the master sending a Stop condition. If a
Stop is sent and the Stop Condition Interrupt Enable (PCIE) bit is clear, the slave will only know by polling the
Stop (P) bit.
DS40002195A-page 274
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-18.ꢀI2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)rotatethispage90
Rev. 30-000026A
4/3/2017
Master sends
Stop condition
Master Releases SDA
to slave for ACK sequence
Receiving Address
Receiving Data
Received Data
ACK
SDA
SCL
ACK=1
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S
P
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
SSPxIF
If AHEN = 1:
SSPxIF is set
SSPxIF is set on
9th falling edge of
No interrupt
Cleared by software
after not ACK
from Slave
SCL, after ACK
BF
Address is
read from
Data is read from SSPxBUF
SSBUF
ACKDT
Slave software
clears ACKDT to
Slave software
sets ACKDT to
not ACK
ACK the received
byte
CKP
When AHEN=1:
CKP is cleared by hardware
and SCL is stretched
When DHEN=1:
CKP is cleared by
hardware on 8th falling
edge of SCL
CKP set by software,
SCL is released
ACKTIM
ACKTIM cleared by
hardware in 9th
rising edge of SCL
ACKTIM set by hardware
on 8th falling edge of SCL
ACKTIM set by hardware
on 8th falling edge of SCL
S
P
Figure 25-19.ꢀI2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)rotatethispage90
Rev. 30-000027A
4/3/2017
Master sends
Stop condition
Master releases
R/W = 0
SDA to slave for ACK sequence
ACK
Receiving Address
Receive Data
Receive Data
SDA
SCL
ACK
9
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
P
1
2
3
4
1
2
3
4
5
6
7
8
1
2
4
5
6
7
8
5
6
7
8
9
3
S
SSPxIF
No interrupt after
Cleared by software
if not ACK
from Slave
BF
Received
address is loaded into
SSPxBUF
Received data is
available on SSPxBUF
SSPxBUF can be
read any time before
next byte is loaded
ACKDT
Slave software clears
ACKDT to ACK
the received byte
Slave sends
not ACK
CKP
CKP is not cleared
if not ACK
When AHEN = 1;
When DHEN = 1;
Set by software,
release SCL
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
on the 8th falling edge
of SCL of a received
data byte, CKP is cleared
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
ACKTIM is cleared by hardware
on 9th rising edge of SCL
S
P
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MSSP - Master Synchronous Serial Port Module
25.2.3.6.3 Slave Mode 10-bit Address Reception
This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit
Addressing mode. Figure 25-20 shows a standard waveform for a slave receiver in 10-bit Addressing mode with
clock stretching enabled.
This is a step-by-step process of what must be done by the slave software to accomplish I2C communication.
1. Bus starts Idle.
2. Master sends Start condition; S bit is set; SSPxIF is set if SCIE is set.
3. Master sends matching high address with the R/W bit clear; the UA bit is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from SSPxBUF, clearing the BF flag.
7. Slave loads low address into SSPxADD, releasing SCL.
8. Master sends matching low address byte to the slave; UA bit is set.
Important:ꢀ Updates to the SSPxADD register are not allowed until after the ACK sequence.
9. Slave sends ACK and SSPxIF is set.
Important:ꢀ If the low address does not match, SSPxIF and UA are still set so that the slave
software can set SSPxADD back to the high address. BF is not set because there is no match. CKP
is unaffected.
10. Slave clears SSPxIF.
11. Slave reads the received matching address from SSPxBUF, clearing BF.
12. Slave loads high address into SSPxADD.
13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set.
14. If the SEN bit is set, CKP is cleared by hardware and the clock is stretched.
15. Slave clears SSPxIF.
16. Slave reads the received byte from SSPxBUF, clearing BF.
17. If SEN is set the slave software sets CKP to release the SCL.
18. Steps 13-17 repeat for each received byte.
19. Master sends Stop to end the transmission.
DS40002195A-page 277
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-20.ꢀI2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)rotatethispage90
Rev. 30-000030A
4/3/2017
Master sends
Stop condition
Receive Data
Receive Second Address Byte
Receive First Address Byte
Receive Data
SDA
0
ACK
A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
ACK
ACK
9
ACK
9
1
1
1
1
SCL
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
S
SCL is held low
while CKP =
0
SSPxIF
Set by hardware
on 9th falling edge
Cleared by software
BF
Data is read
from SSPxBUF
Receive address is
read from SSPxBUF
If address matches
SSPxADD it is loaded into
SSPxBUF
UA
Software updates SSPxADD
and releases SCL
When UA =
1;
SCL is held low
CKP
Set by software,
releasing SCL
When SEN =
CKP is cleared after
9th falling edge of received byte
1;
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
25.2.3.6.4 10-bit Addressing with Address or Data Hold
Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is
the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared
and SCL line is held low are the same. Figure 25-21 can be used as a reference of a slave in 10-bit addressing with
AHEN set.
Figure 25-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode.
DS40002195A-page 279
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-21.ꢀI2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0)rotatethispage90
Rev. 30-000031A
4/3/2017
Receive First Address Byte
Receive Second Address Byte
Receive Data
Receive Data
R/W = 0
SDA
SCL
1
1
1
1
0
A9 A8
ACK
9
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
ACK
9
1
2
3
4
5
6
7
8
UA
1
2
3
4
5
6
7
8
UA
1
2
3
4
5
6
7
8
9
1
2
S
SSPxIF
Set by hardware
on 9th falling edge
Cleared by software
Cleared by software
BF
ACKDT
UA
SSPxBUF can be
read anytime before
the next received byte
Received data
is read from
SSPxBUF
Slave software clears
ACKDT to ACK
the received byte
Update to SSPxADD is
not allowed until 9th
falling edge of SCL
Update of SSPxADD,
clears UA and releases
SCL
If when AHEN = 1;
CKP
on the 8th falling edge
of SCL of an address
byte, CKP is cleared
Set CKP with software
releases SCL
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
Figure 25-22.ꢀI2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)rotatethispage90
Rev. 30-000032A
4/3/2017
Master sends
Stop condition
Master sends
Restart event
Master sends
not ACK
Receiving Address
Receiving Second Address Byte
A7 A6 A5 A4 A3 A2 A1 A0
Transmitting Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
Receive First Address Byte
ACK = 1
R/W = 0
ACK
9
1
1
1
1
0
A9 A8
1
1
1
1
0
A9 A8
SDA
SCL
ACK
ACK
1
6
7
8
9
2
3
4
5
1
1
1
6
7
8
7
8
9
2
3
4
5
2
3
4
5
6
6
7
8
9
2
3
4
5
P
S
Sr
SSPxIF
BF
Set by hardware
Set by hardware
Cleared by software
SSPxBUF loaded
with received address
Received address is
read from SSPxBUF
Data to transmit is
loaded into SSPxBUF
UA
High address is loaded
back into SSPxADD
UA indicates SSPxADD
must be updated
After SSPxADD is
updated, UA is cleared
and SCL is released
CKP
When R/W = 1;
CKP is cleared on
Set by software
releases SCL
ACKSTAT
9th falling edge of SCL
Masters not ACK
is copied
R/W
D/A
R/W is copied from the
matching address byte
Indicates an address
has been received
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
25.2.3.7 Slave Transmission
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit is set. The received
address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit.
Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see “Clock Stretching” for more
details). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done
preparing the transmit data.
The transmit data must be loaded into the SSPxBUF register, which also loads the SSPSR register. Then the SCL pin
should be released by setting the CKP bit. The eight data bits are shifted out on the falling edge of the SCL input.
This ensures that the SDA signal is valid during the SCL high time.
The ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is
copied to the ACKSTAT bit. If ACKSTAT is set (NACK), then the data transfer is complete. In this case, when the
NACK is latched by the slave, the slave goes Idle and waits for another occurrence of a Start condition. If the SDA
line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be
released by setting bit CKP.
An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the
SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth
clock pulse.
25.2.3.7.1 Slave Mode Bus Collision
A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the
Slave Mode Bus Collision Detect Enable (SBCDE) bit is set, the Bus Collision Interrupt Flag (BCLxIF) bit of the PIRx
register is set. Once a bus collision is detected, the slave goes Idle and waits to be addressed again. User software
can use the BCLxIF bit to handle a slave bus collision.
25.2.3.7.2 7-bit Transmission
A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines
what software for a slave will need to do to accomplish a standard transmission. Figure 25-23 can be used as a
reference to this list.
1. Master sends a Start condition.
2. The Start (S) bit is set; SSPxIF is set if SCIE is set.
3. Matching address with R/W bit set is received by the Slave, setting SSPxIF bit.
4. Slave hardware generates an ACK and sets SSPxIF.
5. The SSPxIF bit is cleared by software.
6. Software reads the received address from SSPxBUF, clearing BF.
7. R/W is set so CKP was automatically cleared after the ACK.
8. The slave software loads the transmit data into SSPxBUF.
9. CKP bit is set by software, releasing SCL, allowing the master to clock the data out of the slave.
10. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT bit.
11. SSPxIF bit is cleared.
12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data.
Important:ꢀ
1.
2.
If the master ACKs then the clock will be stretched.
ACKSTAT is the only bit updated on the rising edge of the ninth SCL clock instead of the
falling edge.
13. Steps 9-13 are repeated for each transmitted byte.
14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set.
15. The master sends a Restart condition or a Stop.
DS40002195A-page 282
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-23.ꢀI2C Slave, 7-bit Address, Transmission (AHEN = 0)rotatethispage90
Rev. 30-000028A
4/3/2017
Master sends
Stop condition
ACK
9
Receiving Address
Automatic
Transmitting Data
Automatic
Transmitting Data
R/W = 1
ACK
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
P
S
SSPxIF
BF
Cleared by software
BF is automatically
cleared after 8th falling
edge of SCL
Data to transmit is
loaded into SSPxBUF
Received address
is read from SSPxBUF
CKP
CKP is not
held for not
ACK
When R/W is set
SCL is always
held low after 9th SCL
Set by software
falling edge
ACKSTAT
Masters not ACK
is copied to
ACKSTAT
R/W
D/A
R/W is copied from the
matching address byte
Indicates an address
has been received
S
P
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
25.2.3.7.3 7-bit Transmission with Address Hold Enabled
Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling edge of a
received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt
is set.
Figure 25-24 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit is set; SSPxIF is set if SCIE is set.
3. Master sends matching address with the R/W bit set. After the eighth falling edge of the SCL line the CKP bit
is cleared and SSPxIF interrupt is generated.
4. Slave software clears SSPxIF.
5. Slave software reads the ACKTIM, R/W, and D/A bits to determine the source of the interrupt.
6. Slave reads the address value from the SSPxBUF register, clearing the BF bit.
7. Slave software decides from this information if it wishes to ACK or NACK and sets the ACKDT bit accordingly.
8. Slave software sets the CKP bit, releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into SSPxBUF, setting the BF bit.
Important:ꢀ SSPxBUF cannot be loaded until after the ACK.
13. Slave software sets the CKP bit, releasing the clock.
14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the ACKSTAT bit.
16. Steps 10-15 are repeated for each byte transmitted to the master from the slave.
17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the
communication.
Important:ꢀ Master must send a not ACK on the last byte to ensure that the slave releases the SCL
line to receive a Stop.
DS40002195A-page 284
Preliminary Datasheet
© 2020 Microchip Technology Inc.
Figure 25-24.ꢀI2C Slave, 7-bit Address, Transmission (AHEN = 1)rotatethispage90
Rev. 30-00029A
4/10/2017
Master sends
Stop condition
Master releases SDA
to slave for ACK sequence
Receiving Address
Automatic
Transmitting Data
Automatic
ACK
Transmitting Data
R/W = 1
ACK
9
SDA
SCL
ACK
9
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SSPxIF
BF
Cleared by software
BF is automatically
cleared after 8th falling
edge of SCL
Received address
Data to transmit is
loaded into SSPxBUF
is read from SSPxBUF
ACKDT
Slave clears
ACKDT to ACK
address
ACKSTAT
CKP
Master’s ACK
response is copied
to SSPxSTAT
When AHEN = 1;
CKP is cleared by hardware
after receiving matching
address.
CKP not cleared
after not ACK
When R/W = 1;
CKP is always
cleared after ACK
Set by software,
releases SCL
ACKTIM
ACKTIM is cleared
on 9th rising edge of SCL
ACKTIM is set on 8th falling
edge of SCL
R/W
D/A
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
25.2.4 I2C Master Mode
Master mode is enabled by configuring the appropriate SSPM bits and setting the SSPEN bit. In Master mode, the
SDA and SCL pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS
controls when necessary to drive the pins low.
Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The
Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus
may be taken when the P bit is set, or the bus is Idle.
In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop condition
detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done
by the user software directly manipulating the SDA and SCL lines.
The following events will cause the MSSP Interrupt Flag bit (SSPxIF) to be set (MSSP interrupt, if enabled):
•
•
•
•
•
Start condition detected.
Stop condition detected.
Data transfer byte transmitted/received.
Acknowledge transmitted/received.
Repeated Start generated.
Important:ꢀ
1. The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For
instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF
register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF
will not be written to and the Write Collision Detect (WCOL) bit will be set, indicating that a write to
the SSPxBUF did not occur.
2. Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the
SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware
clears the control bit.
25.2.4.1 I2C Master Mode Operation
The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with
a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the
next serial transfer, the I2C bus will not be released.
In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte
transmitted contains the slave address of the receiving device (7 bits) and the R/W bit. In this case, the R/W bit will
be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is
received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer.
In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and
the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed
by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is
received eight bits at a time. After each byte is received, an Acknowledge sequence is transmitted. Start and Stop
conditions indicate the beginning and end of transmission.
A Baud Rate Generator is used to set the clock frequency output on SCL. See “Baud Rate Generator” for more
details.
25.2.4.1.1 Clock Arbitration
Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the
SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is
suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud
Rate Generator is reloaded with the contents of SSPxADD and begins counting. This ensures that the SCL high time
will always be at least one BRG rollover count in the event that the clock is held low by an external device as shown
in Figure 25-25.
DS40002195A-page 286
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
Figure 25-25.ꢀBaud Rate Generator Timing with Clock Arbitration
Rev. 30-000035A
4/3/2017
SDA
DX
DX ‚ – 1
SCL deasserted but slave holds
SCL low (clock arbitration)
SCL allowed to transition high
SCL
BRG decrements on
Q2 and Q4 cycles
BRG
Value
03h
02h
01h
00h (hold off)
03h
02h
SCL is sampled high, reload takes
place and BRG starts its count
BRG
Reload
25.2.4.1.2 WCOL Status Flag
If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the Write
Collision Detect (WCOL) bit is set and the contents of the buffer are unchanged (the write does not occur). Any time
the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not Idle.
Important:ꢀ Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is
disabled until the Start condition is complete.
25.2.4.1.3 I2C Master Mode Start Condition Timing
To initiate a Start condition (see Figure 25-26), the user sets the Start Condition Enable (SEN) bit. If the SDA and
SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count.
If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
The action of the SDA being driven low while SCL is high is the Start condition and causes the Start (S) bit to be set.
Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the
Baud Rate Generator times out (TBRG), the SEN bit will be automatically cleared by hardware; the Baud Rate
Generator is suspended, leaving the SDA line held low and the Start condition is complete.
Important:ꢀ
1. If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if
during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus
collision occurs, the Bus Collision Interrupt Flag (BCLxIF) is set, the Start condition is aborted and
the I2C module is reset into its Idle state.
2. The Philips I2C Specification states that a bus collision cannot occur on a Start.
DS40002195A-page 287
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
Figure 25-26.ꢀFirst Start Bit Timing
Set Sꢀꢁbit
Write to SEN bit
Write to SSPxBUF
TBRG
SDA
TBRG
1st bit
2nd bit
SDA, SCL
sampled highꢀ
TBRG
TBRG
SCL
25.2.4.1.4 I2C Master Mode Repeated Start Condition Timing
A Repeated Start condition (see Figure 25-27) occurs when the Repeated Start Condition Enable (RSEN) bit is
programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is
asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA
pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out,
if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate
Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then
followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this,
the RSEN bit will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin
held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit will be set. The SSPxIF bit will
not be set until the Baud Rate Generator has timed out.
Important:ꢀ
1. If RSEN is programmed while any other event is in progress, it will not take effect.
2. A bus collision during the Repeated Start condition occurs if:
– SDA is sampled low when SCL goes from low-to-high.
– SCL goes low before SDA is asserted low. This may indicate that another master is attempting
to transmit a data ‘1’.
DS40002195A-page 288
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
Figure 25-27.ꢀRepeated Start Condition Waveform
Rev. 30-000037A
4/10/2017
S bit set by hardware
Write to SSPxCON2
occurs here
SDA = 1,
At completion of Start bit,
hardware clears the RSEN bit
and sets SSPxIF
SDA = 1,
SCL = 1
SCL (no change)
TBRG
TBRG
TBRG
1st bit
SDA
SCL
Write to SSPxBUF occurs here
TBRG
Sr
Repeated Start
TBRG
25.2.4.1.5 Acknowledge Sequence Timing
An Acknowledge sequence (see Figure 25-28) is enabled by setting the Acknowledge Sequence Enable (ACKEN)
bit. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge Data (ACKDT) bit are
presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If
not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then
counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high
(clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the
ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle
mode.
Figure 25-28.ꢀAcknowledge Sequence Waveform
Rev. 30-000040A
4/3/2017
Acknowledge sequence starts here,
ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG
9
TBRG
SDA
SCL
D0
ACK
8
SSPxIF
Cleared in
software
SSPxIF set at the end
of Acknowledge sequence
SSPxIF set at
the end of receive
Cleared in
software
Note: TBRG = one Baud Rate Generator period.
Acknowledge Write Collision
If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write does not occur).
25.2.4.1.6 Stop Condition Timing
A Stop condition (see Figure 25-29) is asserted on the SDA pin at the end of a receive/transmit by setting the Stop
Condition Enable (PEN) bit. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth
clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud
Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be
brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the
SDA pin is sampled high while SCL is high, the P bit is set. One TBRG later, the PEN bit is cleared and the SSPxIF bit
is set.
DS40002195A-page 289
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
Figure 25-29.ꢀStop Condition in Receive or Transmit Mode
Set PEN bit
SCL
SDA
Pꢀꢁbit set
9th falling SCL
edge
PEN bit cleared;
SSPxIF set
ACK/NACK
TBRG
TBRG
TBRG
Write Collision on Stop
If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of
the buffer are unchanged (the write does not occur).
25.2.4.1.7 Sleep Operation
While in Sleep mode, the I2C slave module can receive addresses or data and when an address match or complete
byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled).
25.2.4.1.8 Effects of a Reset
A Reset disables the MSSP module and terminates the current transfer.
25.2.4.2 I2C Master Mode Transmission
Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a
value to the SSPxBUF register. This action will set the Buffer Full Status (BF) bit and allow the Baud Rate Generator
to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after
the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should
be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the
SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth
bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows
the slave device being addressed to respond with an ACK sequence during the ninth bit time if an address match
occurred, or if data was received properly. The status of ACK is written into the Acknowledge Status (ACKSTAT) bit
on the rising edge of the ninth clock. If the master receives an ACK, the ACKSTAT bit is cleared. If a NACK is
received, ACKSTAT is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is
suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (see Figure
25-30).
After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven
address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA
pin, allowing the slave to respond with an ACK. On the falling edge of the ninth clock, the master will sample the SDA
pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT bit.
Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and
the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing
SDA to float.
25.2.4.2.1 BF Status Flag
In Transmit mode, the Buffer Full Status (BF) bit is set when the CPU writes to SSPxBUF, and is cleared when all
eight bits are shifted out.
25.2.4.2.2 WCOL Status Flag
If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte),
the Write Collision Detect (WCOL) bit is set and the contents of the buffer are unchanged (the write does not occur).
DS40002195A-page 290
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
MSSP - Master Synchronous Serial Port Module
The WCOL bit must be cleared by software before the next transmission.
25.2.4.2.3 ACKSTAT Status Flag
In Transmit mode, the Acknowledge Status (ACKSTAT) bit is cleared when the slave has sent an Acknowledge (ACK
= 0), and is set when the slave issues a NACK. A slave sends an ACK when it has recognized its address (including
a General Call), or when the slave has properly received its data.
25.2.4.2.4 Typical Transmit Sequence:
1. The Master generates a Start condition by setting the SEN bit.
2. SSPxIF is set by hardware on completion of the Start.
3. SSPxIF is cleared by software.
4. The MSSP module will wait the required start time before any other operation takes place.
5. Software loads the SSPxBUF with the slave address and the R/W bit. In Master Transmit mode, the R/W value
is zero.
6. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as
SSPxBUF is written to.
7. The MSSP module shifts in the ACK value from the slave device and writes its into the ACKSTAT bit.
8. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit.
9. Software loads the SSPxBUF with eight bits of data.
10. Data is shifted out the SDA pin until all eight bits are transmitted.
11. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit.
12. Steps 8-11 are repeated for all transmitted data bytes.
13. The user generates a Stop or Restart condition by setting the PEN or RSEN bits, respectively. An Interrupt is
generated once the Stop/Restart condition is complete.
Figure 25-30.ꢀI2C Master Mode Waveform (Transmission, 7-bit Address)
NACK,
ACKSTAT = 1
Set SEN bit
From slave,
ACKSTAT = 0
R/W = 0
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
SCL stretched while
SDA
SCL
ACK
SSPxBUF loaded with
address and R/W bit
CPU responds to
SSPxIF
Cleared by
software
Cleared by
software
SSPxIF
BF
Cleared by
software
Cleared by
hardware
Cleared by
hardware
SEN
PEN
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MSSP - Master Synchronous Serial Port Module
Figure 25-31.ꢀI2C Master Mode Waveform (Transmission, 10-bit Address)
From slave,
ACKSTAT = 0
From slave,
ACKSTAT = 0
NACK,
ACKSTAT = 1
Set SEN bit
R/W = 0
Address High byte
Address Low byte
A7 A6 A5 A4 A3 A2 A1 A0
1
1
1
1
1
0
A9 A8
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
ACK
ACK
9
SSPxBUF loaded with
address and R/W bit
SCL stretched while
CPU responds to
SSPxIF
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
Cleared by
software
Cleared by
software
Cleared by
software
Cleared by
software
SSPxIF
BF
Cleared by
hardware
Cleared by
hardware
Cleared by
hardware
SEN
PEN set by software
PEN
Cleared by
hardware
25.2.4.3 I2C Master Mode Reception
Master mode reception (see Figure 25-32) is enabled by setting the Receive Enable (RCEN) bit.
Important:ꢀ The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be
disregarded.
The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-
high) and data is shifted into the SSPxSR. After the falling edge of the eighth clock all the following events occur:
•
•
•
•
•
•
RCEN is automatically cleared by hardware.
The contents of the SSPxSR are loaded into the SSPxBUF.
The BF flag bit is set.
The SSPxIF flag bit is set.
The Baud Rate Generator is suspended from counting.
The SCL pin is held low.
The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is
automatically cleared. The Master can then send an Acknowledge sequence at the end of reception by setting the
Acknowledge Sequence Enable (ACKEN) bit.
25.2.4.3.1 BF Status Flag
In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is
cleared when the SSPxBUF register is read.
25.2.4.3.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight bits are received into SSPxSR while the BF flag bit is already
set from a previous reception.
25.2.4.3.3 WCOL Status Flag
If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPxSR is still shifting in a data byte), the
WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).
25.2.4.3.4 Typical Receive Sequence:
1. The Master generates a Start condition by setting the SEN bit.
2. SSPxIF is set by hardware on completion of the Start.
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MSSP - Master Synchronous Serial Port Module
3. SSPxIF is cleared by software.
4. Software writes SSPxBUF with the slave address to transmit and the R/W bit set.
5. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as
SSPxBUF is written to.
6. The MSSP module shifts in the ACK value from the slave device and writes it into the ACKSTAT bit.
7. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit.
8. Software sets the RCEN bit and the master clocks in a byte from the slave.
9. After the eighth falling edge of SCL, SSPxIF and BF are set.
10. Master clears SSPxIF and reads the received byte from SSPxBUF, which clears BF.
11. Master clears the ACKDT bit and initiates the ACK sequence by setting the ACKEN bit.
12. Master’s ACK is clocked out to the slave and SSPxIF is set.
13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte from the slave.
15. Master sends a NACK or Stop to end communication.
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Figure 25-32.ꢀI2C Master Mode Waveform (Reception, 7-bit Address)rotatethispage90
NACK (from
master)
ACK (from
master)
Stop
R/W
Start
Hardware
sets P
A7 A6 A5 A4 A3 A2 A1 1
D7D6D5D4D3D2D1D0
D7D6D5D4D3D2D1D0
SDA
7-bit address
ACK (from slave)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
Hardware sets SSPxIF
on completion of ACK
Hardware sets SSPxIF
on completion of Start
Master receives
full byte
Cleared by software
SSPxIF
ACKDT
BF
Master s ACK
copied from ACKDT
Master s NACK
copied from ACKDT
Master receives
full byte
Cleared by
hardware
Write to SSPxBUF
Software reads SSPxBUF,
hardware clears BF
Software sets RCEN =
Master receiver
Cleared by
hardware
Cleared by
hardware
Software set
RCEN
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MSSP - Master Synchronous Serial Port Module
Figure 25-33.ꢀI2C Master Mode Waveform (Reception, 10-bit Address)
NACK
(from
master)
R/W
0 A9 A8 1
High address
Stop
R/W
Restart
ACK (from slave)
SDA
SCL
1
1
1
1
0 A9 A8 0
A7 A6 A5 A4 A3 A2 A1 A0
1
1
1
1
D7D6D5D4D3D2D1D0
ACK (from slave)
High address
Low address
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SSPxIF
Cleared by software
Software
reads
Hardware set
SSPxBUF
Byte loaded into
SSPxBUF
BF
Master receives byte
Cleared by
hardware
Software sets RCEN = Master as receiver
Cleared by
hardware
RCEN
ACKSTAT
Slave s ACK copied
to ACKSTAT
25.2.5 Multi-Master Mode
In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the
determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP
module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P
bits cleared. When the bus is busy, enabling the MSSP interrupt will generate an interrupt when the Stop condition
occurs.
In Multi-Master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected
output level. This check is performed by hardware with the result placed in the BCLxIF bit.
The states where arbitration can be lost are:
•
•
•
•
•
Address Transfer
Data Transfer
A Start Condition
A Repeated Start Condition
An Acknowledge Condition
25.2.5.1 Multi-Master Communication, Bus Collision and Bus Arbitration
Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA
pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master
asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data
sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt
Flag (BCLxIF) and reset the I2C port to its Idle state (see Figure 25-34).
If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the
SDA and SCL lines are deasserted, and the SSPxBUF can be written to. When software services the Bus Collision
Interrupt Service Routine, and if the I2C bus is free, software can resume communication by asserting a Start
condition.
If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the
condition is aborted, the SDA and SCL lines are deasserted, and the respective control bits in the SSPxCON2
register are cleared. When software services the bus collision Interrupt Service Routine, and if the I2C bus is free,
software can resume communication by asserting a Start condition.
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MSSP - Master Synchronous Serial Port Module
The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set.
A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left
off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination
of when the bus is free. Control of the I2C bus can be taken when the P bit is set, or the bus is Idle and the S and P
bits are cleared.
Figure 25-34.ꢀBus Collision Timing for Transmit and Acknowledge
Rev. 30-000042A
4/3/2017
Sample SDA. While SCL is high,
data does not match what is driven
by the master.
Data changes
while SCL = 0
SDA line pulled low
by another source
Bus collision has occurred.
SDA released
by master
SDA
SCL
Set bus collision
interrupt (BCLxIF)
BCLxIF
25.2.5.1.1 Bus Collision During a Start Condition
During a Start condition, a bus collision occurs if:
1. SDA or SCL are sampled low at the beginning of the Start condition (see Figure 25-35).
2. SCL is sampled low before SDA is asserted low (see Figure 25-36).
During a Start condition, both the SDA and the SCL pins are monitored.
If the SDA pin is already low, or the SCL pin is already low, then all of the following occur:
•
•
•
the Start condition is aborted,
the BCLxIF flag is set and
the MSSP module is reset to its Idle state (see Figure 25-35).
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MSSP - Master Synchronous Serial Port Module
Figure 25-35.ꢀBus Collision During Start Condition (SDA Only)
Rev. 30-000043A
4/3/2017
SDA goes low before the SEN bit is set.
Set BCLxIF,
S bit and SSPxIF set because
SDA = 0, SCL = 1.
SDA
SCL
SEN
Set SEN, enable Start
condition if SDA = 1, SCL = 1
SEN cleared automatically because of bus collision.
SSPx module reset into Idle state.
SDA sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
SDA = 0, SCL = 1.
BCLxIF
SSPxIF and BCLxIF are
cleared by software
S
SSPxIF
SSPxIF and BCLxIF are
cleared by software
The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud
Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs
because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition.
Figure 25-36.ꢀBus Collision During Start Condition (SCL = 0)
Rev. 30-000044A
4/3/2017
SDA = 0, SCL = 1
TBRG
TBRG
SDA
SCL
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
SCL = 0before SDA = 0,
bus collision occurs. Set BCLxIF.
SCL = 0before BRG time-out,
bus collision occurs. Set BCLxIF.
BCLxIF
Interrupt cleared
by software
S
’0’
’0’
’0’
’0’
SSPxIF
If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (see Figure
25-37). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The
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MSSP - Master Synchronous Serial Port Module
Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a
bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low.
Figure 25-37.ꢀBRG Reset Due to SDA Arbitration During Start Condition
Rev. 30-000045A
4/10/2017
0
SDA = , SCL = 1
Set S
Set SSPxIF
Less than TBRG
TBRG
SDA pulled low by other master.
Reset BRG and assert SDA.
SDA
SCL
S
SCL pulled low after BRG
time out
-
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
’0’
BCLxIF
S
SSPxIF
Interrupts cleared
by software
SDA = 0, SCL = 1,
set SSPxIF
Important:ꢀ The reason that a bus collision is not a factor during a Start condition is that no two bus
masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA
before the other. This condition does not cause a bus collision because the two masters must be allowed
to arbitrate the first address following the Start condition. If the address is the same, arbitration must be
allowed to continue into the data portion, Repeated Start or Stop conditions.
25.2.5.1.2 Bus Collision During a Repeated Start Condition
During a Repeated Start condition, a bus collision occurs if:
1. A low level is sampled on SDA when SCL goes from low level to high level (see Figure 25-38).
2. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’
(see Figure 25-39).
When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down
to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled.
If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, see Figure 25-38).
If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG
times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
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MSSP - Master Synchronous Serial Port Module
Figure 25-38.ꢀBus Collision During a Repeated Start Condition (Case 1)
Rev. 30-000046A
4/3/2017
SDA
SCL
Sample SDA when SCL goes high.
0
If SDA = , set BCLxIF and release SDA and SCL.
RSEN
BCLxIF
Cleared by software
’0’
S
’0’
SSPxIF
If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision
occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition (see
Figure 25-39).
If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is
reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven
low and the Repeated Start condition is complete.
Figure 25-39.ꢀBus Collision During Repeated Start Condition (Case 2)
Rev. 30-000047A
4/3/2017
TBRG
TBRG
SDA
SCL
SCL goes low before SDA,
set BCLxIF. Release SDA and SCL.
BCLxIF
RSEN
Interrupt cleared
by software
’0’
S
SSPxIF
25.2.5.1.3 Bus Collision During a Stop Condition
Bus collision occurs during a Stop condition if:
1. After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed
out (see Figure 25-40).
2. After the SCL pin is deasserted, SCL is sampled low before SDA goes high (see Figure 25-41).
The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When
the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to
zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to
another master attempting to drive a data ‘0’ (see Figure 25-40). If the SCL pin is sampled low before SDA is allowed
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MSSP - Master Synchronous Serial Port Module
to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (see Figure
25-41).
Figure 25-40.ꢀBus Collision During a Stop Condition (Case 1)
Rev. 30-000048A
4/3/2017
SDA sampled
low after TBRG,
set BCLxIF
TBRG
TBRG
TBRG
SDA
SDA asserted low
SCL
PEN
BCLxIF
P
’0’
’0’
SSPxIF
Figure 25-41.ꢀBus Collision During a Stop Condition (Case 2)
Rev. 30-000049A
4/3/2017
TBRG
TBRG
TBRG
SDA
SCL goes low before SDA goes high,
set BCLxIF
Assert SDA
SCL
PEN
BCLxIF
P
’0’
’0’
SSPxIF
25.3
Baud Rate Generator
The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The
Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the
Baud Rate Generator will automatically begin counting down. Example 25-1 shows how the value for SSPxADD is
calculated.
Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain
in its last state.
An internal signal “Reload”, shown in Figure 25-42, triggers the value from SSPxADD to be loaded into the BRG
counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is
asserted depends on the mode in which the MSSP is being operated.
Table 25-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD.
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MSSP - Master Synchronous Serial Port Module
Example 25-1.ꢀMSSP Baud Rate Generator Frequency Equation
ꢞ
ꢊꢋꢌ
ꢞ
=
ꢌꢖꢊꢌꢡ
4 × ꢋꢋꢀꢔꢢꢙꢙ + 1
Figure 25-42.ꢀBaud Rate Generator Block Diagram
Rev. 30-000050A
4/3/2017
SSPM[3:0]
SSPxADD[7:0]
SSPM[3:0]
SCL
Reload
Control
Reload
BRG Down Counter
SSPCLK
FOSC/2
Important:ꢀ Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate
Generator for I2C. This is an implementation limitation.
Table 25-1.ꢀMSSP Clock Rate w/BRG
FCLOCK
(2 Rollovers of BRG)
FOSC
FCY
BRG Value
32 MHz
32 MHz
32 MHz
16 MHz
16 MHz
16 MHz
4 MHz
8 MHz
8 MHz
8 MHz
4 MHz
4 MHz
4 MHz
1 MHz
13h
19h
4Fh
09h
0Ch
27h
09h
400 kHz
308 kHz
100 kHz
400 kHz
308 kHz
100 kHz
100 kHz
Note:ꢀ Refer to the I/O port electrical specifications in the “Electrical Specifications” chapter, Internal Oscillator
Parameters, to ensure the system is designed to support all requirements.
25.4
Register Definitions: MSSP Control
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MSSP - Master Synchronous Serial Port Module
25.4.1 SSPxBUF
Name:ꢀ
SSPxBUF
Address:ꢀ 0x018C
MSSP Data Buffer Register
Bit
7
6
5
4
3
2
1
0
BUF[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – BUF[7:0]ꢀMSSP Input and Output Data Buffer bits
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MSSP - Master Synchronous Serial Port Module
25.4.2 SSPxADD
Name:ꢀ
SSPxADD
Address:ꢀ 0x018D
MSSP Baud Rate Divider and Address Register
Bit
7
6
5
4
3
2
1
0
ADD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADD[7:0]
•
•
SPI and I2C Master: Baud rate divider
I2C Slave: Address bits
Value
11111111
-
Mode
SPI and I2C Master
Description
Baud rate divider. SCK/SCL pin clock period = ((n + 1) * 4)/FOSC. Values
less than 3 are not valid.
00000011
xxxxx11x
-
I2C 10-bit Slave MS
Address
Bits [7:3] and Bit 0 are not used and are don’t care. Bits [2:1] are bits [9:8]
of the 10-bit Slave Most Significant Address
xxxxx00x
11111111
-
I2C 10-bit Slave LS
Address
Bits [7:0] of 10-Bit Slave Least Significant Address
00000000
1111111x
-
I2C 7-bit Slave
Bit 0 is not used and is don’t care. Bits [7:1] are the 7-bit Slave Address
0000000x
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MSSP - Master Synchronous Serial Port Module
25.4.3 SSPxMSK
Name:ꢀ
SSPxMSK
Address:ꢀ 0x018E
MSSP Address Mask Register
Bit
7
6
5
4
MSK[6:0]
R/W
3
2
1
0
MSK0
R/W
1
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
1
Bits 7:1 – MSK[6:0]ꢀMask bits
Value
1
0
Mode
Description
I2C Slave The received address bit n is compared to SSPxADD bit n to detect I2C address match
I2C Slave The received address bit n is not used to detect I2C address match
Bit 0 – MSK0
Mask bit for I2C 10-bit Slave mode
Value
1
Mode
Description
I2C 10-bit Slave The received address bit 0 is compared to SSPxADD bit 0 to detect I2C address
match
I2C 10-bit Slave The received address bit 0 is not used to detect I2C address match
SPI or I2C 7-bit Don’t care
0
x
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MSSP - Master Synchronous Serial Port Module
25.4.4 SSPxSTAT
Name:ꢀ
SSPxSTAT
Address:ꢀ 0x018F
MSSP Status Register
Bit
7
6
5
D/A
R
4
P
R
0
3
S
R
0
2
R/W
R
1
UA
R
0
BF
R
SMP
R/W
0
CKE
R/W
0
Access
Reset
0
0
0
0
Bit 7 – SMPꢀSlew Rate Control bit
Value
Mode
Description
1
0
0
1
0
SPI Master
SPI Master
SPI Slave
I2C
Input data is sampled at the end of data output time
Input data is sampled at the middle of data output time
Keep this bit cleared in SPI Slave mode
Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz)
Slew rate control is enabled for High-Speed mode (400 kHz)
I2C
Bit 6 – CKEꢀ SPI: Clock Select bit(4) I2C: SMBus Select bit
Value
Mode
SPI
SPI
I2C
Description
1
0
1
0
Transmit occurs on the transition from active to Idle clock state
Transmit occurs on the transition from Idle to active clock state
Enables SMBus-specific inputs
I2C
Disables SMBus-specific inputs
Bit 5 – D/A
Data/Address bit
Value
Mode
Description
Reserved
SPI or I2C Master
x
1
0
I2C Slave
I2C Slave
Indicates that the last byte received or transmitted was data
Indicates that the last byte received or transmitted was address
Bit 4 – P
Stop bit(1)
Value
Mode
SPI
I2C
I2C
Description
Reserved
Stop bit was detected last
Stop bit was not detected last
x
1
0
Bit 3 – S
Start bit(1)
Value
Mode
SPI
I2C
I2C
Description
Reserved
Start bit was detected last
Start bit was not detected last
x
1
0
Bit 2 – R/W
Read/Write Information bit(2,3)
Value
Mode
SPI
I2C Slave
I2C Slave
I2C Master
I2C Master
Description
Reserved
Read
x
1
0
1
0
Write
Transmit is in progress
Transmit is not in progress
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MSSP - Master Synchronous Serial Port Module
Bit 1 – UAꢀUpdate Address bit (10-Bit Slave mode only)
Value
Mode
Description
x
1
0
All other modes Reserved
I2C 10-bit Slave Indicates that the user needs to update the address in the SSPxADD register
I2C 10-bit Slave Address does not need to be updated
Bit 0 – BF
Buffer Full Status bit(5)
Value
Mode
Description
I2C Transmit
Character written to SSPxBUF has not been sent
SSPxBUF is ready for next character
Received character in SSPxBUF has not been read
Received character in SSPxBUF has been read
1
0
1
0
I2C Transmit
SPI and I2C Receive
SPI and I2C Receive
Note:ꢀ
1. This bit is cleared on Reset and when SSPEN is cleared.
2. In I2C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid
from the address match to the next Start bit, Stop bit or not ACK bit.
3. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode.
4. Polarity of clock state is set by the CKP bit.
5. I2C receive status does not include ACK and Stop bits.
DS40002195A-page 306
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MSSP - Master Synchronous Serial Port Module
25.4.5 SSPxCON1
Name:ꢀ
SSPxCON1
Address:ꢀ 0x0190
MSSP Control Register 1
Bit
7
6
5
SSPEN
R/W
0
4
3
2
1
0
WCOL
R/W/HS
0
SSPOV
R/W/HS
0
CKP
R/W
0
SSPM[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7 – WCOL
Write Collision Detect bit
Value
Mode
Description
1
SPI
A write to the SSPxBUF register was attempted while the previous byte was
still transmitting (must be cleared by software)
I2C Master transmit
I2C Slave transmit
A write to the SSPxBUF register was attempted while the I2C conditions
were not valid for a transmission to be started (must be cleared by software)
The SSPxBUF register is written while it is still transmitting the previous
word (must be cleared in software)
1
1
0
x
SPI or I2C Master or
Slave transmit
Master or Slave receive Don’t care
No collision
Bit 6 – SSPOV
Receive Overflow Indicator bit(1)
Value
Mode
Description
1
SPI Slave
A byte is received while the SSPxBUF register is still holding the previous
byte. The user must read SSPxBUF, even if only transmitting data, to avoid
setting overflow. (must be cleared in software)
A byte is received while the SSPxBUF register is still holding the previous
byte (must be cleared in software)
I2C Receive
1
SPI Slave or I2C Receive No overflow
SPI Master or I2C Master Don’t care
transmit
0
x
Bit 5 – SSPEN
Master Synchronous Serial Port Enable bit.(2)
Value
Mode Description
1
SPI
Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be made with the
PPS controls. Each signal must be configured with the corresponding TRIS control to the
direction appropriate for the mode selected.
Enables the serial port. The SDAx and SCLx pin selections must be made with the PPS
controls. Since both signals are bidirectional the PPS input pin and PPS output pin selections
must be made that specify the same pin. Both pins must be configured as inputs with the
corresponding TRIS controls.
I2C
1
0
All
Disables serial port and configures these pins as I/O PORT pins
Bit 4 – CKP
SCK Release Control bit
Value
Mode
Description
1
0
1
0
x
SPI
SPI
I2C Slave
I2C Slave
I2C Master
Idle state for the clock is a high level
Idle state for the clock is a low level
Releases clock
Holds clock low (clock stretch), used to ensure data setup time
Unused in this mode
DS40002195A-page 307
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MSSP - Master Synchronous Serial Port Module
Bits 3:0 – SSPM[3:0]
Master Synchronous Serial Port Mode Select bits(4)
Value
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Description
I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled
I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled
Reserved - do not use
Reserved - do not use
I2C Firmware Controlled Master mode (slave Idle)
SPI Master mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3)
Reserved - do not use
I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1))
I2C Slave mode: 10-bit address
I2C Slave mode: 7-bit address
SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled
SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled
SPI Master mode: Clock = TMR2 output/2
SPI Master mode: Clock = FOSC/64
SPI Master mode: Clock = FOSC/16
SPI Master mode: Clock = FOSC/4
Note:ꢀ
1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to
the SSPxBUF register.
2. When enabled, these pins must be properly configured as inputs or outputs.
3. SSPxADD = 0is not supported.
4. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
DS40002195A-page 308
Preliminary Datasheet
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MSSP - Master Synchronous Serial Port Module
25.4.6 SSPxCON2
Name:ꢀ
SSPxCON2
Address:ꢀ 0x0191
MSSP Control Register 2
Control Register for I2C Operation Only
Bit
7
GCEN
R/W
0
6
5
ACKDT
R/W
0
4
ACKEN
R/W
0
3
RCEN
R/W
0
2
1
RSEN
R/W
0
0
ACKSTAT
R/W/HC
0
PEN
R/W
0
SEN
R/W
0
Access
Reset
Bit 7 – GCEN
General Call Enable bit (Slave mode only)
Value
Mode
Description
x
1
0
Master mode
Slave mode
Slave mode
Don’t care
General Call is enabled
General Call is not enabled
Bit 6 – ACKSTATꢀAcknowledge Status bit (Master Transmit mode only)
Value
Description
1
0
Acknowledge was not received from slave
Acknowledge was received from slave
Bit 5 – ACKDT
Acknowledge Data bit (Master Receive mode only)(1)
Value
Description
1
0
Not Acknowledge
Acknowledge
Bit 4 – ACKEN
Acknowledge Sequence Enable bit(2)
Value
Description
1
Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit;
automatically cleared by hardware
0
Acknowledge sequence is Idle
Bit 3 – RCEN
Receive Enable bit (Master Receive mode only)(2)
Value
1
0
Description
Enables Receive mode for I2C
Receive is Idle
Bit 2 – PEN
Stop Condition Enable bit (Master mode only)(2)
Value
Description
1
0
Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware
Stop condition is Idle
Bit 1 – RSEN
Repeated Start Condition Enable bit (Master mode only)(2)
Value
Description
1
0
Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware
Repeated Start condition is Idle
DS40002195A-page 309
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MSSP - Master Synchronous Serial Port Module
Bit 0 – SEN
Start Condition Enable bit (Master mode only)(2)
Value
Description
1
0
Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware
Start condition is Idle
Note:ꢀ
1. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
2. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
DS40002195A-page 310
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MSSP - Master Synchronous Serial Port Module
25.4.7 SSPxCON3
Name:ꢀ
SSPxCON3
Address:ꢀ 0x0192
MSSP Control Register 3
Bit
7
6
PCIE
R/W
0
5
SCIE
R/W
0
4
BOEN
R/W
0
3
SDAHT
R/W
0
2
SBCDE
R/W
0
1
AHEN
R/W
0
0
DHEN
R/W
0
ACKTIM
R/HS/HC
0
Access
Reset
Bit 7 – ACKTIMꢀAcknowledge Time Status bit
Unused in Master mode.
Value
x
1
Mode
Description
This bit is not used
SPI or I2C Master
I2C Slave and AHEN = 1or DHEN Eighth falling edge of SCL has occurred and the ACK/NACK state
is active
= 1
I2C Slave
0
ACK/NACK state is not active. Transitions low on ninth rising
edge of SCL.
Bit 6 – PCIE
Stop Condition Interrupt Enable bit(1)
Value
Mode
Description
x
1
0
SPI or SSPM = 1111or 0111
SSPM ≠ 1111and SSPM ≠ 0111
SSPM ≠ 1111and SSPM ≠ 0111
Don’t care
Enable interrupt on detection of Stop condition
Stop detection interrupts are disabled
Bit 5 – SCIEꢀStart Condition Interrupt Enable bit
Value
Mode
Description
x
1
0
SPI or SSPM = 1111or 0111
SSPM ≠ 1111and SSPM ≠ 0111
SSPM ≠ 1111and SSPM ≠ 0111
Don’t care
Enable interrupt on detection of Start condition
Start detection interrupts are disabled
Bit 4 – BOEN
Buffer Overwrite Enable bit(2)
Value
Mode Description
1
0
1
SPI
SPI
I2C
SSPxBUF is updated every time a new data byte is available, ignoring the BF bit
If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated
SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on
updating the buffer
I2C
SSPxBUF is only updated when SSPOV is clear
0
Bit 3 – SDAHTꢀSDA Hold Time Selection bit
Value
Mode
SPI
I2C
I2C
Description
Not used in SPI mode
Minimum of 300 ns hold time on SDA after the falling edge of SCL
Minimum of 100 ns hold time on SDA after the falling edge of SCL
x
1
0
Bit 2 – SBCDEꢀSlave Mode Bus Collision Detect Enable bit
Unused in Master mode.
Value
Mode
Description
Don’t care
Collision detection is enabled
Collision detection is not enabled
SPI or I2C Master
I2C Slave
x
1
0
I2C Slave
DS40002195A-page 311
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MSSP - Master Synchronous Serial Port Module
Bit 1 – AHENꢀAddress Hold Enable bit
Value
x
Mode
Description
SPI or I2C Master Don’t care
I2C Slave
I2C Slave
Address hold is enabled. As a result CKP is cleared after the eighth falling SCL
edge of an address byte reception. Software must set the CKP bit to resume
operation.
1
0
Address hold is not enabled
Bit 0 – DHENꢀData Hold Enable bit
Value
x
Mode
Description
SPI or I2C Master Don’t care
I2C Slave
I2C Slave
Data hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of
a data byte reception. Software must set the CKP bit to resume operation.
Data hold is not enabled
1
0
Note:ꢀ
1. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
2. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.
DS40002195A-page 312
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MSSP - Master Synchronous Serial Port Module
25.5
Register Summary: MSSP Control
Address
Name
Bit Pos.
0x00
...
Reserved
0x018B
0x018C
0x018D
0x018E
0x018F
0x0190
0x0191
0x0192
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BUF[7:0]
ADD[7:0]
MSK[6:0]
P
MSK0
BF
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
S
R/W
SSPM[3:0]
UA
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
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FVR - Fixed Voltage Reference
26.
FVR - Fixed Voltage Reference
The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V
selectable output levels. The output of the FVR can be configured to supply a reference voltage to the ADC module
as a positive reference and input channel.
The FVR can be enabled by setting the FVREN bit to ‘1’.
Note:ꢀ Fixed Voltage Reference output cannot exceed VDD
.
26.1
Independent Gain Amplifiers
The output of the FVR, which is connected to the ADC, is routed through an independent programmable gain
amplifier. This amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels.
The ADFVR bits are used to enable and configure the gain amplifier settings for the reference supplied to the ADC
module.
Refer to the figure below for block diagram of the FVR module.
Figure 26-1.ꢀFixed Voltage Reference Block Diagram
2
ADCFVR[1:0]
To ADC module
as reference and
input channel
1x
2x
4x
FVR Buffer 1
EN
+
RDY
_
Any peripheral
requiring Fixed
Reference
26.2
26.3
FVR Stabilization Period
When the FVR module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the
circuits stabilize and are ready for use, the FVRRDY bit will be set.
Register Definitions: FVR
Long bit name prefixes for the FVR peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bits Naming Conventions” chapter for more information.
Table 26-1.ꢀFVR Long bit name prefixes
Peripheral
Bit Name Prefix
FVR
FVR
DS40002195A-page 314
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FVR - Fixed Voltage Reference
26.3.1 FVRCON
Name:ꢀ
FVRCON
Address:ꢀ 0x90C
Fixed Voltage Reference Control Register
Bit
7
FVREN
R/W
0
6
5
4
3
2
1
0
FVRRDY
ADFVR[1:0]
Access
Reset
R
0
R/W
0
R/W
0
Bit 7 – FVRENꢀFixed Voltage Reference Enable bit
Value
Description
1
0
Fixed Voltage Reference is enabled
Fixed Voltage Reference is disabled
Bit 6 – FVRRDYꢀ Fixed Voltage Reference Ready Flag bit (2)
Value
Description
1
Fixed Voltage Reference output is ready for use
0
Fixed Voltage Reference output is not ready or not enabled
Bits 1:0 – ADFVR[1:0]ꢀADC FVR Buffer Gain Selection bit
Value
11
10
01
00
Description
ADC FVR Buffer Gain is 4x, (4.096V)(1)
ADC FVR Buffer Gain is 2x, (2.048V)(1)
ADC FVR Buffer Gain is 1x, (1.024V)
ADC FVR Buffer is off
Note:ꢀ
1. Fixed Voltage Reference output cannot exceed VDD
.
2. FVRRDY is always ‘1’.
DS40002195A-page 315
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FVR - Fixed Voltage Reference
26.4
Register Summary - FVR
Address
Name
Bit Pos.
0x00
...
Reserved
FVRCON
0x090B
0x090C
7:0
FVREN
FVRRDY
ADFVR[1:0]
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ADC - Analog-to-Digital Converter
27.
ADC - Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) allows the conversion of an analog input signal into a 10-bit binary
representation of that signal. This device uses analog inputs, which are multiplexed into a single Sample-and-Hold
circuit. The output of the Sample-and-Hold circuit is connected to the input of the converter. The converter generates
a 10-bit binary result via successive approximation and stores the results in the ADC Result registers
(ADRESH:ADRESL register pair).
The ADC voltage reference is software selectable to be either internally generated or externally supplied.
The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the
device from Sleep.
Figure 27-1 shows the block diagram of the ADC.
DS40002195A-page 317
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ADC - Analog-to-Digital Converter
Figure 27-1.ꢀADC Block Diagram
PREF[1:0]
Positive
Reference
Select
FVR_buffer1
11
10
01
00
VREF+ pin
Reserved
VDD
CS[2:0]
VSS
AN0
ANa
VREF- VREF+
External
Channel
Inputs
.
.
.
Fosc
Divider
FOSC/n
FOSC
ADC
Clock
Select
ADC_clk
ANz
sampled
input
ADCRC
VSS
Internal
Channel
Inputs
ADC CLOCK SOURCE
FVR_buffer1
CHS[5:0]
ADC
Sample Circuit
FM
set bit ADIF
10
complete
start
10-bit Result
16
Write to bit
GO/DONE
GO/DONE
ADRESH
ADRESL
Enable
Trigger Select
TRIGSEL[3:0]
ADON
. . .
VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
27.1
ADC Configuration
When configuring and using the ADC, the following functions must be considered:
•
•
•
•
•
•
PORT Configuration
Channel Selection
ADC Voltage Reference Selection
ADC Conversion Clock Source
Interrupt Control
Result Formatting
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ADC - Analog-to-Digital Converter
27.1.1 Port Configuration
The ADC will convert the voltage on a pin whether or not the ANSEL bit is set. When converting analog signals, the
I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to the “I/O Ports”
chapter for more information.
Important:ꢀ Analog voltages on any pin that is defined as a digital input may cause the input buffer to
conduct excess current.
27.1.2 Channel Selection
The Analog Channel Select (CHS) bits determine which channel is connected to the Sample-and-Hold circuit for
conversion. When switching channels, it is recommended to add an acquisition delay before starting the next
conversion. Refer to the “ADC Operation” section for more information.
Important:ꢀ To reduce the chance of measurement error, it is recommended to discharge the Sample-
and-Hold capacitor when switching between ADC channels by starting a conversion on a channel
connected to VSS and terminating the conversion after the acquisition time has elapsed. If the ADC does
not have a dedicated VSS input channel, a free input channel can be connected to VSS and used in place
of the dedicated input channel.
27.1.3 ADC Voltage Reference
The ADC Positive Voltage Reference Selection (PREF) bits provide control of the positive voltage reference. Refer to
the ADC Control Register 1 (ADCON1) for the list of available positive voltage sources.
27.1.4 Conversion Clock
The conversion clock source is selected via the ADC Conversion Clock Select (CS) bits. The available clock sources
include several derivatives of the system clock (FOSC), as well as a dedicated internal fixed-frequency clock referred
to as the ADCRC.
The time to complete one bit conversion is defined as the TAD. Refer to Figure 27-2 for complete timing details of the
ADC conversion.
For a correct conversion, the appropriate TAD specification must be met. Refer to the ADC Timing Specifications table
in the “Electrical Specifications” chapter for more details. Table 27-1 gives examples of appropriate ADC clock
selections.
Important:ꢀ
•
With the exception of the ADCRC clock source, any changes in the system clock frequency will
change the ADC clock frequency, which may adversely affect the ADC result.
•
The internal control logic of the ADC operates off of the clock selected by the CS bits. When the CS
bits select the ADCRC, there may be unexpected delays in operation when setting the ADC control
bits.
Table 27-1.ꢀADC Clock Period (TAD) for Different Device Frequencies (FOSC
)
ADC Clock Period (TAD) for Different Device Frequencies (FOSC
)
ADC Clock
Source
CS[2:0]
32 MHz
62.5 ns(2)
125 ns(2)
20 MHz
100 ns(2)
200 ns(2)
16 MHz
125 ns(2)
250 ns(2)
8 MHz
4 MHz
500 ns(2)
1.0 µs
1 MHz
2.0 µs
4.0 µs
250 ns(2)
500 ns(2)
‘b000
‘b100
FOSC/2
FOSC/4
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ADC - Analog-to-Digital Converter
...........continued
ADC Clock Period (TAD) for Different Device Frequencies (FOSC
)
ADC Clock
Source
CS[2:0]
32 MHz
250 ns(2)
500 ns(2)
1.0 µs
20 MHz
400 ns(2)
800 ns(2)
1.6 µs
16 MHz
500 ns(2)
1.0 µs
8 MHz
1.0 µs
2.0 µs
4.0 µs
8.0 µs
4 MHz
2.0 µs
1 MHz
8.0 µs
‘b001
‘b101
‘b010
‘b110
‘bx11
FOSC/8
FOSC/16
FOSC/32
FOSC/64
ADCRC
Note:ꢀ
4.0 µs
16.0 µs(2)
32.0 µs(2)
64.0 µs(2)
2.0 µs
8.0 µs
2.0 µs
3.2 µs
4.0 µs
16.0 µs(2)
1.0 - 6.0(1,3)
1. Refer to the “Electrical Specifications” chapter to see the TAD parameter for the ADCRC source typical
TAD value.
2. These values violate the required TAD time.
3. The ADC clock period (TAD) and the total ADC conversion time can be minimized when the ADC clock is
derived from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions
are to be performed with the device in Sleep mode.
Figure 27-2.ꢀ10-Bit Analog-to-Digital Conversion TAD Cycles
TAD1
TAD2
b9
TAD3
b8
TAD4
b7
TAD5
b6
TAD6
b5
TAD7
b4
TAD8
b3
TAD9
b2
TAD10
b1
TAD11
b0
THCD
Conversion Starts
TACQ
On the following cycle:
Holding capacitor disconnected
from analog input (THCD).
ADRESH:ADRESL is loaded,
GO bit is cleared,
Set GO bit
ADIF bit is set,
holding capacitor is reconnected to analog input.
Enable ADC (ON bit)
and
Select channel (CS bits)
27.1.5 Interrupts
The ADC module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion.
The ADC Interrupt Flag (ADIF) bit is set upon the completion of each conversion. If the ADC Interrupt Enable (ADIE)
bit is set, an ADC interrupt event occurs. The ADIF bit must be cleared by software.
Important:ꢀ
1. The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC
Interrupt is enabled.
2. The ADC operates in Sleep only when the ADCRC oscillator is selected as the clock source.
The ADC Interrupt can be generated while the device is operating or while in Sleep. While the device is operating in
Sleep mode:
•
If ADIE = 1, PEIE = 1, and GIE = 0: An interrupt will wake the device from Sleep. Upon waking from Sleep, the
instructions following the SLEEPinstruction are executed. The Interrupt Service Routine is not executed.
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ADC - Analog-to-Digital Converter
•
If ADIE = 1, PEIE = 1, and GIE = 1: An interrupt will wake the device from Sleep. Upon waking from Sleep, the
instruction following the SLEEPinstruction is always executed. Then the execution will switch to the Interrupt
Service Routine.
27.1.6 ADC Result Formatting
The 10-bit ADC conversion result can be supplied in two formats: left-justified or right-justified. The ADC Result
Format/Alignment Selection (FM) bit controls the output format as shown in Figure 27-3.
Figure 27-3.ꢀ10-Bit ADC Conversion Result Format
ADRESH
ADRESL
(FM = 0)
MSb
bit 7
LSb
bit 0
bit 7
bit 0
10-bit ADC Result
Unimplemented: Read as 0ꢀ
(FM = 1)
MSb
LSb
bit 0
bit 7
bit 0
bit 7
Unimplemented: Read as 0ꢀ
10-bit ADC Result
Important:ꢀ Writes to the ADRES register pair are always right-justified, regardless of the selected format
mode. Therefore, data read after writing to ADRES when FM = 0will be shifted left four places.
27.2
ADC Operation
27.2.1 Starting a Conversion
To enable the ADC module, the ON bit must be set to ‘1’. A conversion may be started by either of the following:
•
•
Software setting the GO bit to ‘1’
An external trigger (source selected by the ADC Auto-Conversion Trigger (ADACT) register
Important:ꢀ The GO bit should not be set in the same instruction that turns on the ADC. Refer to the “ADC
Conversion Procedure” section for more details.
27.2.2 Completion of a Conversion
When the conversion is complete, the ADC module will:
•
•
•
Clear the GO bit
Set the ADIF bit
Update the ADRES registers with the new conversion result
DS40002195A-page 321
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ADC - Analog-to-Digital Converter
27.2.3 ADC Operation During Sleep
The ADC module can operate in Sleep. This requires the ADC clock source to be set to the ADCRC option. When the
ADC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows
the SLEEPinstruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is
enabled (ADIE = 1), the device will wake up from Sleep when the conversion completes. If the ADC interrupt is
disabled (ADIE = 0), the device remains in Sleep and the ADC module is turned off, although the ON bit remains set.
When the ADC clock source is something other than the ADCRC, a SLEEPinstruction causes the present conversion
to be aborted and the ADC is turned off, although the ON bit remains set.
27.2.3.1 External Trigger During Sleep
If an external trigger is received when the ADC is in Sleep, the trigger will be recorded, but the conversion will not
begin until the device exits Sleep.
27.2.4 Auto-Conversion Trigger
The auto-conversion trigger allows periodic ADC measurements without software intervention. When a rising edge of
the selected source occurs, the GO bit is set by hardware.
The auto-conversion trigger source is selected with the Auto-Conversion Trigger Select (ACT) bits.
Important:ꢀ Using the auto-conversion trigger does not ensure proper ADC timing. It is the user’s
responsibility to ensure that the ADC timing requirements are met.
27.2.5 ADC Conversion Procedure
This is an example procedure for using the ADC to perform an Analog-to-Digital Conversion:
1. Configure Port:
1.1.
1.2.
Disable the pin output driver (Refer to the TRISx register)
Configure the pin as analog (Refer to the ANSELx register)
2. Configure the ADC module:
2.1.
2.2.
2.3.
2.4.
2.5.
Select the ADC conversion clock
Configure the voltage reference
Select the ADC input channel
Configure result format
Turn on the ADC module
3. Configure ADC interrupt (optional):
3.1.
3.2.
3.3.
3.4.
Clear ADC interrupt flag
Enable ADC interrupt
Enable the peripheral interrupt (PEIE bit)
Enable global interrupt (GIE bit)(1)
4. Wait the required acquisition time(2)
.
5. Start conversion by setting the GO bit.
6. Wait for ADC conversion to complete by one of the following:
– Polling the GO bit
– Waiting for the ADC interrupt (if interrupt is enabled)
7. Read ADC Result.
8. Clear the ADC interrupt flag (if interrupt is enabled).
DS40002195A-page 322
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ADC - Analog-to-Digital Converter
Note:ꢀ
1. With global interrupts disabled (GIE = 0), the device will wake from Sleep but will not enter an Interrupt Service
Routine.
2. Refer to the ADC Acquisition Requirements section for more details.
Example 27-1.ꢀADC Conversion (assembly)
; This code block configures the ADC for polling,
; VDD and VSS references,
; ADCRC oscillator, and AN0 input.
; Conversion start & polling for completion are included.
BANKSEL TRISA
BSF
TRISA,0
; Set RA0 to input
; Set RA0 to analog
BANKSEL ANSEL
BSF
ANSEL,0
BANKSEL ADCON0
CLRF
CLRF
CLRF
BSF
MOVLW
MOVWF
CALL
BANKSEL ADCON0
BSF
BTFSC
GOTO
BANKSEL ADRESH
MOVF
MOVWF
MOVF
MOVWF
ADCON0
ADCON1
ADACT
; Auto-conversion disabled
; CHS = RA0, ADC ON
ADCON0,0
B’11110000’ ; FM = Right-justified, CS = ADCRC, PREF = VDD
ADCON1
SampleTime ; Acquisition delay
ADCON0,GO
ADCON0,GO
$-1
; Start conversion
; Is conversion done?
; No, test again
ADRESH,W
RESULTHI
ADRESL,W
RESULTLO
; Read upper byte
; Store in GPR space
; Read lower byte
; Store in GPR space
Example 27-2.ꢀADC Conversion (C)
/*This code block configures the ADC
for polling, VDD and VSS references,
ADCRC oscillator and AN0 input.
Conversion start & polling for completion
are included.
*/
void main() {
//System Initialize
initializeSystem();
// Configure Port
TRISAbits.TRISA0 = 1;
ANSELAbits.ANSELA0 = 1;
// Set RA0 to input
// Set RA0 to analog
// Configure ADC
ADCON1bits.CS = 1;
ADCON1bits.PREF = ‘b11;
ADCON0bits.CHS = ‘b000000; // RA0
ADCON1bits.FM = 1;
ADCON0bits.ON = 1;
// ADCRC Clock
// VDD
// Right justify
// Turn ADC On
while (1) {
ADCON0bits.GO = 1;
while (ADCON0bits.GO);
resultHigh = ADRESH;
resultLow = ADRESL;
// Start conversion
// Wait for conversion done
// Read result
// Read result
}
}
DS40002195A-page 323
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ADC - Analog-to-Digital Converter
27.3
ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to
the input channel voltage level. The analog input model is shown in Figure 27-4. The source impedance (RS) and the
internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The
sampling switch (RSS) impedance varies over the device voltage (VDD). The maximum recommended impedance for
analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the
analog input channel is selected (or changed), an ADC acquisition time must be completed before the conversion can
be started. To calculate the minimum acquisition time, Equation 27-1 may be used. This equation assumes an error
of 1/2 LSb. The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
Equation 27-1.ꢀAcquisition Time Example
Assumptions: Temperature = 50°C; External impedance = 10kΩ; VDD = 5.0V
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
ꢈ
= ꢈ
+ ꢈ + ꢈ
ꢢꢌꢣ
ꢢꢂꢀ ꢌ ꢌꢊꢞꢞ
ꢈ
= 2ꢤꢍ + ꢈ + ꢈꢃꢥꢦꢃꢄꢏꢓꢒꢄꢃ − 25°ꢌ 0.05ꢤꢍ/°ꢌ
ꢌ
ꢢꢌꢣ
The value for TC can be approximated with the following equations:
1
ꢛ + 1
ꢑ
1 −
= ꢑ
; [1] VCHOLD charged to within ½ lsb
ꢢꢀꢀꢖꢧꢠꢙ
ꢌꢕꢊꢖꢙ
2
− 1
= ꢑ
−ꢈ
ꢌ
ꢑ
1 − ꢃ
1 − ꢃ
; [2] VCHOLD charge response to VAPPLIED
ꢉꢌ
ꢢꢀꢀꢖꢧꢠꢙ
ꢌꢕꢊꢖꢙ
−ꢈ
ꢌ
1
ꢛ + 1
ꢑ
= ꢑ
1 −
; Combining [1] and [2]
ꢉꢌ
ꢢꢀꢀꢖꢧꢠꢙ
ꢢꢀꢀꢖꢧꢠꢙ
2
− 1
Note: Where n = ADC resolution in bits
Solving for TC:
ꢈ = − ꢌ
ꢉ
+ ꢉ + ꢉ ꢐꢛ 1/2047
ꢌ
ꢕꢊꢖꢙ ꢧꢌ ꢋꢋ ꢋ
ꢈ = − 10ꢦꢞ 1ꢨΩ + 7ꢨΩ + 10ꢨΩ ꢐꢛ 0.0004885
ꢌ
ꢈ = 1.37ꢤꢍ
ꢌ
Therefore:
ꢈ
= 2ꢤꢍ + 1.37ꢤꢍ + 50°ꢌ − 25°ꢌ 0.05ꢤꢍ/°ꢌ
= 4.62 ꢤꢍ
ꢢꢌꢣ
ꢈ
ꢢꢌꢣ
Important:ꢀ
•
•
•
The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
The charge holding capacitor (CHOLD) is not discharged after each conversion.
The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
DS40002195A-page 324
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© 2020 Microchip Technology Inc.
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ADC - Analog-to-Digital Converter
Figure 27-4.ꢀAnalog Input Model
Sampling
Switch
VDD
Analog
Input pin
VT ꢀ0.6V
VT ꢀ0.6V
SS
RSS
RS
RIC ꢁꢀ1Kꢂꢀ
(1)
CPIN
5pF
VA
ILEAKAGE
CHOLD = 10 PF
Ref-
VSS
Legend: CPIN
= Input Capacitance
ILEAKAGE = Leakage Current at the pin due to various junctions
11
10
9
RIC
RS
= Interconnect Resistance
= Source Impedance
Sampling
Switch
(Kꢂꢀ)
8
RSS
VA
= Analog Voltage
7
6
VT
SS
= Diode Forward Voltage
= Sampling Switch
5
RSS
CHOLD
= Resistance of the Sampling Switch
= Sample/Hold Capacitance
2 3 4 5 6
VDD
Note:
1. Refer to the Electrical Specificationsꢀ chapter of the device data sheet for more details.
(V)
Figure 27-5.ꢀADC Transfer Function
Rev. 30-000115A
5/16/2017
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Analog Input Voltage
1.5 LSB
0.5 LSB
Zero-Scale
Transition
REF-
Full-Scale
Transition
REF+
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ADC - Analog-to-Digital Converter
27.4
Register Definitions: ADC Control
Table 27-2.ꢀADC Long Bit Name Prefixes
Peripheral
Bit Name Prefix
ADC
AD
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ADC - Analog-to-Digital Converter
27.4.1 ADCON0
Name:ꢀ
ADCON0
Address:ꢀ 0x09D
ADC Control Register 0
Bit
7
6
5
4
3
2
1
0
ON
R/W
0
CHS[5:0]
GO
R/W/HS/HC
0
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:2 – CHS[5:0]ꢀAnalog Channel Select
CHS
Selected Channel
111111-011111
011110
Reserved
FVR Buffer 1
Reserved
VSS
011101-011100
011011
011010-010110
010101
Reserved
RC5(1)
RC4(1)
RC3(1)
RC2(1)
Reserved
RB7(2)
RB6(2)
RB5(2)
Reserved
RA5
010100
010011
010010
010001-010000
001111
001110
001101
001100-000110
000101
000100
RA4
000011
Reserved
RA2
000010
000001
RA1
000000
RA0
Note:ꢀ
1. Not available on 8-pin devices (PIC16F15213/14).
2. Only available on 20-pin devices (PIC16F15243/44/45).
Bit 1 – GOꢀADC Conversion Status
Value
Description
1
ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is
automatically cleared by hardware when the ADC conversion has completed.
ADC conversion completed/not in progress
0
Bit 0 – ONꢀADC Enable
Value
Description
1
ADC is enabled
0
ADC is disabled an consumes no operating current
DS40002195A-page 327
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ADC - Analog-to-Digital Converter
27.4.2 ADCON1
Name:ꢀ
ADCON1
Address:ꢀ 0x09E
ADC Control Register 1
Bit
7
FM
R/W
0
6
5
CS[2:0]
R/W
0
4
3
2
1
0
PREF[1:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 7 – FMꢀADC Result Format/Alignment Selection
Value
Description
1
0
Right-justified. The six Most Significant bits of ADRESH are zero-filled.
Left-justified. The six Least Significant bits of ADRESL are zero-filled.
Bits 6:4 – CS[2:0]ꢀADC Conversion Clock Select
Value
111
110
101
100
011
010
001
000
Description
ADCRC
FOSC/64
FOSC/16
FOSC/4
ADCRC
FOSC/32
FOSC/8
FOSC/2
Bits 1:0 – PREF[1:0]ꢀADC Positive Voltage Reference Configuration
Value
11
10
Description
VREF+ is connected to internal Fixed Voltage Reference (FVR)
VREF+ is connected to external VREF+ pin
Reserved
01
00
VREF+ is connected to VDD
DS40002195A-page 328
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ADC - Analog-to-Digital Converter
27.4.3 ADACT
Name:ꢀ
ADACT
Address:ꢀ 0x09F
ADC Auto-Conversion Trigger Source Selection Register
Bit
7
6
5
4
3
2
1
0
ACT[3:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 3:0 – ACT[3:0]ꢀAuto-Conversion Trigger Select
ACT
1111-1110
1101
Auto-conversion Trigger Source
Reserved
Software read of ADRESH
Reserved
1100-1010
1001
Interrupt-on-change Interrupt Flag
PWM4_out
001000
0111
PWM3_out
0110
CCP2_trigger
0101
CCP1_trigger
0100
TMR2_postscaled
TMR1_overflow
0011
0010
TMR0_overflow
0001
Pin selected by ADACTPPS
External Trigger Disabled
0000
DS40002195A-page 329
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ADC - Analog-to-Digital Converter
27.4.4 ADRES
Name:ꢀ
ADRES
Address:ꢀ 0x09B
ADC Result Register
15
Bit
14
13
12
11
10
9
8
ADRES[15:8]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bit
7
6
5
4
3
2
1
0
ADRES[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – ADRES[15:0]ꢀADC Sample Result
Note:ꢀ The individual bytes in this multi-byte register can be accessed with the following register names:
•
•
ADRESH: Accesses the high byte ADRES[15:18]
ADRESL: Accesses the low byte ADRES[7:0]
DS40002195A-page 330
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ADC - Analog-to-Digital Converter
27.5
Register Summary - ADC
Address
Name
Bit Pos.
0x00
...
Reserved
0x9A
7:0
15:8
7:0
ADRES[7:0]
0x9B
ADRES
ADRES[15:8]
0x9D
0x9E
0x9F
ADCON0
ADCON1
ADACT
CHS[5:0]
CS[2:0]
GO
ON
7:0
FM
PREF[1:0]
7:0
ACT[3:0]
DS40002195A-page 331
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Charge Pump
28.
Charge Pump
This family of devices offers a dedicated charge pump, which is controlled through the Charge Pump Control
(CPCON) register. The primary purpose of the charge pump is to supply a constant voltage to the gates of transistor
devices contained in analog peripherals, signal and reference input pass-gates, and to prevent degradation of
transistor performance at low operating voltages.
The charge pump offers the following modes:
•
•
•
Manually Enabled
Automatically Enabled
Disabled
28.1
28.2
Manually Enabled
The charge pump can be manually enabled via the Charge Pump Enable (CPON) bits. When the CPON bits are
configured as ‘11’, the charge pump is enabled. In this case, the charge pump provides additional voltage to all
analog systems, regardless of VDD levels, but also consumes additional current.
Automatically Enabled
The charge pump can also be enabled automatically. This allows the application to determine when to enable the
charge pump. If the charge pump is enabled while VDD levels are above a sufficient threshold, the charge pump does
not improve analog performance, but also consumes additional current. Allowing hardware to monitor VDD and
determine when to enable the charge pump prevents unnecessary current consumption.
When the CPON bits are configured as ‘10’, charge pump hardware monitors VDD and compares the VDD levels to a
reference voltage threshold (VAUTO), which is set to 4.096V. When hardware detects a VDD level lower than the
threshold, the charge pump is automatically enabled. If VDD returns to a level above the threshold, hardware
automatically disables the charge pump.
When the CPON bits are configured as ‘01’, charge pump hardware waits for an analog peripheral, such as the ADC,
to be enabled before monitoring VDD. In this case, charge pump hardware monitors all analog peripherals, and once
an analog peripheral is enabled, hardware begins to compare VDD to VAUTO. When hardware detects a VDD level
lower than the threshold, hardware enables the charge pump. If VDD returns to a level above the threshold, or if the
analog peripheral is disabled, the charge pump is automatically disabled.
28.3
28.4
Disabled
The charge pump is disabled by default (CPON = 00). Clearing the CPON bits will disable the charge pump.
Charge Pump Threshold
The Charge Pump Threshold (CPT) bit indicates whether or not VDD is at an acceptable operating level. Charge
pump hardware compares VDD to the threshold voltage (VAUTO), which is set at 4.096V. If VDD is above VAUTO, the
CPT bit is set (CPT = 1). If VDD is below VAUTO, CPT is clear (CPT = 0).
28.5
Charge Pump Ready
The Charge Pump Ready Status (CPRDY) bit indicates whether or not the charge pump is ready for use. When
CPRDY is set (CPRDY = 1), the charge pump has reached a steady-state operation and is ready for use. When
CPRDY is clear (CPRDY = 0), the charge pump is either in the OFF state or has not reached a steady-state
operation.
DS40002195A-page 332
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Charge Pump
28.6
Register Definitions: Charge Pump
DS40002195A-page 333
Preliminary Datasheet
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Charge Pump
28.6.1 CPCON
Name:ꢀ
CPCON
Address:ꢀ 0x09A
Charge Pump Control Register
Bit
7
6
5
4
3
2
1
CPT
R
0
CPON[1:0]
CPRDY
Access
Reset
R/W
0
R/W
0
R
0
0
Bits 7:6 – CPON[1:0]
Charge Pump Enable
Value
11
Description
Charge pump is enabled
10
Charge pump is automatically enabled when VDD < VAUTO (VAUTO = 4.096V)
01
Charge pump is automatically enabled when an analog peripheral is enabled (ADCON0.ON = 1) AND
VDD < VAUTO
00
Charge pump is disabled
Bit 1 – CPT
Charge Pump Threshold
Value
Description
1
VDD is above the charge pump auto-enable threshold (VAUTO
)
0
VDD is below the charge pump auto-enable threshold (VAUTO
)
Bit 0 – CPRDY
Charge Pump Ready Status
Value
Description
1
Charge pump has reached a steady-state operation
0
Charge pump is Off or has not reached a steady-state operation
DS40002195A-page 334
Preliminary Datasheet
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Instruction Set Summary
29.
Instruction Set Summary
PIC16F152 devices incorporate the standard set of 50 PIC16 core instructions. Each instruction is a 14-bit word
containing the operation code (opcode) and all required operands. The opcodes are broken into three broad
categories:
•
•
•
Byte Oriented
Bit Oriented
Literal and Control
The literal and control category contains the most varied instruction word format.
Table 29-3 lists the instructions recognized by the XC8 assembler.
All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or
three cycles:
•
•
•
•
Subroutine entry takes two cycles (CALL, CALLW)
Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE)
Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)
One additional instruction cycle will be used when any instruction references an indirect file register and the file
select register is pointing to program memory.
One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal
instruction execution rate of 1 MHz.
All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal
digit.
29.1
Read-Modify-Write Operations
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified, and the result is stored according to either the working (W)
register, or the originating file register, depending on the state of the destination designator 'd' (see Table 29-1 for
more information). A read operation is performed on a register even if the instruction writes to that register.
Table 29-1.ꢀOpcode Field Descriptions
Field
Description
f
W
b
Register file address (0x00to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
k
Don’t care location (= 0or 1).
The assembler will generate code with x = 0.
x
It is the recommended form of use for compatibility with all Microchip software tools.
Destination select; d = 0: store result in W, d = 1: store result in file register f.
FSR or INDF number. (0-1)
d
n
mm
Pre/post increment/decrement mode selection
Table 29-2.ꢀAbbreviation Descriptions
Field
Description
PC
Program Counter
DS40002195A-page 335
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Instruction Set Summary
...........continued
Field
Description
Time-Out bit
Carry bit
TO
C
DC
Z
Digit Carry bit
Zero bit
PD
Power-Down bit
29.2
Standard Instruction Set
Table 29-3.ꢀInstruction Set
Mnemonic,
Operands
14-Bit Opcode
Status
Affected
Description
Cycles
Notes
MSb
LSb
BYTE-ORIENTED OPERATIONS
Add WREG and f
ADDWF f, d
ADDWFC f, d
ANDWF f, d
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C, DC, Z
2
2
2
2
2
2
2
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
Add WREG and CARRY bit to f
AND WREG with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
ASRF
LSLF
f, d
f, d
f, d
f
LSRF
CLRF
CLRW
COMF
DECF
INCF
–
Clear WREG
Z
f, d
f, d
f, d
f, d
f, d
f
Complement f
Z
2
2
2
2
2
2
2
2
Decrement f
Z
Increment f
Z
IORWF
MOVF
MOVWF
RLF
Inclusive OR WREG with f
Move f
Z
Z
Move WREG to f
Rotate Left f through Carry
Rotate Right f through Carry
None
C
f, d
f, d
RRF
C
DS40002195A-page 336
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Instruction Set Summary
...........continued
Mnemonic,
14-Bit Opcode
Status
Affected
Description
Cycles
Notes
Operands
MSb
LSb
SUBWF f, d
SUBWFB f, d
SWAPF f, d
XORWF f, d
Subtract WREG from f
1
C, DC, Z
C, DC, Z
None
2
00
0010
1011
1110
0110
dfff
dfff
dfff
dfff
ffff
Subtract WREG from f with
borrow
1
1
1
2
2
2
11
00
00
ffff
ffff
ffff
Swap nibbles in f
Exclusive OR WREG with f
Z
BYTE-ORIENTED SKIP OPERATIONS
DECFSZ f, d
INCFSZ f, d
Decrement f, Skip if 0
1(2)
None
None
1, 2
1, 2
00
00
1011
1111
dfff
dfff
ffff
ffff
Increment f, Skip if 0
1(2)
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
f, b
f, b
Bit Clear f
1
None
None
2
2
01
00bb
01bb
bfff
bfff
ffff
ffff
Bit Set f
1
01
BIT-ORIENTED SKIP OPERATIONS
BTFSC
BTFSS
f, b
f, b
Bit Test f, Skip if Clear
1(2)
None
None
1, 2
1, 2
01
10bb
11bb
bfff
bfff
ffff
ffff
Bit Test f, Skip if Set
1(2)
1010
LITERAL OPERATIONS
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
Add literal and WREG
AND literal with WREG
Inclusive OR literal with WREG
Move literal to BSR
1
1
1
1
1
1
1
1
C, DC, Z
Z
11
11
11
00
11
11
11
11
1110
1001
1000
000
kkkk
kkkk
kkkk
0k
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
Z
None
None
None
C, DC, Z
Z
Move literal to PCLATH
Move literal to W
0001
0000
1100
1010
1kkk
kkkk
kkkk
kkkk
Subtract W from literal
Exclusive OR literal with W
CONTROL OPERATIONS
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Instruction Set Summary
...........continued
Mnemonic,
14-Bit Opcode
Status
Affected
Description
Cycles
Notes
Operands
MSb
LSb
BRA
k
—
k
Relative Branch
2
None
None
None
None
None
None
None
None
11
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
BRW
Relative Branch with WREG
Call Subroutine
2
2
2
2
2
2
2
00
10
00
10
00
11
00
1011
kkkk
1010
kkkk
1001
kkkk
1000
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
—
k
Call Subroutine with WREG
Go to address
k
Return from interrupt
Return with literal in WREG
Return from Subroutine
k
—
INHERENT OPERATIONS
CLRWDT
NOP
—
—
—
—
f
Clear Watchdog Timer
1
1
1
1
1
TO, PD
None
00
00
00
00
00
0000
0000
0000
0000
0000
0110
0000
0000
0110
0110
0100
0000
0001
0011
0fff
No Operation
RESET
SLEEP
TRIS
Software device Reset
Go into Standby mode
Load TRIS register with WREG
None
TO, PD
None
C-COMPILER OPTIMIZED
ADDFSR n, k
n, mm
Add Literal k to FSRn
1
1
1
1
1
None
11
00
11
00
11
0001
0000
1111
0000
1111
0nkk
0001
0nkk
0001
1nkk
kkkk
0nmm
kkkk
1nmm
kkkk
Move Indirect FSRn to WREG with pre/post inc/dec
modifier, mm
Z
Z
2, 3
2
MOVIW
k[n]
Move INDFn to WREG, Indexed Indirect.
n, mm
Move WREG to Indirect FSRn with pre/post inc/dec
modifier, mm
None 2, 3
None
MOVWI
k[n]
Move WREG to INDFn, Indexed Indirect.
2
Note:ꢀ
1. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
2. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will
require one additional instruction cycle.
3. Details on MOVIWand MOVWIinstruction descriptions are available in the next section.
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Instruction Set Summary
29.2.1 Standard Instruction Set
ADDFSR
Add Literal to FSRn
Syntax:
[ label ] ADDFSR FSRn, k
-32 ≤ k ≤ 31;
n ∈ [ 0, 1]
Operands:
Operation:
FSR(n) + k → FSR(n)
None
Status
Affected:
The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.
FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to
wrap-around.
Description:
ADDLW
ADD literal to W
Syntax:
[ label ] ADDLW k
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 255
(W) + k → (W)
C, DC, Z
The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
ADDWF
ADD W to f
Syntax:
[ label ] ADDWF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) + (f) → dest
Status Affected: C, DC, Z
Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
Description:
ADDWFC
ADD W and CARRY bit to f
Syntax:
[ label ] ADDWFC f {,d}
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) + (f) + (C) → dest
C, DC, Z
Status Affected:
Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.
Description:
ANDLW
AND literal with W
[ label ] ANDLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
(W) .AND. k → (W)
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Instruction Set Summary
...........continued
ANDLW
AND literal with W
Status Affected:
Description:
Z
The contents of W are AND’ed with the 8-bit literal ‘k’.
The result is placed in W.
ANDWF
AND W with f
Syntax:
[ label ] ANDWF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) .AND. (f) → dest
Z
Status Affected:
AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
Description:
ASRF
Arithmetic Right Shift
Syntax:
[ label ] ASRF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f[7]) → dest[7]
(f[7:1]) → dest[6:0]
(f[0]) → C
Operation:
Status Affected:
C, Z
The contents of register ‘f’ are shifted one bit to the right through the Carry flag.
The MSb remains unchanged.
If ‘d’ is ‘0’, the result is placed in W.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
Register f → C
BCF
Bit Clear f
Syntax:
[ label ] BCF f, b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
0 → f[b]
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is cleared.
BRA
Relative Branch
[ label ] BRA label
[ label ] BRA $+k
Syntax:
-256 ≤ label - PC + ≤ 255
-256 ≤ k ≤ 255
Operands:
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Instruction Set Summary
...........continued
BRA
Relative Branch
(PC) + 1 + k → PC
None
Operation:
Status
Affected:
Add the signed 9-bit literal ‘k’ to the PC.
Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 +
k.
Description:
This instruction is a 2-cycle instruction. This branch has a limited range.
BRW
Relative Branch with W
[ label ] BRW
Syntax:
Operands:
Operation:
None
(PC) + (W) → PC
Status Affected: None
Add the contents of W (unsigned) to the PC.
Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 +
(W).
Description:
This instruction is a 2-cycle instruction.
BSF
Bit Set f
Syntax:
[ label ] BSF f, b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
1 → (f[b])
Status Affected:
Description:
None
Bit ‘b’ in register ‘f’ is set.
BTFSC
Bit Test File, Skip if Clear
Syntax:
[ label ] BTFSC f, b
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
skip if (f[b]) = 0
None
Status Affected:
If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed.
If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded,
and a NOPis executed instead, making this a 2-cycle instruction.
Description:
BTFSS
Bit Test File, Skip if Set
Syntax:
[ label ] BTFSS f, b
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
skip if (f[b]) = 1
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Instruction Set Summary
...........continued
BTFSS
Bit Test File, Skip if Set
Status Affected:
None
If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed.
If bit ‘b’ is ‘1’, then the next instruction is discarded,
Description:
and a NOPis executed instead, making this a 2-cycle instruction.
CALL
Subroutine Call
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
Operands:
(PC) + 1 → TOS,
k → PC[10:0],
Operation:
(PCLATH[6:3]) → PC[14:11]
None
Status Affected:
Call Subroutine. First, return address (PC + 1) is pushed onto the stack.
The 11-bit immediate address is loaded into PC bits [10:0].
The upper bits of the PC are loaded from PCLATH.
CALLis a 2-cycle instruction.
Description:
CALLW
Syntax:
Subroutine Call with W
[ label ] CALLW
None
Operands:
(PC) + 1 → TOS,
(W) → PC[7:0],
Operation:
(PCLATH[6:0]) → PC[14:8]
Status Affected: None
Subroutine call with W.
First, the return address (PC + 1) is pushed onto the return stack.
Then, the contents of W is loaded into PC[7:0], and the contents of PCLATH into PC[14:8].
CALLWis a 2-cycle instruction.
Description:
CLRF
Clear f
Syntax:
Operands:
[ label ] CLRF f
0 ≤ f ≤ 127
000h → f
1 → Z
Operation:
Status Affected:
Description:
Z
The contents of register ‘f’ are cleared and the Z bit is set.
CLRW
Clear W
Syntax:
Operands:
[ label ] CLRW
None
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Instruction Set Summary
...........continued
CLRW
Clear W
00h → (W)
1 → Z
Operation:
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z) is set.
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Operands:
00h → WDT,
00h → WDT prescaler,
Operation:
1 → TO,
1 → PD
Status Affected:
Description:
TO, PD
CLRWDTinstruction resets the
Watchdog Timer.
It also resets the prescaler of the WDT.
Status bits, TO and PD, are set.
COMF
Complement f
Syntax:
[ label ] COMF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(f) → dest
Z
Status Affected:
The contents of register ‘f’ are complemented.
If ‘d’ is ‘0’, the result is stored in W.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(f) – 1 → dest
Z
Status Affected:
Decrement register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
Description:
DECFSZ
Decrement f, skip if 0
[ label ] DECFSZ f, d
Syntax:
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Instruction Set Summary
...........continued
DECFSZ
Decrement f, skip if 0
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(f) – 1 → dest,
skip if result = 0
The contents of register ‘f’ are decremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction is executed.
If the result is ‘0’, then a NOPis executed instead,
making it a 2-cycle instruction.
Description:
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 2047
Syntax:
Operands:
k → PC[10:0]
PCLATH[6:3] → PC[14:11]
Operation:
Status Affected:
None
GOTOis an unconditional branch.
The 11-bit immediate value is loaded into PC bits [10:0].
The upper bits of PC are loaded from PCLATH[4:3].
GOTOis a 2-cycle instruction.
Description:
INCF
Increment f
Syntax:
[ label ] INCF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(f) + 1 → dest
Z
Status Affected:
The contents of register ‘f’ are incremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
Description:
INCFSZ
Increment f, skip if 0
Syntax:
[ label ] INCFSZ f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f) + 1 → dest,
skip if result = 0
Operation:
Status Affected:
None
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Instruction Set Summary
...........continued
INCFSZ
Increment f, skip if 0
The contents of register ‘f’ are incremented.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
If the result is ‘1’, the next instruction is executed.
If the result is ‘0’, a NOPis executed instead,
making it a 2-cycle instruction.
Description:
IORLW
Inclusive OR literal with W
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
Description:
(W) .OR. k → (W)
Z
The contents of W are ORed with the 8-bit literal ‘k’.
The result is placed in W.
IORWF
Inclusive OR W with f
Syntax:
IORWF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) .OR. (f) → dest
Z
Status Affected:
Inclusive OR the W register with register ‘f’.
If ‘d’ is ‘0’, the result is placed in the W register.
If ‘d’ is ‘1’, the result is placed back in register ‘f’.
Description:
LSLF
Logical Left Shift
Syntax:
[ label ] LSLF f {,d}
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f[7]) → C
(f[6:0]) → dest[7:1]
Operation:
0 → dest[0]
C, Z
Status Affected:
The contents of register ‘f’ are shifted one bit to the left through the Carry flag.
A ‘0’ is shifted into the LSb.
If ‘d’ is ‘0’, the result is placed in W.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
C ← Register f ← 0
LSRF
Logical Right Shift
Syntax:
[ label ] LSRF f {,d}
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Instruction Set Summary
...........continued
LSRF
Logical Right Shift
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 → dest[7]
(f[7:1]) → dest[6:0],
Operation:
(f[0]) → C
C, Z
Status Affected:
The contents of register ‘f’ are shifted one bit to the right through the Carry flag.
A ‘0’ is shifted into the MSb.
If ‘d’ is ‘0’, the result is placed in W.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
0 → register f → C
MOVF
Move f
Syntax:
[ label ] MOVF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
f → dest
Z
Status Affected:
The contents of register f is moved to a destination dependent upon the status of d.
If d = 0, destination is W register.
If d = 1, the destination is file register f itself.
Description:
d = 1is useful to test a file register since status flag Z is affected.
Words:
Cycles:
1
1
Example:
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
MOVIW
Move INDFn to W
[ label ] MOVIW ++FSRn
[ label ] MOVIW --FSRn
[ label ] MOVIW FSRn++
[ label ] MOVIW FSRn--
[ label ] MOVIW k[FSRn]
Syntax:
n ∈ [0,1]
mm ∈ [00,01,10,11]
Operands:
-32 ≤ k ≤ 31
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Instruction Set Summary
...........continued
MOVIW
Move INDFn to W
INDFn → (W)
Effective address is determined by
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Operation:
After the Move, the FSR value will be either:
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Z
MODE
SYNTAX
mm
00
01
10
11
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
Status
Affected:
This instruction is used to move data between W and one of the indirect registers (INDFn).
Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.
The INDFn registers are not physical registers.
Any instruction that accesses an INDFn register actually accesses the register at the address
specified by the FSRn.
Description:
FSRn is limited to the range 0000h - FFFFh.
Incrementing/decrementing it beyond these bounds will cause it to wrap-around.
MOVLB
Move literal to BSR
Syntax:
[ label ] MOVLB k
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 127
k → BSR
None
The 6-bit literal ‘k’ is loaded into the Bank Select Register (BSR).
MOVLP
Move literal to PCLATH
Syntax:
[ label ] MOVLP k
Operands:
Operation:
Status Affected:
Description:
0 ≤ k ≤ 127
k → PCLATH
None
The 7-bit literal ‘k’ is loaded into the PCLATH register.
MOVLW
Syntax:
Move literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Operands:
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Instruction Set Summary
...........continued
MOVLW
Move literal to W
k → (W)
Operation:
Status Affected:
Description:
None
The 8-bit literal ‘k’ is loaded into W register.
The “don’t cares” will assemble as ‘0’s.
Words:
Cycles:
1
1
Example:
MOVLW
5Ah
After Instruction
W = 5Ah
MOVWF
Move W to f
Syntax:
[ label ] MOVWF f
Operands:
Operation:
Status Affected:
Description:
Words:
0 ≤ f ≤ 127
(W) → f
None
Move data from W to register ‘f’.
1
1
Cycles:
Example:
MOVWF
LATA
Before Instruction
LATA = FFh
W = 4Fh
After Instruction
LATA = 4Fh
W = 4Fh
MOVWI
Move W to INDFn
[ label ] MOVWI ++FSRn
[ label ] MOVWI --FSRn
[ label ] MOVWI FSRn++
[ label ] MOVWI FSRn--
[ label ] MOVWI k[FSRn]
Syntax:
n ∈ [0,1]
mm ∈ [00,01,10,11]
Operands:
-32 ≤ k ≤ 31
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Instruction Set Summary
...........continued
MOVWI
Move W to INDFn
(W) → INDFn
Effective address is determined by
•
•
•
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
Operation:
After the Move, the FSR value will be either:
•
•
•
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
None
MODE
SYNTAX
mm
00
01
10
11
Preincrement
Predecrement
Postincrement
Postdecrement
++FSRn
--FSRn
FSRn++
FSRn--
Status
Affected:
This instruction is used to move data between W and one of the indirect registers (INDFn).
Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.
The INDFn registers are not physical registers.
Any instruction that accesses an INDFn register actually accesses the register at the address
specified by the FSRn.
Description:
FSRn is limited to the range 0000h-FFFFh.
Incrementing/decrementing it beyond these bounds will cause it to wrap-around.
The increment/decrement operation on FSRn WILL NOT affect any Status bits.
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
Operation:
Status Affected:
Description:
Words:
No operation
None
No operation.
1
Cycles:
1
NOP
Example:
None.
RESET
Software Reset
[ label ] RESET
None
Syntax:
Operands:
Operation:
Execute a device Reset.
Resets the RI flag of the PCON register.
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Instruction Set Summary
...........continued
RESET
Software Reset
Status Affected:
Description:
None
This instruction provides a way to execute a hardware Reset by software.
RETFIE
Syntax:
Return from Interrupt
[ label ] RETFIE k
None
Operands:
(TOS) → PC,
1 → GIE
Operation:
Status Affected:
None
Return from Interrupt.
Stack is POPed and Top-of-Stack (TOS) is loaded in the PC.
Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON[7]).
This is a 2-cycle instruction.
Description:
Words:
Cycles:
1
2
Example:
RETFIE
After Interrupt
PC = TOS
GIE = 1
RETLW
Syntax:
Return literal to W
[ label ] RETLW k
0 ≤ k ≤ 255
Operands:
k → (W),
(TOS) → PC,
Operation:
Status Affected:
None
The W register is loaded with the 8-bit literal ‘k’.
The program counter is loaded from the top of the stack (the return address).
This is a 2-cycle instruction.
Description:
Words:
Cycles:
1
2
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Instruction Set Summary
Example:
CALL TABLE
; W contains table
; offset value
; W now has
; table value
:
TABLE
ADDWF PC
RETLW k1
RETLW k2
:
; W = offset
; Begin table
;
:
RETLW kn
; End of table
Before Instruction
W = 07h
After Instruction
W = value of k8
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
Operands:
Operation:
(TOS) → PC,
Status Affected: None
Encoding:
0000
0000
0001
001s
Return from subroutine.
Description:
The stack is POPped and the top of the stack (TOS) is loaded into the Program Counter.
This is a 2-cycle instruction.
RLF
Rotate Left f through Carry
Syntax:
[ label ] RLF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f[n]) → dest[n + 1],
(f[7]) → C,
Operation:
(C) → dest[0]
C
Status Affected:
Encoding:
0011
01da
ffff
ffff
The contents of register ‘f’ are rotated one bit to the left through the CARRY flag.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is stored back in register ‘f’ (default).
Description:
register f
C
Words:
Cycles:
1
1
DS40002195A-page 351
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Instruction Set Summary
Example:
RLF
REG1, 0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 1100 1100
C = 1
RRF
Rotate Right f through Carry
Syntax:
[ label ] RRF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f[n]) → dest[n – 1],
(f[0]) → C,
Operation:
(C) → dest[7]
C
Status Affected:
The contents of register ‘f’ are rotated one bit to the right through the CARRY flag.
If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in register ‘f’ (default).
Description:
register f
C
SLEEP
Enter Sleep mode
[ label ] SLEEP
None
Syntax:
Operands:
00h → WDT,
0 → WDT prescaler,
Operation:
1 → TO,
0 → PD
Status Affected:
Description:
TO, PD
The Power-down Status bit (PD) is cleared.
The Time-out Status bit (TO) is set.
Watchdog Timer and its prescaler are cleared.
SUBLW
Subtract W from literal
Syntax:
[ label ] SUBLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
k – (W) → (W)
C, DC, Z
DS40002195A-page 352
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Instruction Set Summary
...........continued
SUBLW
Subtract W from literal
The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’.
The result is placed in the W register.
C =0, W > k
Description
C = 1, W ≤ k
DC = 0, W[3:0] > k[3:0]
DC = 1, W[3:0] ≤ k[3:0]
SUBWF
Subtract W from f
Syntax:
[ label ] SUBWF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(f) - (W) → (dest)
C, DC, Z
Status Affected:
Subtract (2’s complement method) W register from register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
If ‘d’ is ‘1’, the result is stored back in register ‘f.
C =0, W > f
Description
C = 1, W ≤ f
DC = 0, W[3:0] > f[3:0]
DC = 1, W[3:0] ≤ f[3:0]
SUBWFB
Subtract W from f with Borrow
Syntax:
[ label ] SUBFWB f {,d}
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) – (f) – (B) → dest
C, DC, Z
Status Affected:
Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method).
If ‘d’ is ‘0’, the result is stored in W.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
(f[3:0]) → dest[7:4],
(f[7:4]) → dest[3:0]
Operation:
Status Affected:
None
DS40002195A-page 353
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Instruction Set Summary
...........continued
SWAPF
Swap Nibbles in f
The upper and lower nibbles of register ‘f’ are exchanged.
If ‘d’ is ‘0’, the result is placed in W.
Description:
If ‘d’ is ‘1’, the result is placed in register ‘f’ (default).
TRIS
Load TRIS Register with W
[ label ] TRIS f
Syntax:
Operands:
Operation:
Status Affected:
5 ≤ f ≤ 7
(W) → TRIS register ‘f’
None
Move data from W register to TRIS register.
When ‘f’ = 5, TRISA is loaded.
When ‘f’ = 6, TRISB is loaded.
Description:
When ‘f’ = 7, TRISC is loaded.
XORLW
Exclusive OR literal with W
[ label ] XORLW k
0 ≤ k ≤ 255
Syntax:
Operands:
Operation:
Status Affected:
(W) .XOR. k → (W)
Z
The contents of W are XORed with the 8-bit literal ‘k’.
The result is placed in W.
Description:
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORWF f, d
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) .XOR. (f) → dest
Z
Status Affected:
Exclusive OR the contents of the W register with register ‘f’.
If ‘d’ is ‘0’, the result is stored in the W register.
Description:
If ‘d’ is ‘1’, the result is stored back in register ‘f’.
DS40002195A-page 354
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
™
™
ICSP - In-Circuit Serial Programming
™
™
30.
ICSP - In-Circuit Serial Programming
ICSP programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can
be done after the assembly process, allowing the device to be programmed with the most recent firmware or a
custom firmware. Five pins are needed for ICSP programming:
•
•
•
•
•
ICSPCLK
ICSPDAT
MCLR/VPP
VDD
VSS
In Program/Verify mode the program memory, User IDs and the Configuration bits are programmed through serial
communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is
the clock input. For more information on ICSP refer to the “Family Programming Specification”
30.1
30.2
High-Voltage Programming Entry Mode
The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low
then raising the voltage on MCLR/VPP to VIHH
.
Low-Voltage Programming Entry Mode
The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without
high voltage. When the LVP Configuration bit is set to ‘1’, the low-voltage ICSP programming entry is enabled. To
disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’.
Entry into the Low-Voltage Programming Entry mode requires the following steps:
1. MCLR is brought to Vil.
2. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK.
Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be
maintained.
If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be
disabled. See the MCLR Section for more information.
The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode.
30.3
Common Programming Interfaces
Connection to a target device is typically done through an ICSP header. A commonly found connector on
development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 30-1.
DS40002195A-page 355
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
™
™
ICSP - In-Circuit Serial Programming
Figure 30-1.ꢀICD RJ-11 Style Connector Interface
ICSPDAT
NC
ICSPCLK
2 4 6
1 3
V
DD
5
Target
PC Board
VPP/MCLR
VSS
Bottom Side
Pin Description
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
™
Another connector often found in use with the PICkit programmers is a standard 6-pin header with 0.1 inch spacing.
Refer to Figure 30-2.
For additional interface recommendations, refer to the specific device programmer manual prior to PCB design.
It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of
isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even
jumpers. See Figure 30-3 for more information.
™
Figure 30-2.ꢀPICkit Programmer Style Connector Interface
Pin 1 Indicator
1
2
3
4
5
6
DS40002195A-page 356
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
™
™
ICSP - In-Circuit Serial Programming
Pin Description(1)
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
Note:ꢀ
:
1. The 6-pin header (0.100" spacing) accepts 0.025" square pins.
™
Figure 30-3.ꢀTypical Connection for ICSP Programming
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
VSS
MCLR/VPP
VSS
Data
ICSPDAT
ICSPCLK
Clock
*
*
*
To Normal Connections
Isolation devices (as required).
DS40002195A-page 357
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register Summary
31.
Register Summary
Address
Name
Bit Pos.
0x00
0x01
0x02
0x03
INDF0
INDF1
PCL
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
INDF0[7:0]
INDF1[7:0]
PCL[7:0]
STATUS
TO
PD
Z
DC
C
FSR0[7:0]
FSR0[15:8]
FSR1[7:0]
FSR1[15:8]
0x04
0x06
FSR0
FSR1
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
...
BSR
BSR[5:0]
WREG
WREG[7:0]
PCLATH
Reserved
PORTA
PORTB
PORTC
PCLATH[6:0]
7:0
7:0
7:0
RA5
RB5
RC5
RA4
RB4
RC4
RA3
RA2
RC2
RA1
RC1
RA0
RC0
RB7
RC7
RB6
RC6
RC3
Reserved
0x11
0x12
0x13
0x14
0x15
...
TRISA
TRISB
TRISC
7:0
7:0
7:0
TRISA5
TRISB5
TRISC5
TRISA4
TRISB4
TRISC4
Reserved
TRISC3
TRISA2
TRISC2
TRISA1
TRISC1
TRISA0
TRISC0
TRISB7
TRISC7
TRISB6
TRISC6
Reserved
0x17
0x18
0x19
0x1A
0x1B
...
LATA
LATB
LATC
7:0
7:0
7:0
LATA5
LATB5
LATC5
LATA4
LATB4
LATC4
LATA2
LATC2
LATA1
LATC1
LATA0
LATC0
LATB7
LATC7
LATB6
LATC6
LATC3
Reserved
0x99
0x9A
CPCON
ADRES
7:0
7:0
15:8
7:0
7:0
7:0
CPON[1:0]
CPT
GO
CPRDY
ON
ADRES[7:0]
0x9B
ADRES[15:8]
0x9D
0x9E
ADCON0
ADCON1
ADACT
CHS[5:0]
FM
CS[2:0]
PREF[1:0]
0x9F
ACT[3:0]
0xA0
...
Reserved
0x010B
0x010C
0x010D
0x010E
0x010F
0x0110
...
RB4I2C
RB6I2C
RC0I2C
RC1I2C
7:0
7:0
7:0
7:0
SLEW[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
SLEW[1:0]
SLEW[1:0]
SLEW[1:0]
Reserved
0x0118
0x0119
0x011A
RC1REG
TX1REG
7:0
7:0
7:0
15:8
7:0
7:0
7:0
RCREG[7:0]
TXREG[7:0]
SPBRG[7:0]
SPBRG[15:8]
0x011B
SP1BRG
0x011D
0x011E
0x011F
0x0120
...
RC1STA
TX1STA
SPEN
CSRC
RX9
TX9
SREN
TXEN
CREN
ADDEN
SENDB
BRG16
FERR
BRGH
OERR
TRMT
WUE
RX9D
TX9D
SYNC
SCKP
BAUD1CON
ABDOVF
RCIDL
ABDEN
Reserved
0x018B
DS40002195A-page 358
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register Summary
...........continued
Address
Name
Bit Pos.
0x018C
0x018D
0x018E
0x018F
0x0190
0x0191
0x0192
0x0193
...
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BUF[7:0]
ADD[7:0]
MSK[6:0]
MSK0
BF
SMP
WCOL
GCEN
ACKTIM
CKE
SSPOV
ACKSTAT
PCIE
D/A
P
S
R/W
SSPM[3:0]
UA
SSPEN
ACKDT
SCIE
CKP
ACKEN
BOEN
RCEN
PEN
RSEN
AHEN
SEN
SDAHT
SBCDE
DHEN
Reserved
0x020B
7:0
15:8
7:0
7:0
7:0
7:0
TMR1[7:0]
TMR1[15:8]
0x020C
TMRx
0x020E
0x020F
0x0210
0x0211
0x0212
...
TxCON
TxGCON
TxGATE
TxCLK
CKPS[1:0]
SYNC
GVAL
RD16
ON
GE
GPOL
GTM
GSPM
GGO/DONE
GSS[4:0]
CS[4:0]
Reserved
0x028B
0x028C
0x028D
0x028E
0x028F
0x0290
0x0291
0x0292
...
TxTMR
TxPR
7:0
7:0
7:0
7:0
7:0
7:0
T2TMR[7:0]
T2PR[7:0]
TxCON
TxHLT
ON
CKPS[2:0]
CSYNC
OUTPS[3:0]
MODE[4:0]
PSYNC
CPOL
TxCLKCON
TxRST
CS[2:0]
RSEL[3:0]
Reserved
0x030B
7:0
15:8
7:0
CCPR[7:0]
0x030C
CCPR1
CCPR[15:8]
0x030E
0x030F
CCP1CON
CCP1CAP
EN
EN
OUT
OUT
OUT
OUT
FMT
MODE[3:0]
MODE[3:0]
7:0
CTS[1:0]
CTS[1:0]
7:0
CCPR[7:0]
0x0310
CCPR2
15:8
7:0
CCPR[15:8]
0x0312
0x0313
CCP2CON
CCP2CAP
FMT
7:0
7:0
DCL[1:0]
0x0314
PWM3DC
15:8
7:0
DCH[7:0]
DCH[7:0]
0x0316
0x0317
PWM3CON
Reserved
EN
EN
POL
POL
7:0
15:8
7:0
DCL[1:0]
0x0318
PWM4DC
0x031A
0x031B
...
PWM4CON
Reserved
0x059B
0x059C
0x059D
0x059E
0x059F
0x05A0
...
TMR0L
TMR0H
T0CON0
T0CON1
7:0
7:0
7:0
7:0
TMR0L[7:0]
TMR0H[7:0]
EN
OUT
MD16
OUTPS[3:0]
CKPS[3:0]
CS[2:0]
ASYNC
Reserved
0x070B
0x070C
0x070D
0x070E
0x070F
...
PIR0
PIR1
PIR2
7:0
7:0
7:0
TMR0IF
TMR1IF
IOCIF
RC1IF
INTF
ADIF
CCP1IF
CCP2IF
TMR2IF
NVMIF
TX1IF
BCL1IF
SSP1IF
TMR1GIF
Reserved
0x0715
DS40002195A-page 359
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register Summary
...........continued
Address
Name
Bit Pos.
0x0716
0x0717
0x0718
0x0719
...
PIE0
PIE1
PIE2
7:0
7:0
7:0
TMR0IE
TMR1IE
IOCIE
RC1IE
INTE
ADIE
CCP1IE
CCP2IE
TMR2IE
NVMIE
TX1IE
BCL1IE
SSP1IE
TMR1GIE
Reserved
WDTCON
Reserved
0x080B
0x080C
0x080D
...
7:0
CS
PS[4:0]
SEN
0x0810
0x0811
0x0812
0x0813
0x0814
0x0815
...
BORCON
Reserved
PCON0
7:0
SBOREN
STKOVF
BORRDY
BOR
7:0
7:0
STKUNF
RWDT
RMCLR
RI
POR
PCON1
MEMV
Reserved
0x0819
7:0
15:8
7:0
NVMADR[7:0]
0x081A
0x081C
NVMADR
NVMDAT
NVMADR[14:8]
NVMDAT[7:0]
15:8
7:0
NVMDAT[13:8]
0x081E
0x081F
0x0820
...
NVMCON1
NVMCON2
NVMREGS
LWLO
FREE
WRERR
WREN
WR
RD
7:0
NVMCON2[7:0]
Reserved
0x088D
0x088E
0x088F
0x0890
0x0891
0x0892
0x0893
0x0894
...
OSCCON
Reserved
OSCSTAT
OSCEN
7:0
COSC[1:0]
7:0
7:0
7:0
7:0
HFOR
MFOR
LFOR
ADOR
SFOR
HFOEN
MFOEN
LFOEN
ADOEN
OSCTUNE
OSCFRQ
TUN[5:0]
FRQ[2:0]
Reserved
FVRCON
Reserved
0x090B
0x090C
0x090D
...
7:0
FVREN
FVRRDY
ADFVR[1:0]
0x1E8F
0x1E90
0x1E91
0x1E92
0x1E93
0x1E94
...
INTPPS
T0CKIPPS
T1CKIPPS
T1GPPS
7:0
7:0
7:0
7:0
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
Reserved
T2INPPS
Reserved
0x1E9B
0x1E9C
0x1E9D
...
7:0
PORT[1:0]
PIN[2:0]
0x1EA0
0x1EA1
0x1EA2
0x1EA3
...
CCP1PPS
CCP2PPS
7:0
7:0
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
Reserved
0x1EC2
0x1EC3
0x1EC4
ADACTPPS
Reserved
7:0
PORT[1:0]
PIN[2:0]
0x1EC5
0x1EC6
SSP1CLKPPS
SSP1DATPPS
7:0
7:0
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
DS40002195A-page 360
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Register Summary
...........continued
Address
Name
Bit Pos.
0x1EC7
0x1EC8
...
SSP1SSPPS
7:0
PORT[1:0]
PIN[2:0]
Reserved
0x1ECA
0x1ECB
0x1ECC
0x1ECD
...
RX1PPS
TX1PPS
7:0
7:0
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
Reserved
0x1F0F
0x1F10
0x1F11
0x1F12
0x1F13
0x1F14
0x1F15
0x1F16
...
RA0PPS
RA1PPS
RA2PPS
Reserved
RA4PPS
RA5PPS
7:0
7:0
7:0
RA0PPS[5:0]
RA1PPS[5:0]
RA2PPS[5:0]
7:0
7:0
RA4PPS[5:0]
RA5PPS[5:0]
Reserved
0x1F1B
0x1F1C
0x1F1D
0x1F1E
0x1F1F
0x1F20
0x1F21
0x1F22
0x1F23
0x1F24
0x1F25
0x1F26
0x1F27
0x1F28
...
RB4PPS
RB5PPS
RB6PPS
RB7PPS
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS
RC7PPS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RB4PPS[5:0]
RB5PPS[5:0]
RB6PPS[5:0]
RB7PPS[5:0]
RC0PPS[5:0]
RC1PPS[5:0]
RC2PPS[5:0]
RC3PPS[5:0]
RC4PPS[5:0]
RC5PPS[5:0]
RC6PPS[5:0]
RC7PPS[5:0]
Reserved
0x1F37
0x1F38
0x1F39
0x1F3A
0x1F3B
0x1F3C
0x1F3D
0x1F3E
0x1F3F
0x1F40
...
ANSELA
WPUA
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
ANSELA5
WPUA5
ODCA5
SLRA5
ANSELA4
ANSELA2
ANSELA1
WPUA1
ODCA1
SLRA1
ANSELA0
WPUA0
ODCA0
SLRA0
WPUA4
ODCA4
SLRA4
WPUA3
WPUA2
ODCA2
SLRA2
ODCONA
SLRCONA
INLVLA
IOCAP
INLVLA5
IOCAP5
IOCAN5
IOCAF5
INLVLA4
IOCAP4
IOCAN4
IOCAF4
INLVLA3
IOCAP3
IOCAN3
IOCAF3
INLVLA2
IOCAP2
IOCAN2
IOCAF2
INLVLA1
IOCAP1
IOCAN1
IOCAF1
INLVLA0
IOCAP0
IOCAN0
IOCAF0
IOCAN
IOCAF
Reserved
0x1F42
0x1F43
0x1F44
0x1F45
0x1F46
0x1F47
0x1F48
0x1F49
0x1F4A
0x1F4B
...
ANSELB
WPUB
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
ANSELB7
WPUB7
ODCB7
SLRB7
ANSELB6
WPUB6
ODCB6
SLRB6
ANSELB5
WPUB5
ODCB5
SLRB5
ANSELB4
WPUB4
ODCB4
SLRB4
ODCONB
SLRCONB
INLVLB
IOCBP
INLVLB7
IOCBP7
IOCBN7
IOCBF7
INLVLB6
IOCBP6
IOCBN6
IOCBF6
INLVLB5
IOCBP5
IOCBN5
IOCBF5
INLVLB4
IOCBP4
IOCBN4
IOCBF4
IOCBN
IOCBF
Reserved
0x1F4D
0x1F4E
0x1F4F
0x1F50
0x1F51
ANSELC
WPUC
7:0
7:0
7:0
7:0
ANSELC7
WPUC7
ODCC7
SLRC7
ANSELC6
WPUC6
ODCC6
SLRC6
ANSELC5
WPUC5
ODCC5
SLRC5
ANSELC4
WPUC4
ODCC4
SLRC4
ANSELC3
WPUC3
ODCC3
SLRC3
ANSELC2
WPUC2
ODCC2
SLRC2
ANSELC1
WPUC1
ODCC1
SLRC1
ANSELC0
WPUC0
ODCC0
SLRC0
ODCONC
SLRCONC
DS40002195A-page 361
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Register Summary
...........continued
Address
Name
Bit Pos.
0x1F52
0x1F53
0x1F54
0x1F55
0x1F56
...
INLVLC
IOCCP
IOCCN
IOCCF
7:0
7:0
7:0
7:0
INLVLC7
IOCCP7
IOCCN7
IOCCF7
INLVLC6
IOCCP6
IOCCN6
IOCCF6
INLVLC5
IOCCP5
IOCCN5
IOCCF5
INLVLC4
IOCCP4
IOCCN4
IOCCF4
INLVLC3
IOCCP3
IOCCN3
IOCCF3
INLVLC2
IOCCP2
IOCCN2
IOCCF2
INLVLC1
IOCCP1
IOCCN1
IOCCF1
INLVLC0
IOCCP0
IOCCN0
IOCCF0
Reserved
0x8004
7:0
15:8
7:0
MJRREV[1:0]
MNRREV[5:0]
80058005
80068006
0x8007
REVISIONID
DEVICEID
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
Reserved
Reserved
Reserved
MJRREV[5:2]
DEV[7:0]
Reserved
15:8
7:0
DEV[11:8]
RSTOSC[1:0]
FEXTOSC[1:0]
15:8
7:0
VDDAR
CLKOUTEN
MCLRE
BOREN[1:0]
WDTE[1:0]
PWRTS[1:0]
0x8008
15:8
7:0
DEBUG
LVP
STVREN
PPS1WAY
BORV
0x8009
15:8
7:0
WRTAPP
SAFEN
BBEN
BBSIZE[2:0]
WRTC
0x800A
0x800B
15:8
7:0
WRTSAF
WRTB
CP
15:8
DS40002195A-page 362
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
32.
Electrical Specifications
32.1
Absolute Maximum Ratings(†)
Parameter
Rating
Ambient temperature under bias
Storage temperature
-40°C to +125°C
-65°C to +150°C
Voltage on pins with respect to VSS
•
•
•
on VDD pin:
-0.3V to +6.5V
-0.3V to +9.0V
on MCLR pin:
on all other pins:
-0.3V to (VDD + 0.3V)
Maximum current
-40°C ≤ TA ≤ +85°C
300 mA
120 mA
250 mA
85 mA
•
on VSS pin(1)
85°C < TA ≤ +125°C
-40°C ≤ TA ≤ +85°C
85°C < TA ≤ +125°C
•
•
on VDD pin(1)
on any standard I/O pin
±25 mA
Clamp current, IK (VPIN < 0 or VPIN > VDD
Total power dissipation(2)
)
±20 mA
800 mW
Note:ꢀ
1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited
by the device package power dissipation characterizations, see “Thermal Characteristics” to calculate device
specifications.
2. Power dissipation is calculated as follows:
PDIS = VDD x {IDD - Σ IOH} + Σ {(VDD - VOH) x IOH} + Σ (VOI x IOL
)
3. Internal Power Dissipation is calculated as follows: PINTERNAL = IDD x VDD where IDD is current to run the chip
alone without driving any load on the output pins.
4. I/O Power Dissipation is calculated as follows: PI/O =Σ(IOL*VOL)+Σ(IOH*(VDD-VOH))
5. Derated Power is calculated as follows: PDER = PDMAX(TJ-TA)/θJA where TA=Ambient Temperature, TJ =
Junction Temperature.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
32.2
Standard Operating Conditions
The standard operating conditions for any device are defined as:
Parameter
Condition
Operating Voltage:
Operating Temperature:
VDDMIN ≤ VDD ≤ VDDMAX
TAMIN ≤ TA ≤ TAMAX
Parameter
Ratings
VDD — Operating Supply Voltage(1)
DS40002195A-page 363
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
...........continued
Parameter
VDDMIN (FOSC ≤ 16 MHz)
VDDMIN (FOSC ≤ 32 MHz)
VDDMAX
TA — Operating Ambient Temperature Range
Ratings
+1.8V
+2.5V
+5.5V
TA_MIN
-40°C
Industrial Temperature
TA_MAX
TA_MIN
TA_MAX
+85°C
-40°C
Extended Temperature
+125°C
Note:ꢀ
1. See Parameter D002, DC Characteristics: Supply Voltage.
Figure 32-1.ꢀVoltage Frequency Graph, -40°C ≤ TA ≤ +125°C
5.5
2.5
1.8
0
10
Frequency (MHz)
16
4
32
Note:ꢀ
1. The shaded region indicates the permissible combinations of voltage and frequency.
2. Refer to “External Clock/Oscillator Timing Requirements” section for each Oscillator mode’s supported
frequencies.
32.3
DC Characteristics
32.3.1 Supply Voltage
Table 32-1.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Supply Voltage
Characteristic
Min.
Typ.†
Max.
Units
Conditions
DS40002195A-page 364
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Characteristic
Min.
Typ.†
Max.
Units
Conditions
1.8
—
5.5
V
FOSC ≤ 16 MHz
FOSC > 16 MHz
D002
RAM Data Retention(1)
D003 VDR
VDD
2.5
1.7
—
—
5.5
—
V
V
Device in Sleep
mode
Power-on Reset Release Voltage(2)
D004 VPOR
Power-on Reset Rearm Voltage(2)
D005 VPORR
BOR disabled(3)
BOR disabled(3)
BOR disabled(3)
—
—
—
—
—
V
V
1.6
1.5
—
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05
V/ms
† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2. See the following figure, POR and POR REARM with Slow Rising VDD
.
3. See “Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications” for BOR trip point information.
Figure 32-2.ꢀPOR and POR Rearm with Slow Rising VDD
VDD
VPOR
VPORR
SVDD
VSS
(1)
NPOR
POR REARM
VSS
Note:ꢀ
1. When NPOR is low, the device is held in Reset.
DS40002195A-page 365
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
(1,2)
32.3.2 Supply Current (IDD
)
Table 32-2.ꢀ
Standard Operating Conditions (unless otherwise stated)
Device
Conditions
Param. No. Sym.
Min.
Typ.†
Max.
Units
Characteristics
VDD
Note
HFINTOSC = 16
MHz
D101
D102
IDD
—
—
1.5
2.7
—
—
mA
mA
3.0V
HFO16
HFINTOSC = 32
MHz
IDD
3.0V
HFOPLL
† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave,
from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an
impact on the current consumption.
(1,2,3)
32.3.3 Power-Down Current (IPD
)
Table 32-3.ꢀ
Standard Operating Conditions (unless otherwise stated)
Conditions
Param.
No.
Device
Characteristics
Max.
+85°C
Max.
+125°C
Sym.
Min.
Typ.†
Units
VDD
Note
D200
—
—
0.40
18
—
—
—
—
μA
μA
3.0V
3.0V
IPD
IPD Base
D200A
Low-Frequency
Internal
D201
IPD_WDT
—
0.5
—
—
μA
3.0V
Oscillator/WDT
D203
D204
IPD_FVR
IPD_BOR
FVR
—
—
40
14
—
—
—
—
μA
μA
3.0V
3.0V
Brown-out Reset
(BOR)
ADC is
converting (4)
D207
IPD_ADCA
ADC - Active
—
280
—
—
μA
3.0V
† - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is
enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit.
Max. values should be used when calculating total current consumption.
2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is
measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS
.
3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is
available.
4. ADC clock source is ADCRC.
DS40002195A-page 366
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
32.3.4 I/O Ports
Table 32-4.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Device Characteristics
Min.
Typ.†
Max.
Units
Conditions
Input Low Voltage
VIL
I/O PORT:
D300
—
—
—
—
—
—
0.8
V
V
V
4.5V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 4.5V
1.8V ≤ VDD ≤ 5.5V
•
with TTL buffer
D301
0.15 VDD
0.2 VDD
D302
•
with Schmitt Trigger
buffer
D303
D304
—
—
—
—
—
—
0.3 VDD
0.8
V
V
V
•
•
with I2C levels
2.7V ≤ VDD ≤ 5.5V
with SMBus levels
D305
MCLR
0.2 VDD
Input High Voltage
VIH
I/O PORT:
D320
2.0
—
—
—
—
—
—
V
V
V
4.5V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 4.5V
1.8V ≤ VDD ≤ 5.5V
•
with TTL buffer
D321
0.25 VDD+0.8
0.8VDD
D322
•
with Schmitt Trigger
buffer
D323
D324
0.7 VDD
2.1
—
—
—
—
—
—
V
V
V
•
•
with I2C levels
2.7V ≤ VDD ≤ 5.5V
with SMBus levels
D325
MCLR
0.8 VDD
Input Leakage Current(1)
D340
D341
D342
IIL
I/O PORTS
—
—
—
±5
±5
±125
±1000
±200
nA
nA
nA
VSS ≤ VPIN ≤VDD,
Pin at high-impedance,
85°C
VSS ≤ VPIN ≤ VDD
Pin at high-impedance,
125°C
,
MCLR(2)
±50
VSS ≤ VPIN ≤VDD,
Pin at high-impedance,
85°C
Weak Pull-up Current
D350 IPUR
Output Low Voltage
D360 VOL
25
—
120
—
200
0.6
μA
V
VDD = 3.0V, VPIN = VSS
Standard I/O PORTS
Standard I/O PORTS
IOL = 10 mA, VDD
3.0V
=
Output High Voltage
D370
VOH
VDD-0.7
—
—
5
—
V
IOH = 6 mA, VDD = 3.0V
All I/O Pins
D380
CIO
50
pF
DS40002195A-page 367
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Device Characteristics
Min.
Typ.†
Max.
Units
Conditions
† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note:ꢀ
1. Negative current is defined as current sourced by the pin.
2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal
operating conditions. Higher leakage current may be measured at different input voltages.
32.3.5 Memory Programming Specifications
Table 32-5.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param Sym.
No.
Device Characteristics
Min. Typ† Max. Units
Conditions
High Voltage Entry Programming Mode Specifications
MEM01 VIHH
Voltage on MCLR/VPP pin to enter
programming mode
7.9
—
1
9
V
(Note 2)
MEM02 IPPGM
Current on MCLR/VPP pin during
programming mode
—
—
mA (Note 2)
Programming Mode Specifications
MEM10 VBE VDD for Bulk Erase
—
—
2.7
—
—
V
(Note 3)
MEM11 IDDPGM Supply Current during
Programming operation
10
mA
Program Flash Memory Specifications
MEM30 EP
Flash Memory Cell Endurance
-40°C ≤ TA ≤ +85°C
(Note 1)
10k
—
—
E/W
MEM32 TP_RET Characteristic Retention
MEM33 VP_RD VDD for Read operation
Provided no other
specifications are violated
—
40
—
—
—
Year
V
VDDMIN
VDDMIN
VDDMAX
VDDMAX
MEM34 VP_REW VDD for Row Erase or Write
operation
V
MEM35 TP_REW Self-Timed Row Erase or Self-
Timed Write
—
2.0
—
ms
† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-
Timed Write.
2. Required only if the LVP bit of the Configuration Words is disabled.
3. Refer to the “Family Programming Specification” for more information.
DS40002195A-page 368
Preliminary Datasheet
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Electrical Specifications
32.3.6 Thermal Characteristics
Table 32-6.ꢀ
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +125°C
Param No. Sym.
Characteristic
Typ. Units Conditions
TH01
θJA
Thermal Resistance Junction to Ambient
—
—
—
—
—
—
—
—
—
150
—
—
—
—
°C/W 8-pin SOIC package
°C/W 8-pin DFN package
°C/W 14-pin SOIC package
°C/W 14-pin TSSOP package
°C/W 16-pin VQFN 3x3mm package
°C/W 20-pin PDIP package
°C/W 20-pin SSOP package
°C/W 20-pin SOIC package
°C/W 20-pin VQFN 3x3mm package
°C
TH03
TH04
TH05
TH06
TH07
Note:ꢀ
TJMAX
PD
Maximum Junction Temperature
Power Dissipation
W
W
W
W
PD = PINTERNAL+PI/O
PINTERNAL = IDD x VDD
(1)
PINTERNAL Internal Power Dissipation
PI/O
I/O Power Dissipation
Derated Power
PI/O = Σ(IOL*VOL)+Σ(IOH*(VDD-VOH))
(2)
PDER
PDER = PDMAX (TJ-TA)/θJA
1. IDD is current to run the chip alone without driving any load on the output pins.
2. TA = Ambient Temperature, TJ = Junction Temperature.
32.4
AC Characteristics
Figure 32-3.ꢀLoad Conditions
Pin
CL = 50 pF
(for all pins)
VSS
DS40002195A-page 369
Preliminary Datasheet
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Electrical Specifications
32.4.1 External Clock/Oscillator Timing Requirements
Figure 32-4.ꢀClock Timing
OS2,
OS4,
OS6
CLKIN
Q4
Q1
Q2
Q3
Q4
Q1
OS1,OS3,OS5
OS7,OS8,OS9
OS10,OS20
CLKOUT
OS21
Table 32-7.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
ECL Oscillator
Characteristic
Min.
Typ. †
Max.
Units
Conditions
OS1
OS2
FECL
Clock Frequency
Clock Duty Cycle
—
—
—
16
60
MHz
%
TECL_DC
40
ECH Oscillator
OS5
OS6
FECH
TECH_DC
Clock Frequency
Clock Duty Cycle
—
—
—
32
60
MHz
%
40
System Oscillator
OS20
OS21
OS22
FOSC
System Clock
Frequency
—
—
—
32
—
—
MHz
MHz
ns
Note 2, Note 3
FCY
Instruction
Frequency
FOSC/4
1/FCY
TCY
Instruction Period
125
Note 1
DS40002195A-page 370
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
Min.
Typ. †
Max.
Units
Conditions
* These parameters are characterized but not tested.
† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to CLKIN pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “OSC
- Oscillator Module” chapter.
3. The system clock frequency (FOSC) must meet the voltage requirements defined in the “Standard Operating
Conditions” section.
32.4.2 Internal Oscillator Parameters(1)
Table 32-8.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
Min.
Typ. †
4
Max.
Units
Conditions
Note 2
OS50
FHFOSC
Precision Calibrated
HFINTOSC
Frequency
—
—
MHz
8
12
16
32
OS51
OS52
FHFOSCLP
Low-Power
Optimized
HFINTOSC
Frequency
0.92
1.84
0.88
1.76
1
2
1
2
1.08
2.16
1.12
2.24
MHz
MHz
MHz
MHz
-40°C to 85°C
-40°C to 85°C
-40°C to 125 °C
-40°C to 125°C
FMFOSC
Internal Calibrated
MFINTOSC
—
500
—
kHz
Frequency
OS53
OS54
FLFOSC
Internal LFINTOSC
Frequency
—
—
31
2
—
—
kHz
μs
THFOSCST
HFINTOSC Wake-up
from Sleep Start-up
Time
OS56
TLFOSCST
LFINTOSC Wake-up
from Sleep Start-up
Time
—
0.2
—
ms
DS40002195A-page 371
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
Min.
Typ. †
Max.
Units
Conditions
† - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1 μF and 0.01 μF values in parallel are recommended.
2. See Figure 32-5.
Figure 32-5.ꢀPrecision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature
125
± 5%
85
± 3%
60
± 2%
0
± 5%
-40
1.8
2.0
2.3
3.5
4.0
VDD (V)
4.5
5.0
5.5
3.0
DS40002195A-page 372
Preliminary Datasheet
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Electrical Specifications
32.4.3 I/O and CLKOUT Timing Specifications
Figure 32-6.ꢀCLKOUT and I/O Timing
Fetch
Q1
Read
Q2
Execute
Q3
Cycle
Write
Q4
FOSC
IO1
IO2
IO5
CLKOUT
IO4
IO6, IO7
IO8, IO9
IO3
I/O pin
(Input)
IO10, IO11
I/O pin
(Output)
Table 32-9.ꢀI/O and CLKOUT Timing Specifications
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
Min. Typ. † Max. Units Conditions
IO1*
IO2*
IO3*
IO4*
IO5*
TCLKOUTH
CLKOUT rising edge delay (rising edge FOSC
(Q1 cycle) to falling edge CLKOUT
—
—
—
20
50
—
—
50
—
—
70
72
70
—
—
ns
ns
ns
ns
ns
TCLKOUTL
CLKOUT falling edge delay (rising edge FOSC
(Q3 cycle) to rising edge CLKOUT
TIO_VALID
Port output valid time (rising edge FOSC (Q1
cycle) to port valid)
TIO_SETUP Port input setup time (Setup time before rising
edge FOSC – Q2 cycle)
TIO_HOLD
Port input hold time (Hold time after rising edge
FOSC – Q2 cycle)
IO6*
IO7*
IO8*
IO9*
IO10*
IO11*
TIOR_SLREN Port I/O rise time, slew rate enabled
TIOR_SLRDIS Port I/O rise time, slew rate disabled
TIOF_SLREN Port I/O fall time, slew rate enabled
TIOF_SLRDIS Port I/O fall time, slew rate disabled
—
—
—
—
25
25
25
5
—
—
—
—
—
—
ns VDD = 3.0V
ns VDD = 3.0V
ns VDD = 3.0V
ns VDD = 3.0V
ns
25
5
TINT
TIOC
INT pin high or low time to trigger an interrupt
—
—
Interrupt-on-Change minimum high or low time
to trigger interrupt
ns
* - These parameters are characterized but not tested.
DS40002195A-page 373
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
32.4.4 Reset, WDT, Power-up Timer, and Brown-Out Reset Specifications
Figure 32-7.ꢀReset, Watchdog Timer, and Power-up Timer Timing
VDD
MCLR
RST01
Internal
POR
RST04
PWRT
Time-out
Internal
Reset(1)
WDT
Reset
RST03
RST02
RST02
I/O Pins
Note:ꢀ
1. Asserted low.
Figure 32-8.ꢀBrown-out Reset Timing and Characteristics
Rev. 30-000076A
4/6/2017
VDD
VBOR and VHYST
VBOR
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
RST08
Reset
RST04(1)
(due to BOR)
Note:ꢀ
1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0.
DS40002195A-page 374
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Table 32-10.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No.
Sym.
Characteristic
Min.
Typ. †
Max.
Units Conditions
RST01*
TMCLR
MCLR Pulse Width Low to
ensure Reset
2
—
—
μs
RST02*
RST03
TIOZ
I/O high-impedance from
Reset detection
—
—
—
2
μs
TWDT
Watchdog Timer Time-out
Period
16
—
ms
ms
1:512 Prescaler
RST04*
RST06
TPWRT
VBOR
Power-up Timer Period
Brown-out Reset Voltage
—
65
—
2.55
2.7
2.85
V
V
BORV = 0
BORV = 1
2.30
2.45
2.60(1)
RST07
RST08
VBORHYS
TBORDC
Brown-out Reset Hysteresis
—
—
40
3
—
—
mV
μs
Brown-out Reset Response
Time
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note:ꢀ
1. This value corresponds to VBORMAX
.
32.4.5 Analog-to-Digital Converter (ADC) Accuracy Specifications(1,2)
Table 32-11.ꢀ
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param No. Sym.
Characteristic
Resolution
Min. Typ. † Max. Units Conditions
AD01
AD02
NR
EIL
—
—
—
—
10
—
bit
Integral Error
LSb ADCREF+ = 3.0V, ADCREF- =
VSS
AD03
AD04
AD05
AD06
EDL
Differential Error
Offset Error
—
—
—
—
—
—
—
—
—
LSb ADCREF+ = 3.0V, ADCREF- =
VSS
EOFF
LSb ADCREF+ = 3.0V, ADCREF- =
VSS
EGN
Gain Error
—
LSb ADCREF+ = 3.0V, ADCREF- =
VSS
VADREF ADC Reference Voltage (ADREF 1.8
+)
VDD
V
AD07
AD08
VAIN
ZAIN
Full-Scale Range
VSS
—
—
ADREF
—
+
V
Recommended Impedance of
Analog Voltage Source
10
kΩ
AD09
RVREF ADC Voltage Reference Ladder
Impedance
—
50
—
kΩ
DS40002195A-page 375
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = 25°C
Param No. Sym.
Characteristic
Min. Typ. † Max. Units Conditions
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note:ꢀ
1. Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.
2. The ADC conversion result never decreases with an increase in the input and has no missing codes.
32.4.6 Analog-to-Digital Converter (ADC) Conversion Timing Specifications
Table 32-12.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No. Sym. Characteristic
Min. Typ. † Max. Units Conditions
AD20
AD21
AD22
TAD
ADC Clock Period
0.5
1
—
2
9
6
μs
μs
FOSC clock source
ADCRC clock source
TCNV Conversion Time
TACQ Acquisition Time
—
11
—
TAD Set of GO bit to clear of GO
bit
AD23
AD24
—
—
2
—
—
μs
THCD Sample and Hold Capacitor
Disconnect Time
—
—
FOSC clock source
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Figure 32-9.ꢀADC Conversion Timing (ADC Clock FOSC-Based)
Rev. 10-000321B
7/31/2019
BSF ADCON0, GO
1 TCY
AD22
AD23
1 TCY
1 TCY
AD20
ADC_clk
ADRES
ADIF
OLD DATA
NEW DATA
GO
DONE
Sample
Sampling Stopped
DS40002195A-page 376
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Figure 32-10.ꢀADC Conversion Timing (ADC Clock from FRC
)
Rev. 10-000328B
7/31/2019
BSF ADCON0, GO
1 TCY
AD22
AD23
(1)
2 TCY
AD21
ADC_clk
ADRES
ADIF
OLD DATA
NEW DATA
GO
DONE
Sample
Sampling Stopped
Note:ꢀ
1. If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEPinstruction to be executed.
32.4.7 Fixed Voltage Reference (FVR) Specifications
Table 32-13.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No.
FVR01
Sym.
Characteristic
Min. Typ. † Max. Units Conditions
VFVR
VFVR
VFVR
1
1x Gain (1.024V)
2x Gain (2.048V)
4x Gain (4.096V)
-4
-4
-6
—
—
—
—
60
+4
+4
+6
—
%
%
%
μs
VDD ≥ 2.5V, -40°C to 85°C
VDD ≥ 2.5V, -40°C to 85°C
VDD ≥ 4.75V, -40°C to 85°C
FVR02
2
4
FVR03
FVR04
TFVRST FVR Start-up Time
32.4.8 Timer0 and Timer1 External Clock Requirements
Table 32-14.ꢀ
Standard Operating Conditions (unless otherwise stated)
Operating Temperature: -40°C ≤ TA ≤ +125°C
Param No. Sym.
Characteristic
Min.
0.5TCY+20
10
Typ. † Max. Units Conditions
40*
41*
42*
TT0H
TT0L
TT0P
T0CKI High No Prescaler
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Pulse Width
With Prescaler
T0CKI Low
Pulse Width
No Prescaler
0.5TCY+20
10
With Prescaler
T0CKI Period
—
ns N = Prescale
value
DS40002195A-page 377
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Operating Temperature: -40°C ≤ TA ≤ +125°C
Param No. Sym.
Characteristic
Min.
Typ. † Max. Units Conditions
45*
46*
TT1H
TT1L
TT1P
T1CKI High Synchronous, No
0.5TCY+20
—
—
ns
Time
Prescaler
Synchronous, with
Prescaler
15
—
—
ns
Asynchronous
30
—
—
—
—
ns
ns
T1CKI Low
Time
Synchronous, No
Prescaler
0.5TCY+20
Synchronous, with
Prescaler
15
—
—
ns
ns
Asynchronous
30
—
—
—
—
—
47*
49*
T1CKI Input Synchronous
Period
ns N = Prescale
value
Asynchronous
60
—
—
—
ns
TCKEZTMR1 Delay from External Clock Edge to
Timer Increment
2 TOSC
7 TOSC
—
Timers in Sync
mode
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Figure 32-11.ꢀTimer0 and Timing1 External Clock Timings
Rev. 30-000079A
4/6/2017
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
DS40002195A-page 378
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
32.4.9 Capture/Compare/PWM Requirements (CCP)
Table 32-15.ꢀ
Standard Operating Conditions (unless otherwise stated)
Operating Temperature: -40°C ≤ TA ≤ +125°C
Param No. Sym.
Characteristic
Min.
Typ. † Max. Units Conditions
CC01*
CC02*
CC03*
TCC
TCC
TCC
L
CCPx Input
Low Time
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY+20
20
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
H
P
CCPx Input
High Time
0.5TCY+20
20
CCPx Input
Period
(3TCY+40)/N
N = Prescale
value
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Figure 32-12.ꢀCapture/Compare/PWM Timings (CCP)
Rev. 30-000080A
4/6/2017
CCPx
(Capture mode)
CC01
CC02
CC03
Note:ꢀ Refer to Figure 32-3 for load conditions.
32.4.10 EUSART Synchronous Transmission Requirements
Table 32-16.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No.
Sym.
Characteristic
Min. Max. Units Conditions
US120
TCKH2DT
V
SYNC XMIT (Master and Slave)
Clock high to data-out valid
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
3.0V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 5.5V
3.0V ≤ VDD ≤ 5.5V
1.8V ≤ VDD ≤ 5.5V
US121
US122
TCKRF
Clock out rise time and fall time
(Master mode)
50
TDTRF
Data-out rise time and fall time
45
50
DS40002195A-page 379
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Figure 32-13.ꢀEUSART Synchronous Transmission (Master/Slave) Timing
Rev. 30-000081A
4/6/2017
CK
US121
US121
DT
US122
US120
Note:ꢀ Refer to Figure 32-3 for load conditions.
32.4.11 EUSART Synchronous Receive Requirements
Table 32-17.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No.
Sym.
Characteristic
Min. Max. Units Conditions
US125
TDTV2CKL
SYNC RCV (Master and Slave)
Data-setup before CK ↓ (DT hold time)
10
—
ns
US126
TCKL2DTL
Data-hold after CK ↓ (DT hold time)
15
—
ns
Figure 32-14.ꢀEUSART Synchronous Receive (Master/Slave) Timing
Rev. 30-000082A
4/6/2017
CK
US125
DT
US126
Note:ꢀ Refer to Figure 32-3 for load conditions.
32.4.12 SPI Mode Requirements
Table 32-18.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
TSSL2SCH, SS↓ to SCK↓ or SCK↑ input
TSSL2SC
Min.
Typ. † Max. Units Conditions
SP70*
2.25*TCY
—
—
ns
L
SP71*
SP72*
SP73*
TSC
H
SCK input high time (Slave
mode)
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TSCL
SCK input low time (Slave
mode)
TDIV2SCH,
TDIV2SC
Setup time of SDI data
input to SCK edge
L
SP74*
TSCH2DIL,
TSCL2DIL
Hold time of SDI data input
to SCK edge
100
—
—
ns
DS40002195A-page 380
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param No. Sym.
Characteristic
Min.
Typ. † Max. Units Conditions
SP75*
TDO
R
SDO data output rise time
—
25
50
ns
1.8V ≤ VDD
5.5V
≤
SP76*
SP77*
TDO
F
SDO data output fall time
—
10
—
25
50
ns
ns
TSSH2DO
Z
SS↑ to SDO output high-
impedance
10
SP78*
SP79*
SP80*
TSC
R
SCK output rise time
(Master mode)
—
—
—
25
10
—
50
25
ns
ns
ns
1.8V ≤ VDD
5.5V
≤
≤
TSCF
SCK output fall time
(Master mode)
TSCH2DOV, SDO data output valid after
SCK edge
145
1.8V ≤ VDD
5.5V
TSCL2DO
V
SP81*
TDOV2SCH, SDO data output setup to
SCK edge
1 TCY
—
—
ns
TDOV2SC
L
SP82*
SP83*
TSSL2DO
V
SDO data output valid after
SS↓ edge
—
—
—
50
—
ns
ns
TSCH2SSH, SS ↑after SCK edge
TSCL2SS
1.5 TCY + 40
H
* - These parameters are characterized but not tested.
† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS40002195A-page 381
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Figure 32-15.ꢀSPI Master Mode Timing (CKE = 0, SMP = 0)
Rev. 30-000083A
4/6/2017
SS
SP81
SCK
(CKP = 0)
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
LSb In
SP74
SP73
Note:ꢀ Refer to Figure 32-3 for load conditions.
Figure 32-16.ꢀSPI Master Mode Timing (CKE = 1, SMP = 1)
Rev. 30-000084A
4/6/2017
SS
SP81
SCK
(CKP = 0)
SP71
SP73
SP72
SP79
SP78
SCK
(CKP = 1)
SP80
LSb
MSb
bit 6 - - - - - -1
SDO
SDI
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note:ꢀ Refer to Figure 32-3 for load conditions.
DS40002195A-page 382
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Figure 32-17.ꢀSPI Slave Mode Timing (CKE = 0)
Rev. 30-000085A
4/6/2017
SS
SP70
SCK
(CKP = 0)
SP83
SP71
SP72
SP78
SP79
SP79
SCK
(CKP = 1)
SP78
LSb
SP80
MSb
SDO
SDI
bit 6 - - - - - -1
SP75, SP76
bit 6 - - - -1
SP77
MSb In
SP74
SP73
LSb In
Note:ꢀ Refer to Figure 32-3 for load conditions.
Figure 32-18.ꢀSPI Slave Mode Timing (CKE = 1)
Rev. 30-000086A
4/6/2017
SP82
SS
SP70
SP83
SCK
(CKP = 0)
SP72
SP71
SCK
(CKP = 1)
SP80
MSb
bit 6 - - - - - -1
LSb
SDO
SDI
SP77
SP75, SP76
bit 6 - - - -1
MSb In
SP74
LSb In
Note:ꢀ Refer to Figure 32-3 for load conditions.
DS40002195A-page 383
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
32.4.13 I2C Bus Start/Stop Bits Requirements
Table 32-19.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Characteristic
TSU:STA Start condition 100 kHz mode 4700
Setup time
Min. Typ. † Max. Units Conditions
SP90*
SP91*
SP92*
SP93*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
Start condition
400 kHz mode 600
THD:STA Start condition 100 kHz mode 4000
Hold time
ns After this period, the first clock
pulse is generated
400 kHz mode 600
TSU:STO Stop condition 100 kHz mode 4700
Setup time
ns
ns
400 kHz mode 600
THD:STO Stop condition 100 kHz mode 4000
Hold time
400 kHz mode 600
* - These parameters are characterized but not tested.
Figure 32-19.ꢀI2C Bus Start/Stop Bits Timing
Rev. 30-000087A
4/6/2017
SCL
SP93
SP91
SP90
SP92
SDA
Stop
Condition
Start
Condition
Note:ꢀ Refer to Figure 32-3 for load conditions.
32.4.14 I2C Bus Data Requirements
Table 32-20.ꢀ
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
SP100* THIGH
Characteristic
Min.
Max.
Units
Conditions
Clock high
time
100 kHz
mode
4.0
—
μs
Device must
operate at a
minimum of 1.5
MHz
400 kHz
mode
0.6
—
—
μs
Device must
operate at a
minimum of 10
MHz
SSP module
1.5TCY
DS40002195A-page 384
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
...........continued
Standard Operating Conditions (unless otherwise stated)
Param. No. Sym.
Characteristic
Min.
Max.
Units
Conditions
SP101*
TLOW
Clock low
time
100 kHz
mode
4.7
—
μs
Device must
operate at a
minimum of 1.5
MHz
400 kHz
mode
1.3
—
μs
Device must
operate at a
minimum of 10
MHz
SSP module
1.5TCY
—
—
SP102*
SP103*
SP106*
SP107*
SP109*
SP110*
SP111
TR
SDA and
SCL rise
time
100 kHz
mode
1000
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
μs
μs
pF
400 kHz
mode
20 + 0.1CB
300
250
250
—
CB is specified to
be from 10-400 pF
TF
SDA and
SCL fall time mode
100 kHz
—
400 kHz
mode
20 + 0.1CB
CB is specified to
be from 10-400 pF
THD:DAT
TSU:DAT
TAA
Data input
hold time
100 kHz
mode
0
0
400 kHz
mode
0.9
—
Data input
setup time
100 kHz
mode
250
100
—
Note 2
Note 1
400 kHz
mode
—
Output valid 100 kHz
from clock
3500
—
mode
400 kHz
mode
—
TBUF
Bus free time 100 kHz
mode
4.7
1.3
—
—
Time the bus must
be free before a
new transmission
can start
400 kHz
mode
—
CB
Bus capacitive loading
400
* - These parameters are characterized but not tested.
Note:ꢀ
1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
DS40002195A-page 385
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Electrical Specifications
Figure 32-20.ꢀI2C Bus Data Timing
Rev. 30-000088A
4/6/2017
SP100
SP106
SP102
SP103
SP101
SCL
SP90
SP91
SP107
SP92
SDA
In
SP110
SP109
SP109
SDA
Out
Note:ꢀ Refer to Figure 32-3 for load conditions.
DS40002195A-page 386
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
DC and AC Characteristics Graphs and Tables
33.
DC and AC Characteristics Graphs and Tables
Graphs and tables are not available at this time.
DS40002195A-page 387
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
34.
Packaging Information
Package Marking Information
Rev. 30-009000A
5/17/2017
Legend: XX...X Customer-specific information or Microchip part number
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
®
e
P
3
b- free JEDEC
designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
8-Lead DFN (3x3x0.9 mm)
Example
15213
1950
017
XXXX
YYWW
NNN
PIN 1
PIN 1
8-Lead SOIC (3.90 mm)
Example
16F15213
e
3
SN
1950
017
NNN
DS40002195A-page 388
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Rev. 30-009014B
09/21/2017
14-Lead TSSOP (4.4 mm)
Example
16F15224
XXXXXXXX
YYWW
e
3
1950
017
NNN
Rev. 30-009014C
09/21/2017
14-Lead SOIC (3.90 mm)
Example
PIC16F15224
e
3
/SL
1950017
Rev. 30-009016B
12/10/2019
16-Lead VQFN (3x3x0.9 mm)
Example
PIC16
F15224
PIN 1
PIN 1
e
3
/RDB
950017
DS40002195A-page 389
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Rev. 30-009020A
09/21/2017
20-Lead PDIP (300 mil)
Example
PIC16F15244
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
e3
/P
1950017
YYWWNNN
Rev. 30-009020B
09/21/2017
20-Lead SSOP (5.30 mm)
Example
PIC16F15244
e
3
/SS
1950017
Rev. 30-009020C
09/21/2017
20-Lead SOIC (7.50 mm)
Example
PIC16F15244
/SO e
3
1950017
DS40002195A-page 390
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Rev. 30-009020E
12/10/2019
20-Lead VQFN (3x3x0.9 mm)
Example
PIC16
PIN 1
PIN 1
F15244
e
3
/MV
950017
34.1
Package Details
The following sections give the technical details of the packages.
DS40002195A-page 391
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2
DS40002195A-page 392
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
8
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
E1
D
3.90 BSC
4.90 BSC
Chamfer (Optional)
Foot Length
h
L
0.25
0.40
-
-
0.50
1.27
Footprint
L1
1.04 REF
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
0.25
0.51
15°
b
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2
DS40002195A-page 393
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev F
DS40002195A-page 394
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2
DS40002195A-page 395
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40002195A-page 396
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40002195A-page 397
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
NOTE 5
A
D
E
N
E
2
E2
2
E1
2X
0.10 C D
NOTE 1
2X N/2 TIPS
0.20 C
1
2
3
e
NX b
0.25
C A–B D
0.10 C
NOTE 5
B
TOP VIEW
C
A2
A
SEATING
PLANE
14X
0.10 C
SIDE VIEW
A1
h
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
DS40002195A-page 398
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
14
1.27 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
6.00 BSC
Molded Package Width
Overall Length
Chamfer (Optional)
Foot Length
E1
D
h
3.90 BSC
8.65 BSC
0.25
0.40
-
-
0.50
1.27
L
Footprint
L1
1.04 REF
Lead Angle
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0°
0.10
0.31
5°
-
-
-
-
-
-
-
8°
0.25
0.51
15°
15°
c
b
5°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
DS40002195A-page 399
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
1.27 BSC
5.40
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (X14)
E
C
X
0.60
1.55
Contact Pad Length (X14)
Y
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
DS40002195A-page 400
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
E
2
E1
2
E1
E
2X 7 TIPS
0.20 C B A
1
2
e
TOP VIEW
A
A
C
A2
A
SEATING
PLANE
A1
14X
14X b
0.10 C
0.10
C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2
DS40002195A-page 401
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(θ2)
R1
H
R2
c
L
θ1
(L1)
(θ3)
DETAIL B
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Terminals
Pitch
N
e
14
0.65 BSC
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
A
A1
A2
D
–
–
–
1.00
5.00
1.20
0.15
1.05
5.10
0.05
0.80
4.90
E
6.40 BSC
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
E1
b
c
4.30
0.19
0.09
0.45
4.40
–
–
0.60
4.50
0.30
0.20
0.75
L
L1
R1
R2
θ1
θ2
θ3
1.00 REF
0.09
0.09
0°
–
–
–
–
–
–
–
8°
–
Mold Draft Angle
Mold Draft Angle
12° REF
12° REF
–
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2
DS40002195A-page 402
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
C
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (Xnn)
E
C
X
0.65 BSC
5.90
0.45
1.45
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2087 Rev D
DS40002195A-page 403
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
16-Lead Very Thin Plastic Quad Flat, No Lead Package (RDB) - 3x3x0.9 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Package ZPX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
16X
0.08 C
0.10 C
D
A
B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(A3)
0.10
C A B
A
D2
SEATING
PLANE
C
SIDE VIEW
0.10
C A B
E2
2
1
e
2
K
L
N
16X b
NOTE 1
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21379 Rev A Sheet 1 of 2
DS40002195A-page 404
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
16-Lead Very Thin Plastic Quad Flat, No Lead Package (RDB) - 3x3x0.9 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Package ZPX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
16
0.50 BSC
0.85
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
0.90
0.05
0.035
0.21 REF
3.00 BSC
1.70
3.00 BSC
1.70
0.25
0.40
–
1.60
1.80
1.60
0.20
0.35
0.20
1.80
0.30
0.45
–
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21379 Rev A Sheet 2 of 2
DS40002195A-page 405
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
16-Lead Very Thin Plastic Quad Flat, No Lead Package (RDB) - 3x3x0.9 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Package ZPX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
16
ØV
1
G2
2
C2
EV
Y2
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.50 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
1.80
1.80
3.00
3.00
Contact Pad Spacing
Contact Pad Width (X16)
Contact Pad Length (X16)
Contact Pad to Center Pad (X16)
Contact Pad to Contact Pad (X12)
Thermal Via Diameter
0.30
0.80
0.20
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23379 Rev A
DS40002195A-page 406
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
E1
NOTE 1
1
2
3
D
E
A2
A
L
c
A1
b1
eB
e
b
Units
INCHES
NOM
20
Dimension Limits
MIN
MAX
Number of Pins
Pitch
N
e
.100 BSC
–
Top to Seating Plane
A
–
.210
.195
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.980
.115
.008
.045
.014
–
.130
–
.310
.250
1.030
.130
.010
.060
.018
–
.325
.280
1.060
.150
.015
.070
.022
.430
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing §
eB
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-019B
DS40002195A-page 407
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40002195A-page 408
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40002195A-page 409
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40002195A-page 410
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
c
A2
A
φ
A1
L1
L
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
20
0.65 BSC
Overall Height
Molded Package Thickness
Standoff
A
–
–
1.75
–
2.00
1.85
–
A2
A1
E
1.65
0.05
7.40
5.00
6.90
0.55
Overall Width
Molded Package Width
Overall Length
Foot Length
7.80
5.30
7.20
0.75
1.25 REF
–
8.20
5.60
7.50
0.95
E1
D
L
Footprint
L1
c
Lead Thickness
Foot Angle
0.09
0°
0.25
8°
φ
4°
Lead Width
b
0.22
–
0.38
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-072B
DS40002195A-page 411
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.65
0.45
SILK SCREEN
c
Y1
G
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Width (X20)
E
C
X1
0.65 BSC
7.20
0.45
1.75
Contact Pad Length (X20)
Distance Between Pads
Y1
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2072B
DS40002195A-page 412
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
16X
0.08 C
0.10 C
D
A
B
NOTE 1
N
1
2
E
(DATUM B)
(DATUM A)
2X
0.10 C
2X
A1
TOP VIEW
0.10 C
(A3)
0.10
C A B
A
D2
SEATING
PLANE
C
SIDE VIEW
0.10
C A B
E2
2
(CH)
1
NOTE 1
K
N
L
20X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-21380 Rev A Sheet 1 of 2
DS40002195A-page 413
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Length
Exposed Pad Length
Overall Width
Exposed Pad Width
Terminal Width
Terminal Length
N
e
20
0.40 BSC
0.85
A
A1
A3
D
D2
E
E2
b
L
0.80
0.00
0.90
0.05
0.035
0.203 REF
3.00 BSC
1.70
3.00 BSC
1.70
1.60
1.80
1.60
0.15
0.35
0.20
1.80
0.25
0.45
-
0.20
0.40
-
Terminal-to-Exposed-Pad
Pin 1 Index Chamfer
K
CH
0.35 REF
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21380 Rev A Sheet 2 of 2
DS40002195A-page 414
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Packaging Information
20-Lead Very Thin Plastic Quad Flat, No Lead Package (REB) - 3x3 mm Body [VQFN]
With 1.7 mm Exposed Pad; Atmel Legacy Global Package Code ZCL
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
ØV
G2
C2 Y2 EV
G1
Y1
X1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.40 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
1.80
1.80
3.00
3.00
Contact Pad Spacing
Contact Pad Width (X20)
Contact Pad Length (X20)
Contact Pad to Center Pad (X20)
Contact Pad to Contact Pad (X16)
Thermal Via Diameter
0.20
0.80
0.20
0.20
0.30
1.00
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-23380 Rev A
DS40002195A-page 415
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
APPENDIX A: Revision History
35.
APPENDIX A: Revision History
Doc Rev.
Date
Comments
A
04/2020
Initial document release.
DS40002195A-page 416
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
The Microchip Website
Microchip provides online support via our website at http://www.microchip.com/. This website is used to make files
and information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
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To register, go to http://www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
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Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: http://www.microchip.com/support
DS40002195A-page 417
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
PART NO.
Device
–X
/XX
[X]
Tape Temperature Package
and Reel Range
Device:
Device A, Device B, etc
Tape and Reel Option:
Temperature Range:
Package:(2)
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Extended)
= UQFN
I
E
JQ
P
= PDIP
ST
SL
SN
RF
= TSSOP
= SOIC-14
= SOIC-8
= UDFN
Pattern:
QTP, SQTPSM (Serial Quick Turn Programming capability), Code or Special
Requirements (blank otherwise)
•
•
Device A - I/P Industrial temperature, PDIP package
Device B - E/SS Extended temperature, SSOP package
PIS_NOTES
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these
methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for your
convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with
DS40002195A-page 418
Preliminary Datasheet
© 2020 Microchip Technology Inc.
PIC16F15213/14/23/24/43/44
your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER
EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox,
KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST,
MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer,
QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control,
HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus,
ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider,
Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP,
INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad
I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2020, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-5935-4
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit http://www.microchip.com/quality.
DS40002195A-page 419
Preliminary Datasheet
© 2020 Microchip Technology Inc.
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