PIC16F15354T-I/MVQTP

PIC16(L)F15354/55

Full-Featured 28-Pin Microcontrollers

Description

PIC16(L)F15354/55 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,

combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.

The devices feature multiple PWMs, multiple communication, temperature sensor, and memory features like Memory

Access Partition (MAP) to support customers in data protection and bootloader applications, and Device Information

Area (DIA) which stores factory calibration values to help improve temperature sensor accuracy.

Core Features

Power-Saving Functionality

• C Compiler Optimized RISC Architecture

• Operating Speed:

• DOZE mode: Ability to Run the CPU Core Slower

than the System Clock

- DC – 32 MHz clock input

- 125 ns minimum instruction cycle

• IDLE mode: Ability to halt CPU Core while Internal

Peripherals Continue Operating

•

Interrupt Capability

• SLEEP mode: Lowest Power Consumption

• Peripheral Module Disable (PMD):

- Ability to disable hardware module to

minimize active power consumption of

unused peripherals

• 16-Level Deep Hardware Stack

• Timers:

- 8-bit Timer2 with Hardware Limit Timer (HLT)

- 16-bit Timer0/1

• Low-Current Power-on Reset (POR)

• Configurable Power-up Timer (PWRTE)

• Brown-out Reset (BOR)

• Low-Power BOR (LPBOR) Option

• Windowed Watchdog Timer (WWDT):

- Variable prescaler selection

- Variable window size selection

- All sources configurable in hardware or

software

eXtreme Low-Power (XLP) Features

• Sleep mode: 50 nA @ 1.8V, typical

• Watchdog Timer: 500 nA @ 1.8V, typical

• Secondary Oscillator: 500 nA @ 32 kHz

• Operating Current:

- 8 A @ 32 kHz, 1.8V, typical

- 32 A/MHz @ 1.8V, typical

• Programmable Code Protection

Digital Peripherals

Memory

• Four Configurable Logic Cells (CLC):

- Integrated combinational and sequential logic

• Complementary Waveform Generator (CWG):

- Rising and falling edge dead-band control

- Full-bridge, half-bridge, 1-channel drive

- Multiple signal sources

• Up to 14 KB Flash Program Memory

• Up to 1024 Bytes Data SRAM

• Direct, Indirect and Relative Addressing modes

• Memory Access Partition (MAP):

- Write protect

• Two Capture/Compare/PWM (CCP) module:

- 16-bit resolution for Capture/Compare modes

- 10-bit resolution for PWM mode

- Customizable Partition

• Device Information Area (DIA)

• Device Configuration Information (DCI)

• High-Endurance Flash (HEF)

- Last 128 words of Program Flash Memory

• Four 10-Bit PWMs

• Numerically Controlled Oscillator (NCO):

- Generates true linear frequency control and

increased frequency resolution

Operating Characteristics

- Input Clock: 0 Hz < F_NCO< 32 MHz

• Operating Voltage Range:

- 1.8V to 3.6V (PIC16LF15354/55)

- 2.3V to 5.5V (PIC16F15354/55)

• Temperature Range:

- Resolution: F_NCO/2²⁰

• Two EUSART, RS-232, RS-485, LIN compatible

• Two SPI

• Two I²C, SMBus, PMBus™ compatible

- Industrial: -40°C to 85°C

- Extended: -40°C to 125°C

 2016-2018 Microchip Technology Inc.

DS40001853C-page 1

PIC16(L)F15354/55

Digital Peripherals (Cont.)

Flexible Oscillator Structure

• I/O Pins:

- Individually programmable pull-ups

- Slew rate control

• High-Precision Internal Oscillator:

- Software selectable frequency range up to 32

MHz, ±1% typical

- Interrupt-on-change with edge-select

- Input level selection control (ST or TTL)

- Digital open-drain enable

• x2/x4 PLL with Internal and External Sources

• Low-Power Internal 32 kHz Oscillator

(LFINTOSC)

• Peripheral Pin Select (PPS):

- Enables pin mapping of digital I/O

• External 32 kHz Crystal Oscillator (SOSC)

• External Oscillator Block with:

- Three crystal/resonator modes up to 20 MHz

- Three external clock modes up to 32 MHz

• Fail-Safe Clock Monitor:

Analog Peripherals

• Analog-to-Digital Converter (ADC):

- 10-bit with up to 43 external channels

- Operates in Sleep

- Allows for safe shutdown if primary clock

stops

• Oscillator Start-up Timer (OST):

- Ensures stability of crystal oscillator

resources

• Two Comparators:

- FVR, DAC and external input pin available on

inverting and noninverting input

- Software selectable hysteresis

- Outputs available internally to other modules,

or externally through PPS

• 5-Bit Digital-to-Analog Converter (DAC):

- 5-bit resolution, rail-to-rail

- Positive Reference Selection

- Unbuffered I/O pin output

- Internal connections to ADCs and

comparators

• Voltage Reference:

- Fixed Voltage Reference with 1.024V, 2.048V

and 4.096V output levels

• Zero-Cross Detect module:

- AC high voltage zero-crossing detection for

simplifying TRIAC control

- Synchronized switching control and timing

 2016-2018 Microchip Technology Inc.

DS40001853C-page 2

PIC16(L)F15354/55

TABLE 1:

PIC16(L)F153XX FAMILY TYPES

Device

PIC16(L)F15313 (C)

2

3.5 224 256

3.5 224 256 12 11

224 512 12 11

14 224 1024 12 11

224 512 18 17

14 224 1024 18 17

224 512 25 24

14 224 1024 25 24

6

5

1

2

Y

2/4

1

4

Y

1/1

Y

I

PIC16(L)F15323 (C)

PIC16(L)F15324 (D)

PIC16(L)F15325 (B)

PIC16(L)F15344 (D)

PIC16(L)F15345 (B)

PIC16(L)F15354 (A)

PIC16(L)F15355 (A)

2

4

8

4

8

4

8

1

2

1

2

Y

2/4

1

4

Y

1/1

2/1

2/2

Y

I

7

PIC16(L)F15356 (E) 16 28 224 2048 25 24

PIC16(L)F15375 (E) 14 224 1024 36 35

PIC16(L)F15376 (E) 16 28 224 2048 36 35

PIC16(L)F15385 (E) 14 224 1024 44 43

8

PIC16(L)F15386 (E) 16 28 224 2048 44 43

Note 1: I - Debugging integrated on chip.

Data Sheet Index:

A: DS40001853

B: DS40001865

C: DS40001897

D: DS40001889

E: DS40001866

PIC16(L)F15354/5 Data Sheet, 28-Pin

PIC16(L)F15325/45 Data Sheet, 14/20-Pin

PIC16(L)F15313/23 Data Sheet, 8/14-Pin

PIC16(L)F15324/44 Data Sheet, 14/20-Pin

PIC16(L)F15356/75/76/85/86 Data Sheet, 28/40/48-Pin

Note:

For other small form-factor package availability and marking information, visit www.microchip.com/

packaging or contact your local sales office.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 3

PIC16(L)F15354/55

TABLE 2:

PACKAGES

Device

SPDIP

SOIC

SSOP

UQFN (4x4)

UQFN (6x6)

PIC16(L)F15354

PIC16(L)F15355



 2016-2018 Microchip Technology Inc.

DS40001853C-page 4

PIC16(L)F15354/55

PIN DIAGRAMS

28-PIN PDIP, SOIC, SSOP

RB7/ICSPDAT

RB6/ICSPCLK

RB5

28

27

26

25

1

2

3

4

5

6

VPP/MCLR/RE3

RA0

RA1

RA2

RA3

RA4

RB4

RB3

RB2

24

23

22

21

RB1

RB0

RA5

VSS

7

8

9

20 VDD

19 VSS

RA7

RA6

RC0

10

11

RC7

18

17 RC6

RC1 12

RC5

RC4

16

15

RC2

RC3

13

14

Note 1: See Table 3 for location of all peripheral functions.

2: All VDD and all VSS pins must be connected at the circuit board level.

28-PIN UQFN (4x4), UQFN (6x6)

RB3

RB2

RA2

RA3

RA4

RA5

VSS

1

2

3

4

5

6

7

21

20

19 RB1

PIC16(L)F15354

PIC16(L)F15355

18

17

16

15

RB0

VDD

VSS

RC7

RA7

RA6

Note 1: See Table 3 for location of all peripheral functions.

2: All VDD and all VSS pins must be connected at the circuit board level. Allowing one or more VSS or VDD pins to

float may result in degraded electrical performance or non-functionality.

3: The bottom pad of the QFN/UQFN package should be connected to VSS at the circuit board level.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 5

PIC16(L)F15354/55

Table of Contents

1.0 Device Overview ........................................................................................................................................................................... 10

2.0 Guidelines for Getting Started with PIC16(L)F15354/55 Microcontrollers .................................................................................... 19

3.0 Enhanced Mid-Range CPU........................................................................................................................................................... 22

4.0 Memory Organization .................................................................................................................................................................... 24

5.0 Device Configuration ..................................................................................................................................................................... 75

6.0 Device Information Area ............................................................................................................................................................... 86

7.0 Device Configuration Information .................................................................................................................................................. 88

8.0 Resets........................................................................................................................................................................................... 89

9.0 Oscillator Module (with Fail-Safe Clock Monitor) ........................................................................................................................ 100

10.0 Interrupts................................................................................................................................................................................... 117

11.0 Power-Saving Operation Modes ............................................................................................................................................... 139

12.0 Windowed Watchdog Timer (WWDT) ....................................................................................................................................... 146

13.0 Nonvolatile Memory (NVM) Control .......................................................................................................................................... 154

14.0 /O Ports..................................................................................................................................................................................... 172

15.0 Peripheral Pin Select (PPS) Module ......................................................................................................................................... 194

16.0 Peripheral Module Disable ........................................................................................................................................................ 203

17.0 Interrupt-On-Change ................................................................................................................................................................. 211

18.0 Fixed Voltage Reference (FVR) ................................................................................................................................................ 221

19.0 Temperature Indicator Module .................................................................................................................................................. 224

20.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 226

21.0 5-Bit Digital-to-Analog Converter (DAC1) Module ..................................................................................................................... 240

22.0 Numerically Controlled Oscillator (NCO) Module ...................................................................................................................... 245

23.0 Comparator Module .................................................................................................................................................................. 255

24.0 Zero-Cross Detection (ZCD) Module ........................................................................................................................................ 265

25.0 Timer0 Module .......................................................................................................................................................................... 271

26.0 Timer1 Module with Gate Control ............................................................................................................................................. 277

27.0 Timer2 Module With Hardware Limit Timer (HLT) .................................................................................................................... 291

28.0 Capture/Compare/PWM Modules ............................................................................................................................................. 312

29.0 Pulse-Width Modulation (PWM) ................................................................................................................................................ 323

30.0 Complementary Waveform Generator (CWG) Module ............................................................................................................. 330

31.0 Configurable Logic Cell (CLC) .................................................................................................................................................. 355

32.0 Master Synchronous Serial Port (MSSPx) Modules ................................................................................................................. 372

33.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ................................................................ 423

34.0 Reference Clock Output Module ............................................................................................................................................... 451

35.0 n-Circuit Serial Programming™ (ICSP™) ................................................................................................................................. 455

36.0 Instruction Set Summary........................................................................................................................................................... 457

37.0 Electrical Specifications ............................................................................................................................................................ 470

38.0 DC and AC Characteristics Graphs and Charts ........................................................................................................................ 499

39.0 Development Support ............................................................................................................................................................... 519

40.0 Packaging Information .............................................................................................................................................................. 523

 2016-2018 Microchip Technology Inc.

DS40001853C-page 8

PIC16(L)F15354/55

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and

enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at docerrors@microchip.com. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision

of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

•

Microchip’s Worldwide Website; http://www.microchip.com

Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

using.

Customer Notification System

Register on our website at www.microchip.com to receive the most current information on all of our products.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 9

PIC16(L)F15354/55

1.0

DEVICE OVERVIEW

TABLE 1-1:

DEVICE PERIPHERAL

SUMMARY

The PIC16(L)F15354/55 are described within this data

sheet. The PIC16(L)F15354/55 devices are available in

28-pin SPDIP, SSOP, SOIC, and UQFN packages.

Figure 1-1 shows the block diagram of the

PIC16(L)F15354/55 devices. Table 1-2 shows the

pinout descriptions.

Peripheral

Reference Table 1-1 for peripherals available per device.

Analog-to-Digital Converter

●

Digital-to-Analog Converter (DAC1)

Fixed Voltage Reference (FVR)

Numerically Controlled Oscillator (NCO1)

Temperature Indicator Module (TIM)

Zero-Cross Detect (ZCD1)

Capture/Compare/PWM Modules (CCP)

CCP1

CCP2

●

Comparator Module (Cx)

C1

C2

●

Configurable Logic Cell (CLC)

CLC1

CLC2

CLC3

CLC4

●

Complementary Waveform Generator (CWG)

CWG1

●

Enhanced Universal Synchronous/Asynchronous

Receiver/Transmitter (EUSART)

EUSART1

EUSART2

●

Master Synchronous Serial Ports (MSSP)

Pulse-Width Modulator (PWM)

MSSP1

MSSP2

●

PWM3

PWM4

PWM5

PWM6

●

Timers

Timer0

Timer1

Timer2

●

 2016-2017 Microchip Technology Inc.

DS40001853C-page 10

PIC16(L)F15354/55

1.1.2.3

Bit Fields

1.1

Register and Bit Naming

Conventions

Bit fields are two or more adjacent bits in the same

register. Bit fields adhere only to the short bit naming

convention. For example, the three Least Significant

bits of the COG1CON0 register contain the mode

control bits. The short name for this field is MD. There

is no long bit name variant. Bit field access is only

possible in C programs. The following example

demonstrates a C program instruction for setting the

COG1 to the Push-Pull mode:

1.1.1

REGISTER NAMES

When there are multiple instances of the same

peripheral in a device, the peripheral control registers

will be depicted as the concatenation of a peripheral

identifier, peripheral instance, and control identifier.

The control registers section will show just one

instance of all the register names with an ‘x’ in the place

of the peripheral instance number. This naming

convention may also be applied to peripherals when

there is only one instance of that peripheral in the

device to maintain compatibility with other devices in

the family that contain more than one.

COG1CON0bits.MD = 0x5;

Individual bits in a bit field can also be accessed with

long and short bit names. Each bit is the field name

appended with the number of the bit position within the

field. For example, the Most Significant mode bit has

the short bit name MD2 and the long bit name is

G1MD2. The following two examples demonstrate

assembly program sequences for setting the COG1 to

Push-Pull mode:

1.1.2

BIT NAMES

There are two variants for bit names:

• Short name: Bit function abbreviation

• Long name: Peripheral abbreviation + short name

Example 1:

MOVLW ~(1<<G1MD1)

ANDWF COG1CON0,F

1.1.2.1

Short Bit Names

MOVLW 1<<G1MD2 | 1<<G1MD0

IORWF COG1CON0,F

Short bit names are an abbreviation for the bit function.

For example, some peripherals are enabled with the

EN bit. The bit names shown in the registers are the

short name variant.

Example 2:

BSF

BCF

BSF

COG1CON0,G1MD2

COG1CON0,G1MD1

COG1CON0,G1MD0

Short bit names are useful when accessing bits in C

programs. The general format for accessing bits by the

short name is RegisterNamebits.ShortName. For

example, the enable bit, EN, in the COG1CON0 regis-

ter can be set in C programs with the instruction

COG1CON0bits.EN = 1.

1.1.3

REGISTER AND BIT NAMING

EXCEPTIONS

1.1.3.1

Status, Interrupt, and Mirror Bits

Short names are generally not useful in assembly

programs because the same name may be used by

different peripherals in different bit positions. When this

occurs, during the include file generation, all instances

of that short bit name are appended with an underscore

plus the name of the register in which the bit resides to

avoid naming contentions.

Status, interrupt enables, interrupt flags, and mirror bits

are contained in registers that span more than one

peripheral. In these cases, the bit name shown is

unique so there is no prefix or short name variant.

1.1.3.2

Legacy Peripherals

There are some peripherals that do not strictly adhere

to these naming conventions. Peripherals that have

existed for many years and are present in almost every

device are the exceptions. These exceptions were

necessary to limit the adverse impact of the new

conventions on legacy code. Peripherals that do

adhere to the new convention will include a table in the

registers section indicating the long name prefix for

each peripheral instance. Peripherals that fall into the

exception category will not have this table. These

peripherals include, but are not limited to, the following:

1.1.2.2

Long Bit Names

Long bit names are constructed by adding a peripheral

abbreviation prefix to the short name. The prefix is

unique to the peripheral thereby making every long bit

name unique. The long bit name for the COG1 enable

bit is the COG1 prefix, G1, appended with the enable

bit short name, EN, resulting in the unique bit name

G1EN.

Long bit names are useful in both C and assembly pro-

grams. For example, in C the COG1CON0 enable bit

can be set with the G1EN = 1instruction. In assembly,

this bit can be set with the BSF COG1CON0,G1EN

instruction.

• EUSART

• MSSP

 2016-2017 Microchip Technology Inc.

DS40001853C-page 11

PIC16(L)F15354/55

TABLE 1-2:

PIC16(L)F15354/55 PINOUT DESCRIPTION

Input

Name

Function

Output Type

Description

Type

TTL/ST

AN

RA0/ANA0/C1IN0-/C2IN0-/CLCIN0⁽¹⁾

IOCA0

/

RA0

ANA0

CMOS/OD

General purpose I/O.

—

ADC Channel A0 input.

C1IN0-

C2IN0-

CLCIN0⁽¹⁾

IOCA0

RA1

AN

—

Comparator 1 negative input.

Comparator 2 negative input.

Configurable Logic Cell source input.

Interrupt-on-change input.

General purpose I/O.

AN

—

TTL/ST

AN

—

RA1/ANA1/C1IN1-/C2IN1-/CLCIN1⁽¹⁾

IOCA1

/

CMOS/OD

ANA1

—

ADC Channel A1 input.

C1IN1-

C2IN1-

CLCIN1⁽¹⁾

IOCA1

RA2

AN

—

Comparator 1 negative input.

Comparator 2 negative input.

Configurable Logic Cell source input.

Interrupt-on-change input.

General purpose I/O.

AN

—

TTL/ST

AN

—

RA2/ANA2/C1IN0+/C2IN0+/

DAC1OUT1/IOCA2

CMOS/OD

ANA2

—

ADC Channel A2 input.

C1IN0+

C2IN0+

DAC1OUT1

IOCA2

RA3

AN

—

Comparator 2 positive input.

Digital-to-Analog Converter output.

Interrupt-on-change input.

General purpose I/O.

AN

—

AN

TTL/ST

AN

—

RA3/ANA3/C1IN1+/VREF+/IOCA3/

DAC1REF+

CMOS/OD

ANA3

—

ADC Channel A3 input.

C1IN1+

VREF+

IOCA3

DAC1REF+

RA4

AN

—

Comparator 1 positive input.

External ADC and/or DAC positive reference input.

Interrupt-on-change input.

DAC positive reference.

AN

—

TTL/ST

AN

—

AN

RA4/ANA4/T0CKI⁽¹⁾/IOCA4

CMOS/OD

General purpose I/O.

ANA4

—

ADC Channel A4 input.

T0CKI⁽¹⁾

IOCA4

RA5

TTL/ST

AN

—

Timer0 clock input.

—

Interrupt-on-change input.

General purpose I/O.

RA5/ANA5/SS1⁽¹⁾/IOCA5

CMOS/OD

ANA5

—

ADC Channel A5 input.

SS1⁽¹⁾

IOCA5

TTL/ST

MSSP1 SPI slave select input.

Interrupt-on-change input.

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

3:

4:

 2016-2017 Microchip Technology Inc.

DS40001853C-page 13

PIC16(L)F15354/55

TABLE 1-2:

PIC16(L)F15354/55 PINOUT DESCRIPTION (CONTINUED)

Input

Type

Name

Function

Output Type

Description

RA6/ANA6/OSC2/CLKOUT/IOCA6

RA6

TTL/ST

AN

CMOS/OD

—

General purpose I/O.

ANA6

ADC Channel A6 input.

External Crystal/Resonator (LP, XT, HS modes) driver

output.

OSC2

—

XTAL

CLKOUT

IOCA6

RA7

—

CMOS/OD

FOSC/4 digital output (in non-crystal/resonator modes).

Interrupt-on-change input.

TTL/ST

AN

—

RA7/ANA7/OSC1/CLKIN/IOCA7

CMOS/OD

General purpose I/O.

ANA7

OSC1

CLKIN

IOCA7

RB0

—

ADC Channel A7 input.

XTAL

TTL/ST

AN

—

External Crystal/Resonator (LP, XT, HS modes) driver input.

External digital clock input.

—

CMOS/OD

—

Interrupt-on-change input.

RB0/ANB0/C2IN1+/ZCD1/SS2⁽¹⁾

CWG1IN⁽¹⁾/INT⁽¹⁾/IOCB0

/

General purpose I/O.

ANB0

C2IN1+

ADC Channel B0 input.

AN

—

Comparator 2 positive input.

Zero-cross detect input pin (with constant current sink/

source).

ZCD1

AN

SS2⁽¹⁾

CWG1IN⁽¹⁾

INT⁽¹⁾

TTL/ST

AN

—

MSSP2 SPI slave select input.

Complementary Waveform Generator 1 input.

External interrupt request input.

Interrupt-on-change input.

—

IOCB0

RB1

—

RB1/ANB1/C1IN3-/C2IN3-/SCL2^(3,4)

/

CMOS/OD

General purpose I/O.

SCK2⁽¹⁾/IOCB1

ANB1

—

ADC Channel B1 input.

C1IN3-

C2IN3-

SCL2^(3,4)

AN

Comparator 1 negative input.

Comparator 2 negative input.

MSSP2 I²C clock input/output.

AN

—

I²C

OD

MSSP2 SPI serial clock (default input location, SCK2 is a

PPS remappable input and output).

SCK2⁽¹⁾

TTL/ST

CMOS/OD

IOCB1

RB2

TTL/ST

AN

—

Interrupt-on-change input.

General purpose I/O.

RB2/ANB2/SDA2^(3,4)/SDI2⁽¹⁾/IOCB2

CMOS/OD

ANB2

—

OD

—

ADC Channel B2 input.

SDA2^(3,4)

SDI2⁽¹⁾

IOCB2

I²C

MSSP2 I²C serial data input/output.

MSSP2 SPI serial data input.

Interrupt-on-change input.

TTL/ST

—

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

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DS40001853C-page 14

PIC16(L)F15354/55

TABLE 1-2:

PIC16(L)F15354/55 PINOUT DESCRIPTION (CONTINUED)

Input

Type

Name

Function

Output Type

Description

RB3/ANB3/C1IN2-/C2IN2-/IOCB3

RB3

ANB3

TTL/ST

AN

CMOS/OD

General purpose I/O.

—

ADC Channel B3 input.

C1IN2-

C2IN2-

IOCB3

RB4

AN

—

Comparator 1 negative input.

Comparator 2 negative input.

Interrupt-on-change input.

AN

—

TTL/ST

AN

—

RB4/ANB4/ADACT⁽¹⁾/IOCB4

CMOS/OD

General purpose I/O.

ANB4

—

ADC Channel B4 input.

ADACT⁽¹⁾

IOCB4

RB5

TTL/ST

AN

—

ADC Auto-Conversion Trigger input.

Interrupt-on-change input.

—

RB5/ANB5/T1G⁽¹⁾/IOCB5

CMOS/OD

General purpose I/O.

ANB5

—

ADC Channel B5 input.

T1G⁽¹⁾

IOCB5

RB6

ST

—

Timer1 Gate input.

TTL/ST

AN

—

Interrupt-on-change input.

RB6/ANB6/CLCIN2⁽¹⁾/IOCB6/TX2/

CK2⁽³⁾/ICSPCLK

CMOS/OD

General purpose I/O.

ANB6

—

ADC Channel B6 input.

CLCIN2⁽¹⁾

IOCB6

TX2

TTL/ST

—

Configurable Logic Cell source input.

Interrupt-on-change input.

—

CMOS

EUSART2 asynchronous.

CK2⁽³⁾

ICSPCLK

RB7

TTL/ST

ST

CMOS/OD

EUSART2 synchronous mode clock input/output.

In-Circuit Serial Programming™ and debugging clock input.

General purpose I/O.

—

RB7/ANB7/RX2/DT2/CLCIN3⁽¹⁾

IOCB7/DAC1OUT2/ICSPDAT

/

TTL/ST

AN

CMOS/OD

ANB7

—

ADC Channel B7 input.

CLCIN3⁽¹⁾

IOCB7

RX2⁽¹⁾

DT2⁽³⁾

DAC1OUT2

TTL/ST

—

Configurable Logic Cell source input.

Interrupt-on-change input.

—

EUSART2 Asynchronous mode receiver data input.

EUSART2 Synchronous mode data input/output.

Digital-to-Analog Converter output.

CMOS/OD

AN

In-Circuit Serial Programming™ and debugging data input/

output.

ICSPDAT

ST

CMOS

RC0/ANC0/T1CKI⁽¹⁾/IOCC0/SOSCO

RC0

TTL/ST

AN

CMOS/OD

General purpose I/O.

ANC0

—

ADC Channel C0 input.

T1CKI⁽¹⁾

IOCC0

SOSCO

TTL/ST

—

Timer1 external digital clock input.

Interrupt-on-change input.

—

AN

32.768 kHz secondary oscillator crystal driver output.

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

3:

4:

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PIC16(L)F15354/55

TABLE 1-2:

PIC16(L)F15354/55 PINOUT DESCRIPTION (CONTINUED)

Input

Type

Name

Function

Output Type

Description

RC1/ANC1/CCP2⁽¹⁾/IOCC1/SOSCI

RC1

ANC1

TTL/ST

AN

CMOS/OD

General purpose I/O.

ADC Channel C1 input.

CCP2 Capture Input.

—

CCP2⁽¹⁾

IOCC1

SOSCI

RC2

TTL/ST

AN

CMOS/OD

—

Interrupt-on-change input.

32.768 kHz secondary oscillator crystal driver input.

General purpose I/O.

—

CMOS/OD

—

RC2/ANC2/CCP1⁽¹⁾/IOCC2

TTL/ST

AN

ANC2

ADC Channel C2 input.

CCP1⁽¹⁾

IOCC2

RC3

TTL/ST

AN

CMOS/OD

—

CCP1 Capture Input.

Interrupt-on-change input.

General purpose I/O.

RC3/ANC3/SCL1^(3,4)/SCK1⁽¹⁾/T2IN⁽¹⁾

IOCC3

/

CMOS/OD

—

ANC3

ADC Channel C3 input.

SCL1^(3,4)

I²C

OD

MSSP1 I²C input/output.

MSSP1 SPI clock input/output (default input location, SCK1

is a PPS remappable input and output).

SCK1⁽¹⁾

TTL/ST

CMOS/OD

T2IN⁽¹⁾

IOCC3

RC4

TTL/ST

AN

—

Timer2 external input.

—

Interrupt-on-change input.

RC4/ANC4/SDA1^(3,4)/SDI1⁽¹⁾/IOCC4

CMOS/OD

General purpose I/O.

ANC4

SDA1^(3,4)

SDI1⁽¹⁾

IOCC4

RC5

—

ADC Channel C4 input.

I²C

OD

MSSP1 I²C serial data input/output.

MSSP1 SPI serial data input.

Interrupt-on-change input.

TTL/ST

AN

—

RC5/ANC5/IOCC5

CMOS/OD

General purpose I/O.

ANC5

IOCC5

RC6

—

ADC Channel C5 input.

TTL/ST

AN

—

CMOS/OD

—

Interrupt-on-change input.

RC6/ANC6/TX1/CK1⁽¹⁾/IOCC6

General purpose I/O.

ANC6

TX1

ADC Channel C6 input.

—

CMOS

CMOS/OD

—

EUSART1 asynchronous transmit.

EUSART 1 synchronous mode clock input/output.

Interrupt-on-change input.

CK1⁽¹⁾

IOCC6

RC7

TTL/ST

AN

RC7/ANC7/RX1/DT1⁽³⁾/IOCC7

CMOS/OD

—

General purpose I/O.

ANC7

RX1

ADC Channel C7 input.

TTL/ST

—

EUSART1 Asynchronous mode receiver data input.

EUSART1 Synchronous mode data input/output.

Interrupt-on-change input.

DT1⁽³⁾

IOCC7

CMOS/OD

—

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

3:

4:

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PIC16(L)F15354/55

TABLE 1-2:

Name

PIC16(L)F15354/55 PINOUT DESCRIPTION (CONTINUED)

Input

Type

Function

Output Type

Description

RE3/IOCE3/MCLR/VPP

General purpose input only (when MCLR is disabled by the

Configuration bit).

RE3

TTL/ST

—

IOCE3

MCLR

VPP

TTL/ST

ST

—

Interrupt-on-change input.

Master clear input with internal weak pull-up resistor.

ICSP™ High-Voltage Programming mode entry input.

Positive supply voltage input.

HV

VDD

VSS

VDD

Power

VSS

Ground reference.

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

3:

4:

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PIC16(L)F15354/55

TABLE 1-2:

PIC16(L)F15354/55 PINOUT DESCRIPTION (CONTINUED)

Input

Type

Name

Function

Output Type

Description

OUT⁽²⁾

C1OUT

C2OUT

SDO1

—

CMOS/OD

Comparator 1 output.

Comparator 2 output.

MSSP1 SPI serial data output.

SCK1

MSSP1 SPI serial clock output.

SDO2

MSSP2 SPI serial data output.

SCK2

MSSP2 SPI serial clock output.

TX1

EUSART1 Asynchronous mode transmitter data output.

EUSART1 Synchronous mode clock output.

EUSART2 Asynchronous mode transmitter data output.

EUSART2 Synchronous mode clock output.

EUSART Synchronous mode data output.

Timer0 output.

CK1⁽³⁾

TX2

CK2⁽³⁾

DT⁽³⁾

TMR0

CCP1

CCP2 output (compare/PWM functions).

PWM3 output.

CCP2

PWM3OUT

PWM4OUT

PWM5OUT

PWM6OUT

CWG1A

CWG1B

CWG1C

CWG1D

CLC1OUT

CLC2OUT

CLC3OUT

CLC4OUT

NCO1OUT

CLKR

PWM4 output.

PWM5 output.

PWM6 output.

Complementary Waveform Generator 1 output A.

Complementary Waveform Generator 1 output B.

Complementary Waveform Generator 1 output C.

Complementary Waveform Generator 1 output D.

Configurable Logic Cell 1 output.

Configurable Logic Cell 2 output.

Configurable Logic Cell 3 output.

Configurable Logic Cell 4 output.

Numerically Controller Oscillator output.

Clock Reference module output.

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS

ST

XTAL

=

CMOS compatible input or output

Schmitt Trigger input with CMOS levels

Crystal levels

OD

I²C

= Open-Drain

= Schmitt Trigger input with I²C

Note 1:

This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx

pins. Refer to Table 15-1 for details on which PORT pins may be used for this signal.

All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin

options as described in Table 15-3.

This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and

PPS output registers.

These pins are configured for I²C logic levels. The SCLx/SDAx signals may be assigned to any of the RB1/RB2/RC3/RC4 pins. PPS

assignments to the other pins (e.g., RA5) will operate, but input logic levels will be standard TTL/ST, as selected by the INLVL register,

instead of the I²C specific or SMBus input buffer thresholds.

2:

3:

4:

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PIC16(L)F15354/55

2.2

Power Supply Pins

2.0

2.1

GUIDELINES FOR GETTING

STARTED WITH

PIC16(L)F15354/55

2.2.1

DECOUPLING CAPACITORS

The use of decoupling capacitors on every pair of

power supply pins (VDD and VSS) is required.

MICROCONTROLLERS

Consider the following criteria when using decoupling

capacitors:

Basic Connection Requirements

Getting started with the PIC16(L)F15354/55 family of 8-

bit microcontrollers requires attention to a minimal set

of device pin connections before proceeding with

development.

• Value and type of capacitor: A 0.1 F (100 nF),

10-25V capacitor is recommended. The capacitor

should be a low-ESR device, with a resonance

frequency in the range of 200 MHz and higher.

Ceramic capacitors are recommended.

The following pins must always be connected:

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is no greater

than 0.25 inch (6 mm).

• All VDD and VSS pins

(see Section 2.2 “Power Supply Pins”)

• MCLR pin

(see Section 2.3 “Master Clear (MCLR) Pin”)

These pins must also be connected if they are being

used in the end application:

• ICSPCLK/ICSPDAT pins used for In-Circuit Serial

Programming™ (ICSP™) and debugging purposes

(see Section 2.4 “ICSP™ Pins”)

• Handling high-frequency noise: If the board is

experiencing high-frequency noise (upward of

tens of MHz), add a second ceramic type capaci-

tor in parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 F to 0.001 F. Place this

second capacitor next to each primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible

(e.g., 0.1 F in parallel with 0.001 F).

• OSCI and OSCO pins when an external oscillator

source is used

(see Section 2.5 “External Oscillator Pins”)

Additionally, the following pins may be required:

• VREF+/VREF- pins are used when external voltage

reference for analog modules is implemented

The minimum mandatory connections are shown in

Figure 2-1.

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB trace

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTIONS

C2

VDD

R1

R2

inductance.

MCLR

2.2.2

TANK CAPACITORS

C1

PIC16(L)F153xx

On boards with power traces running longer than

six inches in length, it is suggested to use a tank capac-

itor for integrated circuits, including microcontrollers, to

supply a local power source. The value of the tank

capacitor should be determined based on the trace

resistance that connects the power supply source to

the device, and the maximum current drawn by the

device in the application. In other words, select the tank

capacitor so that it meets the acceptable voltage sag at

the device. Typical values range from 4.7 F to 47 F.

VSS

Key (all values are recommendations):

C1: 10nF, 16V ceramic

C2: 0.1uF, 16V ceramic

R1: 10 kΩ

R2: 100Ω to 470Ω

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DS40001853C-page 19

PIC16(L)F15354/55

2.3

Master Clear (MCLR) Pin

2.4

ICSP™ Pins

The MCLR pin provides two specific device

functions: Device Reset, and Device Programming

and Debugging. If programming and debugging are

The ICSPCLK and ICSPDAT pins are used for In-Cir-

cuit Serial Programming™ (ICSP™) and debugging

purposes. It is recommended to keep the trace length

between the ICSP connector and the ICSP pins on the

device as short as possible. If the ICSP connector is

expected to experience an ESD event, a series resistor

is recommended, with the value in the range of a few

tens of ohms, not to exceed 100Ω.

not required in the end application,

a

direct

connection to VDD may be all that is required. The

addition of other components, to help increase the

application’s resistance to spurious Resets from

voltage sags, may be beneficial.

A

typical

configuration is shown in Figure 2-1. Other circuit

designs may be implemented, depending on the

application’s requirements.

Pull-up resistors, series diodes and capacitors on the

ICSPCLK and ICSPDAT pins are not recommended as

they will interfere with the programmer/debugger com-

munications to the device. If such discrete components

are an application requirement, they should be

removed from the circuit during programming and

debugging. Alternatively, refer to the AC/DC character-

istics and timing requirements information in the

respective device Flash programming specification for

information on capacitive loading limits, and pin input

voltage high (VIH) and input low (VIL) requirements.

During programming and debugging, the resistance

and capacitance that can be added to the pin must

be considered. Device programmers and debuggers

drive the MCLR pin. Consequently, specific voltage

levels (VIH and VIL) and fast signal transitions must

not be adversely affected. Therefore, specific values

of R1 and C1 will need to be adjusted based on the

application and PCB requirements. For example, it is

recommended that the capacitor, C1, be isolated

from the MCLR pin during programming and

debugging operations by using a jumper (Figure 2-2).

The jumper is replaced for normal run-time

operations.

For device emulation, ensure that the “Communication

Channel Select” (i.e., ICSPCLK/ICSPDAT pins),

programmed into the device, matches the physical

connections for the ICSP to the Microchip debugger/

emulator tool.

Any components associated with the MCLR pin

should be placed within 0.25 inch (6 mm) of the pin.

For more information on available Microchip

development tools connection requirements, refer to

Section 39.0 “Development Support”.

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

VDD

R1

R2

MCLR

PIC16(L)F153xx

JP

C1

Note 1: R1  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R2  470 will limit any current flowing into

MCLR from the external capacitor, C1, in the

event of MCLR pin breakdown, due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

VIH and VIL specifications are met.

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DS40001853C-page 20

PIC16(L)F15354/55

2.5

External Oscillator Pins

2.6

Unused I/Os

Many microcontrollers have options for at least two

oscillators: a high-frequency primary oscillator and a

Unused I/O pins should be configured as outputs and

driven to a logic low state. Alternatively, connect a 1 kΩ

to 10 kΩ resistor to VSS on unused pins and drive the

output to logic low.

low-frequency

secondary

oscillator

(refer to

Section 9.0 “Oscillator Module (with Fail-Safe

Clock Monitor)” for details).

FIGURE 2-3:

SUGGESTED

PLACEMENT OF THE

OSCILLATOR CIRCUIT

The oscillator circuit should be placed on the same

side of the board as the device. Place the oscillator

circuit close to the respective oscillator pins with no

more than 0.5 inch (12 mm) between the circuit

components and the pins. The load capacitors should

be placed next to the oscillator itself, on the same side

of the board.

Single-Sided and In-Line Layouts:

Copper Pour

(tied to ground)

Primary Oscillator

Crystal

Use a grounded copper pour around the oscillator cir-

cuit to isolate it from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a two-sided

board, avoid any traces on the other side of the board

where the crystal is placed.

DEVICE PINS

Primary

OSC1

OSC2

GND

Oscillator

C1

C2

`

Layout suggestions are shown in Figure 2-3. In-line

packages may be handled with a single-sided layout

that completely encompasses the oscillator pins. With

fine-pitch packages, it is not always possible to com-

pletely surround the pins and components. A suitable

solution is to tie the broken guard sections to a mirrored

ground layer. In all cases, the guard trace(s) must be

returned to ground.

SOSCO

SOSCI

Secondary Oscillator

(SOSC)

`

Crystal

SOSC: C2

SOSC: C1

In planning the application’s routing and I/O assign-

ments, ensure that adjacent port pins, and other

signals in close proximity to the oscillator, are benign

(i.e., free of high frequencies, short rise and fall times,

and other similar noise).

Fine-Pitch (Dual-Sided) Layouts:

Top Layer Copper Pour

(tied to ground)

For additional information and design guidance on

oscillator circuits, refer to these Microchip Application

Notes, available at the corporate website

(www.microchip.com):

Bottom Layer

Copper Pour

(tied to ground)

• AN826, “Crystal Oscillator Basics and Crystal

Selection for rfPIC™ and PICmicro^®Devices”

OSCO

• AN849, “Basic PICmicro^®Oscillator Design”

C2

• AN943, “Practical PICmicro^®Oscillator Analysis

and Design”

Oscillator

Crystal

GND

• AN949, “Making Your Oscillator Work”

C1

OSCI

DEVICE PINS

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DS40001853C-page 21

PIC16(L)F15354/55

3.0

ENHANCED MID-RANGE CPU

This family of devices contains an enhanced mid-range

8-bit CPU core. The CPU has 48 instructions. Interrupt

capability includes automatic context saving.

The hardware stack is 16-levels deep and has

Overflow and Underflow Reset capability. Direct,

Indirect, and Relative Addressing modes are available.

Two File Select Registers (FSRs) provide the ability to

read program and data memory.

FIGURE 3-1:

CORE DATA PATH DIAGRAM

Rev. 10-000055C

11/30/2016

15

Configuration

15

Data Bus

8

Program Counter

Flash

Program

Memory

16-Level Stack

(15-bit)

RAM

14

Program

Bus

12

Program Memory

Read (PMR)

RAM Addr

Addr MUX

Indirect

Instruction Reg

Direct Addr

Addr

7

12

5

12

BSR Reg

15

FSR0 Reg

STATUS Reg

MUX

15

FSR1 Reg

8

3

Power-up

Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode and

Control

ALU

8

CLKIN

CLKOUT

SOSCI

Brown-out

Reset

Timing

Generation

W Reg

SOSCO

VDD

VSS

Internal

Oscillator

Block

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DS40001853C-page 22

PIC16(L)F15354/55

3.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 10.5 “Automatic Context Saving”

for more information.

3.2

16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or

Underflow will set the appropriate bit (STKOVF or

STKUNF) in the PCON0 register, and if enabled, will

cause a software Reset. See Section 4.5 “Stack” for

more details.

3.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can also

be addressed linearly, providing the ability to access

contiguous data larger than 80 bytes. See Section 4.6

“Indirect Addressing” for more details.

3.4

Instruction Set

There are 48 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 36.0 “Instruction Set Summary” for more

details.

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DS40001853C-page 23

PIC16(L)F15354/55

4.1

Program Memory Organization

4.0

MEMORY ORGANIZATION

The enhanced mid-range core has a 15-bit program

counter capable of addressing 32K x 14 program

memory space. Table 4-1 shows the memory sizes

implemented. The Reset vector is at 0000h and the

interrupt vector is at 0004h (see Figure 4-1).

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

- User ID

- Program Flash Memory

- Device Information Area (DIA)

- Device Configuration Information (DCI)

- Revision ID

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

• Stack

• Indirect Addressing

• NVMREG access

TABLE 4-1:

DEVICE SIZES AND ADDRESSES

Device Program Memory Size (Words)

4096

8192

Last Program Memory Address

PIC16(L)F15354

PIC16(L)F15355

0FFFh

1FFFh

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PIC16(L)F15354/55

FIGURE 4-1:

PROGRAM MEMORY MAP

AND STACK FOR

FIGURE 4-2:

PROGRAM MEMORY MAP

AND STACK FOR

PIC16(L)F15354

PIC16(L)F15355

Rev. 10-000040H

8/23/2016

Rev. 10-000040G

1/12/2017

PC<14:0>

15

CALL, CALLW

15

RETURN, RETLW

Interrupt, RETFIE

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

Stack Level 15

0000h

Reset Vector

Interrupt Vector

0004h

0005h

On-chip

Program

Memory

On-chip

Program

Memory

07FFh

0800h

0FFFh

1000h

0FFFh

1000h

17FFh

1800h

1FFFh

2000h

1FFFh

2000h

Unimplemented

3FFFh

4000h

Unimplemented

7FFFh

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PIC16(L)F15354/55

4.1.1

READING PROGRAM MEMORY AS

DATA

There are three methods of accessing constants in

program memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory. The third method

is to use the NVMREG interface to access the program

memory. For an example of NVMREG interface use,

reference Section 13.3, NVMREG Access.

4.1.1.1

RETLWInstruction

The RETLWinstruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 4-1.

EXAMPLE 4-1:

RETLWINSTRUCTION

constants

BRW

;Add Index in W to

;program counter to

;select data

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Index0 data

;Index1 data

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

The BRW instruction makes this type of table very

simple to implement.

4.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by

setting bit 7 of an FSRxH register and reading the

matching INDFx register. The MOVIW instruction will

place the lower eight bits of the addressed word in the

W register. Writes to the program memory cannot be

performed via the INDF registers. Instructions that read

the program memory via the FSR require one extra

instruction

cycle

to

complete.

Example 4-2

demonstrates reading the program memory via an

FSR.

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The HIGH directive will set bit 7 if a label points to a

location in the program memory. This applies to the

assembly code Example 4-2 shown below.

4.2

Memory Access Partition (MAP)

User Flash is partitioned into:

• Application Block

• Boot Block, and

• Storage Area Flash (SAF) Block

EXAMPLE 4-2:

ACCESSING PROGRAM

MEMORY VIA FSR

The user can allocate the memory usage by setting

the BBEN bit, selecting the size of the partition defined

by BBSIZE[2:0] bits and enabling the Storage Area

Flash by the SAFEN bit of the Configuration Word (see

Register 5-4). Refer to Table 4-2 for the different user

Flash memory partitions.

constants

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

my_function

;Index0 data

;Index1 data

;… LOTS OF CODE…

MOVLW

MOVWF

MOVLW

MOVWF

MOVIW

LOW constants

FSR1L

HIGH constants

FSR1H

0[FSR1]

4.2.1

APPLICATION BLOCK

Default settings of the Configuration bits (BBEN = 1

and SAFEN = 1) assign all memory in the user Flash

area to the Application Block.

;THE PROGRAM MEMORY IS IN W

4.2.2

BOOT BLOCK

If BBEN = 1, the Boot Block is enabled and a specific

address range is alloted as the Boot Block based on

the value of the BBSIZE bits of Configuration Word

(Register 5-4) and the sizes provided in Table 5-1.

4.2.3

STORAGE AREA FLASH

Storage Area Flash (SAF) is enabled by clearing the

SAFEN bit of the Configuration Word in Register 5-4. If

enabled, the SAF block is placed at the end of memory

and spans 128 words. If the Storage Area Flash (SAF)

is enabled, the SAF area is not available for program

execution. The 128 words of the SAF quality as High

Endurance Flash (HEF) memory.

4.2.4

MEMORY WRITE PROTECTION

All the memory blocks have corresponding write

protection fuses WRTAPP, WRTB and WRTC bits in

the Configuration Word 4 (Register 5-4). If write-

protected locations are written from NVMCON

registers, memory is not changed and the WRERR bit

defined in Register 12-5 is set as explained in

Section 13.3.8 “WRERR Bit”.

4.2.5

MEMORY VIOLATION

A Memory Execution Violation Reset occurs while

executing an instruction that has been fetched from

outside a valid execution area, clearing the MEMV bit.

Refer to Section 8.12 “Memory Execution Violation”

for the available valid program execution areas and the

PCON1 register definition (Register 8-3) for MEMV bit

conditions.

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TABLE 4-2:

REG

MEMORY ACCESS PARTITION

Address

Partition

BBEN = 1

BBEN = 0

SAFEN = 1

SAFEN = 0

SAFEN = 1

SAFEN = 0

00 0000h

• • •

BOOT BLOCK⁽⁴⁾BOOT BLOCK⁽⁴⁾

Last Boot Block Memory

Address

APPLICATION

BLOCK⁽⁴⁾

Last Boot Block Memory

Address + 1⁽¹⁾

• • •

Last Program Memory

Address - 80h

APPLICATION

BLOCK⁽⁴⁾

APPLICATION

BLOCK⁽⁴⁾

PFM

APPLICATION

BLOCK⁽⁴⁾

Last Program Memory

Address - 7Fh⁽²⁾

• • •

SAF⁽⁴⁾

Last Program Memory

Address

CONFIG Config Memory Address⁽³⁾

CONFIG

Note 1: Last Boot Block Memory Address is based on BBSIZE<2:0> given in Table 5-1.

2: Last Program Memory Address is the Flash size given in Table 4-1.

3: Config Memory Address are the address locations of the Configuration Words given in Table 13-2.

4: Each memory block has a corresponding write protection fuse defined by the WRTAPP, WRTB and WRTC

bits in the Configuration Word (Register 5-4).

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4.3.1

BANK SELECTION

4.3

Data Memory Organization

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). All data memory

can be accessed either directly (via instructions that

use the file registers) or indirectly via the two File Select

Registers (FSR). See Section 4.6 “Indirect

Addressing” for more information.

The data memory is partitioned into 64 memory banks

with 128 bytes in each bank. Each bank consists of:

• 12 core registers

• Up to 100 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

Data memory uses a 13-bit address. The upper six bits

of the address define the Bank address and the lower

seven bits select the registers/RAM in that bank.

FIGURE 4-3:

BANKED MEMORY

PARTITIONING

4.3.2

CORE REGISTERS

Rev. 10-000041B

9/21/2016

The core registers contain the registers that directly

affect the basic operation. The core registers occupy

the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in Table 4-3.

7-bit Bank Offset

00h

Memory Region

Core Registers

(12 bytes)

TABLE 4-3:

CORE REGISTERS

0Bh

0Ch

Special Function Registers(1)

(up to 100 bytes maximum)

Addresses

x00h or x80h

BANKx

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

1Fh

20h

x01h or x81h

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

x0Ah or x8Ah

x0Bh or x8Bh

General Purpose RAM

(80 bytes maximum)

WREG

PCLATH

INTCON

6Fh

70h

Common RAM

(16 bytes)

7Fh

Note 1: This table shows the address for an example

bank with 20 Bytes of SFRs only.

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For example, CLRF STATUSwill clear bits <4:3> and

<1:0>, and set the Z bit. This leaves the STATUS

register as ‘000u u1uu’ (where u= unchanged).

4.3.2.1

STATUS Register

The STATUS register, shown in Register 4-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits, refer to Section 36.0

“Instruction Set Summary”.

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

REGISTER 4-1:

STATUS: STATUS REGISTER

U-0

—

U-0

—

U-0

—

R-1/q

TO

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC⁽¹⁾

R/W-0/u

C⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

TO: Time-Out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

bit 3

bit 2

bit 1

bit 0

PD: Power-Down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit⁽¹⁾(ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

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4.3.3

SPECIAL FUNCTION REGISTER

The Special Function Registers are registers used by

the application to control the desired operation of

peripheral functions in the device. The Special Function

Registers occupy the 20 bytes of the data banks 0-59

and 100 bytes of the data banks 60-63, after the core

registers.

The SFRs associated with the operation of the

peripherals are described in the appropriate peripheral

chapter of this data sheet.

4.3.4

GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank.

4.3.4.1

Linear Access to GPR

The general purpose RAM can be accessed in a non-

banked method via the FSRs. This can simplify access

to large memory structures. See Section 4.6.2 “Linear

Data Memory” for more information.

4.3.5

COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

4.3.6

DEVICE MEMORY MAPS

The memory maps are as shown in Table 4-4 through

Table 4-9.

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PIC16(L)F15354/55

TABLE 4-8:

PIC16(L)F15354/55 MEMORY MAP, BANKS 60, 61, 62, AND 63

Bank 60

Bank 61

Bank 62

Bank 63

—

1F8Ch

1F8Dh

1F8Eh

1F8Fh

1F90h

1F91h

1F92h

1F93h

1F94h

1F95h

1F96h

1F97h

1F98h

—

1E0Ch

1E0Dh

1E0Eh

1E0Fh

1E10h

1E11h

1E12h

1E13h

1E14h

1E15h

1E16h

1E17h

1E18h

1E19h

1E1Ah

1E8Ch

1E8Dh

1E8Eh

1E8Fh

1E90h

1E91h

1E92h

1E93h

1E94h

1E95h

1E96h

1E97h

1E98h

1E99h

1E9Ah

1F0Ch

1F0Dh

1F0Eh

1F0Fh

1F10h

1F11h

1F12h

1F13h

1F14h

1F15h

1F16h

1F17h

1F18h

1F19h

1F1Ah

—

CLCDATA

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1SEL2

CLC1SEL3

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2SEL2

CLC2SEL3

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3SEL2

CLC3SEL3

CLC3GLS0

CLC3GLS1

CLC3GLS2

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4SEL2

CLC4SEL3

CLC4GLS0

CLC4GLS1

CLC4GLS2

CLC4GLS3

—

PPSLOCK

—

INTPPS

RA0PPS

RA1PPS

RA2PPS

RA3PPS

RA4PPS

RA5PPS

RA6PPS

RA7PPS

RB0PPS

RB1PPS

RB2PPS

RB3PPS

RB4PPS

RB5PPS

RB6PPS

RB7PPS

RC0PPS

RC1PPS

RC2PPS

RC3PPS

RC4PPS

RC5PPS

RC6PPS

RC7PPS

—

T0CKIPPS

T1CKIPPS

T1GPPS

—

1F99h

1F9Ah

—

1F9Bh

1F9Ch

1F9Dh

1F9Eh

1F9Fh

1E1Bh

1E1Ch

1E1Dh

1E1Eh

1E1Fh

1E20h

1E21h

1E22h

1E23h

1E24h

1E25h

1E26h

1E27h

1E28h

1E29h

1E2Ah

1E9Bh

1E9Ch

1E9Dh

1E9Eh

1E9Fh

1EA0h

1EA1h

1EA2h

1EA3h

1EA4h

1EA5h

1EA6h

1EA7h

1EA8h

1EA9h

1EAAh

1F1Bh

1F1Ch

1F1Dh

1F1Eh

1F1Fh

1F20h

1F21h

1F22h

1F23h

1F24h

1F25h

1F26h

1F27h

1F28h

1F29h

1F2Ah

T2INPPS

—

1FA0h

1FA1h

1FA2h

1FA3h

1FA4h

1FA5h

1FA6h

1FA7h

1FA8h

1FA9h

1FAAh

CCP1PPS

CCP2PPS

—

1E2Bh

1E2Ch

1E2Dh

1E2Eh

1E2Fh

1E30h

1E31h

1E32h

1EABh

1EACh

1EADh

1EAEh

1F2Bh

1F2Ch

1F2Dh

1F2Eh

1F2Fh

1F30h

1F31h

1F32h

1F33h

1F34h

1F35h

1F36h

1FABh

1FACh

1FADh

1FAEh

1FAFh

1FB0h

1FB1h

1FB2h

1FB3h

1FB4h

1FB5h

—

1EAFh

1EB0h

—

CWG1PPS

—

1EB1h

1EB2h

1EB3h

1EB4h

1EB5h

1EB6h

1EB7h

1EB8h

1EB9h

1EBAh

1EBBh

1EBCh

1EBDh

1EBEh

1EBFh

1EC0h

1EC1h

1EC2h

—

1E33h

1E34h

—

1E35h

1E36h

—

1FB6h

1FB7h

1FB8h

1FB9h

1FBAh

1FBBh

1FBCh

1FBDh

1FBEh

1FBFh

—

1E37h

1E38h

1E39h

1E3Ah

1E3Bh

1E3Ch

1E3Dh

1E3Eh

1E3Fh

1E40h

1E41h

1E42h

1F37h

1F38h

—

ANSELA

WPUA

—

1F39h

1F3Ah

1F3Bh

1F3Ch

1F3Dh

1F3Eh

1F3Fh

1F40h

1F41h

1F42h

—

ODCONA

SLRCONA

INLVLA

IOCAP

—

CLCIN0PPS

—

CLCIN1PPS

—

CLCIN2PPS

—

CLCIN3PPS

IOCAN

IOCAF

—

1FC0h

1FC1h

1FC2h

—

Legend:

= Unimplemented data memory locations, read as ‘0’

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PIC16(L)F15354/55

TABLE 4-8:

PIC16(L)F15354/55 MEMORY MAP, BANKS 60, 61, 62, AND 63 (CONTINUED)

Bank 60

Bank 61

Bank 62

Bank 63

—

ADACTPPS

—

ANSELB

WPUB

1FC3h

1FC4h

1FC5h

1FC6h

1FC7h

1FC8h

1FC9h

1FCAh

1E43h

1E44h

1E45h

1E46h

1E47h

1E48h

1E49h

1E4Ah

1EC3h

1EC4h

1EC5h

1EC6h

1EC7h

1EC8h

1EC9h

1ECAh

1F43h

1F44h

1F45h

1F46h

1F47h

1F48h

1F49h

1F4Ah

—

SSP1CLKPPS

ODCONB

SLRCONB

INLVLB

IOCBP

SSP1DATPPS

SSP1SSPPS

SSP2CLKPPS

SSP2DATPPS

IOCBN

IOCBF

SSP2SSPPS

RX1DTPPS

—

1FCBh

1FCCh

1FCDh

1FCEh

1FCFh

1FD0h

1FD1h

1FD2h

1FD3h

1FD4h

1FD5h

1E4Bh

1E4Ch

1E4Dh

1E4Eh

1E4Fh

1E50h

1E51h

1E52h

1E53h

1E54h

1E55h

1E56h

1E57h

1E58h

1E59h

1E5Ah

1ECBh

1ECCh

1ECDh

1ECEh

1ECFh

1ED0h

1ED1h

1ED2h

1ED3h

1ED4h

1ED5h

1ED6h

1ED7h

1ED8h

1ED9h

1EDAh

1F4Bh

1F4Ch

1F4Dh

1F4Eh

1F4Fh

1F50h

1F51h

1F52h

1F53h

1F54h

1F55h

1F56h

1F57h

1F58h

1F59h

1F5Ah

TX1CKPPS

RX2DTPPS

TX2CKPPS

—

ANSELC

WPUC

—

ODCONC

SLRCONC

INLVLC

IOCCP

—

IOCCN

IOCCF

—

1FD6h

1FD7h

1FD8h

1FD9h

1FDAh

1FDBh

1FDCh

1FDDh

1FDEh

1FDFh

1FE0h

1FE1h

1FE2h

1FE3h

1FE4h

1FE5h

1FE6h

1FE7h

1FE8h

1FE9h

1FEAh

1FEBh

—

1E5Bh

1E5Ch

1E5Dh

1E5Eh

1E5Fh

1E60h

1E61h

1E62h

1EDBh

1EDCh

1EDDh

1EDEh

1F5Bh

1F5Ch

1F5Dh

1F5Eh

1F5Fh

1F60h

1F61h

1F62h

1F63h

1F64h

1F65h

1F66h

—

1EDFh

1EE0h

—

1EE1h

1EE2h

1EE3h

1EE4h

1EE5h

1EE6h

1EE7h

1EE8h

1EE9h

1EEAh

1EEBh

1EECh

1EEDh

1EEEh

1EEFh

—

BSR_ICDSHAD

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

—

1E63h

1E64h

—

WPUE

—

1E65h

1E66h

—

1E67h

1E68h

1F67h

1F68h

—

INLVLE

IOCEP

IOCEN

IOCEF

—

1E69h

1E6Ah

1E6Bh

1E6Ch

1E6Dh

1E6Eh

1F69h

1F6Ah

1F6Bh

1F6Ch

1F6Dh

1F6Eh

—

1FECh

1FEDh

1FEEh

1FEFh

—

STKPTR

—

TOSL

—

TOSH

1E6Fh

1F6Fh

Legend:

= Unimplemented data memory locations, read as ‘0’

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TABLE 4-9:

SPECIAL FUNCTION REGISTER SUMMARY BANKS 0-63 (ALL BANKS)

Bank Offset

Bank 0-Bank 63

Value on:

POR, BOR

Value on:

MCLR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All Banks

Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a

physical register)

x00h or x80h

INDF0

xxxx xxxx xxxx xxxx

Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a

physical register)

x01h or x81h

INDF1

x02h or x82h

x03h or x83h

x04h or x84h

x05h or x85h

x06h or x86h

x07h or x87h

x08h or x88h

x09h or x89h

x0Ah or x8Ah

x0Bh or x8Bh

PCL

0000 0000 0000 0000

---1 1000 ---q quuu

0000 0000 uuuu uuuu

0000 0000 0000 0000

0000 0000 uuuu uuuu

0000 0000 0000 0000

--00 0000 --00 0000

0000 0000 uuuu uuuu

-000 0000 -000 0000

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

—

TO

PD

Z

DC

C

FSR0L

Indirect Data Memory Address 0 Low Pointer

FSR0H Indirect Data Memory Address 0 High Pointer

FSR1L Indirect Data Memory Address 1 Low Pointer

FSR1H Indirect Data Memory Address 1 High Pointer

BSR<5:0>

—

WREG

PCLATH

INTCON

Working Register

—

Write Buffer for the upper 7 bits of the Program Counter

PEIE

GIE

—

INTEDG 00-- ---1 00-- ---1

Legend:

x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations

unimplemented, read as ‘0’.

Note 1:

These Registers can be accessed from any bank.

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4.4.2

COMPUTED GOTO

4.4

PCL and PCLATH

A computed GOTOis accomplished by adding an offset to

the program counter (ADDWF PCL). When performing a

table read using a computed GOTOmethod, care should

be exercised if the table location crosses a PCL memory

boundary (each 256-byte block). Refer to Application

Note AN556, “Implementing a Table Read” (DS00556).

The Program Counter (PC) is 15 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<14:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 4-4 shows the five

situations for the loading of the PC.

4.4.3

COMPUTED FUNCTION CALLS

FIGURE 4-4:

LOADING OF PC IN

A computed function CALLallows programs to maintain

tables of functions and provide another way to execute

state machines or look-up tables. When performing a

table read using a computed function CALL, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block).

DIFFERENT SITUATIONS

Rev. 10-000042A

7/30/2013

PCH

7

14

PCL

0

Instruction

with PCL as

Destination

PC

8

6

0

If using the CALLinstruction, the PCH<2:0> and PCL

registers are loaded with the operand of the CALL

instruction. PCH<6:3> is loaded with PCLATH<6:3>.

PCLATH

ALU result

PCH

14

6

PCL

0

The CALLW instruction enables computed calls by

combining PCLATH and W to form the destination

address. A computed CALLW is accomplished by

loading the W register with the desired address and

executing CALLW. The PCL register is loaded with the

value of W and PCH is loaded with PCLATH.

GOTO,

CALL

PC

4

11

OPCODE <10:0>

PCLATH

PCH

7

14

6

PCL

0

CALLW

PC

4.4.4

BRANCHING

8

W

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses

page boundaries. There are two forms of branching,

BRW and BRA. The PC will have incremented to fetch

the next instruction in both cases. When using either

branching instruction, a PCL memory boundary may be

crossed.

PCLATH

14

PCL

0

PCH

BRW

BRA

PC

15

PC + W

If using BRW, load the W register with the desired

unsigned address and execute BRW. The entire PC will

be loaded with the address PC + 1 + W.

15

If using BRA, the entire PC will be loaded with

PC + 1 + the signed value of the operand of the BRA

instruction.

PC + OPCODE <8:0>

4.4.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<14:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by writ-

ing the desired upper seven bits to the PCLATH regis-

ter. When the lower eight bits are written to the PCL

register, all 15 bits of the program counter will change

to the values contained in the PCLATH register and

those being written to the PCL register.

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4.5.1

ACCESSING THE STACK

4.5

Stack

The stack is accessible through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS

is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR,

which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is five bits to allow detection of

overflow and underflow.

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figure 4-5 through Figure 4-8). The

stack space is not part of either program or data space.

The PC is PUSHed onto the stack when CALL or

CALLWinstructions are executed or an interrupt causes

a branch. The stack is POPed in the event of a

RETURN, RETLW or a RETFIE instruction execution.

PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN

bit is programmed to ‘0‘ (Configuration Words). This

means that after the stack has been PUSHed sixteen

times, the seventeenth PUSH overwrites the value that

was stored from the first PUSH. The eighteenth PUSH

overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an

Overflow/Underflow, regardless of whether the Reset is

enabled.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation, CALL, CALLWand

interrupts will increment STKPTR while RETLW,

RETURN, and RETFIE will decrement STKPTR.

STKPTR can be monitored to obtain to value of stack

memory left at any given time. The STKPTR always

points at the currently used place on the stack.

Therefore, a CALL or CALLW will increment the

STKPTR and then write the PC, and a return will

unload the PC value from the stack and then

decrement the STKPTR.

Note 1: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, CALLW, RETURN, RETLW and

RETFIE instructions or the vectoring to

an interrupt address.

Reference Figure 4-5 through Figure 4-8 for examples

of accessing the stack.

FIGURE 4-5:

ACCESSING THE STACK EXAMPLE 1

Rev. 10-000043A

7/30/2013

Stack Reset Disabled

STKPTR = 0x1F

TOSH:TOSL

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

0x1F

(STVREN = 0)

Initial Stack Configuration:

After Reset, the stack is empty. The

empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL register will return ‘0’. If the

Stack Overflow/Underflow Reset is

disabled, the TOSH/TOSL register will

return the contents of stack address

0x0F.

Stack Reset Enabled

STKPTR = 0x1F

TOSH:TOSL

0x0000

(STVREN = 1)

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FIGURE 4-6:

ACCESSING THE STACK EXAMPLE 2

Rev. 10-000043B

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

This figure shows the stack configuration

after the first CALL or a single interrupt.

If a RETURNinstruction is executed, the

return address will be placed in the

Program Counter and the Stack Pointer

decremented to the empty state (0x1F).

STKPTR = 0x00

TOSH:TOSL

0x00

Return Address

FIGURE 4-7:

ACCESSING THE STACK EXAMPLE 3

Rev. 10-000043C

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

After seven CALLs or six CALLs and an

interrupt, the stack looks like the figure on

the left. A series of RETURNinstructions will

repeatedly place the return addresses into

the Program Counter and pop the stack.

STKPTR = 0x06

TOSH:TOSL

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

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FIGURE 4-8:

ACCESSING THE STACK EXAMPLE 4

Rev. 10-000043D

7/30/2013

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

When the stack is full, the next CALLor

an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00 so

the stack will wrap and overwrite the

return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will

not be overwritten.

STKPTR = 0x10

TOSH:TOSL

4.5.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Words (Register 5-2)

is programmed to ‘1’, the device will be Reset if the

stack is PUSHed beyond the sixteenth level or POPed

beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON

register.

4.6

Indirect Addressing

The INDFn registers are not physical registers. Any

instruction that accesses an INDFn register actually

accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address

specifies one of the two INDFn registers, the read will

return ‘0’ and the write will not occur (though Status bits

may be affected). The FSRn register value is created

by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an

addressing space with 65536 locations. These locations

are divided into three memory regions:

• Traditional/Banked Data Memory

• Linear Data Memory

• Program Flash Memory

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FIGURE 4-9:

INDIRECT ADDRESSING PIC16(L)F15354

Rev. 10-000044B

9/16/2016

0x0000

Traditional

Data Memory

0x1FFF

0x2000

Linear

Data Memory

0X2FEF

0X2FF0

Reserved

0x7FFF

0x8000

FSR

Address

Range

PC value = 0x000

Program

Flash Memory

0x8FFF

PC value = 0xFFF

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FIGURE 4-10:

INDIRECT ADDRESSING PIC16(L)F15355

Rev. 10-000044C

9/16/2016

0x0000

Traditional

Data Memory

0x1FFF

0x2000

Linear

Data Memory

0X2FEF

0X2FF0

Reserved

0x7FFF

0x8000

FSR

Address

Range

PC value = 0x0000

Program

Flash Memory

0x9FFF

PC value = 0x1FFF

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4.6.1

TRADITIONAL/BANKED DATA

MEMORY

The traditional or banked data memory is a region from

FSR address 0x000 to FSR address 0x1FFF. The

addresses correspond to the absolute addresses of all

SFR, GPR and common registers.

FIGURE 4-11:

TRADITIONAL/BANKED DATA MEMORY MAP

Rev. 10-000056B

12/14/2016

Direct Addressing

Indirect Addressing

From Opcode

0

BSR

5

0

6

7

FSRxH

0

7

FSRxL

0

0 0 0

Bank Select Location Select

000000 000001 000010

Bank Select

Location Select

111111

0x00

0x7F

Bank 63

Bank 0 Bank 1 Bank 2

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4.6.2

LINEAR DATA MEMORY

4.6.3

PROGRAM FLASH MEMORY

The linear data memory is the region from FSR

address 0x2000 to FSR address 0X2FEF. This region

is a virtual region that points back to the 80-byte blocks

of GPR memory in all the banks. Refer to Figure 4-12

for the Linear Data Memory Map.

To make constant data access easier, the entire

Program Flash Memory is mapped to the upper half of

the FSR address space. When the MSB of FSRnH is

set, the lower 15 bits are the address in program

memory which will be accessed through INDF. Only the

lower eight bits of each memory location is accessible

via INDF. Writing to the Program Flash Memory cannot

be accomplished via the FSR/INDF interface. All

instructions that access Program Flash Memory via the

FSR/INDF interface will require one additional

instruction cycle to complete.

Note:

The address range 0x2000 to 0x2FF0 rep-

resents the complete addressable Linear

Data Memory up to Bank 50. The actual

implemented Linear Data Memory will dif-

fer from one device to the other in a family.

Confirm the memory limits on every

device.

FIGURE 4-13:

PROGRAM FLASH

MEMORY MAP

Unimplemented memory reads as 0x00. Use of the

linear data memory region allows buffers to be larger

than 80 bytes because incrementing the FSR beyond

one bank will go directly to the GPR memory of the next

bank.

Rev. 10-000058A

7/31/2013

7

FSRnH

0

7

FSRnL

0

1

The 16 bytes of common memory are not included in

the linear data memory region.

Location Select

0x8000

0x0000

FIGURE 4-12:

LINEAR DATA MEMORY

MAP

Rev. 10-000057B

8/24/2016

Program

Flash

Memory

(low 8 bits)

7

FSRnH

0

7

FSRnL

0

Location Select

0x2000

0x020

Bank 0

0x06F

0x7FFF

0xFFFF

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

0x1920

Bank 50

0x196F

0x2FEF

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5.0

DEVICE CONFIGURATION

Device configuration consists of the Configuration

Words, User ID, Device ID, Device Information Area

(DIA), (see Section 6.0 “Device Information Area”),

and the Device Configuration Information (DCI)

regions, (see Section 7.0 “Device Configuration

Information”).

5.1

Configuration Words

The devices have several Configuration Words

starting at address 8007h. The Configuration bits

establish configuration values prior to the execution of

any software; Configuration bits enable or disable

device-specific features.

In terms of programming, these important

Configuration bits should be considered:

1. LVP: Low-Voltage Programming Enable bit

• 1= ON – Low-Voltage Programming is enabled.

MCLR/VPP pin function is MCLR. MCLRE

Configuration bit is ignored.

• 0= OFF – HV on MCLR/VPP must be used for

programming.

2. CP: User Nonvolatile Memory (NVM)

Program Memory Code Protection bit

• 1= OFF – User NVM code protection disabled

• 0= ON – User NVM code protection enabled

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5.2

Register Definitions: Configuration Words

REGISTER 5-1:

CONFIGURATION WORD 1: OSCILLATORS

R/P-1

U-1

R/P-1

U-1

—

U-1

—

R/P-1

FCMEN

—

CSWEN

CLKOUTEN

bit 13

bit 8

U-1

R/P-1

RSTOSC2

R/P-1

U-1

—

R/P-1

—

RSTOSC1

RSTOSC0

FEXTOSC2

FEXTOSC1

FEXTOSC0

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

x = Bit is unknown

W = Writable bit

U = Unimplemented bit, read as

‘1’

‘0’ = Bit is cleared

n = Value when blank or after

Bulk Erase

bit 13

FCMEN: Fail-Safe Clock Monitor Enable bit

1= FSCM timer enabled

0= FSCM timer disabled

bit 12

bit 11

Unimplemented: Read as ‘1’

CSWEN: Clock Switch Enable bit

1= Writing to NOSC and NDIV is allowed

0= The NOSC and NDIV bits cannot be changed by user software

bit 10-9

bit 8

Unimplemented: Read as ‘1’

CLKOUTEN: Clock Out Enable bit

If FEXTOSC = EC (high, mid or low) or Not Enabled:

1= CLKOUT function is disabled; I/O or oscillator function on OSC2

0= CLKOUT function is enabled; FOSC/4 clock appears at OSC2

Otherwise:

This bit is ignored.

bit 7

Unimplemented: Read as ‘1’

bit 6-4

RSTOSC<2:0>: Power-up Default Value for COSC bits

This value is the Reset-default value for COSC and selects the oscillator first used by user software.

111= EXTOSC operating per FEXTOSC bits

110= HFINTOSC (1 MHz) with OSCFRQ = '010' (4 MHz) and CDIV = '0010' (4:1)

101= LFINTOSC

100= SOSC

011= Reserved

010= EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits

001= HFINTOSC with 2x PLL (32 MHz), with OSCFRQ = '101' (16 MHz) and CDIV = '0000' (1:1)

000= HFINTOSC (32 MHz), with OSCFRQ = '110' (32 MHz) and CDIV = '0000' (1:1)

bit 3

Unimplemented: Read as ‘1’

bit 2-0

FEXTOSC<2:0>:FEXTOSC External Oscillator Mode Selection bits

111= EC (External Clock) above 8 MHz

110= EC (External Clock) for 100 kHz to 8 MHz

101= EC (External Clock) below 100 kHz

100= Oscillator not enabled

011= Reserved (do not use)

010= HS (Crystal oscillator) above 4 MHz

001= XT (Crystal oscillator) above 100 kHz, below 4 MHz

000= LP (Crystal oscillator) optimized for 32.768 kHz

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REGISTER 5-2:

CONFIGURATION WORD 2: SUPERVISORS

R/P-1

BORV

U-1

—

DEBUG

STVREN

PPS1WAY

ZCDDIS

bit 13

bit 8

bit 0

R/P-1

BOREN0

R/P-1

U-1

—

U-1

—

U-1

—

R/P-1

BOREN1

bit 7

LPBOREN

PWRTE

MCLRE

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

x = Bit is unknown

W = Writable bit

U = Unimplemented bit, read as

‘1’

‘0’ = Bit is cleared

n = Value when blank or after

Bulk Erase

bit 13

bit 12

bit 11

bit 10

bit 9

DEBUG: Debugger Enable bit

1= Background debugger disabled

0= Background debugger enabled

STVREN: Stack Overflow/Underflow Reset Enable bit

1= Stack Overflow or Underflow will cause a Reset

0= Stack Overflow or Underflow will not cause a Reset

PPS1WAY: PPSLOCK One-Way Set Enable bit

1= The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle

0= The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)

ZCDDIS: Zero-Cross Detect Disable bit

1= ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of the ZCDCON register

0= ZCD always enabled (ZCDSEN bit is ignored)

(1)

BORV: Brown-out Reset Voltage Selection bit

1= Brown-out Reset voltage (VBOR) set to lower trip point level

0= Brown-out Reset voltage (VBOR) set to higher trip point level

Unimplemented: Read as ‘1’

bit 8

BOREN<1:0>: Brown-out Reset Enable bits

bit 7-6

When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit

11= Brown-out Reset is enabled; SBOREN bit is ignored

10= Brown-out Reset is enabled while running, disabled in Sleep; SBOREN bit is ignored

01= Brown-out Reset is enabled according to SBOREN

00= Brown-out Reset is disabled

LPBOREN: Low-Power BOR Enable bit

1= ULPBOR is disabled

bit 5

0= ULPBOR is enabled

Unimplemented: Read as ‘1’

bit 4-2

bit 1

PWRTE: Power-up Timer Enable bit

1= PWRT is disabled

0= PWRT is enabled

MCLRE: Master Clear (MCLR) Enable bit

If LVP = 1:

bit 0

RE3 pin function is MCLR (it will reset the device when driven low)

If LVP = 0:

1= MCLR pin is MCLR (it will reset the device when driven low)

0= MCLR pin may be used as general purpose RE3 input

Note 1: See Vbor parameter for specific trip point voltages.

2: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers

and programmers. For normal device operation, this bit should be maintained as a ‘1’.

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REGISTER 5-3:

CONFIGURATION WORD 3: WINDOWED WATCHDOG

R/P-1

WDTCCS2

WDTCCS1

WDTCCS0

WDTCWS2

WDTCWS1

WDTCWS0

bit 13

bit 8

U-1

—

R/P-1

WDTE1

R/P-1

WDTE0

WDTCPS4

WDTCPS3

WDTCPS2

WDTCPS1

WDTCPS0

bit 7

bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared

P = Programmable bit

‘1’ = Bit is set

x = Bit is unknown

W = Writable bit

U = Unimplemented bit, read as ‘1’

n = Value when blank or after Bulk

Erase

bit 13-11

WDTCCS<2:0>: WDT Input Clock Selector bits

111= Software Control

110= Reserved

.

010= SOSC 32 kHz

001= WDT reference clock is the 31.25 kHz HFINTOSC (MFINTOSC) output

000= WDT reference clock is the 31.0 kHz LFINTOSC

bit 10-8

WDTCWS<2:0>: WDT Window Select bits

WDTWS at POR

Software

control of

WDTWS?

Keyed

access

required?

Window

opening

Percent of time

WDTCWS

Window delay

Percent of time

Value

111

110

101

100

011

010

001

000

111

101

100

011

010

001

000

n/a

25

100

75

Yes

No

37.5

50

62.5

50

No

Yes

62.5

75

37.5

25

87.5

12.5

bit 7

Unimplemented: Read as ‘1’

bit 6-5

WDTE<1:0>: WDT Operating mode:

11=WDT enabled regardless of Sleep; SWDTEN is ignored

10=WDT enabled while Sleep = 0, suspended when Sleep = 1; SWDTEN ignored

01=WDT enabled/disabled by SWDTEN bit in WDTCON0

00=WDT disabled, SWDTEN is ignored

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REGISTER 5-3:

CONFIGURATION WORD 3: WINDOWED WATCHDOG (CONTINUED)

bit 4-0

WDTCPS<4:0>: WDT Period Select bits

WDTPS at POR

Divider Ratio

Software Control

of WDTPS?

WDTCPS

Value

Typical Time Out

(FIN = 31 kHz)

11111⁽¹⁾

01011

1:65536

1:32

2 s

Yes

No

2¹⁶

2⁵

11110

...

11110

...

1 ms

10011

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

10010

10001

10000

01111

01110

01101

01100

01011

01010

01001

01000

00111

00110

00101

00100

00011

00010

00001

00000

1:8388608 2²³

1:4194304 2²²

1:2097152 2²¹

1:1048576 2²⁰

1:524299 2¹⁹

1:262144 2¹⁸

1:131072 2¹⁷

256 s

128 s

64 s

32 s

16 s

8 s

4 s

1:65536

1:32768

1:16384

1:8192

1:4096

1:2048

1:1024

1:512

2¹⁶

2¹⁵

2¹⁴

2¹³

2¹²

2¹¹

2¹⁰

2⁹

2 s

1 s

512 ms

256 ms

128 ms

64 ms

32 ms

16 ms

8 ms

4 ms

2 ms

1 ms

No

1:256

2⁸

1:128

2⁷

1:64

2⁶

1:32

2⁵

Note 1: 0b11111is the default value of the WDTCPS bits.

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REGISTER 5-4:

CONFIGURATION WORD 4: MEMORY

R/W-1

U-1

R/W-1

U-1

R/W-1

(1)

LVP

—

WRTSAF

11

—

WRTC

9

WRTB

bit 13

12

10

bit 8

R/W-1

U-1

R/W-1

(1)

WRTAPP

—

6

—

5

SAFEN

4

BBEN

3

BBSIZE2

2

BBSIZE1

1

BBSIZE0

bit 0

bit 7

Legend:

R = Readable bit

P = Programmable bit

‘1’ = Bit is set

x = Bit is unknown

W = Writable bit

U = Unimplemented bit, read

as ‘1’

‘0’ = Bit is cleared

n = Value when blank or after

Bulk Erase

bit 13

LVP: Low Voltage Programming Enable bit

1= Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is ignored.

0= HV on MCLR/VPP must be used for programming.

The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this

rule is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally

eliminating LVP mode from the configuration state.

The preconditioned (erased) state for this bit is critical.

bit 12

bit 11

Unimplemented: Read as ‘1’

WRTSAF: Storage Area Flash Write Protection bit

1= SAF NOT write-protected

0= SAF write-protected

Unimplemented, if SAF is not supported in the device family and only applicable if SAFEN = 0.

bit 10

bit 9

Unimplemented: Read as ‘1’

WRTC: Configuration Register Write Protection bit

1= Configuration Register NOT write-protected

0= Configuration Register write-protected

bit 8

bit 7

WRTB: Boot Block Write Protection bit

1= Boot Block NOT write-protected

0= Boot Block write-protected

Only applicable if BBEN = 0.

WRTAPP: Application Block Write Protection bit

1= Application Block NOT write-protected

0= Application Block write-protected

bit 6-5

bit 4

Unimplemented: Read as ‘1’

SAFEN: SAF Enable bit

1= SAF disabled

0= SAF enabled

bit 3

BBEN: Boot Block Enable bit

1= Boot Block disabled

0= Boot Block enabled

bit 2-0

BBSIZE<2:0>: Boot Block Size Selection bits (See Table 5-1)

BBSIZE is used only when BBEN = 0

BBSIZ bits can only be written while BBEN = 1; after BBEN = 0, BBSIZ is write-protected.

Note 1: Bits are implemented as sticky bits. Once protection is enabled, it can only be reset through a Bulk Erase.

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PIC16(L)F15354/55

TABLE 5-1:

BBEN

BOOT BLOCK SIZE BITS

Actual Boot Block Size

User Program Memory Size (words)

Last Boot Block

Memory Access

BBSIZE<2:0>

PIC16(L)F15354

PIC16(L)F15355

1

0

xxx

111

0

—

512

01FFh

03FFh

07FFh

0FFFh

110

1024

2048

1024

2048

4096

101

100-000

Note:

The maximum boot block size is half the user program memory size. All selections higher than the

maximum are set to half size. For example, all BBSIZE = 000- 100produce a boot block size of 4kW on

a 8kW device.

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REGISTER 5-5:

CONFIGURATION WORD 5: CODE PROTECTION

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

bit 13

bit 8

bit 0

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

R/P-1

CP

—

bit 7

Legend:

R = Readable bit

‘0’ = Bit is cleared

P = Programmable bit

‘1’ = Bit is set

x = Bit is unknown

W = Writable bit

U = Unimplemented bit, read as ‘1’

n = Value when blank or after Bulk

Erase

bit 13-1

bit 0

Unimplemented: Read as ‘1’

CP: Program Flash Memory Code Protection bit

1 = Program Flash Memory code protection disabled

0 = Program Flash Memory code protection enabled

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5.3

Code Protection

Code protection allows the device to be protected from

unauthorized access. Program memory protection and

data memory are controlled independently. Internal

access to the program memory is unaffected by any

code protection setting.

5.3.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from

external reads and writes by the CP bit in Configuration

Words. When CP = 0, external reads and writes of

program memory are inhibited and a read will return all

‘0’s. The CPU can continue to read program memory,

regardless of the protection bit settings. Self-writing the

program memory is dependent upon the write

protection

setting.

See

Section 5.4

“Write

Protection” for more information.

5.4

Write Protection

Write protection allows the device to be protected from

unintended self-writes. Applications, such as boot

loader software, can be protected while allowing other

regions of the program memory to be modified.

The WRTAPP, WRTSAF, WRTB, WRTC bits in

Configuration Words (Register 5-4) define whether the

corresponding region of the program memory block is

protected or not.

5.5

User ID

Four memory locations (8000h-8003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

readable and writable during normal execution. See

Section 13.3.6 “NVMREG Access to Device

Information Area, Device Configuration Area, User

ID, Device ID and Configuration Words” for more

information on accessing these memory locations. For

more information on checksum calculation, see the

“PIC16(L)F153xx Memory Programming Specification”

(DS40001838).

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5.6

Device ID and Revision ID

The 14-bit Device ID word is located at 8006h and the

14-bit Revision ID is located at 8005h. These locations

are read-only and cannot be erased or modified.

Development tools, such as device programmers and

debuggers, may be used to read the Device ID,

Revision ID and Configuration Words. These locations

can also be read from the NVMCON register.

5.7

Register Definitions: Device and Revision

REGISTER 5-6:

DEVID: DEVICE ID REGISTER

R

DEV<13:8>

bit 13

bit 8

bit 0

R

DEV<7:0>

bit 7

Legend:

R = Readable bit

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 13-0

DEV<13:0>: Device ID bits

Device

DEVID<13:0> Values

PIC16F15354

PIC16LF15354

PIC16F15355

PIC16LF15355

11 0000 1010 1100 (30ACh)

11 0000 1010 1101 (30ADh)

11 0000 1010 1110 (30AEh)

11 0000 1010 1111 (30AFh)

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REGISTER 5-7:

REVISIONID: REVISION ID REGISTER

R

1

R

0

R

MJRREV<5:0>

MNRREV<5:0>

bit 13

bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared

‘1’ = Bit is set

x = Bit is unknown

bit 13-12 Fixed Value: Read-only bits

These bits are fixed with value ‘10’ for all devices included in this data sheet.

bit 11-6 MJRREV<5:0>: Major Revision ID bits

These bits are used to identify a major revision.

bit 5-0

MNRREV<5:0>: Minor Revision ID bits

These bits are used to identify a minor revision.

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The complete DIA table is shown in Table 6-1: Device

Information Area, followed by a description of each

region and its functionality. The data is mapped from

8100h to 811Fh in the PIC16(L)F15354/55 family.

These locations are read-only and cannot be erased or

modified. The data is programmed into the device

during manufacturing.

6.0

DEVICE INFORMATION AREA

The Device Information Area (DIA) is a dedicated

region in the program memory space; it is a new feature

in the PIC16(L)F15354/55 family of devices. The DIA

contains the calibration data for the internal

temperature indicator module, stores the Microchip

Unique Identifier words and the Fixed Voltage

Reference voltage readings measured in mV.

TABLE 6-1:

DEVICE INFORMATION AREA

Address Range

Name of Region

Standard Device Information

MUI0

MUI1

MUI2

MUI3

8100h-8108h

MUI4

MUI5

Microchip Unique Identifier (9 Words)

MUI6

MUI7

MUI8

8109h

MUI9

1 Word Reserved

EUI0

EUI1

EUI2

EUI3

810Ah-8111h

Unassigned (8 Words)

EUI4

EUI5

EUI6

EUI7

8112h

Reserved

TSLR2

Reserved

TSHR2

Reserved

FVRA1X

FVRA2X

Unassigned (1 word)

8113h

Temperature indicator ADC reading at 90°C (low range setting)

Unassigned (1 word)

8114h

8115h

Unassigned (1 word)

8116h

Temperature indicator ADC reading at 90°C (high range setting)

Unassigned (1 Word)

8117h

8118h

ADC FVR1 Output voltage for 1x setting (in mV)

ADC FVR1 Output Voltage for 2x setting (in mV)

ADC FVR1 Output Voltage for 4x setting (in mV)

Comparator FVR2 output voltage for 1x setting (in mV)

Comparator FVR2 output voltage for 2x setting (in mV)

Comparator FVR2 output voltage for 4x setting (in mV)

Unassigned (2 Words)

8119h

(1)

811Ah

811Bh

811Ch

811Dh

811Eh-811Fh

FVRA4X

FVRC1X

FVRC2X

(1)

FVRC4X

Note 1: Value not present on LF devices.

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6.1

Microchip Unique identifier (MUI)

6.3

Analog-to-Digital Conversion Data

of the Temperature Sensor

The PIC16(L)F15354/55 devices are individually

encoded during final manufacturing with a Microchip

Unique Identifier, or MUI. The MUI cannot be erased by

a Bulk Erase command or any other user-accessible

means. This feature allows for manufacturing traceabil-

ity of Microchip Technology devices in applications

where this is a required. It may also be used by the

application manufacturer for a number of functions that

require unverified unique identification, such as:

The purpose of the temperature indicator module is to

provide a temperature-dependent voltage that can be

measured by an analog module. Section 19.0 “Tem-

perature Indicator Module” explains the operation of

the Temperature Indicator module and defines terms

such as the low range and high range settings of the

sensor.

The DIA table contains the internal ADC measurement

values of the temperature sensor for low and high

range at fixed points of reference. The values are

measured during test and are unique to each device.

The right-justified ADC readings are stored in the DIA

memory region. The calibration data can be used to

plot the approximate sensor output voltage, VTSENSE

vs. Temperature curve.

• Tracking the device

• Unique serial number

The MUI consists of nine program words. When taken

together, these fields form a unique identifier. The MUI

is stored in nine read-only locations, located between

8100h to 8109h in the DIA space. Table 6-1 lists the

addresses of the identifier words.

• TSLR2: Address 8113h stores the measurements

for the low range setting of the temperature

sensor at VDD = 3V.

• TSHR2: Address 8116h stores the measurements

for the high range setting of the temperature

sensor at VDD = 3V.

Note:

For applications that require verified unique

identification, contact your Microchip Tech-

nology sales office to create a Serialized

Quick Turn Programming option.

6.2

External Unique Identifier (EUI)

The stored measurements are made by the device

ADC using the internal VREF = 2.048V.

The EUI data is stored at locations 810Ah to 8111h in

the program memory region. This region is an optional

space for placing application specific information. The

data is coded per customer requirements during

manufacturing. The EUI cannot be erased by a Bulk

Erase command.

6.4

Fixed Voltage Reference Data

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

Note:

Data is stored in this address range on

receiving a request from the customer.

The customer may contact the local sales

representative or Field Applications

Engineer, and provide them the unique

identifier information that is required to be

stored in this region.

• ADC input channel

• ADC positive reference

• Comparator positive input

• Digital-to-Analog Converter

For more information on the FVR, refer to Section 18.0

“Fixed Voltage Reference (FVR)”.

The DIA stores measured FVR voltages for this device

in mV for the different buffer settings of 1x, 2x or 4x at

program memory locations 8118h to 811Dh.

• FVRA1X stores the value of ADC FVR1 Output

voltage for 1x setting (in mV)

• FVRA2X stores the value of ADC FVR1 Output

Voltage for 2x setting (in mV)

• FVRA4X stores the value of ADC FVR1 Output

Voltage for 4x setting (in mV)

• FVRC1X stores the value of Comparator FVR2

output voltage for 1x setting (in mV)

• FVRC2X stores the value of Comparator FVR2

output voltage for 2x setting (in mV)

• FVRC4X stores the value of Comparator FVR2

output voltage for 4x setting (in mV)

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Refer to Table 7-1 for the complete DCI table address

and description. The DCI holds information about the

device which is useful for programming and bootloader

applications. These locations are read-only and cannot

be erased or modified.

7.0

DEVICE CONFIGURATION

INFORMATION

The Device Configuration Information (DCI) is a

dedicated region in the Program Flash Memory

mapped from 8200h to 821Fh. The data stored in the

DCI memory is hard-coded into the device during

manufacturing.

TABLE 7-1:

DEVICE CONFIGURATION INFORMATION FOR PIC16(L)F15354/55 DEVICES

VALUE

ADDRESS

Name

DESCRIPTION

UNITS

PIC16(L)F15354

PIC16(L)F15355

8200h

8201h

8202h

8203h

8204h

ERSIZ

WLSIZ

URSIZ

EESIZ

PCNT

Erase Row Size

32

128

0

32

256

0

Words

Latches

Rows

Bytes

Pins

Number of write latches

Number of User Rows

EE Data memory size

Pin Count

28

7.1

DIA and DCI Access

The DIA and DCI data are read-only and cannot be

erased or modified. See 13.3.6 “NVMREG Access to

Device Information Area, Device Configuration

Area, User ID, Device ID and Configuration Words”

for more information on accessing these memory

locations.

Development tools, such as device programmers and

debuggers, may be used to read the DIA and DCI

regions, similar to the Device ID and Revision ID.

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A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 8-1.

8.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WWDT Reset

• RESETinstruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

• Memory Violation Reset (MEMV)

To allow VDD to stabilize, an optional Power-up Timer

can be enabled to extend the Reset time after a BOR

or POR event.

FIGURE 8-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Rev. 10-000006F

8/30/2016

ICSP™ Programming Mode Exit

RESETInstruction

Memory Violation

Stack Underflow

Stack Overflow

VPP/MCLR

MCLRE

WWDT Time-out/

Window violation

Device

Reset

Power-on

Reset

VDD

Brown-out

R

(1)

Power-up

Timer

Reset

ꢀ

LFINTOSC

PWRTE

LPBOR

Reset

Note 1: See Table 8-1 for BOR active conditions.

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8.1

Power-on Reset (POR)

The POR circuit holds the device in Reset until VDD has

reached an acceptable level for minimum operation.

Slow rising VDD, fast operating speeds or analog

performance may require greater than minimum VDD.

The PWRT, BOR or MCLR features can be used to

extend the start-up period until all device operation

conditions have been met.

8.2

Brown-out Reset (BOR)

The BOR circuit holds the device in Reset when VDD

reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for

execution protection can be implemented.

The Brown-out Reset module has four operating

modes controlled by the BOREN<1:0> bits in

Configuration Words. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Table 8-1 for more information.

The Brown-out Reset voltage level is selectable by

configuring the BORV bit in Configuration Words.

A VDD noise rejection filter prevents the BOR from

triggering on small events. If VDD falls below VBOR for

a duration greater than parameter TBORDC, the device

will reset. See Figure 8-2 for more information.

TABLE 8-1:

BOREN<1:0>

11

BOR OPERATING MODES

Instruction Execution upon:

Release of POR or Wake-up from Sleep

SBOREN

Device Mode

BOR Mode

X

Awake

Sleep

X

Active

Wait for release of BOR⁽¹⁾(BORRDY = 1)

Waits for release of BOR (BORRDY = 1)

Waits for BOR Reset release

10

Disabled

Active

1

0

X

Waits for BOR Reset release (BORRDY = 1)

Begins immediately (BORRDY = x)

01

00

X

Disabled

X

Note 1:In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR

ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR

circuit is forced on by the BOREN<1:0> bits.

8.2.1

BOR IS ALWAYS ON

8.2.2

BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Words are

programmed to ‘11’, the BOR is always on. The device

start-up will be delayed until the BOR is ready and VDD

is higher than the BOR threshold.

When the BOREN bits of Configuration Words are

programmed to ‘10’, the BOR is on, except in Sleep.

The device start-up will be delayed until the BOR is

ready and VDD is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does

not delay wake-up from Sleep.

BOR protection is not active during Sleep. The device

wake-up will be delayed until the BOR is ready.

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8.2.3

BOR CONTROLLED BY SOFTWARE

8.2.4

BOR IS ALWAYS OFF

When the BOREN bits of Configuration Words are

programmed to ‘01’, the BOR is controlled by the

SBOREN bit of the BORCON register. The device start-

up is not delayed by the BOR ready condition or the

VDD level.

When the BOREN bits of the Configuration Words are

programmed to ‘00’, the BOR is off at all times. The

device start-up is not delayed by the BOR ready

condition or the VDD level.

BOR protection begins as soon as the BOR circuit is

ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

FIGURE 8-2:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

TPWRT

VDD

VBOR

Internal

Reset

< TPWRT

(1)

TPWRT

VDD

VBOR

Internal

Reset

(1)

TPWRT

Note 1: TPWRT delay only if PWRTE bit is programmed to ‘0’.

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8.3

Register Definitions: Brown-out Reset Control

REGISTER 8-1:

R/W-1/u

SBOREN⁽¹⁾

BORCON: BROWN-OUT RESET CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-q/u

BORRDY

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

SBOREN: Software Brown-out Reset Enable bit⁽¹⁾

If BOREN <1:0> in Configuration Words  01:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Words = 01:

1= BOR Enabled

0= BOR Disabled

bit 6-1

bit 0

Unimplemented: Read as ‘0’

BORRDY: Brown-out Reset Circuit Ready Status bit

1= The Brown-out Reset circuit is active

0= The Brown-out Reset circuit is inactive

Note 1: BOREN<1:0> bits are located in Configuration Words.

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8.5.2

MCLR DISABLED

8.4

Low-Power Brown-out Reset

(LPBOR)

When MCLR is disabled, the pin functions as a general

purpose input and the internal weak pull-up is under

software control. See Section 14.1 “I/O Priorities” for

more information.

The Low-Power Brown-out Reset (LPBOR) is an

important part of the Reset subsystem. Refer to

Figure 8-1 to see how the BOR and LPBOR interact

with other modules.

8.6

Windowed Watchdog Timer

(WWDT) Reset

The LPBOR is used to monitor the external VDD pin.

When too low of a voltage is detected, the device is

held in Reset.

The Watchdog Timer generates a Reset if the firmware

does not issue a CLRWDTinstruction within the time-out

period and the window is open. The TO and PD bits in

the STATUS register and the WDT bit in PCON are

changed to indicate a WDT Reset caused by the timer

overflowing, and WDTWV bit in the PCON register is

changed to indicate a WDT Reset caused by a window

violation. See Section 12.0 “Windowed Watchdog

Timer (WWDT)” for more information.

8.4.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of the

Configuration Word (Register 5-1). When the device is

erased, the LPBOR module defaults to disabled.

8.4.2

LPBOR MODULE OUTPUT

The output of the LPBOR module is a signal indicating

whether or not a Reset is to be asserted. When this

occurs, a register bit (BOR) is changed to indicate that

a BOR Reset has occurred. The same bit is set for

either the BOR or the LPBOR (refer to Register 8-3).

This signal is OR’d with the output of the BOR module

to provide the generic BOR signal, which goes to the

PCON register and to the power control block. Refer to

Figure 8-1 for the OR gate connections of the BOR and

LPBOR Reset signals, which eventually generates one

common BOR Reset.

8.7

RESETInstruction

A RESETinstruction will cause a device Reset. The RI

bit in the PCON register will be set to ‘0’. See Table 8-4

for default conditions after a RESET instruction has

occurred.

8.8

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON

register indicate the Reset condition. These Resets are

enabled by setting the STVREN bit in Configuration

Words. See Section 4.5.2 “Overflow/Underflow

Reset” for more information.

8.5

MCLR

The MCLR is an optional external input that can reset

the device. The MCLR function is controlled by the

MCLRE bit of Configuration Words and the LVP bit of

Configuration Words (Table 8-2).

8.9

Programming Mode Exit

Upon exit of In-Circuit Serial Programming™ (ICSP™)

mode, the device will behave as if a POR had just

occurred (the device does not reset upon run time self-

programming/erase operations).

TABLE 8-2:

MCLRE

MCLR CONFIGURATION

LVP

MCLR

0

1

x

0

1

Disabled

Enabled

8.10 Power-up Timer

The Power-up Timer optionally delays device execution

after a BOR or POR event. This timer is typically used to

allow VDD to stabilize before allowing the device to start

running.

8.5.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the device

is held in Reset. The MCLR pin is connected to VDD

through an internal weak pull-up. Refer to Section 2.3

“Master Clear (MCLR) Pin” for recommended MCLR

connections.

The Power-up Timer is controlled by the PWRTE bit of

the Configuration Words.

The Power-up Timer provides a nominal 64 ms time out

on POR or Brown-out Reset. The device is held in

Reset as long as PWRT is active. The PWRT delay

allows additional time for the VDD to rise to an accept-

able level. The Power-up Timer is enabled by clearing

the PWRTE bit in the Configuration Words. The Power-

up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

Note:

A Reset does not drive the MCLR pin low.

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8.11 Start-up Sequence

Upon the release of a POR or BOR, the following must

occur before the device will begin executing:

1. Power-up Timer runs to completion (if enabled).

2. Oscillator start-up timer runs to completion (if

required for oscillator source).

3. MCLR must be released (if enabled).

The total time-out will vary based on oscillator

configuration and Power-up Timer Configuration. See

Section 9.0 “Oscillator Module (with Fail-Safe

Clock Monitor)” for more information.

The Power-up Timer runs independently of MCLR

Reset. If MCLR is kept low long enough, the Power-up

Timer and oscillator start-up timer will expire. This is

useful for testing purposes or to synchronize more than

one device operating in parallel. See Figure 8-3.

FIGURE 8-3:

RESET START-UP SEQUENCE

Rev. 10-000032C

9/14/2016

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Int. Oscillator

FOSC

code execution ⁽¹⁾

Begin Execution

Internal Oscillator, PWRTEN = 0

Internal Oscillator, PWRTEN = 1

VDD

Internal POR

Power-up Timer

MCLR

TPWRT

Internal RESET

Ext. Clock (EC)

FOSC

Begin Execution

code execution ⁽¹⁾

External Clock (EC modes), PWRTEN = 0

External Clock (EC modes), PWRTEN = 1

Note 1: Code execution begins 10 FOSC cycles after the FOSC clock is released.

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8.12 Memory Execution Violation

A

Memory Execution Violation Reset occurs if

executing an instruction being fetched from outside the

valid execution area. The different valid execution

areas are defined as follows:

• Flash Memory: Table 4-1 shows the addresses

available on the PIC16(L)F15354/55 devices

based on user Flash size. Execution outside this

region generates a memory execution violation.

• Storage Area Flash (SAF): If Storage Area Flash

(SAF) is enabled (Section 4.2.3 “Storage Area

Flash”), the SAF area (Table 4-2) is not a valid

execution area.

Prefetched instructions that are not executed do not

cause memory execution violations. For example, a

GOTOinstruction in the last memory location will prefetch

from an invalid location; this is not an error. If an

instruction from an invalid location tries to execute, the

memory violation is generated immediately, and any

concurrent interrupt requests are ignored. When a

memory execution violation is generated, the device is

reset and flag MEMV is cleared in PCON1 (Register 8-3)

to signal the cause. The flag needs to be set in code after

a memory execution violation.

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8.13 Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON registers are updated to indicate the cause of

the Reset. Table 8-3 and Table 8-4 show the Reset

conditions of these registers.

TABLE 8-3:

RESET STATUS BITS AND THEIR SIGNIFICANCE

Condition

0

u

1

u

0

u

1

u

1

u

0

u

1

u

0

u

1

u

0

u

0

u

x

0

u

1

0

x

1

0

1

u

1

u

1

x

0

1

u

0

u

0

u

1

u

1

u

0

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WWDT Reset

WWDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

Memory violation Reset

TABLE 8-4:

RESET CONDITION FOR SPECIAL REGISTERS

Program

Counter

STATUS

Register

PCON0

Register

PCON1

Register

Condition

Power-on Reset

0000h

---1 1000

---u uuuu

0011 110x

uuuu 0uuu

---- --1-

MCLR Reset during normal operation

MCLR Reset during Sleep

WWDT Timeout Reset

0000h

PC + 1

0000h

PC + 1⁽¹⁾

0000h

0

---1 0uuu

---0 uuuu

---0 0uuu

---u uuuu

---1 1000

---1 0uuu

---u uuuu

-uuu uuuu

uuuu 0uuu

uuu0 uuuu

uuuu uuuu

uu0u uuuu

0011 11u0

uuuu uuuu

uuuu u0uu

1uuu uuuu

u1uu uuuu

uuuu uuuu

---- --u-

---- --0-

WWDT Wake-up from Sleep

WWDT Window Violation

Brown-out Reset

Interrupt Wake-up from Sleep

RESETInstruction Executed

Stack Overflow Reset (STVREN = 1)

Stack Underflow Reset (STVREN = 1)

Memory Violation Reset (MEMV = 0)

Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.

Note 1:When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

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8.14 Power Control (PCONx) Registers

The Power Control (PCONx) registers contain flag bits

to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Watchdog Timer Window Violation Reset

(WDTWV)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

• Memory Violation Reset (MEMV)

The PCON0 register bits are shown in Register 8-2.

The PCON1 register bits are shown in Register 8-3.

Hardware will change the corresponding register bit

during the Reset process; if the Reset was not caused

by the condition, the bit remains unchanged (Table 8-4).

Software should reset the bit to the inactive state after

the restart (hardware will not reset the bit).

Software may also set any PCON bit to the active state,

so that user code may be tested, but no reset action will

be generated.

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8.15 Register Definitions: Power Control

REGISTER 8-2:

R/W/HS-0/q R/W/HS-0/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u

STKOVF STKUNF WDTWV

bit 7

PCON0: POWER CONTROL REGISTER 0

RWDT

RMCLR

RI

POR

BOR

bit 0

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR/Value at all other Resets

q = Value depends on condition

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

STKOVF: Stack Overflow Flag bit

1= A Stack Overflow occurred

0= A Stack Overflow has not occurred or cleared by firmware

STKUNF: Stack Underflow Flag bit

1= A Stack Underflow occurred

0= A Stack Underflow has not occurred or cleared by firmware

WDTWV: WDT Window Violation Flag bit

1= A WDT Window Violation Reset has not occurred or set to ‘1’ by firmware

0= A WDT Window Violation Reset has occurred (a CLRWDTinstruction was executed either without

arming the window or outside the window (cleared by hardware)

bit 4

bit 3

bit 2

bit 1

bit 0

RWDT: Watchdog Timer Reset Flag bit

1= A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware

0= A Watchdog Timer Reset has occurred (cleared by hardware)

RMCLR: MCLR Reset Flag bit

1= A MCLR Reset has not occurred or set to ‘1’ by firmware

0= A MCLR Reset has occurred (cleared by hardware)

RI: RESETInstruction Flag bit

1= A RESETinstruction has not been executed or set to ‘1’ by firmware

0= A RESETinstruction has been executed (cleared by hardware)

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset

occurs)

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REGISTER 8-3:

PCON1: POWER CONTROL REGISTER 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HC-1/u

MEMV

U-0

—

bit 7

bit 0

Legend:

HC = Bit is cleared by hardware

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-2

bit 1

Unimplemented: Read as ‘0’

MEMV: Memory Violation Flag bit

1= No Memory Violation Reset occurred or set to ‘1’ by firmware.

0= A Memory Violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs))

bit 0

Unimplemented: Read as ‘0’

TABLE 8-5:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Register

on Page

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BORCON

PCON0

PCON1

SBOREN

—

RWDT

—

RMCLR

—

RI

—

POR

MEMV

DC

BORRDY

BOR

92

99

STKOVF STKUNF WDTWV

—

STATUS

—

TO

PD

Z

C

30

WDTCON0

WDTPS<4:0>

SWDTEN

150

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.

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If an external clock source is selected, the FEXTOSC

bits of Configuration Word 1 must be used to select the

external clock mode.

9.0

9.1

OSCILLATOR MODULE (WITH

FAIL-SAFE CLOCK MONITOR)

The external oscillator module can be configured in one

of the following clock modes, by setting the

FEXTOSC<2:0> bits of Configuration Word 1:

Overview

The oscillator module has a wide variety of clock

sources and selection features that allow it to be used

in a wide range of applications while maximizing

performance and minimizing power consumption.

Figure 9-1 illustrates a block diagram of the oscillator

module.

1. ECL – External Clock Low-Power mode

ECL ≤ 500 kHz

2. ECM – External Clock Medium Power mode

ECM ≤ 8 MHz

3. ECH – External Clock High-Power mode

Clock sources can be supplied from external oscillators,

quartz-crystal resonators. In addition, the system clock

source can be supplied from one of two internal

oscillators and PLL circuits, with a choice of speeds

selectable via software. Additional clock features

include:

ECH ≤ 32 MHz

4. LP – 32 kHz Low-Power Crystal mode.

5. XT – Medium Gain Crystal or Ceramic Resonator

Oscillator mode (between 100 kHz and 4 MHz)

6. HS – High Gain Crystal or Ceramic Resonator

mode (above 4 MHz)

• Selectable system clock source between external

or internal sources via software.

The ECH, ECM, and ECL clock modes rely on an

external logic level signal as the device clock source.

The LP, XT, and HS clock modes require an external

crystal or resonator to be connected to the device.

Each mode is optimized for a different frequency range.

The INTOSC internal oscillator block produces low and

high-frequency clock sources, designated LFINTOSC

and HFINTOSC. (see Internal Oscillator Block,

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, ECH, ECM, ECL) and switch

automatically to the internal oscillator.

• Oscillator Start-up Timer (OST) ensures stability

of crystal oscillator sources.

The RSTOSC bits of Configuration Word 1 determine

the type of oscillator that will be used when the device

reset, including when it is first powered up.

Figure 9-1).

A

wide selection of device clock

frequencies may be derived from these clock sources.

The internal clock modes, LFINTOSC, HFINTOSC (set

at 1 MHz), or HFINTOSC (set at 32 MHz) can be set

through the RSTOSC bits.

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The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC^®MCU design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

9.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the

clock source to function. Examples are: oscillator

modules (ECH, ECM, ECL mode), quartz crystal

resonators or ceramic resonators (LP, XT and HS

modes).

There is also a secondary oscillator block which is

optimized for a 32.768 kHz external clock source,

which can be used as an alternate clock source.

FIGURE 9-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

There are two internal oscillator blocks:

CLKIN

Clock from

Ext. System

- HFINTOSC

- LFINTOSC

PIC^®MCU

OSC2/CLKOUT

The HFINTOSC can produce clock frequencies from 1-

32 MHz, and is responsible for generating the two

MFINTOSC frequencies (500 kHz and 32 kHz) that can

be used by some peripherals. The LFINTOSC

generates a 31 kHz clock frequency.

(1)

FOSC/4 or

I/O

Note 1: Output depends upon CLKOUTEN bit of the

Configuration Words.

There is a 4x PLL that can be used by the external

oscillator. See Section 9.2.1.4 “4x PLL” for more

details. Additionally, there is a PLL that can be used by

the HFINTOSC at certain frequencies. See

Section 9.2.2.2 “Internal Oscillator Frequency

Adjustment” for more details.

9.2.1.2

LP, XT, HS Modes

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

OSC1 and OSC2 (Figure 9-3). The three modes select

a low, medium or high gain setting of the internal

inverter-amplifier to support various resonator types

and speed.

9.2.1

EXTERNAL CLOCK SOURCES

An external clock source can be used as the device

system clock by performing one of the following

actions:

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is designed to

drive only 32.768 kHz tuning-fork type crystals (watch

crystals), but can operate up to 100 kHz.

• Program the RSTOSC<2:0> bits in the

Configuration Words to select an external clock

source that will be used as the default system

clock upon a device Reset

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive crystals and

resonators with a frequency range up to 4 MHz.

• Write the NOSC<2:0> and NDIV<3:0> bits in the

OSCCON1 register to switch the system clock

source

See Section 9.3 “Clock Switching” for more

information.

HS Oscillator mode selects the highest gain setting of the

internal inverter-amplifier. HS mode current consumption

is the highest of the three modes. This mode is best

suited for resonators that require operating frequencies

up to 20 MHz.

9.2.1.1

EC Mode

The External Clock (EC) mode allows an externally

generated logic level signal to be the system clock

source. When operating in this mode, an external clock

source is connected to the OSC1/CLKIN input. OSC2/

CLKOUT is available for general purpose I/O or

CLKOUT. Figure 9-2 shows the pin connections for EC

mode.

Figure 9-3 and Figure 9-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

EC mode has three power modes to select from through

Configuration Words:

• ECH – High power, 32 MHz

• ECM – Medium power, 8 MHz

• ECL – Low power, 0.1 MHz

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FIGURE 9-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 9-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

Rev. 10-000059A

7/30/2013

PIC^®MCU

OSC1/CLKIN

C1

To Internal

Logic

C1

C2

To Internal

Logic

(3)

(2)

RP

RF

Sleep

Quartz

Crystal

(2)

Sleep

RF

OSC2/CLKOUT

(1)

C2

RS

Ceramic

OSC2/CLKOUT

(1)

RS

Resonator

Note 1: A series resistor (RS) may be required for

Note 1:

2:

A series resistor (Rs) may be required for

quartz crystals with low drive level.

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator mode

selected (typically between 2 M to 10 M.

The value of RF varies with the Oscillator mode

selected (typically between 2 MΩ and 10 MΩ).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation.

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

9.2.1.3

Oscillator Start-up Timer (OST)

If the oscillator module is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) counts

1024 oscillations from OSC1. This occurs following a

Power-on Reset (POR), Brown-out Reset (BOR) or a

wake-up from Sleep. The OST ensures that the

oscillator circuit, using a quartz crystal resonator or

ceramic resonator, has started and is providing a stable

system clock to the oscillator module.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

• AN949, “Making Your Oscillator Work”

(DS00949)

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9.2.1.4

4x PLL

Note 1: Quartz

crystal

characteristics

vary

The oscillator module contains a PLL that can be used

with external clock sources to provide a system clock

source. The input frequency for the PLL must fall within

specifications. See the PLL Clock Timing

Specifications in Table 37-9.

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

The PLL may be enabled for use by one of two

methods:

1. Program the RSTOSC bits in the Configuration

Word 1 to enable the EXTOSC with 4x PLL

(RSTOSC<2:0> = '010').

3: For oscillator design assistance, reference

the following Microchip Application Notes:

• AN826, “Crystal Oscillator Basics and

Crystal Selection for rfPIC^®and PIC^®

Devices” (DS00826)

• AN849, “Basic PIC^®Oscillator Design”

2. Write the NOSC bits in the OSCCON1 register

to enable the EXTOSC with 4x PLL

(NOSC<2:0> = '010').

(DS00849)

• AN943, “Practical PIC^®Oscillator

Analysis and Design” (DS00943)

9.2.1.5

Secondary Oscillator

The secondary oscillator is a separate oscillator block

that can be used as an alternate system clock source.

The secondary oscillator is optimized for 32.768 kHz,

and can be used with an external crystal oscillator con-

nected to the SOSCI and SOSCO device pins, or an

external clock source connected to the SOSCIN pin.

Refer to Section 9.3 “Clock Switching” for more

information.

• AN949, “Making Your Oscillator Work”

(DS00949)

• TB097, “Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS” (DS91097)

• AN1288, “Design Practices for Low-

Power External Oscillators” (DS01288)

FIGURE 9-5:

QUARTZ CRYSTAL

OPERATION

(SECONDARY

OSCILLATOR)

PIC^®MCU

SOSCI

C1

C2

To Internal

Logic

32.768 kHz

Quartz

Crystal

SOSCO

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9.2.2

INTERNAL CLOCK SOURCES

9.2.2.1

HFINTOSC

The device may be configured to use an internal

oscillator block as the system clock by performing one

of the following actions:

The High-Frequency Internal Oscillator (HFINTOSC) is

a precision digitally-controlled internal clock source

that produces a stable clock up to 32 MHz. The

HFINTOSC can be enabled through one of the

following methods:

• Program the RSTOSC<2:0> bits in Configuration

Words to select the INTOSC clock source, which

will be used as the default system clock upon a

device Reset.

• Programming the RSTOSC<2:0> bits in

Configuration Word 1 to ‘110’ (1 MHz) or ‘001’

(32 MHz) to set the oscillator upon device Power-

up or Reset.

• Write the NOSC<2:0> bits in the OSCCON1

register to switch the system clock source to the

internal oscillator during run-time. See

Section 9.3 “Clock Switching” for more

information.

• Write to the NOSC<2:0> bits of the OSCCON1

register during run-time.

The HFINTOSC frequency can be selected by setting

the HFFRQ<2:0> bits of the OSCFRQ register. The

MFINTOSC is an internal clock source within the

HFINTOSC that provides two (500 kHz, 32 kHz) con-

stant clock outputs. These constant clock outputs are

available for selection to various peripherals, internally.

In INTOSC mode, the OSC1/CLKIN pin is available for

general purpose I/O. The OSC2/CLKOUT pin is

available for general purpose I/O or CLKOUT.

The function of the OSC2/CLKOUT pin is determined

by the CLKOUTEN bit in Configuration Words.

The NDIV<3:0> bits of the OSCCON1 register allow for

division of the HFINTOSC output from a range between

1:1 and 1:512.

The internal oscillator block has two independent

oscillators that can produce two internal system clock

sources.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates up

to 32 MHz.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is factory-calibrated and operates at

31 kHz.

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9.2.2.2

Internal Oscillator Frequency

Adjustment

9.3

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the New Oscillator Source (NOSC) and New Divider

selection request (NDIV) bits of the OSCCON1 register.

The following clock sources can be selected:

The HFINTOSC and LFINTOSC internal oscillators are

both factory-calibrated. The HFINTOSC oscillator can

be adjusted in software by writing to the OSCTUNE

register (Register 9-7). OSCTUNE does not affect the

LFINTOSC frequency.

• External Oscillator (EXTOSC)

The default value of the OSCTUNE register is 00h. The

value is a 6-bit two’s complement number. A value of

1Fh will provide an adjustment to the maximum

frequency. A value of 20h will provide an adjustment to

the minimum frequency.

• High-Frequency Internal Oscillator (HFINTOSC)

• Low-Frequency Internal Oscillator (LFINTOSC)

• Secondary Oscillator (SOSC)

• EXTOSC with 4x PLL

• HFINTOSC with 2x PLL

When the OSCTUNE register is modified, the current

HFINTOSC oscillator frequency will begin shifting to the

new frequency. Code execution continues during this

shift. There is no indication that the shift has occurred.

9.3.1

NEW OSCILLATOR SOURCE

(NOSC) AND NEW DIVIDER

SELECTION REQUEST (NDIV) BITS

The New Oscillator Source (NOSC) and New Divider

selection request (NDIV) bits of the OSCCON1 register

select the system clock source and the frequency that

are used for the CPU and peripherals.

9.2.2.3

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is

a factory-calibrated 31 kHz internal clock source.

When new values of NOSC and NDIV are written to

OSCCON1, the current oscillator selection will

continue to operate while waiting for the new clock

source to indicate that it is stable and ready. In some

cases, the newly requested source may already be in

use, and is ready immediately. In the case of a divider-

only change, the new and old sources are the same,

and will be immediately ready. The device may enter

Sleep while waiting for the switch as described in

Section 9.3.3 “Clock Switch and Sleep”.

The LFINTOSC is the clock source for the Power-up

Timer (PWRT), Watchdog Timer (WDT), and Fail-Safe

Clock Monitor (FSCM). The LFINTOSC can also be

used as the system clock, or as a clock or input source

to certain peripherals.

The LFINTOSC is selected as the clock source through

one of the following methods:

• Programming the RSTOSC<2:0> bits of Configu-

ration Word 1 to enable LFINTOSC

(RSTOSC<2:0> = '101')

When the new oscillator is ready, the New Oscillator is

Ready (NOSCR) bit of OSCCON3 and the Clock

Switch Interrupt Flag (CSWIF) bit of PIR1 become set

(CSWIF = 1). If Clock Switch Interrupts are enabled

(CSWIE = 1), an interrupt will be generated at that time.

The Oscillator Ready (ORDY) bit of OSCCON3 can

also be polled to determine when the oscillator is ready

in lieu of an interrupt.

• Write to the NOSC<2:0> bits of the OSCCON1

register (NOSC<2:0> = '101')

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Windowed Watchdog Timer (WWDT)

• Timer1

• Timer0

If the Clock Switch Hold (CSWHOLD) bit of OSCCON3

is clear, the oscillator switch will occur when the new

Oscillator’s READY bit (NOSCR) is set, and the

interrupt (if enabled) will be serviced at the new

oscillator setting.

• Timer2

• Fail-Safe Clock Monitor (FSCM)

• CLKR

• CLC

9.2.2.4

Oscillator Status and Manual Enable

If CSWHOLD is set, the oscillator switch is suspended,

while execution continues using the current (old) clock

source. When the NOSCR bit is set, software should:

The ‘ready’ status of each oscillator is displayed in the

OSCSTAT register (Register 9-4). The oscillators can

also be manually enabled through the OSCEN register

(Register 9-7). Manual enabling makes it possible to

verify the operation of the EXTOSC or SOSC crystal

oscillators. This can be achieved by enabling the

selected oscillator, then watching the corresponding

‘ready’ state of the oscillator in the OSCSTAT register.

• set CSWHOLD = 0so the switch can complete, or

• copy COSC into NOSC to abandon the switch.

If DOZE is in effect, the switch occurs on the next clock

cycle, whether or not the CPU is operating during that

cycle.

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Changing the clock post-divider without changing the

clock source (e.g., changing FOSC from 1 MHz to 2

MHz) is handled in the same manner as a clock source

change, as described previously. The clock source will

already be active, so the switch is relatively quick.

CSWHOLD must be clear (CSWHOLD = 0) for the

switch to complete.

9.3.3

CLOCK SWITCH AND SLEEP

If OSCCON1 is written with a new value and the device

is put to Sleep before the switch completes, the switch

will not take place and the device will enter Sleep

mode.

When the device wakes from Sleep and the

CSWHOLD bit is clear, the device will wake with the

‘new’ clock active, and the clock switch interrupt flag bit

(CSWIF) will be set.

The current COSC and CDIV are indicated in the

OSCCON2 register up to the moment when the switch

actually occurs, at which time OSCCON2 is updated

and ORDY is set. NOSCR is cleared by hardware to

indicate that the switch is complete.

When the device wakes from Sleep and the

CSWHOLD bit is set, the device will wake with the ‘old’

clock active and the new clock will be requested again.

9.3.2

PLL INPUT SWITCH

Switching between the PLL and any non-PLL source is

managed as described above. The input to the PLL is

established when NOSC selects the PLL, and main-

tained by the COSC setting.

When NOSC and COSC select the PLL with different

input sources, the system continues to run using the

COSC setting, and the new source is enabled per

NOSC. When the new oscillator is ready (and

CSWHOLD = 0), system operation is suspended while

the PLL input is switched and the PLL acquires lock.

Note:

If the PLL fails to lock, the FSCM will

trigger.

FIGURE 9-6:

CLOCK SWITCH (CSWHOLD = 0)

OSCCON1

WRITTEN

OSC #1

OSC #2

ORDY

NOTE 2

NOSCR

NOTE 1

CSWIF

USER

CLEAR

CSWHOLD

Note 1:CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.

2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.

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FIGURE 9-7:

CLOCK SWITCH (CSWHOLD = 1)

OSCCON1

WRITTEN

OSC #1

OSC #2

ORDY

NOSCR

NOTE 1

CSWIF

USER

CLEAR

CSWHOLD

Note 1:CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.

FIGURE 9-8:

CLOCK SWITCH ABANDONED

OSCCON1

WRITTEN

OSCCON1

WRITTEN

OSC #1

NOTE 2

ORDY

NOSCR

NOTE 1

CSWIF

CSWHOLD

Note 1:CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.

2: ORDY = 0if OSCCON1 does not match OSCCON2; a new switch will begin.

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9.4.2

FAIL-SAFE OPERATION

9.4

Fail-Safe Clock Monitor

When the external clock fails, the FSCM switches the

device clock to the HFINTOSC at 1 MHz clock

frequency and sets the bit flag OSFIF of the PIR1

register. Setting this flag will generate an interrupt if the

OSFIE bit of the PIE1 register is also set. The device

firmware can then take steps to mitigate the problems

that may arise from a failed clock. The system clock will

continue to be sourced from the internal clock source

until the device firmware successfully restarts the

external oscillator and switches back to external

operation, by writing to the NOSC and NDIV bits of the

OSCCON1 register.

The Fail-Safe Clock Monitor (FSCM) allows the device

to continue operating should the external oscillator fail.

The FSCM is enabled by setting the FCMEN bit in

Configuration Word 1. The FSCM is applicable to all

external Oscillator modes (LP, XT, HS, ECL, ECM,

ECH and Secondary Oscillator).

FIGURE 9-9:

FSCM BLOCK DIAGRAM

Clock Monitor

Latch

External

Clock

S

Q

9.4.3

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset,

executing a SLEEP instruction or changing the NOSC

and NDIV bits of the OSCCON1 register. When

switching to the external oscillator, or external oscillator

and PLL, the OST is restarted. While the OST is

running, the device continues to operate from the

INTOSC selected in OSCCON1. When the OST times

out, the Fail-Safe condition is cleared after successfully

switching to the external clock source. The OSFIF bit

should be cleared prior to switching to the external

clock source. If the Fail-Safe condition still exists, the

OSFIF flag will again become set by hardware.

LFINTOSC

Oscillator

÷ 64

R

Q

31 kHz

(~32 s)

488 Hz

(~2 ms)

Sample Clock

Clock

Failure

Detected

9.4.1

FAIL-SAFE DETECTION

The FSCM module detects a failed oscillator by

comparing the external oscillator to the FSCM sample

clock. The sample clock is generated by dividing the

LFINTOSC by 64. See Figure 9-9. Inside the fail

detector block is a latch. The external clock sets the

latch on each falling edge of the external clock. The

sample clock clears the latch on each rising edge of the

sample clock. A failure is detected when an entire half-

cycle of the sample clock elapses before the external

clock goes low.

9.4.4

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect an oscillator failure

after the Oscillator Start-up Timer (OST) has expired.

The OST is used after waking up from Sleep and after

any type of Reset. The OST is not used with the EC

Clock modes so that the FSCM will be active as soon

as the Reset or wake-up has completed. Therefore, the

device will always be executing code while the OST is

operating.

FIGURE 9-10:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

Clock Monitor Output

(Q)

Failure

Detected

OSCFIF

Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in

this example have been chosen for clarity.

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9.5

Register Definitions: Oscillator Control

REGISTER 9-1:

OSCCON1: OSCILLATOR CONTROL REGISTER1

U-0

—

R/W-f/f⁽¹⁾

NOSC<2:0>^(2,3)

R/W-f/f⁽¹⁾

R/W-q/q

bit 0

NDIV<3:0>^(2,3,4)

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

f = determined by fuse setting

bit 7

Unimplemented: Read as ‘0’

bit 6-4

NOSC<2:0>: New Oscillator Source Request bits

The setting requests a source oscillator and PLL combination per Table 9-1.

POR value = RSTOSC (Register 5-1).

bit 3-0

NDIV<3:0>: New Divider Selection Request bits

The setting determines the new postscaler division ratio per Table 9-1.

Note 1: The default value (f/f) is set equal to the RSTOSC Configuration bits.

2: If NOSC is written with a reserved value (Table 9-1), the operation is ignored and neither NOSC nor NDIV

is written.

3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.

4: When NOSC = 110(HFINTOSC 1 MHz), the NDIV bits will default to ‘0010’ upon Reset; for all other

NOSC settings the NDIV bits will default to ‘0000’ upon Reset.

REGISTER 9-2:

OSCCON2: OSCILLATOR CONTROL REGISTER 2

U-0

—

R-n/n⁽²⁾

COSC<2:0>

CDIV<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

Unimplemented: Read as ‘0’

bit 6-4

COSC<2:0>: Current Oscillator Source Select bits (read-only)

Indicates the current source oscillator and PLL combination per Table 9-1.

bit 3-0

CDIV<3:0>: Current Divider Select bits (read-only)

Indicates the current postscaler division ratio per Table 9-1.

Note 1:The POR value is the value present when user code execution begins.

2: The Reset value (n/n) is the same as the NOSC/NDIV bits.

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TABLE 9-1:

NOSC/COSC BIT SETTINGS

TABLE 9-2:

NDIV/CDIV BIT SETTINGS

NOSC<2:0>/

COSC<2:0>

NDIV<3:0>/

CDIV<3:0>

Clock Source

Clock divider

(1)

111

110

101

100

011

010

001

000

EXTOSC

1111-1010

1001

Reserved

(2)

HFINTOSC (1 MHz)

512

256

128

64

32

16

8

LFINTOSC

SOSC

1000

0111

Reserved

0110

(1)

EXTOSC with 4x PLL

0101

(1)

HFINTOSC with 2x PLL (32 MHz)

0100

HFINTOSC (32 MHz)

0011

Note 1: EXTOSC configured by the FEXTOSC bits of

Configuration Word 1 (Register 5-1).

2: HFINTOSC settings are configured with the

HFFRQ bits of the OSCFRQ register

(Register 9-6).

0010

4

0001

2

0000

1

REGISTER 9-3:

OSCCON3: OSCILLATOR CONTROL REGISTER 3

R/W/HC-0/0

R/W-0/0

SOSCPWR

U-0

—

R-0/0

U-0

—

U-0

—

U-0

—

CSWHOLD

bit 7

ORDY

NOSCR

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CSWHOLD: Clock Switch Hold bit

1= Clock switch will hold (with interrupt) when the oscillator selected by NOSC is ready

0= Clock switch may proceed when the oscillator selected by NOSC is ready; if this bit

is clear at the time that NOSCR becomes ‘1’, the switch will occur

bit 6

SOSCPWR: Secondary Oscillator Power Mode Select bit

1= Secondary oscillator operating in High-power mode

0= Secondary oscillator operating in Low-power mode

bit 5

bit 4

Unimplemented: Read as ‘0’.

ORDY: Oscillator Ready bit (read-only)

1= OSCCON1 = OSCCON2; the current system clock is the clock specified by NOSC

0= A clock switch is in progress

bit 3

NOSCR: New Oscillator is Ready bit (read-only)

1= A clock switch is in progress and the oscillator selected by NOSC indicates a “ready” condition

0= A clock switch is not in progress, or the NOSC-selected oscillator is not yet ready

bit 2-0

Unimplemented: Read as ‘0’

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REGISTER 9-4:

OSCSTAT: OSCILLATOR STATUS REGISTER 1

R-q/q

EXTOR

bit 7

R-q/q

LFOR

R-q/q

SOR

R-q/q

U-0

—

R-q/q

PLLR

HFOR

MFOR

ADOR

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Reset value is determined by hardware

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EXTOR: EXTOSC (external) Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

HFOR: HFINTOSC Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

MFOR: MFINTOSC Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

LFOR: LFINTOSC Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

SOR: Secondary (Timer1) Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

ADOR: CRC Oscillator Ready bit

1= The oscillator is ready to be used

0= The oscillator is not enabled, or is not yet ready to be used.

bit 1

bit 0

Unimplemented: Read as ‘0’

PLLR: PLL is Ready bit

1= The PLL is ready to be used

0= The PLL is not enabled, the required input source is not ready, or the PLL is not locked.

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REGISTER 9-5:

R/W-0/0

OSCEN: OSCILLATOR MANUAL ENABLE REGISTER

R/W-0/0

HFOEN

R/W-0/0

MFOEN

R/W-0/0

LFOEN

R/W-0/0

ADOEN

U-0

—

U-0

—

EXTOEN

bit 7

SOSCEN

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1-0

EXTOEN: External Oscillator Manual Request Enable bit⁽¹⁾

1= EXTOSC is explicitly enabled, operating as specified by FEXTOSC

0= EXTOSC could be enabled by some modules

HFOEN: HFINTOSC Oscillator Manual Request Enable bit

1= HFINTOSC is explicitly enabled, operating as specified by OSCFRQ

0= HFINTOSC could be enabled by another module

MFOEN: MFINTOSC Oscillator Manual Request Enable bit

1= MFINTOSC is explicitly enabled

0= MFINTOSC could be enabled by another module

LFOEN: LFINTOSC (31 kHz) Oscillator Manual Request Enable bit

1= LFINTOSC is explicitly enabled

0= LFINTOSC could be enabled by another module

SOSCEN: Secondary (Timer1) Oscillator Manual Request bit

1= Secondary oscillator is explicitly enabled, operating as specified by SOSCPWR

0= Secondary oscillator could be enabled by another module

ADOEN: FRC Oscillator Manual Request Enable bit

1= FRC is explicitly enabled

0= FRC could be enabled by another module

Unimplemented: Read as ‘0’

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REGISTER 9-6:

OSCFRQ: HFINTOSC FREQUENCY SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-q/q

HFFRQ<2:0>⁽¹⁾

R/W-q/q

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

HFFRQ<2:0>: HFINTOSC Frequency Selection bits

Nominal Freq (MHz):

111= Reserved

110= 32

101= 16

100= 12

011= 8

010= 4

001= 2

000= 1

Note 1: When RSTOSC=110(HFINTOSC 1 MHz), the HFFRQ bits will default to ‘010’ upon Reset; when RSTOSC = 001

(HFINTOSC 32 MHz), the HFFRQ bits will default to ‘101’ upon Reset.

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REGISTER 9-7:

OSCTUNE: HFINTOSC TUNING REGISTER

U-0

—

U-0

—

R/W-1/1

R/W-0/0

HFTUN<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’.

HFTUN<5:0>: HFINTOSC Frequency Tuning bits

01 1111 = Maximum frequency

01 1110 =

•••

00 0001 =

00 0000 = Center frequency. Oscillator module is running at the calibrated frequency (default value).

11 1111 =

•••

10 0001 =

10 0000 = Minimum frequency.

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TABLE 9-3:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON1

OSCCON2

OSCCON3

OSCFRQ

OSCSTAT

OSCTUNE

OSCEN

—

NOSC<2:0>

COSC<2:0>

—

NDIV<3:0>

110

111

114

112

115

113

CDIV<3:0>

—

CWSHOLD SOSCPWR

ORDY

—

NOSCR

—

PLLR

—

HFFRQ<2:0>

—

EXTOR

HFOR

MFOR

LFOR

SOR

ADOR

—

HFTUN<5:0>

EXTOEN

HFOEN

MFOEN

LFOEN

SOSCEN

ADOEN

—

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

TABLE 9-4:

SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Register

on Page

Name

Bits Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

13:8

7:0

—

FCMEN

—

CSWEN

—

CLKOUTEN

CONFIG1

76

RSTOSC<2:0>

FEXTOSC<2:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.

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10.0 INTERRUPTS

The interrupt feature allows certain events to preempt

normal program flow. Firmware is used to determine

the source of the interrupt and act accordingly. Some

interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce interrupts. Refer to the

corresponding chapters for details.

A block diagram of the interrupt logic is shown in

Figure 10-1.

FIGURE 10-1:

INTERRUPT LOGIC

Rev. 10-000010C

10/12/2016

TMR0IF

TMR0IE

Wake-up

(If in Sleep mode)

INTF

INTE

Peripheral Interrupts

(ADIF) PIR1 <0>

(ADIE) PIE1 <0>

IOCIF

IOCIE

Interrupt

to CPU

PEIE

GIE

PIRn

PIEn

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10.1 Operation

10.2 Interrupt Latency

Interrupts are disabled upon any device Reset. They

are enabled by setting the following bits:

Interrupt latency is defined as the time from when the

interrupt event occurs to the time code execution at the

interrupt vector begins. The interrupt is sampled during

Q1 of the instruction cycle. The actual interrupt latency

then depends on the instruction that is executing at the

time the interrupt is detected. See Figure 10-2 and

Figure 10-3 for more details.

• GIE bit of the INTCON register

• Interrupt Enable bit(s) of the PIEx[y] registers for

the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIEx registers)

The PIR1, PIR2, PIR3, PIR4, PIR5, PIR6, and PIR7

registers record individual interrupts via interrupt flag

bits. Interrupt flag bits will be set, regardless of the

status of the GIE, PEIE and individual interrupt enable

bits.

The following events happen when an interrupt event

occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the

stack

• Critical registers are automatically saved to the

shadow registers (See “Section 10.5 “Auto-

matic Context Saving”)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR)

should determine the source of the interrupt by polling

the interrupt flag bits. The interrupt flag bits must be

cleared before exiting the ISR to avoid repeated

interrupts. Because the GIE bit is cleared, any interrupt

that occurs while executing the ISR will be recorded

through its interrupt flag, but will not cause the

processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the

previous address from the stack, restoring the saved

context from the shadow registers and setting the GIE

bit.

For additional information on a specific interrupts

operation, refer to its peripheral chapter.

Note 1: Individual interrupt flag bits are set,

regardless of the state of any other

enable bits.

2: All interrupts will be ignored while the GIE

bit is cleared. Any interrupt occurring

while the GIE bit is clear will be serviced

when the GIE bit is set again.

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FIGURE 10-2:

INTERRUPT LATENCY

Rev. 10-000269E

8/31/2016

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

INT

Valid Interrupt

window⁽¹⁾

PC

1 Cycle Instruction at PC

PC = 0x0004

PC - 1

PC - 2

PC + 1

PC = 0x0005 PC = 0x0006

PC = 0x0004 PC = 0x0005

Fetch

PC - 1

PC

123

Execute

Indeterminate

Latency⁽²⁾

Latency

Note 1: An interrupt may occur at any time during the interrupt window.

2: Since an interrupt may occur any time during the interrupt window, the actual latency can vary.

FIGURE 10-3:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(4)

INT pin

INTF

(1)

(2)

(5)

Interrupt Latency

GIE

INSTRUCTION FLOW

PC

PC + 1

—

0004h

0005h

PC

Inst (PC)

PC + 1

Instruction

Fetched

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Forced NOP

Inst (PC)

Inst (PC – 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: For minimum width of INT pulse, refer to AC specifications in Section 37.0 “Electrical Specifications”.

4: INTF may be set any time during the Q4-Q1 cycles.

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10.3 Interrupts During Sleep

Interrupts can be used to wake from Sleep. To wake

from Sleep, the peripheral must be able to operate

without the system clock. The interrupt source must

have the appropriate Interrupt Enable bit(s) set prior to

entering Sleep.

On waking from Sleep, if the GIE bit is also set, the

processor will branch to the interrupt vector. Otherwise,

the processor will continue executing instructions after

the SLEEPinstruction. The instruction directly after the

SLEEP instruction will always be executed before

branching to the ISR. Refer to Section 11.0 “Power-

Saving Operation Modes” for more details.

10.4 INT Pin

The INT pin can be used to generate an asynchronous

edge-triggered interrupt. Refer to Figure 10-3. This

interrupt is enabled by setting the INTE bit of the PIE0

register. The INTEDG bit of the INTCON register

determines on which edge the interrupt will occur. When

the INTEDG bit is set, the rising edge will cause the

interrupt. When the INTEDG bit is clear, the falling edge

will cause the interrupt. The INTF bit of the PIR0 register

will be set when a valid edge appears on the INT pin. If

the GIE and INTE bits are also set, the processor will

redirect program execution to the interrupt vector.

10.5 Automatic Context Saving

Upon entering an interrupt, the return PC address is

saved on the stack. Additionally, the following registers

are automatically saved in the shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these

registers are automatically restored. Any modifications

to these registers during the ISR will be lost. If

modifications to any of these registers are desired, the

corresponding shadow register should be modified and

the value will be restored when exiting the ISR. The

shadow registers are available in Bank 31 and are

readable and writable. Depending on the user’s

application, other registers may also need to be saved.

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10.6 Register Definitions: Interrupt Control

REGISTER 10-1: INTCON: INTERRUPT CONTROL REGISTER

R/W-0/0

GIE

R/W-0/0

PEIE

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1/1

INTEDG

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

GIE: Global Interrupt Enable bit

1= Enables all active interrupts

0= Disables all interrupts

PEIE: Peripheral Interrupt Enable bit

1= Enables all active peripheral interrupts

0= Disables all peripheral interrupts

bit 5-1

bit 0

Unimplemented: Read as ‘0’

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of INT pin

0= Interrupt on falling edge of INT pin

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-2: PIE0: PERIPHERAL INTERRUPT ENABLE REGISTER 0

U-0

—

U-0

—

R/W-0/0

TMR0IE

R/W-0/0

IOCIE

U-0

—

U-0

—

U-0

—

R/W-0/0

INTE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-6

bit 5

Unimplemented: Read as ‘0’

TMR0IE: Timer0 Overflow Interrupt Enable bit

1= Enables the Timer0 interrupt

0= Disables the Timer0 interrupt

bit 4

IOCIE: Interrupt-on-Change Interrupt Enable bit

1= Enables the IOC change interrupt

0= Disables the IOC change interrupt

bit 3-1

bit 0

Unimplemented: Read as ‘0’

INTE: INT External Interrupt Flag bit⁽¹⁾

1= Enables the INT external interrupt

0= Disables the INT external interrupt

Note 1: The External Interrupt INT pin is selected by INTPPS (Register 15-1).

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by PIE1-PIE7. Interrupt sources

controlled by the PIE0 register do not

require PEIE to be set in order to allow

interrupt vectoring (when GIE is set).

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REGISTER 10-3: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

OSFIE

R/W-0/0

CSWIE

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

—

R/W-0/0

ADIE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the Oscillator Fail Interrupt

0= Disables the Oscillator Fail Interrupt

CSWIE: Clock Switch Complete Interrupt Enable bit

1= The clock switch module interrupt is enabled

0= The clock switch module interrupt is disabled

bit 5-1

bit 0

Unimplemented: Read as ‘0’

ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit

1= Enables the ADC interrupt

0= Disables the ADC interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7

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REGISTER 10-4: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

U-0

—

R/W-0/0

ZCDIE

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

C2IE

R/W-0/0

C1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

bit 6

Unimplemented: Read as ‘0’

ZCDIE: Zero-Cross Detection (ZCD) Interrupt Enable bit

1= Enables the ZCD interrupt

0= Disables the ZCD interrupt

bit 5-2

bit 1

Unimplemented: Read as ‘0’

C2IE: Comparator C2 Interrupt Enable bit

1= Enables the Comparator C2 interrupt

0= Disables the Comparator C2 interrupt

bit 0

C1IE: Comparator C1 Interrupt Enable bit

1= Enables the Comparator C1 interrupt

0= Disables the Comparator C1 interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7.

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REGISTER 10-5: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3

R/W-0/0

RC2IE

R/W-0/0

TX2IE

R/W-0/0

RC1IE

R/W-0/0

TX1IE

R/W-0/0

BCL2IE

R/W-0/0

SSP2IE

R/W-0/0

BCL1IE

R/W-0/0

SSP1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RC2IE: USART2 Receive Interrupt Enable bit

1= Enables the USART2 receive interrupt

0= Enables the USART2 receive interrupt

TX2IE: USART2 Transmit Interrupt Enable bit

1= Enables the USART2 transmit interrupt

0= Disables the USART2 transmit interrupt

RC1IE: USART1 Receive Interrupt Enable bit

1= Enables the USART1 receive interrupt

0= Enables the USART1 receive interrupt

TX1IE: USART1 Transmit Interrupt Enable bit

1= Enables the USART1 transmit interrupt

0= Disables the USART1 transmit interrupt

BCL2IE: MSSP2 Bus Collision Interrupt Enable bit

1= MSSP bus Collision interrupt enabled

0= MSSP bus Collision interrupt disabled

SSP2IE: MSSP2 Interrupt Enable bit

1= Enables the MSSP2 Interrupt

0= Disables the MSSP Interrupt

BCL1IE: MSSP1 Bus Collision Interrupt Enable bit

1= MSSP1 bus collision interrupt enabled

0= MSSP1 bus collision interrupt disabled

SSP1IE: MSSP1 Interrupt Enable bit

1= Enables the MSSP1 interrupt

0= Disables the MSSP1 interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by PIE1-PIE7.

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REGISTER 10-6: PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

TMR2IE

R/W-0/0

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

bit 0

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Enables the Timer1 overflow interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7.

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REGISTER 10-7: PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5

R/W-0/0

CLC4IE

R/W-0/0

CLC3IE

R/W-0/0

CLC2IE

R/W-0/0

CLC1IE

U-0

—

U-0

—

U-0

—

R/W-0/0

TMR1GIE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7

bit 6

bit 5

bit 4

CLC4IE: CLC4 Interrupt Enable bit

1= CLC4 interrupt enabled

0= CLC4 interrupt disabled

CLC3IE: CLC3 Interrupt Enable bit

1= CLC3 interrupt enabled

0= CLC3 interrupt disabled

CLC2IE: CLC2 Interrupt Enable bit

1= CLC2 interrupt enabled

0= CLC2 interrupt disabled

CLC1IE: CLC1 Interrupt Enable bit

1= CLC1 interrupt enabled

0= CLC1 interrupt disabled

bit 3-1

bit 0

Unimplemented: Read as ‘0’

TMR1GIE: Timer1 Gate Interrupt Enable bit

1= Enables the Timer1 gate acquisition interrupt

0= Disables the Timer1 gate acquisition interrupt

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7.

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REGISTER 10-8: PIE6: PERIPHERAL INTERRUPT ENABLE REGISTER 6

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CCP2IE

R/W-0/0

CCP1IE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-2

bit 1

Unimplemented: Read as ‘0’.

CCP2IE: CCP2 Interrupt Enable bit

1= CCP2 interrupt is enabled

0= CCP2 interrupt is disabled

bit 0

CCP1IE: CCP1 Interrupt Enable bit

1= CCP1 interrupt is enabled

0= CCP1 interrupt is disabled

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7.

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REGISTER 10-9: PIE7: PERIPHERAL INTERRUPT ENABLE REGISTER 7

U-0

—

U-0

—

R/W-0/0

NVMIE

R/W-0/0

NCO1IE

U-0

—

U-0

—

U-0

—

R/W-0/0

CWG1IE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-6

bit 5

Unimplemented: Read as ‘0’.

NVMIE: NVM Interrupt Enable bit

1= NVM task complete interrupt enabled

0= NVM interrupt not enabled

bit 4

NCO1IE: NCO Interrupt Enable bit

1= NCO rollover interrupt enabled

0= NCO rollover interrupt disabled

bit 3-1

bit 0

Unimplemented: Read as ‘0’.

CWG1IE: CWG1 Interrupt Enable bit

1= CWG1 interrupt is enabled

0= CWG1 interrupt disabled

Note:

Bit PEIE of the INTCON register must be

set to enable any peripheral interrupt

controlled by registers PIE1-PIE7.

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REGISTER 10-10: PIR0: PERIPHERAL INTERRUPT STATUS REGISTER 0

U-0

—

U-0

—

R/W/HS-0/0

TMR0IF

R-0

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

IOCIF

INTF⁽¹⁾

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS= Hardware Set

bit 7-6

bit 5

Unimplemented: Read as ‘0’

TMR0IF: Timer0 Overflow Interrupt Flag bit

1= Timer0 register has overflowed (must be cleared in software)

0= Timer0 register did not overflow

bit 4

IOCIF: Interrupt-on-Change Interrupt Flag bit (read-only)⁽²⁾

1= One or more of the IOCAF-IOCEF register bits are currently set, indicating an enabled edge was

detected by the IOC module.

0= None of the IOCAF-IOCEF register bits are currently set

bit 3-1

bit 0

Unimplemented: Read as ‘0’

INTF: INT External Interrupt Flag bit⁽¹⁾

1= The INT external interrupt occurred (must be cleared in software)

0= The INT external interrupt did not occur

Note 1: The External Interrupt INT pin is selected by INTPPS (Register 15-1).

2: The IOCIF bit is the logical OR of all the IOCAF-IOCEF flags. Therefore, to clear the IOCIF flag,

application firmware must clear all of the lower level IOCAF-IOCEF register bits.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state

of its corresponding enable bit or the

Global Enable bit, GIE, of the INTCON

register. User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-11: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W/HS-0/0 R/W/HS-0/0

OSFIF CSWIF

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

ADIF

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7

bit 6

OSFIF: Oscillator Fail-Safe Interrupt Flag bit

1= Oscillator fail-safe interrupt has occurred (must be cleared in software)

0= No oscillator fail-safe interrupt

CSWIF: Clock Switch Complete Interrupt Flag bit

1= The clock switch module indicates an interrupt condition and is ready to complete the clock switch

operation (must be cleared in software)

0= The clock switch does not indicate an interrupt condition

bit 5-1

bit 0

Unimplemented: Read as ‘0’

ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit

1= An A/D conversion or complex operation has completed (must be cleared in software)

0= An A/D conversion or complex operation is not complete

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-12: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

U-0

—

R/W/HS-0/0

ZCDIF

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0 R/W/HS-0/0

C2IF C1IF

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7

bit 6

Unimplemented: Read as ‘0’

ZCDIF: Zero-Cross Detect (ZCD1) Interrupt Flag bit

1= An enabled rising and/or falling ZCD1 event has been detected (must be cleared in software)

0= No ZCD1 event has occurred

bit 5-2

bit 1

Unimplemented: Read as ‘0’

C2IF: Comparator C2 Interrupt Flag bit

1= Comparator 2 interrupt asserted (must be cleared in software)

0= Comparator 2 interrupt not asserted

bit 0

C1IF: Comparator C1 Interrupt Flag bit

1= Comparator 1 interrupt asserted (must be cleared in software)

0= Comparator 1 interrupt not asserted

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-13: PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3

R/HS-0/0

RC2IF

R/HS-0/0

TX2IF

R/HS-0/0

RC1IF

R/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

TX1IF BCL2IF SSP2IF BCL1IF SSP1IF

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware clearable

bit 7

bit 6

RC2IF: EUSART2 Receive Interrupt Flag bit⁽¹⁾

1= The EUSART2 receive buffer is not empty (contains at least one byte)

0= The EUSART2 receive buffer is empty

TX2IF: EUSART2 Transmit Interrupt Flag bit⁽²⁾

1= The EUSART2 transmit buffer contains at least one unoccupied space

0= The EUSART2 transmit buffer is currently full. The application firmware should not write to

TXxREG

bit 5

bit 4

RC1IF: EUSART1 Receive Interrupt Flag bit ⁽¹⁾

1= The EUSART1 receive buffer is not empty (contains at least one byte)

0= The EUSART1 receive buffer is empty

TX1IF: EUSART1 Transmit Interrupt Flag bit⁽²⁾

1= The EUSART1 transmit buffer contains at least one unoccupied space

0= The EUSART1 transmit buffer is currently full. The application firmware should not write to

TXxREG.

bit 3

bit 2

bit 1

bit 0

BCL2IF: MSSP2 Bus Collision Interrupt Flag bit

1= A bus collision was detected (must be cleared in software)

0= No bus collision was detected

SSP2IF: MSSP2 Interrupt Flag bit

1= The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0= Waiting for the Transmission/Reception/Bus Condition in progress

BCL1IF: MSSP1 Bus Collision Interrupt Flag bit

1= A bus collision was detected (must be cleared in software)

0= No bus collision was detected

SSP1IF: MSSP1 Interrupt Flag bit

1= The Transmission/Reception/Bus Condition is complete (must be cleared in software)

0= Waiting for the Transmission/Reception/Bus Condition in progress

Note 1: The RCxIF flag is a read-only bit. To clear the RCxIF flag, the firmware must read from RCxREG enough

times to remove all bytes from the receive buffer.

2: The TXxIF flag is a read-only bit, indicating if there is room in the transmit buffer. To clear the TX1IF flag,

the firmware must write enough data to TXxREG to completely fill all available bytes in the buffer. The

TXxIF flag does not indicate transmit completion (use TRMT for this purpose instead).

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-14: PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0 R/W/HS-0/0

TMR2IF TMR1IF

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

TRM2IF: Timer2 Interrupt Flag bit

1 = The TMR2 postscaler overflowed, or in 1:1 mode, a TMR2 to PR2 match occurred (must be

cleared in software)

0= No TMR2 event has occurred

bit 0

TRM1IF: Timer1 Overflow Interrupt Flag bit

1= Timer1 overflow occurred (must be cleared in software)

0= No Timer1 overflow occurred

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-15: PIR5: PERIPHERAL INTERRUPT REQUEST REGISTER 5

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

U-0

—

R/W/HS-0/0

CLC4IF

bit 7

CLC3IF

CLC2IF

CLC1IF

—

TMR1GIF

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7

bit 6

bit 5

bit 4

CLC4IF: CLC4 Interrupt Flag bit

1= A CLC4OUT interrupt condition has occurred (must be cleared in software)

0= No CLC4 interrupt event has occurred

CLC3IF: CLC3 Interrupt Flag bit

1= A CLC3OUT interrupt condition has occurred (must be cleared in software)

0= No CLC3 interrupt event has occurred

CLC2IF: CLC2 Interrupt Flag bit

1= A CLC2OUT interrupt condition has occurred (must be cleared in software)

0= No CLC2 interrupt event has occurred

CLC1IF: CLC1 Interrupt Flag bit

1= A CLC1OUT interrupt condition has occurred (must be cleared in software)

0= No CLC1 interrupt event has occurred

bit 3-1

bit 0

Unimplemented: Read as ‘0’

TMR1GIF: Timer1 Gate Interrupt Flag bit

1= The Timer1 Gate has gone inactive (the acquisition is complete)

0= The Timer1 Gate has not gone inactive

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-16: PIR6: PERIPHERAL INTERRUPT REQUEST REGISTER 6

U-0

R/W/HS-0/0

CCP2IF

R/W/HS-0/0

CCP1IF

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

CCP2IF: CCP2 Interrupt Flag bit

CCPM Mode

Value

Capture

Compare

PWM

Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

1

0

Capture did not occur

Compare match did not occur

Output trailing edge did not occur

bit 0

CCP1IF: CCP1 Interrupt Flag bit

CCPM Mode

Compare

Value

Capture

PWM

Capture occurred

(must be cleared in software)

Compare match occurred

(must be cleared in software)

Output trailing edge occurred

(must be cleared in software)

1

0

Capture did not occur

Compare match did not occur

Output trailing edge did not occur

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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REGISTER 10-17: PIR7: PERIPHERAL INTERRUPT REQUEST REGISTER 7

U-0

—

U-0

—

R/W/HS-0/0 R/W/HS-0/0

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

NVMIF

NCO1IF

CWG1IF

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS = Hardware set

bit 7-6

bit 5

Unimplemented: Read as ‘0’

NVMIF: Nonvolatile Memory (NVM) Interrupt Flag bit

1= The requested NVM operation has completed

0= NVM interrupt not asserted

bit 4

NCO1IF: Numerically Controlled Oscillator (NCO) Interrupt Flag bit

1= The NCO has rolled over

0= No NCO interrupt event has occurred

bit 3-1

bit 0

Unimplemented: Read as ‘0’

CWG1IF: CWG1 Interrupt Flag bit

1= CWG1 has gone into shutdown

0= CWG1 is operating normally, or interrupt cleared

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the

appropriate interrupt flag bits are clear

prior to enabling an interrupt.

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TABLE 10-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE0

PIE1

PIE2

PIE3

PIE4

PIE5

PIE6

PIE7

PIR0

PIR1

PIR2

PIR3

PIR4

PIR5

PIR6

PIR7

Legend:

GIE

—

PEIE

—

TMR0IE

—

IOCIE

—

INTEDG

INTE

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

OSFIE

CSWIE

ADIE

—

RC2IE

—

ZCDIE

TX2IE

—

RC1IE

—

TX1IE

—

BCL2IE

—

SSP2IE

—

C2IE

C1IE

BCL1IE

TMR2IE

—

SSP1IE

TMR1IE

TMR1GIE

CCP1IE

CWG1IE

INTF

CLC4IE

—

CLC3IE

—

CLC2IE

—

CLC1IE

—

CCP2IE

—

NVMIE

TMR0IF

NCO1IE

IOCIF

—

OSFIF

—

CSWIF

ZCDIF

TX2IF

—

C2IF

ADIF

C1IF

RC2IF

—

RC1IF

—

TX1IF

—

BCL2IF

—

SSP2IF

—

BCL1IF

TMR2IF

—

SSP1IF

TMR1IF

TMR1GIF

CCP1IF

CWG1IF

CLC4IF

—

CLC3IF

—

CLC2IF

—

CLC1IF

—

CCP2IF

—

NVMIF

NCO1IF

—

— = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts.

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affected. The reduced execution saves power by

eliminating unnecessary operations within the CPU

and memory.

11.0 POWER-SAVING OPERATION

MODES

The purpose of the Power-Down modes is to reduce

power consumption. There are three Power-Down

modes: DOZE mode, IDLE mode, and SLEEP mode.

When the Doze Enable (DOZEN) bit is set (DOZEN =

1), the CPU executes only one instruction cycle out of

every N cycles as defined by the DOZE<2:0> bits of the

CPUDOZE register. For example, if DOZE<2:0> = 100,

the instruction cycle ratio is 1:32. The CPU and

memory execute for one instruction cycle and then lay

idle for 31 instruction cycles. During the unused cycles,

the peripherals continue to operate at the system clock

speed.

11.1 DOZE Mode

DOZE mode saves power by reducing CPU execution

and program memory access, without affecting

peripheral operation. DOZE mode differs from Sleep

mode because the system oscillators continue to

operate, while only the CPU and program memory are

FIGURE 11-1:

DOZE MODE OPERATION EXAMPLE

System

Clock

1

2

/ŶƐƚƌƵĐƚŝŽŶ

WĞƌŝŽĚ

3

4

1

2

3

4

1

2

3

4

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4

CPU Clock

PFM Op’s

Fetch

Exec

Fetch

Exec

Push

0004h

NOP

Fetch

Exec

Fetch

Exec

Exec^(1,2)

Exec

CPU Op’s

Interrupt

Here

(ROI = 1)

Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.

2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.

11.1.1

DOZE OPERATION

The Doze operation is illustrated in Figure 11-1. For

example, if ROI = 1 and DOZE<2:0> = '001', the

instruction cycle ratio is 1:4. The CPU and memory

operate for one instruction cycle and stay idle for the

next three instruction cycles.

As with normal operation, the program memory fetches

for the next instruction cycle. The system clock to the

peripherals continue throughout.

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11.1.2

INTERRUPTS DURING DOZE

If an interrupt occurs during DOZE, system behavior

can be configured using the Recover-On-Interrupt

(ROI) bit and the Doze-On-Exit (DOE) bit. Refer to

Table 11-1 for details about system behavior in all

cases for a transition from Main to ISR back to Main.

TABLE 11-1: INTERRUPTS DURING DOZE

Code Flow

DOZEN

ROI

Main

ISR⁽¹⁾

Return to Main

0

1

0

1

0

1

Normal

operation

Normal operation and

DOZEN (in hardware) DOZEN = 0

(unchanged)

DOE =

Normal

operation

Normal operation and

DOZEN (in hardware) DOZEN = 0

(unchanged)

DOE =

If DOE = 1when If DOE = 0when

return from inter- return from inter-

rupt:

DOZE operation

Normal operation

DOZE

operation

DOZE operation and

DOZEN (in hardware) DOZEN = 1

(unchanged)

DOE =

and DOZEN = 1 and DOZEN = 0

(in hardware) (in hardware)

DOZE

Normal operation and

DOE =

operation

DOZEN (in hardware) DOZEN = 0

(unchanged)

Note 1: User software can change the DOE bit in the ISR.

Refer to individual chapters for more details on

peripheral operation during Sleep.

11.2 Sleep Mode

Sleep mode is entered by executing the SLEEP

instruction, while the Idle Enable (IDLEN) bit of the

CPUDOZE register is clear (IDLEN = 0). If the SLEEP

instruction is executed while the IDLEN bit is set

(IDLEN = 1), the CPU will enter the IDLE mode

(Section 11.2.3 “Low-Power Sleep Mode”).

To minimize current consumption, the following

conditions should be considered:

- I/O pins should not be floating

- External circuitry sinking current from I/O pins

- Internal circuitry sourcing current from I/O

pins

- Current draw from pins with internal weak

pull-ups

Upon entering Sleep mode, the following conditions

exist:

1. WDT will be cleared but keeps running if

enabled for operation during Sleep

- Modules using any oscillator

I/O pins that are high-impedance inputs should be

pulled to VDD or VSS externally to avoid switching

currents caused by floating inputs.

2. The PD bit of the STATUS register is cleared

3. The TO bit of the STATUS register is set

4. CPU Clock and System Clock

Any module with a clock source that is not FOSC can be

enabled. Examples of internal circuitry that might be

sourcing current include modules such as the DAC and

FVR modules. See Section 21.0 “5-Bit Digital-to-

Analog Converter (DAC1) Module”, Section 18.0

“Fixed Voltage Reference (FVR)” for more informa-

tion on these modules.

5. 31 kHz LFINTOSC, HFINTOSC and SOSC are

unaffected and peripherals using them may

continue operation in Sleep.

6. ADC is unaffected if the dedicated FRC

oscillator is selected the conversion will be left

abandoned if FOSC is selected and ADRES will

have an incorrect value

7. I/O ports maintain the status they had before

Sleep was executed (driving high, low, or high-

impedance). This does not apply in the case of

any asynchronous peripheral which is active

and may affect the I/O port value

8. Resets other than WDT are not affected by

Sleep mode

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The WDT is cleared when the device wakes-up from

Sleep, regardless of the source of wake-up.

11.2.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

11.2.2

WAKE-UP USING INTERRUPTS

1. External Reset input on MCLR pin, if enabled.

2. BOR Reset, if enabled.

When global interrupts are disabled (GIE cleared) and

any interrupt source, with the exception of the clock

switch interrupt, has both its interrupt enable bit and

interrupt flag bit set, one of the following will occur:

3. POR Reset.

4. Watchdog Timer, if enabled.

5. Any external interrupt.

• If the interrupt occurs before the execution of a

SLEEPinstruction

6. Interrupts by peripherals capable of running

during Sleep (see individual peripheral for more

information).

- SLEEPinstruction will execute as a NOP

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

The first three events will cause a device Reset. The

last three events are considered a continuation of

program execution. To determine whether a device

Reset or wake-up event occurred, refer to

Section 8.12 “Memory Execution Violation”.

- PD bit of the STATUS register will not be

cleared

• If the interrupt occurs during or after the

execution of a SLEEPinstruction

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is prefetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be enabled. Wake-up will

occur regardless of the state of the GIE bit. If the GIE

bit is disabled, the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

enabled, the device executes the instruction after the

SLEEPinstruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

- SLEEPinstruction will be completely

executed

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

FIGURE 11-2:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN⁽¹⁾

(3)

CLKOUT⁽²⁾

TOST

Interrupt Latency⁽⁴⁾

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Forced NOP

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

External clock. High, Medium, Low mode assumed.

CLKOUT is shown here for timing reference.

TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.

GIE = 1assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.

2:

3:

4:

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11.2.3

LOW-POWER SLEEP MODE

11.3 IDLE Mode

The PIC16F15354/55 device contains an internal Low

Dropout (LDO) voltage regulator, which allows the

device I/O pins to operate at voltages up to 5.5V while

the internal device logic operates at a lower voltage.

The LDO and its associated reference circuitry must

remain active when the device is in Sleep mode.

When the Idle Enable (IDLEN) bit is clear (IDLEN = 0),

the SLEEPinstruction will put the device into full Sleep

mode (see Section 11.2 “Sleep Mode”). When IDLEN

is set (IDLEN = 1), the SLEEP instruction will put the

device into IDLE mode. In IDLE mode, the CPU and

memory operations are halted, but the peripheral

clocks continue to run. This mode is similar to DOZE

mode, except that in IDLE both the CPU and program

memory are shut off.

The PIC16F15354/55 allows the user to optimize the

operating current in Sleep, depending on the

application requirements.

Low-Power Sleep mode can be selected by setting the

VREGPM bit of the VREGCON register. Depending on

the configuration of these bits, the LDO and reference

circuitry are placed in a low-power state when the

device is in Sleep.

Note:

Peripherals using FOSC will continue

running while in Idle (but not in Sleep).

Peripherals

using

HFINTOSC,

LFINTOSC, or SOSC will continue

running in both Idle and Sleep.

11.2.3.1

Sleep Current vs. Wake-up Time

In the default operating mode, the LDO and reference

circuitry remain in the normal configuration while in

Sleep. The device is able to exit Sleep mode quickly

since all circuits remain active. In Low-Power Sleep

mode, when waking-up from Sleep, an extra delay time

is required for these circuits to return to the normal

configuration and stabilize.

Note:

If CLKOUT is enabled (CLKOUT = 0,

Configuration Word 1), the output will

continue operating while in Idle.

11.3.1

IDLE AND INTERRUPTS

IDLE mode ends when an interrupt occurs (even if

GIE = 0), but IDLEN is not changed. The device can re-

enter IDLE by executing the SLEEPinstruction.

The Low-Power Sleep mode is beneficial for

applications that stay in Sleep mode for long periods of

time. The Normal mode is beneficial for applications

that need to wake from Sleep quickly and frequently.

If Recover-on-Interrupt is enabled (ROI = 1), the

interrupt that brings the device out of Idle also restores

full-speed CPU execution when doze is also enabled.

11.2.3.2

Peripheral Usage in Sleep

Some peripherals that can operate in Sleep mode will

not operate properly with the Low-Power Sleep mode

selected. The Low-Power Sleep mode is intended for

use with these peripherals:

11.3.2

IDLE AND WDT

When in IDLE, the WDT Reset is blocked and will

instead wake the device. The WDT wake-up is not an

interrupt, therefore ROI does not apply.

• Brown-out Reset (BOR)

• Watchdog Timer (WDT)

• External interrupt pin/interrupt-on-change pins

• Timer1 (with external clock source)

Note:

The WDT can bring the device out of

IDLE, in the same way it brings the device

out of Sleep. The DOZEN bit is not

affected.

It is the responsibility of the end user to determine what

is acceptable for their application when setting the

VREGPM settings in order to ensure operation in

Sleep.

Note:

The PIC16LF15354/55 does not have a

configurable Low-Power Sleep mode.

PIC16LF15354/55 is an unregulated

device and is always in the lowest power

state when in Sleep, with no wake-up time

penalty. This device has a lower maximum

VDD and I/O voltage than the

PIC16F15354/55. See Section 37.0

“Electrical Specifications” for more

information.

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11.4 Register Definitions: Voltage Regulator and DOZE Control

REGISTER 11-1: VREGCON: VOLTAGE REGULATOR CONTROL REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

U-1

—

VREGPM

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

bit 1

Unimplemented: Read as ‘0’

VREGPM: Voltage Regulator Power Mode Selection bit

1= Low-Power Sleep mode enabled in Sleep⁽²⁾

Draws lowest current in Sleep, slower wake-up

0= Normal Power mode enabled in Sleep⁽²⁾

Draws higher current in Sleep, faster wake-up

bit 0

Unimplemented: Read as ‘1’. Maintain this bit set

Note 1: PIC16F15354/55 only.

2: See Section 37.0 “Electrical Specifications”.

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REGISTER 11-2: CPUDOZE: DOZE AND IDLE REGISTER

R/W-0/0

IDLEN

R/W/HC/HS-0/0 R/W-0/0 R/W/HS/HC-0/0

U-0

—

R/W-0/0

DOZEN⁽¹⁾

ROI⁽¹⁾

DOE⁽¹⁾

DOZE<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

HC = Bit is cleared by hardware

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other

Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HS = Bit is set by hardware

bit 7

bit 6

bit 5

bit 4

IDLEN: Idle Enable bit

1= A SLEEPinstruction places the device into IDLE mode

0= A SLEEPinstruction places the device into Sleep mode

DOZEN: Doze Enable bit

1= Places the device into DOZE mode

0= Places the device into Normal mode

ROI: Recover-on-Interrupt bit

1= Entering the Interrupt Service Routine (ISR) makes DOZEN = 0

0= Entering the Interrupt Service Routine (ISR) does not change DOZEN

DOE: Doze on Exit bit

1= Exiting the ISR makes DOZEN = 1

0= Exiting the ISR does not change DOZEN

bit 3

Unimplemented: Read as ‘0’

bit 2-0

DOZE<2:0>: Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles

111=1:256

110=1:128

101=1:64

100=1:32

011=1:16

010=1:8

001=1:4

000=1:2

Note 1: Refer to Table 11-1 for more details.

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TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STATUS

—

TO

—

PD

—

Z

DC

C

30

VREGCON

CPUDOZE

—

VREGPM

DOZE<2:0>

—

143

144

IDLEN

DOZEN

ROI

DOE

—

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode.

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12.0 WINDOWED WATCHDOG

TIMER (WWDT)

The Watchdog Timer (WDT) is a system timer that

generates a Reset if the firmware does not issue a

CLRWDT instruction within the time-out period. The

Watchdog Timer is typically used to recover the system

from unexpected events. The Windowed Watchdog

Timer (WWDT) differs in that CLRWDTinstructions are

only accepted when they are performed within a

specific window during the time-out period.

The WDT has the following features:

• Selectable clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256

seconds (nominal)

• Configurable window size from 12.5 to 100

percent of the time-out period

• Multiple Reset conditions

• Operation during Sleep

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FIGURE 12-1:

WATCHDOG TIMER BLOCK DIAGRAM

Rev. 10-000162C

10/12/2016

WWDT

Armed

WDT

Window

Violation

Window Closed

Comparator

Window

Sizes

CLRWDT

RESET

WDTWS

Reserved

111

110

101

100

011

010

001

000

Reserved

R

Reserved

18-bit Prescale

Counter

E

Reserved

SOSC

MFINTOSC/16

LFINTOSC

WDTCS

WDTPS

R

5-bit

WDT Counter

Overflow

Latch

WDT Time-out

WDTE<1:0> = 01

SWDTEN

WDTE<1:0> = 11

WDTE<1:0> = 10

Sleep

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12.1 Independent Clock Source

12.3 Time-Out Period

The WDT can derive its time base from either the 31

kHz LFINTOSC or 31.25 kHz MFINTOSC internal

oscillators, or the secondary oscillator SOSC,

depending on the value of either the WDTCCS<2:0>

Configuration bits or the WDTCS<2:0> bits of

WDTCON1. Time intervals in this chapter are based on

a minimum nominal interval of 1 ms. See Section 37.0

“Electrical Specifications” for LFINTOSC and

MFINTOSC tolerances.

The WDTPS bits of the WDTCON0 register set the

time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is two

seconds.

12.2 WDT Operating Modes

The Watchdog Timer module has four operating modes

controlled by the WDTE<1:0> bits in Configuration

Words. See Table 12-1.

12.2.1

WDT IS ALWAYS ON

When the WDTE bits of Configuration Words are set to

‘11’, the WDT is always on.

WDT protection is active during Sleep.

12.2.2

WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Words are set to

‘10’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

12.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Words are set to

‘01’, the WDT is controlled by the SWDTEN bit of the

WDTCON0 register.

12.2.4

WDT IS OFF

When the WDTE bits of the Configuration Word are set

to ‘00’, the WDT is always OFF.

WDT protection is unchanged by Sleep. See Table 12-1

for more details.

TABLE 12-1: WDT OPERATING MODES

Device

Mode

WDT

Mode

WDTE<1:0>

SWDTEN

11

10

X

Active

Awake

Sleep Disabled

1

0

X

Active

01

00

Disabled

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• Oscillator Start-up Timer (OST) is running

12.4 Watchdog Window

• Any write to the WDTCON0 or WDTCON1 registers

The Watchdog Timer has an optional Windowed mode

that is controlled by the WDTCWS<2:0> Configuration

bits and WINDOW<2:0> bits of the WDTCON1 register.

In the Windowed mode, the CLRWDT instruction must

occur within the allowed window of the WDT period. Any

CLRWDT instruction that occurs outside of this window

will trigger a window violation and will cause a WDT

Reset, similar to a WDT time out. See Figure 12-2 for an

example.

12.5.1

CLRWDTCONSIDERATIONS

(WINDOWED MODE)

When in Windowed mode, the WDT must be armed

before a CLRWDTinstruction will clear the timer. This is

performed by reading the WDTCON0 register. Execut-

ing a CLRWDT instruction without performing such an

arming action will trigger a window violation.

See Table 12-2 for more information.

The window size is controlled by the WDTCWS<2:0>

Configuration bits, or the WINDOW<2:0> bits of

WDTCON1, if WDTCWS<2:0> = 111.

12.6 Operation During Sleep

In the event of a window violation, a Reset will be

generated and the WDTWV bit of the PCON register

will be cleared. This bit is set by a POR or can be set in

firmware.

When the device enters Sleep, the WDT is cleared. If

the WDT is enabled during Sleep, the WDT resumes

counting. When the device exits Sleep, the WDT is

cleared again.

The WDT remains clear until the OST, if enabled, com-

pletes. See Section 9.0 “Oscillator Module (with Fail-

Safe Clock Monitor)” for more information on the OST.

12.5 Clearing the WDT

The WDT is cleared when any of the following

conditions occur:

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device

wakes up and resumes operation. The TO and PD bits

in the STATUS register are changed to indicate the

event. The RWDT bit in the PCON register can also be

used. See Section 4.3.2.1 “STATUS Register” for

more information.

• Any Reset

• Valid CLRWDTinstruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• WDT is disabled

TABLE 12-2: WDT CLEARING CONDITIONS

Conditions

WDT

WDTE<1:0> = 00

WDTE<1:0> = 01 and SWDTEN = 0

WDTE<1:0> = 10 and enter Sleep

CLRWDTCommand

Cleared

Oscillator Fail Detected

Exit Sleep + System Clock = SOSC, EXTOSC, INTOSC

Change INTOSC divider (IRCF bits)

Unaffected

FIGURE 12-2:

WINDOW PERIOD AND DELAY

Rev. 10-000163A

8/15/2016

CLRWDTInstruction

(or other WDT Reset)

Window Period

Window Closed

Window Open

Time-out Event

Window Delay

(window violation can occur)

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12.7 Register Definitions: Windowed Watchdog Timer Control

REGISTER 12-1: WDTCON0: WATCHDOG TIMER CONTROL REGISTER 0

R/W⁽³⁾-q/q⁽²⁾R/W⁽³⁾-q/q⁽²⁾R/W⁽³⁾-q/q⁽²⁾R/W⁽³⁾-q/q⁽²⁾R/W⁽³⁾-q/q⁽²⁾

U-0

R/W-0/0

SWDTEN

—

(1)

WDTPS<4:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-1

Unimplemented: Read as ‘0’

WDTPS<4:0>: Watchdog Timer Prescale Select bits⁽¹⁾

Bit Value = Prescale Rate

11111 =Reserved. Results in minimum interval (1:32)

•

10011 =Reserved. Results in minimum interval (1:32)

10010 =1:8388608 (2²³) (Interval 256s nominal)

10001 =1:4194304 (2²²) (Interval 128s nominal)

10000 =1:2097152 (2²¹) (Interval 64s nominal)

01111 =1:1048576 (2²⁰) (Interval 32s nominal)

01110 =1:524288 (2¹⁹) (Interval 16s nominal)

01101 =1:262144 (2¹⁸) (Interval 8s nominal)

01100 =1:131072 (2¹⁷) (Interval 4s nominal)

01011 =1:65536 (Interval 2s nominal) (Reset value)

01010 =1:32768 (Interval 1s nominal)

01001 =1:16384 (Interval 512 ms nominal)

01000 =1:8192 (Interval 256 ms nominal)

00111 =1:4096 (Interval 128 ms nominal)

00110 =1:2048 (Interval 64 ms nominal)

00101 =1:1024 (Interval 32 ms nominal)

00100 =1:512 (Interval 16 ms nominal)

00011 =1:256 (Interval 8 ms nominal)

00010 =1:128 (Interval 4 ms nominal)

00001 =1:64 (Interval 2 ms nominal)

00000 =1:32 (Interval 1 ms nominal)

bit 0

SWDTEN: Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> = 1x:

This bit is ignored.

If WDTE<1:0> = 01:

1= WDT is turned on

0= WDT is turned off

If WDTE<1:0> = 00:

This bit is ignored.

Note 1: Times are approximate. WDT time is based on 31 kHz LFINTOSC.

2: When WDTCPS <4:0> in CONFIG3 = 11111, the Reset value of WDTPS<4:0> is 01011. Otherwise, the

Reset value of WDTPS<4:0> is equal to WDTCPS<4:0> in CONFIG3.

3: When WDTCPS <4:0> in CONFIG3 ≠ 11111, these bits are read-only.

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REGISTER 12-2: WDTCON1: WATCHDOG TIMER CONTROL REGISTER 1

R/W⁽³⁾-q/q⁽¹⁾R/W⁽³⁾-q/q⁽¹⁾R/W⁽³⁾-q/q⁽¹⁾

WDTCS<2:0>

R/W⁽⁴⁾-q/q⁽²⁾

U-0

—

WINDOW<2:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

Unimplemented: Read as ‘0’

bit 6-4

WDTCS<2:0>: Watchdog Timer Clock Select bits

111=Reserved

•

010=SOSC 32 kHz

001=MFINTOSC 31.25 kHz

000=LFINTOSC 31 kHz

bit 3

Unimplemented: Read as ‘0’

bit 2-0

WINDOW<2:0>: Watchdog Timer Window Select bits

Window delay

Percent of time

Window opening

Percent of time

WINDOW<2:0>

111

110

101

100

011

010

001

000

N/A

12.5

25

100

87.5

75

37.5

50

62.5

50

62.5

75

37.5

25

87.5

12.5

Note 1: If WDTCCS <2:0> in CONFIG3 = 111, the Reset value of WDTCS<2:0> is 000.

2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3 register.

3: If WDTCCS<2:0> in CONFIG3 ≠ 111, these bits are read-only.

4: If WDTCWS<2:0> in CONFIG3 ≠ 111, these bits are read-only.

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REGISTER 12-3: WDTPSL: WDT PRESCALE SELECT LOW BYTE REGISTER

R-0/0

PSCNT<7:0>

R-0/0

(1)

R-0/0

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-0

PSCNT<7:0>: Prescale Select Low Byte bits

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR

registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

REGISTER 12-4: WDTPSH: WDT PRESCALE SELECT HIGH BYTE REGISTER

R-0/0

(1)

PSCNT<15:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-0

PSCNT<15:8>: Prescale Select High Byte bits

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR

registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

REGISTER 12-5: WDTTMR: WDT TIMER REGISTER

U-0

—

R-0/0

(1)

WDTTMR<3:0>

STATE

PSCNT<17:16>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

Unimplemented: Read as ‘0’

bit 6-3

bit 2

WDTTMR<3:0>: Watchdog Timer Value bits

STATE: WDT Armed Status bit

1= WDT is armed

0= WDT is not armed

(1)

bit 1-0

PSCNT<17:16>: Prescale Select Upper Byte bits

Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the WDTTMR

registers. PSCNT<17:0> is intended for debug operations and should be read during normal operation.

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TABLE 12-3: SUMMARY OF REGISTERS

ASSOCIATED WITH

WATCHDOG TIMER

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OSCCON1

OSCCON2

OSCCON3

PCON0

—

NOSC<2:0>

COSC<2:0>

—

NDIV<3:0>

CDIV<3:0>

110

111

99

CSWHOLD SOSCPWR

ORDY

NOSCR

—

STKOVF

STKUNF

WDTWV

—

RWDT

TO

RMCLR

RI

Z

POR

DC

BOR

C

STATUS

—

PD

WDTPS<4:0>

—

30

WDTCON0

WDTCON1

WDTPSL

WDTPSH

WDTTMR

Legend:

SWDTEN

150

151

152

WDTCS<2:0>

WINDOW<2:0>

PSCNT<7:0>

PSCNT<15:8>

WDTTMR<4:0>

—

STATE

PSCNT<17:16>

– = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer.

TABLE 12-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Register

on Page

Name

Bits Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

—

CSWEN

—

CLKOUTEN

13:8

7:0

FCMEN

CONFIG1

76

RSTOSC<2:0>

FEXTOSC<2:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.

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13.0 NONVOLATILE MEMORY

(NVM) CONTROL

TABLE 13-1: FLASH MEMORY

ORGANIZATION BY DEVICE

NVM consists of the Program Flash Memory.

Total

Program

Flash

Row

Erase Latches

(words) (words)

Write

NVM is accessible by using both the FSR and INDF

registers, or through the NVMREG register interface.

Device

(words)

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the operating

voltage range of the device.

4096

8192

PIC16(L)F15354

PIC16(L)F15355

32

NVM can be protected in two ways; by either code

protection or write protection.

It is important to understand the program memory

structure for erase and programming operations. The

program memory is arranged in rows. A row consists of

32 14-bit program memory words. A row is the

minimum size that can be erased by user software.

Code protection (CP bit in Configuration Word 5)

disables access, reading and writing, to the program

memory via external device programmers. Code

protection does not affect the self-write and erase

functionality. Code protection can only be Reset by a

device programmer performing a Bulk Erase to the

device, clearing all nonvolatile memory, Configuration

bits, and User IDs.

All or a portion of a row can be programmed. Data to be

written into the program memory row is written to 14-bit

wide data write latches. These latches are not directly

accessible, but may be loaded via sequential writes to

the NVMDATH:NVMDATL register pair.

Write protection prohibits self-write and erase to a

portion or all of the program memory, as defined by the

WRT<1:0> bits of Configuration Word 4. Write

protection does not affect a device programmer’s ability

to read, write, or erase the device.

Note:

To modify only a portion of a previously

programmed row, the contents of the

entire row must be read. Then, the new

data and retained data can be written into

the write latches to reprogram the row of

13.1 Program Flash Memory

program

memory.

However,

any

unprogrammed locations can be written

without first erasing the row. In this case,

it is not necessary to save and rewrite the

other previously programmed locations

The program memory consists of an array of 14-bit

words as user memory, with additional words for User

ID information, Configuration words, and interrupt

vectors. The program memory provides storage

locations for:

13.1.1

PROGRAM MEMORY VOLTAGES

• User program instructions

• User defined data

The program memory is readable and writable during

normal operation over the full VDD range.

Program memory data can be read and/or written to

through:

13.1.1.1

Programming Externally

• CPU instruction fetch (read-only)

• FSR/INDF indirect access (read-only)

(Section 13.2 “FSR and INDF Access”)

• NVMREG access (Section 13.3 “NVMREG

Access”

The program memory cell and control logic support

write and Bulk Erase operations down to the minimum

device operating voltage. Special BOR operation is

enabled during Bulk Erase (Section 8.2.4 “BOR is

always OFF”).

• In-Circuit Serial Programming™ (ICSP™)

Read operations return a single word of memory. When

write and erase operations are done on a row basis, the

row size is defined in Table 13-1. Program memory will

erase to a logic ‘1’ and program to a logic ‘0’.

13.1.1.2

Self-programming

The program memory cell and control logic will support

write and row erase operations across the entire VDD

range. Bulk Erase is not available when self-

programming.

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FIGURE 13-1:

FLASH PROGRAM

MEMORY READ

FLOWCHART

13.2 FSR and INDF Access

The FSR and INDF registers allow indirect access to

the program memory.

Rev. 10-000046D

8/15/2016

13.2.1

FSR READ

With the intended address loaded into an FSR register

a MOVIWinstruction or read of INDF will read data from

the program memory.

Start

Read Operation

Reading from NVM requires one instruction cycle. The

CPU operation is suspended during the read, and

resumes immediately after. Read operations return a

single byte of memory.

Select Memory:

PFM, DIA, DCI, Config Words, User

ID (NVMREGS)

13.2.2

FSR WRITE

Writing/erasing the NVM through the FSR registers (ex.

MOVWI instruction) is not supported in the

PIC16(L)F15354/55 devices.

Select

Word Address

(NVMADRH:NVMADRL)

13.3 NVMREG Access

Data read now in

The NVMREG interface allows read/write access to all

the locations accessible by FSRs, and also read/write

access to the User ID locations, and read-only access

to the device identification, revision, and Configuration

data.

NVMDATH:NVMDATL

End

Read Operation

Writing or erasing of NVM via the NVMREG interface is

prevented when the device is write-protected.

13.3.1

NVMREG READ OPERATION

To read a NVM location using the NVMREG interface,

the user must:

1. Clear the NVMREGS bit of the NVMCON1

register if the user intends to access the

program memory locations, or set NMVREGS if

the user intends to access User ID, or

Configuration locations.

2. Write

the

desired

address

into

the

NVMADRH:NVMADRL register pair (Table 13-

2).

3. Set the RD bit of the NVMCON1 register to

initiate the read.

Once the read control bit is set, the CPU operation is

suspended during the read, and resumes immediately

after. The data is available in the very next cycle, in the

NVMDATH:NVMDATL register pair; therefore, it can be

read as two bytes in the following instructions.

NVMDATH:NVMDATL register pair will hold this value

until another read or until it is written to by the user.

Upon completion, the RD bit is cleared by hardware.

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EXAMPLE 13-1:

PROGRAM MEMORY READ

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO

*

data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSELNVMADRL; Select Bank for NVMCON registers

MOVLWPROG_ADDR_LO;

MOVWFNVMADRL; Store LSB of address

MOVLWPROG_ADDR_HI;

MOVWFNVMADRH; Store MSB of address

BCF NVMCON1,NVMREGS; Do not select Configuration Space

BSF NVMCON1,RD; Initiate read

MOVFNVMDATL,W; Get LSB of word

MOVWFPROG_DATA_LO; Store in user location

MOVFNVMDATH,W; Get MSB of word

MOVWFPROG_DATA_HI; Store in user location

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13.3.2

NVM UNLOCK SEQUENCE

FIGURE 13-2:

NVM UNLOCK

SEQUENCE FLOWCHART

The unlock sequence is a mechanism that protects the

NVM from unintended self-write programming or

erasing. The sequence must be executed and

completed without interruption to successfully

complete any of the following operations:

Rev. 10-000047B

8/24/2015

Start

Unlock Sequence

• Program memory Row Erase

• Load of program memory write latches

• Write of program memory write latches to pro-

gram memory

• Write of program memory write latches to User

IDs

Write 0x55 to

NVMCON2

The unlock sequence consists of the following steps

and must be completed in order:

Write 0xAA to

NVMCON2

• Write 55h to NVMCON2

• Write AAh to NMVCON2

• Set the WR bit of NVMCON1

Once the WR bit is set, the processor will stall internal

operations until the operation is complete and then

resume with the next instruction.

Initiate

Write or Erase operation

(WR = 1)

Note:

The two NOPinstructions after setting the

WR bit that were required in previous

End

Unlock Sequence

devices

PIC16(L)F15354/55

Figure 13-2.

are

not

required

devices.

for

See

Since the unlock sequence must not be interrupted,

global interrupts should be disabled prior to the unlock

sequence and re-enabled after the unlock sequence is

completed.

EXAMPLE 13-2:

NVM UNLOCK SEQUENCE

BCF INTCON, GIE; Recommended so sequence is not interrupted

BANKSELNVMCON1;

BSF NVMCON1, WREN; Enable write/erase

MOVLW55h; Load 55h

MOVWFNVMCON2; Step 1: Load 55h into NVMCON2

MOVLWAAh; Step 2: Load W with AAh

MOVWFNVMCON2; Step 3: Load AAH into NVMCON2

BSF NVMCON1, WR; Step 4: Set WR bit to begin write/erase

BSF INTCON, GIE; Re-enable interrupts

Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order shown.

2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.

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13.3.3

NVMREG ERASE OF PROGRAM

MEMORY

FIGURE 13-3:

NVM ERASE

FLOWCHART

Rev. 10-000048B

8/24/2015

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten. The

program memory can only be erased one row at a time.

No automatic erase occurs upon the initiation of the

write to program memory.

Start

Erase Operation

To erase a program memory row:

1. Clear the NVMREGS bit of the NVMCON1

register to erase program memory locations, or

set the NMVREGS bit to erase User ID

locations.

Select Memory:

PFM, Config Words, User ID

(NVMREGS)

2. Write

the

desired

address

into

the

Select Word Address

(NVMADRH:NVMADRL)

NVMADRH:NVMADRL register pair (Table 13-2).

3. Set the FREE and WREN bits of the NVMCON1

register.

4. Perform the unlock sequence as described in

Section 13.3.2 “NVM Unlock Sequence”.

Select Erase Operation

(FREE=1)

If the program memory address is write-protected, the

WR bit will be cleared and the erase operation will not

take place.

While erasing the program memory, CPU operation is

suspended, and resumes when the operation is

complete. Upon completion, the NVMIF is set, and an

interrupt will occur if the NVMIE bit is also set.

Enable Write/Erase Operation

(WREN=1)

Write latch data is not affected by erase operations,

and WREN will remain unchanged.

Disable Interrupts

(GIE=0)

Unlock Sequence

(See Note 1)

CPU stalls while

Erase operation completes

(2 ms typical)

Disable Write/Erase Operation

(WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Erase Operation

Note 1: See Figure 13-2.

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EXAMPLE 13-3:

ERASING ONE ROW OF PROGRAM FLASH MEMORY (PFM)

; This sample row erase routine assumes the following:

; 1.A valid address within the erase row is loaded in variables ADDRH:ADDRL

; 2.ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

BANKSEL

MOVF

NVMADRL

ADDRL,W

MOVWF

MOVF

NVMADRL

; Load lower 8 bits of erase address boundary

ADDRH,W

MOVWF

BCF

NVMADRH

; Load upper 6 bits of erase address boundary

; Choose PFM memory area

NVMCON1,NVMREGS

NVMCON1,FREE

BSF

; Specify an erase operation

BSF

BCF

NVMCON1,WREN

INTCON,GIE

; Enable writes

; Disable interrupts during unlock sequence

; -------------------------------REQUIRED UNLOCK SEQUENCE:------------------------------

MOVLW

MOVWF

MOVLW

55h

; Load 55h to get ready for unlock sequence

; First step is to load 55h into NVMCON2

; Second step is to load AAh into W

NVMCON2

AAh

MOVWF

BSF

NVMCON2

NVMCON1,WR

; Third step is to load AAh into NVMCON2

; Final step is to set WR bit

; --------------------------------------------------------------------------------------

BSF

BCF

INTCON,GIE

; Re-enable interrupts, erase is complete

; Disable writes

NVMCON1,WREN

TABLE 13-2: NVM ORGANIZATION AND ACCESS INFORMATION

Master Values

NVMREG Access

FSR Access

FSR

Program

Counter (PC),

ICSP™

NVMREGS

bit

(NVMCON1)

Memory

Function

NVMADR<

Allowed

FSR

Memory Type

Programming

Address

14:0>

Operations

Address

Reset Vector

User Memory

INT Vector

0000h

0001h

0003h

0004h

0005h

0

0000h

0001h

0003h

0004h

0005h

0FFFh

1FFFh

0000h

0003h

0004h

0005h

0006h

0007h

0008h

0009h

000Ah

000Bh

8000h

8001h

8003h

8004h

8005h

8FFFh

9FFFh

Program Flash

Memory

Read

Write

Read-0nly

(1)

User Memory

0FFFh

0

(2)

1FFFh

8000h

8003h

8004h

8005h

8006h

8007h

8008h

8009h

800Ah

800Bh

Read

Write

—

Program Flash

Memory

User ID

1

Reserved

Rev ID

—

1

Read-Only

Device ID

CONFIG1

CONFIG2

CONFIG3

CONFIG4

CONFIG5

No Access

Program Flash

Memory

Read

Write

Program Flash

Memory and

Hard coded

Read-Only

0100h-

02FFh

DIA and DCI

8100h-82FFh

1

No Access

Note 1: PIC16(L)F15354 only.

2: PIC16(L)F15355 only.

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PIC16(L)F15354/55

The following steps should be completed to load the

write latches and program a row of program memory.

These steps are divided into two parts. First, each write

13.3.4

NVMREG WRITE TO PROGRAM

MEMORY

Program memory is programmed using the following

steps:

latch

is

loaded

with

data

from

the

NVMDATH:NVMDATL using the unlock sequence with

LWLO = 1. When the last word to be loaded into the

write latch is ready, the LWLO bit is cleared and the

unlock sequence executed. This initiates the

programming operation, writing all the latches into

Flash program memory.

1. Load the address of the row to be programmed

into NVMADRH:NVMADRL.

2. Load each write latch with data.

3. Initiate a programming operation.

4. Repeat steps 1 through 3 until all data is written.

Note:

The special unlock sequence is required

to load a write latch with data or initiate a

Flash programming operation. If the

unlock sequence is interrupted, writing to

the latches or program memory will not be

initiated.

Before writing to program memory, the word(s) to be

written must be erased or previously unwritten.

Program memory can only be erased one row at a time.

No automatic erase occurs upon the initiation of the

write.

Program memory can be written one or more words at

a time. The maximum number of words written at one

time is equal to the number of write latches. See

Figure 13-4 (row writes to program memory with 32

write latches) for more details.

1. Set the WREN bit of the NVMCON1 register.

2. Clear the NVMREGS bit of the NVMCON1

register.

3. Set the LWLO bit of the NVMCON1 register.

When the LWLO bit of the NVMCON1 register is

‘1’, the write sequence will only load the write

latches and will not initiate the write to Flash

program memory.

The write latches are aligned to the Flash row address

boundary defined by the upper ten bits of

NVMADRH:NVMADRL, (NVMADRH<6:0>:NVMADRL<7:5>)

with the lower five bits of NVMADRL, (NVMADRL<4:0>)

determining the write latch being loaded. Write opera-

tions do not cross these boundaries. At the completion

of a program memory write operation, the data in the

write latches is reset to contain 0x3FFF.

4. Load the NVMADRH:NVMADRL register pair

with the address of the location to be written.

5. Load the NVMDATH:NVMDATL register pair

with the program memory data to be written.

6. Execute the unlock sequence (Section 13.3.2

“NVM Unlock Sequence”). The write latch is

now loaded.

7. Increment the NVMADRH:NVMADRL register

pair to point to the next location.

8. Repeat steps 5 through 7 until all but the last

write latch has been loaded.

9. Clear the LWLO bit of the NVMCON1 register.

When the LWLO bit of the NVMCON1 register is

‘0’, the write sequence will initiate the write to

Flash program memory.

10. Load the NVMDATH:NVMDATL register pair

with the program memory data to be written.

11. Execute the unlock sequence (Section 13.3.2

“NVM Unlock Sequence”). The entire program

memory latch content is now written to Flash

program memory.

Note:

The program memory write latches are

reset to the blank state (0x3FFF) at the

completion of every write or erase

operation. As a result, it is not necessary

to load all the program memory write

latches. Unloaded latches will remain in

the blank state.

An example of the complete write sequence is shown in

Example 13-4. The initial address is loaded into the

NVMADRH:NVMADRL register pair; the data is loaded

using indirect addressing.

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FIGURE 13-5:

PROGRAM FLASH MEMORY WRITE FLOWCHART

Rev. 10-000049C

8/24/2015

Start

Write Operation

Determine number of

words to be written into

PFM. The number of

words cannot exceed the

number of words per row

(word_cnt)

Load the value to write

TABLAT

Update the word counter

(word_cnt--)

Write Latches to PFM

Select access to PFM

locations using

NVMREG<1:0> bits

Disable Interrupts

(GIE = 0)

Last word to

write ?

Yes

Select Row Address

TBLPTR

No

Unlock Sequence

(See note 1)

Disable Interrupts

Select Write Operation

(GIE = 0)

(FREE = 0)

CPU stalls while Write

operation completes

(2 ms typical)

Unlock Sequence

(See note 1)

Load Write Latches Only

Enable Write/Erase

Operation (WREN = 1)

Re-enable Interrupts

No delay when writing to

PFM Latches

(GIE = 1)

Disable Write/Erase

Operation (WREN = 0)

Re-enable Interrupts

(GIE = 1)

End

Write Operation

Increment Address

TBLPTR++

Note 1: See Figure 13-2.

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EXAMPLE 13-4:

WRITING TO PROGRAM FLASH MEMORY

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

;

stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

; 5. NVM interrupts are not taken into account

BANKSEL

MOVF

NVMADRH

ADDRH,W

MOVWF

MOVF

NVMADRH

; Load initial address

ADDRL,W

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

NVMADRL

LOW DATA_ADDR

FSR0L

; Load initial data address

HIGH DATA_ADDR

FSR0H

NVMCON1,NVMREGS

; Set Program Flash Memory as write location

BSF

NVMCON1,WREN

NVMCON1,LWLO

; Enable writes

; Load only write latches

LOOP

MOVIW

MOVWF

FSR0++

NVMDATL

; Load first data byte

; Load second data byte

MOVIW

MOVWF

FSR0++

NVMDATH

MOVF

NVMADRL,W

0x1F

XORLW

ANDLW

; Check if lower bits of address are 00000

; and if on last of 32 addresses

0x1F

BTFSC

GOTO

STATUS,Z

START_WRITE

; Last of 32 words?

; If so, go write latches into memory

CALL

UNLOCK_SEQ

; If not, go load latch

; Increment address

INCF

GOTO

NVMADRL,F

LOOP

START_WRITE

BCF

NVMCON1,LWLO

; Latch writes complete, now write memory

CALL

BCF

UNLOCK_SEQ

NVMCON1,WREN

; Perform required unlock sequence

; Disable writes

UNLOCK_SEQ

MOVLW

BCF

55h

INTCON,GIE

NVMCON2

AAh

; Disable interrupts

MOVWF

MOVLW

MOVWF

BSF

; Begin unlock sequence

NVMCON2

NVMCON1,WR

INTCON,GIE

BSF

; Unlock sequence complete, re-enable interrupts

return

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13.3.5

MODIFYING FLASH PROGRAM

MEMORY

FIGURE 13-6:

FLASH PROGRAM

MEMORY MODIFY

FLOWCHART

When modifying existing data in a program memory

row, and data within that row must be preserved, it must

first be read and saved in a RAM image. Program

memory is modified using the following steps:

Rev. 10-000050B

8/21/2015

Start

Modify Operation

1. Load the starting address of the row to be

modified.

2. Read the existing data from the row into a RAM

image.

Read Operation

(See Note 1)

3. Modify the RAM image to contain the new data

to be written into program memory.

4. Load the starting address of the row to be

rewritten.

An image of the entire row

read must be stored in RAM

5. Erase the program memory row.

6. Load the write latches with data from the RAM

image.

7. Initiate a programming operation.

Modify Image

The words to be modified are

changed in the RAM image

Erase Operation

(See Note 2)

Write Operation

Use RAM image

(See Note 3)

End

Modify Operation

Note 1: See Figure 13-1.

2: See Figure 13-3.

3: See Figure 13-5.

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13.3.6

NVMREG ACCESS TO DEVICE

INFORMATION AREA, DEVICE

CONFIGURATION AREA, USER ID,

DEVICE ID AND CONFIGURATION

WORDS

NVMREGS can be used to access the following

memory regions:

• Device Information Area (DIA)

• Device Configuration Information (DCI)

• User ID region

• Device ID and Revision ID

• Configuration Words

The value of NVMREGS is set to ‘1’ in the NVMCON1

register to access these regions. The memory regions

listed above would be pointed to by PC<15> = 1, but

not all addresses reference valid data. Different access

may exist for reads and writes. Refer to Table 13-3.

When read access is initiated on an address outside

the parameters listed in Table 13-3, the NVMDATH:

NVMDATL register pair is cleared, reading back ‘0’s.

TABLE 13-3:

NVMREGS ACCESS TO DEVICE INFORMATION AREA, DEVICE CONFIGURATION

AREA, USER ID, DEVICE ID AND CONFIGURATION WORDS (NVMREGS = 1)

Address

Function

Read Access

Write Access

8000h-8003h

8005h-8006h

8007h-800Bh

8100h-82FFh

User IDs

Yes

No

Device ID/Revision ID

Configuration Words 1-5

DIA and DCI

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EXAMPLE 13-5:

DEVICE ID ACCESS

; This write routine assumes the following:

; 1. A full row of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in common RAM (locations 0x70 - 0x7F)

; 5. NVM interrupts are not taken into account

BANKSEL

MOVF

NVMADRH

ADDRH,W

MOVWF

MOVF

NVMADRH

ADDRL,W

; Load initial address

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

NVMADRL

LOW DATA_ADDR

FSR0L

HIGH DATA_ADDR

FSR0H

NVMCON1,NVMREGS

; Load initial data address

; Set PFM as write location

BSF

NVMCON1,WREN

NVMCON1,LWLO

; Enable writes

; Load only write latches

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++

NVMDATL

FSR0++

NVMDATH

; Load first data byte

; Load second data byte

CALL

INCF

MOVF

XORLW

ANDLW

UNLOCK_SEQ

NVMADRL,F

NVMADRL,W

0x1F

; If not, go load latch

; Increment address

; Check if lower bits of address are 00000

; and if on last of 32 addresses

0x1F

BTFSC

GOTO

STATUS,Z

START_WRITE

; Last of 32 words?

; If so, go write latches into memory

GOTO

LOOP

START_WRITE

BCF

NVMCON1,LWLO

; Latch writes complete, now write memory

CALL

BCF

UNLOCK_SEQ

NVMCON1,LWLO

; Perform required unlock sequence

; Disable writes

UNLOCK_SEQ

MOVLW

BCF

MOVWF

MOVLW

MOVWF

BSF

55h

INTCON,GIE

NVMCON2

AAh

NVMCON2

NVMCON1,WR

INTCON,GIE

; Disable interrupts

; Begin unlock sequence

BSF

; Unlock sequence complete, re-enable interrupts

return

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13.3.7

WRITE VERIFY

It is considered good programming practice to verify that

program memory writes agree with the intended value.

Since program memory is stored as a full row then the

stored program memory contents are compared with the

intended data stored in RAM after the last write is

complete.

FIGURE 13-7:

FLASH PROGRAM

MEMORY VERIFY

FLOWCHART

Rev. 10-000051B

12/4/2015

Start

Verify Operation

This routine assumes that the last

row of data written was from an

image saved on RAM. This image

will be used to verify the data

currently stored in PFM

Read Operation⁽¹⁾

NVMDAT =

RAM image ?

No

Yes

Fail

Verify Operation

No

Last word ?

Yes

End

Verify Operation

Note 1: See Figure 13-1.

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13.3.8

WRERR BIT

The WRERR bit can be used to determine if a write

error occurred.

WRERR will be set if one of the following conditions

occurs:

• If WR is set while the NVMADRH:NMVADRL

points to a write-protected address

• A Reset occurs while a self-write operation was in

progress

• An unlock sequence was interrupted

The WRERR bit is normally set by hardware, but can

be set by the user for test purposes. Once set, WRERR

must be cleared in software.

TABLE 13-4: ACTIONS FOR PFM WHEN WR = 1

Free

LWLO

Actions for PFM when WR = 1

Comments

1

x

Erase the 32-word row of NVMADRH:NVMADRL • If WP is enabled, WR is cleared and

location. See Section 13.3.3 “NVMREG Erase

WRERR is set

of Program Memory”

• All 32 words are erased

• NVMDATH:NVMDATL is ignored

0

1

0

Copy NVMDATH:NVMDATL to the write latch

corresponding to NVMADR LSBs. See

Section 13.3.3 “NVMREG Erase of Program

Memory”

• Write protection is ignored

• No memory access occurs

Write the write-latch data to PFM row. See

Section 13.3.3 “NVMREG Erase of Program

Memory”

• If WP is enabled, WR is cleared and

WRERR is set

• Write latches are reset to 3FFh

• NVMDATH:NVMDATL is ignored

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13.4 Register Definitions: Flash Program Memory Control

REGISTER 13-1: NVMDATL: NONVOLATILE MEMORY DATA LOW BYTE REGISTER

R/W-x/u

NVMDAT<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

NVMDAT<7:0>: Read/write value for Least Significant bits of program memory

REGISTER 13-2: NVMDATH: NONVOLATILE MEMORY DATA HIGH BYTE REGISTER

U-0

—

U-0

—

R/W-x/u

NVMDAT<13:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

NVMDAT<13:8>: Read/write value for Most Significant bits of program memory

REGISTER 13-3: NVMADRL: NONVOLATILE MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0

NVMADR<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

NVMADR<7:0>: Specifies the Least Significant bits for program memory address

REGISTER 13-4: NVMADRH: NONVOLATILE MEMORY ADDRESS HIGH BYTE REGISTER

U-1

R/W-0/0

(1)

—

NVMADR<14:8>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

Unimplemented: Read as ‘1’

NVMADR<14:8>: Specifies the Most Significant bits for program memory address

bit 6-0

Note 1: Bit is undefined while WR = 1

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REGISTER 13-5: NVMCON1: NONVOLATILE MEMORY CONTROL 1 REGISTER

U-0

—

R/W-0/0

LWLO

R/W/HC-0/0

FREE

R/W/HC-x/q

R/W-0/0

WREN

R/S/HC-0/0

RD

(1,2,3)

(4,5,6)

NVMREGS

WRERR

WR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

S = Bit can only be set

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

bit 6

Unimplemented: Read as ‘0’

NVMREGS: Configuration Select bit

1= Access DIA, DCI, Configuration, User ID and Device ID Registers

0= Access Program Flash Memory

bit 5

LWLO: Load Write Latches Only bit

When FREE = 0:

1= The next WR command updates the write latch for this word within the row; no memory operation is initiated.

0= The next WR command writes data or erases

Otherwise: The bit is ignored

bit 4

bit 3

FREE: Program Flash Memory Erase Enable bit

1= Performs an erase operation with the next WR command; the 32-word pseudo-row containing the indicated

address is erased (to all 1s) to prepare for writing.

0= All erase operations have completed normally

(1,2,3)

WRERR: Program/Erase Error Flag bit

This bit is normally set by hardware.

1= A write operation was interrupted by a Reset, interrupted unlock sequence, or WR was written to one while

NVMADR points to a write-protected address.

0= The program or erase operation completed normally

bit 2

bit 1

WREN: Program/Erase Enable bit

1= Allows program/erase cycles

0= Inhibits programming/erasing of program Flash

(4,5,6)

WR: Write Control bit

When NVMREG:NVMADR points to a Program Flash Memory location:

1= Initiates the operation indicated by Table 13-4

0= NVM program/erase operation is complete and inactive.

(7)

bit 0

RD: Read Control bit

1= Initiates a read at address = NVMADR1, and loads data to NVMDAT Read takes one instruction cycle and the

bit is cleared when the operation is complete. The bit can only be set (not cleared) in software.

0= NVM read operation is complete and inactive

Note 1: Bit is undefined while WR = 1.

2: Bit must be cleared by software; hardware will not clear this bit.

3: Bit may be written to ‘1’ by software in order to implement test sequences.

4: This bit can only be set by following the unlock sequence of Section 13.3.2 “NVM Unlock Sequence”.

5: Operations are self-timed, and the WR bit is cleared by hardware when complete.

6: Once a write operation is initiated, setting this bit to zero will have no effect.

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REGISTER 13-6: NVMCON2: NONVOLATILE MEMORY CONTROL 2 REGISTER

W-0/0

NVMCON2<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

S = Bit can only be set

‘1’ = Bit is set

bit 7-0

NVMCON2<7:0>: Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first followed by an AAh before setting the WR bit of the

NVMCON1 register. The value written to this register is used to unlock the writes.

TABLE 13-5: SUMMARY OF REGISTERS ASSOCIATED WITH NONVOLATILE MEMORY (NVM)

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE7

GIE

—

PEIE

—

INTEDG

CWG1IE

121

129

137

170

171

169

NVMIE

NCO1IE

PIR7

—

NVMIF

LWLO

NCO1IF

FREE

—

CWG1IF

RD

NVMCON1

NVMCON2

NVMADRL

NVMREGS

WRERR

WREN

WR

NVMCON2<7:0>

NVMADR<7:0>

(1)

NVMADRH

NVMDATL

—

NVMADR<14:8>

NVMDAT<7:0>

NVMDAT<13:8>

NVMDATH

—

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by NVM.

Note 1: Unimplemented, read as ‘1’.

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Disabling the input buffer prevents analog signal levels

on the pin between a logic high and low from causing

excessive current in the logic input circuitry. A

simplified model of a generic I/O port, without the

interfaces to other peripherals, is shown in Figure 14-1.

14.0 I/O PORTS

TABLE 14-1: PORT AVAILABILITY PER

DEVICE

Device

FIGURE 14-1:

GENERIC I/O PORT

OPERATION

Rev. 10-000052A

7/30/2013

PIC16(L)F15354/55

●

Read LATx

Each port has standard registers for its operation.

These registers are:

• PORTx registers (reads the levels on the pins of

the device)

TRISx

D

Q

• LATx registers (output latch)

• TRISx registers (data direction)

• ANSELx registers (analog select)

• WPUx registers (weak pull-up)

• INLVLx (input level control)

Write LATx

VDD

Write PORTx

CK

Data Register

Data bus

• SLRCONx registers (slew rate)

• ODCONx registers (open-drain)

I/O pin

Read PORTx

To digital peripherals

ANSELx

Most port pins share functions with device peripherals,

both analog and digital. In general, when a peripheral

is enabled on a port pin, that pin cannot be used as a

general purpose output; however, the pin can still be

read.

To analog peripherals

VSS

The Data Latch (LATx registers) is useful for read-

modify-write operations on the value that the I/O pins

are driving.

14.1 I/O Priorities

Each pin defaults to the PORT data latch after Reset.

Other functions are selected with the peripheral pin

select logic. See Section 15.0 “Peripheral Pin Select

(PPS) Module” for more information.

A write operation to the LATx register has the same

effect as a write to the corresponding PORTx register.

A read of the LATx register reads of the values held in

the I/O PORT latches, while a read of the PORTx

register reads the actual I/O pin value.

Analog input functions, such as ADC and comparator

inputs, are not shown in the peripheral pin select lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx register. Digital output

functions may continue to control the pin when it is in

Analog mode.

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital

input buffer associated with that bit is disabled.

Analog outputs, when enabled, take priority over the

digital outputs and force the digital output driver to the

high-impedance state.

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14.2.3

OPEN-DRAIN CONTROL

14.2 PORTA Registers

14.2.1 DATA REGISTER

The ODCONA register (Register 14-6) controls the

open-drain feature of the port. Open-drain operation is

independently selected for each pin. When an

ODCONA bit is set, the corresponding port output

becomes an open-drain driver capable of sinking

current only. When an ODCONA bit is cleared, the

corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

PORTA is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 14-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., disable the

output driver). Clearing a TRISA bit (= 0) will make the

corresponding PORTA pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Example 14.2.8 shows how to

initialize PORTA.

Note:

It is not necessary to set open-drain

control when using the pin for I²C; the I²C

module controls the pin and makes the pin

open-drain.

Reading the PORTA register (Register 14-1) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATA).

14.2.4

SLEW RATE CONTROL

The SLRCONA register (Register 14-7) controls the

slew rate option for each port pin. Slew rate control is

independently selectable for each port pin. When an

SLRCONA bit is set, the corresponding port pin drive is

slew rate limited. When an SLRCONA bit is cleared,

The corresponding port pin drive slews at the maximum

rate possible.

The PORT data latch LATA (Register 14-3) holds the

output port data, and contains the latest value of a

LATA or PORTA write.

EXAMPLE 14-1:

INITIALIZING PORTA

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

14.2.5

INPUT THRESHOLD CONTROL

The INLVLA register (Register 14-8) controls the input

voltage threshold for each of the available PORTA input

pins. A selection between the Schmitt Trigger CMOS or

the TTL Compatible thresholds is available. The input

threshold is important in determining the value of a read

of the PORTA register and also the level at which an

interrupt-on-change occurs, if that feature is enabled.

See Table 37-4 for more information on threshold

levels.

BANKSELPORTA;

CLRF

BANKSELLATA;Data Latch

CLRF LATA;

BANKSELANSELA;

PORTA;Init PORTA

CLRF

ANSELA;digital I/O

BANKSELTRISA;

MOVLW

MOVWF

B'00111000';Set RA<5:3> as inputs

TRISA;and set RA<2:0> as

;outputs

Note:

Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

14.2.2

DIRECTION CONTROL

active may inadvertently generate

a

The TRISA register (Register 14-2) controls the

PORTA pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISA register are maintained set when using

them as analog inputs. I/O pins configured as analog

inputs always read ‘0’.

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

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14.2.6

ANALOG CONTROL

The ANSELA register (Register 14-4) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

The state of the ANSELA bits has no effect on digital

output functions. A pin with its TRIS bit clear and its

ANSEL bit set will still operate as a digital output, but

the Input mode will be analog. This can cause

unexpected behavior when executing read-modify-

write instructions on the affected port.

Note:

The ANSELA bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

14.2.7

WEAK PULL-UP CONTROL

The WPUA register (Register 14-5) controls the

individual weak pull-ups for each PORT pin.

14.2.8

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions.

Each pin defaults to the PORT latch data after Reset.

Other output functions are selected with the peripheral

pin select logic or by enabling an analog output, such

as the DAC. See Section 15.0 “Peripheral Pin Select

(PPS) Module” for more information.

Analog input functions, such as ADC and comparator

inputs are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

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14.3 Register Definitions: PORTA

REGISTER 14-1: PORTA: PORTA REGISTER

R/W-x/u

RA7

R/W-x/u

RA6

R/W-x/u

RA5

R/W-x/u

RA4

R-x/u

RA3

R/W-x/u

RA2

R/W-x/u

RA1

R/W-x/u

RA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RA<7:0>: PORTA I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register returns

of actual I/O pin values.

REGISTER 14-2: TRISA: PORTA TRI-STATE REGISTER

R/W-1/1

TRISA7

R/W-1/1

TRISA6

R/W-1/1

TRISA5

R/W-1/1

TRISA4

R/W-1/1

TRISA3

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISA<7:0>: PORTA Tri-State Control bit

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

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REGISTER 14-3: LATA: PORTA DATA LATCH REGISTER

R/W-x/u

LATA7

R/W-x/u

LATA6

R/W-x/u

LATA5

R/W-x/u

LATA4

R/W-1/1

LATA3

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATA<7:0>: RA<7:0> Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register returns

actual I/O pin values.

REGISTER 14-4: ANSELA: PORTA ANALOG SELECT REGISTER

R/W-1/1

ANSA7

R/W-1/1

ANSA6

R/W-1/1

ANSA5

R/W-1/1

ANSA4

R/W-1/1

ANSA3

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ANSA<7:0>: Analog Select between Analog or Digital Function on pins RA<7:0>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

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REGISTER 14-5: WPUA: WEAK PULL-UP PORTA REGISTER

R/W-0/0

WPUA7

R/W-0/0

WPUA6

R/W-0/0

WPUA5

R/W-0/0

WPUA4

R/W-0/0

WPUA3

R/W-0/0

WPUA2

R/W-0/0

WPUA1

R/W-0/0

WPUA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

WPUA<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: The weak pull-up device is automatically disabled if the pin is configured as an output.

REGISTER 14-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER

R/W-0/0

ODCA7

R/W-0/0

ODCA6

R/W-0/0

ODCA5

R/W-0/0

ODCA4

R/W-0/0

ODCA3

R/W-0/0

ODCA2

R/W-0/0

ODCA1

R/W-0/0

ODCA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ODCA<7:0>: PORTA Open-Drain Enable bits

For RA<7:0> pins, respectively

1= Port pin operates as open-drain drive (sink current only)

0= Port pin operates as standard push-pull drive (source and sink current)

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REGISTER 14-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER

R/W-1/1

SLRA7

R/W-1/1

SLRA6

R/W-1/1

SLRA5

R/W-1/1

SLRA4

R/W-1/1

SLRA3

R/W-1/1

SLRA2

R/W-1/1

SLRA1

R/W-1/1

SLRA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SLRA<7:0>: PORTA Slew Rate Enable bits

For RA<7:0> pins, respectively

1= Port pin slew rate is limited

0= Port pin slews at maximum rate

REGISTER 14-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER

R/W-1/1

INLVLA7

R/W-1/1

INLVLA6

R/W-1/1

INLVLA5

R/W-1/1

INLVLA4

R/W-1/1

INLVLA3

R/W-1/1

INLVLA2

R/W-1/1

INLVLA1

R/W-1/1

INLVLA0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

INLVLA<7:0>: PORTA Input Level Select bits

For RA<7:0> pins, respectively

1= ST input used for PORT reads and interrupt-on-change

0= TTL input used for PORT reads and interrupt-on-change

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TABLE 14-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTA

TRISA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

175

176

177

178

TRISA7

LATA7

TRISA6

LATA6

TRISA5

LATA5

TRISA4

LATA4

TRISA3

LATA3

TRISA2

LATA2

TRISA1

LATA1

TRISA0

LATA0

LATA

ANSELA

WPUA

ANSA7

WPUA7

ODCA7

SLRA7

ANSA6

WPUA6

ODCA6

SLRA6

ANSA5

WPUA5

ODCA5

SLRA5

ANSA4

WPUA4

ODCA4

SLRA4

ANSA3

WPUA3

ODCA3

SLRA3

ANSA2

WPUA2

ODCA2

SLRA2

ANSA1

WPUA1

ODCA1

SLRA1

ANSA0

WPUA0

ODCA0

SLRA0

ODCONA

SLRCONA

INLVLA

INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0

Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

PORTA.

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14.4.5

INPUT THRESHOLD CONTROL

14.4 PORTB Registers

14.4.1 DATA REGISTER

The INLVLB register (Register 14-8) controls the input

voltage threshold for each of the available PORTB input

pins. A selection between the Schmitt Trigger CMOS or

the TTL Compatible thresholds is available. The input

threshold is important in determining the value of a read

of the PORTB register and also the level at which an

interrupt-on-change occurs, if that feature is enabled.

See Table 37-4 for more information on threshold

levels.

PORTB is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 14-10). Setting a TRISB bit (= 1) will make

the corresponding PORTB pin an input (i.e., disable the

output driver). Clearing a TRISB bit (= 0) will make the

corresponding PORTB pin an output (i.e., enables

output driver and puts the contents of the output latch

on the selected pin). Figure 14-1 shows how to initialize

PORTB.

Note:

Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

Reading the PORTB register (Register 14-9) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch (LATB).

active may inadvertently generate

a

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

The PORT data latch LATB (Register 14-11) holds the

output port data, and contains the latest value of a

LATB or PORTB write.

14.4.6

ANALOG CONTROL

The ANSELB register (Register 14-12) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

14.4.2

DIRECTION CONTROL

The TRISB register (Register 14-10) controls the

PORTB pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits

in the TRISB register are maintained set when using

them as analog inputs. I/O pins configured as analog

inputs always read ‘0’.

The state of the ANSELB bits has no effect on digital

output functions. A pin with its TRIS bit clear and its

ANSEL bit set will still operate as a digital output, but

the Input mode will be analog. This can cause

unexpected behavior when executing read-modify-

write instructions on the affected port.

14.4.3

OPEN-DRAIN CONTROL

The ODCONB register (Register 14-14) controls the

open-drain feature of the port. Open-drain operation is

independently selected for each pin. When an

ODCONB bit is set, the corresponding port output

becomes an open-drain driver capable of sinking

current only. When an ODCONB bit is cleared, the

corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

Note:

The ANSELB bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

14.4.7

WEAK PULL-UP CONTROL

The WPUB register (Register 14-5) controls the

individual weak pull-ups for each PORT pin.

Note:

It is not necessary to set open-drain

control when using the pin for I²C; the I²C

module controls the pin and makes the pin

open-drain.

14.4.8

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTB pin is multiplexed with other functions.

Each pin defaults to the PORT latch data after Reset.

Other output functions are selected with the peripheral

pin select logic or by enabling an analog output, such

as the DAC. See Section 15.0 “Peripheral Pin Select

(PPS) Module” for more information.

14.4.4

SLEW RATE CONTROL

The SLRCONB register (Register 14-15) controls the

slew rate option for each port pin. Slew rate control is

independently selectable for each port pin. When an

SLRCONB bit is set, the corresponding port pin drive is

slew rate limited. When an SLRCONB bit is cleared,

The corresponding port pin drive slews at the maximum

rate possible.

Analog input functions, such as ADC and comparator

inputs are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

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14.5 Register Definitions: PORTB

REGISTER 14-9: PORTB: PORTB REGISTER

R/W-x/u

RB7

R/W-x/u

RB6

R/W-x/u

RB5

R/W-x/u

RB4

R/W-x/u

RB3

R/W-x/u

RB2

R/W-x/u

RB1

R/W-x/u

RB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

RB<7:0>: PORTB I/O Value bits⁽¹⁾

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTB are actually written to corresponding LATB register. The actual I/O pin values are read

from the PORTB register.

REGISTER 14-10: TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB7

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

R/W-1/1

TRISB3

R/W-1/1

TRISB2

R/W-1/1

TRISB1

R/W-1/1

TRISB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TRISB<7:0>: PORTB Tri-State Control bit

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

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REGISTER 14-11: LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB7

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

R/W-x/u

LATB3

R/W-x/u

LATB2

R/W-x/u

LATB1

R/W-x/u

LATB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

LATB<7:0>: RB<7:0> Output Latch Value bits⁽¹⁾

Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register returns

actual I/O pin values.

REGISTER 14-12: ANSELB: PORTB ANALOG SELECT REGISTER

R/W-1/1

ANSB7

R/W-1/1

ANSB6

R/W-1/1

ANSB5

R/W-1/1

ANSB4

R/W-1/1

ANSB3

R/W-1/1

ANSB2

R/W-1/1

ANSB1

R/W-1/1

ANSB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ANSB<7:0>: Analog Select between Analog or Digital Function on pins RB<7:0>, respectively

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

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REGISTER 14-13: WPUB: WEAK PULL-UP PORTB REGISTER

R/W-0/0

WPUB7

R/W-0/0

WPUB6

R/W-0/0

WPUB5

R/W-0/0

WPUB4

R/W-0/0

WPUB3

R/W-0/0

WPUB2

R/W-0/0

WPUB1

R/W-0/0

WPUB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

WPUB<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

REGISTER 14-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER

R/W-0/0

ODCB7

R/W-0/0

ODCB6

R/W-0/0

ODCB5

R/W-0/0

ODCB4

R/W-0/0

ODCB3

R/W-0/0

ODCB2

R/W-0/0

ODCB1

R/W-0/0

ODCB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ODCB<7:0>: PORTB Open-Drain Enable bits

For RB<7:0> pins, respectively

1= Port pin operates as open-drain drive (sink current only)

0= Port pin operates as standard push-pull drive (source and sink current)

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REGISTER 14-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER

R/W-1/1

SLRB7

R/W-1/1

SLRB6

R/W-1/1

SLRB5

R/W-1/1

SLRB4

R/W-1/1

SLRB3

R/W-1/1

SLRB2

R/W-1/1

SLRB1

R/W-1/1

SLRB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SLRB<7:0>: PORTB Slew Rate Enable bits

For RB<7:0> pins, respectively

1= Port pin slew rate is limited

0= Port pin slews at maximum rate

REGISTER 14-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER

R/W-1/1

INLVLB7

R/W-1/1

INLVLB6

R/W-1/1

INLVLB5

R/W-1/1

INLVLB4

R/W-1/1

INLVLB3

R/W-1/1

INLVLB2

R/W-1/1

INLVLB1

R/W-1/1

INLVLB0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

INLVLB<7:0>: PORTB Input Level Select bits

For RB<7:0> pins, respectively

1= ST input used for PORT reads and interrupt-on-change

0= TTL input used for PORT reads and interrupt-on-change

TABLE 14-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTB

TRISB

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

181

182

183

184

TRISB7

LATB7

ANSB7

WPUB7

ODCB7

SLRB7

TRISB6

LATB6

ANSB6

WPUB6

ODCB6

SLRB6

TRISB5

LATB5

ANSB5

WPUB5

ODCB5

SLRB5

TRISB4

LATB4

ANSB4

WPUB4

ODCB4

SLRB4

TRISB3

LATB3

ANSB3

WPUB3

ODCB3

SLRB3

TRISB2

LATB2

ANSB2

WPUB2

ODCB2

SLRB2

TRISB1

LATB1

ANSB1

WPUB1

ODCB1

SLRB1

TRISB0

LATB0

ANSB0

WPUB0

ODCB0

SLRB0

LATB

ANSELB

WPUB

ODCONB

SLRCONB

INLVLB

INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0

Legend: x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by

PORTB.

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14.6.5

INPUT THRESHOLD CONTROL

14.6 PORTC Registers

14.6.1 DATA REGISTER

The INLVLC register (Register 14-24) controls the input

voltage threshold for each of the available PORTC

input pins. A selection between the Schmitt Trigger

CMOS or the TTL Compatible thresholds is available.

The input threshold is important in determining the

value of a read of the PORTC register and also the

level at which an interrupt-on-change occurs, if that

feature is enabled. See Table 37-4 for more information

on threshold levels.

PORTC is an 8-bit wide bidirectional port. The

corresponding data direction register is TRISC

(Register 14-18). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (= 0) will make the corresponding

PORTC pin an output (i.e., enable the output driver and

put the contents of the output latch on the selected pin).

Figure 14-1 shows how to initialize an I/O port.

Note:

Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

Reading the PORTC register (Register 14-17) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the PORT data latch (LATC).

active may inadvertently generate

a

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

The PORT data latch LATC (Register 14-19) holds the

output port data, and contains the latest value of a LATC

or PORTC write.

14.6.6

ANALOG CONTROL

The ANSELC register (Register 14-20) is used to

configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELC bit high will cause all

digital reads on the pin to be read as ‘0’ and allow

analog functions on the pin to operate correctly.

14.6.2

DIRECTION CONTROL

The TRISC register (Register 14-18) controls the

PORTC pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISC register are maintained set when using them

as analog inputs. I/O pins configured as analog inputs

always read ‘0’.

The state of the ANSELC bits has no effect on digital

output functions. A pin with TRIS clear and ANSELC set

will still operate as a digital output, but the Input mode

will be analog. This can cause unexpected behavior

when executing read-modify-write instructions on the

affected port.

14.6.3

OPEN-DRAIN CONTROL

The ODCONC register (Register 14-22) controls the

open-drain feature of the port. Open-drain operation is

independently selected for each pin. When an

ODCONC bit is set, the corresponding port output

becomes an open-drain driver capable of sinking

current only. When an ODCONC bit is cleared, the

corresponding port output pin is the standard push-pull

drive capable of sourcing and sinking current.

Note:

The ANSELC bits default to the Analog

mode after Reset. To use any pins as

digital general purpose or peripheral

inputs, the corresponding ANSEL bits

must be initialized to ‘0’ by user software.

14.6.7

WEAK PULL-UP CONTROL

The WPUC register (Register 14-21) controls the

individual weak pull-ups for each port pin.

Note:

It is not necessary to set open-drain

control when using the pin for I²C; the I²C

module controls the pin and makes the pin

open-drain.

14.6.8

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

Each pin defaults to the PORT latch data after Reset.

Other output functions are selected with the peripheral

pin select logic. See Section 15.0 “Peripheral Pin

Select (PPS) Module” for more information.

14.6.4

SLEW RATE CONTROL

The SLRCONC register (Register 14-23) controls the

slew rate option for each port pin. Slew rate control is

independently selectable for each port pin. When an

SLRCONC bit is set, the corresponding port pin drive is

slew rate limited. When an SLRCONC bit is cleared,

The corresponding port pin drive slews at the maximum

rate possible.

Analog input functions, such as ADC and comparator

inputs, are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

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14.7 Register Definitions: PORTC

REGISTER 14-17: PORTC: PORTC REGISTER

R/W-x/u

RC7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

(1)

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is > VIH

0= Port pin is < VIL

Note 1: Writes to PORTC are actually written to corresponding LATC register. The actual I/O pin values are read from

the PORTC register.

REGISTER 14-18: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7

R/W-1/1

TRISC6

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

REGISTER 14-19: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7

R/W-x/u

LATC6

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

(1)

bit 7-0

LATC<7:0>: PORTC Output Latch Value bits

Note 1: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register returns

actual I/O pin values.

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PIC16(L)F15354/55

REGISTER 14-20: ANSELC: PORTC ANALOG SELECT REGISTER

R/W-1/1

ANSC7

R/W-1/1

ANSC6

R/W-1/1

ANSC5

R/W-1/1

ANSC4

R/W-1/1

ANSC3

R/W-1/1

ANSC2

R/W-1/1

ANSC1

R/W-1/1

ANSC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ANSC<7:0>: Analog Select between Analog or Digital Function on Pins RC<7:0>, respectively⁽¹⁾

1= Analog input. Pin is assigned as analog input⁽¹⁾. Digital input buffer disabled.

0= Digital I/O. Pin is assigned to port or digital special function.

Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to

allow external control of the voltage on the pin.

REGISTER 14-21: WPUC: WEAK PULL-UP PORTC REGISTER

R/W-0/0

WPUC7

R/W-0/0

WPUC6

R/W-0/0

WPUC5

R/W-0/0

WPUC4

R/W-0/0

WPUC3

R/W-0/0

WPUC2

R/W-0/0

WPUC1

R/W-0/0

WPUC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

WPUC<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

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PIC16(L)F15354/55

REGISTER 14-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER

R/W-0/0

ODCC7

R/W-0/0

ODCC6

R/W-0/0

ODCC5

R/W-0/0

ODCC4

R/W-0/0

ODCC3

R/W-0/0

ODCC2

R/W-0/0

ODCC1

R/W-0/0

ODCC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ODCC<7:0>: PORTC Open-Drain Enable bits

For RC<7:0> pins, respectively

1= Port pin operates as open-drain drive (sink current only)

0= Port pin operates as standard push-pull drive (source and sink current)

REGISTER 14-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER

R/W-1/1

SLRC7

R/W-1/1

SLRC6

R/W-1/1

SLRC5

R/W-1/1

SLRC4

R/W-1/1

SLRC3

R/W-1/1

SLRC2

R/W-1/1

SLRC1

R/W-1/1

SLRC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SLRC<7:0>: PORTC Slew Rate Enable bits

For RC<7:0> pins, respectively

1= Port pin slew rate is limited

0= Port pin slews at maximum rate

REGISTER 14-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER

R/W-1/1

INLVLC7

R/W-1/1

INLVLC6

R/W-1/1

INLVLC5

R/W-1/1

INLVLC4

R/W-1/1

INLVLC3

R/W-1/1

INLVLC2

R/W-1/1

INLVLC1

R/W-1/1

INLVLC0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

INLVLC<7:0>: PORTC Input Level Select bits

For RC<7:0> pins, respectively

1= ST input used for PORT reads and interrupt-on-change

0= TTL input used for PORT reads and interrupt-on-change

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TABLE 14-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

186

187

188

TRISC

TRISC7

LATC7

TRISC6

LATC6

TRISC5

LATC5

TRISC4

LATC4

ANSC4

WPUC4

ODCC4

SLRC4

TRISC3

LATC3

ANSC3

WPUC3

ODCC3

SLRC3

TRISC2

LATC2

TRISC1

LATC1

TRISC0

LATC0

LATC

ANSELC

WPUC

ANSC7

WPUC7

ODCC7

SLRC7

INLVLC7

ANSC6

WPUC6

ODCC6

SLRC6

INLVLC6

ANSC5

WPUC5

ODCC5

SLRC5

INLVLC5

ANSC2

WPUC2

ODCC2

SLRC2

INLVLC2

ANSC1

WPUC1

ODCC1

SLRC1

INLVLC1

ANSC0

WPUC0

ODCC0

SLRC0

INLVLC0

ODCONC

SLRCONC

INLVLC

INLVLC4 INLVLC3

Legend: – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

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14.8.5

PORTE FUNCTIONS AND OUTPUT

PRIORITIES

14.8 PORTE Registers

14.8.1 DATA REGISTER

Each pin defaults to the PORT latch data after Reset.

Other output functions are selected with the peripheral

pin select logic. See Section 15.0 “Peripheral Pin

Select (PPS) Module” for more information.

PORTE is a single bit-bit wide port. The corresponding

data direction register is TRISE (Register 14-25).

Setting a TRISE bit (= 1) will make the corresponding

PORTE pin an input (i.e., disable the output driver).

Clearing a TRISE bit (= 0) will make the corresponding

PORTE pin an output (i.e., enables output driver and

puts the contents of the output latch on the selected

pin). Figure 14-1 shows how to initialize PORTE.

Analog input functions, such as ADC and comparator

inputs, are not shown in the peripheral pin select lists.

Digital output functions may continue to control the pin

when it is in Analog mode.

Reading the PORTE register (Register 14-25) reads

the status of the pins, whereas writing to it will write to

the PORT latch. All write operations are read-modify-

write operations. Therefore, a write to a port implies

that the port pins are read, this value is modified and

then written to the PORT data latch (LATE).

14.8.2

DIRECTION CONTROL

The TRISE register (Register 14-26) controls the

PORTE pin output drivers, even when they are being

used as analog inputs. The user should ensure the bits in

the TRISE register are maintained set when using them

as analog inputs. I/O pins configured as analog inputs

always read ‘0’.

Note:

The TRISE3 bit is a read-only bit and it

always reads a ‘1’.

14.8.3

INPUT THRESHOLD CONTROL

The INLVLE register (Register 14-28) controls the input

voltage threshold for each of the available PORTE

input pins. A selection between the Schmitt Trigger

CMOS or the TTL Compatible thresholds is available.

The input threshold is important in determining the

value of a read of the PORTE register and also the level

at which an interrupt-on-change occurs, if that feature

is enabled. See Table 37-4 for more information on

threshold levels.

Note:

Changing the input threshold selection

should be performed while all peripheral

modules are disabled. Changing the

threshold level during the time a module is

active may inadvertently generate

a

transition associated with an input pin,

regardless of the actual voltage level on

that pin.

14.8.4

WEAK PULL-UP CONTROL

The WPUE register (Register 14-27) controls the

individual weak pull-ups for each port pin.

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14.9 Register Definitions: PORTE

REGISTER 14-25: PORTE: PORTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-x/u

RE3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

RE<3>: PORTE Input Pin bit

1= Port pin is > VIH

0= Port pin is < VIL

bit 2-0

Unimplemented: Read as ‘0’

REGISTER 14-26: TRISE: PORTE TRI-STATE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-1

U-0

—

U-0

—

U-0

—

(1)

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

Unimplemented: Read as ‘1’

Unimplemented: Read as ‘0’

bit 2-0

Note 1: Unimplemented, read as ‘1’.

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REGISTER 14-27: WPUE: WEAK PULL-UP PORTE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1/1

WPUE3⁽¹⁾

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WPUE3: Weak Pull-up Register bit⁽¹⁾

1= Pull-up enabled

0= Pull-up disabled

bit 2-0

Unimplemented: Read as ‘0’

Note 1: If MCLRE = 1, the weak pull-up in RE3 is always enabled; bit WPUE3 is not affected.

2: The weak pull-up device is automatically disabled if the pin is configured as an output.

REGISTER 14-28: INLVLE: PORTE INPUT LEVEL CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1/1

INLVLE3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

Unimplemented: Read as ‘0’

INLVLE3: PORTE Input Level Select bits

For RE3 pin,

1= ST input used for PORT reads and interrupt-on-change

0= TTL input used for PORT reads and interrupt-on-change

bit 2-0

Unimplemented: Read as ‘0’

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TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Register

on Page

Name

PORTE

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

RE3

—

191

(1)

TRISE

—

WPUE

WPUE3

192

INLVLE

INLVLE3

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE.

Note 1: Unimplemented, read as ‘1’

TABLE 14-6: SUMMARY OF CONFIGURATION WORD WITH PORTE

Register

on Page

Name

Bits

Bit -/7

Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

STVREN PPS1WAY ZCDDIS

BORV

13:8

7:0

—

DEBUG

—

CONFIG2

77

BOREN <1:0>

LPBOREN

—

PWRTE

MCLRE

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTE.

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PIC16(L)F15354/55

15.0 PERIPHERAL PIN SELECT

(PPS) MODULE

The Peripheral Pin Select (PPS) module connects

peripheral inputs and outputs to the device I/O pins.

Only digital signals are included in the selections.

All analog inputs and outputs remain fixed to their

assigned pins. Input and output selections are

independent as shown in the simplified block diagram

Figure 15-1.

FIGURE 15-1:

SIMPLIFIED PPS BLOCK DIAGRAM

PPS Outputs

RA0PPS

PPS Inputs

abcPPS

RA0

Peripheral abc

RxyPPS

Rxy

Peripheral xyz

RE3PPS⁽¹⁾

RE3⁽¹⁾

xyzPPS

Note 1: RE3 is PPS input capable only (when MLCR is disabled).

15.1 PPS Inputs

15.2 PPS Outputs

Each peripheral has a PPS register with which the

inputs to the peripheral are selected. Inputs include the

device pins.

Each I/O pin has a PPS register with which the pin

output source is selected. With few exceptions, the port

TRIS control associated with that pin retains control

over the pin output driver. Peripherals that control the

pin output driver as part of the peripheral operation will

override the TRIS control as needed. These

peripherals are (See Section 15.3 “Bidirectional

Pins”):

Although every peripheral has its own PPS input

selection register, the selections are identical for every

peripheral as shown in Register 15-1.

Note:

The notation “xxx” in the register name is

a place holder for the peripheral identifier.

For example, CLC1PPS.

• EUSART (synchronous operation)

• MSSP (I²C)

Although every pin has its own PPS peripheral

selection register, the selections are identical for every

pin as shown in Register 15-2.

Note:

The notation “Rxy” is a place holder for the

pin port and bit identifiers. For example, x

and y for PORTA bit 0 would be A and 0,

respectively, resulting in the pin PPS

output selection register RA0PPS.

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PIC16(L)F15354/55

TABLE 15-1: PPS INPUT SIGNAL ROUTING OPTIONS (PIC16(L)F15354/55)

Remappable to Pins of PORTx

PIC16(L)F15354/55

Default

Location at

POR

INPUT SIGNAL

NAME

Input Register

Name

Reset Value

(xxxPPS<5:0>)

PORTA

PORTB

PORTC

INT

INTPPS

RB0

RA4

RC0

RB5

RC3

RC2

RC1

RB0

RA0

RA1

RB6

RB7

RB4

RC3

RC4

RA5

RB1

RB2

RB0

RC7

RC6

RB7

RB6

01000

00100

10000

01101

10011

10010

10001

01000

00000

00001

01110

01111

01100

10011

10100

00101

01001

01010

01000

10111

10110

01111

01110



T0CKI

T0CKIPPS

T1CKI

T1CKIPSS



T1G

T1GPPS



T2IN

T2INPPS



CCP1

CCP1PPS



CCP2

CCP2PPS

CWG1IN

CLCIN0

CLCIN1

CLCIN2

CLCIN3

ADACT

SCK1/SCL1

SDI1/SDA1

SS1

CWG1PPS

CLCIN0PPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

ADACTPPS

SSP1CLKPPS

SSP1DATPPS

SSP1SS1PPS

SSP2CLKPPS

SSP2DATPPS

SSP2SSPPS

RX1DTPPS

TX1CKPPS

RX2DTPPS

TX2CKPPS



SCK2/SCL2

SDI2/SDA2

SS2



RX1/DT1

CK1

RX2/DT2

CK2

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TABLE 15-2: PPS INPUT REGISTER

VALUES

Desired Input Pin

Value to Write to Register

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RB0

RB1

RB2

RB3

RB4

RB5

RB6

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

Note 1: Only a few of the values in this column are

valid for any given signal. For example,

since the INT signal can only be mapped

to PORTA or PORTB pins, only the regis-

ter values 0x00-0x0F (corresponding to

RA<7:0> and RB<7:0>) are valid values

to write to the INTPPS register.

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15.3 Bidirectional Pins

15.5 PPS Permanent Lock

PPS selections for peripherals with bidirectional

signals on a single pin must be made so that the PPS

input and PPS output select the same pin. Peripherals

that have bidirectional signals include:

The PPS can be permanently locked by setting the

PPS1WAY Configuration bit. When this bit is set, the

PPSLOCKED bit can only be cleared and set one time

after a device Reset. This allows for clearing the

PPSLOCKED bit so that the input and output selections

can be made during initialization. When the

PPSLOCKED bit is set after all selections have been

made, it will remain set and cannot be cleared until after

the next device Reset event.

• EUSART (synchronous operation)

• MSSP (I²C)

Note:

The I²C SCLx and SDAx functions can be

remapped through PPS. However, only

the RB1, RB2, RC3 and RC4 pins have

the I²C and SMBus specific input buffers

implemented (I²C mode disables INLVL

and sets thresholds that are specific for

I²C). If the SCLx or SDAx functions are

mapped to some other pin (other than

RB1, RB2, RC3 or RC4), the general

purpose TTL or ST input buffers (as

configured based on INLVL register

setting) will be used instead. In most

applications, it is therefore recommended

only to map the SCLx and SDAx pin

functions to the RB1, RB2, RC3 or RC4

pins.

15.6 Operation During Sleep

PPS input and output selections are unaffected by Sleep.

15.7 Effects of a Reset

A device Power-on-Reset (POR) clears all PPS input

and output selections to their default values (Permanent

Lock Removed). All other Resets leave the selections

unchanged. Default input selections are shown in

Table 15-1.

15.4 PPS Lock

The PPS includes a mode in which all input and output

selections can be locked to prevent inadvertent

changes. PPS selections are locked by setting the

PPSLOCKED bit of the PPSLOCK register. Setting and

clearing this bit requires a special sequence as an extra

precaution against inadvertent changes. Examples of

setting and clearing the PPSLOCKED bit are shown in

Example 15-1.

EXAMPLE 15-1:

PPS LOCK/UNLOCK

SEQUENCE

; suspend interrupts

BCF INTCON,GIE

BANKSELPPSLOCK

; required sequence, next 5 instructions

;

; set bank

MOVLW

MOVWF

MOVLW

MOVWF

0x55

PPSLOCK

0xAA

PPSLOCK

; Set PPSLOCKED bit to disable writes or

; Clear PPSLOCKED bit to enable writes

BSF

; restore interrupts

BSF INTCON,GIE

PPSLOCK,PPSLOCKED

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PIC16(L)F15354/55

TABLE 15-3: PPS OUTPUT SIGNAL

ROUTING OPTIONS

(PIC16(L)F15354/55)

Remappable to Pins of

PORTx

Output

Signal

Name

RxyPPS

Register

Value

PIC16(L)F15354/55

PORTA PORTB PORTC

CLKR

0x1B

0x1A

0x19

0x18

0x17

0x16

0x15

0x14

0x13

0x12

0x11

0x10

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01



NCO1OUT

TMR0



SDO2/SDA2

SCK2/SCL2

SDO1/SDA1

SCK1/SCL1

C2OUT



C1OUT

DT2



TX2/CK2

DT1

TX1/CK1

PWM6OUT

PWM5OUT

PWM4OUT

PWM3OUT

CCP2



CCP1

CWG1D

CWG1C

CWG1B

CWG1A

CLC4OUT

CLC3OUT

CLC2OUT

CLC1OUT



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PIC16(L)F15354/55

15.8 Register Definitions: PPS Input Selection

REGISTER 15-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION⁽¹⁾

U-0

—

U-0

—

R/W-q/u

R/W/q/u

R/W-q/u

xxxPPS<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = value depends on peripheral

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

xxxPPS<5:0>: Peripheral xxx Input Selection bits

See Table 15-1.

Note 1: The “xxx” in the register name “xxxPPS” represents the input signal function name, such as “INT”,

“T0CKI”, “RX”, etc. This register summary shown here is only a prototype of the array of actual registers,

as each input function has its own dedicated SFR (ex: INTPPS, T0CKIPPS, RXPPS, etc.).

2: Each specific input signal may only be mapped to a subset of these I/O pins, as shown in Table 15-1.

Attempting to map an input signal to a non-supported I/O pin will result in undefined behavior. For

example, the “INT” signal map be mapped to any PORTA or PORTB pin. Therefore, the INTPPS register

may be written with values from 0x00-0x0F (corresponding to RA0-RB7). Attempting to write 0x10 or

higher to the INTPPS register is not supported and will result in undefined behavior.

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REGISTER 15-2: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER

U-0

—

U-0

—

U-0

—

R/W-0/u

bit 0

RxyPPS<4:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

RxyPPS<4:0>: Pin Rxy Output Source Selection bits

See Table 15-3.

REGISTER 15-3: PPSLOCK: PPS LOCK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

PPSLOCKED

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-1

bit 0

Unimplemented: Read as ‘0’

PPSLOCKED: PPS Locked bit

1= PPS is locked. PPS selections can not be changed.

0= PPS is not locked. PPS selections can be changed.

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TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PPSLOCK

INTPPS

—

PPSLOCKED

200

199

200

INTPPS<5:0>

T0CKIPPS<5:0>

T1CKIPPS<5:0>

T1GPPS<5:0>

T0CKIPPS

T1CKIPPS

T1GPPS

T2INPPS

T2INPPS<5:0>

CCP1PPS<5:0>

CCP2PPS<5:0>

CWG1PPS<5:0>

SSP1CLKPPS<5:0>

SSP1DATPPS<5:0>

SSP1SSPPS<5:0>

SSP2CLKPPS<5:0>

SSP2DATPPS<5:0>

SSP2SSPPS<5:0>

RX1DTPPS<5:0>

TX1CKPPS<5:0>

CLCIN0PPS<5:0>

CLCIN1PPS<5:0>

CLCIN2PPS<5:0>

CLCIN3PPS<5:0>

RX2DTPPS<5:0>

TX2CKPPS<5:0>

ADACTPPS<5:0>

RA0PPS<4:0>

CCP1PPS

CCP2PPS

CWG1PPS

SSP1CLKPPS

SSP1DATPPS

SSP1SSPPS

SSP2CLKPPS

SSP2DATPPS

SSP2SSPPS

RX1DTPPS

TX1CKPPS

CLCIN0PPS

CLCIN1PPS

CLCIN2PPS

CLCIN3PPS

RX2DTPPS

TX2CKPPS

ADACTPPS

RA0PPS

—

RA1PPS

RA1PPS<4:0>

RA2PPS

RA2PPS<4:0>

RA3PPS

RA3PPS<4:0>

RA4PPS

RA4PPS<4:0>

RA5PPS

RA5PPS<4:0>

RA6PPS

RA6PPS<4:0>

RA7PPS

RA7PPS<4:0>

RB0PPS

RB0PPS<4:0>

RB1PPS

RB1PPS<4:0>

RB2PPS

RB2PPS<4:0>

RB3PPS

RB3PPS<4:0>

RB4PPS

RB4PPS<4:0>

RB5PPS

RB5PPS<4:0>

RB6PPS

RB6PPS<4:0>

RB7PPS

RB7PPS<4:0>

RC0PPS

RC0PPS<4:0>

RC1PPS<4:0>

RC1PPS

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.

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TABLE 15-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE (CONTINUED)

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RC2PPS

—

RC2PPS<4:0>

RC3PPS<4:0>

RC4PPS<4:0>

RC5PPS<4:0>

RC6PPS<4:0>

RC7PPS<4:0>

200

RC3PPS

RC4PPS

RC5PPS

RC6PPS

RC7PPS

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module.

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PIC16(L)F15354/55

16.2 Enabling a module

16.0 PERIPHERAL MODULE

DISABLE

When the register bit is cleared, the module is re-

enabled and will be in its Reset state; SFR data will

reflect the POR Reset values.

The PIC16(L)F15354/55 provides the ability to disable

selected modules, placing them into the lowest

possible Power mode.

Depending on the module, it may take up to one full

instruction cycle for the module to become active.

There should be no interaction with the module

(e.g., writing to registers) for at least one instruction

after it has been re-enabled.

For legacy reasons, all modules are ON by default

following any Reset.

16.1 Disabling a Module

Disabling a module has the following effects:

16.3 Disabling a Module

• All clock and control inputs to the module are

suspended; there are no logic transitions, and the

module will not function.

When a module is disabled, all the associated PPS

selection registers (Registers xxxPPS Register 15-1,

15-2, and 15-3), are also disabled.

• The module is held in Reset:

- Writing to SFRs is disabled

- Reads return 00h

16.4 System Clock Disable

Setting SYSCMD (PMD0, Register 16-1) disables the

system clock (FOSC) distribution network to the

peripherals. Not all peripherals make use of SYSCLK,

so not all peripherals are affected. Refer to the specific

peripheral description to see if it will be affected by this

bit.

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16.5 Register Definitions: Peripheral Module Disable Control

REGISTER 16-1: PMD0: PMD CONTROL REGISTER 0

R/W-0/0

FVRMD

U-0

—

U-0

—

U-0

—

R/W-0/0

NVMMD

R/W-0/0

IOCMD

SYSCMD

CLKRMD

7

0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

‘1’ = Bit is set

bit 7

bit 6

SYSCMD: Disable Peripheral System Clock Network bit

See description in Section 16.4 “System Clock Disable”.

1= System clock network disabled (a.k.a. FOSC)

0= System clock network enabled

FVRMD: Disable Fixed Voltage Reference (FVR) bit

1= FVR module disabled

0= FVR module enabled

bit 5-3

bit 2

Unimplemented: Read as ‘0’

NVMMD: NVM Module Disable bit⁽¹⁾

1= User memory reading and writing is disabled; NVMCON registers cannot be written; FSR access

to these locations returns zero.

0= NVM module enabled

bit 1

bit 0

CLKRMD: Disable Clock Reference CLKR bit

1= CLKR module disabled

0= CLKR module enabled

IOCMD: Disable Interrupt-on-Change bit, All Ports

1= IOC module(s) disabled

0= IOC module(s) enabled

Note 1: When enabling NVM, a delay of up to 1 µs may be required before accessing data.

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REGISTER 16-2: PMD1: PMD CONTROL REGISTER 1

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

NCO1MD

TMR2MD

TMR1MD

TMR0MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

NCO1MD: Disable Numerically Control Oscillator bit

1= NCO1 module disabled

0= NCO1 module enabled

bit 6-3

bit 2

Unimplemented: Read as ‘0’

TMR2MD: Disable Timer TMR2 bit

1= Timer2 module disabled

0= Timer2 module enabled

bit 1

bit 0

TMR1MD: Disable Timer TMR1 bit

1= Timer1 module disabled

0= Timer1 module enabled

TMR0MD: Disable Timer TMR0 bit

1= Timer0 module disabled

0= Timer0 module enabled

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REGISTER 16-3: PMD2: PMD CONTROL REGISTER 2

U-0

—

R/W-0/0

ADCMD

U-0

—

U-0

—

R/W-0/0

ZCDMD

DAC1MD

CMP2MD

CMP1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

Unimplemented: Read as ‘0’

DAC1MD: Disable DAC1 bit

1= DAC module disabled

0= DAC module enabled

bit 5

ADCMD: Disable ADC bit

1= ADC module disabled

0= ADC module enabled

bit 4-3

bit 2

Unimplemented: Read as ‘0’

CMP2MD: Disable Comparator C2 bit

1= C2 module disabled

0= C2 module enabled

bit 1

bit 0

CMP1MD: Disable Comparator C1 bit

1= C1 module disabled

0= C1 module enabled

ZCDMD: Disable ZCD bit

1= ZCD module disabled

0= ZCD module enabled

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PIC16(L)F15354/55

REGISTER 16-4: PMD3: PMD CONTROL REGISTER 3

U-0

—

U-0

—

R/W-0/0

PWM6MD

PWM5MD

PWM4MD

PWM3MD

CCP2MD

CCP1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5

Unimplemented: Read as ‘0’

PWM6MD: Disable Pulse-Width Modulator PWM6 bit

1= PWM6 module disabled

0= PWM6 module enabled

bit 4

bit 3

bit 2

bit 1

bit 0

PWM5MD: Disable Pulse-Width Modulator PWM5 bit

1= PWM5 module disabled

0= PWM5 module enabled

PWM4MD: Disable Pulse-Width Modulator PWM4 bit

1= PWM4 module disabled

0= PWM4 module enabled

PWM3MD: Disable Pulse-Width Modulator PWM3 bit

1= PWM3 module disabled

0= PWM3 module enabled

CCP2MD: Disable CCP2 bit

1= CCP2 module disabled

0= CCP2 module enabled

CCP1MD: Disable CCP1 bit

1= CCP1 module disabled

0= CCP1 module enabled

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PIC16(L)F15354/55

REGISTER 16-5: PMD4: PMD CONTROL REGISTER 4

R/W-0/0

U-0

—

U-0

—

U-0

—

R/W-0/0

UART2MD

UART1MD

MSSP2MD

MSSP1MD

CWG1MD

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

UART2MD: Disable EUSART2 bit

1= EUSART2 module disabled

0= EUSART2 module enabled

UART1MD: Disable EUSART1 bit

1= EUSART1 module disabled

0= EUSART1 module enabled

MSSP2MD: Disable MSSP2 bit

1= MSSP2 module disabled

0= MSSP2 module enabled

MSSP1MD: Disable MSSP1 bit

1= MSSP1 module disabled

0= MSSP1 module enabled

bit 3-1

bit 0

Unimplemented: Read as ‘0’

CWG1MD: Disable CWG1 bit

1= CWG1 module disabled

0= CWG1 module enabled

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REGISTER 16-6: PMD5 – PMD CONTROL REGISTER 5

U-0

—

U-0

—

U-0

—

R/W-0/0

U-0

—

CLC4MD

CLC3MD

CLC2MD

CLC1MD

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

CLC4MD: Disable CLC4 bit

1= CLC4 module disabled

0= CLC4 module enabled

bit 3

bit 2

bit 1

bit 0

CLC3MD: Disable CLC3 bit

1= CLC3 module disabled

0= CLC3 module enabled

CLC2MD: Disable CLC2 bit

1= CLC2 module disabled

0= CLC2 module enabled

CLC1MD: Disable CLC1 bit

1= CLC1 module disabled

0= CLC1 module enabled

Unimplemented: Read as ‘0’

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TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE PMD MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PMD0

SYSCMD

NCO1MD

—

FVRMD

—

NVMMD

CLKRMD

IOCMD

204

205

206

207

208

209

PMD1

PMD2

PMD3

PMD4

PMD5

TMR2MD TMR1MD TMR0MD

DAC1MD

—

ADCMD

CMP2MD CMP1MD

ZCDMD

CCP1MD

CWG1MD

—

PWM6MD PWM5MD PWM4MD PWM3MD CCP2MD

UART2MD UART1MD MSSP2MD MSSP1MD

CLC4MD

—

CLC3MD

CLC2MD

CLC1MD

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the PMD module.

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17.3 Interrupt Flags

17.0 INTERRUPT-ON-CHANGE

The bits located in the IOCxF registers are status flags

that correspond to the interrupt-on-change pins of each

port. If an expected edge is detected on an appropriately

enabled pin, then the status flag for that pin will be set,

and an interrupt will be generated if the IOCIE bit is set.

The IOCIF bit of the PIR0 register reflects the status of

all IOCxF bits.

All pins on ports A, B and C and lower four bits of PORTE

can be configured to operate as Interrupt-on-Change

(IOC) pins. An interrupt can be generated by detecting a

signal that has either a rising edge or a falling edge. Any

individual pin, or combination of pins, can be configured

to generate an interrupt. The interrupt-on-change

module has the following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

17.3.1

CLEARING INTERRUPT FLAGS

The individual status flags, (IOCxF register bits), can be

cleared by resetting them to zero. If another edge is

detected during this clearing operation, the associated

status flag will be set at the end of the sequence,

regardless of the value actually being written.

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 17-1 is a block diagram of the IOC module.

17.1 Enabling the Module

In order to ensure that no detected edge is lost while

clearing flags, only AND operations masking out known

changed bits should be performed. The following

sequence is an example of what should be performed.

To allow individual pins to generate an interrupt, the

IOCIE bit of the PIE0 register must be set. If the IOCIE

bit is disabled, the edge detection on the pin will still

occur, but an interrupt will not be generated.

EXAMPLE 17-1:

CLEARING INTERRUPT

FLAGS

17.2 Individual Pin Configuration

(PORTA EXAMPLE)

For each pin, a rising edge detector and a falling edge

detector are present. To enable a pin to detect a rising

edge, the associated bit of the IOCxP register is set. To

enable a pin to detect a falling edge, the associated bit

of the IOCxN register is set.

MOVLW0xff

XORWFIOCAF, W

ANDWFIOCAF, F

17.4 Operation in Sleep

A pin can be configured to detect rising and falling

edges simultaneously by setting the associated bits in

both of the IOCxP and IOCxN registers.

The interrupt-on-change interrupt event will wake the

device from Sleep mode, if the IOCIE bit is set.

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FIGURE 17-1:

INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTB EXAMPLE)

Rev. 10-000037C

9/14/2016

D

Q

IOCBNx

R

edge

detect

RBx

S

data bus =

0 or 1

to data bus

IOCBFx

D

Q

D

Q

IOCBPx

write IOCBFx

R

IOCIE

IOC interrupt

to CPU core

RESET

from all other

IOCnFx individual

pin detectors

Note 1: See Table 8-1 for BOR Active Conditions.

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17.5 Register Definitions: Interrupt-on-Change Control

REGISTER 17-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER

R/W-0/0

IOCAP7

R/W-0/0

IOCAP6

R/W-0/0

IOCAP5

R/W-0/0

IOCAP4

R/W-0/0

IOCAP3

R/W-0/0

IOCAP2

R/W-0/0

IOCAP1

R/W-0/0

IOCAP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCAP<7:0>: Interrupt-on-Change PORTA Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive-going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 17-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER

R/W-0/0

IOCAN7

R/W-0/0

IOCAN6

R/W-0/0

IOCAN5

R/W-0/0

IOCAN4

R/W-0/0

IOCAN3

R/W-0/0

IOCAN2

R/W-0/0

IOCAN1

R/W-0/0

IOCAN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCAN<7:0>: Interrupt-on-Change PORTA Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative-going edge. IOCAFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

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REGISTER 17-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCAF7

bit 7

IOCAF6

IOCAF5

IOCAF4

IOCAF3

IOCAF2

IOCAF1

IOCAF0

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-0

IOCAF<7:0>: Interrupt-on-Change PORTA Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCAPx = 1and a rising edge was detected on RAx, or when IOCANx = 1and a falling

edge was detected on RAx.

0= No change was detected, or the user cleared the detected change.

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REGISTER 17-4: IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER

R/W-0/0

IOCBP7

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

R/W-0/0

IOCBP3

R/W-0/0

IOCBP2

R/W-0/0

IOCBP1

R/W-0/0

IOCBP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBP<7:0>: Interrupt-on-Change PORTB Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive-going edge. IOCBFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

REGISTER 17-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

R/W-0/0

IOCBN3

R/W-0/0

IOCBN2

R/W-0/0

IOCBN1

R/W-0/0

IOCBN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCBN<7:0>: Interrupt-on-Change PORTB Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative-going edge. IOCBFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin.

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REGISTER 17-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCBF7

bit 7

IOCBF6

IOCBF5

IOCBF4

IOCBF3

IOCBF2

IOCBF1

IOCBF0

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-0

IOCBF<7:0>: Interrupt-on-Change PORTB Flag bits

1= An enabled change was detected on the associated pin.

Set when IOCBPx = 1and a rising edge was detected on RBx, or when IOCBNx = 1and a falling

edge was detected on RBx.

0= No change was detected, or the user cleared the detected change.

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REGISTER 17-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER

R/W-0/0

IOCCP7

R/W-0/0

IOCCP6

R/W-0/0

IOCCP5

R/W-0/0

IOCCP4

R/W-0/0

IOCCP3

R/W-0/0

IOCCP2

R/W-0/0

IOCCP1

R/W-0/0

IOCCP0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin

REGISTER 17-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER

R/W-0/0

IOCCN7

R/W-0/0

IOCCN6

R/W-0/0

IOCCN5

R/W-0/0

IOCCN4

R/W-0/0

IOCCN3

R/W-0/0

IOCCN2

R/W-0/0

IOCCN1

R/W-0/0

IOCCN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits

1= Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin

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REGISTER 17-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCCF7

bit 7

IOCCF6

IOCCF5

IOCCF4

IOCCF3

IOCCF2

IOCCF1

IOCCF0

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-0

IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits

1= An enabled change was detected on the associated pin

Set when IOCCPx = 1and a rising edge was detected on RCx, or when IOCCNx = 1and a falling

edge was detected on RCx.

0= No change was detected, or the user cleared the detected change

REGISTER 17-10: IOCEP: INTERRUPT-ON-CHANGE PORTE POSITIVE EDGE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

IOCEP3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-4

bit 3

Unimplemented: Read as ‘0’

IOCEP3: Interrupt-on-Change PORTE Positive Edge Enable bit

1= Interrupt-on-Change enabled on the pin for a positive-going edge. IOCCFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin

bit 2-0

Unimplemented: Read as ‘0’

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REGISTER 17-11: IOCEN: INTERRUPT-ON-CHANGE PORTE NEGATIVE EDGE REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

IOCEN3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-4

bit 3

Unimplemented: Read as ‘0’

IOCEN3: Interrupt-on-Change PORTE Negative Edge Enable bit

1= Interrupt-on-Change enabled on the pin for a negative-going edge. IOCCFx bit and IOCIF flag will

be set upon detecting an edge.

0= Interrupt-on-Change disabled for the associated pin

bit 2-0

Unimplemented: Read as ‘0’

REGISTER 17-12: IOCEF: INTERRUPT-ON-CHANGE PORTE FLAG REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W/HS-0/0

IOCEF3

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

bit 7-4

bit 3

Unimplemented: Read as ‘0’

IOCEF3: Interrupt-on-Change PORTE Flag bit

1= An enabled change was detected on the associated pin

Set when IOCCPx = 1and a rising edge was detected on RCx, or when IOCCNx = 1and a falling

edge was detected on RCx.

0= No change was detected, or the user cleared the detected change

bit 2-0

Unimplemented: Read as ‘0’

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TABLE 17-1:

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE0

GIE

—

PEIE

—

INTEDG

INTE

121

122

213

214

215

216

217

218

219

TMR0IE

IOCAP5

IOCAN5

IOCAF5

IOCBP5

IOCBN5

IOCBF5

IOCCP5

IOCCN5

IOCCF5

—

IOCIE

IOCAP4

IOCAN4

IOCAF4

IOCBP4

IOCBN4

IOCBF4

IOCCP4

IOCCN4

IOCCF4

—

IOCAP

IOCAN

IOCAF

IOCBP

IOCBN

IOCBF

IOCCP

IOCCN

IOCCF

IOCEP

IOCEN

IOCEF

IOCAP7

IOCAN7

IOCAF7

IOCBP7

IOCBN7

IOCBF7

IOCCP7

IOCCN7

IOCCF7

—

IOCAP6

IOCAN6

IOCAF6

IOCBP6

IOCBN6

IOCBF6

IOCCP6

IOCCN6

IOCCF6

—

IOCAP3

IOCAN3

IOCAF3

IOCBP3

IOCBN3

IOCBF3

IOCCP3

IOCCN3

IOCCF3

IOCEP3

IOCEN3

IOCEF3

IOCAP2

IOCAN2

IOCAF2

IOCBP2

IOCBN2

IOCBF2

IOCCP2

IOCCN2

IOCCF2

—

IOCAP1

IOCAN1

IOCAF1

IOCBP1

IOCBN1

IOCBF1

IOCCP1

IOCCN1

IOCCF1

—

IOCAP0

IOCAN0

IOCAF0

IOCBP0

IOCBN0

IOCBF0

IOCCP0

IOCCN0

IOCCF0

—

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change.

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18.1 Independent Gain Amplifiers

18.0 FIXED VOLTAGE REFERENCE

(FVR)

The output of the FVR, which is connected to the ADC,

comparators, and DAC, is routed through two

independent programmable gain amplifiers. Each

amplifier can be programmed for a gain of 1x, 2x or 4x,

to produce the three possible voltage levels.

The Fixed Voltage Reference, or FVR, is a stable

voltage reference, independent of VDD, with 1.024V,

2.048V or 4.096V selectable output levels. The output

of the FVR can be configured to supply a reference

voltage to the following:

The ADFVR<1:0> bits of the FVRCON register are

used to enable and configure the gain amplifier settings

for the reference supplied to the ADC module.

• ADC input channel

• ADC positive reference

Reference

Section 20.0

“Analog-to-Digital

• Comparator positive and negative input

• Digital-to-Analog Converter (DAC)

Converter (ADC) Module” for additional information.

The CDAFVR<1:0> bits of the FVRCON register are used

to enable and configure the gain amplifier settings for the

reference supplied to the DAC and comparator module.

Reference Section 21.0 “5-Bit Digital-to-Analog

Converter (DAC1) Module” and Section 23.0

“Comparator Module” for additional information.

The FVR can be enabled by setting the FVREN bit of

the FVRCON register.

Note:

Fixed Voltage Reference output cannot

exceed VDD.

18.2 FVR Stabilization Period

When the Fixed Voltage Reference module is enabled,

it requires time for the reference and amplifier circuits

to stabilize.

FVRRDY is an indicator of the reference being ready.

In the case of an LF device, or a device on which the

BOR is enabled in the Configuration Word settings,

then the FVRRDY bit will be high prior to setting

FVREN as those module require the reference voltage.

FIGURE 18-1:

VOLTAGE REFERENCE BLOCK DIAGRAM

Rev. 10-000053D

9/15/2016

2

ADFVR<1:0>

1x

2x

4x

ADC FVR Buffer

CDAFVR<1:0>

1x

2x

4x

Comparator and DAC

FVR Buffer

FVREN

Voltageꢀ

Reference

FVRRDY (Note 1)

Note 1: FVRRDY is always ‘1’.

2: Any peripheral requiring the Fixed Reference (See Table 18-1).

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18.3 Register Definitions: FVR Control

REGISTER 18-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R/W-0/0

FVREN

R-q/q

FVRRDY⁽¹⁾

R/W-0/0

TSEN⁽³⁾

R/W-0/0

TSRNG⁽³⁾

R/W-0/0

CDAFVR<1:0>

ADFVR<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3-2

FVREN: Fixed Voltage Reference Enable bit

1= Fixed Voltage Reference is enabled

0= Fixed Voltage Reference is disabled

FVRRDY: Fixed Voltage Reference Ready Flag bit⁽¹⁾

1= Fixed Voltage Reference output is ready for use

0= Fixed Voltage Reference output is not ready or not enabled

TSEN: Temperature Indicator Enable bit⁽³⁾

1= Temperature Indicator is enabled

0= Temperature Indicator is disabled

TSRNG: Temperature Indicator Range Selection bit⁽³⁾

1= Temperature in High Range VOUT = 3VT

0= Temperature in Low Range VOUT = 2VT

CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits

11=Comparator FVR Buffer Gain is 4x, (4.096V)⁽²⁾

10=Comparator FVR Buffer Gain is 2x, (2.048V)⁽²⁾

01=Comparator FVR Buffer Gain is 1x, (1.024V)

00=Comparator FVR Buffer is off

bit 1-0

ADFVR<1:0>: ADC FVR Buffer Gain Selection bit

11=ADC FVR Buffer Gain is 4x, (4.096V)⁽²⁾

10=ADC FVR Buffer Gain is 2x, (2.048V)⁽²⁾

01=ADC FVR Buffer Gain is 1x, (1.024V)

00=ADC FVR Buffer is off

Note 1: FVRRDY is always ‘1’.

2: Fixed Voltage Reference output cannot exceed VDD.

3: See Section 19.0 “Temperature Indicator Module” for additional information.

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TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FVRCON

ADCON0

ADCON1

DAC1CON0

Legend:

FVREN

FVRRDY

TSEN

TSRNG

CDAFVR<1:0>

ADFVR<1:0>

222

234

235

243

CHS<5:0>

ADCS<2:0>

DAC1OE1 DAC1OE2

GO/DONE

ADON

ADFM

—

ADPREF<1:0>

DAC1EN

—

DAC1PSS<1:0>

—

DAC1NSS

– = unimplemented locations read as ‘0’. Shaded cells are not used with the Fixed Voltage Reference.

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19.1.1

TEMPERATURE INDICATOR

RANGE

19.0 TEMPERATURE INDICATOR

MODULE

The temperature indicator circuit operates in either high

or low range. The high range, selected by setting the

TSRNG bit of the FVRCON register, provides a wider

output voltage. This provides more resolution over the

temperature range. High range requires a higher-bias

voltage to operate and thus, a higher VDD is needed.

The low range is selected by clearing the TSRNG bit of

the FVRCON register. The low range generates a lower

sensor voltage and thus, a lower VDD voltage is needed

to operate the circuit.

This family of devices is equipped with a temperature

circuit designed to measure the operating temperature

of the silicon die.

The circuit’s range of operating temperature falls

between -40°C and +125°C. A one-point calibration

allows the circuit to indicate a temperature closely

surrounding that point. A two-point calibration allows

the circuit to sense the entire range of temperature

more accurately.

The output voltage of the sensor is the highest value at

-40°C and the lowest value at +125°C.

19.1 Module Operation

The temperature indicator module consists of a

temperature-sensing circuit that provides a voltage to

the device ADC. The analog voltage output, VMEAS,

varies inversely to the device temperature. The output of

the temperature indicator is referred to as VMEAS.

• High Range: The High range is used in applica-

tions with the reference for the ADC,

VREF = 2.048V.Thisrangemaynotbesuitablefor

battery-powered applications. The ADC reading

(in counts) at 90°C for the high range setting is

stored in the DIA Table (Table 6-1) as parameter

TSHR2.

Figure 19-1 shows a simplified block diagram of the

temperature indicator module.

• Low Range: This mode is useful in applications in

which the VDD is too low for high-range operation.

The VDD in this mode can be as low as 1.8V. VDD

must, however, be at least 0.5V higher than the

maximum sensor voltage depending on the

expected low operating temperature. The ADC

reading (in counts) at 90°C for the Low range set-

ting is stored in the DIA Table (Table 6-1) as

parameter TSLR2.

FIGURE 19-1:

TEMPERATURE

INDICATOR MODULE

BLOCK DIAGRAM

5HYꢀꢁꢂꢃꢄꢃꢃꢃꢃꢅꢆ'

ꢂꢂꢇꢂꢈꢇꢉꢃꢂꢊ

9''

19.1.2

MINIMUM OPERATING VDD

7651*

76(1

9_0($6

7HPSHUDWXUHꢁ,QGLFDWRUꢁ

When the temperature circuit is operated in low range,

the device may be operated at any operating voltage

that is within specifications. When the temperature

circuit is operated in high range, the device operating

voltage, VDD, must be high enough to ensure that the

temperature circuit is correctly biased.

7Rꢁ$'&

0RGXOH

*1'

Table 19-1 shows the recommended minimum VDD vs.

Range setting.

The output of the circuit is measured using the internal

Analog-to-Digital Converter. A channel is reserved for

the temperature circuit output. Refer to Section 20.0

“Analog-to-Digital Converter (ADC) Module” for

detailed information.

TABLE 19-1: RECOMMENDED VDD vs.

RANGE

Min.VDD, TSRNG = 1

Min. VDD, TSRNG = 0

(High Range)

(Low Range)

The ON/OFF bit for the module is located in the

FVRCON register. See Section 18.0 “Fixed Voltage

Reference (FVR)” for more information. The circuit is

enabled by setting the TSEN bit of the FVRCON

register. When the module is disabled, the circuit draws

no current.

 2.5

 1.8

The circuit operates in either High or Low range. Refer

to Section 19.1.1 “Temperature Indicator Range” for

more details on the range settings.

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19.2 Temperature Calculation

Note 1: It is recommended to take the average of

ten measurements of ADCmeas to

reduce noise and improve accuracy.

This section describes the steps involved in calculating

the die temperature, TMEAS:

1. Obtain the ADC count value of the measured

analog voltage: The analog output voltage,

VMEAS is converted to a digital count value by

the Analog to Digital Converter (ADC) and is

referred to as ADCMEAS.

2: Refer to Section 37.0, Electrical Specifi-

cations for FVR reference voltage accu-

racy.

19.2.1

19.2.1.1

CALIBRATION

2. Obtain the ADC count value, ADCDIA at 90

degrees, in the DIA table (Table 6-1). This

parameter is TSLR2 for the low range setting or

TSHR2 for the high range setting of the

temperature indicator module.

Higher-Order Calibration

If the application requires more precise temperature

measurement, additional calibrations steps will be

necessary. For these applications, two-point or three-

point calibration is recommended.

3. Obtain the output analog voltage (in mV) value

of the Fixed Reference Voltage (FVR) for 2x

setting, from the DIA Table. This parameter is

FVRA2X in the DIA table (Table 5-3).

19.3 ADC Acquisition Time

4. Obtain the value of the temperature indicator

voltage sensitivity, parameter Mv, from Table 37-

26 for the corresponding range setting.

To ensure accurate temperature measurements, the

user must wait a certain minimum acquisition time

(parameter TS01 in Table 37-26) for the ADC value to

settle, after the ADC input multiplexer is connected to

the temperature indicator output, before the conversion

is performed.

Equation 19-1 provides an estimate for the die

temperature based on the above parameters.

EQUATION 19-1: SENSOR TEMPERATURE

ADC

– ADC

  FVRA2X

MEAS

DIA

T

= 90 + --------------------------------------------------------------------------------------------

MEAS

N

2 – 1  Mv

Where:

ADCMEAS

estimated

= ADC reading at temperature being

ADCDIA = ADC reading stored in the DIA

FVRA2X = FVR value stored in the DIA for 2x setting

N = Resolution of the ADC

Mv = Temperature Indicator voltage sensitivity (mV/°C)

TABLE 19-2: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR⁽¹⁾

Register

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

on page

FVRCON

EN

RDY

TSEN

TSRNG

CDAFVR<1:0>

ADFVR<1:0>

222

Legend: — = Unimplemented location, read as ‘0’. Shaded cells are unused by the temperature indicator module.

Note 1: It is recommended to take the average of ten measurements of ADCMEAS to reduce noise and improve

accuracy.

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The ADC voltage reference is software selectable to be

either internally generated or externally supplied.

20.0 ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The ADC can generate an interrupt upon completion of

a conversion. This interrupt can be used to wake-up the

device from Sleep.

The Analog-to-Digital Converter (ADC) allows

conversion of an analog input signal to a 10-bit binary

representation of that signal. This device uses analog

inputs, which are multiplexed into a single sample and

hold circuit. The output of the sample and hold is

connected to the input of the converter. The converter

generates a 10-bit binary result via successive

approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 20-1 shows the block diagram of the ADC.

FIGURE 20-1:

ADC BLOCK DIAGRAM

Rev. 10-000033A

V

DD

ADPREF

7/30/2013

Positive

Reference

Select

V

DD

VREF+ pin

ADCS<2:0>

F

V

SS

AN0

ANa

VRNEG VRPOS

External

Channel

Inputs

.

Fosc

OSC/n

F

OSC

Divider

ADC

Clock

Select

ADC_clk

sampled

input

F

RC

ANz

F

RC

Temp Indicator

DACx_output

FVR_buffer1

Internal

Channel

Inputs

ADC CLOCK SOURCE

ADFM

ADC

Sample Circuit

CHS<4:0>

set bit ADIF

10

complete

start

10-bit Result

16

Write to bit

GO/DONE

Q1

Q4

ADRESH

ADRESL

Q2

Enable

Trigger Select

TRIGSEL<3:0>

ADON

. . .

V

SS

Trigger Sources

AUTO CONVERSION

TRIGGER

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20.1.3

ADC VOLTAGE REFERENCE

20.1 ADC Configuration

The ADPREF<1:0> bits of the ADCON1 register

provides control of the positive voltage reference. The

positive voltage reference can be:

When configuring and using the ADC the following

functions must be considered:

• Port configuration

• VREF+ pin

• Channel selection

• VDD

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• FVR 2.048V

• FVR 4.096V (Not available on LF devices)

The ADPREF bit of the ADCON1 register provides

control of the negative voltage reference. The negative

voltage reference can be:

• Result formatting

20.1.1

PORT CONFIGURATION

• VREF- pin

• VSS

The ADC can be used to convert both analog and

digital signals. When converting analog signals, the I/O

pin will be configured for analog by setting the

associated TRIS and ANSEL bits. Refer to

Section 14.0 “I/O Ports” for more information.

See Section 18.0 “Fixed Voltage Reference (FVR)”

for more details on the Fixed Voltage Reference.

20.1.4

CONVERSION CLOCK

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

The source of the conversion clock is software

selectable via the ADCS<2:0> bits of the ADCON1

register. There are seven possible clock options:

20.1.2

CHANNEL SELECTION

• FOSC/2

There are several channel selections available:

• FOSC/4

• Seven Port A channels

• Seven Port B channels

• Seven Port C channels

• Temperature Indicator

• DAC output

• FOSC/8

• FOSC/16

• FOSC/32

• FOSC/64

• ADCRC (dedicated RC oscillator)

• Fixed Voltage Reference (FVR)

• AVSS (Ground)

The time to complete one bit conversion is defined as

TAD. One full 10-bit conversion requires 11.5 TAD

periods as shown in Figure 20-2.

The CHS<5:0> bits of the ADCON0 register

(Register 20-1) determine which channel is connected

to the sample and hold circuit.

For correct conversion, the appropriate TAD specification

must be met. Refer to Table 37-13 for more information.

Table 20-1 gives examples of appropriate ADC clock

selections.

When changing channels, a delay is required before

starting the next conversion. Refer to Section 20.2

“ADC Operation” for more information.

Note:

Unless using the ADCRC, any changes in

the system clock frequency will change

the ADC clock frequency, which may

adversely affect the ADC result.

Note:

It is recommended that when switching

from an ADC channel of a higher voltage

to a channel of a lower voltage, that the

user selects the VSS channel before con-

necting to the channel with the lower volt-

age. If the ADC does not have a dedicated

VSS input channel, the VSS selection

(DAC1R<4:0> = b’00000’) through the

DAC output channel can be used. If the

DAC is in use, a free input channel can be

connected to VSS, and can be used in

place of the DAC.

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TABLE 20-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES

ADC Clock Period (TAD)

Device Frequency (FOSC)

ADC

ADCS<2:0>

Clock Source

32 MHz

20 MHz

16 MHz 8 MHz

4 MHz

1 MHz

(2)

FOSC/2

FOSC/4

000

100

001

101

010

110

x11

62.5ns

125 ns

0.5 s

100 ns

200 ns

400 ns

125 ns

250 ns

500 ns

1.0 s

2.0 s

4.0 s

2.0 s

4.0 s

(2)

(3)

FOSC/8

0.5 s

1.0 s

2.0 s

4.0 s

8.0 s

16.0 s

32.0 s

64.0 s

(3)

FOSC/16

FOSC/32

FOSC/64

ADCRC

800 ns

1.0 s

800 ns

1.6 s

3.2 s

1.0 s

2.0 s

(3)

(2)

8.0 s

(3)

(2)

2.0 s

4.0 s

8.0 s

16.0 s

(1,4)

1.0-6.0 s

Legend: Shaded cells are outside of recommended range.

Note 1: See TAD parameter for ADCRC source typical TAD value.

2: These values violate the required TAD time.

3: Outside the recommended TAD time.

4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived

from the system clock FOSC. However, the ADCRC oscillator source must be used when conversions are to be

performed with the device in Sleep mode.

FIGURE 20-2:

ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

Rev. 10-000035A

7/30/2013

TAD1

TAD2

b9

TAD3

b8

TAD4

b7

TAD5

b6

TAD6

b5

TAD7

b4

TAD8

b3

TAD9

b2

TAD10

b1

TAD11

b0

THCD

Conversion Starts

TACQ

On the following cycle:

Holding capacitor disconnected

from analog input (THCD).

ADRESH:ADRESL is loaded,

GO bit is cleared,

Set GO bit

ADIF bit is set,

holding capacitor is reconnected to analog input.

Enable ADC (ADON bit)

and

Select channel (ACS bits)

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20.1.5

INTERRUPTS

20.1.6

RESULT FORMATTING

The ADC module allows for the ability to generate an

interrupt upon completion of an Analog-to-Digital

conversion. The ADC Interrupt Flag is the ADIF bit in

the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be

cleared in software.

The 10-bit ADC conversion result can be supplied in

two formats, left justified or right justified. The ADFM bit

of the ADCON1 register controls the output format.

Figure 20-3 shows the two output formats.

Note 1: The ADIF bit is set at the completion of

every conversion, regardless of whether

or not the ADC interrupt is enabled.

2: The ADC operates during Sleep only

when the ADCRC oscillator is selected.

This interrupt can be generated while the device is

operating or while in Sleep. If the device is in Sleep, the

interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the SLEEP

instruction is always executed. If the user is attempting

to wake-up from Sleep and resume in-line code

execution, the ADIE bit of the PIE1 register and the

PEIE bit of the INTCON register must both be set and

the GIE bit of the INTCON register must be cleared. If

all three of these bits are set, the execution will switch

to the Interrupt Service Routine (ISR).

FIGURE 20-3:

10-BIT ADC CONVERSION RESULT FORMAT

Rev. 10-000 054A

12/21/201 6

ADRESH

ADRESL

LSb

(ADFM = 0) MSb

bit 7

bit 0

bit 7

bit 0

10-bit ADC Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSb

LSb

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit ADC Result

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20.2 ADC Operation

Note:

The Auto-conversion feature is not avail-

able while the device is in Sleep mode.

20.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘1’. Setting the GO/

DONE bit of the ADCON0 register to a ‘1’ will start the

Analog-to-Digital conversion.

TABLE 20-2: ADC AUTO-CONVERSION

TABLE

ADACT

VALUE

SOURCE/

PERIPHERAL

Note:

The GO/DONE bit will not be set in the

same instruction that turns on the ADC.

Refer to Section 20.2.5 “ADC Conver-

sion Procedure”.

DESCRIPTION

0x00

Disabled

ADACTPPS

TMR0

External Trigger Disabled

Pin Selected by ADACTPPS

Timer0 overflow condition

Timer1 overflow condition

0x01

0x02

0x03

20.2.2

COMPLETION OF A CONVERSION

TMR1

Match between Timer2 postscaled

value and PR2

When the conversion is complete, the ADC module will:

0x04

TMR2

• Clear the GO/DONE bit

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

CCP1

CCP2

PWM3

PWM4

PWM5

PWM6

NCO1

C1OUT

C2OUT

IOCIF

CLC1

CCP1 output

• Set the ADIF Interrupt Flag bit

CCP2 output

PWM3 output

• Update the ADRESH and ADRESL registers with

new conversion result

PWM4 output

PWM5 output

PWM6 output

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is

turned off and any pending conversion is

terminated.

NCO1 output

Comparator C1 output

Comparator C2 output

Interrupt-on change flag trigger

CLC1 output

20.2.3

ADC OPERATION DURING SLEEP

CLC2

CLC2 output

The ADC module can operate during Sleep. This

requires the ADC clock source to be set to the ADCRC

option. When the ADCRC oscillator source is selected,

the ADC waits one additional instruction before starting

the conversion. This allows the SLEEPinstruction to be

executed, which can reduce system noise during the

conversion. If the ADC interrupt is enabled, the device

will wake-up from Sleep when the conversion

completes. If the ADC interrupt is disabled, the ADC

module is turned off after the conversion completes,

although the ADON bit remains set.

CLC3

CLC3 output

CLC4

CLC4 output

0x13-0xFF Reserved

Reserved, do not use

When the ADC clock source is something other than

ADCRC, a SLEEP instruction causes the present

conversion to be aborted and the ADC module is

turned off, although the ADON bit remains set.

20.2.4

AUTO-CONVERSION TRIGGER

The Auto-conversion Trigger allows periodic ADC

measurements without software intervention. When a

rising edge of the selected source occurs, the GO/

DONE bit is set by hardware.

The Auto-conversion Trigger source is selected with

the ADACT<4:0> bits of the ADACT register.

Using the Auto-conversion Trigger does not assure

proper ADC timing. It is the user’s responsibility to

ensure that the ADC timing requirements are met.

See Table 20-2 for auto-conversion sources.

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20.2.5

ADC CONVERSION PROCEDURE

EXAMPLE 20-1:

ADC CONVERSION

This is an example procedure for using the ADC to

perform an Analog-to-Digital conversion:

;This code block configures the ADC

;for polling, Vdd and Vss references, ADCRC

;oscillator and AN0 input.

;

;Conversion start & polling for completion ;

are included.

1. Configure Port:

• Disable pin output driver (Refer to the TRIS

register)

;

BANKSELADCON1;

MOVLWB’11110000’;Right justify, ADCRC

;oscillator

• Configure pin as analog (Refer to the ANSEL

register)

MOVWFADCON1;Vdd and Vss Vref

BANKSELTRISA;

BSF TRISA,0;Set RA0 to input

BANKSELANSELA;

BSF ANSELA,0;Set RA0 to analog

BANKSELADCON0;

MOVLWB’00000001’;Select channel AN0

MOVWFADCON0;Turn ADC On

CALLSampleTime;Acquisiton delay

BSF ADCON0,ADGO;Start conversion

BTFSCADCON0,ADGO;Is conversion done?

GOTO$-1 ;No, test again

BANKSELADRESH;

MOVFADRESH,W;Read upper 2 bits

MOVWFRESULTHI;store in GPR space

BANKSELADRESL;

2. Configure the ADC module:

• Select ADC conversion clock

• Select voltage reference

• Select ADC input channel

• Turn on ADC module

3. Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt⁽¹⁾

4. Wait the required acquisition time⁽²⁾

.

MOVFADRESL,W;Read lower 8 bits

MOVWFRESULTLO;Store in GPR space

5. Start conversion by setting the GO/DONE bit.

6. Wait for ADC conversion to complete by one of

the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt

7. Read ADC Result.

8. Clear the ADC interrupt flag (required if interrupt

is enabled).

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep

and resume in-line code execution.

2: Refer to Section 20.3 “ADC Acquisi-

tion Requirements”.

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source impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (or changed), an ADC acquisition must be

done before the conversion can be started. To calculate

the minimum acquisition time, Equation 20-1 may be

used. This equation assumes that 1/2 LSb error is used

(1024 steps for the ADC). The 1/2 LSb error is the

maximum error allowed for the ADC to meet its

specified resolution.

20.3 ADC Acquisition Requirements

For the ADC to meet its specified accuracy, the charge

holding capacitor (CHOLD) must be allowed to fully

charge to the input channel voltage level. The Analog

Input model is shown in Figure 20-4. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), refer

to Figure 20-4. The maximum recommended

impedance for analog sources is 10 k. As the

EQUATION 20-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + Temperature - 25°C0.05µs/°C

The value for TC can be approximated with the following equations:

1





;[1] VCHOLD charged to within 1/2 lsb

^VAPPLIED^{1 – -------------------------- = VCHOLD}



2^{n + 1} – 1

–TC

---------





RC

VAPPLIED 1 – e

= V^CHOLD







;[2] VCHOLD charge response to VAPPLIED

;combining [1] and [2]



–Tc

--------









RC

1







^{= VAPPLIED}^{1 – --------------------------}

2^{n + 1} – 1

VAPPLIED 1 – e





Note: Where n = number of bits of the ADC.

Solving for TC:

TC = –CHOLDRIC + RSS + RS ln(1/2047)

= –10pF1k + 7k + 10k ln(0.0004885)

= 1.37µs

Therefore:

TACQ = 2µs + 1.37 + 50°C- 25°C0.05µs/°C

= 4.62µs

Note 1: The VAPPLIED has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin

leakage specification.

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FIGURE 20-4:

ANALOG INPUT MODEL

Rev. 10-000070A

8/23/2016

VDD

Sampling

Analog

switch

VT § 0.6V

SS

Input pin

RS

RIC 1K

RSS

(1)

ILEAKAGE

CHOLD = 10 pF

Ref-

CPIN

5pF

VA

6V

5V

Legend: CHOLD

CPIN

= Sample/Hold Capacitance

= Input Capacitance

VDD 4V

RSS

3V

2V

ILEAKAGE = Leakage Current at the pin due to varies injunctions

RIC

RSS

SS

VT

= Interconnect Resistance

= Resistance of Sampling switch

= Sampling Switch

= Threshold Voltage

= Source Resistance

5 6 7 8 91011

Sampling Switch

(k )

RS

Note 1: See Refer to Section 37.0 “Electrical Specifications”.

FIGURE 20-5:

ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

03h

02h

01h

00h

Analog Input Voltage

1.5 LSB

0.5 LSB

Zero-Scale

Transition

Ref-

Full-Scale

Transition

Ref+

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20.4 Register Definitions: ADC Control

REGISTER 20-1: ADCON0: ADC CONTROL REGISTER 0

R/W-0/0

CHS<5:0>

R/W-0/0

ADON

GO/DONE

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-2

CHS<5:0>: Analog Channel Select bits

111111=FVR Buffer 2 reference voltage

(2)

111110=FVR 1Buffer 1 reference voltage

(1)

111101=DAC1 output voltage

(3)

111100=Temperature sensor output

111011=AVSS (Analog Ground)

111010-011000= Reserved. No channel connected

•

010111= RC7

010110= RC6

010101= RC5

010100= RC4

010011= RC3

010010= RC2

010001= RC1

010000= RC0

001111= RB7

001110= RB6

001101= RB5

001100= RB4

001011= RB3

001010= RB2

001001= RB1

001000= RB0

(4)

001011= RA7

000101= RA5

000100= RA4

000011= RA3

000010= RA2

000001= RA1

000000= RA0

bit 1

bit 0

GO/DONE: ADC Conversion Status bit

1= ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle.

This bit is automatically cleared by hardware when the ADC conversion has completed.

0= ADC conversion completed/not in progress

ADON: ADC Enable bit

1= ADC is enabled

0= ADC is disabled and consumes no operating current

Note 1:

See Section 21.0 “5-Bit Digital-to-Analog Converter (DAC1) Module” for more information.

See Section 18.0 “Fixed Voltage Reference (FVR)” for more information.

2:

3:

4:

See Section 19.0 “Temperature Indicator Module” for more information.

The analog channel functionality on these pins is disabled when the system clock source is selected is external.

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REGISTER 20-2: ADCON1: ADC CONTROL REGISTER 1

R/W-0/0

ADFM

R/W-0/0

U-0

—

U-0

—

R/W-0/0

ADCS<2:0>

ADPREF<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

ADFM: ADC Result Format Select bit

1= Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is

loaded.

0= Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is

loaded.

bit 6-4

ADCS<2:0>: ADC Conversion Clock Select bits

111=ADCRC (dedicated RC oscillator)

110=FOSC/64

101=FOSC/16

100=FOSC/4

011=ADCRC (dedicated RC oscillator)

010=FOSC/32

001=FOSC/8

000=FOSC/2

bit 3-2

bit 1-0

Unimplemented: Read as ‘0’

ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits

11=VREF+ is connected to internal Fixed Voltage Reference (FVR) module⁽¹⁾

10=VREF+ is connected to external VREF+ pin⁽¹⁾

01=Reserved

00=VREF+ is connected to VDD

Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage

specification exists. See Table 37-14 for details.

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REGISTER 20-3: ADACT: A/D AUTO-CONVERSION TRIGGER

U-0

—

U-0

—

U-0

—

R/W-0/0

ADACT<4:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

ADACT<4:0>: Auto-Conversion Trigger Selection bits⁽¹⁾(see Table 20-2)

Note 1: This is a rising edge sensitive input for all sources.

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REGISTER 20-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x/u

ADRES<9:2>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<9:2>: ADC Result Register bits

Upper eight bits of 10-bit conversion result

REGISTER 20-5: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

ADRES<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-0

ADRES<1:0>: ADC Result Register bits

Lower two bits of 10-bit conversion result

Reserved: Do not use.

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REGISTER 20-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

—

R/W-x/u

ADRES<9:8>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-2

bit 1-0

Reserved: Do not use.

ADRES<9:8>: ADC Result Register bits

Upper two bits of 10-bit conversion result

REGISTER 20-7: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x/u

bit 0

ADRES<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

ADRES<7:0>: ADC Result Register bits

Lower eight bits of 10-bit conversion result

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TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

Register

on Page

Name

INTCON

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

GIE

PEIE

—

INTEDG

ADIE

121

123

131

175

181

186

176

182

187

234

235

236

OSFIE

CSWIE

PIE1

PIR1

OSFIF

TRISA7

TRISB7

TRISC7

ANSA7

ANSB7

ANSC7

CSWIF

TRISA6

TRISB6

TRISC6

ANSA6

ANSB6

ANSC6

—

ADIF

TRISA

TRISB

TRISC

ANSELA

ANSELB

ANSELC

TRISA5

TRISB5

TRISC5

ANSA5

ANSB5

ANSC5

TRISA4

TRISB4

TRISC4

ANSA4

ANSB4

ANSC4

TRISA3

TRISB3

TRISC3

ANSA3

ANSB3

ANSC3

TRISA2

TRISB2

TRISC2

ANSA2

ANSB2

ANSC2

TRISA1

TRISB1

TRISC1

ANSA1

ANSB1

ANSC1

TRISA0

TRISB0

TRISC0

ANSA0

ANSB0

ANSC0

ADCON0

ADCON1

ADACT

CHS<5:0>

GO/DONE

ADON

ADFM

—

ADCS<2:0>

—

ADPREF<1:0>

—

ADACT<4:0>

ADRESH

ADRESH<7:0>

ADRESL<7:0>

237

222

243

112

ADRESL

FVRCON

DAC1CON1

OSCSTAT1

Legend:

FVREN

—

FVRRDY

—

TSEN

—

TSRNG

CDAFVR<1:0>

ADFVR<1:0>

DAC1R<4:0>

ADOR

EXTOR

HFOR

MFOR

LFOR

SOR

—

PLLR

—= unimplemented read as ‘0’. Shaded cells are not used for the ADC module.

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21.1 Output Voltage Selection

21.0 5-BIT DIGITAL-TO-ANALOG

CONVERTER (DAC1) MODULE

The DAC has 32 voltage level ranges. The 32 levels

are set with the DAC1R<4:0> bits of the DAC1CON1

register.

The Digital-to-Analog Converter supplies a variable

voltage reference, ratiometric with the input source,

with 32 selectable output levels.

The DAC output voltage is determined by Equation 21-1:

The input of the DAC can be connected to:

• External VREF pins

• VDD supply voltage

• FVR (Fixed Voltage Reference)

The output of the DAC can be configured to supply a

reference voltage to the following:

• Comparator positive input

• ADC input channel

• DAC1OUT pin

The Digital-to-Analog Converter (DAC) is enabled by

setting the DAC1EN bit of the DAC1CON0 register.

EQUATION 21-1: DAC OUTPUT VOLTAGE

V

= V

– V

^D-----^A----^C-----¹---^R-----^---⁴---^:--⁰---^- + V

SOURCE-



OUT

SOURCE+

SOURCE-

5

2

V

= V

or

V

or FVR

SOURCE+

= V

DD

or V

REF+

V

REF-

SOURCE-

SS

21.2 Ratiometric Output Level

The DAC output value is derived using a resistor ladder

with each end of the ladder tied to a positive and

negative voltage reference input source. If the voltage

of either input source fluctuates, a similar fluctuation will

result in the DAC output value.

The value of the individual resistors within the ladder

can be found in Table 37-15.

21.3 DAC Voltage Reference Output

The DAC voltage can be output to the DAC1OUT1/2

pins by setting the DAC1OE1/2 bits of the DAC1CON0

register, respectively. Selecting the DAC reference

voltage for output on the DAC1OUT1/2 pins

automatically overrides the digital output buffer and

digital input threshold detector functions, disables the

weak pull-up, and disables the current-controlled drive

function of that pin. Reading the DAC1OUT1/2 pin

when it has been configured for DAC reference voltage

output will always return a ‘0’.

Due to the limited current drive capability, a buffer must

be used on the DAC voltage reference output for

external connections to the DAC1OUT1/2 pins.

Figure 21-2 shows an example buffering technique.

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FIGURE 21-1:

DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM

Rev. 10-000026G

12/15/2016

Reserved

11

10

01

00

V

SOURCE+

DACR<4:0>

FVR Buffer

5

R

V

REF+

V

DD

R

DACPSS

DACx_output

32

Steps

To Peripherals

DACEN

R

DACxOUT1⁽¹⁾

DACOE1

DACxOUT2⁽¹⁾

VREF

-

1

0

DACOE2

V

SOURCE-

V

SS

DACNSS

Note 1: The unbuffered DACx_output is provided on the DACxOUT pin(s).

FIGURE 21-2:

VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE

PIC^®MCU

DAC

Module

R

+

–

Buffered DAC Output

DAC1OUT

Voltage

Reference

Output

Impedance

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21.4 Operation During Sleep

The DAC continues to function during Sleep. When the

device wakes up from Sleep through an interrupt or a

Watchdog Timer time-out, the contents of the

DAC1CON0 register are not affected.

21.5 Effects of a Reset

A device Reset affects the following:

• DAC is disabled.

• DAC output voltage is removed from the

DAC1OUT1/2 pins.

• The DAC1R<4:0> range select bits are cleared.

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21.6 Register Definitions: DAC Control

REGISTER 21-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0

R/W-0/0

U-0

—

R/W-0/0

U-0

—

R/W-0/0

DAC1EN

DAC1OE1

DAC1OE2

DAC1PSS<1:0>

DAC1NSS

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

DAC1EN: DAC1 Enable bit

1= DAC is enabled

0= DAC is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

DAC1OE1: DAC1 Voltage Output 1 Enable bit

1= DAC voltage level is an output on the DAC1OUT1 pin

0= DAC voltage level is disconnected from the DAC1OUT1 pin

bit 4

DAC1OE2: DAC1 Voltage Output 2 Enable bit

1= DAC voltage level is an output on the DAC1OUT2 pin

0= DAC voltage level is disconnected from the DAC1OUT2 pin

bit 3-2

DAC1PSS<1:0>: DAC1 Positive Source Select bits

11=Reserved, do not use

10=FVR output

01=VREF+ pin

00=VDD

bit 1

bit 0

Unimplemented: Read as ‘0’

DAC1NSS: Read as ‘0’

REGISTER 21-2: DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0/0

bit 0

DAC1R<4:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

DAC1R<4:0>: DAC1 Voltage Output Select bits

VOUT = (VSRC+ - VSRC-)*(DAC1R<4:0>/32) + VSRC

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TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

DAC1CON0

DAC1CON1

CM1PSEL

CM2PSEL

Legend:

DAC1EN

—

DAC1OE1 DAC1OE2

—

DAC1PSS<1:0>

DAC1R<4:0>

—

DAC1NSS

243

263

—

PCH<2:0>

— = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module.

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22.0 NUMERICALLY CONTROLLED

OSCILLATOR (NCO) MODULE

The Numerically Controlled Oscillator (NCO) module is

a timer that uses overflow from the addition of an

increment value to divide the input frequency. The

advantage of the addition method over simple counter

driven timer is that the output frequency resolution

does not vary with the divider value. The NCO is most

useful for application that requires frequency accuracy

and fine resolution at a fixed duty cycle.

Features of the NCO include:

• 20-bit Increment Function

• Fixed Duty Cycle mode (FDC) mode

• Pulse Frequency (PF) mode

• Output Pulse Width Control

• Multiple Clock Input Sources

• Output Polarity Control

• Interrupt Capability

Figure 22-1 is a simplified block diagram of the NCO

module.

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22.1 NCO OPERATION

The NCO operates by repeatedly adding a fixed value to

an accumulator. Additions occur at the input clock rate.

The accumulator will overflow with a carry periodically,

which is the raw NCO output (NCO_overflow). This

effectively reduces the input clock by the ratio of the

addition value to the maximum accumulator value. See

Equation 22-1.

The NCO output can be further modified by stretching

the pulse or toggling a flip-flop. The modified NCO

output is then distributed internally to other peripherals

and can be optionally output to a pin. The accumulator

overflow also generates an interrupt (NCO_overflow).

The NCO period changes in discrete steps to create an

average frequency.

EQUATION 22-1: NCO OVERFLOW FREQUENCY

NCO Clock Frequency  Increment Value

FOVERFLOW= ---------------------------------------------------------------------------------------------------------------

2²⁰

22.1.1

NCO CLOCK SOURCES

22.1.4

INCREMENT REGISTERS

Clock sources available to the NCO include:

The increment value is stored in three registers making

up a 20-bit incrementer. In order of LSB to MSB they

are:

• HFINTOSC

• FOSC

• LC1_out

• LC2_out

• LC3_out

• LC4_out

• NCO1INCL

• NCO1INCH

• NCO1INCU

When the NCO module is enabled, the NCO1INCU and

NCO1INCH registers should be written first, then the

NCO1INCL register. Writing to the NCO1INCL register

initiates the increment buffer registers to be loaded

simultaneously on the second rising edge of the

NCO_clk signal.

• MFINTOSC (500 kHz)

• MFINTOSC (32 kHz)

• SOSC

• CLKR

The NCO clock source is selected by configuring the

N1CKS<2:0> bits in the NCO1CLK register.

The registers are readable and writable. The increment

registers are double-buffered to allow value changes to

be made without first disabling the NCO module.

22.1.2

ACCUMULATOR

The accumulator is a 20-bit register. Read and write

access to the accumulator is available through three

registers:

When the NCO module is disabled, the increment

buffers are loaded immediately after a write to the

increment registers.

• NCO1ACCL

• NCO1ACCH

• NCO1ACCU

Note: The increment buffer registers are not user-

accessible.

22.1.3

ADDER

The NCO Adder is a full adder, which operates

synchronously from the source clock. The addition of

the previous result and the increment value replaces

the accumulator value on the rising edge of each input

clock.

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22.2 FIXED DUTY CYCLE MODE

22.5 Interrupts

In Fixed Duty Cycle (FDC) mode, every time the

accumulator overflows (NCO_overflow), the output is

toggled at a frequency rate half of the FOVERFLOW. This

provides a 50% duty cycle, provided that the increment

value remains constant. For more information, see

Figure 22-2.

When the accumulator overflows (NCO_overflow), the

NCO Interrupt Flag bit, NCO1IF, of the PIR7 register is

set. To enable the interrupt event (NCO_interrupt), the

following bits must be set:

• N1EN bit of the NCO1CON register

• NCO1IE bit of the PIE7 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The FDC mode is selected by clearing the N1PFM bit

in the NCO1CON register.

The interrupt must be cleared by software by clearing

the NCO1IF bit in the Interrupt Service Routine.

22.3 PULSE FREQUENCY MODE

In Pulse Frequency (PF) mode, every time the

Accumulator overflows, the output becomes active for

one or more clock periods. Once the clock period

expires, the output returns to an inactive state. This

provides a pulsed output. The output becomes active

on the rising clock edge immediately following the

overflow event. For more information, see Figure 22-2.

22.6 Effects of a Reset

All of the NCO registers are cleared to zero as the

result of a Reset.

22.7 Operation in Sleep

The NCO module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock source selected remains active.

The value of the active and inactive states depends on

the polarity bit, N1POL in the NCO1CON register.

The PF mode is selected by setting the N1PFM bit in

the NCO1CON register.

The HFINTOSC remains active during Sleep when the

NCO module is enabled and the HFINTOSC is

selected as the clock source, regardless of the system

clock source selected.

22.3.1

OUTPUT PULSE WIDTH CONTROL

When operating in PF mode, the active state of the out-

put can vary in width by multiple clock periods. Various

pulse widths are selected with the N1PWS<2:0> bits in

the NCO1CLK register.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the NCO clock

source, when the NCO is enabled, the CPU will go idle

during Sleep, but the NCO will continue to operate and

the HFINTOSC will remain active.

When the selected pulse width is greater than the

Accumulator overflow time frame, then NCO1 output

does not toggle.

This will have a direct effect on the Sleep mode current.

22.4 OUTPUT POLARITY CONTROL

The last stage in the NCO module is the output polarity.

The N1POL bit in the NCO1CON register selects the

output polarity. Changing the polarity while the

interrupts are enabled will cause an interrupt for the

resulting output transition.

The NCO output signal (NCO1_out) is available to the

following peripherals:

• CLC

• CWG

• Timer1

• Timer2

• CLKR

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22.8 NCO Control Registers

REGISTER 22-1: NCO1CON: NCO CONTROL REGISTER

R/W-0/0

N1EN

U-0

—

R-0/0

R/W-0/0

N1POL

U-0

—

U-0

—

U-0

—

R/W-0/0

N1PFM

N1OUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

N1EN: NCO1 Enable bit

1= NCO1 module is enabled

0= NCO1 module is disabled

bit 6

bit 5

Unimplemented: Read as ‘0’

N1OUT: NCO1 Output bit

Displays the current output value of the NCO1 module.

bit 4

N1POL: NCO1 Polarity bit

1= NCO1 output signal is inverted

0= NCO1 output signal is not inverted

bit 3-1

bit 0

Unimplemented: Read as ‘0’

N1PFM: NCO1 Pulse Frequency Mode bit

1= NCO1 operates in Pulse Frequency mode

0= NCO1 operates in Fixed Duty Cycle mode, divide by 2

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REGISTER 22-2: NCO1CLK: NCO1 INPUT CLOCK CONTROL REGISTER

R/W-0/0

N1PWS<2:0>^(1,2)

R/W-0/0

U-0

—

R/W-0/0

bit 0

N1CKS<3:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-5

N1PWS<2:0>: NCO1 Output Pulse Width Select bits⁽¹⁾

111= NCO1 output is active for 128 input clock periods

110= NCO1 output is active for 64 input clock periods

101= NCO1 output is active for 32 input clock periods

100= NCO1 output is active for 16 input clock periods

011= NCO1 output is active for 8 input clock periods

010= NCO1 output is active for 4 input clock periods

001= NCO1 output is active for 2 input clock periods

000= NCO1 output is active for 1 input clock period

bit 4

Unimplemented: Read as ‘0’

bit 3-0

N1CKS<3:0>: NCO1 Clock Source Select bits

1011-1111= Reserved

1010= LC4_out

1001= LC3_out

1000= LC2_out

0111= LC1_out

0110= CLKR

0101= SOSC

0100= MFINTOSC (32 kHz)

0011= MFINTOSC (500 kHz)

0010= LFINTOSC

0001= HFINTOSC

0000= FOSC

Note 1: N1PWS applies only when operating in Pulse Frequency mode.

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REGISTER 22-3: NCO1ACCL: NCO1 ACCUMULATOR REGISTER – LOW BYTE

R/W-0/0

bit 0

NCO1ACC<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCO1ACC<7:0>: NCO1 Accumulator, Low Byte

REGISTER 22-4: NCO1ACCH: NCO1 ACCUMULATOR REGISTER – HIGH BYTE

R/W-0/0

bit 7

R/W-0/0

bit 0

NCO1ACC<15:8>

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-0

NOC1ACC<15:8>: NCO1 Accumulator, High Byte

REGISTER 22-5: NCO1ACCU: NCO1 ACCUMULATOR REGISTER – UPPER BYTE⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

bit 0

NCO1ACC<19:16>

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

NCO1ACC<19:16>: NCO1 Accumulator, Upper Byte

Note 1: The accumulator spans registers NCO1ACCU:NCO1ACCH: NCO1ACCL. The 24 bits are reserved but

not all are used.This register updates in real-time, asynchronously to the CPU; there is no provision to

guarantee atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is

operating will produce undefined results.

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REGISTER 22-6:

R/W-0/0 R/W-0/0

NCO1INCL: NCO1 INCREMENT REGISTER – LOW BYTE^(1,2)

R/W-0/0

R/W-1/1

bit 0

NCO1INC<7:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCO1INC<7:0>: NCO1 Increment, Low Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

2: NCO1INC is double-buffered as INCBUF; INCBUF is updated on the next falling edge of NCOCLK after

writing to NCO1INCL; NCO1INCU and NCO1INCH should be written prior to writing NCO1INCL.

REGISTER 22-7: NCO1INCH: NCO1 INCREMENT REGISTER – HIGH BYTE⁽¹⁾

R/W-0/0

bit 0

NCO1INC<15:8>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

NCO1INC<15:8>: NCO1 Increment, High Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

REGISTER 22-8: NCO1INCU: NCO1 INCREMENT REGISTER – UPPER BYTE⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

NCO1INC<19:16>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

NCO1INC<19:16>: NCO1 Increment, Upper Byte

Note 1: The logical increment spans NCO1INCU:NCO1INCH:NCO1INCL.

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TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH NCO

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

—

PEIE

―

—

―

—

―

—

―

INTEDG

CWG1IF

CWG1IE

N1PFM

121

137

PIR7

—

NVMIF

NVMIE

N1OUT

NCO1IF

NCO1IE

N1POL

―

—

PIE7

129

250

251

252

253

200

NCO1CON

NCO1CLK

NCO1ACCL

NCO1ACCH

NCO1ACCU

NCO1INCL

NCO1INCH

NCO1INCU

RxyPPS

N1EN

―

N1PWS<2:0>

N1CKS<3:0>

NCO1ACC<7:0>

NCO1ACC<15:8>

―

NCO1ACC<19:16>

―

NCO1INC<7:0>

NCO1INC<15:8>

―

NCO1AINC<19:16>

RxyPPS<4:0>

―

Legend:

—= unimplemented read as ‘0’. Shaded cells are not used for NCO module.

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FIGURE 23-1:

SINGLE COMPARATOR

23.0 COMPARATOR MODULE

Comparators are used to interface analog circuits to a

digital circuit by comparing two analog voltages and

providing a digital indication of their relative magnitudes.

Comparators are very useful mixed signal building

blocks because they provide analog functionality

independent of program execution. The analog

comparator module includes the following features:

VIN+

VIN-

+

Output

–

VIN-

VIN+

• Programmable input selection

• Selectable voltage reference

• Programmable output polarity

• Rising/falling output edge interrupts

• CWG1 Auto-shutdown source

Output

23.1

Comparator Overview

A single comparator is shown in Figure 23-1 along with

the relationship between the analog input levels and

the digital output. When the analog voltage at VIN+ is

less than the analog voltage at VIN-, the output of the

comparator is a digital low level. When the analog

voltage at VIN+ is greater than the analog voltage at

VIN-, the output of the comparator is a digital high level.

Note:

The black areas of the output of the

comparator represents the uncertainty

due to input offsets and response time.

The comparators available are shown in Table 23-1.

TABLE 23-1: AVAILABLE COMPARATORS

Device

C1

C2

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●

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FIGURE 23-2:

COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000027K

11/20/2015

3

CxNCH<2:0>

CxON⁽¹⁾

CxINTP

CxINTN

Interrupt

Rising

Edge

set bit

CxIF

CxIN0-

CxIN1-

000

001

010

011

100

101

110

111

Interrupt

Falling

Edge

CxON⁽¹⁾

Cx

CxIN2-

CxIN3-

CxVN

CxVP

CxOUT

-

D

Q

Reserved

FVR_buffer2

MCxOUT

+

Q1

CxSP CxHYS

CxPOL

CxOUT_sync

to

peripherals

CxSYNC

Q

CxIN0+

CxIN1+

000

001

010

011

100

101

110

111

TRIS bit

0

1

CxOUT

PPS

Reserved

DAC_output

FVR_buffer2

D

RxyPPS

(From Timer1 Module) T1CLK

CxPCH<2:0>

CxON⁽¹⁾

2

Note 1:

When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a ‘0’ at the output.

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23.2.3

COMPARATOR OUTPUT POLARITY

23.2 Comparator Control

Inverting the output of the comparator is functionally

equivalent to swapping the comparator inputs. The

polarity of the comparator output can be inverted by

setting the CxPOL bit of the CMxCON0 register.

Clearing the CxPOL bit results in a non-inverted output.

Each comparator has two control registers: CMxCON0

and CMxCON1.

The CMxCON0 register (see Register 23-1) contains

Control and Status bits for the following:

• Enable

Table 23-2 shows the output state versus input

conditions, including polarity control.

• Output

• Output polarity

• Hysteresis enable

• Timer1 output synchronization

TABLE 23-2: COMPARATOR OUTPUT

STATE VS. INPUT

The CMxCON1 register (see Register 23-2) contains

Control bits for the following:

CONDITIONS

Input Condition

CxPOL

CxOUT

• Interrupt on positive/negative edge enables

CxVN > CxVP

CxVN < CxVP

CxVN > CxVP

CxVN < CxVP

0

1

0

1

0

23.2.1

COMPARATOR ENABLE

Setting the CxON bit of the CMxCON0 register enables

the comparator for operation. Clearing the CxON bit

disables the comparator resulting in minimum current

consumption.

23.2.2

COMPARATOR OUTPUT

The output of the comparator can be monitored by

reading either the CxOUT bit of the CMxCON0 register

or the MCxOUT bit of the CMOUT register.

The comparator output can also be routed to an

external pin through the RxyPPS register (Register 15-

2). The corresponding TRIS bit must be clear to enable

the pin as an output.

Note 1: The internal output of the comparator is

latched with each instruction cycle.

Unless otherwise specified, external out-

puts are not latched.

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The associated interrupt flag bit, CxIF bit of the PIR2

register, must be cleared in software. If another edge is

detected while this flag is being cleared, the flag will still

be set at the end of the sequence.

23.3 Comparator Hysteresis

A selectable amount of separation voltage can be

added to the input pins of each comparator to provide a

hysteresis function to the overall operation. Hysteresis

is enabled by setting the CxHYS bit of the CMxCON0

register.

Note:

Although a comparator is disabled, an

interrupt can be generated by changing

the output polarity with the CxPOL bit of

the CMxCON0 register, or by switching

the comparator on or off with the CxON bit

of the CMxCON0 register.

See Comparator Specifications in Table 37-14 for more

information.

23.4 Timer1 Gate Operation

The output resulting from a comparator operation can

be used as a source for gate control of Timer1. See

Section 26.7 “Timer Gate” for more information. This

feature is useful for timing the duration or interval of an

analog event.

23.6 Comparator Positive Input

Selection

Configuring the CxPCH<2:0> bits of the CMxPSEL

register directs an internal voltage reference or an

analog pin to the noninverting input of the comparator:

It is recommended that the comparator output be

synchronized to Timer1. This ensures that Timer1 does

not increment while a change in the comparator is

occurring.

• CxIN0+ analog pin

• DAC output

23.4.1

COMPARATOR OUTPUT

SYNCHRONIZATION

• FVR (Fixed Voltage Reference)

• VSS (Ground)

The output from a comparator can be synchronized

with Timer1 by setting the CxSYNC bit of the

CMxCON0 register.

See Section 18.0 “Fixed Voltage Reference (FVR)”

for more information on the Fixed Voltage Reference

module.

Once enabled, the comparator output is latched on the

falling edge of the Timer1 source clock. If a prescaler is

used with Timer1, the comparator output is latched after

the prescaling function. To prevent a race condition, the

comparator output is latched on the falling edge of the

Timer1 clock source and Timer1 increments on the

rising edge of its clock source. See the Comparator

Block Diagram (Figure 23-2) and the Timer1 Block

Diagram (Figure 26-1) for more information.

See Section 21.0 “5-Bit Digital-to-Analog Converter

(DAC1) Module” for more information on the DAC

input signal.

Any time the comparator is disabled (CxON = 0), all

comparator inputs are disabled.

23.7 Comparator Negative Input

Selection

The CxNCH<2:0> bits of the CMxNSEL register direct

an analog input pin and internal reference voltage or

analog ground to the inverting input of the comparator:

23.5 Comparator Interrupt

An interrupt can be generated upon a change in the

output value of the comparator for each comparator, a

rising edge detector and a falling edge detector are

present.

• CxINy - pin

• FVR (Fixed Voltage Reference)

• Analog Ground

When either edge detector is triggered and its associ-

ated enable bit is set (CxINTP and/or CxINTN bits of

the CMxCON1 register), the Corresponding Interrupt

Flag bit (CxIF bit of the PIR2 register) will be set.

Note:

To use CxINy+ and CxINy- pins as analog

input, the appropriate bits must be set in

the ANSEL register and the correspond-

ing TRIS bits must also be set to disable

the output drivers.

To enable the interrupt, you must set the following bits:

• CxON, CxPOL and CxSP bits of the CMxCON0

register

• CxIE bit of the PIE2 register

• CxINTP bit of the CMxCON1 register (for a rising

edge detection)

• CxINTN bit of the CMxCON1 register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

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23.8 Comparator Response Time

23.9 Analog Input Connection

Considerations

The comparator output is indeterminate for a period of

time after the change of an input source or the selection

of a new reference voltage. This period is referred to as

the response time. The response time of the comparator

differs from the settling time of the voltage reference.

Therefore, both of these times must be considered when

determining the total response time to a comparator

input change. See the Comparator and Voltage

Reference Specifications in Table 37-14 for more

details.

A simplified circuit for an analog input is shown in

Figure 23-3. Since the analog input pins share their

connection with a digital input, they have reverse

biased ESD protection diodes to VDD and VSS. The

analog input, therefore, must be between VSS and VDD.

If the input voltage deviates from this range by more

than 0.6V in either direction, one of the diodes is

forward biased and a latch-up may occur.

A maximum source impedance of 10 k is recommended

for the analog sources. Also, any external component

connected to an analog input pin, such as a capacitor or

a Zener diode, should have very little leakage current to

minimize inaccuracies introduced.

Note 1: When reading a PORT register, all pins

configured as analog inputs will read as a

‘0’. Pins configured as digital inputs will

convert as an analog input, according to

the input specification.

2: Analog levels on any pin defined as a

digital input, may cause the input buffer to

consume more current than is specified.

FIGURE 23-3:

ANALOG INPUT MODEL

VDD

Analog

Input

VT  0.6V

RIC

Rs < 10K

To Comparator

(1)

ILEAKAGE

CPIN

5 pF

VA

VT  0.6V

Vss

Legend: CPIN

= Input Capacitance

ILEAKAGE = Leakage Current at the pin due to various junctions

RIC

RS

VA

= Interconnect Resistance

= Source Impedance

= Analog Voltage

VT

= Threshold Voltage

Note 1: See I/O Ports in Table 37-4.

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23.10 CWG1 Auto-shutdown Source

The output of the comparator module can be used as

an auto-shutdown source for the CWG1 module. When

the output of the comparator is active and the

corresponding ASxE is enabled, the CWG operation

will be suspended immediately (see Section 30.10

“Auto-Shutdown”).

23.11 Operation in Sleep Mode

The comparator module can operate during Sleep. The

comparator clock source is based on the Timer1 clock

source. If the Timer1 clock source is either the system

clock (FOSC) or the instruction clock (FOSC/4), Timer1

will not operate during Sleep, and synchronized

comparator outputs will not operate.

A comparator interrupt will wake the device from Sleep.

The CxIE bits of the PIE2 register must be set to enable

comparator interrupts.

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23.12 Register Definitions: Comparator Control

REGISTER 23-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0

R/W-0/0

ON

R-0/0

OUT

U-0

—

R/W-0/0

POL

U-0

—

U-0

—

R/W-0/0

HYS

R/W-0/0

SYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ON: Comparator Enable bit

1= Comparator is enabled

0= Comparator is disabled and consumes no active power

OUT: Comparator Output bit

If CxPOL = 1(inverted polarity):

1= CxVP < CxVN

0= CxVP > CxVN

If CxPOL = 0(noninverted polarity):

1= CxVP > CxVN

0= CxVP < CxVN

bit 5

bit 4

Unimplemented: Read as ‘0’

POL: Comparator Output Polarity Select bit

1= Comparator output is inverted

0= Comparator output is not inverted

bit 3-2

bit 1

Unimplemented: Read as ‘0’

HYS: Comparator Hysteresis Enable bit

1= Comparator hysteresis enabled

0= Comparator hysteresis disabled

bit 0

SYNC: Comparator Output Synchronous Mode bit

1= Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source.

Output updated on the falling edge of Timer1 clock source.

0= Comparator output to Timer1 and I/O pin is asynchronous

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REGISTER 23-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

INTP

R/W-0/0

INTN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

INTP: Comparator Interrupt on Positive-Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit

0= No interrupt flag will be set on a positive-going edge of the CxOUT bit

bit 0

INTN: Comparator Interrupt on Negative-Going Edge Enable bits

1= The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit

0= No interrupt flag will be set on a negative-going edge of the CxOUT bit

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REGISTER 23-3: CMxNSEL: COMPARATOR Cx NEGATIVE INPUT SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

NCH<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

NCH<2:0>: Comparator Negative Input Channel Select bits

111=CxVN connects to AVSS

110=CxVN connects to FVR Buffer 2

101=CxVN unconnected

100=CxVN unconnected

011=CxVN connects to CxIN3- pin

010=CxVN connects to CxIN2- pin

001=CxVN connects to CxIN1- pin

000=CxVN connects to CxIN0- pin

REGISTER 23-4: CMxPSEL: COMPARATOR Cx POSITIVE INPUT SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

PCH<2:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

PCH<2:0>: Comparator Positive Input Channel Select bits

111=CxVP connects to AVSS

110=CxVP connects to FVR Buffer 2

101=CxVP connects to DAC output

100=CxVP unconnected

011=CxVP unconnected

010=CxVP unconnected

001=CxVP connects to CxIN1+ pin

000=CxVP connects to CxIN0+ pin

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REGISTER 23-5: CMOUT: COMPARATOR OUTPUT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0/0

MC2OUT

MC1OUT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-2

bit 1

Unimplemented: Read as ‘0’

MC2OUT: Mirror Copy of C2OUT bit

MC1OUT: Mirror Copy of C1OUT bit

bit 0

TABLE 23-3: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CMxCON0

CMxCON1

CMOUT

ON

—

OUT

—

POL

—

HYS

INTP

SYNC

INTN

261

262

264

222

243

121

124

132

200

199

—

MC2OUT

MC1OUT

FVRCON

FVREN FVRRDY

TSEN

TSRNG

DAC1OE2

CDAFVR<1:0>

DAC1PSS<1:0>

DAC1R<4:0>

ADFVR<1:0>

DAC1CON0 DAC1EN

—

DAC1OE1

—

DAC1NSS

DAC1CON1

INTCON

PIE2

—

GIE

—

―

PEIE

ZCDIE

ZCDIF

―

INTEDG

C1IE

—

C2IE

C2IF

PIR2

—

C1IF

RxyPPS

CLCINxPPS

T1GPPS

Legend:

―

RxyPPS<4:0>

—

CLCIN0PPS<5:0>

T1GPPS<5:0>

―

— = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module.

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24.1 External Resistor Selection

24.0 ZERO-CROSS DETECTION

(ZCD) MODULE

The ZCD module requires a current limiting resistor in

series with the external voltage source. The impedance

and rating of this resistor depends on the external

source peak voltage. Select a resistor value that will drop

all of the peak voltage when the current through the

^{resistor is nominally 300}A. Refer to Equation 24-1 and

Figure 24-1. Make sure that the ZCD I/O pin internal

weak pull-up is disabled so it does not interfere with the

current source and sink.

The ZCD module detects when an A/C signal crosses

through the ground potential. The actual zero crossing

threshold is the zero crossing reference voltage,

VCPINV, which is typically 0.75V above ground.

The connection to the signal to be detected is through

a series current limiting resistor. The module applies a

current source or sink to the ZCD pin to maintain a

constant voltage on the pin, thereby preventing the pin

voltage from forward biasing the ESD protection

diodes. When the applied voltage is greater than the

reference voltage, the module sinks current. When the

applied voltage is less than the reference voltage, the

module sources current. The current source and sink

action keeps the pin voltage constant over the full

range of the applied voltage. The ZCD module is

shown in the simplified block diagram Figure 24-2.

EQUATION 24-1: EXTERNAL RESISTOR

VPEAK

R^SERIES= ----------------

310^–4

FIGURE 24-1:

EXTERNAL VOLTAGE

The ZCD module is useful when monitoring an A/C

waveform for, but not limited to, the following purposes:

VMAXPEAK

VMINPEAK

VPEAK

• A/C period measurement

• Accurate long term time measurement

• Dimmer phase delayed drive

• Low EMI cycle switching

VCPINV

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FIGURE 24-2:

SIMPLIFIED ZCD BLOCK DIAGRAM

Rev. 10-000194D

VPULLUP

6/10/2016

optional

VDD

RPULLUP

-

ZCDxIN

RSERIES

External

voltage

source

RPULLDOWN

Zcpinv

+

optional

ZCD Output for other modules

ZCDxOUT pin

ZCDxPOL

Interrupt

det

ZCDxINTP

ZCDxINTN

Set

ZCDxIF

flag

Interrupt

det

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24.2 ZCD Logic Output

24.5 Correcting for VCPINV offset

The ZCD module includes a Status bit, which can be

read to determine whether the current source or sink is

active. The OUT bit of the ZCDxCON register is set

when the current sink is active, and cleared when the

current source is active. The OUT bit is affected by the

polarity even if the module is disabled.

The actual voltage at which the ZCD switches is the

reference voltage at the noninverting input of the ZCD

op amp. For external voltage source waveforms other

than square waves, this voltage offset from zero

causes the zero-cross event to occur either too early or

too late.

24.5.1

CORRECTION BY AC COUPLING

24.3 ZCD Logic Polarity

When the external voltage source is sinusoidal then the

effects of the VCPINV offset can be eliminated by isolat-

ing the external voltage source from the ZCD pin with a

capacitor in addition to the voltage reducing resistor.

The capacitor will cause a phase shift resulting in the

ZCD output switch in advance of the actual zero cross-

ing event. The phase shift will be the same for both ris-

ing and falling zero crossings, which can be

compensated for by either delaying the CPU response

to the ZCD switch by a timer or other means, or select-

ing a capacitor value large enough that the phase shift

is negligible.

The POL bit of the ZCDxCON register inverts the

ZCDxOUT bit relative to the current source and sink

output. When the POL bit is set, a logic '1' on the OUT

bit indicates that the current source is active, and a

logic '0' on the OUT bit indicates that the current sink is

active. When the POL bit is clear, a logic '1' on the OUT

bit indicates that the current sink is active, and a logic

'0' on the OUT bit indicates that the current source is

active.

The POL bit affects the ZCD interrupts. See

Section 24.4 “ZCD Interrupts”.

To determine the series resistor and capacitor values

for this configuration, start by computing the imped-

ance, Z, to obtain a peak current of 300 uA. Next, arbi-

trarily select a suitably large non-polar capacitor and

compute its reactance, Xc, at the external voltage

source frequency. Finally, compute the series resistor,

capacitor peak voltage, and phase shift by the formulas

shown in Equation 24-2.

24.4 ZCD Interrupts

An interrupt will be generated upon a change in the

ZCD logic output when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in the ZCD for this purpose.

The ZCDIF bit of the PIR2 register will be set when

either edge detector is triggered and its associated

enable bit is set. The INTP enables rising edge inter-

rupts and the INTN bit enables falling edge interrupts.

Both are located in the ZCDxCON register.

EQUATION 24-2: R-C CALCULATIONS

VPEAK = external voltage source peak voltage

f = external voltage source frequency

C = series capacitor

To fully enable the interrupt, the following bits must be set:

• ZCDIE bit of the PIE2 register

• INTP bit of the ZCDxCON register

(for a rising edge detection)

R = series resistor

VC = Peak capacitor voltage

• INTN bit of the ZCDxCON register

(for a falling edge detection)

 = Capacitor induced zero crossing phase advance

in radians

• PEIE and GIE bits of the INTCON register

T_= Time ZC event occurs before actual zero

crossing

Z = VPEAK/3x10^-4

Changing the POL bit can cause an interrupt,

regardless of the level of the EN bit.

The ZCDIF bit of the PIR2 register must be cleared in

software as part of the interrupt service. If another edge

is detected while this flag is being cleared, the flag will

still be set at the end of the sequence.

Xc = 1/(2fC)

R =  (Z²- Xc²)

VC = Xc(3x10^-4)

 = Tan^-1(Xc/R)

T_= /(2f)

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This offset time can be compensated for by adding a

pull-up or pull-down biasing resistor to the ZCD pin. A

pull-up resistor is used when the external voltage

source is varying relative to VSS. A pull-down resistor is

used when the voltage is varying relative to VDD. The

resistor adds a bias to the ZCD pin so that the target

external voltage source must go to zero to pull the pin

voltage to the VCPINV switching voltage. The pull-up or

pull-down value can be determined with the equation

shown in Equation 24-4.

EXAMPLE 24-1:

VRMS = 120

VPEAK =VRMS* 

f = 60 Hz

C = 0.1 uF

Z = VPEAK/3x10^-4= 169.7/(3x10^-4) = 565.7 kOhms

Xc = 1/(2fC) = 1/(2*60*1*10^-7) = 26.53 kOhms

R =  (Z²- Xc²) = 565.1 kOhms (computed)

R = 560 kOhms (used)

EQUATION 24-4: ZCD PULL-UP/DOWN

ZR =  (R²+ Xc²) = 560.6 kOhms (using actual resis-

tor)

IPEAK = VPEAK/ ZR = 302.7*10^-6

When External Signal is relative to Vss:

VC = Xc* IPEAK = 8.0 V

RSERIESVPULLUP – Vcpinv

RPULLUP = ------------------------------------------------------------------------

Vcpinv

 = Tan^-1(Xc/R) = 0.047 radians

T_= /(2f) = 125.6 us

When External Signal is relative to VDD:

·

24.5.2

CORRECTION BY OFFSET

CURRENT

RSERIES  Vcpinv







RPULLDOWN = -------------------------------------------------



VDD – Vcpinv

When the waveform is varying relative to VSS, then the

zero cross is detected too early as the waveform falls

and too late as the waveform rises. When the

waveform is varying relative to VDD, then the zero cross

is detected too late as the waveform rises and too early

as the waveform falls. The actual offset time can be

determined for sinusoidal waveforms with the

corresponding equations shown in Equation 24-3.

24.6 Handling VPEAK variations

If the peak amplitude of the external voltage is

expected to vary, the series resistor must be selected

to keep the ZCD current source and sink below the

design maximum range of ± 600 A and above a

reasonable minimum range. A general rule of thumb is

that the maximum peak voltage can be no more than

six times the minimum peak voltage. To ensure that the

maximum current does not exceed ± 600 A and the

minimum is at least ± 100 A, compute the series

resistance as shown in Equation 24-5. The

compensating pull-up for this series resistance can be

determined with Equation 24-4 because the pull-up

value is not dependent from the peak voltage.

EQUATION 24-3: ZCD EVENT OFFSET

When External Voltage Source is relative to Vss:

Vcpinv





asin -----------------



_VPEAK

T^OFFSET= ----------------------------------

2  Freq

When External Voltage Source is relative to VDD:

EQUATION 24-5: SERIES R FOR V RANGE

VDD–Vcpinv





asin --------------------------------

VMAXPEAK + VMINPEAK





VPEAK

RSERIES = ---------------------------------------------------------

710^–4

T^OFFSET= ------------------------------------------------

2  Freq

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24.7 Operation During Sleep

The ZCD current sources and interrupts are unaffected

by Sleep.

24.8 Effects of a Reset

The ZCD circuit can be configured to default to the active

or inactive state on Power-on-Reset (POR). When the

ZCDDIS Configuration bit is cleared, the ZCD circuit will

be active at POR. When the ZCD Configuration bit is set,

the EN bit of the ZCDxCON register must be set to

enable the ZCD module.

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24.9 Register Definitions: ZCD Control

REGISTER 24-1: ZCDCON: ZERO-CROSS DETECTION CONTROL REGISTER

R/W-q/q

SEN

U-0

—

R-x/x

OUT

R/W-0/0

POL

U-0

—

U-0

—

R/W-0/0

INTP

R/W-0/0

INTN

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = value depends on Configuration bits

bit 7

SEN: Zero-Cross Detection Enable bit

1= Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current.

0= Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls.

bit 6

bit 5

Unimplemented: Read as ‘0’

OUT: Zero-Cross Detection Logic Level bit

POL bit = 1:

1= ZCD pin is sourcing current

0= ZCD pin is sinking current

POL bit = 0:

1= ZCD pin is sinking current

0= ZCD pin is sourcing current

bit 4

POL: Zero-Cross Detection Logic Output Polarity bit

1= ZCD logic output is inverted

0= ZCD logic output is not inverted

bit 3-2

bit 1

Unimplemented: Read as ‘0’

INTP: Zero-Cross Positive Edge Interrupt Enable bit

1= ZCDIF bit is set on low-to-high ZCDx_output transition

0= ZCDIF bit is unaffected by low-to-high ZCDx_output transition

bit 0

INTN: Zero-Cross Negative Edge Interrupt Enable bit

1= ZCDIF bit is set on high-to-low ZCDx_output transition

0= ZCDIF bit is unaffected by high-to-low ZCDx_output transition

TABLE 24-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE

Register

on page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PIE2

124

132

270

—

ZCDIE

—

C2IE

C1IE

PIR2

—

ZCDIF

—

C2IF

INTP

C1IF

INTN

ZCDxCON

EN

OUT

POL

Legend: — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module.

TABLE 24-2: SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE

Register

on Page

Name

Bits Bit -/7 Bit -/6

Bit 13/5

Bit 12/4

Bit 11/3

Bit 10/2

Bit 9/1

Bit 8/0

STVREN PPS1WAY ZCDDIS

BORV

13:8

7:0

—

DEBUG

—

CONFIG2

77

BOREN <1:0> LPBOREN

—

PWRTE MCLRE

Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module.

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The value of TMR0L is compared to that of the Period

buffer, a copy of TMR0H, on each clock cycle. When

the two values match, the following events happen:

25.0 TIMER0 MODULE

The Timer0 module is an 8/16-bit timer/counter with the

following features:

• TMR0_out goes high for one prescaled clock

period

• 16-bit timer/counter

• 8-bit timer/counter with programmable period

• Synchronous or asynchronous operation

• Selectable clock sources

• Programmable prescaler (independent of

Watchdog Timer)

• TMR0L is reset

• The contents of TMR0H are copied to the period

buffer

In 8-bit mode, the TMR0L and TMR0H registers are

both directly readable and writable. The TMR0L

register is cleared on any device Reset, while the

TMR0H register initializes at FFh.

• Programmable postscaler

• Operation during Sleep mode

• Interrupt on match or overflow

• Output on I/O pin (via PPS) or to other peripherals

Both the prescaler and postscaler counters are cleared

on the following events:

• A write to the TMR0L register

• A write to either the T0CON0 or T0CON1

registers

• Any device Reset – Power-on Reset (POR),

MCLR Reset, Watchdog Timer Reset (WDTR) or

25.1 Timer0 Operation

Timer0 can operate as either an 8-bit timer/counter or

a 16-bit timer/counter. The mode is selected with the

T016BIT bit of the T0CON register.

•

Brown-out Reset (BOR)

25.1.1

16-BIT MODE

25.1.3 COUNTER MODE

In normal operation, TMR0 increments on the rising

edge of the clock source. A 15-bit prescaler on the

clock input gives several prescale options (see

prescaler control bits, T0CKPS<3:0> in the T0CON1

register).

In Counter mode, the prescaler is normally disabled by

setting the T0CKPS bits of the T0CON1 register to

‘0000’. Each rising edge of the clock input (or the

output of the prescaler if the prescaler is used)

increments the counter by ‘1’.

25.1.1.1

Timer0 Reads and Writes in 16-Bit

Mode

25.1.4

TIMER MODE

TMR0H is not the actual high byte of Timer0 in 16-bit

mode. It is actually a buffered version of the real high

byte of Timer0, which is neither directly readable nor

writable (see Figure 25-1). TMR0H is updated with the

contents of the high byte of Timer0 during a read of

TMR0L. This provides the ability to read all 16 bits of

Timer0 without having to verify that the read of the high

and low byte was valid, due to a rollover between

successive reads of the high and low byte.

In Timer mode, the Timer0 module will increment every

instruction cycle as long as there is a valid clock signal

and the T0CKPS bits of the T0CON1 register

(Register 25-2) are set to ‘0000’. When a prescaler is

added, the timer will increment at the rate based on the

prescaler value.

25.1.5

ASYNCHRONOUS MODE

When the T0ASYNC bit of the T0CON1 register is set

(T0ASYNC = ‘1’), the counter increments with each

rising edge of the input source (or output of the

prescaler, if used). Asynchronous mode allows the

counter to continue operation during Sleep mode

provided that the clock also continues to operate during

Sleep.

Similarly, a write to the high byte of Timer0 must also

take place through the TMR0H Buffer register. The high

byte is updated with the contents of TMR0H when a

write occurs to TMR0L. This allows all 16 bits of Timer0

to be updated at once.

25.1.2

8-BIT MODE

25.1.6

SYNCHRONOUS MODE

In normal operation, TMR0 increments on the rising

edge of the clock source. A 15-bit prescaler on the

clock input gives several prescale options (see

prescaler control bits, T0CKPS<3:0> in the T0CON1

register).

When the T0ASYNC bit of the T0CON1 register is clear

(T0ASYNC = 0), the counter clock is synchronized to

the system oscillator (FOSC/4). When operating in

Synchronous mode, the counter clock frequency

cannot exceed FOSC/4.

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25.2 Clock Source Selection

25.5 Operation during Sleep

The T0CS<2:0> bits of the T0CON1 register are used

to select the clock source for Timer0. Register 25-2

displays the clock source selections.

When operating synchronously, Timer0 will halt. When

operating asynchronously, Timer0 will continue to

increment and wake the device from Sleep (if Timer0

interrupts are enabled) provided that the input clock

source is active.

25.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected, Timer0

operates as a timer and will increment on multiples of

the clock source, as determined by the Timer0

prescaler.

25.6 Timer0 Interrupts

The Timer0 interrupt flag bit (TMR0IF) is set when

either of the following conditions occur:

25.2.2

EXTERNAL CLOCK SOURCE

• 8-bit TMR0L matches the TMR0H value

• 16-bit TMR0 rolls over from ‘FFFFh’

When an external clock source is selected, Timer0 can

operate as either a timer or a counter. Timer0 will

increment on multiples of the rising edge of the external

clock source, as determined by the Timer0 prescaler.

When the postscaler bits (T0OUTPS<3:0>) are set to

1:1 operation (no division), the T0IF flag bit will be set

with every TMR0 match or rollover. In general, the

TMR0IF flag bit will be set every T0OUTPS +1 matches

or rollovers.

25.3 Programmable Prescaler

If Timer0 interrupts are enabled (TMR0IE bit of the

PIE0 register = 1), the CPU will be interrupted and the

device may wake from sleep (see Section 25.2 “Clock

Source Selection” for more details).

A software programmable prescaler is available for

exclusive use with Timer0. There are 16 prescaler

options for Timer0 ranging in powers of two from 1:1 to

1:32768. The prescaler values are selected using the

T0CKPS<3:0> bits of the T0CON1 register.

25.7 Timer0 Output

The prescaler is not directly readable or writable.

Clearing the prescaler register can be done by writing

to the TMR0L register or the T0CON1 register.

The Timer0 output can be routed to any I/O pin via the

RxyPPS output selection register (see Section 15.0

“Peripheral Pin Select (PPS) Module” for additional

information). The Timer0 output can also be used by

other peripherals, such as the Auto-conversion Trigger

of the Analog-to-Digital Converter. Finally, the Timer0

output can be monitored through software via the

Timer0 output bit (T0OUT) of the T0CON0 register

(Register 25-1).

25.4 Programmable Postscaler

A software programmable postscaler (output divider) is

available for exclusive use with Timer0. There are 16

postscaler options for Timer0 ranging from 1:1 to 1:16.

The postscaler values are selected using the

T0OUTPS<3:0> bits of the T0CON0 register.

TMR0_out will be one postscaled clock period when a

match occurs between TMR0L and TMR0H in 8-bit

mode, or when TMR0 rolls over in 16-bit mode. The

Timer0 output is a 50% duty cycle that toggles on each

TMR0_out rising clock edge.

The postscaler is not directly readable or writable.

Clearing the postscaler register can be done by writing

to the TMR0L register or the T0CON0 register.

In the 16-bit mode, if the postscaler option is selected

to a ratio other than 1:1, the reload of the TMR0H and

TMR0L registers is not possible inside the Interrupt

Service Routine. The timer period must be calculated

with the prescaler and postscaler factors selected.

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FIGURE 25-1:

BLOCK DIAGRAM OF TIMER0

Rev. 10-000017D

4/6/2017

CLC1

SOSC

111

110

MFINTOSC

LFINTOSC

HFINTOSC

FOSC/4

101

100

011

010

001

000

Peripherals

TMR0

body

T0CKPS<3:0>

T0OUTPS<3:0>

T0IF

1

Prescaler

IN

OUT

T0_out

TMR0

Postscaler

0

SYNC

FOSC/4

T016BIT

PPS

T0ASYNC

D

Q

PPS

T0CKIPPS

RxyPPS

CK

3

T0CS<2:0>

16-bit TMR0 Body Diagram (T016BIT = 1)

8-bit TMR0 Body Diagram (T016BIT = 0)

Clear

IN

TMR0 High

Byte

OUT

IN

R

TMR0L

8

Read TMR0L

Write TMR0L

COMPARATOR

OUT

T0_match

8

TMR0H

TMR0 High

Byte

Latch

Enable

8

TMR0H

8

Internal Data Bus

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25.8 Register Definitions: Timer0 Control

REGISTER 25-1: T0CON0: TIMER0 CONTROL REGISTER 0

R/W-0/0

T0EN

U-0

—

R-0

R/W-0/0

T016BIT

R/W-0/0

T0OUT

T0OUTPS<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

T0EN: Timer0 Enable bit

1 = The module is enabled and operating

0 = The module is disabled and in the lowest power mode

bit 6

bit 5

Unimplemented: Read as ‘0’

T0OUT: Timer0 Output bit (read-only)

Timer0 output bit

bit 4

T016BIT: Timer0 Operating as 16-bit Timer Select bit

1 = Timer0 is a 16-bit timer

0= Timer0 is an 8-bit timer

bit 3-0

T0OUTPS<3:0>: Timer0 output postscaler (divider) select bits

1111= 1:16 Postscaler

1110= 1:15 Postscaler

1101= 1:14 Postscaler

1100= 1:13 Postscaler

1011= 1:12 Postscaler

1010= 1:11 Postscaler

1001= 1:10 Postscaler

1000= 1:9 Postscaler

0111= 1:8 Postscaler

0110= 1:7 Postscaler

0101= 1:6 Postscaler

0100= 1:5 Postscaler

0011= 1:4 Postscaler

0010= 1:3 Postscaler

0001= 1:2 Postscaler

0000= 1:1 Postscaler

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REGISTER 25-2: T0CON1: TIMER0 CONTROL REGISTER 1

R/W-0/0

bit 0

T0CS<2:0>

T0ASYNC

T0CKPS<3:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-5

T0CS<2:0>: Timer0 Clock Source select bits

111= LC1_out

110= SOSC

101= MFINTOSC (500 kHz)

100= LFINTOSC

011= HFINTOSC

010= FOSC/4

001= T0CKIPPS (Inverted)

000= T0CKIPPS (True)

bit 4

T0ASYNC: TMR0 Input Asynchronization Enable bit

1 = The input to the TMR0 counter is not synchronized to system clocks

0= The input to the TMR0 counter is synchronized to FOSC/4

bit 3-0

T0CKPS<3:0>: Prescaler Rate Select bit

1111= 1:32768

1110= 1:16384

1101= 1:8192

1100= 1:4096

1011= 1:2048

1010= 1:1024

1001= 1:512

1000= 1:256

0111= 1:128

0110= 1:64

0101= 1:32

0100= 1:16

0011= 1:8

0010= 1:4

0001= 1:2

0000= 1:1

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TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

TMR0L

Holding Register for the Least Significant Byte of the 16-bit TMR0 Register

Holding Register for the Most Significant Byte of the 16-bit TMR0 Register

271*

274

TMR0H

T0CON0

T0CON1

T0CKIPPS

TMR0PPS

T1GCON

INTCON

PIR0

T0EN

―

T0CS<2:0>

―

T0OUT

T016BIT

T0OUTPS<3:0>

T0CKPS<3:0>

T0ASYNC

275

―

T0CKIPPS<5:0>

TMR0PPS<5:0>

GGO/DONE GVAL

199

287

121

130

122

―

GE

GIE

―

GPOL

PEIE

―

GTM

―

GSPM

―

—

―

—

―

INTEDG

INTF

TMR0IF

TMR0IE

IOCIF

IOCIE

PIE0

―

INTE

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.

*

Page with Register information.

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• Wake-up on overflow (external clock,

Asynchronous mode only)

26.0 TIMER1 MODULE WITH GATE

CONTROL

• Time base for the Capture/Compare function

• Auto-conversion Trigger (with CCP)

• Selectable Gate Source Polarity

• Gate Toggle mode

The Timer1 module is 16-bit timer/counters with the

following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Gate Single-Pulse mode

• Gate Value Status

• Clock source for optional comparator

synchronization

• Gate Event Interrupt

Figure 26-1 is a block diagram of the Timer1 module.

This device has one instance of Timer1 type modules.

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

FIGURE 26-1:

TIMER1 BLOCK DIAGRAM

Rev. 10-000018J

8/15/2016

TMRxGATE<4:0>

4

TxGPPS

PPS

TxGSPM

00000

1

0

D

Q

TxGVAL

0

1

Single Pulse

Acq. Control

NOTE (5)

11111

Q1

D

Q

TxGGO/DONE

TxGPOL

TMRxON

TxGTM

CK

R

Q

Interrupt

det

set bit

TMRxGIF

TMRxGE

set flag bit

TMRxIF

TMRxON

EN

D

To Comparators (6)

Synchronized Clock Input

TMRx⁽²⁾

TMRxH TMRxL

Tx_overflow

Q

0

1

TxCLK

TxSYNC

TMRxCLK<3:0>

4

TxCKIPPS

PPS

(1)

0000

Prescaler

1,2,4,8

Synchronize⁽³⁾

Note ⁽⁴⁾

det

1111

2

Fosc/2

Internal

Clock

TxCKPS<1:0>

Sleep

Input

Note 1: ST Buffer is high speed type when using TxCKIPPS.

2: TMRx register increments on rising edge.

3: Synchronize does not operate while in Sleep.

4: See Register 26-3 for Clock source selections.

5: See Register 26-4 for GATE source selections.

6: Synchronized comparator output should not be used in conjunction with synchronized input clock.

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26.1 Timer1 Operation

26.2 Clock Source Selection

The Timer1 modules are 16-bit incrementing counters

which are accessed through the TMR1H:TMR1L

register pairs. Writes to TMR1H or TMR1L directly

update the counter.

The T1CLK register is used to select the clock source for

the timer. Register 26-3 shows the possible clock

sources that may be selected to make the timer

increment.

When used with an internal clock source, the module is

a timer and increments on every instruction cycle.

When used with an external clock source, the module

can be used as either a timer or counter and incre-

ments on every selected edge of the external source.

26.2.1

INTERNAL CLOCK SOURCE

When the internal clock source FOSC is selected, the

TMR1H:TMR1L register pair will increment on multiples

of FOSC as determined by the respective Timer1

prescaler.

The timer is enabled by configuring the TMR1ON and

GE bits in the T1CON and T1GCON registers,

respectively. Table 26-1 displays the Timer1 enable

selections.

When the FOSC internal clock source is selected, the

timer register value will increment by four counts every

instruction clock cycle. Due to this condition, a 2 LSB

error in resolution will occur when reading the

TMR1H:TMR1L value. To utilize the full resolution of the

timer in this mode, an asynchronous input signal must

be used to gate the timer clock input.

TABLE 26-1: TIMER1 ENABLE

SELECTIONS

Timer1

Operation

Out of the total timer gate signal sources, the following

subset of sources can be asynchronous and may be

useful for this purpose:

TMR1ON

TMR1GE

1

0

1

0

1

0

Count Enabled

• CLC4 output

Always On

• CLC3 output

Off

• CLC2 output

• CLC1 output

• Zero-Cross Detect output

• Comparator2 output

• Comparator1 output

• TxG PPS remappable input pin

26.2.2

EXTERNAL CLOCK SOURCE

When the timer is enabled and the external clock input

source (ex: T1CKI PPS remappable input) is selected as

the clock source, the timer will increment on the rising

edge of the external clock input.

When using an external clock source, the timer can be

configured to run synchronously or asynchronously, as

described in Section 26.6 “Timer Operation in

Asynchronous Mode”.

When used as a timer with a clock oscillator, an

external 32.768 kHz crystal can be used connected to

the SOSCI/SOSCO pins.

Note:

When using Timer1 to count events, a fall-

ing edge must be registered by the

counter prior to the first incrementing ris-

ing edge after any one or more of the fol-

lowing conditions:

•The timer is first enabled after POR

•Firmware writes to TMR1H or TMR1L

•The timer is disabled

•The timer is re-enabled (e.g.,

TMR1ON-->1) when the T1CKI

signal is currently logic low.

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ability to accurately read all 16 bits of Timer1 without

having to determine whether a read of the high byte,

followed by a read of the low byte, has become invalid

due to a rollover between reads.

26.3 Timer Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The CKPS bits of the

T1CON register control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

A write to the high byte of Timer1 must also take place

through the TMR1H Buffer register. The Timer1 high

byte is updated with the contents of TMR1H when a

write occurs to TMR1L. This allows a user to write all 16

bits at once to

26.4 Timer1 16-Bit Read/Write Mode

both the high and low bytes of Timer1. The high byte of

Timer1 is not directly readable or writable in this mode.

All reads and writes must take place through the Timer1

High Byte Buffer register. Writes to TMR1H do not clear

Timer1 can be configured for 16-bit reads and writes.

When the RD16 control bit (T1CON<1>) is set, the

address for TMR1H is mapped to a buffer register for the

high byte of Timer1. A read from TMR1L loads the

contents of the high byte of Timer1 into the Timer1 High

Byte Buffer register. This provides the user with the

the Timer1 prescaler. The prescaler is only cleared on

writes to TMR1L.

FIGURE 26-2:

TIMER1 16-BIT READ/WRITE MODE BLOCK DIAGRAM

Rev. 10-000017H

4/28/2017

16-bit TMR1/3/5 Body Diagram (RD16 = 1)

IN

OUT

TMR1L

TMR1 High Byte

8

Read TMR1L

Write TMR1L

8

TMR1H

8

Internal Data Bus

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26.6.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS MODE

26.5 Secondary Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is

built-in between pins SOSCI (input) and SOSCO

(amplifier output). This internal circuit is designed to be

used in conjunction with an external 32.768 kHz

crystal.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

The oscillator circuit is enabled by setting the SOSCEN

bit of the OSCEN register. The oscillator will continue to

run during Sleep.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the TMR1H:TMR1L register pair.

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

SOSCEN should be set and a suitable

delay observed prior to using Timer1 with

the SOSC source. A suitable delay similar

to the OST delay can be implemented in

software by clearing the TMR1IF bit then

presetting the TMR1H:TMR1L register

pair to FC00h. The TMR1IF flag will be set

when 1024 clock cycles have elapsed,

thereby indicating that the oscillator is

running and reasonably stable.

26.7 Timer Gate

Timer1 can be configured to count freely or the count

can be enabled and disabled using the time gate

circuitry. This is also referred to as Timer Gate Enable.

The timer gate can also be driven by multiple select-

able sources.

26.7.1

TIMER GATE ENABLE

26.6 Timer Operation in Asynchronous

Mode

The Timer Gate Enable mode is enabled by setting the

GE bit of the T1GCON register. The polarity of the

Timer Gate Enable mode is configured using the GPOL

bit of the T1GCON register.

If the control bit SYNC of the T1CON register is set, the

external clock input is not synchronized. The timer

increments asynchronously to the internal phase

clocks. If the external clock source is selected then the

timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 26.6.1 “Reading and Writing Timer1 in

Asynchronous Mode”).

When Timer Gate Enable signal is enabled, the timer

will increment on the rising edge of the Timer1 clock

source. When Timer Gate Enable signal is disabled,

the timer always increments, regardless of the GE bit.

See Figure 26-4 for timing details.

TABLE 26-2: TIMER GATE ENABLE

SELECTIONS

Note:

When switching from synchronous to

asynchronous operation, it is possible to

skip an increment. When switching from

asynchronous to synchronous operation,

it is possible to produce an additional

increment.

T1CLK T1GPOL

T1G

Timer Operation



1

0

1

0

1

0

Counts

Holds Count

Counts

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26.7.2

TIMER GATE SOURCE SELECTION

26.7.4

TIMER1 GATE SINGLE-PULSE

MODE

One of the several different external or internal signal

sources may be chosen to gate the timer and allow the

timer to increment. The gate input signal source can be

selected based on the T1GATE register setting. See the

T1GATE register (Register 26-4) description for a

complete list of the available gate sources. The polarity

for each available source is also selectable. Polarity

selection is controlled by the GPOL bit of the T1GCON

register.

When Timer1 Gate Single-Pulse mode is enabled, it is

possible to capture a single-pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

GSPM bit in the T1GCON register. Next, the GGO/

DONE bit in the T1GCON register must be set. The

timer will be fully enabled on the next incrementing

edge. On the next trailing edge of the pulse, the GGO/

DONE bit will automatically be cleared. No other gate

events will be allowed to increment the timer until the

GGO/DONE bit is once again set in software. See

Figure 26-6 for timing details.

26.7.2.1

T1G Pin Gate Operation

The T1G pin is one source for the timer gate control. It

can be used to supply an external source to the time

gate circuitry.

If the Single-Pulse Gate mode is disabled by clearing the

GSPM bit in the T1GCON register, the GGO/DONE bit

should also be cleared.

26.7.2.2

Timer0 Overflow Gate Operation

Enabling the Toggle mode and the Single-Pulse mode

simultaneously will permit both sections to work

together. This allows the cycle times on the timer gate

source to be measured. See Figure 26-7 for timing

details.

When Timer0 overflows, or a period register match

condition occurs (in 8-bit mode), a low-to-high pulse will

automatically be generated and internally supplied to

the Timer1 gate circuitry.

26.7.2.3

Comparator C1 Gate Operation

26.7.5

TIMER1 GATE VALUE STATUS

The output resulting from a Comparator 1 operation can

be selected as a source for the timer gate control. The

Comparator 1 output can be synchronized to the timer

clock or left asynchronous. For more information see

When Timer1 Gate Value Status is utilized, it is possible

to read the most current level of the gate control value.

The value is stored in the GVAL bit in the T1GCON reg-

ister. The GVAL bit is valid even when the timer gate is

not enabled (GE bit is cleared).

Section 23.4.1

“Comparator

Output

Synchronization”.

26.7.6

TIMER1 GATE EVENT INTERRUPT

26.7.2.4

Comparator C2 Gate Operation

When Timer1 Gate Event Interrupt is enabled, it is

possible to generate an interrupt upon the completion

of a gate event. When the falling edge of GVAL occurs,

the TMR1GIF flag bit in the PIR5 register will be set. If

the TMR1GIE bit in the PIE5 register is set, then an

interrupt will be recognized.

The output resulting from a Comparator 2 operation

can be selected as a source for the timer gate control.

The Comparator 2 output can be synchronized to the

timer clock or left asynchronous. For more information

see

Section 23.4.1

“Comparator

Output

Synchronization”.

The TMR1GIF flag bit operates even when the timer

gate is not enabled (TMR1GE bit is cleared).

26.7.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possi-

ble to measure the full-cycle length of a timer gate sig-

nal, as opposed to the duration of a single level pulse.

The timer gate source is routed through a flip-flop that

changes state on every incrementing edge of the

signal. See Figure 26-5 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

GTM bit of the T1GCON register. When the GTM bit is

cleared, the flip-flop is cleared and held clear. This is

necessary in order to control which edge is measured.

Note:

Enabling Toggle mode at the same time

as changing the gate polarity may result in

indeterminate operation.

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26.8 Timer1 Interrupts

26.10 CCP Capture/Compare Time Base

The timer register pair (TMR1H:TMR1L) increments to

FFFFh and rolls over to 0000h. When the timer rolls

over, the respective timer interrupt flag bit of the PIR5

register is set. To enable the interrupt on rollover, you

must set these bits:

The CCP modules use the TMR1H:TMR1L register

pair as the time base when operating in Capture or

Compare mode.

In Capture mode, the value in the TMR1H:TMR1L

register pair is copied into the CCPRxH:CCPRxL

register pair on a configured event.

• ON bit of the T1CON register

• TMR1IE bit of the PIE4 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

In Compare mode, an event is triggered when the value

CCPRxH:CCPRxL register pair matches the value in

the TMR1H:TMR1L register pair. This event can be an

Auto-conversion Trigger.

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

For more information, see Section 28.0 “Capture/

Compare/PWM Modules”.

26.11 CCP Auto-Conversion Trigger

Note:

To avoid immediate interrupt vectoring,

the TMR1H:TMR1L register pair should

be preloaded with a value that is not immi-

nently about to rollover, and the TMR1IF

flag should be cleared prior to enabling

the timer interrupts.

When any of the CCP’s are configured to trigger an

auto-conversion, the trigger will clear the

TMR1H:TMR1L register pair. This auto-conversion

does not cause a timer interrupt. The CCP module may

still be configured to generate a CCP interrupt.

In this mode of operation, the CCPRxH:CCPRxL

register pair becomes the period register for Timer1.

26.9 Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

The timer should be synchronized and FOSC/4 should

be selected as the clock source in order to utilize the

Auto-conversion Trigger. Asynchronous operation of

the timer can cause an Auto-conversion Trigger to be

missed.

• ON bit of the T1CON register must be set

• TMR1IE bit of the PIE4 register must be set

• PEIE bit of the INTCON register must be set

• SYNC bit of the T1CON register must be set

• CS bits of the T1CLK register must be configured

In the event that a write to TMR1H or TMR1L coincides

with an Auto-conversion Trigger from the CCP, the

write will take precedence.

For more information, see Section 28.2.4 “Compare

During Sleep”.

• The timer clock source must be enabled and

continue operation during sleep. When the SOSC

is used for this purpose, the SOSCEN bit of the

OSCEN register must be set.

The device will wake-up on an overflow and execute

the next instructions. If the GIE bit of the INTCON

register is set, the device will call the Interrupt Service

Routine.

Secondary oscillator will continue to operate in Sleep

regardless of the SYNC bit setting.

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FIGURE 26-3:

TIMER1 INCREMENTING EDGE

TxCKI = 1

when the timer is

enabled

TxCKI = 0

when the timer is

enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

FIGURE 26-4:

TIMER1 GATE ENABLE MODE

TMRxGE

TxGPOL

Selected

gate input

TxCKI

TxGVAL

TMRxH:TMRxL

Count

N

N + 1

N + 2

N + 3

N + 4

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FIGURE 26-5:

TIMER1 GATE TOGGLE MODE

TMRxGE

TxGPOL

TxGTM

Selected

gate input

TxCKI

TxGVAL

N

N + 1 N + 2 N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

TMRxH:TMRxL

Count

FIGURE 26-6:

TIMER1 GATE SINGLE-PULSE MODE

TMRxGE

TxGPOL

TxGSPM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of selected source

Selected gate

source

TxCKI

TxGVAL

TMRxH:TMRxL

Count

N

N + 1

N + 2

Cleared by

software

Set by hardware on

falling edge of TxGVAL

Cleared by software

TMRxGIF

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FIGURE 26-7:

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE

TMRxGE

TxGPOL

TxGSPM

TxGTM

Cleared by hardware on

falling edge of TxGVAL

TxGGO/

DONE

Set by software

Counting enabled on

rising edge of selected source

Selected gate

source

TxCKI

TxGVAL

TMRxH:TMRxL

Count

N + 2

N + 3 N + 4

N

N + 1

Set by hardware on

falling edge of TxGVAL

Cleared by

software

Cleared by software

TMRxGIF

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26.12 Register Definitions: Timer1 Control

REGISTER 26-1: T1CON: TIMER1 CONTROL REGISTER

U-0

—

U-0

—

R/W-0/u

U-0

—

R/W-0/u

SYNC

R/W-0/u

RD16

R/W-0/u

ON

CKPS<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11=1:8 Prescale value

10=1:4 Prescale value

01=1:2 Prescale value

00=1:1 Prescale value

bit 3

bit 2

Unimplemented: Read as ‘0’

SYNC: Timer1 Synchronization Control bit

When TMR1CLK = FOSC or FOSC/4

This bit is ignored. The timer uses the internal clock and no additional synchronization is performed.

ELSE

0= Synchronize external clock input with system clock

1= Do not synchronize external clock input

bit 1

bit 0

RD16: 16-bit Read/Write Mode Enable bit

0= Enables register read/write of Timer1 in two 8-bit operation

1= Enables register read/write of Timer1 in one 16-bit operation

ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1 and clears Timer1 gate flip-flop

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REGISTER 26-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

GE

R/W-0/u

GPOL

R/W-0/u

GTM

R/W-0/u

GSPM

R/W/HC-0/u

GGO/DONE

R-x/x

U-0

—

U-0

—

GVAL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

GE: Timer1 Gate Enable bit

If ON = 0:

This bit is ignored

If ON = 1:

1= Timer1 counting is controlled by the Timer1 gate function

0= Timer1 is always counting

bit 6

bit 5

GPOL: Timer1 Gate Polarity bit

1= Timer1 gate is active-high (Timer1 counts when gate is high)

0= Timer1 gate is active-low (Timer1 counts when gate is low)

GTM: Timer1 Gate Toggle Mode bit

1= Timer1 Gate Toggle mode is enabled

0= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

bit 4

bit 3

GSPM: Timer1 Gate Single-Pulse Mode bit

1= Timer1 Gate Single-Pulse mode is enabled

0= Timer1 Gate Single-Pulse mode is disabled

GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit

1= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0= Timer1 gate single-pulse acquisition has completed or has not been started

This bit is automatically cleared when GSPM is cleared

bit 2

GVAL: Timer1 Gate Value Status bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L

Unaffected by Timer1 Gate Enable (GE)

bit 1-0

Unimplemented: Read as ‘0’

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REGISTER 26-3: T1CLK TIMER1 CLOCK SELECT REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/u

CS<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

CS<3:0>: Timer1 Clock Select bits

1111= Reserved

1110= Reserved

1101= LC4_out

1100= LC3_out

1011= LC2_out

1010= LC1_out

1001= Timer0 overflow output

1000= CLKR output

0111= SOSC

0110= MFINTOSC (32 kHz)

0101= MFINTOSC (500 kHz)

0100= LFINTOSC

0011= HFINTOSC

0010= FOSC

0001= FOSC/4

0000= T1CKIPPS

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REGISTER 26-4: T1GATE TIMER1 GATE SELECT REGISTER

U-0

—

U-0

—

U-0

—

R/W-0/u

GSS<4:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

GSS<4:0>: Timer1 Gate Select bits

11111-10001= Reserved

10000= LC4_out

01111= LC3_out

01110= LC2_out

01101= LC1_out

00100= ZCD1_output

01011= C2OUT_sync

01010= C1OUT_sync

01001= NCO1_out

01000= PWM6_out

00111= PWM5_out

00110= PWM4_out

00101= PWM3_out

00100= CCP2_out

00011= CCP1_out

00010= TMR2_postscaled

00001= Timer0 overflow output

00000= T1GPPS

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TABLE 26-3: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE4

GIE

—

PEIE

—

―

—

―

—

―

—

―

—

―

INTEDG

TMR1IE

TMR1IF

121

126

134

286

287

TMR2IE

TMR2IF

PIR4

—

T1CON

—

CKPS<1:0>

—

SYNC

GVAL

RD16

—

ON

—

T1GCON

GE

GPOL

GTM

—

GSPM

GGO/DONE

T1GATE

T1CLK

—

GSS<4:0>

289

288

277*

199

319

364

236

—

CS<3:0>

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1H

T1CKIPPS

T1GPPS

CCPxCON

CLCxSELy

ADACT

―

T1CKIPPS<5:0>

T1GPPS<5:0>

―

CCPxEN

―

CCPxOE CCPxOUT CCPxFMT

CCPxMODE<3:0>

LCxDyS<4:0>

ADACT<4:0>

―

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used with the Timer1 modules.

*

Page with register information.

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• Selectable external hardware timer Resets

• Programmable prescaler (1:1 to 1:128)

• Programmable postscaler (1:1 to 1:16)

• Selectable synchronous/asynchronous operation

• Alternate clock sources

27.0 TIMER2 MODULE WITH

HARDWARE LIMIT TIMER (HLT)

The Timer2 module is an 8-bit timer that can operate as

free-running period counters or in conjunction with

external signals that control start, run, freeze, and reset

operation in One-Shot and Monostable modes of

operation. Sophisticated waveform control such as

pulse density modulation are possible by combining the

operation of this timer with other internal peripherals

such as the comparators and CCP modules. Features

of the timer include:

• Interrupt-on-period

• Three modes of operation:

- Free Running Period

- One-shot

- Monostable

See Figure 27-1 for a block diagram of Timer2. See

Figure 27-2 for the clock source block diagram.

• 8-bit timer register

• 8-bit period register

FIGURE 27-1:

TIMER2 BLOCK DIAGRAM

Rev. 10-000168C

9/10/2015

RSEL <ꢋ:0>

INPPS

TxIN

PPS

MODE<4:0>

MODE<3>

reset

Edge Detector

Level Detector

Mode Control

(2 clock Sync)

External

Reset

CCP_pset⁽¹⁾

TMRx_ers

(2)

Sources

MODE<4:3>=01

MODE<4:1>=1011

enable

Clear ON

D

Q

CPOL

TMRx_clk

Prescaler

3

0

T[7MR^R

Comparator

7[PR

Set flag bit

TMRxIF

Sync

1

Fosc/4

CKPS<2:0>

PSYNC

TMRx_postscaled

Postscaler

4

Sync

(2 Clocks)

ON

1

0

OUTPS<3:0>

CSYNC

Note 1: Signal to the CCP to trigger the PWM pulse.

2: See Register 27-4 for external Reset sources.

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the output postscaler counter. When the postscaler

count equals the value in the OUTPS<4:0> bits of the

TMR2CON1 register, a one TMR2_clk period wide pulse

occurs on the TMR2_postscaled output, and the

postscaler count is cleared.

FIGURE 27-2:

TIMER2 CLOCK SOURCE

BLOCK DIAGRAM

TxCLKCON

INPPS

IN PPS

Rev. 10-000 169B

5/29/201 4

TX

27.1.2

ONE-SHOT MODE

TX

The One-Shot mode is identical to the Free Running

Period mode except that the ON bit is cleared and the

timer is stopped when TMR2 matches PR2 and will not

restart until the T2ON bit is cycled off and on.

Postscaler OUTPS<4:0> values other than 0 are

meaningless in this mode because the timer is stopped

at the first period event and the postscaler is reset

when the timer is restarted.

Timer Clock Sources

(See Table 27-2)

TMR2_clk

27.1.3

MONOSTABLE MODE

Monostable modes are similar to One-Shot modes

except that the ON bit is not cleared and the timer can

be restarted by an external Reset event.

27.1 Timer2 Operation

Timer2 operates in three major modes:

27.2 Timer2 Output

• Free Running Period

• One-shot

The Timer2 module’s primary output is TMR2_posts-

caled, which pulses for a single TMR2_clk period when

the postscaler counter matches the value in the

OUTPS bits of the TMR2CON register. The PR2 post-

scaler is incremented each time the TMR2 value

matches the PR2 value. This signal can be selected as

an input to several other input modules:

• Monostable

Within each mode there are several options for starting,

stopping, and reset. Table 27-1 lists the options.

In all modes, the TMR2 count register is incremented

on the rising edge of the clock signal from the program-

mable prescaler. When TMR2 equals PR2, a high level

is output to the postscaler counter. TMR2 is cleared on

the next clock input.

• The ADC module, as an Auto-conversion Trigger

• COG, as an auto-shutdown source

In addition, the Timer2 is also used by the CCP module

for pulse generation in PWM mode. Both the actual

TMR2 value as well as other internal signals are sent to

the CCP module to properly clock both the period and

pulse width of the PWM signal. See Section 28.0

“Capture/Compare/PWM Modules” for more details

on setting up Timer2 for use with the CCP, as well as

the timing diagrams in Section 27.5 “Operation

Examples” for examples of how the varying Timer2

modes affect CCP PWM output.

An external signal from hardware can also be config-

ured to gate the timer operation or force a TMR2 count

Reset. In Gate modes the counter stops when the gate

is disabled and resumes when the gate is enabled. In

Reset modes the TMR2 count is reset on either the

level or edge from the external source.

The TMR2 and PR2 registers are both directly readable

and writable. The TMR2 register is cleared and the

PR2 register initializes to FFh on any device Reset.

Both the prescaler and postscaler counters are cleared

on the following events:

27.3 External Reset Sources

In addition to the clock source, the Timer2 also takes in

an external Reset source. This external Reset source

is selected for Timer2 with the T2RST register. This

source can control starting and stopping of the timer, as

well as resetting the timer, depending on which mode

the timer is in. The mode of the timer is controlled by

the MODE<4:0> bits of the TMR2HLT register. Edge-

Triggered modes require six Timer clock periods

between external triggers. Level-Triggered modes

require the triggering level to be at least three Timer

clock periods long. External triggers are ignored while

in Debug Freeze mode.

• a write to the TMR2 register

• a write to the T2CON register

• any device Reset

• External Reset Source event that resets the timer.

Note:

TMR2 is not cleared when T2CON is

written.

27.1.1

FREE RUNNING PERIOD MODE

The value of TMR2 is compared to that of the Period

register, PR2, on each TMR2_clk cycle. When the two

values match, the comparator resets the value of TMR2

to 00h on the next rising TMR2_clk edge and increments

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TABLE 27-1: TIMER2 OPERATING MODES

MODE<4:0>

Output

Timer Control

Mode

Operation

<4:3> <2:0>

Start

Reset

Stop

000

Software gate (Figure 27-4)

ON = 1

—

ON = 0

Hardware gate, active-high

(Figure 27-5)

ON = 1and

TMRx_ers = 1

ON = 0or

TMRx_ers = 0

001

010

Period

Pulse

ON = 1and

TMRx_ers = 0

—

ON = 0or

TMRx_ers = 1

Hardware gate, active-low

Free

Running

Period

011

00

Rising or falling edge Reset

Rising edge Reset (Figure 27-6)

Falling edge Reset

TMRx_ers ↕

TMRx_ers ↑

TMRx_ers ↓

100

ON = 0

Period

Pulse

101

with

Hardware

Reset

ON = 1

ON = 0or

TMRx_ers = 0

110

Low level Reset

TMRx_ers = 0

High level Reset (Figure 27-7)

ON = 0or

TMRx_ers = 1

111

000

001

TMRx_ers = 1

One-shot

Software start (Figure 27-8)

ON = 1

—

ON = 1and

TMRx_ers ↑

Rising edge start (Figure 27-9)

Edge

triggered

start

ON = 1and

TMRx_ers ↓

010

011

Falling edge start

Any edge start

—

ON = 0

or

Next clock

after

TMRx = PRx

(Note 2)

(Note 1)

ON = 1and

TMRx_ers ↕

—

One-shot

01

Rising edge start and

Rising edge Reset (Figure 27-10)

ON = 1and

TMRx_ers ↑

100

TMRx_ers ↑

TMRx_ers ↓

TMRx_ers = 0

TMRx_ers = 1

Edge

triggered

start

and

hardware

Reset

Falling edge start and

Falling edge Reset

ON = 1and

TMRx_ers ↓

101

110

Rising edge start and

Low level Reset (Figure 27-11)

ON = 1and

TMRx_ers ↑

Falling edge start and

High level Reset

ON = 1and

TMRx_ers ↓

(Note 1)

111

000

001

Reserved

Rising edge start

(Figure 27-12)

ON = 1and

TMRx_ers ↑

ON = 0

or

Next clock

after

TMRx = PRx

(Note 3)

—

Edge

triggered

start

Mono-stable

ON = 1and

TMRx_ers ↓

010

011

Falling edge start

Any edge start

(Note 1)

ON = 1and

TMRx_ers ↕

10

Reserved

100

Reserved

101

Level

triggered

start

and

hardware

Reset

High level start and

Low level Reset (Figure 27-13)

ON = 1and

TMRx_ers = 1

110

TMRx_ers = 0

TMRx_ers = 1

ON = 0or

Held in Reset

(Note 2)

One-shot

Low level start &

High level Reset

ON = 1and

TMRx_ers = 0

111

Reserved

11

xxx

Reserved

Note 1: If ON = 0then an edge is required to restart the timer after ON = 1.

2: When TMRx = PRx then the next clock clears ON and stops TMRx at 00h.

3: When TMRx = PRx then the next clock stops TMRx at 00h but does not clear ON.

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27.4 Timer2 Interrupt

Timer2 can also generate a device interrupt. The

interrupt is generated when the postscaler counter

matches one of 16 postscale options (from 1:1 through

1:16), which are selected with the postscaler control

bits, OUTPS<3:0> of the T2CON register. The interrupt

is enabled by setting the TMR2IE interrupt enable bit of

the PIE4 register. Interrupt timing is illustrated in

Figure 27-3.

FIGURE 27-3:

TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM

Rev. 10-000205A

4/7/2016

CKPS

PRx

0b010

1

OUTPS

0b0001

TMRx_clk

TMRx

0

1

0

1

0

1

0

TMRx_postscaled

TMRxIF

(1)

(2)

(1)

Note 1: Setting the interrupt flag is synchronized with the instruction clock.

Synchronization may take as many as 2 instruction cycles

2: Cleared by software.

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27.5.1

SOFTWARE GATE MODE

27.5 Operation Examples

This mode corresponds to legacy Timer2 operation.

The timer increments with each clock input when

ON = 1and does not increment when ON = 0. When

the TMR2 count equals the PR2 period count the timer

resets on the next clock and continues counting from 0.

Operation with the ON bit software controlled is illus-

trated in Figure 27-4. With PR2 = 5, the counter

advances until TMR2 = 5, and goes to zero with the

next clock.

Unless otherwise specified, the following notes apply to

the following timing diagrams:

- Both the prescaler and postscaler are set to

1:1 (both the CKPS and OUTPS bits in the

T2CON register are cleared).

- The diagrams illustrate any clock except

Fosc/4 and show clock-sync delays of at

least two full cycles for both ON and

Timer2_ers. When using Fosc/4, the clock-

sync delay is at least one instruction period

for Timer2_ers; ON applies in the next

instruction period.

- The PWM Duty Cycle and PWM output are

illustrated assuming that the timer is used for

the PWM function of the CCP module as

described in Section 28.0 “Capture/Com-

pare/PWM Modules”. The signals are not a

part of the Timer2 module.

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FIGURE 27-4:

SOFTWARE GATE MODE TIMING DIAGRAM (MODE = 00000)

Rev. 10-000195B

5/30/2014

MODE

0b00000

TMRx_clk

Instruction⁽¹⁾

ON

BSF

BCF

BSF

PRx

5

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to

set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

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When MODE<4:0> = 00001then the timer is stopped

when the external signal is high. When

MODE<4:0> = 00010 then the timer is stopped when

the external signal is low.

27.5.2

HARDWARE GATE MODE

The Hardware Gate modes operate the same as the

Software Gate mode except the TMR2_ers external

signal gates the timer. When used with the CCP the

gating extends the PWM period. If the timer is stopped

when the PWM output is high then the duty cycle is also

extended.

Figure 27-5 illustrates the Hardware Gating mode for

MODE<4:0> = 00001in which a high input level starts

the counter.

FIGURE 27-5:

HARDWARE GATE MODE TIMING DIAGRAM (MODE = 00001)

Rev. 10-000 196B

5/30/201 4

MODE

TMRx_clk

TMRx_ers

PRx

0b00001

5

3

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

PWM Output

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When the timer is used in conjunction with the CCP in

PWM mode then an early Reset shortens the period

and restarts the PWM pulse after a two clock delay.

Refer to Figure 27-6.

27.5.3

EDGE-TRIGGERED HARDWARE

LIMIT MODE

In Hardware Limit mode the timer can be reset by the

TMR2_ers external signal before the timer reaches the

period count. Three types of Resets are possible:

• Reset on rising or falling edge

(MODE<4:0>= 00011)

• Reset on rising edge (MODE<4:0> = 00100)

• Reset on falling edge (MODE<4:0> = 00101)

FIGURE 27-6:

EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00100)

Rev. 10-000 197B

5/30/201 4

MODE

0b00100

5

TMRx_clk

PRx

Instruction⁽¹⁾

ON

BSF

BCF BSF

TMRx_ers

TMRx

0

1

2

0

1

2

3

4

3

5

0

1

2

3

4

5

0

1

TMRx_postscaled

PWM Duty

Cycle

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to

set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

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When the CCP uses the timer as the PWM time base

then the PWM output will be set high when the timer

starts counting and then set low only when the timer

count matches the CCPRx value. The timer is reset

when either the timer count matches the PR2 value or

two clock periods after the external Reset signal goes

true and stays true.

27.5.4

LEVEL-TRIGGERED HARDWARE

LIMIT MODE

In the Level-Triggered Hardware Limit Timer modes the

counter is reset by high or low levels of the external

signal TMR2_ers, as shown in Figure 27-7. Selecting

MODE<4:0> = 00110will cause the timer to reset on a

low

level

external

signal.

Selecting

The timer starts counting, and the PWM output is set

high, on either the clock following the PR2 match or two

clocks after the external Reset signal relinquishes the

Reset. The PWM output will remain high until the timer

counts up to match the CCPRx pulse width value. If the

external Reset signal goes true while the PWM output

is high then the PWM output will remain high until the

Reset signal is released allowing the timer to count up

to match the CCPRx value.

MODE<4:0> = 00111will cause the timer to reset on a

high level external signal. In the example, the counter

is reset while TMR2_ers = 1. ON is controlled by BSF

and BCF instructions. When ON = 0the external signal

is ignored.

FIGURE 27-7:

LEVEL-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM

(MODE = 00111)

Rev. 10-000198B

5/30/2014

MODE

0b00111

5

TMRx_clk

PRx

Instruction⁽¹⁾

ON

BSF

BCF

BSF

TMRx_ers

TMRx

0

1

2

0

1

2

3

4

5

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to

set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

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When One-Shot mode is used in conjunction with the

CCP PWM operation the PWM pulse drive starts

concurrent with setting the ON bit. Clearing the ON bit

while the PWM drive is active will extend the PWM

drive. The PWM drive will terminate when the timer

value matches the CCPRx pulse width value. The

PWM drive will remain off until software sets the ON bit

to start another cycle. If software clears the ON bit after

the CCPRx match but before the PR2 match then the

PWM drive will be extended by the length of time the

ON bit remains cleared. Another timing cycle can only

be initiated by setting the ON bit after it has been

cleared by a PR2 period count match.

27.5.5

SOFTWARE START ONE-SHOT

MODE

In One-Shot mode the timer resets and the ON bit is

cleared when the timer value matches the PR2 period

value. The ON bit must be set by software to start

another timer cycle. Setting MODE<4:0> = 01000

selects One-Shot mode which is illustrated in

Figure 27-8. In the example, ON is controlled by BSF

and BCF instructions. In the first case, a BSF instruc-

tion sets ON and the counter runs to completion and

clears ON. In the second case, a BSF instruction starts

the cycle, BCF/BSF instructions turn the counter off

and on during the cycle, and then it runs to completion.

FIGURE 27-8:

SOFTWARE START ONE-SHOT MODE TIMING DIAGRAM (MODE = 01000)

Rev. 10-000199B

4/7/2016

MODE

0b01000

TMRx_clk

PRx

5

Instruction⁽¹⁾

ON

BSF

BCF

BSF

TMRx

0

1

2

3

4

5

0

1

2

3

4

5

0

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions

executed by the CPU to set or clear the ON bit of TxCON. CPU

execution is asynchronous to the timer clock input.

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If the timer is halted by clearing the ON bit then another

TMR2_ers edge is required after the ON bit is set to

resume counting. Figure 27-9 illustrates operation in

the rising edge One-Shot mode.

27.5.6

EDGE-TRIGGERED ONE-SHOT

MODE

The Edge-Triggered One-Shot modes start the timer

on an edge from the external signal input, after the ON

bit is set, and clear the ON bit when the timer matches

the PR2 period value. The following edges will start

the timer:

When Edge-Triggered One-Shot mode is used in con-

junction with the CCP then the edge-trigger will activate

the PWM drive and the PWM drive will deactivate when

the timer matches the CCPRx pulse width value and

stay deactivated when the timer halts at the PR2 period

count match.

• Rising edge (MODE<4:0> = 01001)

• Falling edge (MODE<4:0> = 01010)

• Rising or Falling edge (MODE<4:0> = 01011)

FIGURE 27-9:

EDGE-TRIGGERED ONE-SHOT MODE TIMING DIAGRAM (MODE = 01001)

Rev. 10-000200B

5/19/2016

MODE

0b01001

5

TMRx_clk

PRx

Instruction⁽¹⁾

ON

BSF

BCF

TMRx_ers

TMRx

0

1

2

3

4

5

0

1

2

CCP_pset

TMRx_postscaled

PWM Duty

Cycle

3

PWM Output

Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to

set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.

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27.6 Timer2 Operation During Sleep

When PSYNC = 1, Timer2 cannot be operated while

the processor is in Sleep mode. The contents of the

TMR2 and PR2 registers will remain unchanged while

processor is in Sleep mode.

When PSYNC = 0, Timer2 will operate in Sleep as long

as the clock source selected is also still running.

Selecting the LFINTOSC, MFINTOSC, or HFINTOSC

oscillator as the timer clock source will keep the

selected oscillator running during Sleep.

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27.7 Register Definitions: Timer2 Control

REGISTER 27-1: T2CLKCON: TIMER2 CLOCK SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CS<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

CS<3:0>: Timer2 Clock Select bits

1111= Reserved

1110= LC4_out

1101= LC3_out

1100= LC2_out

1011= LC1_out

1010= ZCD1_output

1001= NCO1_out

1000= CLKR

0111= SOSC

0110= MFINTOSC (31.25 kHz)

0101= MFINTOSC (500 kHz)

0100= LFINTOSC

0011= HFINTOSC (32 MHz)

0010= FOSC

0001= FOSC/4

0000= T2CKIPPS

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REGISTER 27-2: T2CON: TIMER2 CONTROL REGISTER

R/W/HC-0/0

ON⁽¹⁾

R/W-0/0

bit 0

CKPS<2:0>

OUTPS<3:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

bit 7

ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off: all counters and state machines are reset

bit 6-4

CKPS<2:0>: Timer2-type Clock Prescale Select bits

111=1:128 Prescaler

110=1:64 Prescaler

101=1:32 Prescaler

100=1:16 Prescaler

011=1:8 Prescaler

010=1:4 Prescaler

001=1:2 Prescaler

000=1:1 Prescaler

bit 3-0

OUTPS<3:0>: Timer2 Output Postscaler Select bits

1111=1:16 Postscaler

1110=1:15 Postscaler

1101=1:14 Postscaler

1100=1:13 Postscaler

1011=1:12 Postscaler

1010=1:11 Postscaler

1001=1:10 Postscaler

1000=1:9 Postscaler

0111=1:8 Postscaler

0110=1:7 Postscaler

0101=1:6 Postscaler

0100=1:5 Postscaler

0011=1:4 Postscaler

0010=1:3 Postscaler

0001=1:2 Postscaler

0000=1:1 Postscaler

Note 1: In certain modes, the ON bit will be auto-cleared by hardware. See Section 27.5 “Operation Examples”.

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REGISTER 27-3: T2HLT: TIMER2 HARDWARE LIMIT CONTROL REGISTER

R/W-0/0

(1, 2)

(3)

(4, 5)

(6, 7)

PSYNC

bit 7

CKPOL

CKSYNC

MODE<4:0>

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

-n/n = Value at POR and BOR/Value at all other Resets

(1, 2)

bit 7

PSYNC: Timer2 Prescaler Synchronization Enable bit

1= TMR2 Prescaler Output is synchronized to Fosc/4

0= TMR2 Prescaler Output is not synchronized to Fosc/4

(3)

bit 6

CKPOL: Timer2 Clock Polarity Selection bit

1= Falling edge of input clock clocks timer/prescaler

0= Rising edge of input clock clocks timer/prescaler

(4, 5)

bit 5

CKSYNC: Timer2 Clock Synchronization Enable bit

1= ON register bit is synchronized to TMR2_clk input

0= ON register bit is not synchronized to TMR2_clk input

(6, 7)

bit 4-0

MODE<4:0>: Timer2 Control Mode Selection bits

See Table 27-1.

Note 1: Setting this bit ensures that reading TM2x will return a valid value.

2: When this bit is ‘1’, Timer2 cannot operate in Sleep mode.

3: CKPOL should not be changed while ON = 1.

4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.

5: When this bit is set then the timer operation will be delayed by two TMR2 input clocks after the ON bit is set.

6: Unless otherwise indicated, all modes start upon ON = 1and stop upon ON = 0(stops occur without affecting the value

of TMR2).

7: When TMR2 = PR2, the next clock clears TMR2, regardless of the operating mode.

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REGISTER 27-4: T2RST: TIMER2 EXTERNAL RESET SIGNAL SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

RSEL<3:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

RSEL<3:0>: Timer2 External Reset Signal Source Selection bits

1111= Reserved

1101= LC4_out

1100= LC3_out

1011= LC2_out

1010= LC1_out

1001= ZCD1_output

1000= C2OUT_sync

0111= C1OUT_sync

0110= PWM6_out

0101= PWM5_out

0100= PWM4_out

0011= PWM3_out

0010= CCP2_out

0001= CCP1_out

0000= T2INPPS

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TABLE 27-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CCP1CON

CCP2CON

INTCON

PIE4

EN

GIE

—

OUT

—

FMT

—

MODE<3:0>

319

121

134

PEIE

—

INTEDG

TMR1IE

TMR1IF

—

TMR2IE

TMR2IF

PIR4

—

PR2

Timer2 Module Period Register

Holding Register for the 8-bit TMR2 Register

291*

292*

308

307

310

309

TMR2

T2CON

T2CLKCON

T2RST

T2HLT

ON

—

CKPS<2:0>

OUTPS<3:0>

—

CS<3:0>

—

RSEL<3:0>

PSYNC

CKPOL

CKSYNC

MODE<4:0>

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module.

*

Page provides register information.

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28.0 CAPTURE/COMPARE/PWM

MODULES

The Capture/Compare/PWM module is a peripheral

that allows the user to time and control different events,

and to generate Pulse-Width Modulation (PWM)

signals. In Capture mode, the peripheral allows the

timing of the duration of an event. The Compare mode

allows the user to trigger an external event when a

predetermined amount of time has expired. The PWM

mode can generate Pulse-Width Modulated signals of

varying frequency and duty cycle.

The Capture/Compare/PWM modules available are

shown in Table 28-1.

TABLE 28-1: AVAILABLE CCP MODULES

Device

CCP1

CCP2

PIC16(L)F15354/55

●

The Capture and Compare functions are identical for all

CCP modules.

Note 1: In devices with more than one CCP

module, it is very important to pay close

attention to the register names used. A

number placed after the module acronym

is used to distinguish between separate

modules. For example, the CCP1CON

and CCP2CON control the same

operational aspects of two completely

different CCP modules.

2: Throughout

this

section,

generic

references to a CCP module in any of its

operating modes may be interpreted as

being equally applicable to CCPx module.

Register names, module signals, I/O pins,

and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular module,

when required.

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Figure 28-1 shows a simplified diagram of the capture

operation.

28.1 Capture Mode

Capture mode makes use of the 16-bit Timer1

resource. When an event occurs on the capture

source, the 16-bit CCPRxH:CCPRxL register pair

captures and stores the 16-bit value of the

TMR1H:TMR1L register pair, respectively. An event is

defined as one of the following and is configured by the

CCPxMODE<3:0> bits of the CCPxCON register:

28.1.1

CAPTURE SOURCES

In Capture mode, the CCPx pin should be configured

as an input by setting the associated TRIS control bit.

Note:

If the CCPx pin is configured as an output,

a write to the port can cause a capture

condition.

• Every falling edge

• Every rising edge

The capture source is selected by configuring the

CCPxCTS<2:0> bits of the CCPxCAP register. The

following sources can be selected:

• Every 4th rising edge

• Every 16th rising edge

• CCPxPPS input

• C1OUT_sync

• C2OUT_sync

• IOC_interrupt

• LC1_out

When a capture is made, the Interrupt Request Flag bit

CCPxIF of the PIR6 register is set. The interrupt flag

must be cleared in software. If another capture occurs

before the value in the CCPRxH, CCPRxL register pair

is read, the old captured value is overwritten by the new

captured value.

• LC2_out

• LC3_out

• LC4_out

FIGURE 28-1:

CAPTURE MODE OPERATION BLOCK DIAGRAM

Rev. 10-000158F

9/1/2015

RxyPPS

CCPx

CTS<2:0>

TRIS Control

LC4_out

111

110

101

100

011

010

001

000

LC3_out

LC2_out

CCPRxH CCPRxL

16

set CCPxIF

LC1_out

Prescaler

1,4,16

and

Edge Detect

IOC_interrupt

C2OUT_sync

C1OUT_sync

PPS

16

MODE <3:0>

TMR1H

TMR1L

CCPx

CCPxPPS

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28.1.2

TIMER1 MODE RESOURCE

28.1.5

CAPTURE DURING SLEEP

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

Capture mode depends upon the Timer1 module for

proper operation. There are two options for driving the

Timer1 module in Capture mode. It can be driven by the

instruction clock (FOSC/4), or by an external clock source.

See Section 26.0 “Timer1 Module with Gate

Control” for more information on configuring Timer1.

When Timer1 is clocked by FOSC/4, Timer1 will not

increment during Sleep. When the device wakes from

Sleep, Timer1 will continue from its previous state.

28.1.3

SOFTWARE INTERRUPT MODE

Capture mode will operate during Sleep when Timer1

is clocked by an external clock source.

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep the

CCPxIE interrupt enable bit of the PIE6 register clear to

avoid false interrupts. Additionally, the user should

clear the CCPxIF interrupt flag bit of the PIR6 register

following any change in Operating mode.

28.2 Compare Mode

Compare mode makes use of the 16-bit Timer1

resource. The 16-bit value of the CCPRxH:CCPRxL

register pair is constantly compared against the 16-bit

value of the TMR1H:TMR1L register pair. When a

match occurs, one of the following events can occur:

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, Timer1 must be clocked from the

instruction clock (FOSC/4).

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate an Auto-conversion Trigger

• Generate a Software Interrupt

28.1.4

CCP PRESCALER

There are four prescaler settings specified by the

CCPxMODE<3:0> bits of the CCPxCON register.

Whenever the CCP module is turned off, or the CCP

module is not in Capture mode, the prescaler counter

is cleared. Any Reset will clear the prescaler counter.

The action on the pin is based on the value of the

CCPxMODE<3:0> control bits of the CCPxCON

register. At the same time, the interrupt flag CCPxIF bit

is set, and an ADC conversion can be triggered, if

selected.

Switching from one capture prescaler to another does not

clear the prescaler and may generate a false interrupt. To

avoid this unexpected operation, turn the module off by

clearing the CCPxCON register before changing the

prescaler. Example 28-1 demonstrates the code to

perform this function.

All Compare modes can generate an interrupt and

trigger and ADC conversion.

Figure 28-2 shows a simplified diagram of the compare

operation.

FIGURE 28-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

EXAMPLE 28-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

BANKSELCCPxCON

;Set Bank bits to point

;to CCPxCON

CCPxMODE<3:0>

Mode Select

CLRF

CCPxCON

;Turn CCP module off

Set CCPxIF Interrupt Flag

MOVLW

NEW_CAPT_PS;Load the W reg with

;the new prescaler

(PIR6)

4

CCPx

CCPRxH CCPRxL

Comparator

;move value and CCP ON

MOVWF

CCPxCON

;Load CCPxCON with this

;value

Q

S

R

Output

Logic

Match

TMR1H TMR1L

TRIS

Output Enable

Auto-conversion Trigger

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28.2.1

CCPX PIN CONFIGURATION

28.3 PWM Overview

The software must configure the CCPx pin as an output

by clearing the associated TRIS bit and defining the

appropriate output pin through the RxyPPS registers.

See Section 15.0 “Peripheral Pin Select (PPS)

Module” for more details.

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the on state and the low portion of the signal

is considered the off state. The high portion, also known

as the pulse width, can vary in time and is defined in

steps. A larger number of steps applied, which

lengthens the pulse width, also supplies more power to

the load. Lowering the number of steps applied, which

shortens the pulse width, supplies less power. The

PWM period is defined as the duration of one complete

cycle or the total amount of on and off time combined.

The CCP output can also be used as an input for other

peripherals.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and in turn the power that is applied to the

load.

28.2.2

TIMER1 MODE RESOURCE

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

The term duty cycle describes the proportion of the on

time to the off time and is expressed in percentages,

where 0% is fully off and 100% is fully on. A lower duty

cycle corresponds to less power applied and a higher

duty cycle corresponds to more power applied.

See Section 26.0 “Timer1 Module with Gate Control”

for more information on configuring Timer1.

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Compare

mode. In order for Compare mode to

recognize the trigger event on the CCPx

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

Figure 28-3 shows a typical waveform of the PWM

signal.

28.3.1

STANDARD PWM OPERATION

The standard PWM mode generates a Pulse-Width

Modulation (PWM) signal on the CCPx pin with up to

ten bits of resolution. The period, duty cycle, and

resolution are controlled by the following registers:

28.2.3

AUTO-CONVERSION TRIGGER

All CCPx modes set the CCP interrupt flag (CCPxIF).

When this flag is set and a match occurs, an Auto-

conversion Trigger can take place if the CCP module is

selected as the conversion trigger source.

• PR2 registers

• T2CON registers

• CCPRxL registers

• CCPxCON registers

Refer to Section 20.2.4 “Auto-Conversion Trigger”

for more information.

Figure 28-4 shows a simplified block diagram of PWM

operation.

Note:

Removing the match condition by

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Auto-

conversion Trigger and the clock edge

that generates the Timer1 Reset, will

preclude the Reset from occurring

Note:

The corresponding TRIS bit must be

cleared to enable the PWM output on the

CCPx pin.

FIGURE 28-3:

CCP PWM OUTPUT SIGNAL

28.2.4

COMPARE DURING SLEEP

Period

Since FOSC is shut down during Sleep mode, the

Compare mode will not function properly during Sleep,

unless the timer is running. The device will wake on

interrupt (if enabled).

Pulse Width

TMR2 = PR2

TMR2 = CCPRxH:CCPRxL

TMR2 = 0

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FIGURE 28-4:

SIMPLIFIED PWM BLOCK DIAGRAM

Rev. 10-000 157C

9/5/201 4

Duty cycle registers

CCPRxH

CCPRxL

CCPx_out

To Peripherals

set CCPIF

10-bit Latch⁽²⁾

(Not accessible by user)

R

S

Q

Comparator

PPS

CCPx

RxyPPS

TRIS Control

TMR2 Module

TMR2

R

(1)

ERS logic

CCPx_pset

Comparator

PR2

6. Enable PWM output pin:

28.3.2

SETUP FOR PWM OPERATION

•Wait until the Timer overflows and the TMR2IF

bit of the PIR4 register is set. See Note

below.

The following steps should be taken when configuring

the CCP module for standard PWM operation:

1. Use the desired output pin RxyPPS control to

select CCPx as the source and disable the

CCPx pin output driver by setting the associated

TRIS bit.

•Enable the CCPx pin output driver by clearing

the associated TRIS bit.

Note:

In order to send a complete duty cycle and

period on the first PWM output, the above

steps must be included in the setup

sequence. If it is not critical to start with a

complete PWM signal on the first output,

then step 6 may be ignored.

2. Load the PR2 register with the PWM period

value.

3. Configure the CCP module for the PWM mode

by loading the CCPxCON register with the

appropriate values.

4. Load the CCPRxL register, and the CCPRxH

register with the PWM duty cycle value and

configure the CCPxFMT bit of the CCPxCON

register to set the proper register alignment.

28.3.3

CCP/PWM CLOCK SELECTION

The PIC16(L)F15354/55 allows each individual CCP

and PWM module to select the timer source that

controls the module. Each module has an independent

selection.

5. Configure and start Timer2:

•Clear the TMR2IF interrupt flag bit of the

PIR4 register. See Note below.

•Configure the CKPS bits of the T2CON reg-

ister with the Timer prescale value.

•Enable the Timer by setting the Timer2 ON

bit of the T2CON register.

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PIC16(L)F15354/55

28.3.4

TIMER2 TIMER RESOURCE

FIGURE 28-5:

PWM 10-BIT ALIGNMENT

This device has a newer version of the Timer2 module

that has many new modes, which allow for greater

customization and control of the PWM signals than on

older parts. Refer to Section 27.5 “Operation

Examples” for examples of PWM signal generation

using the different modes of Timer2. The CCP

operation requires that the timer used as the PWM time

base has the FOSC/4 clock source selected

Rev. 10-000 160A

12/9/201 3

CCPRxH

CCPRxL

FMT = 0

7 6 5 4 3 2 1 0

CCPRxH

CCPRxL

7 6 5 4 3 2 1 0

FMT = 1

7 6 5 4 3 2 1 0

28.3.5

PWM PERIOD

10-bit Duty Cycle

9 8 7 6 5 4 3 2 1 0

The PWM period is specified by the PR2 register of

Timer2. The PWM period can be calculated using the

formula of Equation 28-1.

EQUATION 28-2: PULSE WIDTH

EQUATION 28-1: PWM PERIOD

PWM Period = PR2 + 1  4  TOSC 

Pulse Width = CCPRxH:CCPRxL register pair 

TOSC  (TMR2 Prescale Value)

(TMR2 Prescale Value)

Note 1: TOSC = 1/FOSC

EQUATION 28-3: DUTY CYCLE RATIO

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

CCPRxH:CCPRxL register pair

Duty Cycle Ratio = ---------------------------------------------------------------------------------

4PR2 + 1

• TMR2 is cleared

• The CCPx pin is set. (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

CCPRxH:CCPRxL register pair are used to double

buffer the PWM duty cycle. This double buffering

provides for glitchless PWM operation.

• The PWM duty cycle is transferred from the

CCPRxL/H register pair into a 10-bit buffer.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two bits

of the prescaler, to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to 1:1.

Note:

The Timer postscaler (see Section 27.4

“Timer2 Interrupt”) is not used in the

determination of the PWM frequency.

28.3.6

PWM DUTY CYCLE

When the 10-bit time base matches the

CCPRxH:CCPRxL register pair, then the CCPx pin is

cleared (see Figure 28-4).

The PWM duty cycle is specified by writing a 10-bit

value to the CCPRxH:CCPRxL register pair. The

alignment of the 10-bit value is determined by the

CCPRxFMT bit of the CCPxCON register (see

Figure 28-5). The CCPRxH:CCPRxL register pair can

be written to at any time; however the duty cycle value

is not latched into the 10-bit buffer until after a match

between PR2 and TMR2.

28.3.7

PWM RESOLUTION

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit resolution

will result in 1024 discrete duty cycles, whereas an 8-bit

resolution will result in 256 discrete duty cycles.

Equation 28-2 is used to calculate the PWM pulse

width.

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 28-4.

Equation 28-3 is used to calculate the PWM duty cycle

ratio.

EQUATION 28-4: PWM RESOLUTION

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

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TABLE 28-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

PR2 Value

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 28-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz

153.85 kHz 200.0 kHz

16

0x65

8

4

0x65

8

1

0x65

8

1

0x19

6

1

0x0C

5

1

0x09

5

PR2 Value

Maximum Resolution (bits)

28.3.8

OPERATION IN SLEEP MODE

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the CCPx

pin is driving a value, it will continue to drive that value.

When the device wakes up, TMR2 will continue from its

previous state.

28.3.9

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 9.0 “Oscillator Module (with Fail-Safe

Clock Monitor)” for additional details.

28.3.10 EFFECTS OF RESET

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

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28.4 Register Definitions: CCP Control

Long bit name prefixes for the CCP peripherals are

shown in Section 1.1 “Register and Bit Naming

Conventions”.

TABLE 28-4: LONG BIT NAMES PREFIXES

FOR CCP PERIPHERALS

Peripheral

Bit Name Prefix

CCP1

CCP2

CCP1

CCP2

REGISTER 28-1: CCPxCON: CCPx CONTROL REGISTER

R/W-0/0

EN

U-0

—

R-x

R/W-0/0

FMT

R/W-0/0

OUT

MODE<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Reset

bit 7

EN: CCPx Module Enable bit

1= CCPx is enabled

0= CCPx is disabled

bit 6

bit 5

bit 4

Unimplemented: Read as ‘0’

OUT: CCPx Output Data bit (read-only)

FMT: CCPW (Pulse Width) Alignment bit

MODE = Capture mode

Unused

MODE = Compare mode

Unused

MODE = PWM mode

1= Left-aligned format

0= Right-aligned format

(1)

bit 3-0

MODE<3:0>: CCPx Mode Select bits

1111- 1100= PWM mode (Timer2 as the timer source)

1110= Reserved

1101=Reserved

1100= Reserved

1011=Compare mode: output will pulse 0-1-0; Clears TMR1

1010=Compare mode: output will pulse 0-1-0

1001=Compare mode: clear output on compare match

1000=Compare mode: set output on compare match

0111=Capture mode: every 16th rising edge of CCPx input

0110=Capture mode: every 4th rising edge of CCPx input

0101=Capture mode: every rising edge of CCPx input

0100=Capture mode: every falling edge of CCPx input

0011=Capture mode: every edge of CCPx input

0010=Compare mode: toggle output on match

0001=Compare mode: toggle output on match; clear TMR1

0000=Capture/Compare/PWM off (resets CCPx module)

Note 1: All modes will set the CCPxIF bit, and will trigger an ADC conversion if CCPx is selected as the ADC trigger source.

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REGISTER 28-2: CCPxCAP: CAPTURE INPUT SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/x

bit 0

CTS<2:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Reset

u = Bit is unchanged

‘1’ = Bit is set

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

CTS<2:0>: Capture Trigger Input Selection bits

CTS

111

110

101

100

011

010

001

000

CCP1.capture

CCP2.capture

LC4_out

LC3_out

LC2_out

LC1_out

IOC_interrupt

C2OUT

C1OUT

CCP1PPS

CCP2PPS

R/W-x/x

REGISTER 28-3: CCPRxL REGISTER: CCPx REGISTER LOW BYTE

R/W-x/x

CCPRx<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Reset

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

CCPxMODE = Capture mode

CCPRxL<7:0>: Capture value of TMR1L

CCPxMODE = Compare mode

CCPRxL<7:0>: LS Byte compared to TMR1L

CCPxMODE = PWM modes when CCPxFMT = 0:

CCPRxL<7:0>: Pulse-width Least Significant eight bits

CCPxMODE = PWM modes when CCPxFMT = 1:

CCPRxL<7:6>: Pulse-width Least Significant two bits

CCPRxL<5:0>: Not used.

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REGISTER 28-4: CCPRxH REGISTER: CCPx REGISTER HIGH BYTE

R/W-x/x

bit 0

CCPRx<15:8>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Reset

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

CCPxMODE = Capture mode

CCPRxH<7:0>: Captured value of TMR1H

CCPxMODE = Compare mode

CCPRxH<7:0>: MS Byte compared to TMR1H

CCPxMODE = PWM modes when CCPxFMT = 0:

CCPRxH<7:2>: Not used

CCPRxH<1:0>: Pulse-width Most Significant two bits

CCPxMODE = PWM modes when CCPxFMT = 1:

CCPRxH<7:0>: Pulse-width Most Significant eight bits

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TABLE 28-5: SUMMARY OF REGISTERS ASSOCIATED WITH CCPx

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

—

INTEDG

121

144

PIR6

—

CCP2IF

CCP2IE

CCP1IF

CCP1IE

PIE6

136

319

320

321

319

320

199

200

236

364

353

CCP1CON

CCP1CAP

CCPR1L

CCPR1H

CCP2CON

CCP2CAP

CCPR2L

CCPR2H

CCP1PPS

CCP2PPS

RxyPPS

EN

—

OUT

—

FMT

—

MODE<3:0>

CTS<2:0>

—

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

EN

—

OUT

—

FMT

—

MODE<3:0>

CTS<2:0>

—

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

—

CCP1PPS<5:0>

CCP2PPS<5:0>

—

RxyPPS<4:0>

ADACT

ADACT<4:0>

LCxDyS<4:0>

CLCxSELy

CWG1DAT

Legend:

—

DAT<3:0>

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the CCP module.

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FIGURE 29-1:

PWM OUTPUT

29.0 PULSE-WIDTH MODULATION

(PWM)

Rev. 10-000023C

8/26/2015

Q1

Q2

Q3

Q4

The PWMx modules generate Pulse-Width Modulated

(PWM) signals of varying frequency and duty cycle.

FOSC

PWM

In addition to the CCP modules, the PIC16(L)F15354/

55 devices contain four 10-bit PWM modules (PWM3,

PWM4, PWM5 and PWM6). The PWM modules

reproduce the PWM capability of the CCP modules.

Pulse Width

(1)

TMRx = 0

(1)

TMRx = PWMxDC

Note:

The PWM3/4/5/6 modules are four

instances of the same PWM module

design. Throughout this section, the lower

case ‘x’ in register and bit names is a

generic reference to the PWM module

number (which should be substituted with

(1)

TMRx = PRx

Note 1: Timer dependent on PWMTMRS register settings.

3, or 4, or,

5 or 6 during code

development). For example, the control

register is generically described in this

chapter as PWMxCON, but the actual

device

PWM4CON,

registers

are

PWM5CON

PWM3CON,

and

PWM6CON. Similarly, the PWMxEN bit

represents the PWM3EN, PWM4EN,

PWM5EN and PWM6EN bits.

Pulse-Width Modulation (PWM) is a scheme that

provides power to a load by switching quickly between

fully on and fully off states. The PWM signal resembles

a square wave where the high portion of the signal is

considered the ‘on’ state (pulse width), and the low

portion of the signal is considered the ‘off’ state. The

term duty cycle describes the proportion of the ‘on’ time

to the ‘off’ time and is expressed in percentages, where

0% is fully off and 100% is fully on. A lower duty cycle

corresponds to less power applied and a higher duty

cycle corresponds to more power applied. The PWM

period is defined as the duration of one complete cycle

or the total amount of on and off time combined.

PWM resolution defines the maximum number of steps

that can be present in a single PWM period. A higher

resolution allows for more precise control of the pulse

width time and, in turn, the power that is applied to the

load.

Figure 29-1 shows a typical waveform of the PWM

signal.

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PIC16(L)F15354/55

29.1 Standard PWM Mode

The standard PWM mode generates a Pulse-Width

Modulation (PWM) signal on the PWMx pin with up to

ten bits of resolution. The period, duty cycle, and

resolution are controlled by the following registers:

• TMR2 register

• PR2 register

• PWMxCON registers

• PWMxDCH registers

• PWMxDCL registers

Figure 29-2 shows a simplified block diagram of PWM

operation.

If PWMPOL = 0, the default state of the output is ‘0‘. If

PWMPOL = 1, the default state is ‘1’. If PWMEN = 0,

the output will be the default state.

Note:

The corresponding TRIS bit must be

cleared to enable the PWM output on the

PWMx pin

FIGURE 29-2:

SIMPLIFIED PWM BLOCK DIAGRAM

Rev. 10-000022B

9/24/2014

PWMxDCL<7:6>

Duty cycle registers

PWMxDCH

PWMx_out

To Peripherals

10-bit Latch

(Not visible to user)

R

S

Q

Comparator

0

1

PPS

PWMx

TMR2 Module

RxyPPS

TRIS Control

R

PWMxPOL

(1)

TMR2

Comparator

PR2

T2_match

Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to

create 10-bit time-base.

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PIC16(L)F15354/55

29.1.1

PWM CLOCK SELECTION

29.1.4

PWM DUTY CYCLE

The PIC16(L)F15354/55 allows each individual CCP

and PWM module to select the timer source that con-

trols the module. Each module has an independent

selection.

The PWM duty cycle is specified by writing a 10-bit

value to the PWMxDC register. The PWMxDCH

contains the eight MSbs and the PWMxDCL<7:6> bits

contain the two LSbs.

The PWMDC register is double-buffered and can be

updated at any time. This double buffering is essential

for glitch-free PWM operation. New values take effect

when TMR2 = PR2. Note that PWMDC is left-justified.

29.1.2

USING THE TMR2 WITH THE PWM

MODULE

This device has a newer version of the TMR2 module

that has many new modes, which allow for greater

customization and control of the PWM signals than on

older parts. Refer to Section 27.5 “Operation

Examples” for examples of PWM signal generation

using the different modes of Timer2.

The 8-bit timer TMR2 register is concatenated with

either the 2-bit internal system clock (FOSC), or two

bits of the prescaler, to create the 10-bit time base. The

system clock is used if the Timer2 prescaler is set to

1:1.

Equation 29-2 is used to calculate the PWM pulse

width.

Note:

PWM operation requires that the timer

used as the PWM time base has the

FOSC/4 clock source selected.

Equation 29-3 is used to calculate the PWM duty cycle

ratio.

29.1.3

PWM PERIOD

EQUATION 29-2: PULSE WIDTH

Referring to Figure 29-1, the PWM output has a period

and a pulse width. The frequency of the PWM is the

inverse of the period (1/period).

Pulse Width

ꢀꢀൌꢀꢀ

ሺܹܲ

ܥܦݔܯ

ሻ

ꢀή

ꢀ

ܱܶܵ

ܥ

ꢀꢀ ήꢀ

ꢀሺܶ

ܯ

ܴʹꢀܲ

ݎ

݁

ݏ

݈ܿܽ݁ꢀܸ݈ܽ

ݑ

݁ሻꢀ

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following formula:

EQUATION 29-3: DUTY CYCLE RATIO

ሺ

ሻ

ܹܲ

ܥܦݔܯ

ܦ

ݕݐݑ

ꢀ

ݕܥ

݈ܿ݁ꢀܴܽ

ݐ

݅

݋

ꢀꢀ

ൌ

ꢀ

EQUATION 29-1: PWM PERIOD

ሺ

ሻ

Ͷ ܴܲʹ

൅ ͳ

ܹܲ

ܯ

ꢀܲ݁

ݎ

݅

݋

݀ ൌꢀꢀሾሺܴܲʹሻꢀ൅ ꢀͳሿꢀή ꢀͶꢀ ή ꢀܱܶܵ

ܥ

ꢀꢀ

29.1.5

PWM RESOLUTION

ήꢀሺܶ

ܯ

ܴʹꢀܲ

ݎ

݁

ݏ

݈ܿܽ݁ꢀܸ݈ܽ

ݑ

݁ሻ

The resolution determines the number of available duty

cycles for a given period. For example, a 10-bit

resolution will result in 1024 discrete duty cycles,

whereas an 8-bit resolution will result in 256 discrete

duty cycles.

Note 1: TOSC = 1/FOSC

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

• TMR2 is cleared

• The PWMx pin is set (Exception: If the PWM duty

cycle = 0%, the pin will not be set.)

The maximum PWM resolution is ten bits when PR2 is

255. The resolution is a function of the PR2 register

value as shown by Equation 29-4.

• The PWM pulse width is latched from PWMxDC.

EQUATION 29-4: PWM RESOLUTION

Note:

If the pulse width value is greater than the

period the assigned PWM pin(s) will

remain unchanged.

log4PR2 + 1

Resolution = ----------------------------------------- bits

log2

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29.1.6

OPERATION IN SLEEP MODE

29.1.8

EFFECTS OF RESET

In Sleep mode, the TMR2 register will not increment

and the state of the module will not change. If the

PWMx pin is driving a value, it will continue to drive that

value. When the device wakes up, TMR2 will continue

from its previous state.

Any Reset will force all ports to Input mode and the

PWMx registers to their Reset states.

29.1.7

CHANGES IN SYSTEM CLOCK

FREQUENCY

The PWM frequency is derived from the system clock

frequency. Any changes in the system clock frequency

will result in changes to the PWM frequency. See

Section 9.0 “Oscillator Module (with Fail-Safe

Clock Monitor)” for additional details.

TABLE 29-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

4.88 kHz

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

PR2 Value

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

TABLE 29-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency

Timer Prescale

1.22 kHz

4.90 kHz

19.61 kHz

76.92 kHz 153.85 kHz 200.0 kHz

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

PR2 Value

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

6. Wait until the TMR2IF is set.

29.1.9

SETUP FOR PWM OPERATION

7. When the TMR2IF flag bit is set:

The following steps should be taken when configuring

the module for using the PWMx outputs:

• Clear the associated TRIS bit(s) to enable the out-

put driver.

• Route the signal to the desired pin by configuring

the RxyPPS register.

• Enable the PWMx module by setting the

PWMxEN bit of the PWMxCON register.

1. Disable the PWMx pin output driver(s) by setting

the associated TRIS bit(s).

2. Configure the PWM output polarity by

configuring the PWMxPOL bit of the PWMxCON

register.

In order to send a complete duty cycle and period on

the first PWM output, the above steps must be followed

in the order given. If it is not critical to start with a

complete PWM signal, then the PWM module can be

enabled during Step 2 by setting the PWMxEN bit of

the PWMxCON register.

3. Load the PR2 register with the PWM period value,

as determined by Equation 29-1.

4. Load the PWMxDCH register and bits <7:6> of

the PWMxDCL register with the PWM duty cycle

value, as determined by Equation 29-2.

5. Configure and start Timer2:

• Clear the TMR2IF interrupt flag bit of the PIR4

register.

• Select the Timer2 prescale value by configuring

the CKPS<2:0> bits of the T2CON register.

• Enable Timer2 by setting the Timer2 ON bit of the

T2CON register.

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29.2 Register Definitions: PWM Control

REGISTER 29-1: PWMxCON: PWM CONTROL REGISTER

R/W-0/0

U-0

—

R-0

R/W-0/0

U-0

—

U-0

—

U-0

—

U-0

—

PWMxEN

PWMxOUT PWMxPOL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7

PWMxEN: PWM Module Enable bit

1= PWM module is enabled

0= PWM module is disabled

bit 6

bit 5

bit 4

Unimplemented: Read as ‘0’

PWMxOUT: PWM Module Output Level when Bit is Read

PWMxPOL: PWMx Output Polarity Select bit

1= PWM output is active-low

0= PWM output is active-high

bit 3-0

Unimplemented: Read as ‘0’

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REGISTER 29-2: PWMxDCH: PWM DUTY CYCLE HIGH BITS

R/W-x/u

bit 0

PWMxDC<9:2>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

PWMxDC<9:2>: PWM Duty Cycle Most Significant bits

These bits are the MSbs of the PWM duty cycle. The two LSbs are found in PWMxDCL Register.

REGISTER 29-3: PWMxDCL: PWM DUTY CYCLE LOW BITS

R/W-x/u

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

PWMxDC<1:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

bit 7-6

bit 5-0

PWMxDC<1:0>: PWM Duty Cycle Least Significant bits

These bits are the LSbs of the PWM duty cycle. The MSbs are found in PWMxDCH Register.

Unimplemented: Read as ‘0’

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TABLE 29-3: SUMMARY OF REGISTERS ASSOCIATED WITH PWMx

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

T2CON

ON

CKPS<2:0>

OUTPS<3:0>

308

292*

291*

200

353

364

T2TMR

T2PR

Holding Register for the 8-bit TMR2 Register

TMR2 Period Register

―

—

―

—

RxyPPS<4:0>

DAT<3:0>

RxyPPS

—

CWG1DAT

CLCxSELy

LCxDyS<5:0>

Legend: -= Unimplemented locations, read as ‘0’. Shaded cells are not used by the PWMx module.

Page with Register information.

*

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30.1 Fundamental Operation

30.0 COMPLEMENTARY WAVEFORM

GENERATOR (CWG) MODULE

The CWG module can operate in six different modes,

as specified by MODE of the CWG1CON0 register:

The Complementary Waveform Generator (CWG)

produces half-bridge, full-bridge, and steering of PWM

waveforms. It is backwards compatible with previous

ECCP functions.

• Half-Bridge mode (Figure 30-9)

• Push-Pull mode (Figure 30-2)

- Full-Bridge mode, Forward (Figure 30-3)

- Full-Bridge mode, Reverse (Figure 30-3)

• Steering mode (Figure 30-10)

The CWG has the following features:

• Six operating modes:

- Synchronous Steering mode

- Asynchronous Steering mode

- Full-Bridge mode, Forward

- Full-Bridge mode, Reverse

- Half-Bridge mode

• Synchronous Steering mode (Figure 30-11)

It may be necessary to guard against the possibility of

circuit faults or a feedback event arriving too late or not

at all. In this case, the active drive must be terminated

before the Fault condition causes damage. Thus, all

output modes support auto-shutdown, which is covered

in 30.10 “Auto-Shutdown”.

- Push-Pull mode

• Output polarity control

• Output steering

30.1.1

HALF-BRIDGE MODE

- Synchronized to rising event

- Immediate effect

In Half-Bridge mode, two output signals are generated

as true and inverted versions of the input as illustrated

in Figure 30-9. A non-overlap (dead-band) time is

inserted between the two outputs as described in

Section 30.5 “Dead-Band Control”.

• Independent 6-bit rising and falling event dead-

band timers

- Clocked dead band

The unused outputs CWG1C and CWG1D drive similar

signals, with polarity independently controlled by the

POLC and POLD bits of the CWG1CON1 register,

respectively.

- Independent rising and falling dead-band

enables

• Auto-shutdown control with:

- Selectable shutdown sources

- Auto-restart enable

- Auto-shutdown pin override control

The CWG modules available are shown in Table 30-1.

TABLE 30-1: AVAILABLE CWG MODULES

Device

CWG1

PIC16(L)F15354/55

●

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30.1.2

PUSH-PULL MODE

In Push-Pull mode, two output signals are generated,

alternating copies of the input as illustrated in

Figure 30-2. This alternation creates the push-pull

effect required for driving some transformer-based

power supply designs.

The push-pull sequencer is reset whenever EN = 0or

if an auto-shutdown event occurs. The sequencer is

clocked by the first input pulse, and the first output

appears on CWG1A.

The unused outputs CWG1C and CWG1D drive copies

of CWG1A and CWG1B, respectively, but with polarity

controlled by the POLC and POLD bits of the

CWG1CON1 register, respectively.

30.1.3

FULL-BRIDGE MODES

In Forward and Reverse Full-Bridge modes, three out-

puts drive static values while the fourth is modulated by

the input data signal. In Forward Full-Bridge mode,

CWG1A is driven to its active state, CWG1B and

CWG1C are driven to their inactive state, and CWG1D

is modulated by the input signal. In Reverse Full-Bridge

mode, CWG1C is driven to its active state, CWG1A and

CWG1D are driven to their inactive states, and CWG1B

is modulated by the input signal. In Full-Bridge mode,

the dead-band period is used when there is a switch

from forward to reverse or vice-versa. This dead-band

control is described in Section 30.5 “Dead-Band Con-

trol”, with additional details in Section 30.6 “Rising

Edge and Reverse Dead Band” and Section 30.7

“Falling Edge and Forward Dead Band”.

The mode selection may be toggled between forward

and reverse toggling the MODE<0> bit of the

CWG1CON0 while keeping MODE<2:1> static, without

disabling the CWG module.

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30.1.4

STEERING MODES

In Steering modes, the data input can be steered to any

or all of the four CWG output pins. In Synchronous

Steering mode, changes to steering selection registers

take effect on the next rising input.

In Non-Synchronous mode, steering takes effect on the

next instruction cycle. Additional details are provided in

Section 30.9 “CWG Steering Mode”.

FIGURE 30-4:

SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES)

Rev. 10-000164B

8/26/2015

See

CWGxISM

Register

CWG_dataA

CWG_dataB

CWG_data

CWG_dataC

CWG_dataD

D

E

Q

CWGxISM <3:0>

R

EN

SHUTDOWN

30.2 Clock Source

The CWG module allows the following clock sources to

be selected:

• Fosc (system clock)

• HFINTOSC (16 MHz only)

The clock sources are selected using the CS bit of the

CWG1CLKCON register.

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30.3 Selectable Input Sources

30.4 Output Control

The CWG generates the output waveforms from the

input sources in Table 30-2.

30.4.1

POLARITY CONTROL

The polarity of each CWG output can be selected

independently. When the output polarity bit is set, the

corresponding output is active-high. Clearing the

output polarity bit configures the corresponding output

as active-low. However, polarity does not affect the

override levels. Output polarity is selected with the

POLx bits of the CWG1CON1. Auto-shutdown and

steering options are unaffected by polarity.

TABLE 30-2: SELECTABLE INPUT

SOURCES

Source Peripheral

CWG input PPS pin

Signal Name

CWG1PPS

CCP1

CCP1_out

CCP2_out

PWM3_out

PWM4_out

PWM5_out

PWM6_out

NCO1_out

C1OUT_sync

C2OUT_sync

LC1_out

CCP2

PWM3

PWM4

PWM5

PWM6

NCO

Comparator C1

Comparator C2

CLC1

CLC2

LC2_out

CLC3

LC3_out

CLC4

LC4_out

The input sources are selected using the CWG1DAT

register.

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FIGURE 30-5:

CWG OUTPUT BLOCK DIAGRAM

Rev. 10-000171B

9/24/2014

LSAC<1:0>

RxyPPS

‘1’

‘0’

11

10

01

00

TRIS Control

1

0

CWG_dataA

POLA

High Z

PPS

CWGxA

CWGxB

CWGxC

CWGxD

1

0

OVRA

OVRB

OVRC

OVRD

STRA⁽¹⁾

LSBD<1:0>

RxyPPS

PPS

‘1’

‘0’

11

10

01

00

TRIS Control

1

0

CWG_dataB

POLB

High Z

1

0

STRB⁽¹⁾

LSAC<1:0>

RxyPPS

PPS

‘1’

‘0’

11

10

01

00

1

0

CWG_dataC

POLC

High Z

1

0

STRC⁽¹⁾

LSBD<1:0>

RxyPPS

PPS

‘1’

‘0’

11

10

01

00

1

0

CWG_dataD

POLD

High Z

1

0

STRD⁽¹⁾

CWG_shutdown

Note 1: STRx is held to 1 in all modes other than Output Steering Mode.

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30.5 Dead-Band Control

30.6 Rising Edge and Reverse Dead

Band

The dead-band control provides non-overlapping PWM

signals to prevent shoot-through current in PWM

switches. Dead-band operation is employed for Half-

Bridge and Full-Bridge modes. The CWG contains two

6-bit dead-band counters. One is used for the rising

edge of the input source control in Half-Bridge mode or

for reverse dead-band Full-Bridge mode. The other is

used for the falling edge of the input source control in

Half-Bridge mode or for forward dead band in Full-

Bridge mode.

CWG1DBR controls the rising edge dead-band time at

the leading edge of CWG1A (Half-Bridge mode) or the

leading edge of CWG1B (Full-Bridge mode). The

CWG1DBR value is double-buffered. When EN = 0,

the CWG1DBR register is loaded immediately when

CWG1DBR is written. When EN = 1, then software

must set the LD bit of the CWG1CON0 register, and the

buffer will be loaded at the next falling edge of the CWG

input signal. If the input source signal is not present for

enough time for the count to be completed, no output

will be seen on the respective output.

Dead band is timed by counting CWG clock periods

from zero up to the value in the rising or falling dead-

band counter registers. See CWG1DBR and

CWG1DBF registers, respectively.

30.7 Falling Edge and Forward Dead

Band

30.5.1

DEAD-BAND FUNCTIONALITY IN

HALF-BRIDGE MODE

CWG1DBF controls the dead-band time at the leading

edge of CWG1B (Half-Bridge mode) or the leading

edge of CWG1D (Full-Bridge mode). The CWG1DBF

value is double-buffered. When EN = 0, the

CWG1DBF register is loaded immediately when

CWG1DBF is written. When EN = 1 then software

must set the LD bit of the CWG1CON0 register, and

the buffer will be loaded at the next falling edge of the

CWG input signal. If the input source signal is not

present for enough time for the count to be completed,

no output will be seen on the respective output.

In Half-Bridge mode, the dead-band counters dictate

the delay between the falling edge of the normal output

and the rising edge of the inverted output. This can be

seen in Figure 30-9.

30.5.2

DEAD-BAND FUNCTIONALITY IN

FULL-BRIDGE MODE

In Full-Bridge mode, the dead-band counters are used

when undergoing a direction change. The MODE<0>

bit of the CWG1CON0 register can be set or cleared

while the CWG is running, allowing for changes from

Forward to Reverse mode. The CWG1A and CWG1C

signals will change upon the first rising input edge

following a direction change, but the modulated signals

(CWG1B or CWG1D, depending on the direction of the

change) will experience a delay dictated by the dead-

band counters. This is demonstrated in Figure 30-3.

Refer to Figure 30-6 and Figure 30-7 for examples.

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EQUATION 30-1: DEAD-BAND

UNCERTAINTY

30.8 Dead-Band Uncertainty

When the rising and falling edges of the input source

are asynchronous to the CWG clock, it creates uncer-

tainty in the dead-band time delay. The maximum

uncertainty is equal to one CWG clock period. Refer to

Equation 30-1 for more details.

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

Example:

FCWG_CLOCK = 16 MHz

Therefore:

1

TDEADBAND_UNCERTAINTY = ----------------------------

Fcwg_clock

1

= ------------------

16MHz

= 62.5ns

FIGURE 30-8:

EXAMPLE OF PWM DIRECTION CHANGE

MODE0

CWG1A

CWG1B

CWG1C

CWG1D

No delay

CWG1DBR

No delay

CWG1DBF

CWG1_data

Note 1: WGPOL{ABCD} = 0

2: The direction bit MODE<0> (Register 30-1) can be written any time during the PWM cycle, and takes effect at the

next rising CWG1_data.

3: When changing directions, CWG1A and CWG1C switch at rising CWG1_data; modulated CWG1B and CWG1D

are held inactive for the dead band duration shown; dead band affects only the first pulse after the direction change.

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FIGURE 30-9:

CWG HALF-BRIDGE MODE OPERATION

CWG1_clock

CWG1A

CWG1C

Rising Event Dead Band

Falling Event Dead Band

Rising Event D

Falling Event Dead Band

CWG1B

CWG1D

CWG1_data

Note: CWG1_rising_src = CCP1_out, CWG1_falling_src = ~CCP1_out

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30.9.1

STEERING SYNCHRONIZATION

30.9 CWG Steering Mode

Changing the MODE bits allows for two modes of

steering, synchronous and asynchronous.

In Steering mode (MODE = 00x), the CWG allows any

combination of the CWG1x pins to be the modulated

signal. The same signal can be simultaneously avail-

able on multiple pins, or a fixed-value output can be

presented.

When MODE = 000, the steering event is asynchro-

nous and will happen at the end of the instruction that

writes to STRx (that is, immediately). In this case, the

output signal at the output pin may be an incomplete

waveform. This can be useful for immediately removing

a signal from the pin.

When the respective STRx bit of CWG1OCON0 is ‘0’,

the corresponding pin is held at the level defined. When

the respective STRx bit of CWG1OCON0 is ‘1’, the pin

is driven by the input data signal. The user can assign

the input data signal to one, two, three, or all four output

pins.

When MODE = 001, the steering update is synchro-

nous and occurs at the beginning of the next rising

edge of the input data signal. In this case, steering the

output on/off will always produce a complete waveform.

The POLx bits of the CWG1CON1 register control the

signal polarity only when STRx = 1.

Figure 30-10 and Figure 30-11 illustrate the timing of

asynchronous and synchronous steering, respectively.

The CWG auto-shutdown operation also applies in

Steering modes as described in Section 30.10 “Auto-

Shutdown”. An auto-shutdown event will only affect

pins that have STRx = 1.

FIGURE 30-10:

EXAMPLE OF ASYNCHRONOUS STEERING EVENT (MODE<2:0> = 000)

Rising Event

CWG1_data

(Rising and Falling Source)

STR<D:A>

OVR<D:A> Data

CWG1<D:A>

OVR<D:A>

follows CWG1_data

FIGURE 30-11:

EXAMPLE OF STEERING EVENT (MODE<2:0> = 001)

CWG1_data

(Rising and Falling Source)

STR<D:A>

CWG1<D:A>

OVR<D:A> Data

follows CWG1_data

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30.10 Auto-Shutdown

30.11 Operation During Sleep

Auto-shutdown is a method to immediately override the

CWG output levels with specific overrides that allow for

safe shutdown of the circuit. The shutdown state can be

either cleared automatically or held until cleared by

software. The auto-shutdown circuit is illustrated in

Figure 30-12.

The CWG module operates independently from the

system clock and will continue to run during Sleep,

provided that the clock and input sources selected

remain active.

The HFINTOSC remains active during Sleep when all

the following conditions are met:

• CWG module is enabled

• Input source is active

30.10.1 SHUTDOWN

The shutdown state can be entered by either of the

following two methods:

• HFINTOSC is selected as the clock source,

regardless of the system clock source selected.

• Software generated

• External Input

In other words, if the HFINTOSC is simultaneously

selected as the system clock and the CWG clock

source, when the CWG is enabled and the input source

is active, then the CPU will go idle during Sleep, but the

HFINTOSC will remain active and the CWG will con-

tinue to operate. This will have a direct effect on the

Sleep mode current.

30.10.1.1 Software Generated Shutdown

Setting the SHUTDOWN bit of the CWG1AS0 register

will force the CWG into the shutdown state.

When the auto-restart is disabled, the shutdown state

will persist as long as the SHUTDOWN bit is set.

When auto-restart is enabled, the SHUTDOWN bit will

clear automatically and resume operation on the next

rising edge event.

30.10.2 EXTERNAL INPUT SOURCE

External shutdown inputs provide the fastest way to

safely suspend CWG operation in the event of a Fault

condition. When any of the selected shutdown inputs

goes active, the CWG outputs will immediately go to the

selected override levels without software delay. Several

input sources can be selected to cause a shutdown con-

dition. All input sources are active-low. The sources are:

• Comparator C1OUT_sync

• Comparator C2OUT_sync

• Timer2 – TMR2_postscaled

• CWG1IN input pin

Shutdown inputs are selected using the CWG1AS1

register (Register 30-6).

Note:

Shutdown inputs are level sensitive, not

edge sensitive. The shutdown state can-

not be cleared, except by disabling auto-

shutdown, as long as the shutdown input

level persists.

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30.12.2 AUTO-SHUTDOWN RESTART

30.12 Configuring the CWG

After an auto-shutdown event has occurred, there are

two ways to resume operation:

The following steps illustrate how to properly configure

the CWG.

• Software controlled

• Auto-restart

1. Ensure that the TRIS control bits corresponding

to the desired CWG pins for your application are

set so that the pins are configured as inputs.

The restart method is selected with the REN bit of the

CWG1CON2 register. Waveforms of software con-

trolled and automatic restarts are shown in Figure 30-13

and Figure 30-14.

2. Clear the EN bit, if not already cleared.

3. Set desired mode of operation with the MODE

bits.

4. Set desired dead-band times, if applicable to

mode, with the CWG1DBR and CWG1DBF

registers.

30.12.2.1 Software Controlled Restart

When the REN bit of the CWG1AS0 register is cleared,

the CWG must be restarted after an auto-shutdown

event by software. Clearing the shutdown state

requires all selected shutdown inputs to be low, other-

wise the SHUTDOWN bit will remain set. The overrides

will remain in effect until the first rising edge event after

the SHUTDOWN bit is cleared. The CWG will then

resume operation.

5. Setup the following controls in the CWG1AS0

and CWG1AS1 registers.

a. Select the desired shutdown source.

b. Select both output overrides to the desired

levels (this is necessary even if not using auto-

shutdown because start-up will be from a shut-

down state).

30.12.2.2 Auto-Restart

c. Set which pins will be affected by auto-shut-

down with the CWG1AS1 register.

When the REN bit of the CWG1CON2 register is set,

the CWG will restart from the auto-shutdown state

automatically. The SHUTDOWN bit will clear automati-

cally when all shutdown sources go low. The overrides

will remain in effect until the first rising edge event after

the SHUTDOWN bit is cleared. The CWG will then

resume operation.

d. Set the SHUTDOWN bit and clear the REN bit.

6. Select the desired input source using the

CWG1DAT register.

7. Configure the following controls.

a. Select desired clock source using the

CWG1CLKCON register.

b. Select the desired output polarities using the

CWG1CON1 register.

c. Set the output enables for the desired outputs.

8. Set the EN bit.

9. Clear TRIS control bits corresponding to the

desired output pins to configure these pins as

outputs.

10. If auto-restart is to be used, set the REN bit and

the SHUTDOWN bit will be cleared automati-

cally. Otherwise, clear the SHUTDOWN bit to

start the CWG.

30.12.1 PIN OVERRIDE LEVELS

The levels driven to the output pins, while the shutdown

input is true, are controlled by the LSBD and LSAC bits

of the CWG1AS0 register. LSBD<1:0> controls the

CWG1B and D override levels and LSAC<1:0> controls

the CWG1A and C override levels. The control bit logic

level corresponds to the output logic drive level while in

the shutdown state. The polarity control does not affect

the override level.

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30.13 Register Definitions: CWG Control

Long bit name prefixes for the CWG peripherals are

shown in Section 1.1 “Register and Bit Naming

Conventions”.

REGISTER 30-1: CWG1CON0: CWG1 CONTROL REGISTER 0

R/W-0/0

EN

R/W/HC-0/0

LD⁽¹⁾

U-0

—

U-0

—

U-0

—

R/W-0/0

bit 0

MODE<2:0>

bit 7

Legend:

HC = Bit is cleared by hardware

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

EN: CWG1 Enable bit

1= Module is enabled

0= Module is disabled

LD: CWG1 Load Buffer bits⁽¹⁾

1= Buffers to be loaded on the next rising/falling event

0= Buffers not loaded

bit 5-3

bit 2-0

Unimplemented: Read as ‘0’

MODE<2:0>: CWG1 Mode bits

111= Reserved

110= Reserved

101= CWG outputs operate in Push-Pull mode

100= CWG outputs operate in Half-Bridge mode

011= CWG outputs operate in Reverse Full-Bridge mode

010= CWG outputs operate in Forward Full-Bridge mode

001= CWG outputs operate in Synchronous Steering mode

000= CWG outputs operate in Steering mode

Note 1: This bit can only be set after EN = 1and cannot be set in the same instruction that EN is set.

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REGISTER 30-2: CWG1CON1: CWG1 CONTROL REGISTER 1

U-0

—

U-0

—

R-x

IN

U-0

—

R/W-0/0

POLD

R/W-0/0

POLC

R/W-0/0

POLB

R/W-0/0

POLA

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5

Unimplemented: Read as ‘0’

IN: CWG Input Value bit

bit 4

Unimplemented: Read as ‘0’

bit 3

POLD: CWG1D Output Polarity bit

1= Signal output is inverted polarity

0= Signal output is normal polarity

bit 2

bit 1

bit 0

POLC: CWG1C Output Polarity bit

1= Signal output is inverted polarity

0= Signal output is normal polarity

POLB: CWG1B Output Polarity bit

1= Signal output is inverted polarity

0= Signal output is normal polarity

POLA: CWG1A Output Polarity bit

1= Signal output is inverted polarity

0= Signal output is normal polarity

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REGISTER 30-3: CWG1DBR: CWG1 RISING DEAD-BAND COUNTER REGISTER

U-0

—

U-0

—

R/W-x/u

bit 0

DBR<5:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

DBR<5:0>: Rising Event Dead-Band Value for Counter bits

REGISTER 30-4: CWG1DBF: CWG1 FALLING DEAD-BAND COUNTER REGISTER

U-0

—

U-0

—

R/W-x/u

bit 0

DBF<5:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

DBF<5:0>: Falling Event Dead-Band Value for Counter bits

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REGISTER 30-5: CWG1AS0: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 0

R/W/HS-0/0

SHUTDOWN^{(1, 2)}

bit 7

R/W-0/0

REN

R/W-0/0

R/W-1/1

R/W-0/0

R/W-1/1

U-0

—

U-0

—

LSBD<1:0>

LSAC<1:0>

bit 0

Legend:

HC = Bit is cleared by hardware

R = Readable bit

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

W = Writable bit

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other

Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

q = Value depends on condition

bit 7

SHUTDOWN: Auto-Shutdown Event Status bit^{(1, 2)}

1= An Auto-Shutdown state is in effect

0= No Auto-shutdown event has occurred

bit 6

REN: Auto-Restart Enable bit

1= Auto-restart enabled

0= Auto-restart disabled

bit 5-4

LSBD<1:0>: CWG1B and CWG1D Auto-Shutdown State Control bits

11=A logic ‘1’ is placed on CWG1B/D when an auto-shutdown event is present

10=A logic ‘0’ is placed on CWG1B/D when an auto-shutdown event is present

01=Pin is tri-stated on CWG1B/D when an auto-shutdown event is present

00=The inactive state of the pin, including polarity, is placed on CWG1B/D after the required dead-

band interval

bit 3-2

LSAC<1:0>: CWG1A and CWG1C Auto-Shutdown State Control bits

11=A logic ‘1’ is placed on CWG1A/C when an auto-shutdown event is present

10=A logic ‘0’ is placed on CWG1A/C when an auto-shutdown event is present

01=Pin is tri-stated on CWG1A/C when an auto-shutdown event is present

00=The inactive state of the pin, including polarity, is placed on CWG1A/C after the required dead-

band interval

bit 1-0

Unimplemented: Read as ‘0’

Note 1: This bit may be written while EN = 0 (CWG1CON0 register) to place the outputs into the shutdown

configuration.

2: The outputs will remain in auto-shutdown state until the next rising edge of the input signal after this bit is

cleared.

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REGISTER 30-6: CWG1AS1: CWG1 AUTO-SHUTDOWN CONTROL REGISTER 1

U-1

—

U-1

—

U-1

—

R/W-0/0

AS4E

R/W-0/0

AS3E

R/W-0/0

AS2E

R/W-0/0

AS1E

R/W-0/0

AS0E

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-5

bit 4

Unimplemented: Read as ‘0’

AS4E: CLC2 Output bit

1= LC2_out shut-down is enabled

0= LC2_out shut-down is disabled

bit 3

bit 2

bit 0

AS3E: Comparator C2 Output bit

1= C2 output shut-down is enabled

0= C2 output shut-down is disabled

AS2E: Comparator C1 Output bit

1= C1 output shut-down is enabled

0= C1 output shut-down is disabled

AS1E: TMR2 Postscale Output bit

1= TMR2 Postscale shut-down is enabled

0= TMR2 Postscale shut-down is disabled

AS0E: CWG1 Input Pin bit

1= Input pin selected by CWG1PPS shut-down is enabled

0= Input pin selected by CWG1PPS shut-down is disabled

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REGISTER 30-7: CWG1STR: CWG1 STEERING CONTROL REGISTER⁽¹⁾

R/W-0/0

OVRD

R/W-0/0

OVRC

R/W-0/0

OVRB

R/W-0/0

OVRA

R/W-0/0

STRD⁽²⁾

R/W-0/0

STRC⁽²⁾

R/W-0/0

STRB⁽²⁾

R/W-0/0

STRA⁽²⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7

bit 6

bit 5

bit 4

bit 3

OVRD: Steering Data D bit

OVRC: Steering Data C bit

OVRB: Steering Data B bit

OVRA: Steering Data A bit

STRD: Steering Enable D bit⁽²⁾

1= CWG1D output has the CWG1_data waveform with polarity control from POLD bit

0= CWG1D output is assigned the value of OVRD bit

bit 2

bit 1

bit 0

STRC: Steering Enable C bit⁽²⁾

1= CWG1C output has the CWG1_data waveform with polarity control from POLC bit

0= CWG1C output is assigned the value of OVRC bit

STRB: Steering Enable B bit⁽²⁾

1= CWG1B output has the CWG1_data waveform with polarity control from POLB bit

0= CWG1B output is assigned the value of OVRB bit

STRA: Steering Enable A bit⁽²⁾

1= CWG1A output has the CWG1_data waveform with polarity control from POLA bit

0= CWG1A output is assigned the value of OVRA bit

Note 1: The bits in this register apply only when MODE<2:0> = 00x.

2: This bit is effectively double-buffered when MODE<2:0> = 001.

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REGISTER 30-8: CWG1CLK: CWG1 CLOCK SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CS

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-1

bit 0

Unimplemented: Read as ‘0’

CS: CWG1 Clock Selection bit

1= HFINTOSC 16 MHz is selected

0= FOSC is selected

REGISTER 30-9: CWG1DAT: CWG1 INPUT SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

DAT<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

q = Value depends on condition

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

DAT<3:0>: CWG1 Input Selection bits

1111=Reserved. No channel connected.

1110=Reserved. No channel connected.

1101=LC4_out

1100=LC3_out

1011=LC2_out

1010=LC1_out

1001=Comparator C2 out

1000=Comparator C1 out

0111=NCO1 output

0110=PWM6_out

0101=PWM5_out

0100=PWM4_out

0011=PWM3_out

0010=CCP2_out

0001=CCP1_out

0000=CWG11CLK

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TABLE 30-3:

SUMMARY OF REGISTERS ASSOCIATED WITH CWG

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CWG1CLKCON

CWG1DAT

CWG1DBR

CWG1DBF

CWG1CON0

CWG1CON1

CWG1AS0

CWG1AS1

CWG1STR

—

CS

353

349

352

348

350

351

352

—

DAT<3:0>

—

DBR<5:0>

DBF<5:0>

—

EN

—

LD

—

IN

—

MODE<2:0>

POLB

—

POLD

POLC

POLA

—

SHUTDOWN

—

REN

—

LSBD<1:0>

LSAC<1:0>

—

AS4E

AS3E

STRD

AS2E

STRC

AS1E

AS0E

STRA

OVRD

OVRC

OVRB

OVRA

STRB

Legend:

– = unimplemented locations read as ‘0’. Shaded cells are not used by CWG.

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Refer to Figure 31-1 for a simplified diagram showing

signal flow through the CLCx.

31.0 CONFIGURABLE LOGIC CELL

(CLC)

Possible configurations include:

The Configurable Logic Cell (CLCx) module provides

programmable logic that operates outside the speed

limitations of software execution. The logic cell selects

from 40 input signals and, through the use of

configurable gates, reduces the inputs to four logic

lines that drive one of eight selectable single-output

logic functions.

•

Combinatorial Logic

- AND

- NAND

- AND-OR

- AND-OR-INVERT

- OR-XOR

Input sources are a combination of the following:

- OR-XNOR

• I/O pins

• Latches

• Internal clocks

• Peripherals

• Register bits

- S-R

- Clocked D with Set and Reset

- Transparent D with Set and Reset

- Clocked J-K with Reset

The output can be directed internally to peripherals and

to an output pin.

The CLC modules available are shown in Table 31-1.

TABLE 31-1: AVAILABLE CLC MODULES

Device

CLC1 CLC2 CLC3 CLC4

PIC16(L)F15354/55

●

Note:

The CLC1, CLC2, CLC3 and CLC4 are

four separate module instances of the

same CLC module design. Throughout

this section, the lower case ‘x’ in register

and bit names is a generic reference to

the CLC number (which should be substi-

tuted with 1, 2, 3, or 4 during code devel-

opment). For example, the control register

is generically described in this chapter as

CLCxCON, but the actual device registers

are CLC1CON, CLC2CON, CLC3CON

and CLC4CON. Similarly, the LCxEN bit

represents the LC1EN, LC2EN, LC3EN

and LC4EN bits.

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FIGURE 31-1:

CLCx SIMPLIFIED BLOCK DIAGRAM

Rev. 10-000025H

11/9/2016

OUT

CLCxOUT

D

Q

Q1

LCx_in[0]

LCx_in[1]

LCx_in[2]

CLCx_out

to Peripherals

EN

.

lcxg1

CLCxPPS

PPS

lcxg2

Logic

lcxq

Function

CLCx

lcxg3

(2)

lcxg4

POL

TRIS

MODE<2:0>

Interrupt

det

LCx_in[n-2]

LCx_in[n-1]

LCx_in[n]

INTP

INTN

set bit

CLCxIF

Interrupt

det

Note 1: See Figure 31-2: Input Data Selection and Gating.

2: See Figure 31-3: Programmable Logic Functions.

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TABLE 31-2:

CLCx DATA INPUT SELECTION

31.1 CLCx Setup

LCxDyS<5:0>

Programming the CLCx module is performed by

configuring the four stages in the logic signal flow. The

four stages are:

CLCx Input Source

Value

101000 to 111111 [40+]

100111 [39]

100110 [38]

100101 [37]

100100 [36]

100011 [35]

100010 [34]

100001 [33]

100000 [32]

011111 [31]

011110 [30]

011101 [29]

011100 [28]

011011 [27]

011010 [26]

011001 [25]

011000 [24]

010111 [23]

010110 [22]

010101 [21]

010100 [20]

010011 [19]

010010 [18]

010001 [17]

010000 [16]

001111 [15]

001110 [14]

001101 [13]

001100 [12]

001011 [11]

001010 [10]

001001 [9]

Reserved

CWG1B output

CWG1A output

MSSP2 SCK output

MSSP2 SDO output

MSSP1 SCK output

MSSP1 SDO output

EUSART2 (TX/CK) output

EUSART2 (DT) output

EUSART1 (TX/CK) output

EUSART1 (DT) output

CLC4 output

• Data selection

• Data gating

• Logic function selection

• Output polarity

Each stage is setup at run time by writing to the corre-

sponding CLCx Special Function Registers. This has

the added advantage of permitting logic reconfiguration

on-the-fly during program execution.

31.1.1

DATA SELECTION

There are 40 signals available as inputs to the

configurable logic. Four 40-input multiplexers are used

to select the inputs to pass on to the next stage.

CLC3 output

CLC2 output

CLC1 output

Data selection is through four multiplexers as indicated

on the left side of Figure 31-2. Data inputs in the figure

are identified by a generic numbered input name.

IOCIF

ZCD output

C2OUT

Table 31-2 correlates the generic input name to the

actual signal for each CLC module. The column labeled

‘LCxDyS<5:0> Value’ indicates the MUX selection code

for the selected data input. LCxDyS is an abbreviation to

identify specific multiplexers: LCxD1S<5:0> through

LCxD4S<5:0>.

C1OUT

NCO1 output

PWM6 output

PWM5 output

PWM4 output

PWM3 output

CCP2 output

Data inputs are selected with CLCxSEL0 through

CLCxSEL3

registers

(Register 31-3

through

CCP1 output

Register 31-6).

Timer2 overflow

Timer1 overflow

Timer0 overflow

CLKR

ADCRC

SOSC

001000 [8]

MFINTOSC (32 kHz)

MFINTOSC (500 kHz)

LFINTOSC

000111 [7]

000110 [6]

000101 [5]

HFINTOSC

000100 [4]

FOSC

000011 [3]

CLCIN3PPS

000010 [2]

CLCIN2PPS

000001 [1]

CLCIN1PPS

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Data gating is indicated in the right side of Figure 31-2.

Only one gate is shown in detail. The remaining three

gates are configured identically with the exception that

the data enables correspond to the enables for that

gate.

31.1.2

DATA GATING

Outputs from the input multiplexers are directed to the

desired logic function input through the data gating

stage. Each data gate can direct any combination of the

four selected inputs.

31.1.3

LOGIC FUNCTION

Note:

Data gating is undefined at power-up.

There are eight available logic functions including:

The gate stage is more than just signal direction. The

gate can be configured to direct each input signal as

inverted or non-inverted data. The output of each gate

can be inverted before going on to the logic function

stage.

• AND-OR

• OR-XOR

• AND

• S-R Latch

The gating is in essence a 1-to-4 input AND/NAND/OR/

NOR gate. When every input is inverted and the output

is inverted, the gate is an OR of all enabled data inputs.

When the inputs and output are not inverted, the gate

is an AND or all enabled inputs.

• D Flip-Flop with Set and Reset

• D Flip-Flop with Reset

• J-K Flip-Flop with Reset

• Transparent Latch with Set and Reset

Logic functions are shown in Figure 31-2. Each logic

function has four inputs and one output. The four inputs

are the four data gate outputs of the previous stage.

The output is fed to the inversion stage and from there

to other peripherals, an output pin, and back to the

CLCx itself.

Table 31-3 summarizes the basic logic that can be

obtained in gate 1 by using the gate logic select bits.

The table shows the logic of four input variables, but

each gate can be configured to use less than four. If

no inputs are selected, the output will be zero or one,

depending on the gate output polarity bit.

31.1.4

OUTPUT POLARITY

TABLE 31-3: DATA GATING LOGIC

The last stage in the Configurable Logic Cell is the

output polarity. Setting the LCxPOL bit of the CLCxPOL

register inverts the output signal from the logic stage.

Changing the polarity while the interrupts are enabled

will cause an interrupt for the resulting output transition.

CLCxGLSy

0x55

LCxGyPOL

Gate Logic

4-input AND

1

0x55

0xAA

0x00

0

1

0

1

4-input NAND

4-input NOR

4-input OR

Logic 0

Logic 1

It is possible (but not recommended) to select both the

true and negated values of an input. When this is done,

the gate output is zero, regardless of the other inputs,

but may emit logic glitches (transient-induced pulses).

If the output of the channel must be zero or one, the

recommended method is to set all gate bits to zero and

use the gate polarity bit to set the desired level.

Data gating is configured with the logic gate select

registers as follows:

• Gate 1: CLCxGLS0 (Register 31-7)

• Gate 2: CLCxGLS1 (Register 31-8)

• Gate 3: CLCxGLS2 (Register 31-9)

• Gate 4: CLCxGLS3 (Register 31-10)

Register number suffixes are different than the gate

numbers because other variations of this module have

multiple gate selections in the same register.

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31.2 CLCx Interrupts

31.6 CLCx Setup Steps

An interrupt will be generated upon a change in the

output value of the CLCx when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in each CLC for this purpose.

The following steps should be followed when setting up

the CLCx:

• Disable CLCx by clearing the LCxEN bit.

• Select desired inputs using CLCxSEL0 through

CLCxSEL3 registers (See Table 31-2).

• Clear any associated ANSEL bits.

The CLCxIF bit of the associated PIR5 register will be

set when either edge detector is triggered and its asso-

ciated enable bit is set. The LCxINTP enables rising

edge interrupts and the LCxINTN bit enables falling

edge interrupts. Both are located in the CLCxCON

register.

• Enable the chosen inputs through the four gates

using CLCxGLS0, CLCxGLS1, CLCxGLS2, and

CLCxGLS3 registers.

• Select the gate output polarities with the

LCxGyPOL bits of the CLCxPOL register.

To fully enable the interrupt, set the following bits:

• CLCxIE bit of the PIE5 register

• Select the desired logic function with the

LCxMODE<2:0> bits of the CLCxCON register.

• LCxINTP bit of the CLCxCON register (for a rising

edge detection)

• Select the desired polarity of the logic output with

the LCxPOL bit of the CLCxPOL register. (This

step may be combined with the previous gate out-

put polarity step).

• LCxINTN bit of the CLCxCON register (for a

falling edge detection)

• PEIE and GIE bits of the INTCON register

• If driving a device pin, set the desired pin PPS

control register and also clear the TRIS bit

corresponding to that output.

The CLCxIF bit of the PIR5 register, must be cleared in

software as part of the interrupt service. If another edge

is detected while this flag is being cleared, the flag will

still be set at the end of the sequence.

• If interrupts are desired, configure the following

bits:

- Set the LCxINTP bit in the CLCxCON register

for rising event.

31.3 Output Mirror Copies

Mirror copies of all LCxCON output bits are contained

in the CLCxDATA register. Reading this register reads

the outputs of all CLCs simultaneously. This prevents

any reading skew introduced by testing or reading the

LCxOUT bits in the individual CLCxCON registers.

- Set the LCxINTN bit in the CLCxCON

register for falling event.

- Set the CLCxIE bit of the PIE5 register.

- Set the GIE and PEIE bits of the INTCON

register.

• Enable the CLCx by setting the LCxEN bit of the

CLCxCON register.

31.4 Effects of a Reset

The CLCxCON register is cleared to zero as the result

of a Reset. All other selection and gating values remain

unchanged.

31.5 Operation During Sleep

The CLC module operates independently from the

system clock and will continue to run during Sleep,

provided that the input sources selected remain active.

The HFINTOSC remains active during Sleep when the

CLC module is enabled and the HFINTOSC is

selected as an input source, regardless of the system

clock source selected.

In other words, if the HFINTOSC is simultaneously

selected as the system clock and as a CLC input

source, when the CLC is enabled, the CPU will go idle

during Sleep, but the CLC will continue to operate and

the HFINTOSC will remain active.

This will have a direct effect on the Sleep mode current.

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FIGURE 31-2:

INPUT DATA SELECTION AND GATING

Data Selection

LCx_in

Data GATE 1

lcxd1T

lcxd1N

LCxD1G1T

LCxD1G1N

LCxD2G1T

LCxD2G1N

LCxD3G1T

LCxD3G1N

LCxD4G1T

LCxD4G1N

LCx_in

LCxD1S<5:0>

lcxg1

LCxG1POL

lcxd2T

lcxd2N

LCx_in

LCxD2S<5:0>

LCxD3S<5:0>

LCxD4S<5:0>

Data GATE 2

lcxg2

lcxd3T

lcxd3N

(Same as Data GATE 1)

Data GATE 3

LCx_in

lcxg3

lcxg4

(Same as Data GATE 1)

Data GATE 4

(Same as Data GATE 1)

lcxd4T

lcxd4N

LCx_in

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FIGURE 31-3:

PROGRAMMABLE LOGIC FUNCTIONS

Rev. 10-000122A

5/18/2016

AND-OR

OR-XOR

lcxg1

lcxg2

lcxg1

lcxg2

lcxq

lcxg3

lcxg4

lcxg3

lcxg4

LCxMODE<2:0> = 000

LCxMODE<2:0> = 001

4-input AND

S-R Latch

lcxg1

lcxq

S

R

Q

lcxg2

lcxg3

lcxq

lcxg3

lcxg4

LCxMODE<2:0> = 010

LCxMODE<2:0> = 011

1-Input D Flip-Flop with S and R

2-Input D Flip-Flop with R

lcxg4

lcxg2

S

D

Q

D

Q

lcxg2

lcxq

lcxg1

lcxg3

lcxg1

R

lcxg3

LCxMODE<2:0> = 100

LCxMODE<2:0> = 101

J-K Flip-Flop with R

1-Input Transparent Latch with S and R

lcxg4

J

Q

lcxg2

lcxq

S

D

Q

lcxg2

lcxq

lcxg1

lcxg4

K

R

LE

lcxg3

lcxg1

R

lcxg3

LCxMODE<2:0> = 110

LCxMODE<2:0> = 111

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31.7 Register Definitions: CLC Control

REGISTER 31-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER

R/W-0/0

LCxEN

U-0

—

R-0/0

R/W-0/0

bit 0

LCxOUT

LCxINTP

LCxINTN

LCxMODE<2:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

LCxEN: Configurable Logic Cell Enable bit

1= Configurable logic cell is enabled and mixing input signals

0= Configurable logic cell is disabled and has logic zero output

bit 6

bit 5

Unimplemented: Read as ‘0’

LCxOUT: Configurable Logic Cell Data Output bit

Read-only: logic cell output data, after LCPOL; sampled from CLCxOUT

LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit

bit 4

1= CLCxIF will be set when a rising edge occurs on CLCxOUT

0= CLCxIF will not be set

bit 3

LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit

1= CLCxIF will be set when a falling edge occurs on CLCxOUT

0= CLCxIF will not be set

bit 2-0

LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits

111=Cell is 1-input transparent latch with S and R

110=Cell is J-K flip-flop with R

101=Cell is 2-input D flip-flop with R

100=Cell is 1-input D flip-flop with S and R

011=Cell is S-R latch

010=Cell is 4-input AND

001=Cell is OR-XOR

000=Cell is AND-OR

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REGISTER 31-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER

R/W-0/0

LCxPOL

U-0

—

U-0

—

U-0

—

R/W-x/u

LCxG4POL LCxG3POL

LCxG2POL LCxG1POL

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

LCxPOL: CLCxOUT Output Polarity Control bit

1= The output of the logic cell is inverted

0= The output of the logic cell is not inverted

bit 6-4

bit 3

Unimplemented: Read as ‘0’

LCxG4POL: Gate 3 Output Polarity Control bit

1= The output of gate 3 is inverted when applied to the logic cell

0= The output of gate 3 is not inverted

bit 2

bit 1

bit 0

LCxG3POL: Gate 2 Output Polarity Control bit

1= The output of gate 2 is inverted when applied to the logic cell

0= The output of gate 2 is not inverted

LCxG2POL: Gate 1 Output Polarity Control bit

1= The output of gate 1 is inverted when applied to the logic cell

0= The output of gate 1 is not inverted

LCxG1POL: Gate 0 Output Polarity Control bit

1= The output of gate 0 is inverted when applied to the logic cell

0= The output of gate 0 is not inverted

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REGISTER 31-3: CLCxSEL0: GENERIC CLCx DATA 0 SELECT REGISTER

U-0

—

U-0

—

R/W-x/u

LCxD1S<5:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

LCxD1S<5:0>: CLCx Data1 Input Selection bits

See Table 31-2.

REGISTER 31-4: CLCxSEL1: GENERIC CLCx DATA 1 SELECT REGISTER

U-0

—

U-0

—

R/W-x/u

LCxD2S<5:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

LCxD2S<5:0>: CLCx Data 2 Input Selection bits

See Table 31-2.

REGISTER 31-5: CLCxSEL2: GENERIC CLCx DATA 2 SELECT REGISTER

U-0

—

U-0

—

R/W-x/u

LCxD3S<5:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

LCxD3S<5:0>: CLCx Data 3 Input Selection bits

See Table 31-2.

REGISTER 31-6: CLCxSEL3: GENERIC CLCx DATA 3 SELECT REGISTER

U-0

—

U-0

—

R/W-x/u

LCxD4S<5:0>

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

LCxD4S<5:0>: CLCx Data 4 Input Selection bits

See Table 31-2.

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REGISTER 31-7: CLCxGLS0: GATE 0 LOGIC SELECT REGISTER

R/W-x/u

LCxG1D4T

LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T

LCxG1D2N

LCxG1D1T LCxG1D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG1D4T: Gate 0 Data 4 True (non-inverted) bit

1= CLCIN3 (true) is gated into CLCx Gate 0

0= CLCIN3 (true) is not gated into CLCx Gate 0

LCxG1D4N: Gate 0 Data 4 Negated (inverted) bit

1= CLCIN3 (inverted) is gated into CLCx Gate 0

0= CLCIN3 (inverted) is not gated into CLCx Gate 0

LCxG1D3T: Gate 0 Data 3 True (non-inverted) bit

1= CLCIN2 (true) is gated into CLCx Gate 0

0= CLCIN2 (true) is not gated into CLCx Gate 0

LCxG1D3N: Gate 0 Data 3 Negated (inverted) bit

1= CLCIN2 (inverted) is gated into CLCx Gate 0

0= CLCIN2 (inverted) is not gated into CLCx Gate 0

LCxG1D2T: Gate 0 Data 2 True (non-inverted) bit

1= CLCIN1 (true) is gated into CLCx Gate 0

0= CLCIN1 (true) is not gated into l CLCx Gate 0

LCxG1D2N: Gate 0 Data 2 Negated (inverted) bit

1= CLCIN1 (inverted) is gated into CLCx Gate 0

0= CLCIN1 (inverted) is not gated into CLCx Gate 0

LCxG1D1T: Gate 0 Data 1 True (non-inverted) bit

1= CLCIN0 (true) is gated into CLCx Gate 0

0= CLCIN0 (true) is not gated into CLCx Gate 0

LCxG1D1N: Gate 0 Data 1 Negated (inverted) bit

1= CLCIN0 (inverted) is gated into CLCx Gate 0

0= CLCIN0 (inverted) is not gated into CLCx Gate 0

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REGISTER 31-8: CLCxGLS1: GATE 1 LOGIC SELECT REGISTER

R/W-x/u

LCxG2D4T

LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T

LCxG2D2N

LCxG2D1T LCxG2D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG2D4T: Gate 1 Data 4 True (non-inverted) bit

1= CLCIN3 (true) is gated into CLCx Gate 1

0= CLCIN3 (true) is not gated into CLCx Gate 1

LCxG2D4N: Gate 1 Data 4 Negated (inverted) bit

1= CLCIN3 (inverted) is gated into CLCx Gate 1

0= CLCIN3 (inverted) is not gated into CLCx Gate 1

LCxG2D3T: Gate 1 Data 3 True (non-inverted) bit

1= CLCIN2 (true) is gated into CLCx Gate 1

0= CLCIN2 (true) is not gated into CLCx Gate 1

LCxG2D3N: Gate 1 Data 3 Negated (inverted) bit

1= CLCIN2 (inverted) is gated into CLCx Gate 1

0= CLCIN2 (inverted) is not gated into CLCx Gate 1

LCxG2D2T: Gate 1 Data 2 True (non-inverted) bit

1= CLCIN1 (true) is gated into CLCx Gate 1

0= CLCIN1 (true) is not gated into CLCx Gate 1

LCxG2D2N: Gate 1 Data 2 Negated (inverted) bit

1= CLCIN1 (inverted) is gated into CLCx Gate 1

0= CLCIN1 (inverted) is not gated into CLCx Gate 1

LCxG2D1T: Gate 1 Data 1 True (non-inverted) bit

1= CLCIN0 (true) is gated into CLCx Gate 1

0= CLCIN0 (true) is not gated into CLCx Gate1

LCxG2D1N: Gate 1 Data 1 Negated (inverted) bit

1= CLCIN0 (inverted) is gated into CLCx Gate 1

0= CLCIN0 (inverted) is not gated into CLCx Gate 1

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REGISTER 31-9: CLCxGLS2: GATE 2 LOGIC SELECT REGISTER

R/W-x/u

LCxG3D4T

LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T

LCxG3D2N

LCxG3D1T LCxG3D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG3D4T: Gate 2 Data 4 True (non-inverted) bit

1= CLCIN3 (true) is gated into CLCx Gate 2

0= CLCIN3 (true) is not gated into CLCx Gate 2

LCxG3D4N: Gate 2 Data 4 Negated (inverted) bit

1= CLCIN3 (inverted) is gated into CLCx Gate 2

0= CLCIN3 (inverted) is not gated into CLCx Gate 2

LCxG3D3T: Gate 2 Data 3 True (non-inverted) bit

1= CLCIN2 (true) is gated into CLCx Gate 2

0= CLCIN2 (true) is not gated into CLCx Gate 2

LCxG3D3N: Gate 2 Data 3 Negated (inverted) bit

1= CLCIN2 (inverted) is gated into CLCx Gate 2

0= CLCIN2 (inverted) is not gated into CLCx Gate 2

LCxG3D2T: Gate 2 Data 2 True (non-inverted) bit

1= CLCIN1 (true) is gated into CLCx Gate 2

0= CLCIN1 (true) is not gated into CLCx Gate 2

LCxG3D2N: Gate 2 Data 2 Negated (inverted) bit

1= CLCIN1 (inverted) is gated into CLCx Gate 2

0= CLCIN1 (inverted) is not gated into CLCx Gate 2

LCxG3D1T: Gate 2 Data 1 True (non-inverted) bit

1= CLCIN0 (true) is gated into CLCx Gate 2

0= CLCIN0 (true) is not gated into CLCx Gate 2

LCxG3D1N: Gate 2 Data 1 Negated (inverted) bit

1= CLCIN0 (inverted) is gated into CLCx Gate 2

0= CLCIN0 (inverted) is not gated into CLCx Gate 2

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REGISTER 31-10: CLCxGLS3: GATE 3 LOGIC SELECT REGISTER

R/W-x/u

LCxG4D4T

LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T

LCxG4D2N

LCxG4D1T LCxG4D1N

bit 0

bit 7

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LCxG4D4T: Gate 3 Data 4 True (non-inverted) bit

1= CLCIN3 (true) is gated into CLCx Gate 3

0= CLCIN3 (true) is not gated into CLCx Gate 3

LCxG4D4N: Gate 3 Data 4 Negated (inverted) bit

1= CLCIN3 (inverted) is gated into CLCx Gate 3

0= CLCIN3 (inverted) is not gated into CLCx Gate 3

LCxG4D3T: Gate 3 Data 3 True (non-inverted) bit

1= CLCIN2 (true) is gated into CLCx Gate 3

0= CLCIN2 (true) is not gated into CLCx Gate 3

LCxG4D3N: Gate 3 Data 3 Negated (inverted) bit

1= CLCIN2 (inverted) is gated into CLCx Gate 3

0= CLCIN2 (inverted) is not gated into CLCx Gate 3

LCxG4D2T: Gate 3 Data 2 True (non-inverted) bit

1= CLCIN1 (true) is gated into CLCx Gate 3

0= CLCIN1 (true) is not gated into CLCx Gate 3

LCxG4D2N: Gate 3 Data 2 Negated (inverted) bit

1= CLCIN1 (inverted) is gated into CLCx Gate 3

0= CLCIN1 (inverted) is not gated into CLCx Gate 3

LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit

1= CLCIN0 (true) is gated into CLCx Gate 3

0= CLCIN0 (true) is not gated into CLCx Gate 3

LCxG4D1N: Gate 3 Data 1 Negated (inverted) bit

1= CLCIN0 (inverted) is gated into CLCx Gate 3

0= CLCIN0 (inverted) is not gated into CLCx Gate 3

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REGISTER 31-11: CLCDATA: CLC DATA OUTPUT

U-0

—

U-0

—

U-0

—

U-0

—

R-0

MLC4OUT

MLC3OUT

MLC2OUT

MLC1OUT

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3

bit 2

bit 1

bit 0

Unimplemented: Read as ‘0’

MLC4OUT: Mirror copy of LC4OUT bit

MLC3OUT: Mirror copy of LC3OUT bit

MLC2OUT: Mirror copy of LC2OUT bit

MLC1OUT: Mirror copy of LC1OUT bit

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TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE

PEIE

CLC3IF

CLC4IE

―

—

―

—

―

INTEDG

TMR1GIF

TMR1GIE

121

135

127

362

363

364

365

366

367

368

362

363

364

365

366

367

368

362

363

364

365

366

367

368

362

363

364

365

PIR5

CLC4IF

CLC2IF

CLC2IE

LC1OUT

―

CLC1IF

CLC1IE

LC1INTP

―

—

PIE5

CLC4IE

—

CLC1CON

CLC1POL

CLC1SEL0

CLC1SEL1

CLC1SEL2

CLC1SEL3

CLC1GLS0

CLC1GLS1

CLC1GLS2

CLC1GLS3

CLC2CON

CLC2POL

CLC2SEL0

CLC2SEL1

CLC2SEL2

CLC2SEL3

CLC2GLS0

CLC2GLS1

CLC2GLS2

CLC2GLS3

CLC3CON

CLC3POL

CLC3SEL0

CLC3SEL1

CLC3SEL2

CLC3SEL3

CLC3GLS0

CLC3GLS1

CLC3GLS2

CLC3GLS3

CLC4CON

CLC4POL

CLC4SEL0

CLC4SEL1

CLC4SEL2

CLC4SEL3

LC1EN

LC1INTN

LC1MODE<2:0>

LC1G2POL

LC1POL

―

LC1G4POL LC1G3POL

LC1G1POL

―

LC1D1S<5:0>

LC1D2S<5:0>

―

LC1D3S<5:0>

LC1D4S<5:0>

―

LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N

LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N

LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N

LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N

LC1G1D1T

LC1G2D1T

LC1G1D1N

LC1G2D1N

LC1G3D1N

LC1G4D1N

―

LC1G3D1T

―

LC1G4D1T

LC2EN

―

LC2OUT

LC2INTP

LC2INTN

LC2MODE<2:0>

LC2G2POL

LC2POL

―

LC2G4POL LC2G3POL

LC2D1S<5:0>

LC2D2S<5:0>

LC2D3S<5:0>

LC2D4S<5:0>

LC2G1POL

―

LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N

LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N

LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N

LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N

LC2G1D1T

LC2G2D1T

LC2G1D1N

LC2G2D1N

LC2G3D1N

LC2G4D1N

―

LC2G3D1T

―

LC2G4D1T

LC3EN

―

LC3OUT

LC3INTP

LC3INTN

LC3MODE<2:0>

LC3G2POL

LC3POL

―

LC3G4POL LC3G3POL

LC3D1S<5:0>

LC3D2S<5:0>

LC3D3S<5:0>

LC3D4S<5:0>

LC3G1POL

―

LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N

LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N

LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N

LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N

LC3G1D1T

LC3G2D1T

LC3G1D1N

LC3G2D1N

LC3G3D1N

LC3G4D1N

―

LC3G3D1T

―

LC3G4D1T

LC4EN

LC4POL

―

LC4OUT

LC4INTP

LC4INTN

LC4MODE<2:0>

LC4G2POL LC4G1POL

―

LC4G4POL LC4G3POL

LC4D1S<5:0>

LC4D2S<5:0>

LC4D3S<5:0>

LC4D4S<5:0>

―

CLC4GLS0

―

LC4G1D3T LC4G1D3N LC4G1D2T LC4G1D2N

LC4G1D1T

LC4G1D1N

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

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TABLE 31-4: SUMMARY OF REGISTERS ASSOCIATED WITH CLCx (continued)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CLC4GLS1

CLC4GLS2

CLC4GLS3

CLCIN0PPS

CLCIN1PPS

CLCIN2PPS

―

LC4G2D3T LC4G2D3N LC4G2D2T LC4G2D2N

LC4G3D3T LC4G3D3N LC4G3D2T LC4G3D2N

LC4G4D3T LC4G4D3N LC4G4D2T LC4G4D2N

CLCIN0PPS<5:0>

LC4G2D1T

LC4G3D1T

LC4G4D1T

LC4G2D1N

LC4G3D1N

LC4G4D1N

366

367

368

199

CLCIN1PPS<5:0>

CLCIN2PPS<5:0>

CLCIN3PPS

CLCIN3PPS<5:0>

Legend:

— = unimplemented, read as ‘0’. Shaded cells are unused by the CLCx modules.

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32.0 MASTER SYNCHRONOUS

SERIAL PORT (MSSPx)

MODULES

32.1 MSSP Module Overview

The Master Synchronous Serial Port (MSSP) module is

a serial interface useful for communicating with other

peripheral or microcontroller devices. These peripheral

devices may be serial EEPROMs, shift registers,

display drivers, A/D converters, etc. The MSSP module

can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I²C)

The SPI interface supports the following modes and

features:

• Master mode

• Slave mode

• Clock Parity

• Slave Select Synchronization (Slave mode only)

• Daisy-chain connection of slave devices

Figure 32-1 is a block diagram of the SPI interface

module.

FIGURE 32-1:

MSSP BLOCK DIAGRAM (SPI MODE)

Data Bus

Write

Read

SSPxBUF Reg

SSPSR Reg

SSPDATPPS

PPS

SDI

Shift

Clock

bit 0

SDO

PPS

RxyPPS

SS

Control

Enable

SS

2 (CKP, CKE)

Clock Select

PPS

Edge

Select

SSPSSPPS

(2)

SSPCLKPPS

SSPM<3:0>

4

T2_match

SCK

(

)

PPS

2

TOSC

Prescaler

4, 16, 64

Edge

Select

PPS

(1)

Baud Rate

Generator

(SSPxADD)

RxyPPS

TRIS bit

Note 1: Output selection for master mode

2: Input selection for slave mode

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The I²C interface supports the following modes and

features:

Note 1: In devices with more than one MSSP

module, it is very important to pay close

attention to SSPxCONx register names.

SSPxCON1 and SSPxCON2 registers

control different operational aspects of

the same module, while SSP1CON1 and

SSP2CON1 control the same features for

two different modules.

• Master mode

• Slave mode

• Byte NACKing (Slave mode)

• Limited multi-master support

• 7-bit and 10-bit addressing

• Start and Stop interrupts

• Interrupt masking

2: Throughout this section, generic refer-

ences to an MSSPx module in any of its

operating modes may be interpreted as

being equally applicable to MSSP1 or

MSSP2. Register names, module I/O sig-

nals, and bit names may use the generic

designator ‘x’ to indicate the use of a

numeral to distinguish a particular mod-

ule when required.

• Clock stretching

• Bus collision detection

• General call address matching

• Address masking

• Selectable SDA hold times

Figure 32-2 is a block diagram of the I²C interface

module in Master mode. Figure 32-3 is a diagram of the

I²C interface module in Slave mode.

FIGURE 32-2:

MSSP BLOCK DIAGRAM (I²C MASTER MODE)

Internal

data bus

[SSPM<3:0>]

(1)

SSPDATPPS

Read

Write

SDA

SDA in

PPS

SSPxBUF

SSPSR

Baud Rate

Generator

(SSPxADD)

Shift

Clock

(1)

RxyPPS

PPS

MSb

LSb

Start bit, Stop bit,

Acknowledge

Generate (SSPxCON2)

(2)

SSPCLKPPS

SCL

PPS

Start bit detect,

Stop bit detect

(2)

RxyPPS

Write collision detect

Clock arbitration

State counter for

Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV

Reset SEN, PEN (SSPxCON2)

Set SSPxIF, BCL1IF

SCL in

end of XMIT/RCV

Bus Collision

Address Match detect

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

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FIGURE 32-3:

MSSP BLOCK DIAGRAM (I²C SLAVE MODE)

Internal

Data Bus

Read

Write

(2)

SSPCLKPPS

SSPxBUF Reg

SSPSR Reg

SCL

PPS

Shift

Clock

Stretching

MSb

LSb

(2)

RxyPPS

SSPxMSK Reg

Match Detect

SSPxADD Reg

(1)

SSPDATPPS

SDA

Addr Match

PPS

Set, Reset

S, P bits

(SSPxSTAT Reg)

Start and

Stop bit Detect

(1)

RxyPPS

Note 1: SDA pin selections must be the same for input and output

2: SCL pin selections must be the same for input and output

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During each SPI clock cycle, a full-duplex data

transmission occurs. This means that while the master

device is sending out the MSb from its shift register (on

its SDO pin) and the slave device is reading this bit and

saving it as the LSb of its shift register, that the slave

device is also sending out the MSb from its shift register

(on its SDO pin) and the master device is reading this

bit and saving it as the LSb of its shift register.

32.2 SPI Mode Overview

The Serial Peripheral Interface (SPI) bus is a

synchronous serial data communication bus that

operates in Full-Duplex mode. Devices communicate

in a master/slave environment where the master device

initiates the communication.

A slave device is

controlled through a Chip Select known as Slave

Select.

After eight bits have been shifted out, the master and

slave have exchanged register values.

The SPI bus specifies four signal connections:

• Serial Clock (SCK)

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Slave Select (SS)

If there is more data to exchange, the shift registers are

loaded with new data and the process repeats itself.

Whether the data is meaningful or not (dummy data),

depends on the application software. This leads to

three scenarios for data transmission:

Figure 32-1 shows the block diagram of the MSSP

module when operating in SPI mode.

• Master sends useful data and slave sends dummy

data.

The SPI bus operates with a single master device and

one or more slave devices. When multiple slave

devices are used, an independent Slave Select

connection can be used to address each slave individ-

ually.

• Master sends useful data and slave sends useful

data.

• Master sends dummy data and slave sends useful

data.

Figure 32-4 shows a typical connection between a

master device and multiple slave devices.

Transmissions must be performed in multiples of eight

clock pulses. When there is no more data to be trans-

mitted, the master stops sending the clock signal and it

deselects the slave.

The master selects only one slave at a time. Most slave

devices have tri-state outputs so their output signal

appears disconnected from the bus when they are not

selected.

Every slave device connected to the bus that has not

been selected through its slave select line must disre-

gard the clock and transmission signals and must not

transmit out any data of its own.

Transmissions involve two shift registers, eight bits in

size, one in the master and one in the slave. Data is

always shifted out one bit at a time, with the Most

Significant bit (MSb) shifted out first. At the same time,

a new Least Significant bit (LSb) is shifted into the

same register.

Figure 32-5 shows a typical connection between two

processors configured as master and slave devices.

Data is shifted out of both shift registers on the

programmed clock edge and latched on the opposite

edge of the clock.

The master device transmits information out on its SDO

output pin which is connected to, and received by, the

slave’s SDI input pin. The slave device transmits infor-

mation out on its SDO output pin, which is connected

to, and received by, the master’s SDI input pin.

To begin communication, the master device first sends

out the clock signal. Both the master and the slave

devices should be configured for the same clock polar-

ity.

The master device starts a transmission by sending out

the MSb from its shift register. The slave device reads

this bit from that same line and saves it into the LSb

position of its shift register.

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FIGURE 32-4:

SPI MASTER AND MULTIPLE SLAVE CONNECTION

SCK

SDO

SCK

SDI

SDO

SS

SPI Master

SPI Slave

#1

SDI

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

32.2.1

SPI MODE REGISTERS

The MSSP module has five registers for SPI mode

operation. These are:

• MSSP STATUS register (SSPxSTAT)

• MSSP Control register 1 (SSPxCON1)

• MSSP Control register 3 (SSPxCON3)

• MSSP Data Buffer register (SSPxBUF)

• MSSP Address register (SSPxADD)

• MSSP Shift register (SSPxSR)

(Not directly accessible)

SSPxCON1 and SSPxSTAT are the control and status

registers in SPI mode operation. The SSPxCON1

register is readable and writable. The lower six bits of

the SSPxSTAT are read-only. The upper two bits of the

SSPxSTAT are read/write.

In one SPI master mode, SSPxADD can be loaded

with a value used in the Baud Rate Generator. More

information on the Baud Rate Generator is available in

Section 32.7 “Baud Rate Generator”.

SSPxSR is the shift register used for shifting data in

and out. SSPxBUF provides indirect access to the

SSPxSR register. SSPxBUF is the buffer register to

which data bytes are written, and from which data

bytes are read.

In receive operations, SSPxSR and SSPxBUF

together create a buffered receiver. When SSPxSR

receives a complete byte, it is transferred to SSPxBUF

and the SSPxIF interrupt is set.

During transmission, the SSPxBUF is not buffered. A

write to SSPxBUF will write to both SSPxBUF and

SSPxSR.

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32.2.2 SPI MODE OPERATION

The MSSP consists of a transmit/receive shift register

(SSPxSR) and a buffer register (SSPxBUF). The

SSPxSR shifts the data in and out of the device, MSb first.

The SSPxBUF holds the data that was written to the

SSPxSR until the received data is ready. Once the eight

bits of data have been received, that byte is moved to the

SSPxBUF register. Then, the Buffer Full Detect bit, BF of

the SSPxSTAT register, and the interrupt flag bit, SSPxIF,

are set. Any write to the SSPxBUF register during

transmission/reception of data will be ignored and the

write collision detect bit WCOL of the SSPxCON1

register, will be set. User software must clear the WCOL

bit to allow the following write(s) to the SSPxBUF register

to complete successfully.

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPxCON1<3:0> and SSPxSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

When the application software is expecting to receive

valid data, the SSPxBUF should be read before the next

byte of data to transfer is written to the SSPxBUF. The

Buffer Full bit, BF of the SSPxSTAT register, indicates

when SSPxBUF has been loaded with the received data

(transmission is complete). When the SSPxBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. If the interrupt method is not going to be

used, then software polling can be done to ensure that a

write collision does not occur.

• Slave Select mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN of the

SSPxCON1 register, must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSPxCONx registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial port

pins. For the pins to behave as the serial port function,

some must have their data direction bits (in the TRISx

register) appropriately programmed as follows:

• SDI must have corresponding TRIS bit set

• SDO must have corresponding TRIS bit cleared

The SSPxSR is not directly readable or writable and

can only be accessed by addressing the SSPxBUF

register.

• SCK (Master mode) must have corresponding

TRIS bit cleared

• SCK (Slave mode) must have corresponding

TRIS bit set

• SS must have corresponding TRIS bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 32-5:

SPI MASTER/SLAVE CONNECTION

SPI Master SSPM<3:0> = 00xx

= 1010

SPI Slave SSPM<3:0> = 010x

SDO

SDI

Serial Input Buffer

(SSPxBUF)

SDI

SDO

Shift Register

(SSPxSR)

Shift Register

(SSPxSR)

LSb

MSb

LSb

Serial Clock

SCK

SS

Slave Select

(optional)

General I/O

Processor 2

Processor 1

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The clock polarity is selected by appropriately

programming the CKP bit of the SSPxCON1 register

and the CKE bit of the SSPxSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 32-6, Figure 32-8, Figure 32-9 and

Figure 32-10, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

32.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK line. The master

determines when the slave (Processor 2, Figure 32-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDO output could be

disabled (programmed as an input). The SSPxSR

register will continue to shift in the signal present on the

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPxBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

• FOSC/4 (or TCY)

• FOSC/16 (or 4 * TCY)

• FOSC/64 (or 16 * TCY)

• Timer2 output/2

• FOSC/(4 * (SSPxADD + 1))

Figure 32-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

data is shown.

FIGURE 32-6:

SPI MODE WAVEFORM (MASTER MODE)

Write to

SSPxBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

(CKE = 0)

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPxIF

SSPxSR to

SSPxBUF

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32.2.4

SPI SLAVE MODE

32.2.5

SLAVE SELECT

SYNCHRONIZATION

In Slave mode, the data is transmitted and received as

external clock pulses appear on SCK. When the last

bit is latched, the SSPxIF interrupt flag bit is set.

The Slave Select can also be used to synchronize

communication. The Slave Select line is held high until

the master device is ready to communicate. When the

Slave Select line is pulled low, the slave knows that a

new transmission is starting.

Before enabling the module in SPI Slave mode, the clock

line must match the proper Idle state. The clock line can

be observed by reading the SCK pin. The Idle state is

determined by the CKP bit of the SSPxCON1 register.

If the slave fails to receive the communication properly,

it will be reset at the end of the transmission, when the

Slave Select line returns to a high state. The slave is

then ready to receive a new transmission when the

Slave Select line is pulled low again. If the Slave Select

line is not used, there is a risk that the slave will

eventually become out of sync with the master. If the

slave misses a bit, it will always be one bit off in future

transmissions. Use of the Slave Select line allows the

slave and master to align themselves at the beginning

of each transmission.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

While in Sleep mode, the slave can transmit/receive

data. The shift register is clocked from the SCK pin

input and when a byte is received, the device will

generate an interrupt. If enabled, the device will wake-

up from Sleep.

32.2.4.1 Daisy-Chain Configuration

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPxCON1<3:0> = 0100).

The SPI bus can sometimes be connected in a daisy-

chain configuration. The first slave output is connected

to the second slave input, the second slave output is

connected to the third slave input, and so on. The final

slave output is connected to the master input. Each

slave sends out, during a second group of clock

pulses, an exact copy of what was received during the

first group of clock pulses. The whole chain acts as

one large communication shift register. The daisy-

chain feature only requires a single Slave Select line

from the master device.

When the SS pin is low, transmission and reception are

enabled and the SDO pin is driven.

When the SS pin goes high, the SDO pin is no longer

driven, even if in the middle of a transmitted byte and

becomes a floating output. External pull-up/pull-down

resistors may be desirable depending on the applica-

tion.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPxCON1<3:0>

=

Figure 32-7 shows the block diagram of a typical

daisy-chain connection when operating in SPI mode.

0100), the SPI module will reset if the SS

pin is set to VDD.

In a daisy-chain configuration, only the most recent

byte on the bus is required by the slave. Setting the

BOEN bit of the SSPxCON3 register will enable writes

to the SSPxBUF register, even if the previous byte has

not been read. This allows the software to ignore data

that may not apply to it.

2: When the SPI is used in Slave mode with

CKE set; the user must enable SS pin

control.

3: While operated in SPI Slave mode the

SMP bit of the SSPxSTAT register must

remain clear.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

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FIGURE 32-7:

SPI DAISY-CHAIN CONNECTION

SCK

SPI Master

SDO

SDI

SDO

SS

SPI Slave

#1

General I/O

SCK

SDI

SDO

SS

SPI Slave

#2

SCK

SDI

SDO

SS

SPI Slave

#3

FIGURE 32-8:

SLAVE SELECT SYNCHRONOUS WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Shift register SSPxSR

and bit count are reset

SSPxBUF to

SSPxSR

bit 6

bit 7

bit 0

SDO

SDI

bit 7

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

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FIGURE 32-9:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPxBUF

Valid

bit 6

bit 2

bit 5

bit 4

bit 3

bit 1

bit 0

SDO

bit 7

SDI

bit 0

bit 7

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

FIGURE 32-10:

SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPxBUF

Valid

bit 6

bit 3

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

SDI

bit 0

Input

Sample

SSPxIF

Interrupt

Flag

SSPxSR to

SSPxBUF

Write Collision

detection active

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32.2.6 SPI OPERATION IN SLEEP MODE

If the requested slave exists on the bus, it will respond

with an Acknowledge bit, otherwise known as an ACK.

The master then continues to either transmit or receive

data from the slave device.

In SPI Master mode, module clocks may be operating

at a different speed than when in Full-Power mode; in

the case of the Sleep mode, all clocks are halted.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmission/

reception will remain in that state until the device

wakes. After the device returns to Run mode, the

module will resume transmitting and receiving data.

FIGURE 32-11:

I²C MASTER/

SLAVE CONNECTION

VDD

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all eight bits have been received, the

MSSP interrupt flag bit will be set and if enabled, will

wake the device.

SCL

VDD

Master

Slave

SDA

32.3 I²C MODE OVERVIEW

The Inter-Integrated Circuit (I²C) bus is a multi-master

serial data communication bus. Devices communicate

in a master/slave environment where the master

devices initiate the communication. A slave device is

controlled through addressing.

The line is held high to indicate Start and Stop bits.

On the last byte of data communicated, the master

device may end the transmission by sending a Stop bit.

If the master device is in Receive mode, it sends the

Stop bit in place of the last ACK bit. A Stop bit is

indicated by a low-to-high transition of the SDA line

while the SCL line is held high.

The I²C bus specifies two signal connections:

• Serial Clock (SCL)

• Serial Data (SDA)

In some cases, the master may want to maintain

control of the bus and re-initiate another transmission.

If so, the master device may send a Restart condition

in place of the Stop condition or last ACK bit when it is

in Receive mode.

Figure 32-11 shows the block diagram of the MSSP

module when operating in I²C mode.

Both the SCL and SDA connections are bidirectional

open-drain lines, each requiring pull-up resistors for the

supply voltage. Pulling the line to ground is considered

a logical zero and letting the line float is considered a

logical one.

The I²C bus specifies three message protocols:

• Single message where a master writes data to a

slave.

• Single message where a master reads data from

a slave.

• Combined message where a master initiates a

minimum of two writes, or two reads, or a combi-

nation of writes and reads, to one or more slaves.

Figure 32-11 shows a typical connection between two

processors configured as master and slave devices.

The I²C bus can operate with one or more master

devices and one or more slave devices.

There are four potential modes of operation for a given

device:

• Master Transmit mode

(master is transmitting data to a slave)

• Master Receive mode

(master is receiving data from a slave)

• Slave Transmit mode

(slave is transmitting data to a master)

• Slave Receive mode

(slave is receiving data from the master)

To begin communication, the master device sends out

a Start condition followed by the address byte of the

slave it intends to communicate with.

This is followed by a single Read/Write bit, which deter-

mines whether the master intends to transmit to or

receive data from the slave device.

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32.4 I²C MODE OPERATION

32.3.1

CLOCK STRETCHING

When a slave device has not completed processing

data, it can delay the transfer of more data through the

process of clock stretching. An addressed slave device

may hold the SCL clock line low after receiving or send-

ing a bit, indicating that it is not yet ready to continue.

The master that is communicating with the slave will

attempt to raise the SCL line in order to transfer the

next bit, but will detect that the clock line has not yet

been released. Because the SCL connection is open-

drain, the slave has the ability to hold that line low until

it is ready to continue communicating.

All MSSP I²C communication is byte oriented and

shifted out MSb first. Six SFR registers and two

interrupt flags interface the module with the PIC^®

microcontroller and user software. Two pins, SDA and

SCL, are exercised by the module to communicate

with other external I²C devices.

32.4.1 BYTE FORMAT

All communication in I²C is done in 9-bit segments. A

byte is sent from a master to a slave or vice-versa, fol-

lowed by an Acknowledge bit sent back. After the

eighth falling edge of the SCL line, the device output-

ting data on the SDA changes that pin to an input and

reads in an acknowledge value on the next clock

pulse.

Clock stretching allows receivers that cannot keep up

with a transmitter to control the flow of incoming data.

32.3.2

ARBITRATION

Each master device must monitor the bus for Start and

Stop bits. If the device detects that the bus is busy, it

cannot begin a new message until the bus returns to an

Idle state.

The clock signal, SCL, is provided by the master. Data

is valid to change while the SCL signal is low, and

sampled on the rising edge of the clock. Changes on

the SDA line while the SCL line is high define special

conditions on the bus, explained below.

However, two master devices may try to initiate a trans-

mission on or about the same time. When this occurs,

the process of arbitration begins. Each transmitter

checks the level of the SDA data line and compares it

to the level that it expects to find. The first transmitter to

observe that the two levels do not match, loses arbitra-

tion, and must stop transmitting on the SDA line.

32.4.2 DEFINITION OF I²C TERMINOLOGY

There is language and terminology in the description

of I²C communication that have definitions specific to

I²C. That word usage is defined below and may be

used in the rest of this document without explanation.

This table was adapted from the Philips I²C

specification.

For example, if one transmitter holds the SDA line to a

logical one (lets it float) and a second transmitter holds

it to a logical zero (pulls it low), the result is that the

SDA line will be low. The first transmitter then observes

that the level of the line is different than expected and

concludes that another transmitter is communicating.

32.4.3 SDA AND SCL PINS

Selection of any I²C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open-drain. These

pins should be set by the user to inputs by setting the

appropriate TRIS bits.

The first transmitter to notice this difference is the one

that loses arbitration and must stop driving the SDA

line. If this transmitter is also a master device, it also

must stop driving the SCL line. It then can monitor the

lines for a Stop condition before trying to reissue its

transmission. In the meantime, the other device that

has not noticed any difference between the expected

and actual levels on the SDA line continues with its

original transmission.

Note 1: Any device pin can be selected for SDA

and SCL functions with the PPS periph-

eral. These functions are bidirectional.

The SDA input is selected with the

SSPDATPPS registers. The SCL input is

selected with the SSPCLKPPS registers.

Outputs are selected with the RxyPPS

registers. It is the user’s responsibility to

make the selections so that both the input

and the output for each function is on the

same pin.

Slave Transmit mode can also be arbitrated, when a

master addresses multiple slaves, but this is less

common.

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32.4.4 SDA HOLD TIME

32.4.5 START CONDITION

The hold time of the SDA pin is selected by the SDAHT

bit of the SSPxCON3 register. Hold time is the time

SDA is held valid after the falling edge of SCL. Setting

the SDAHT bit selects a longer 300 ns minimum hold

time and may help on buses with large capacitance.

The I²C specification defines a Start condition as a

transition of SDA from a high to a low state while SCL

line is high. A Start condition is always generated by

the master and signifies the transition of the bus from

an Idle to an active state. Figure 32-12 shows wave

forms for Start and Stop conditions.

TABLE 32-1: I²C BUS TERMS

32.4.6 STOP CONDITION

TERM

Description

A Stop condition is a transition of the SDA line from

low-to-high state while the SCL line is high.

Transmitter

The device which shifts data out

onto the bus.

Note: At least one SCL low time must appear

before a Stop is valid, therefore, if the SDA

line goes low then high again while the SCL

line stays high, only the Start condition is

detected.

Receiver

Master

The device which shifts data in

from the bus.

The device that initiates a transfer,

generates clock signals and termi-

nates a transfer.

Slave

The device addressed by the

master.

32.4.7 RESTART CONDITION

A Restart is valid any time that a Stop would be valid.

A master can issue a Restart if it wishes to hold the

bus after terminating the current transfer. A Restart

has the same effect on the slave that a Start would,

resetting all slave logic and preparing it to clock in an

address. The master may want to address the same or

another slave. Figure 32-13 shows the wave form for a

Restart condition.

Multi-master

Arbitration

A bus with more than one device

that can initiate data transfers.

Procedure to ensure that only one

master at a time controls the bus.

Winning arbitration ensures that

the message is not corrupted.

Synchronization Procedure to synchronize the

clocks of two or more devices on

the bus.

In 10-bit Addressing Slave mode a Restart is required

for the master to clock data out of the addressed

slave. Once a slave has been fully addressed, match-

ing both high and low address bytes, the master can

issue a Restart and the high address byte with the R/

W bit set. The slave logic will then hold the clock and

prepare to clock out data.

Idle

No master is controlling the bus,

and both SDA and SCL lines are

high.

Active

Any time one or more master

devices are controlling the bus.

Addressed

Slave

Slave device that has received a

matching address and is actively

being clocked by a master.

32.4.8 START/STOP CONDITION INTERRUPT

MASKING

Matching

Address

Address byte that is clocked into a

slave that matches the value

stored in SSPxADD.

The SCIE and PCIE bits of the SSPxCON3 register

can enable the generation of an interrupt in Slave

modes that do not typically support this function. Slave

modes where interrupt on Start and Stop detect are

already enabled, these bits will have no effect.

Write Request

Read Request

Slave receives a matching

address with R/W bit clear, and is

ready to clock in data.

Master sends an address byte with

the R/W bit set, indicating that it

wishes to clock data out of the

Slave. This data is the next and all

following bytes until a Restart or

Stop.

Clock Stretching When a device on the bus hold

SCL low to stall communication.

Bus Collision

Any time the SDA line is sampled

low by the module while it is out-

putting and expected high state.

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FIGURE 32-12:

I²C START AND STOP CONDITIONS

SDA

SCL

S

P

Change of

Data Allowed

Stop

Start

Condition

FIGURE 32-13:

I²C RESTART CONDITION

Sr

Change of

Data Allowed

Restart

Condition

32.4.9 ACKNOWLEDGE SEQUENCE

Slave software, when the AHEN and DHEN bits are

set, allow the user to set the ACK value sent back to

the transmitter. The ACKDT bit of the SSPxCON2

register is set/cleared to determine the response.

The 9th SCL pulse for any transferred byte in I²C is

dedicated as an Acknowledge. It allows receiving

devices to respond back to the transmitter by pulling

the SDA line low. The transmitter must release control

of the line during this time to shift in the response. The

Acknowledge (ACK) is an active-low signal, pulling the

SDA line low indicates to the transmitter that the

device has received the transmitted data and is ready

to receive more.

There are certain conditions where an ACK will not be

sent by the slave. If the BF bit of the SSPxSTAT

register or the SSPOV bit of the SSPxCON1 register

are set when a byte is received.

When the module is addressed, after the eighth falling

edge of SCL on the bus, the ACKTIM bit of the

SSPxCON3 register is set. The ACKTIM bit indicates

the acknowledge time of the active bus. The ACKTIM

Status bit is only active when the AHEN bit or DHEN

bit is enabled.

The result of an ACK is placed in the ACKSTAT bit of

the SSPxCON2 register.

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32.5 I²C SLAVE MODE OPERATION

32.5.2 SLAVE RECEPTION

When the R/W bit of a matching received address byte

is clear, the R/W bit of the SSPxSTAT register is

cleared. The received address is loaded into the

SSPxBUF register and acknowledged.

The MSSP Slave mode operates in one of four modes

selected by the SSPM bits of SSPxCON1 register. The

modes can be divided into 7-bit and 10-bit Addressing

mode. 10-bit Addressing modes operate the same as

7-bit with some additional overhead for handling the

larger addresses.

When the overflow condition exists for a received

address, then not Acknowledge is given. An overflow

condition is defined as either bit BF of the SSPxSTAT

register is set, or bit SSPOV of the SSPxCON1 register

is set. The BOEN bit of the SSPxCON3 register

modifies this operation. For more information see

Register 32-4.

Modes with Start and Stop bit interrupts operate the

same as the other modes with SSPxIF additionally

getting set upon detection of a Start, Restart, or Stop

condition.

32.5.1 SLAVE MODE ADDRESSES

An MSSP interrupt is generated for each transferred

data byte. Flag bit, SSPxIF, must be cleared by

software.

The SSPxADD register (Register 32-6) contains the

Slave mode address. The first byte received after a

Start or Restart condition is compared against the

value stored in this register. If the byte matches, the

value is loaded into the SSPxBUF register and an

interrupt is generated. If the value does not match, the

module goes idle and no indication is given to the

software that anything happened.

When the SEN bit of the SSPxCON2 register is set,

SCL will be held low (clock stretch) following each

received byte. The clock must be released by setting

the CKP bit of the SSPxCON1 register.

32.5.2.1 7-bit Addressing Reception

The SSP Mask register (Register 32-5) affects the

address matching process. See Section 32.5.9 “SSP

Mask Register” for more information.

This section describes a standard sequence of events

for the MSSP module configured as an I²C slave in 7-

bit Addressing mode. Figure 32-14 and Figure 32-15

is used as a visual reference for this description.

32.5.1.1 I²C Slave 7-bit Addressing Mode

This is a step by step process of what typically must

be done to accomplish I²C communication.

In 7-bit Addressing mode, the LSb of the received data

byte is ignored when determining if there is an address

match.

1. Start bit detected.

2. S bit of SSPxSTAT is set; SSPxIF is set if

interrupt on Start detect is enabled.

32.5.1.2 I²C Slave 10-bit Addressing Mode

3. Matching address with R/W bit clear is received.

In 10-bit Addressing mode, the first received byte is

compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9

and A8 are the two MSb’s of the 10-bit address and

stored in bits 2 and 1 of the SSPxADD register.

4. The slave pulls SDA low sending an ACK to the

master, and sets SSPxIF bit.

5. Software clears the SSPxIF bit.

6. Software reads received address from

SSPxBUF clearing the BF flag.

After the acknowledge of the high byte the UA bit is set

and SCL is held low until the user updates SSPxADD

with the low address. The low address byte is clocked

in and all eight bits are compared to the low address

value in SSPxADD. Even if there is not an address

match; SSPxIF and UA are set, and SCL is held low

until SSPxADD is updated to receive a high byte

again. When SSPxADD is updated the UA bit is

cleared. This ensures the module is ready to receive

the high address byte on the next communication.

7. If SEN = 1; Slave software sets CKP bit to

release the SCL line.

8. The master clocks out a data byte.

9. Slave drives SDA low sending an ACK to the

master, and sets SSPxIF bit.

10. Software clears SSPxIF.

11. Software reads the received byte from

SSPxBUF clearing BF.

A high and low address match as a write request is

required at the start of all 10-bit addressing communi-

cation. A transmission can be initiated by issuing a

Restart once the slave is addressed, and clocking in

the high address with the R/W bit set. The slave

hardware will then acknowledge the read request and

prepare to clock out data. This is only valid for a slave

after it has received a complete high and low address

byte match.

12. Steps 8-12 are repeated for all received bytes

from the master.

13. Master sends Stop condition, setting P bit of

SSPxSTAT, and the bus goes idle.

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32.5.2.2 7-bit Reception with AHEN and DHEN

Slave device reception with AHEN and DHEN set

operate the same as without these options with extra

interrupts and clock stretching added after the eighth

falling edge of SCL. These additional interrupts allows

time for the slave software to decide whether it wants

to ACK the receive address or data byte.

This list describes the steps that need to be taken by

slave software to use these options for I²C

communication. Figure 32-16 displays a module using

both address and data holding. Figure 32-17 includes

the operation with the SEN bit of the SSPxCON2

register set.

1. S bit of SSPxSTAT is set; SSPxIF is set if

interrupt on Start detect is enabled.

2. Matching address with R/W bit clear is clocked

in. SSPxIF is set, and CKP is cleared in hard-

ware after the eighth falling edge of SCL.

3. Slave clears the SSPxIF.

4. Slave can look at the ACKTIM bit of the

SSPxCON3 register to determine if the SSPxIF

was after or before the ACK.

5. Slave reads the address value from SSPxBUF,

clearing the BF flag.

6. Slave sets ACK value clocked out to the master

by setting ACKDT.

7. Slave releases the clock by setting CKP in soft-

ware.

8. SSPxIF is set after an ACK, not after a NACK.

9. If SEN = 1 the slave hardware will stretch the

clock after the ACK.

10. Slave clears SSPxIF.

Note: SSPxIF is still set after the ninth falling edge

of SCL even if there is no clock stretching

and BF has been cleared. Only if NACK is

sent to master is SSPxIF not set

11. SSPxIF set, and CKP is cleared in hardware

after eighth falling edge of SCL for a received

data byte.

12. Slave looks at ACKTIM bit of SSPxCON3 to

determine the source of the interrupt.

13. Slave reads the received data from SSPxBUF

clearing BF.

14. Steps 7-14 are the same for each received data

byte.

15. Communication is ended by either the slave

sending an ACK = 1, or the master sending a

Stop condition. If a Stop is sent and Interrupt on

Stop Detect is disabled, the slave will only know

by polling the P bit of the SSPxSTAT register.

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32.5.3

SLAVE TRANSMISSION

32.5.3.2

7-bit Transmission

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPxSTAT register is set. The received address is

loaded into the SSPxBUF register, and an ACK pulse is

sent by the slave on the ninth bit.

A master device can transmit a read request to a

slave, and then clock data out of the slave. The list

below outlines what software for a slave will need to

do to accomplish a standard transmission. Figure 32-

18 can be used as a reference to this list.

Following the ACK, slave hardware clears the CKP bit

and the SCL pin is held low (see Section 32.5.6

“Clock Stretching” for more detail). By stretching the

clock, the master will be unable to assert another clock

pulse until the slave is done preparing the transmit

data.

1. Master sends a Start condition on SDA and

SCL.

2. S bit of SSPxSTAT is set; SSPxIF is set if

interrupt on Start detect is enabled.

3. Matching address with R/W bit set is received by

the Slave setting SSPxIF bit.

The transmit data must be loaded into the SSPxBUF

register which also loads the SSPxSR register. Then

the SCL pin should be released by setting the CKP bit

of the SSPxCON1 register. The eight data bits are

shifted out on the falling edge of the SCL input. This

ensures that the SDA signal is valid during the SCL

high time.

4. Slave hardware generates an ACK and sets

SSPxIF.

5. SSPxIF bit is cleared by software.

6. Software reads the received address from

SSPxBUF, clearing BF.

7. R/W is set so CKP was automatically cleared by

hardware after the ACK.

The ACK pulse from the master-receiver is latched on

the rising edge of the ninth SCL input pulse. This ACK

value is copied to the ACKSTAT bit of the SSPxCON2

register. If ACKSTAT is set (not ACK), then the data

transfer is complete. In this case, when the not ACK is

latched by the slave, the slave goes idle and waits for

another occurrence of the Start bit. If the SDA line was

low (ACK), the next transmit data must be loaded into

the SSPxBUF register. Again, the SCL pin must be

released by setting bit CKP.

8. The slave software loads the transmit data into

SSPxBUF.

9. CKP bit is set in software, releasing SCL, allow-

ing the master to clock the data out of the slave.

10. SSPxIF is set after the ACK response from the

master is loaded into the ACKSTAT bit.

11. SSPxIF bit is cleared.

12. The slave software checks the ACKSTAT bit to

see if the master wants to clock out more data.

An MSSP interrupt is generated for each data transfer

byte. The SSPxIF bit must be cleared by software and

the SSPxSTAT register is used to determine the status

of the byte. The SSPxIF bit is set on the falling edge of

the ninth clock pulse.

Note 1:If the master ACKs the clock will be

stretched.

2: ACKSTAT is the only bit updated on the

rising edge of SCL (9th) rather than the

falling.

32.5.3.1

Slave Mode Bus Collision

13. Steps 9-13 are repeated for each transmitted

byte.

A slave receives a read request and begins shifting

data out on the SDA line. If a bus collision is detected

and the SBCDE bit of the SSPxCON3 register is set,

the BCL1IF bit of the PIR3 register is set. Once a bus

collision is detected, the slave goes idle and waits to be

addressed again. User software can use the BCL1IF bit

to handle a slave bus collision.

14. If the master sends a not ACK; the clock is not

held, but SSPxIF is still set.

15. The master sends a Restart condition or a Stop.

16. The slave is no longer addressed.

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32.5.3.3

7-bit Transmission with Address

Hold Enabled

Setting the AHEN bit of the SSPxCON3 register

enables additional clock stretching and interrupt

generation after the eighth falling edge of a received

matching address. Once a matching address has

been clocked in, CKP is cleared and the SSPxIF

interrupt is set.

Figure 32-19 displays a standard waveform of a 7-bit

address slave transmission with AHEN enabled.

1. Master sends Start condition; the S bit of

SSPxSTAT is set; SSPxIF is set if interrupt on

Start detect is enabled.

2. Master sends matching address with R/W bit

set. After the eighth falling edge of the SCL line

the CKP bit is cleared by hardware and SSPxIF

interrupt is generated.

3. Slave software clears SSPxIF.

4. Slave software reads ACKTIM bit of SSPxCON3

register, and R/W and D/A of the SSPxSTAT

register to determine the source of the interrupt.

5. Slave reads the address value from the

SSPxBUF register clearing the BF bit.

6. Slave software decides from this information if it

wishes to ACK or not ACK and sets the ACKDT

bit of the SSPxCON2 register accordingly.

7. Slave software sets the CKP bit releasing SCL.

8. Master clocks in the ACK value from the slave.

9. Slave hardware automatically clears the CKP bit

and sets SSPxIF after the ACK if the R/W bit is

set.

10. Slave software clears SSPxIF.

11. Slave loads value to transmit to the master into

SSPxBUF setting the BF bit.

Note: SSPxBUF cannot be loaded until after the

ACK.

12. Slave sets the CKP bit releasing the clock.

13. Master clocks out the data from the slave and

sends an ACK value on the ninth SCL pulse.

14. Slave hardware copies the ACK value into the

ACKSTAT bit of the SSPxCON2 register.

15. Steps 10-15 are repeated for each byte transmit-

ted to the master from the slave.

16. If the master sends a not ACK the slave

releases the bus allowing the master to send a

Stop and end the communication.

Note: Master must send a not ACK on the last

byte to ensure that the slave releases the

SCL line to receive a Stop.

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32.5.4 SLAVE MODE 10-BIT ADDRESS

RECEPTION

32.5.5 10-BIT ADDRESSING WITH ADDRESS OR

DATA HOLD

This section describes a standard sequence of events

for the MSSP module configured as an I²C slave in 10-

bit Addressing mode.

Reception using 10-bit addressing with AHEN or

DHEN set is the same as with 7-bit modes. The only

difference is the need to update the SSPxADD register

using the UA bit. All functionality, specifically when the

CKP bit is cleared and SCL line is held low are the

same. Figure 32-21 can be used as a reference of a

slave in 10-bit addressing with AHEN set.

Figure 32-20 is used as a visual reference for this

description.

This is a step by step process of what must be done by

slave software to accomplish I²C communication.

Figure 32-22 shows a standard waveform for a slave

transmitter in 10-bit Addressing mode.

1. Master sends Start condition; S bit of SSPxSTAT

is set; SSPxIF is set if interrupt on Start detect is

enabled.

2. Master sends matching high address with R/W

bit clear; UA bit of the SSPxSTAT register is set.

3. Slave sends ACK and SSPxIF is set.

4. Software clears the SSPxIF bit.

5. Software reads received address from

SSPxBUF clearing the BF flag.

6. Slave loads low address into SSPxADD,

releasing SCL.

7. Master sends matching low address byte to the

slave; UA bit is set.

Note: Updates to the SSPxADD register are not

allowed until after the ACK sequence.

8. Slave sends ACK and SSPxIF is set.

Note: If the low address does not match, SSPxIF

and UA are still set so that the slave

software can set SSPxADD back to the high

address. BF is not set because there is no

match. CKP is unaffected.

9. Slave clears SSPxIF.

10. Slave reads the received matching address

from SSPxBUF clearing BF.

11. Slave loads high address into SSPxADD.

12. Master clocks a data byte to the slave and

clocks out the slaves ACK on the ninth SCL

pulse; SSPxIF is set.

13. If SEN bit of SSPxCON2 is set, CKP is cleared

by hardware and the clock is stretched.

14. Slave clears SSPxIF.

15. Slave reads the received byte from SSPxBUF

clearing BF.

16. If SEN is set the slave software sets CKP to

release the SCL.

17. Steps 13-17 repeat for each received byte.

18. Master sends Stop to end the transmission.

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32.5.6 CLOCK STRETCHING

32.5.6.3 Byte NACKing

Clock stretching occurs when a device on the bus

holds the SCL line low, effectively pausing communi-

cation. The slave may stretch the clock to allow more

time to handle data or prepare a response for the

master device. A master device is not concerned with

stretching as anytime it is active on the bus and not

transferring data it is stretching. Any stretching done

by a slave is invisible to the master software and

handled by the hardware that generates SCL.

When AHEN bit of SSPxCON3 is set; CKP is cleared

by hardware after the eighth falling edge of SCL for a

received matching address byte. When DHEN bit of

SSPxCON3 is set; CKP is cleared after the eighth fall-

ing edge of SCL for received data.

Stretching after the eighth falling edge of SCL allows

the slave to look at the received address or data and

decide if it wants to ACK the received data.

32.5.7 CLOCK SYNCHRONIZATION AND THE

CKP BIT

The CKP bit of the SSPxCON1 register is used to

control stretching. Any time the CKP bit is cleared, the

module will wait for the SCL line to go low and then

hold it. Setting CKP will release SCL and allow more

communication.

Any time the CKP bit is cleared, the module will wait

for the SCL line to go low and then hold it. However,

clearing the CKP bit will not assert the SCL output low

until the SCL output is already sampled low. There-

fore, the CKP bit will not assert the SCL line until an

external I²C master device has already asserted the

SCL line. The SCL output will remain low until the CKP

bit is set and all other devices on the I²C bus have

released SCL. This ensures that a write to the CKP bit

will not violate the minimum high time requirement for

SCL (see Figure 32-23).

32.5.6.1 Normal Clock Stretching

Following an ACK if the R/W bit of SSPxSTAT is set, a

read request, the slave hardware will clear CKP. This

allows the slave time to update SSPxBUF with data to

transfer to the master. If the SEN bit of SSPxCON2 is

set, the slave hardware will always stretch the clock

after the ACK sequence. Once the slave is ready; CKP

is set by software and communication resumes.

32.5.6.2 10-bit Addressing Mode

In 10-bit Addressing mode, when the UA bit is set the

clock is always stretched. This is the only time the SCL

is stretched without CKP being cleared. SCL is

released immediately after a write to SSPxADD.

FIGURE 32-23:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX ‚ – 1

Master device

asserts clock

CKP

Master device

releases clock

WR

SSPxCON1

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32.5.8 GENERAL CALL ADDRESS SUPPORT

In 10-bit Address mode, the UA bit will not be set on

the reception of the general call address. The slave

will prepare to receive the second byte as data, just as

it would in 7-bit mode.

The addressing procedure for the I²C bus is such that

the first byte after the Start condition usually deter-

mines which device will be the slave addressed by the

master device. The exception is the general call

address which can address all devices. When this

address is used, all devices should, in theory, respond

with an acknowledge.

If the AHEN bit of the SSPxCON3 register is set, just

as with any other address reception, the slave hard-

ware will stretch the clock after the eighth falling edge

of SCL. The slave must then set its ACKDT value and

release the clock with communication progressing as it

would normally.

The general call address is a reserved address in the

I²C protocol, defined as address 0x00. When the

GCEN bit of the SSPxCON2 register is set, the slave

module will automatically ACK the reception of this

address regardless of the value stored in SSPxADD.

After the slave clocks in an address of all zeros with

the R/W bit clear, an interrupt is generated and slave

software can read SSPxBUF and respond. Figure 32-

24 shows a general call reception sequence.

FIGURE 32-24:

SLAVE MODE GENERAL CALL ADDRESS SEQUENCE

Address is compared to General Call Address

after ACK, set interrupt

Receiving Data

D5 D4 D3 D2 D1

ACK

R/W = 0

ACK

General Call Address

SDA

SCL

D7 D6

D0

8

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

9

S

SSPxIF

BF (SSPxSTAT<0>)

Cleared by software

SSPxBUF is read

GCEN (SSPxCON2<7>)

’1’

32.5.9 SSP MASK REGISTER

This register is reset to all ‘1’s upon any Reset

condition and, therefore, has no effect on standard

SSP operation until written with a mask value.

An SSP Mask (SSPxMSK) register (Register 32-5) is

available in I²C Slave mode as a mask for the value

held in the SSPxSR register during an address

comparison operation. A zero (‘0’) bit in the SSPxMSK

register has the effect of making the corresponding bit

of the received address a “don’t care”.

The SSP Mask register is active during:

• 7-bit Address mode: address compare of A<7:1>.

• 10-bit Address mode: address compare of A<7:0>

only. The SSP mask has no effect during the

reception of the first (high) byte of the address.

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32.6.1 I²C MASTER MODE OPERATION

2

32.6 I C Master Mode

The master device generates all of the serial clock

pulses and the Start and Stop conditions. A transfer is

ended with a Stop condition or with a Repeated Start

condition. Since the Repeated Start condition is also

the beginning of the next serial transfer, the I²C bus will

not be released.

Master mode is enabled by setting and clearing the

appropriate SSPM bits in the SSPxCON1 register and

by setting the SSPEN bit. In Master mode, the SDA and

SCK pins must be configured as inputs. The MSSP

peripheral hardware will override the output driver TRIS

controls when necessary to drive the pins low.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ‘0’. Serial data is

transmitted eight bits at a time. After each byte is

transmitted, an Acknowledge bit is received. Start and

Stop conditions are output to indicate the beginning

and the end of a serial transfer.

Master mode of operation is supported by interrupt

generation on the detection of the Start and Stop

conditions. The Stop (P) and Start (S) bits are cleared

from a Reset or when the MSSP module is disabled.

Control of the I²C bus may be taken when the P bit is

set, or the bus is Idle.

In Firmware Controlled Master mode, user code

conducts all I²C bus operations based on Start and

Stop bit condition detection. Start and Stop condition

detection is the only active circuitry in this mode. All

other communication is done by the user software

directly manipulating the SDA and SCL lines.

In Master Receive mode, the first byte transmitted

contains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ‘1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ‘1’ to indicate the receive bit.

Serial data is received via SDA, while SCL outputs the

serial clock. Serial data is received eight bits at a time.

After each byte is received, an Acknowledge bit is

transmitted. Start and Stop conditions indicate the

beginning and end of transmission.

The following events will cause the SSP Interrupt Flag

bit, SSPxIF, to be set (SSP interrupt, if enabled):

• Start condition generated

• Stop condition generated

• Data transfer byte transmitted/received

• Acknowledge transmitted/received

• Repeated Start generated

A Baud Rate Generator is used to set the clock

frequency output on SCL. See Section 32.7 “Baud

Rate Generator” for more detail.

Note 1:The MSSP module, when configured in I²C

Master mode, does not allow queuing of

events. For instance, the user is not

allowed to initiate a Start condition and

immediately write the SSPxBUF register

to initiate transmission before the Start

condition is complete. In this case, the

SSPxBUF will not be written to and the

WCOL bit will be set, indicating that a

write to the SSPxBUF did not occur

2: When in Master mode, Start/Stop

detection is masked and an interrupt is

generated when the SEN/PEN bit is

cleared and the generation is complete.

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32.6.2 CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

releases the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the Baud Rate

Generator (BRG) is suspended from counting until the

SCL pin is actually sampled high. When the SCL pin is

sampled high, the Baud Rate Generator is reloaded

with the contents of SSPxADD<7:0> and begins count-

ing. This ensures that the SCL high time will always be

at least one BRG rollover count in the event that the

clock is held low by an external device (Figure 32-25).

FIGURE 32-25:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

DX

DX ‚ – 1

SCL allowed to transition high

SCL deasserted but slave holds

SCL low (clock arbitration)

SCL

BRG decrements on

Q2 and Q4 cycles

BRG

Value

03h

02h

01h

00h (hold off)

03h

02h

SCL is sampled high, reload takes

place and BRG starts its count

BRG

Reload

32.6.3 WCOL STATUS FLAG

If the user writes the SSPxBUF when a Start, Restart,

Stop, Receive or Transmit sequence is in progress, the

WCOL is set and the contents of the buffer are

unchanged (the write does not occur). Any time the

WCOL bit is set it indicates that an action on SSPxBUF

was attempted while the module was not idle.

Note:

Because queuing of events is not allowed,

writing to the lower five bits of SSPxCON2

is disabled until the Start condition is

complete.

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2

32.6.4 I C MASTER MODE START

by hardware; the Baud Rate Generator is suspended,

leaving the SDA line held low and the Start condition is

complete.

CONDITION TIMING

To initiate a Start condition (Figure 32-26), the user

sets the Start Enable bit, SEN bit of the SSPxCON2

register. If the SDA and SCL pins are sampled high,

the Baud Rate Generator is reloaded with the contents

of SSPxADD<7:0> and starts its count. If SCL and

SDA are both sampled high when the Baud Rate Gen-

erator times out (TBRG), the SDA pin is driven low. The

action of the SDA being driven low while SCL is high is

the Start condition and causes the S bit of the

SSPxSTAT1 register to be set. Following this, the

Baud Rate Generator is reloaded with the contents of

SSPxADD<7:0> and resumes its count. When the

Baud Rate Generator times out (TBRG), the SEN bit of

the SSPxCON2 register will be automatically cleared

Note 1:If at the beginning of the Start condition, the

SDA and SCL pins are already sampled

low, or if during the Start condition, the

SCL line is sampled low before the SDA

line is driven low, a bus collision occurs,

the Bus Collision Interrupt Flag, BCLIF, is

set, the Start condition is aborted and the

I²C module is reset into its Idle state.

2: The Philips I²C specification states that a

bus collision cannot occur on a Start.

FIGURE 32-26:

FIRST START BIT TIMING

Set S bit (SSPxSTAT<3>)

Write to SEN bit occurs here

At completion of Start bit,

hardware clears SEN bit

and sets SSPxIF bit

SDA = 1,

SCL = 1

TBRG

Write to SSPxBUF occurs here

2nd bit

SDA

1st bit

TBRG

SCL

S

TBRG

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2

32.6.5 I C MASTER MODE REPEATED

cally cleared and the Baud Rate Generator will not be

reloaded, leaving the SDA pin held low. As soon as a

Start condition is detected on the SDA and SCL pins,

the S bit of the SSPxSTAT register will be set. The

SSPxIF bit will not be set until the Baud Rate Generator

has timed out.

START CONDITION TIMING

A Repeated Start condition (Figure 32-27) occurs when

the RSEN bit of the SSPxCON2 register is pro-

grammed high and the master state machine is no lon-

ger active. When the RSEN bit is set, the SCL pin is

asserted low. When the SCL pin is sampled low, the

Baud Rate Generator is loaded and begins counting.

The SDA pin is released (brought high) for one Baud

Rate Generator count (TBRG). When the Baud Rate

Generator times out, if SDA is sampled high, the SCL

pin will be deasserted (brought high). When SCL is

sampled high, the Baud Rate Generator is reloaded

and begins counting. SDA and SCL must be sampled

high for one TBRG. This action is then followed by

assertion of the SDA pin (SDA = 0) for one TBRG while

SCL is high. SCL is asserted low. Following this, the

RSEN bit of the SSPxCON2 register will be automati-

Note 1: If RSEN is programmed while any other

event is in progress, it will not take effect.

2: A bus collision during the Repeated Start

condition occurs if:

•SDA is sampled low when SCL goes

from low-to-high.

•SCL goes low before SDA is

asserted low. This may indicate

that another master is attempting

to transmit a data ‘1’.

FIGURE 32-27:

REPEATED START CONDITION WAVEFORM

S bit set by hardware

Write to SSPxCON2

occurs here

SDA = 1,

At completion of Start bit,

hardware clears RSEN bit

and sets SSPxIF

SDA = 1,

SCL = 1

SCL (no change)

TBRG

1st bit

SDA

SCL

Write to SSPxBUF occurs here

TBRG

Sr

Repeated Start

TBRG

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32.6.6 I²C MASTER MODE TRANSMISSION

32.6.6.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit of the SSPxCON2

register is cleared when the slave has sent an Acknowl-

edge (ACK = 0) and is set when the slave does not

Acknowledge (ACK = 1). A slave sends an Acknowl-

edge when it has recognized its address (including a

general call), or when the slave has properly received

its data.

Transmission of a data byte, a 7-bit address or the

other half of a 10-bit address is accomplished by simply

writing a value to the SSPxBUF register. This action will

set the Buffer Full flag bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted. SCL is held low for one Baud Rate Generator

rollover count (TBRG). Data should be valid before SCL

is released high. When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF flag is cleared and the master releases SDA.

This allows the slave device being addressed to

respond with an ACK bit during the ninth bit time if an

address match occurred, or if data was received prop-

erly. The status of ACK is written into the ACKSTAT bit

on the rising edge of the ninth clock. If the master

receives an Acknowledge, the Acknowledge Status bit,

ACKSTAT, is cleared. If not, the bit is set. After the ninth

clock, the SSPxIF bit is set and the master clock (Baud

Rate Generator) is suspended until the next data byte

is loaded into the SSPxBUF, leaving SCL low and SDA

unchanged (Figure 32-28).

32.6.6.4 Typical transmit sequence:

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

3. SSPxIF is cleared by software.

4. The MSSP module will wait the required start

time before any other operation takes place.

5. The user loads the SSPxBUF with the slave

address to transmit.

6. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

7. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

8. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the

SSPxIF bit.

After the write to the SSPxBUF, each bit of the address

will be shifted out on the falling edge of SCL until all

seven address bits and the R/W bit are completed. On

the falling edge of the eighth clock, the master will

release the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit of the SSPxCON2

register. Following the falling edge of the ninth clock

transmission of the address, the SSPxIF is set, the BF

flag is cleared and the Baud Rate Generator is turned

off until another write to the SSPxBUF takes place,

holding SCL low and allowing SDA to float.

9. The user loads the SSPxBUF with eight bits of

data.

10. Data is shifted out the SDA pin until all eight bits

are transmitted.

11. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

12. Steps 8-11 are repeated for all transmitted data

bytes.

13. The user generates a Stop or Restart condition

by setting the PEN or RSEN bits of the SSPx-

CON2 register. Interrupt is generated once the

Stop/Restart condition is complete.

32.6.6.1

BF Status Flag

In Transmit mode, the BF bit of the SSPxSTAT register

is set when the CPU writes to SSPxBUF and is cleared

when all eight bits are shifted out.

32.6.6.2

WCOL Status Flag

If the user writes the SSPxBUF when a transmit is

already in progress (i.e., SSPxSR is still shifting out a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

WCOL must be cleared by software before the next

transmission.

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I²C MASTER MODE RECEPTION

32.6.7.4 Typical Receive Sequence:

32.6.7

Master mode reception (Figure 32-29) is enabled by

programming the Receive Enable bit, RCEN bit of the

SSPxCON2 register.

1. The user generates a Start condition by setting

the SEN bit of the SSPxCON2 register.

2. SSPxIF is set by hardware on completion of the

Start.

Note:

The MSSP module must be in an Idle

state before the RCEN bit is set or the

RCEN bit will be disregarded.

3. SSPxIF is cleared by software.

4. User writes SSPxBUF with the slave address to

transmit and the R/W bit set.

The Baud Rate Generator begins counting and on each

rollover, the state of the SCL pin changes (high-to-low/

low-to-high) and data is shifted into the SSPxSR. After

the falling edge of the eighth clock, the receive enable

flag is automatically cleared, the contents of the

SSPxSR are loaded into the SSPxBUF, the BF flag bit

is set, the SSPxIF flag bit is set and the Baud Rate

Generator is suspended from counting, holding SCL

low. The MSSP is now in Idle state awaiting the next

command. When the buffer is read by the CPU, the BF

flag bit is automatically cleared. The user can then

send an Acknowledge bit at the end of reception by set-

ting the Acknowledge Sequence Enable, ACKEN bit of

the SSPxCON2 register.

5. Address is shifted out the SDA pin until all eight

bits are transmitted. Transmission begins as

soon as SSPxBUF is written to.

6. The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit of the SSPxCON2 register.

7. The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the

SSPxIF bit.

8. User sets the RCEN bit of the SSPxCON2

register and the master clocks in a byte from the

slave.

9. After the eighth falling edge of SCL, SSPxIF and

BF are set.

32.6.7.1

BF Status Flag

10. Master clears SSPxIF and reads the received

byte from SSPxBUF, clears BF.

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPxBUF from SSPxSR. It

is cleared when the SSPxBUF register is read.

11. Master sets ACK value sent to slave in ACKDT

bit of the SSPxCON2 register and initiates the

ACK by setting the ACKEN bit.

32.6.7.2

SSPOV Status Flag

12. Master’s ACK is clocked out to the slave and

SSPxIF is set.

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPxSR and the BF flag bit is

already set from a previous reception.

13. User clears SSPxIF.

14. Steps 8-13 are repeated for each received byte

from the slave.

32.6.7.3

WCOL Status Flag

If the user writes the SSPxBUF when a receive is

already in progress (i.e., SSPxSR is still shifting in a

data byte), the WCOL bit is set and the contents of the

buffer are unchanged (the write does not occur).

15. Master sends a not ACK or Stop to end

communication.

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32.6.8

ACKNOWLEDGE SEQUENCE

TIMING

32.6.9

STOP CONDITION TIMING

A Stop bit is asserted on the SDA pin at the end of a

receive/transmit by setting the Stop Sequence Enable

bit, PEN bit of the SSPxCON2 register. At the end of a

receive/transmit, the SCL line is held low after the

falling edge of the ninth clock. When the PEN bit is set,

the master will assert the SDA line low. When the SDA

line is sampled low, the Baud Rate Generator is

reloaded and counts down to ‘0’. When the Baud Rate

Generator times out, the SCL pin will be brought high

and one TBRG (Baud Rate Generator rollover count)

later, the SDA pin will be deasserted. When the SDA

pin is sampled high while SCL is high, the P bit of the

SSPxSTAT register is set. A TBRG later, the PEN bit is

cleared and the SSPxIF bit is set (Figure 32-31).

An Acknowledge sequence is enabled by setting the

Acknowledge Sequence Enable bit, ACKEN bit of the

SSPxCON2 register. When this bit is set, the SCL pin is

pulled low and the contents of the Acknowledge data bit

are presented on the SDA pin. If the user wishes to

generate an Acknowledge, then the ACKDT bit should

be cleared. If not, the user should set the ACKDT bit

before starting an Acknowledge sequence. The Baud

Rate Generator then counts for one rollover period

(TBRG) and the SCL pin is deasserted (pulled high).

When the SCL pin is sampled high (clock arbitration),

the Baud Rate Generator counts for TBRG. The SCL pin

is then pulled low. Following this, the ACKEN bit is auto-

matically cleared, the Baud Rate Generator is turned off

and the MSSP module then goes into IDLE mode

(Figure 32-30).

32.6.9.1

WCOL Status Flag

If the user writes the SSPxBUF when a Stop sequence

is in progress, then the WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

32.6.8.1

WCOL Status Flag

If the user writes the SSPxBUF when an Acknowledge

sequence is in progress, then WCOL bit is set and the

contents of the buffer are unchanged (the write does

not occur).

FIGURE 32-30:

ACKNOWLEDGE SEQUENCE WAVEFORM

Acknowledge sequence starts here,

write to SSPxCON2

ACKEN automatically cleared

ACKEN = 1, ACKDT = 0

TBRG

ACK

TBRG

SDA

SCL

D0

8

9

SSPxIF

Cleared in

SSPxIF set at

the end of receive

software

Cleared in

software

SSPxIF set at the end

of Acknowledge sequence

Note: TBRG = one Baud Rate Generator period.

FIGURE 32-31:

STOP CONDITION RECEIVE OR TRANSMIT MODE

SCL = 1for TBRG, followed by SDA = 1for TBRG

after SDA sampled high. P bit (SSPxSTAT<4>) is set.

Write to SSPxCON2,

set PEN

PEN bit (SSPxCON2<2>) is cleared by

hardware and the SSPxIF bit is set

Falling edge of

9th clock

TBRG

SCL

SDA

ACK

P

TBRG

SCL brought high after TBRG

SDA asserted low before rising edge of clock

to setup Stop condition

Note: TBRG = one Baud Rate Generator period.

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32.6.10 SLEEP OPERATION

32.6.13 MULTI -MASTER COMMUNICATION,

BUS COLLISION AND BUS

While in Sleep mode, the I²C slave module can receive

addresses or data and when an address match or

complete byte transfer occurs, wake the processor

from Sleep (if the MSSP interrupt is enabled).

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag, BCL1IF and reset the

I²C port to its Idle state (Figure 32-32).

32.6.11 EFFECTS OF A RESET

A Reset disables the MSSP module and terminates the

current transfer.

32.6.12 MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset or when the

MSSP module is disabled. Control of the I²C bus may

be taken when the P bit of the SSPxSTAT register is

set, or the bus is Idle, with both the S and P bits clear.

When the bus is busy, enabling the SSP interrupt will

generate the interrupt when the Stop condition occurs.

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF flag is

cleared, the SDA and SCL lines are deasserted and the

SSPxBUF can be written to. When the user services

the bus collision Interrupt Service Routine and if the I²C

bus is free, the user can resume communication by

asserting a Start condition.

In multi-master operation, the SDA line must be

monitored for arbitration to see if the signal level is the

expected output level. This check is performed by

hardware with the result placed in the BCL1IF bit.

If a Start, Repeated Start, Stop or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are deasserted and the respective control bits in

the SSPxCON2 register are cleared. When the user

services the bus collision Interrupt Service Routine and

if the I²C bus is free, the user can resume

communication by asserting a Start condition.

The states where arbitration can be lost are:

• Address Transfer

• Data Transfer

• A Start Condition

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPxIF bit will be set.

• A Repeated Start Condition

• An Acknowledge Condition

A write to the SSPxBUF will start the transmission of

data at the first data bit, regardless of where the

transmitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I²C

bus can be taken when the P bit is set in the SSPxSTAT

register, or the bus is Idle and the S and P bits are

cleared.

FIGURE 32-32:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

Sample SDA. While SCL is high,

data does not match what is driven

by the master.

Data changes

while SCL = 0

SDA line pulled low

by another source

Bus collision has occurred.

SDA released

by master

SDA

SCL

Set bus collision

interrupt (BCL1IF)

BCL1IF

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If the SDA pin is sampled low during this count, the

BRG is reset and the SDA line is asserted early

(Figure 32-35). If, however, a ‘1’ is sampled on the SDA

pin, the SDA pin is asserted low at the end of the BRG

count. The Baud Rate Generator is then reloaded and

counts down to zero; if the SCL pin is sampled as ‘0’

during this time, a bus collision does not occur. At the

end of the BRG count, the SCL pin is asserted low.

32.6.13.1 Bus Collision During a Start

Condition

During a Start condition, a bus collision occurs if:

a) SDA or SCL are sampled low at the beginning of

the Start condition (Figure 32-33).

b) SCL is sampled low before SDA is asserted low

(Figure 32-34).

During a Start condition, both the SDA and the SCL

pins are monitored.

Note:

The reason that bus collision is not a

factor during a Start condition is that no

two bus masters can assert a Start condi-

tion at the exact same time. Therefore,

one master will always assert SDA before

the other. This condition does not cause a

bus collision because the two masters

must be allowed to arbitrate the first

address following the Start condition. If

the address is the same, arbitration must

be allowed to continue into the data por-

tion, Repeated Start or Stop conditions.

If the SDA pin is already low, or the SCL pin is already

low, then all of the following occur:

• the Start condition is aborted,

• the BCL1IF flag is set and

•

the MSSP module is reset to its Idle state

(Figure 32-33).

The Start condition begins with the SDA and SCL pins

deasserted. When the SDA pin is sampled high, the

Baud Rate Generator is loaded and counts down. If the

SCL pin is sampled low while SDA is high, a bus

collision occurs because it is assumed that another

master is attempting to drive a data ‘1’ during the Start

condition.

FIGURE 32-33:

BUS COLLISION DURING START CONDITION (SDA ONLY)

SDA goes low before the SEN bit is set.

Set BCL1IF,

S bit and SSPxIF set because

SDA = 0, SCL = 1.

SDA

SCL

SEN

Set SEN, enable Start

condition if SDA = 1, SCL = 1

SEN cleared automatically because of bus collision.

SSP module reset into Idle state.

SDA sampled low before

Start condition. Set BCL1IF.

S bit and SSPxIF set because

SDA = 0, SCL = 1.

BCL1IF

SSPxIF and BCL1IF are

cleared by software

S

SSPxIF

SSPxIF and BCL1IF are

cleared by software

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FIGURE 32-34:

BUS COLLISION DURING START CONDITION (SCL = 0)

SDA = 0, SCL = 1

TBRG

SDA

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

SCL

SEN

SCL = 0before SDA = 0,

bus collision occurs. Set BCL1IF.

SCL = 0before BRG time-out,

bus collision occurs. Set BCL1IF.

BCL1IF

Interrupt cleared

by software

S

’0’

SSPxIF

FIGURE 32-35:

BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION

SDA = 0, SCL = 1

Set S

Set SSPxIF

Less than TBRG

TBRG

SDA pulled low by other master.

Reset BRG and assert SDA.

SDA

SCL

S

SCL pulled low after BRG

time-out

SEN

Set SEN, enable Start

sequence if SDA = 1, SCL = 1

’0’

BCL1IF

S

SSPxIF

Interrupts cleared

by software

SDA = 0, SCL = 1,

set SSPxIF

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counting. If SDA goes from high-to-low before the BRG

times out, no bus collision occurs because no two

masters can assert SDA at exactly the same time.

32.6.13.2 Bus Collision During a Repeated

Start Condition

During a Repeated Start condition, a bus collision

occurs if:

If SCL goes from high-to-low before the BRG times out

and SDA has not already been asserted, a bus collision

occurs. In this case, another master is attempting to

transmit a data ‘1’ during the Repeated Start condition,

see Figure 32-37.

a) A low level is sampled on SDA when SCL goes

from low level to high level (Case 1).

b) SCL goes low before SDA is asserted low,

indicating that another master is attempting to

transmit a data ‘1’ (Case 2).

If, at the end of the BRG time-out, both SCL and SDA

are still high, the SDA pin is driven low and the BRG is

reloaded and begins counting. At the end of the count,

regardless of the status of the SCL pin, the SCL pin is

driven low and the Repeated Start condition is

complete.

When the user releases SDA and the pin is allowed to

float high, the BRG is loaded with SSPxADD and

counts down to zero. The SCL pin is then deasserted

and when sampled high, the SDA pin is sampled.

If SDA is low, a bus collision has occurred (i.e., another

master is attempting to transmit a data ‘0’, Figure 32-36).

If SDA is sampled high, the BRG is reloaded and begins

FIGURE 32-36:

BUS COLLISION DURING A REPEATED START CONDITION (CASE 1)

SDA

SCL

Sample SDA when SCL goes high.

If SDA = 0, set BCL1IF and release SDA and SCL.

RSEN

BCL1IF

Cleared by software

’0’

S

’0’

SSPxIF

FIGURE 32-37:

BUS COLLISION DURING REPEATED START CONDITION (CASE 2)

TBRG

SDA

SCL

SCL goes low before SDA,

set BCL1IF. Release SDA and SCL.

BCL1IF

RSEN

Interrupt cleared

by software

’0’

S

SSPxIF

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The Stop condition begins with SDA asserted low.

When SDA is sampled low, the SCL pin is allowed to

float. When the pin is sampled high (clock arbitration),

the Baud Rate Generator is loaded with SSPxADD and

counts down to zero. After the BRG times out, SDA is

sampled. If SDA is sampled low, a bus collision has

occurred. This is due to another master attempting to

drive a data ‘0’ (Figure 32-38). If the SCL pin is sampled

low before SDA is allowed to float high, a bus collision

occurs. This is another case of another master

attempting to drive a data ‘0’ (Figure 32-39).

32.6.13.3 Bus Collision During a Stop

Condition

Bus collision occurs during a Stop condition if:

a) After the SDA pin has been deasserted and

allowed to float high, SDA is sampled low after

the BRG has timed out (Case 1).

b) After the SCL pin is deasserted, SCL is sampled

low before SDA goes high (Case 2).

FIGURE 32-38:

BUS COLLISION DURING A STOP CONDITION (CASE 1)

SDA sampled

low after TBRG,

set BCL1IF

TBRG

SDA

SDA asserted low

SCL

PEN

BCL1IF

P

’0’

SSPxIF

FIGURE 32-39:

BUS COLLISION DURING A STOP CONDITION (CASE 2)

TBRG

SDA

SCL goes low before SDA goes high,

set BCL1IF

Assert SDA

SCL

PEN

BCL1IF

P

’0’

SSPxIF

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module clock line. The logic dictating when the reload

signal is asserted depends on the mode the MSSP is

being operated in.

32.7 BAUD RATE GENERATOR

The MSSP module has a Baud Rate Generator avail-

able for clock generation in both I²C and SPI Master

modes. The Baud Rate Generator (BRG) reload value

is placed in the SSPxADD register (Register 32-6).

When a write occurs to SSPxBUF, the Baud Rate

Generator will automatically begin counting down.

Table 32-4 demonstrates clock rates based on

instruction cycles and the BRG value loaded into

SSPxADD.

EQUATION 32-1:

Once the given operation is complete, the internal clock

will automatically stop counting and the clock pin will

remain in its last state.

FOSC

FCLOCK = --------------------------------------------------

SSP1ADD + 14

An internal signal “Reload” in Figure 32-40 triggers the

value from SSPxADD to be loaded into the BRG

counter. This occurs twice for each oscillation of the

FIGURE 32-40:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM<3:0>

SSPxADD<7:0>

SSPM<3:0>

SCL

Reload

Control

Reload

BRG Down Counter

SSPCLK

FOSC/2

Note: Values of 0x00, 0x01 and 0x02 are not

valid for SSPxADD when used as a Baud

Rate Generator for I²C. This is an

implementation limitation.

TABLE 32-2: MSSP CLOCK RATE W/BRG

FCLOCK

(2 Rollovers of BRG)

FOSC

FCY

BRG Value

32 MHz

16 MHz

4 MHz

8 MHz

4 MHz

1 MHz

13h

19h

4Fh

09h

0Ch

27h

09h

400 kHz

308 kHz

100 kHz

400 kHz

308 kHz

100 kHz

Note:

Refer to the I/O port electrical specifications in Table 37-4 to ensure the system is designed to support IOL

requirements.

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32.8 Register Definitions: MSSPx Control

REGISTER 32-1: SSPxSTAT: SSPx STATUS REGISTER

R/W-0/0

SMP

R/W-0/0

R/HS/HC-0

D/A

R/HS/HC-0

R/W

R/HS/HC-0

UA

R/HS/HC-0

BF

(1)

(2)

CKE

P

S

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS/HC = Hardware set/clear

bit 7

SMP: SPI Data Input Sample bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

2

In I C Master or Slave mode:

1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)

0 = Slew rate control enabled for High-Speed mode (400 kHz)

(1)

bit 6

CKE: SPI Clock Edge Select bit (SPI mode only)

In SPI Master or Slave mode:

1= Transmit occurs on transition from active to Idle clock state

0= Transmit occurs on transition from Idle to active clock state

2

In I C mode only:

1= Enable input logic so that thresholds are compliant with SMBus specification

0= Disable SMBus specific inputs

2

bit 5

bit 4

D/A: Data/Address bit (I C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

(2)

P: Stop bit

2

(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

(2)

bit 3

bit 2

S: Start bit

2

(I C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

2

R/W: Read/Write bit information (I C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the

next Start bit, Stop bit, or not ACK bit.

2

In I C Slave mode:

1= Read

0= Write

2

In I C Master mode:

1= Transmit is in progress

0= Transmit is not in progress

OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in IDLE mode.

2

bit 1

bit 0

UA: Update Address bit (10-bit I C mode only)

1= Indicates that the user needs to update the address in the SSPxADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

2

Receive (SPI and I C modes):

1= Receive complete, SSPxBUF is full

0= Receive not complete, SSPxBUF is empty

2

Transmit (I C mode only):

1= Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full

0= Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty

Note 1:

2:

Polarity of clock state is set by the CKP bit of the SSPxCON register.

This bit is cleared on Reset and when SSPEN is cleared.

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REGISTER 32-2: SSPxCON1: SSPx CONTROL REGISTER 1

R/C/HS-0/0

WCOL

R/C/HS-0/0

SSPOV⁽¹⁾

R/W-0/0

SSPEN

R/W-0/0

CKP

R/W-0/0

SSPM<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS = Bit is set by hardware C = User cleared

bit 7

bit 6

WCOL: Write Collision Detect bit (Transmit mode only)

1= The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software)

0= No collision

SSPOV: Receive Overflow Indicator bit⁽¹⁾

In SPI mode:

1= A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost.

Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid

setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the

SSPxBUF register (must be cleared in software).

0= No overflow

In I²C mode:

1= A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode

(must be cleared in software).

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, the following pins must be properly configured as input or output

In SPI mode:

1= Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins⁽²⁾

0= Disables serial port and configures these pins as I/O port pins

In I²C mode:

1= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins⁽³⁾

0= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level

0= Idle state for clock is a low level

In I²C Slave mode:

SCL release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I²C Master mode:

Unused in this mode

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1101= Reserved

1100= Reserved

1011= I²C firmware controlled Master mode (slave idle)

1010= SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))⁽⁵⁾

1001= Reserved

1000= I²C Master mode, clock = FOSC / (4 * (SSPxADD+1))⁽⁴⁾

0111= I²C Slave mode, 10-bit address

0110= I²C Slave mode, 7-bit address

0101= SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin

0100= SPI Slave mode, clock = SCK pin, SS pin control enabled

0011= SPI Master mode, clock = T2_match/2

0010= SPI Master mode, clock = FOSC/64

0001= SPI Master mode, clock = FOSC/16

0000= SPI Master mode, clock = FOSC/4

Note 1:

2:

In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register.

When enabled, these pins must be properly configured as input or output. Use SSPxSSPPS, SSPxCLKPPS, SSPxDATPPS, and

RxyPPS to select the pins.

3:

4:

5:

When enabled, the SDA and SCL pins must be configured as inputs. Use SSPxCLKPPS, SSPxDATPPS, and RxyPPS to select the pins.

SSPxADD values of 0, 1 or 2 are not supported for I²C mode.

SSPxADD value of ‘0’ is not supported. Use SSPM = 0000instead.

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REGISTER 32-3: SSPxCON2: SSPx CONTROL REGISTER 2 (I²C MODE ONLY)⁽¹⁾

R/W-0/0

GCEN

R/HS/HC-0

ACKSTAT

R/W-0/0

ACKDT

R/S/HC-0/0 R/S/HC-0/0 R/S/HC-0/0

ACKEN RCEN PEN

R/S/HC-0/0 R/S/HC-0/0

RSEN SEN

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

-n/n = Value at POR and BOR/Value at all other Resets

HC = Cleared by hardware S = User set

bit 7

bit 6

bit 5

GCEN: General Call Enable bit (in I²C Slave mode only)

1= Enable interrupt when a general call address (0x00 or 00h) is received in the SSPxSR

0= General call address disabled

ACKSTAT: Acknowledge Status bit (in I²C mode only)

1= Acknowledge was not received

0= Acknowledge was received

ACKDT: Acknowledge Data bit (in I²C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1= Not Acknowledge

0= Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I²C Master mode only)

In Master Receive mode:

1= Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0= Acknowledge sequence idle

bit 3

bit 2

RCEN: Receive Enable bit (in I²C Master mode only)

1= Enables Receive mode for I²C

0= Receive idle

PEN: Stop Condition Enable bit (in I²C Master mode only)

SCKMSSP Release Control:

1= Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0= Stop condition Idle

bit 1

bit 0

RSEN: Repeated Start Condition Enable bit (in I²C Master mode only)

1= Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Repeated Start condition Idle

SEN: Start Condition Enable/Stretch Enable bit

In Master mode:

1= Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0= Start condition Idle

In Slave mode:

1= Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0= Clock stretching is disabled

Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I²C module is not in the IDLE mode, this bit may not be

set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).

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REGISTER 32-4: SSPxCON3: SSPx CONTROL REGISTER 3

R-0/0

R/W-0/0

PCIE

R/W-0/0

SCIE

R/W-0/0

BOEN

R/W-0/0

SDAHT

R/W-0/0

SBCDE

R/W-0/0

AHEN

R/W-0/0

DHEN

(3)

ACKTIM

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

2

(3)

bit 7

bit 6

bit 5

bit 4

ACKTIM: Acknowledge Time Status bit (I C mode only)

2

th

1= Indicates the I C bus is in an Acknowledge sequence, set on 8 falling edge of SCL clock

0= Not an Acknowledge sequence, cleared on 9^THrising edge of SCL clock

2

PCIE: Stop Condition Interrupt Enable bit (I C mode only)

1= Enable interrupt on detection of Stop condition

(2)

0= Stop detection interrupts are disabled

2

SCIE: Start Condition Interrupt Enable bit (I C mode only)

1= Enable interrupt on detection of Start or Restart conditions

(2)

0= Start detection interrupts are disabled

BOEN: Buffer Overwrite Enable bit

(1)

In SPI Slave mode:

1= SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit

0= If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1

register is set, and the buffer is not updated

In I C Master mode and SPI Master mode:

This bit is ignored.

2

In I C Slave mode:

1= SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the

SSPOV bit only if the BF bit = 0.

0= SSPxBUF is only updated when SSPOV is clear

2

bit 3

bit 2

SDAHT: SDA Hold Time Selection bit (I C mode only)

1= Minimum of 300 ns hold time on SDA after the falling edge of SCL

0= Minimum of 100 ns hold time on SDA after the falling edge of SCL

2

SBCDE: Slave Mode Bus Collision Detect Enable bit (I C Slave mode only)

If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the

PIR3 register is set, and bus goes idle

1= Enable slave bus collision interrupts

0= Slave bus collision interrupts are disabled

2

bit 1

bit 0

AHEN: Address Hold Enable bit (I C Slave mode only)

1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1

register will be cleared and the SCL will be held low.

0= Address holding is disabled

2

DHEN: Data Hold Enable bit (I C Slave mode only)

1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the

SSPxCON1 register and SCL is held low.

0= Data holding is disabled

Note 1: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new

byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF.

2: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.

3: The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.

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REGISTER 32-5: SSPxMSK: SSPx MASK REGISTER

R/W-1/1

SSPxMSK<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-1

bit 0

SSPxMSK<7:1>: Mask bits

1= The received address bit n is compared to SSPxADD<n> to detect I²C address match

0= The received address bit n is not used to detect I²C address match

SSPxMSK<0>: Mask bit for I²C Slave mode, 10-bit Address

I²C Slave mode, 10-bit address (SSPM<3:0> = 0111or 1111):

1= The received address bit 0 is compared to SSPxADD<0> to detect I²C address match

0= The received address bit 0 is not used to detect I²C address match

I²C Slave mode, 7-bit address:

MSK0 bit is ignored.

REGISTER 32-6: SSPxADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I²C MODE)

R/W-0/0

SSPxADD<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

Master mode:

bit 7-0

SSPxADD<7:0>: Baud Rate Clock Divider bits

SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC

10-Bit Slave mode – Most Significant Address Byte:

bit 7-3

Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit

pattern sent by master is fixed by I²C specification and must be equal to ‘11110’. However, those bits

are compared by hardware and are not affected by the value in this register.

bit 2-1

bit 0

SSPxADD<2:1>: Two Most Significant bits of 10-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

10-Bit Slave mode – Least Significant Address Byte:

bit 7-0

SSPxADD<7:0>: Eight Least Significant bits of 10-bit address

7-Bit Slave mode:

bit 7-1

bit 0

SSPxADD<7:1>: 7-bit address

Not used: Unused in this mode. Bit state is a “don’t care”.

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REGISTER 32-7: SSPxBUF: MSSPx BUFFER REGISTER

R/W-x

SSPxBUF<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SSPxBUF<7:0>: MSSP Buffer bits

TABLE 32-3: SUMMARY OF REGISTERS ASSOCIATED WITH MSSPx

Register

on Page

Name

INTCON

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

GIE

PEIE

TX2IF

TX2IE

INTEDG

SSP1IF

SSP1IE

BF

121

141

133

PIR3

PIE3

RC2IF

RC2IE

RC1IF

RC1IE

TX1IF

TX1IE

BCL2IF

BCL2IE

S

SSP2IF

SSP2IE

R/W

BCL1IF

BCL1IE

UA

SSP1STAT

SSP1CON1

SSP1CON2

SSP1CON3

SSP1MSK

SSP1ADD

SSP1BUF

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

417

418

419

417

421

422

SSPEN

ACKDT

SCIE

CKP

SSPM<3:0>

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

SSPMSK<7:0>

SSPADD<7:0>

SSPBUF<7:0>

SSP2STAT

SSP2CON1

SSP2CON2

SSP2CON3

SSP2MSK

SMP

WCOL

GCEN

ACKTIM

CKE

SSPOV

ACKSTAT

PCIE

D/A

P

S

R/W

UA

BF

417

418

419

417

421

422

199

200

SSPEN

ACKDT

SCIE

CKP

SSPM<3:0>

ACKEN

BOEN

RCEN

PEN

RSEN

AHEN

SEN

SDAHT

SBCDE

DHEN

SSPMSK<7:0>

SSP2ADD

SSPADD<7:0>

SSPBUF<7:0>

SSP2BUF

SSP1CLKPPS

SSP1DATPPS

SSP1SSPPS

SSP2CLKPPS

SSP2DATPPS

SSP2SSPPS

RxyPPS

—

SSP1CLKPPS<5:0>

SSP1DATPPS<5:0>

SSP1SSPPS<5:0>

SSP2CLKPPS<5:0>

SSP2DATPPS<5:0>

SSP2SSPPS<5:0>

RxyPPS<4:0>

Legend:

— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx module

2

Note 1: When using designated I C pins, the associated pin values in INLVLx will be ignored.

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The EUSART module includes the following capabilities:

33.0 ENHANCED UNIVERSAL

SYNCHRONOUS

• Full-duplex asynchronous transmit and receive

• Two-character input buffer

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

• One-character output buffer

• Programmable 8-bit or 9-bit character length

• Address detection in 9-bit mode

The Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART) module is a serial I/O

communications peripheral. It contains all the clock

generators, shift registers and data buffers necessary

to perform an input or output serial data transfer

independent of device program execution. The

EUSART, also known as a Serial Communications

Interface (SCI), can be configured as a full-duplex

asynchronous system or half-duplex synchronous

• Input buffer overrun error detection

• Received character framing error detection

• Half-duplex synchronous master

• Half-duplex synchronous slave

• Programmable clock polarity in synchronous

modes

• Sleep operation

system.

Full-Duplex

mode

is

useful

for

The EUSART module implements the following

additional features, making it ideally suited for use in

Local Interconnect Network (LIN) bus systems:

communications with peripheral systems, such as CRT

terminals and personal computers. Half-Duplex

Synchronous mode is intended for communications

with peripheral devices, such as A/D or D/A integrated

circuits, serial EEPROMs or other microcontrollers.

These devices typically do not have internal clocks for

baud rate generation and require the external clock

signal provided by a master synchronous device.

• Automatic detection and calibration of the baud rate

• Wake-up on Break reception

• 13-bit Break character transmit

Block diagrams of the EUSART transmitter and

receiver are shown in Figure 33-1 and Figure 33-2.

Note:

Two identical EUSART modules are

implemented on this device, EUSART1

and EUSART2. All references to

EUSART1 apply to EUSART2 as well.

The EUSART transmit output (TX_out) is available to

the TX/CK pin and internally to the following peripherals:

• Configurable Logic Cell (CLC)

FIGURE 33-1:

EUSART TRANSMIT BLOCK DIAGRAM

Data Bus

TXxIE

TXxIF

SYNC

CSRC

Interrupt

TXxREG Register

RxyPPS⁽¹⁾

8

CK pin

TXEN

RX/DT pin

MSb

(8)

LSb

0

PPS

1

0

Pin Buffer

PPS

• • •

and Control

Transmit Shift Register (TSR)

CKPPS

SYNC

TX_out

TRMT

Baud Rate Generator

BRG16

FOSC

÷ n

TX9

n

+ 1

Multiplier x4

x16 x64

TX9D

TX/CK pin

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

1

PPS

RxyPPS

SPxBRGH SPxBRGL

SYNC

CSRC

Note 1: In Synchronous mode the DT output and RX input PPS

selections should enable the same pin.

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FIGURE 33-2:

EUSART RECEIVE BLOCK DIAGRAM

SPEN

CREN

OERR

RCIDL

RXPPS⁽¹⁾

RX/DT pin

RSR Register

MSb

Stop (8)

LSb

Start

Pin Buffer

and Control

Data

Recovery

7

1

0

PPS

• • •

Baud Rate Generator

FOSC

RX9

÷ n

BRG16

n

+ 1

Multiplier

x4

x16 x64

SYNC

BRGH

BRG16

1

X

1

0

1

0

1

0

FIFO

SPxBRGH SPxBRGL

X

RX9D

FERR

RCxREG Register

8

Data Bus

Note 1: In Synchronous mode the DT output and RX input PPS

RXxIF

RXxIE

Interrupt

selections should enable the same pin.

The operation of the EUSART module is controlled

through three registers:

• Transmit Status and Control (TXxSTA)

• Receive Status and Control (RCxSTA)

• Baud Rate Control (BAUDxCON)

These registers are detailed in Register 33-1,

Register 33-2 and Register 33-3, respectively.

The RX input pin is selected with the RXxPPS. The CK

input is selected with the TXxPPS register. TX, CK, and

DT output pins are selected with each pin’s RxyPPS

register. Since the RX input is coupled with the DT output

in Synchronous mode, it is the user’s responsibility to

select the same pin for both of these functions when

operating in Synchronous mode. The EUSART control

logic will control the data direction drivers automatically.

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33.1.1.2

Transmitting Data

33.1 EUSART Asynchronous Mode

A transmission is initiated by writing a character to the

TXxREG register. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXxREG is immediately

transferred to the TSR register. If the TSR still contains

all or part of a previous character, the new character

data is held in the TXxREG until the Stop bit of the

previous character has been transmitted. The pending

character in the TXxREG is then transferred to the TSR

in one TCY immediately following the Stop bit

transmission. The transmission of the Start bit, data bits

and Stop bit sequence commences immediately

following the transfer of the data to the TSR from the

TXxREG.

The EUSART transmits and receives data using the

standard non-return-to-zero (NRZ) format. NRZ is

implemented with two levels: a VOH Mark state which

represents a ‘1’ data bit, and a VOL Space state which

represents a ‘0’ data bit. NRZ refers to the fact that

consecutively transmitted data bits of the same value

stay at the output level of that bit without returning to a

neutral level between each bit transmission. An NRZ

transmission port idles in the Mark state. Each character

transmission consists of one Start bit followed by eight

or nine data bits and is always terminated by one or

more Stop bits. The Start bit is always a space and the

Stop bits are always marks. The most common data

format is eight bits. Each transmitted bit persists for a

period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-

bit Baud Rate Generator is used to derive standard

baud rate frequencies from the system oscillator. See

Table 33-3 for examples of baud rate configurations.

33.1.1.3

Transmit Data Polarity

The polarity of the transmit data can be controlled with

the SCKP bit of the BAUDxCON register. The default

state of this bit is ‘0’ which selects high true transmit idle

and data bits. Setting the SCKP bit to ‘1’ will invert the

transmit data resulting in low true idle and data bits. The

SCKP bit controls transmit data polarity in

Asynchronous mode only. In Synchronous mode, the

SCKP bit has a different function. See Section 33.4.1.2

“Clock Polarity”.

The EUSART transmits and receives the LSb first. The

EUSART’s transmitter and receiver are functionally

independent, but share the same data format and baud

rate. Parity is not supported by the hardware, but can

be implemented in software and stored as the ninth

data bit.

33.1.1

EUSART ASYNCHRONOUS

TRANSMITTER

33.1.1.4

Transmit Interrupt Flag

The TXxIF interrupt flag bit of the PIR3 register is set

whenever the EUSART transmitter is enabled and no

character is being held for transmission in the TXxREG.

In other words, the TXxIF bit is only clear when the TSR

is busy with a character and a new character has been

queued for transmission in the TXxREG. The TXxIF flag

bit is not cleared immediately upon writing TXxREG.

TXxIF becomes valid in the second instruction cycle

following the write execution. Polling TXxIF immediately

following the TXxREG write will return invalid results.

The TXxIF bit is read-only, it cannot be set or cleared by

software.

The EUSART transmitter block diagram is shown in

Figure 33-1. The heart of the transmitter is the serial

Transmit Shift Register (TSR), which is not directly

accessible by software. The TSR obtains its data from

the transmit buffer, which is the TXxREG register.

33.1.1.1

Enabling the Transmitter

The EUSART transmitter is enabled for asynchronous

operations by configuring the following three control

bits:

• TXEN = 1

• SYNC = 0

• SPEN = 1

The TXxIF interrupt can be enabled by setting the

TXxIE interrupt enable bit of the PIE3 register. How-

ever, the TXxIF flag bit will be set whenever the

TXxREG is empty, regardless of the state of TXxIE

enable bit.

All other EUSART control bits are assumed to be in

their default state.

Setting the TXEN bit of the TXxSTA register enables the

transmitter circuitry of the EUSART. Clearing the SYNC

bit of the TXxSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCxSTA register enables the EUSART and

automatically configures the TX/CK I/O pin as an output.

If the TX/CK pin is shared with an analog peripheral, the

analog I/O function must be disabled by clearing the

corresponding ANSEL bit.

To use interrupts when transmitting data, set the TXxIE

bit only when there is more data to send. Clear the

TXxIE interrupt enable bit upon writing the last charac-

ter of the transmission to the TXxREG.

Note:

The TXxIF Transmitter Interrupt flag is set

when the TXEN enable bit is set.

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33.1.1.5

TSR Status

33.1.1.7

Asynchronous Transmission Set-up:

The TRMT bit of the TXxSTA register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

register from the TXxREG. The TRMT bit remains clear

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user has to

poll this bit to determine the TSR status.

1. Initialize the SPxBRGH, SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 33.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

3. If 9-bit transmission is desired, set the TX9

control bit. A set ninth data bit will indicate that

the eight Least Significant data bits are an

address when the receiver is set for address

detection.

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

4. Set SCKP bit if inverted transmit is desired.

33.1.1.6

Transmitting 9-Bit Characters

5. Enable the transmission by setting the TXEN

control bit. This will cause the TXxIF interrupt bit

to be set.

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXxSTA register is set, the

EUSART will shift nine bits out for each character trans-

mitted. The TX9D bit of the TXxSTA register is the

ninth, and Most Significant data bit. When transmitting

9-bit data, the TX9D data bit must be written before

writing the eight Least Significant bits into the TXxREG.

All nine bits of data will be transferred to the TSR shift

register immediately after the TXxREG is written.

6. If interrupts are desired, set the TXxIE interrupt

enable bit of the PIE3 register. An interrupt will

occur immediately provided that the GIE and

PEIE bits of the INTCON register are also set.

7. If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

8. Load 8-bit data into the TXxREG register. This

will start the transmission.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 33.1.2.7 “Address

Detection” for more information on the Address mode.

FIGURE 33-3:

ASYNCHRONOUS TRANSMISSION

Write to TXxREG

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXxIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

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FIGURE 33-4:

ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)

Write to TXxREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

TX/CK

Start bit

Word 2

bit 0

bit 1

bit 7/8

bit 0

Stop bit

Word 2

1 TCY

Word 1

TXxIF bit

(Transmit Buffer

Reg. Empty Flag)

1 TCY

Word 1

Transmit Shift Reg.

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

33.1.2

EUSART ASYNCHRONOUS

RECEIVER

33.1.2.2

Receiving Data

The receiver data recovery circuit initiates character

reception on the falling edge of the first bit. The first bit,

also known as the Start bit, is always a zero. The data

recovery circuit counts one-half bit time to the center of

the Start bit and verifies that the bit is still a zero. If it is

not a zero then the data recovery circuit aborts

character reception, without generating an error, and

resumes looking for the falling edge of the Start bit. If

the Start bit zero verification succeeds then the data

recovery circuit counts a full bit time to the center of the

next bit. The bit is then sampled by a majority detect

circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR.

This repeats until all data bits have been sampled and

shifted into the RSR. One final bit time is measured and

the level sampled. This is the Stop bit, which is always

a ‘1’. If the data recovery circuit samples a ‘0’ in the

Stop bit position then a framing error is set for this

character, otherwise the framing error is cleared for this

character. See Section 33.1.2.4 “Receive Framing

Error” for more information on framing errors.

The Asynchronous mode is typically used in RS-232

systems. The receiver block diagram is shown in

Figure 33-2. The data is received on the RX/DT pin and

drives the data recovery block. The data recovery block

is actually a high-speed shifter operating at 16 times

the baud rate, whereas the serial Receive Shift

Register (RSR) operates at the bit rate. When all eight

or nine bits of the character have been shifted in, they

are immediately transferred to a two character First-In-

First-Out (FIFO) memory. The FIFO buffering allows

reception of two complete characters and the start of a

third character before software must start servicing the

EUSART receiver. The FIFO and RSR registers are not

directly accessible by software. Access to the received

data is via the RCxREG register.

33.1.2.1

Enabling the Receiver

The EUSART receiver is enabled for asynchronous

operation by configuring the following three control bits:

Immediately after all data bits and the Stop bit have

been received, the character in the RSR is transferred

to the EUSART receive FIFO and the RXxIF interrupt

flag bit of the PIR3 register is set. The top character in

the FIFO is transferred out of the FIFO by reading the

RCxREG register.

• CREN = 1

• SYNC = 0

• SPEN = 1

All other EUSART control bits are assumed to be in

their default state.

Setting the CREN bit of the RCxSTA register enables

the receiver circuitry of the EUSART. Clearing the SYNC

bit of the TXxSTA register configures the EUSART for

asynchronous operation. Setting the SPEN bit of the

RCxSTA register enables the EUSART. The

programmer must set the corresponding TRIS bit to

configure the RX/DT I/O pin as an input.

Note:

If the receive FIFO is overrun, no additional

characters will be received until the overrun

condition is cleared. See Section 33.1.2.5

“Receive Overrun Error” for more

information on overrun errors.

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

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33.1.2.3

Receive Interrupts

33.1.2.6

Receiving 9-Bit Characters

The RXxIF interrupt flag bit of the PIR3 register is set

whenever the EUSART receiver is enabled and there is

an unread character in the receive FIFO. The RXxIF

interrupt flag bit is read-only, it cannot be set or cleared

by software.

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCxSTA register is set the EUSART

will shift nine bits into the RSR for each character

received. The RX9D bit of the RCxSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCxREG.

RXxIF interrupts are enabled by setting all of the

following bits:

• RXxIE, Interrupt Enable bit of the PIE3 register

• PEIE, Peripheral Interrupt Enable bit of the

INTCON register

33.1.2.7

Address Detection

• GIE, Global Interrupt Enable bit of the INTCON

register

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCxSTA

register.

The RXxIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RXxIF interrupt

bit. All other characters will be ignored.

33.1.2.4

Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCxSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCxREG.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCxSTA register which resets the EUSART.

Clearing the CREN bit of the RCxSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCxREG will not clear the FERR bit.

33.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCxSTA register is

set. The characters already in the FIFO buffer can be

read but no additional characters will be received until

the error is cleared. The error must be cleared by either

clearing the CREN bit of the RCxSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCxSTA register.

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33.1.2.8

Asynchronous Reception Setup:

33.1.2.9

9-bit Address Detection Mode Setup

1. Initialize the SPxBRGH, SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 33.3 “EUSART

Baud Rate Generator (BRG)”).

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

1. Initialize the SPxBRGH, SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 33.3 “EUSART

Baud Rate Generator (BRG)”).

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

2. Clear the ANSEL bit for the RX pin (if applicable).

4. If interrupts are desired, set the RXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

3. Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

5. If 9-bit reception is desired, set the RX9 bit.

6. Enable reception by setting the CREN bit.

4. If interrupts are desired, set the RXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

7. The RXxIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RXxIE interrupt enable bit was also set.

5. Enable 9-bit reception by setting the RX9 bit.

6. Enable address detection by setting the ADDEN

bit.

8. Read the RCxSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

7. Enable reception by setting the CREN bit.

8. The RXxIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RXxIE interrupt enable

bit was also set.

9. Get the received eight Least Significant data bits

from the receive buffer by reading the RCxREG

register.

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

9. Read the RCxSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received eight Least Significant data bits

from the receive buffer by reading the RCxREG

register. Software determines if this is the

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 33-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX/DT pin

bit 7/8

bit 0 bit 1

Stop

bit

Stop

bit

Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg.

Word 2

RCxREG

Word 1

RCxREG

RCIDL

Read Rcv

Buffer Reg.

RCxREG

RXxIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCxREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

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33.2 Clock Accuracy with

Asynchronous Operation

The factory calibrates the internal oscillator block

output (INTOSC). However, the HFINTOSC frequency

may drift as VDD or temperature changes, and this

directly affects the asynchronous baud rate. Two

methods may be used to adjust the baud rate clock, but

both require a reference clock source of some kind.

The first (preferred) method uses the OSCTUNE

register to adjust the HFINTOSC output. Adjusting the

value in the OSCTUNE register allows for fine resolution

changes to the system clock source. See

Section 9.2.2.2 “Internal Oscillator Frequency

Adjustment” for more information.

The other method adjusts the value in the Baud Rate

Generator. This can be done automatically with the

Auto-Baud Detect feature (see Section 33.3.1 “Auto-

Baud Detect”). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

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EXAMPLE 33-1:

CALCULATING BAUD

RATE ERROR

33.3 EUSART Baud Rate Generator

(BRG)

The Baud Rate Generator (BRG) is an 8-bit or 16-bit

timer that is dedicated to the support of both the

asynchronous and synchronous EUSART operation.

By default, the BRG operates in 8-bit mode. Setting the

BRG16 bit of the BAUDxCON register selects 16-bit

mode.

For a device with FOSC of 16 MHz, desired baud rate

of 9600, Asynchronous mode, 8-bit BRG:

FOSC

Desired Baud Rate = -----------------------------------------------------------------------

64[SPBRGH:SPBRGL] + 1

Solving for SPxBRGH:SPxBRGL:

FOSC

---------------------------------------------

Desired Baud Rate

X = --------------------------------------------- – 1

64

The SPxBRGH, SPxBRGL register pair determines the

period of the free running baud rate timer. In

Asynchronous mode the multiplier of the baud rate

period is determined by both the BRGH bit of the

TXxSTA register and the BRG16 bit of the BAUDxCON

register. In Synchronous mode, the BRGH bit is ignored.

16000000

-----------------------

9600

= ----------------------- – 1

64

= 25.042 = 25

Table 33-1 contains the formulas for determining the

baud rate. Example 33-1 provides a sample calculation

for determining the baud rate and baud rate error.

16000000

Calculated Baud Rate = --------------------------

6425 + 1

Typical baud rates and error values for various

Asynchronous modes have been computed for your

convenience and are shown in Table 33-3. It may be

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG (BRG16 = 1) to reduce the baud rate

error. The 16-bit BRG mode is used to achieve slow

baud rates for fast oscillator frequencies.

= 9615

Calc. Baud Rate – Desired Baud Rate

Error = --------------------------------------------------------------------------------------------

Desired Baud Rate

9615 – 9600

= ---------------------------------- = 0 . 1 6 %

9600

Writing a new value to the SPxBRGH, SPxBRGL

register pair causes the BRG timer to be reset (or

cleared). This ensures that the BRG does not wait for a

timer overflow before outputting the new baud rate.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit to

make sure that the receive operation is idle before

changing the system clock.

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8th the BRG base clock rate. The resulting byte

measurement is the average bit time when clocked at

full speed.

33.3.1

AUTO-BAUD DETECT

The EUSART module supports automatic detection

and calibration of the baud rate.

Note 1: If the WUE bit is set with the ABDEN bit,

auto-baud detection will occur on the byte

following the Break character (see

In the Auto-Baud Detect (ABD) mode, the clock to the

BRG is reversed. Rather than the BRG clocking the

incoming RX signal, the RX signal is timing the BRG.

The Baud Rate Generator is used to time the period of

a received 55h (ASCII “U”) which is the Sync character

for the LIN bus. The unique feature of this character is

that it has five rising edges including the Stop bit edge.

Section 33.3.3

“Auto-Wake-up

on

Break”).

2: It is up to the user to determine that the

incoming character baud rate is within the

range of the selected BRG clock source.

Some combinations of oscillator frequency

and EUSART baud rates are not possible.

Setting the ABDEN bit of the BAUDxCON register

starts the auto-baud calibration sequence. While the

ABD sequence takes place, the EUSART state

machine is held in Idle. On the first rising edge of the

receive line, after the Start bit, the SPxBRG begins

counting up using the BRG counter clock as shown in

Figure 33-6. The fifth rising edge will occur on the RX

pin at the end of the eighth bit period. At that time, an

accumulated value totaling the proper BRG period is

left in the SPxBRGH, SPxBRGL register pair, the

ABDEN bit is automatically cleared and the RXxIF

interrupt flag is set. The value in the RCxREG needs to

be read to clear the RXxIF interrupt. RCxREG content

should be discarded. When calibrating for modes that

do not use the SPxBRGH register the user can verify

that the SPxBRGL register did not overflow by

checking for 00h in the SPxBRGH register.

3: During the auto-baud process, the auto-

baud counter starts counting at one. Upon

completion of the auto-baud sequence, to

achieve maximum accuracy, subtract 1

from the SPxBRGH:SPxBRGL register

pair.

TABLE 33-1:

BRG16 BRGH

BRG COUNTER CLOCK RATES

BRG Base

Clock

BRG ABD

Clock

0

1

FOSC/64

FOSC/16

FOSC/512

FOSC/128

1

0

1

FOSC/16

FOSC/4

FOSC/128

FOSC/32

The BRG auto-baud clock is determined by the BRG16

and BRGH bits as shown in Table 33-1. During ABD,

both the SPxBRGH and SPxBRGL registers are used

as a 16-bit counter, independent of the BRG16 bit

setting. While calibrating the baud rate period, the

SPxBRGH and SPxBRGL registers are clocked at 1/

Note:

During the ABD sequence, SPxBRGL and

SPxBRGH registers are both used as a 16-

bit counter, independent of the BRG16

setting.

FIGURE 33-6:

AUTOMATIC BAUD RATE CALIBRATION

XXXXh

0000h

001Ch

BRG Value

Edge #5

Stop bit

Edge #1

bit 1

Edge #2

bit 3

Edge #3

bit 5

bit 4

Edge #4

bit 7

RX pin

Start

bit 0

bit 2

bit 6

BRG Clock

Auto Cleared

Set by User

ABDEN bit

RCIDL

RXxIF bit

(Interrupt)

Read

RCxREG

XXh

1Ch

00h

SPxBRGL

SPxBRGH

Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.

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33.3.2

AUTO-BAUD OVERFLOW

33.3.3.1

Special Considerations

During the course of automatic baud detection, the

ABDOVF bit of the BAUDxCON register will be set if the

baud rate counter overflows before the fifth rising edge

is detected on the RX pin. The ABDOVF bit indicates

that the counter has exceeded the maximum count that

can fit in the 16 bits of the SPxBRGH:SPxBRGL

register pair. The overflow condition will set the RXxIF

flag. The counter continues to count until the fifth rising

edge is detected on the RX pin. The RCIDL bit will

remain false (‘0’) until the fifth rising edge at which time

the RCIDL bit will be set. If the RCxREG is read after

the overflow occurs but before the fifth rising edge then

the fifth rising edge will set the RXxIF again.

Break Character

To avoid character errors or character fragments during

a wake-up event, the wake-up character must be all

zeros.

When the wake-up is enabled the function works

independent of the low time on the data stream. If the

WUE bit is set and a valid non-zero character is

received, the low time from the Start bit to the first rising

edge will be interpreted as the wake-up event. The

remaining bits in the character will be received as a

fragmented character and subsequent characters can

result in framing or overrun errors.

Therefore, the initial character in the transmission must

be all ‘0’s. This must be ten or more bit times, 13-bit

times recommended for LIN bus, or any number of bit

times for standard RS-232 devices.

Terminating the auto-baud process early to clear an

overflow condition will prevent proper detection of the

sync character fifth rising edge. If any falling edges of

the sync character have not yet occurred when the

ABDEN bit is cleared then those will be falsely detected

as Start bits. The following steps are recommended to

clear the overflow condition:

Oscillator Start-up Time

Oscillator start-up time must be considered, especially

in applications using oscillators with longer start-up

intervals (i.e., LP, XT or HS/PLL mode). The Sync

Break (or wake-up signal) character must be of

sufficient length, and be followed by a sufficient

interval, to allow enough time for the selected oscillator

to start and provide proper initialization of the EUSART.

1. Read RCxREG to clear RXxIF.

2. If RCIDL is ‘0’ then wait for RDCIF and repeat

step 1.

3. Clear the ABDOVF bit.

33.3.3

AUTO-WAKE-UP ON BREAK

WUE Bit

During Sleep mode, all clocks to the EUSART are

suspended. Because of this, the Baud Rate Generator

is inactive and a proper character reception cannot be

performed. The Auto-Wake-up feature allows the

controller to wake-up due to activity on the RX/DT line.

This feature is available only in Asynchronous mode.

The wake-up event causes a receive interrupt by

setting the RXxIF bit. The WUE bit is cleared in

hardware by a rising edge on RX/DT. The interrupt

condition is then cleared in software by reading the

RCxREG register and discarding its contents.

To ensure that no actual data is lost, check the RCIDL

bit to verify that a receive operation is not in process

before setting the WUE bit. If a receive operation is not

occurring, the WUE bit may then be set just prior to

entering the Sleep mode.

The Auto-Wake-up feature is enabled by setting the

WUE bit of the BAUDxCON register. Once set, the

normal receive sequence on RX/DT is disabled, and the

EUSART remains in an Idle state, monitoring for a wake-

up event independent of the CPU mode. A wake-up

event consists of a high-to-low transition on the RX/DT

line. (This coincides with the start of a Sync Break or a

wake-up signal character for the LIN protocol.)

The EUSART module generates an RXxIF interrupt

coincident with the wake-up event. The interrupt is

generated synchronously to the Q clocks in normal CPU

operating modes (Figure 33-7), and asynchronously if

the device is in Sleep mode (Figure 33-8). The interrupt

condition is cleared by reading the RCxREG register.

The WUE bit is automatically cleared by the low-to-high

transition on the RX line at the end of the Break. This

signals to the user that the Break event is over. At this

point, the EUSART module is in IDLE mode waiting to

receive the next character.

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FIGURE 33-7:

AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION

Q1 Q2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3Q4

OSC1

Auto Cleared

Bit set by user

WUE bit

RX/DT Line

RXxIF

Cleared due to User Read of RCxREG

Note 1: The EUSART remains in Idle while the WUE bit is set.

FIGURE 33-8:

AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP

Q4

Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3

Q1

Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4

Auto Cleared

OSC1

Bit Set by User

WUE bit

RX/DT Line

Note 1

RXxIF

Cleared due to User Read of RCxREG

Sleep Command Executed

Sleep Ends

Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposcsignal is

still active. This sequence should not depend on the presence of Q clocks.

2: The EUSART remains in Idle while the WUE bit is set.

33.3.4

BREAK CHARACTER SEQUENCE

33.3.4.1

Break and Sync Transmit Sequence

The EUSART module has the capability of sending the

special Break character sequences that are required by

the LIN bus standard. A Break character consists of a

Start bit, followed by 12 ‘0’ bits and a Stop bit.

The following sequence will start a message frame

header made up of a Break, followed by an auto-baud

Sync byte. This sequence is typical of a LIN bus

master.

To send a Break character, set the SENDB and TXEN

bits of the TXxSTA register. The Break character

transmission is then initiated by a write to the TXxREG.

The value of data written to TXxREG will be ignored

and all ‘0’s will be transmitted.

1. Configure the EUSART for the desired mode.

2. Set the TXEN and SENDB bits to enable the

Break sequence.

3. Load the TXxREG with a dummy character to

initiate transmission (the value is ignored).

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN specification).

4. Write ‘55h’ to TXxREG to load the Sync

character into the transmit FIFO buffer.

5. After the Break has been sent, the SENDB bit is

reset by hardware and the Sync character is

then transmitted.

The TRMT bit of the TXxSTA register indicates when the

transmit operation is active or idle, just as it does during

normal transmission. See Figure 33-9 for the timing of

the Break character sequence.

When the TXxREG becomes empty, as indicated by

the TXxIF, the next data byte can be written to TXxREG.

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33.3.5

RECEIVING A BREAK CHARACTER

The Enhanced EUSART module can receive a Break

character in two ways.

The first method to detect a Break character uses the

FERR bit of the RCxSTA register and the received data

as indicated by RCxREG. The Baud Rate Generator is

assumed to have been initialized to the expected baud

rate.

A Break character has been received when:

• RXxIF bit is set

• FERR bit is set

• RCxREG = 00h

The second method uses the Auto-Wake-up feature

described in Section 33.3.3 “Auto-Wake-up on

Break”. By enabling this feature, the EUSART will

sample the next two transitions on RX/DT, cause an

RXxIF interrupt, and receive the next data byte fol-

lowed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Detect feature.

For both methods, the user can set the ABDEN bit of

the BAUDxCON register before placing the EUSART in

Sleep mode.

FIGURE 33-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXxREG

Dummy Write

BRG Output

(Shift Clock)

TX (pin)

Start bit

bit 0

bit 1

Break

bit 11

Stop bit

TXxIF bit

(Transmit

Interrupt Flag)

TRMT bit

(Transmit Shift

Empty Flag)

SENDB Sampled Here

Auto Cleared

SENDB

(send Break

control bit)

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33.4.1.2

Clock Polarity

33.4 EUSART Synchronous Mode

A clock polarity option is provided for Microwire

compatibility. Clock polarity is selected with the SCKP

bit of the BAUDxCON register. Setting the SCKP bit

sets the clock Idle state as high. When the SCKP bit is

set, the data changes on the falling edge of each clock.

Clearing the SCKP bit sets the Idle state as low. When

the SCKP bit is cleared, the data changes on the rising

edge of each clock.

Synchronous serial communications are typically used

in systems with a single master and one or more

slaves. The master device contains the necessary

circuitry for baud rate generation and supplies the clock

for all devices in the system. Slave devices can take

advantage of the master clock by eliminating the

internal clock generation circuitry.

There are two signal lines in Synchronous mode: a

bidirectional data line and a clock line. Slaves use the

external clock supplied by the master to shift the serial

data into and out of their respective receive and trans-

mit shift registers. Since the data line is bidirectional,

synchronous operation is half-duplex only. Half-duplex

refers to the fact that master and slave devices can

receive and transmit data but not both simultaneously.

The EUSART can operate as either a master or slave

device.

33.4.1.3

Synchronous Master Transmission

Data is transferred out of the device on the RX/DT pin.

The RX/DT and TX/CK pin output drivers are automat-

ically enabled when the EUSART is configured for

synchronous master transmit operation.

A transmission is initiated by writing a character to the

TXxREG register. If the TSR still contains all or part of

a previous character the new character data is held in

the TXxREG until the last bit of the previous character

has been transmitted. If this is the first character, or the

previous character has been completely flushed from

the TSR, the data in the TXxREG is immediately trans-

ferred to the TSR. The transmission of the character

commences immediately following the transfer of the

data to the TSR from the TXxREG.

Start and Stop bits are not used in synchronous

transmissions.

33.4.1

SYNCHRONOUS MASTER MODE

The following bits are used to configure the EUSART

for synchronous master operation:

• SYNC = 1

Each data bit changes on the leading edge of the

master clock and remains valid until the subsequent

leading clock edge.

• CSRC = 1

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

Setting the SYNC bit of the TXxSTA register configures

the device for synchronous operation. Setting the CSRC

bit of the TXxSTA register configures the device as a

master. Clearing the SREN and CREN bits of the

RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured

to receive. Setting the SPEN bit of the RCxSTA register

enables the EUSART.

33.4.1.4

Synchronous Master Transmission

Set-up:

1. Initialize the SPxBRGH, SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 33.3 “EUSART

Baud Rate Generator (BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

33.4.1.1

Master Clock

3. Disable Receive mode by clearing bits SREN

and CREN.

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device config-

ured as a master transmits the clock on the TX/CK line.

The TX/CK pin output driver is automatically enabled

when the EUSART is configured for synchronous

transmit or receive operation. Serial data bits change

on the leading edge to ensure they are valid at the

trailing edge of each clock. One clock cycle is gener-

ated for each data bit. Only as many clock cycles are

generated as there are data bits.

4. Enable Transmit mode by setting the TXEN bit.

5. If 9-bit transmission is desired, set the TX9 bit.

6. If interrupts are desired, set the TXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

7. If 9-bit transmission is selected, the ninth bit

should be loaded in the TX9D bit.

8. Start transmission by loading data to the

TXxREG register.

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FIGURE 33-10:

SYNCHRONOUS TRANSMISSION

RX/DT

bit 0

bit 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

Word 1

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

TXxREG Reg

Write Word 1

Write Word 2

TXxIF bit

(Interrupt Flag)

TRMT bit

‘1’

TXEN bit

Note:

Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.

FIGURE 33-11:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RX/DT pin

bit 0

bit 2

bit 1

bit 6

bit 7

TX/CK pin

Write to

TXxREG reg

TXxIF bit

TRMT bit

TXEN bit

To initiate reception, set either SREN or CREN. Data is

sampled at the RX/DT pin on the trailing edge of the

TX/CK clock pin and is shifted into the Receive Shift

Register (RSR). When a complete character is

received into the RSR, the RXxIF bit is set and the

character is automatically transferred to the two char-

acter receive FIFO. The Least Significant eight bits of

the top character in the receive FIFO are available in

RCxREG. The RXxIF bit remains set as long as there

are unread characters in the receive FIFO.

33.4.1.5

Synchronous Master Reception

Data is received at the RX/DT pin. The RX/DT pin

output driver is automatically disabled when the

EUSART is configured for synchronous master receive

operation.

In Synchronous mode, reception is enabled by setting

either the Single Receive Enable bit (SREN of the

RCxSTA register) or the Continuous Receive Enable

bit (CREN of the RCxSTA register).

When SREN is set and CREN is clear, only as many

clock cycles are generated as there are data bits in a

single character. The SREN bit is automatically cleared

at the completion of one character. When CREN is set,

clocks are continuously generated until CREN is

cleared. If CREN is cleared in the middle of a character

the CK clock stops immediately and the partial charac-

ter is discarded. If SREN and CREN are both set, then

SREN is cleared at the completion of the first character

and CREN takes precedence.

Note:

If the RX/DT function is on an analog pin,

the corresponding ANSEL bit must be

cleared for the receiver to function.

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received. The RX9D bit of the RCxSTA register is the

ninth, and Most Significant, data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the eight Least Significant bits

from the RCxREG.

33.4.1.6

Slave Clock

Synchronous data transfers use a separate clock line,

which is synchronous with the data. A device configured

as a slave receives the clock on the TX/CK line. The TX/

CK pin output driver is automatically disabled when the

device is configured for synchronous slave transmit or

receive operation. Serial data bits change on the leading

edge to ensure they are valid at the trailing edge of each

clock. One data bit is transferred for each clock cycle.

Only as many clock cycles should be received as there

are data bits.

33.4.1.9

Synchronous Master Reception Set-

up:

1. Initialize the SPxBRGH, SPxBRGL register pair

for the appropriate baud rate. Set or clear the

BRGH and BRG16 bits, as required, to achieve

the desired baud rate.

Note:

If the device is configured as a slave and

the TX/CK function is on an analog pin, the

corresponding ANSEL bit must be cleared.

2. Clear the ANSEL bit for the RX pin (if applicable).

3. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

33.4.1.7

Receive Overrun Error

4. Ensure bits CREN and SREN are clear.

The receive FIFO buffer can hold two characters. An

overrun error will be generated if a third character, in its

entirety, is received before RCxREG is read to access

the FIFO. When this happens the OERR bit of the

RCxSTA register is set. Previous data in the FIFO will

not be overwritten. The two characters in the FIFO

buffer can be read, however, no additional characters

will be received until the error is cleared. The OERR bit

can only be cleared by clearing the overrun condition.

If the overrun error occurred when the SREN bit is set

and CREN is clear then the error is cleared by reading

RCxREG. If the overrun occurred when the CREN bit is

set then the error condition is cleared by either clearing

the CREN bit of the RCxSTA register or by clearing the

SPEN bit which resets the EUSART.

5. If interrupts are desired, set the RXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

6. If 9-bit reception is desired, set bit RX9.

7. Start reception by setting the SREN bit or for

continuous reception, set the CREN bit.

8. Interrupt flag bit RXxIF will be set when recep-

tion of a character is complete. An interrupt will

be generated if the enable bit RXxIE was set.

9. Read the RCxSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

10. Read the 8-bit received data by reading the

RCxREG register.

11. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCxSTA

register or by clearing the SPEN bit which resets

the EUSART.

33.4.1.8

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCxSTA register is set the EUSART

will shift nine bits into the RSR for each character

FIGURE 33-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 0)

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

‘0’

CREN bit

RXxIF bit

(Interrupt)

Read

RCxREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRGH = 0.

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33.4.2

SYNCHRONOUS SLAVE MODE

33.4.2.1

EUSART Synchronous Slave

Transmit

The following bits are used to configure the EUSART

for synchronous slave operation:

The operation of the Synchronous Master and Slave

modes

are

identical

(see

Section 33.4.1.3

• SYNC = 1

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

• CSRC = 0

• SREN = 0(for transmit); SREN = 1(for receive)

• CREN = 0(for transmit); CREN = 1(for receive)

• SPEN = 1

If two words are written to the TXxREG and then the

SLEEPinstruction is executed, the following will occur:

1. The first character will immediately transfer to

the TSR register and transmit.

Setting the SYNC bit of the TXxSTA register configures

the device for synchronous operation. Clearing the

CSRC bit of the TXxSTA register configures the device as

a slave. Clearing the SREN and CREN bits of the

RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to

receive. Setting the SPEN bit of the RCxSTA register

enables the EUSART.

2. The second word will remain in the TXxREG

register.

3. The TXxIF bit will not be set.

4. After the first character has been shifted out of

TSR, the TXxREG register will transfer the

second character to the TSR and the TXxIF bit

will now be set.

5. If the PEIE and TXxIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

33.4.2.2

Synchronous Slave Transmission

Set-up:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for the CK pin (if applicable).

3. Clear the CREN and SREN bits.

4. If interrupts are desired, set the TXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

5. If 9-bit transmission is desired, set the TX9 bit.

6. Enable transmission by setting the TXEN bit.

7. If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

8. Start transmission by writing the Least

Significant eight bits to the TXxREG register.

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33.4.2.3

EUSART Synchronous Slave

Reception

33.4.2.4

Synchronous Slave Reception Set-

up:

The operation of the Synchronous Master and Slave

modes is identical (Section 33.4.1.5 “Synchronous

Master Reception”), with the following exceptions:

1. Set the SYNC and SPEN bits and clear the

CSRC bit.

2. Clear the ANSEL bit for both the CK and DT pins

(if applicable).

• Sleep

3. If interrupts are desired, set the RXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

• CREN bit is always set, therefore the receiver is

never idle

• SREN bit, which is a “don’t care” in Slave mode

4. If 9-bit reception is desired, set the RX9 bit.

5. Set the CREN bit to enable reception.

A character may be received while in Sleep mode by

setting the CREN bit prior to entering Sleep. Once the

word is received, the RSR register will transfer the data

to the RCxREG register. If the RXxIE enable bit is set,

the interrupt generated will wake the device from Sleep

and execute the next instruction. If the GIE bit is also

set, the program will branch to the interrupt vector.

6. The RXxIF bit will be set when reception is

complete. An interrupt will be generated if the

RXxIE bit was set.

7. If 9-bit mode is enabled, retrieve the Most

Significant bit from the RX9D bit of the RCxSTA

register.

8. Retrieve the eight Least Significant bits from the

receive FIFO by reading the RCxREG register.

9. If an overrun error occurs, clear the error by

either clearing the CREN bit of the RCxSTA

register or by clearing the SPEN bit which resets

the EUSART.

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33.5.2

SYNCHRONOUS TRANSMIT

DURING SLEEP

33.5 EUSART Operation During Sleep

The EUSART will remain active during Sleep only in the

Synchronous Slave mode. All other modes require the

system clock and therefore cannot generate the neces-

sary signals to run the Transmit or Receive Shift

registers during Sleep.

To transmit during Sleep, all the following conditions

must be met before entering Sleep mode:

• The RCxSTA and TXxSTA Control registers must

be configured for synchronous slave transmission

(see Section 33.4.2.2 “Synchronous Slave

Transmission Set-up:”).

Synchronous Slave mode uses an externally generated

clock to run the Transmit and Receive Shift registers.

• The TXxIF interrupt flag must be cleared by writ-

ing the output data to the TXxREG, thereby filling

the TSR and transmit buffer.

33.5.1

SYNCHRONOUS RECEIVE DURING

SLEEP

• If interrupts are desired, set the TXxIE bit of the

PIE3 register and the PEIE bit of the INTCON

register.

To receive during Sleep, all the following conditions

must be met before entering Sleep mode:

• RCxSTA and TXxSTA Control registers must be

configured for Synchronous Slave Reception (see

Section 33.4.2.4 “Synchronous Slave

Reception Set-up:”).

• Interrupt enable bits TXxIE of the PIE3 register

and PEIE of the INTCON register must set.

Upon entering Sleep mode, the device will be ready to

accept clocks on TX/CK pin and transmit data on the

RX/DT pin. When the data word in the TSR has been

completely clocked out by the external device, the

pending byte in the TXxREG will transfer to the TSR

and the TXxIF flag will be set. Thereby, waking the

processor from Sleep. At this point, the TXxREG is

available to accept another character for transmission,

which will clear the TXxIF flag.

• If interrupts are desired, set the RXxIE bit of the

PIE3 register and the GIE and PEIE bits of the

INTCON register.

• The RXxIF interrupt flag must be cleared by read-

ing RCxREG to unload any pending characters in

the receive buffer.

Upon entering Sleep mode, the device will be ready to

accept data and clocks on the RX/DT and TX/CK pins,

respectively. When the data word has been completely

clocked in by the external device, the RXxIF interrupt

flag bit of the PIR3 register will be set. Thereby, waking

the processor from Sleep.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit is also set then the Interrupt

Service Routine at address 0004h will be called.

Upon waking from Sleep, the instruction following the

SLEEP instruction will be executed. If the Global

Interrupt Enable (GIE) bit of the INTCON register is

also set, then the Interrupt Service Routine at address

004h will be called.

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33.6 Register Definitions: EUSART Control

REGISTER 33-1: TXxSTA: TRANSMIT STATUS AND CONTROL REGISTER

R/W-/0

CSRC

R/W-0/0

TX9

R/W-0/0

TXEN⁽¹⁾

R/W-0/0

SYNC

R/W-0/0

SENDB

R/W-0/0

BRGH

R-1/1

R/W-0/0

TX9D

TRMT

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Unused in this mode – value ignored

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

bit 4

bit 3

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit⁽¹⁾

1= Transmit enabled

0= Transmit disabled

SYNC: EUSART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

SENDB: Send Break Character bit

Asynchronous mode:

1= Send SYNCH BREAK on next transmission – Start bit, followed by 12 ‘0’ bits, followed by Stop

bit; cleared by hardware upon completion

0= SYNCH BREAK transmission disabled or completed

Synchronous mode:

Unused in this mode – value ignored

bit 2

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode – value ignored

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: Ninth bit of Transmit Data

Can be address/data bit or a parity bit.

Note 1: SREN/CREN overrides TXEN in Sync mode.

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REGISTER 33-2: RCxSTA: RECEIVE STATUS AND CONTROL REGISTER

R/W-0/0

SPEN⁽¹⁾

R/W-0/0

RX9

R/W-0/0

SREN

R/W-0/0

CREN

R/W-0/0

ADDEN

R-0/0

RX9D

FERR

OERR

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

bit 5

SPEN: Serial Port Enable bit⁽¹⁾

1= Serial port enabled

0= Serial port disabled (held in Reset)

RX9: 9-Bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Unused in this mode – value ignored

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete.

Synchronous mode – Slave

Unused in this mode – value ignored

CREN: Continuous Receive Enable bit

Asynchronous mode:

bit 4

1= Enables continuous receive until enable bit CREN is cleared

0= Disables continuous receive

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection – enable interrupt and load of the receive buffer when the ninth bit in

the receive buffer is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

Asynchronous mode 8-bit (RX9 = 0):

Unused in this mode – value ignored

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCxREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: Ninth bit of Received Data

This can be address/data bit or a parity bit and must be calculated by user firmware.

Note 1: The EUSART module automatically changes the pin from tri-state to drive as needed. Configure the

associated TRIS bits for TX/CK and RX/DT to 1.

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REGISTER 33-3: BAUDxCON: BAUD RATE CONTROL REGISTER

R/W-0/0

R-1/1

U-0

—

R/W-0/0

SCKP

R/W-0/0

BRG16

U-0

—

R/W-0/0

WUE

R/W-0/0

ABDEN

ABDOVF

RCIDL

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

bit 6

ABDOVF: Auto-Baud Detect Overflow bit

Asynchronous mode:

1= Auto-baud timer overflowed

0= Auto-baud timer did not overflow

Synchronous mode:

Don’t care

RCIDL: Receive Idle Flag bit

Asynchronous mode:

1= Receiver is Idle

0= Start bit has been received and the receiver is receiving

Synchronous mode:

Don’t care

bit 5

bit 4

Unimplemented: Read as ‘0’

SCKP: Clock/Transmit Polarity Select bit

Asynchronous mode:

1= Idle state for transmit (TX) is a low level

0= Idle state for transmit (TX) is a high level

Synchronous mode:

1= Idle state for clock (CK) is a high level

0= Idle state for clock (CK) is a low level

bit 3

BRG16: 16-bit Baud Rate Generator bit

1= 16-bit Baud Rate Generator is used

0= 8-bit Baud Rate Generator is used

bit 2

bit 1

Unimplemented: Read as ‘0’

WUE: Wake-up Enable bit

Asynchronous mode:

1= USART will continue to sample the Rx pin – interrupt generated on falling edge; bit cleared in

hardware on following rising edge.

0= RX pin not monitored nor rising edge detected

Synchronous mode:

Unused in this mode – value ignored

ABDEN: Auto-Baud Detect Enable bit

Asynchronous mode:

bit 0

1= Enable baud rate measurement on the next character – requires reception of a SYNCH field

(55h);

cleared in hardware upon completion

0= Baud rate measurement disabled or completed

Synchronous mode:

Unused in this mode – value ignored

 2016-2017 Microchip Technology Inc.

DS40001853C-page 444

PIC16(L)F15354/55

REGISTER 33-4: RCxREG⁽¹⁾: RECEIVE DATA REGISTER

R-0

RCxREG<7:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-0

RCxREG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-2)

Note 1: RCxREG (including the 9^thbit) is double buffered, and data is available while new data is being received.

REGISTER 33-5: TXxREG⁽¹⁾: TRANSMIT DATA REGISTER

R/W-0

bit 0

TXxREG<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

TXxREG<7:0>: Lower eight bits of the received data; read-only; see also RX9D (Register 33-1)

Note 1: TXxREG (including the 9th bit) is double buffered, and can be written when previous data has started

shifting.

REGISTER 33-6: SPxBRGL⁽¹⁾: BAUD RATE GENERATOR REGISTER

R/W-0

bit 0

SPxBRG<7:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7-0

SPxBRG<7:0>: Lower eight bits of the Baud Rate Generator

Note 1: Writing to SP1BRG resets the BRG counter.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 445

PIC16(L)F15354/55

REGISTER 33-7: SPxBRGH^{(1, 2)}: BAUD RATE GENERATOR HIGH REGISTER

R/W-0

bit 0

SPxBRG<15:8>

bit 7

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

u = Bit is unchanged

‘1’ = Bit is set

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

SPxBRG<15:8>: Upper eight bits of the Baud Rate Generator

Note 1: SPxBRGH value is ignored for all modes unless BAUDxCON<BRG16> is active.

2: Writing to SPxBRGH resets the BRG counter.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 446

PIC16(L)F15354/55

TABLE 33-2: SUMMARY OF REGISTERS ASSOCIATED WITH EUSART

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

PIE3

GIE

PEIE

―

INTEDG

SSP1IE

121

125

RC2IE

TX2IE

RC1IE

TX1IE

BCL2IE

SSP2IE

BCL1IE

PIR3

RC2IF

TX2IF

RC1IF

TX1IF

BCL2IF

SSP2IF

BCL1IF

SSP1IF

133

443

442

444

445*

446*

199

200

364

RCxSTA

TXxSTA

SPEN

CSRC

RX9

TX9

SREN

TXEN

―

CREN

SYNC

SCKP

ADDEN

SENDB

BRG16

FERR

BRGH

―

OERR

TRMT

WUE

RX9D

TX9D

BAUDxCON

RCxREG

TXxREG

SPxBRGL

SPxBRGH

RXPPS

ABDOVF

RCIDL

ABDEN

EUSART Receive Data Register

EUSART Transmit Data Register

SPxBRG<7:0>

SPxBRG<15:8>

RXPPS<5:0>

CXPPS<5:0>

RxyPPS<4:0>

LCxDyS<5:0>

―

CKPPS

RxyPPS

―

CLCxSELy

Legend:

— = unimplemented location, read as ‘0’. Shaded cells are not used for the EUSART module.

*

Page with register information.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 447

PIC16(L)F15354/55

TABLE 33-3: BAUD RATE FORMULAS

Configuration Bits

Baud Rate Formula

BRG/EUSART Mode

SYNC

BRG16

BRGH

0

1

0

1

0

1

0

1

0

1

x

8-bit/Asynchronous

16-bit/Asynchronous

8-bit/Synchronous

16-bit/Synchronous

FOSC/[64 (n+1)]

FOSC/[16 (n+1)]

FOSC/[4 (n+1)]

Legend:

x= Don’t care, n = value of SPxBRGH, SPxBRGL register pair.

TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 32.000 MHz

FOSC = 20.000 MHz

FOSC = 18.432 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

—

255

129

32

—

239

119

29

—

143

71

17

16

8

—

1221

2404

9470

10417

19.53k

1.73

0.16

-1.36

0.00

1.73

1200

2400

9600

10286

19.20k

0.00

-1.26

0.00

—

1200

2400

9600

10165

19.20k

0.00

-2.42

0.00

—

2400

2404

9615

10417

19.23k

0.16

0.00

0.16

207

51

47

25

9600

10417

19.2k

57.6k

115.2k

29

27

15

14

2

55.55k

—

-3.55

—

3

—

57.60k

—

7

57.60k

—

SYNC = 0, BRGH = 0, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

0.00

—

300

1200

—

1202

2404

9615

10417

—

0.16

0.00

—

103

51

12

11

300

1202

2404

—

0.16

—

207

51

25

—

5

300

1200

2400

9600

—

191

47

23

5

300

1202

—

0.16

—

51

12

—

2400

9600

—

10417

19.2k

57.6k

115.2k

10417

—

0.00

—

2

—

19.20k

0.00

—

0

—

57.60k

—

 2016-2017 Microchip Technology Inc.

DS40001853C-page 448

PIC16(L)F15354/55

TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

2400

9600

10417

19.2k

57.6k

—

71

65

35

11

5

9615

10417

19.23k

57.14k

0.16

0.00

0.16

-0.79

2.12

207

191

103

34

9615

10417

19.23k

56.82k

0.16

0.00

0.16

-1.36

129

119

64

9600

10378

19.20k

57.60k

115.2k

0.00

-0.37

0.00

119

110

59

19

9

9600

0.00

0.53

0.00

10473

19.20k

57.60k

115.2k

21

115.2k 117.64k

16

113.64k -1.36

10

SYNC = 0, BRGH = 1, BRG16 = 0

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

—

300

1200

—

1202

2404

9615

10417

19.23k

—

207

103

25

—

191

95

23

21

11

3

300

1202

2404

—

0.16

—

207

51

25

—

5

0.16

0.00

0.16

—

1200

0.00

0.53

0.00

2400

2404

9615

10417

19231

55556

—

0.16

0.00

0.16

-3.55

—

207

51

47

25

8

2400

9600

10417

19.2k

57.6k

115.2k

23

10473

19.2k

57.60k

115.2k

10417

—

0.00

—

12

—

1

—

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

2400

9600

10417

19.2k

57.6k

300.0

1200

0.00

-0.02

-0.04

0.16

0.00

0.16

-0.79

6666

3332

832

207

191

103

34

300.0

1200

-0.01

-0.03

0.16

0.00

0.16

-1.36

4166

1041

520

129

119

64

300.0

1200

0.00

-0.37

0.00

3839

959

479

119

110

59

300.0

1200

0.00

0.53

0.00

2303

575

287

71

2401

2399

2400

9615

9600

10417

19.23k

57.14k

10417

19.23k

56.818

10378

19.20k

57.60k

10473

19.20k

57.60k

65

35

21

19

11

115.2k

117.6k

2.12

16

113.636 -1.36

10

115.2k

0.00

9

115.2k

0.00

5

 2016-2017 Microchip Technology Inc.

DS40001853C-page 449

PIC16(L)F15354/55

TABLE 33-4: BAUD RATE FOR ASYNCHRONOUS MODES (CONTINUED)

SYNC = 0, BRGH = 0, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

value

SPBRG

value

SPBRG

Actual

Rate

%

Actual

Rate

%

Error

Actual

Rate

%

Error

Actual

Rate

%

value

(decimal)

value

(decimal)

Error

(decimal)

300

1200

299.9

1199

-0.02

-0.08

0.16

0.00

0.16

-3.55

—

1666

416

207

51

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

300.0

1200

0.00

0.53

0.00

767

191

95

23

21

11

3

300.5

1202

2404

—

0.16

—

207

51

25

—

5

2400

2404

9615

10417

19.23k

55556

—

2400

9600

10417

19.2k

57.6k

115.2k

47

23

10473

19.20k

57.60k

115.2k

10417

—

0.00

—

25

12

—

8

—

1

—

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

FOSC = 20.000 MHz FOSC = 18.432 MHz

FOSC = 32.000 MHz

FOSC = 11.0592 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

0.01

0.04

0.00

-0.08

0.64

26666

6666

3332

832

300.0

1200

0.00

-0.01

0.02

-0.03

0.00

0.16

-0.22

0.94

16665

4166

2082

520

479

259

86

300.0

1200

0.00

0.08

0.00

15359

3839

1919

479

441

239

79

300.0

1200

0.00

0.16

0.00

9215

2303

1151

287

264

143

47

2400

9600

9604

9597

9600

10417

19.2k

57.6k

115.2k

10417

19.18k

57.55k

115.9k

767

10417

19.23k

57.47k

116.3k

10425

19.20k

57.60k

115.2k

10433

19.20k

57.60k

115.2k

416

138

68

42

39

23

SYNC = 0, BRGH = 1, BRG16 = 1or SYNC = 1, BRG16 = 1

FOSC = 4.000 MHz FOSC = 3.6864 MHz

FOSC = 8.000 MHz

FOSC = 1.000 MHz

BAUD

RATE

SPBRG

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

Actual

Rate

%

value

(decimal)

value

(decimal)

value

(decimal)

value

(decimal)

Error

300

1200

300.0

1200

0.00

-0.02

0.04

0.16

0

6666

1666

832

207

191

103

34

300.0

1200

0.01

0.04

0.08

0.16

0.00

0.16

2.12

-3.55

3332

832

416

103

95

300.0

1200

0.00

0.53

0.00

3071

767

383

95

300.1

1202

2404

9615

10417

19.23k

—

0.04

0.16

0.00

0.16

—

832

207

103

25

2400

2401

2398

2400

9600

9615

9600

10417

19.2k

57.6k

115.2k

10417

19.23k

57.14k

117.6k

10417

19.23k

58.82k

111.1k

10473

19.20k

57.60k

115.2k

87

23

0.16

-0.79

2.12

51

47

12

16

15

—

16

8

7

—

 2016-2017 Microchip Technology Inc.

DS40001853C-page 450

PIC16(L)F15354/55

34.3 SELECTABLE DUTY CYCLE

34.0 REFERENCE CLOCK OUTPUT

MODULE

The CLKRDC<1:0> bits of the CLKRCON register can

be used to modify the duty cycle of the output clock. A

duty cycle of 25%, 50%, or 75% can be selected for all

clock rates, with the exception of the undivided base

FOSC value.

The reference clock output module provides the ability

to send a clock signal to the clock reference output pin

(CLKR).

The reference clock output module has the following

features:

The duty cycle can be changed while the module is

enabled; however, in order to prevent glitches on the

output, the CLKRDC<1:0> bits should only be changed

when the module is disabled (CLKREN = 0).

• Selectable input clock

• Programmable clock divider

• Selectable duty cycle

Note:

The CLKRDC1 bit is reset to ‘1’. This

makes the default duty cycle 50% and not

0%.

34.1 CLOCK SOURCE

The reference clock output module has a selectable

clock source. The CLKRCLK register (Register 34-2)

controls which input is used.

34.4 OPERATION IN SLEEP MODE

34.1.1

CLOCK SYNCHRONIZATION

The reference clock output module clock is based on

the system clock. When the device goes to Sleep, the

module outputs will remain in their current state. This

will have a direct effect on peripherals using the

reference clock output as an input signal.

Once the reference clock enable (CLKREN) is set, the

module is ensured to be glitch-free at start-up.

When the reference clock output is disabled, the output

signal will be disabled immediately.

Clock dividers and clock duty cycles can be changed

while the module is enabled, but glitches may occur on

the output. To avoid possible glitches, clock dividers

and clock duty cycles should be changed only when the

CLKREN is clear.

34.2 PROGRAMMABLE CLOCK

DIVIDER

The module takes the system clock input and divides it

based on the value of the CLKRDIV<2:0> bits of the

CLKRCON register (Register 34-1).

The following configurations can be made based on the

CLKRDIV<2:0> bits:

• Base clock value

• Base clock value divided by 2

• Base clock value divided by 4

• Base clock value divided by 8

• Base clock value divided by 16

• Base clock value divided by 32

• Base clock value divided by 64

• Base clock value divided by 128

The clock divider values can be changed while the

module is enabled; however, in order to prevent

glitches on the output, the CLKRDIV<2:0> bits should

only be changed when the module is disabled

(CLKREN = 0).

 2016-2017 Microchip Technology Inc.

DS40001853C-page 451

PIC16(L)F15354/55

FIGURE 34-1:

CLOCK REFERENCE BLOCK DIAGRAM

Rev. 10-000261A

9/10/2015

CLKRDIV<2:0>

Counter Reset

CLKREN

128

64

32

16

8

111

110

101

100

011

010

001

000

CLKRDC<1:0>

Duty Cycle

See

CLKRCLK

Register

CLKR

PPS

4

2

To Peripherals

D

Q

CLKREN

CLKRCLK<3:0>

FREEZE ENABLED⁽¹⁾

EN

ICD FREEZE MODE⁽¹⁾

FIGURE 34-2:

CLOCK REFERENCE TIMING

P2

P1

F_OSC

CLKREN

CLKR Output

CLKRDIV[2:0] = 001

CLKRDC[1:0] = 10

Duty Cycle

(50%)

F_OSC/ 2

CLKR Output

CLKRDIV[2:0] = 001

CLKRDC[1:0] = 01

Duty Cycle (25%)

 2016-2017 Microchip Technology Inc.

DS40001853C-page 452

PIC16(L)F15354/55

34.5 Register Definition: Reference Clock Output Control

REGISTER 34-1: CLKRCON: REFERENCE CLOCK CONTROL REGISTER

R/W-0/0

U-0

R/W-0/0

CLKREN

—

CLKRDC<1:0>

CLKRDIV<2:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

x = Bit is unknown

‘0’ = Bit is cleared

bit 7

CLKREN: Reference Clock Module Enable bit

1= Reference clock module enabled

0= Reference clock module is disabled

bit 6-5

bit 4-3

Unimplemented: Read as ‘0’

CLKRDC<1:0>: Reference Clock Duty Cycle bits ⁽¹⁾

11= Clock outputs duty cycle of 75%

10= Clock outputs duty cycle of 50%

01= Clock outputs duty cycle of 25%

00= Clock outputs duty cycle of 0%

bit 2-0

CLKRDIV<2:0>: Reference Clock Divider bits

111= Base clock value divided by 128

110= Base clock value divided by 64

101= Base clock value divided by 32

100= Base clock value divided by 16

011= Base clock value divided by 8

010= Base clock value divided by 4

001= Base clock value divided by 2

000= Base clock value

Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 453

PIC16(L)F15354/55

REGISTER 34-2: CLKRCLK: CLOCK REFERENCE CLOCK SELECTION REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0/0

CLKRCLK<3:0>

bit 7

bit 0

Legend:

R = Readable bit

u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit

x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

CLKRCLK<3:0>: CLKR Input bits

Clock Selection

1111= Reserved

•

1011= Reserved

1010= LC4_out

1001= LC3_out

1000= LC2_out

0111= LC1_out

0110= NCO1_out

0101= SOSC

0100= MFINTOSC (31.25 kHz)

0011= MFINTOSC (500 kHz)

0010= LFINTOSC

0001= HFINTOSC

0000= FOSC

TABLE 34-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK REFERENCE OUTPUT

Register

on Page

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

CLKRCON

CLKRCLK

CLCxSELy

RxyPPS

CLKREN

—

CLKRDC<1:0>

—

CLKRDIV<2:0>

453

454

364

200

—

CLKRCLK<3:0>

LCxDyS<5:0>

RxyPPS<4:0>

—

Legend:

— = unimplemented, read as ‘0’. Shaded cells are not used by the CLKR module.

 2016-2017 Microchip Technology Inc.

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35.3 Common Programming Interfaces

35.0 IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

Connection to a target device is typically done through

an ICSP™ header. A commonly found connector on

development tools is the RJ-11 in the 6P6C (6-pin, 6-

connector) configuration. See Figure 35-1.

ICSP™ programming allows customers to manufacture

circuit boards with unprogrammed devices. Programming

can be done after the assembly process, allowing the

device to be programmed with the most recent firmware

or a custom firmware. Five pins are needed for ICSP™

programming:

FIGURE 35-1:

ICD RJ-11 STYLE

CONNECTOR INTERFACE

• ICSPCLK

• ICSPDAT

• MCLR/VPP

• VDD

ICSPDAT

• VSS

NC

2 4 6

VDD

In Program/Verify mode the program memory, User IDs

and the Configuration Words are programmed through

serial communications. The ICSPDAT pin is

bidirectional I/O used for transferring the serial data

and the ICSPCLK pin is the clock input. For more

information on ICSP™ refer to the “PIC16(L)F153XX

Memory Programming Specification” (DS40001838).

ICSPCLK

1 3

5

Target

PC Board

Bottom Side

a

VPP/MCLR

VSS

Pin Description*

1 = VPP/MCLR

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

35.1 High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT

pins low then raising the voltage on MCLR/VPP to VIHH.

5 = ICSPCLK

6 = No Connect

35.2 Low-Voltage Programming Entry

Mode

Another connector often found in use with the PICkit™

programmers is a standard 6-pin header with 0.1 inch

spacing. Refer to Figure 35-2.

The Low-Voltage Programming Entry mode allows the

PIC^®Flash MCUs to be programmed using VDD only,

without high voltage. When the LVP bit of Configuration

Words is set to ‘1’, the low-voltage ICSP programming

entry is enabled. To disable the Low-Voltage ICSP

mode, the LVP bit must be programmed to ‘0’. The LVP

bit can only be reprogrammed to ‘0’ by using the High-

Voltage Programming mode.

For additional interface recommendations, refer to your

specific device programmer manual prior to PCB

design.

It is recommended that isolation devices be used to

separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific

application and may include devices such as resistors,

diodes, or even jumpers. See Figure 35-3 for more

information.

Entry into the Low-Voltage Programming Entry mode

requires the following steps:

1. MCLR is brought to VIL.

2.

A

32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be

held at VIL for as long as Program/Verify mode is to be

maintained.

If low-voltage programming is enabled (LVP = 1), the

MCLR Reset function is automatically enabled and

cannot be disabled. See Section 8.5 “MCLR” for more

information.

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FIGURE 35-2:

PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE

Rev. 10-000128A

7/30/2013

Pin 1 Indicator

Pin Description*

1 = VPP/MCLR

1

2

3

4

5

6

2 = VDD Target

3 = VSS (ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No connect

FIGURE 35-3:

TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

Rev. 10-000129A

7/30/2013

External

Programming

Signals

Device to be

Programmed

VDD

VPP

VSS

MCLR/VPP

VSS

Data

ICSPDAT

ICSPCLK

Clock

*

To Normal Connections

*

Isolation devices (as required).

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36.1 Read-Modify-Write Operations

36.0 INSTRUCTION SET SUMMARY

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according in either the working

(W) register, or the originating file register, depending

on the state of the destination designator 'd' (see

Table 36-1 for more information). A read operation is

performed on a register even if the instruction writes to

that register.

Each instruction is a 14-bit word containing the

operation code (opcode) and all required operands.

The opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most

varied instruction word format.

Table 36-3 lists the instructions recognized by the

MPASM^TMassembler.

TABLE 36-1: OPCODE FIELD

DESCRIPTIONS

All instructions are executed within a single instruction

cycle, with the following exceptions, which may take

two or three cycles:

Field

Description

f

W

b

Register file address (0x00 to 0x7F)

Working register (accumulator)

• Subroutine entry takes two cycles (CALL, CALLW)

• Returns from interrupts or subroutines take two

cycles (RETURN, RETLW, RETFIE)

• Program branching takes two cycles (GOTO, BRA,

BRW, BTFSS, BTFSC, DECFSZ, INCSFZ)

• One additional instruction cycle will be used when

any instruction references an indirect file register

and the file select register is pointing to program

memory.

Bit address within an 8-bit file register

Literal field, constant data or label

k

x

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

One instruction cycle consists of 4 oscillator cycles; for

an oscillator frequency of 4 MHz, this gives a nominal

instruction execution rate of 1 MHz.

n

FSR or INDF number. (0-1)

mm

Prepost increment-decrement mode selection

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

TABLE 36-2: ABBREVIATION

DESCRIPTIONS

Field

Description

PC

TO

C

Program Counter

Time-Out bit

Carry bit

DC

Z

Digit Carry bit

Zero bit

PD

Power-Down bit

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36.2 General Format for Instructions

TABLE 36-3: INSTRUCTION SET

14-Bit Opcode

Status

Mnemonic,

Description

Operands

Cycles

Notes

Affected

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ADDWFC f, d

ANDWF

ASRF

LSLF

f, d

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

1

00 0111 dfff ffff C, DC, Z

11 1101 dfff ffff C, DC, Z

00 0101 dfff ffff Z

11 0111 dfff ffff C, Z

11 0101 dfff ffff C, Z

11 0110 dfff ffff C, Z

2

f, d

f

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB f, d

SWAPF

XORWF

00 0001 lfff ffff

00 0001 0000 00xx

00 1001 dfff ffff

00 0011 dfff ffff

00 1010 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 1fff ffff

00 1101 dfff ffff

00 1100 dfff ffff

Z

–

f, d

f

f, d

2

C

00 0010 dfff ffff C, DC, Z

11 1011 dfff ffff C, DC, Z

00 1110 dfff ffff

f, d

00 0110 dfff ffff

Z

BYTE ORIENTED SKIP OPERATIONS

f, d

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

00

1011 dfff ffff

1111 dfff ffff

1, 2

DECFSZ

INCFSZ

BIT-ORIENTED FILE REGISTER OPERATIONS

f, b

Bit Clear f

Bit Set f

1

01

00bb bfff ffff

01bb bfff ffff

2

BCF

BSF

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS

f, b

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

01

10bb bfff ffff

11bb bfff ffff

1, 2

LITERAL OPERATIONS

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

1

11

00

11

1110 kkkk kkkk C, DC, Z

1001 kkkk kkkk

1000 kkkk kkkk

Z

000

0k

kkkk

0001 1kkk kkkk

0000 kkkk kkkk

Subtract W from literal

Exclusive OR literal with W

1100 kkkk kkkk C, DC, Z

1010 kkkk kkkk

Z

Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second

cycle is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

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TABLE 36-3: INSTRUCTION SET (CONTINUED)

14-Bit Opcode

Status

Mnemonic,

Description

Operands

Cycles

Notes

Affected

MSb

LSb

CONTROL OPERATIONS

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN

k

–

k

–

k

–

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

2

11

00

10

00

10

00

11

00

001k kkkk kkkk

0000 0000 1011

0kkk kkkk kkkk

0000 0000 1010

1kkk kkkk kkkk

0000 0000 1001

0100 kkkk kkkk

0000 0000 1000

INHERENT OPERATIONS

CLRWDT

NOP

RESET

SLEEP

TRIS

–

f

Clear Watchdog Timer

No Operation

Software device Reset

Go into Standby or IDLE mode

Load TRIS register with W

1

00

0000 0110 0100 TO, PD

0000 0000 0000

0000 0000 0001

0000 0110 0011 TO, PD

0000 0110 0fff

C-COMPILER OPTIMIZED

ADDFSR n, k

Add Literal k to FSRn

Move Indirect FSRn to W with pre/post inc/dec

modifier, mm

1

11 0001 0nkk kkkk

00 0000 0001 0nmm

MOVIW

n mm

Z

2, 3

k[n]

n mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec

modifier, mm

1

11 1111 0nkk kkkk

00 0000 0001 1nmm

2

2, 3

MOVWI

k[n]

Move W to INDFn, Indexed Indirect.

1

11 1111 1nkk kkkk

2

Note 1:If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require

one additional instruction cycle.

3: See Section 36.3 “Instruction Descriptions” for detailed MOVIW and MOVWI instruction descriptions.

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36.3 Instruction Descriptions

ADDFSR

Add Literal to FSRn

ANDLW

AND literal with W

Syntax:

[ label ] ADDFSR FSRn, k

Syntax:

[ label ] ANDLW

0  k  255

k

Operands:

-32  k  31

n  [ 0, 1]

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k)  (W)

Operation:

FSR(n) + k  FSR(n)

Z

Status Affected:

Description:

None

The contents of W register are

AND’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

The signed 6-bit literal ‘k’ is added to

the contents of the FSRnH:FSRnL

register pair.

FSRn is limited to the range 0000h-

FFFFh. Moving beyond these bounds

will cause the FSR to wrap-around.

ADDLW

Add literal and W

ANDWF

AND W with f

Syntax:

[ label ] ADDLW

0  k  255

k

Syntax:

[ label ] ANDWF f,d

Operands:

Operation:

Status Affected:

Description:

Operands:

0  f  127

d 0,1

(W) + k  (W)

C, DC, Z

Operation:

(W) .AND. (f)  (destination)

The contents of the W register are

added to the 8-bit literal ‘k’ and the

result is placed in the W register.

Status Affected:

Description:

Z

AND the W register with register ‘f’. If

‘d’ is ‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

ADDWF

Add W and f

ASRF

Arithmetic Right Shift

Syntax:

[ label ] ADDWF f,d

Syntax:

[ label ] ASRF f {,d}

Operands:

0  f  127

d 0,1

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f)  (destination)

Operation:

(f<7>) dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, DC, Z

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the result is

stored in the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. The MSb remains unchanged. If

‘d’ is ‘0’, the result is placed in W. If ‘d’

is ‘1’, the result is stored back in

register ‘f’.

ADDWFC

ADD W and CARRY bit to f

C

register f

Syntax:

[ label ] ADDWFC

f {,d}

Operands:

0  f  127

d [0,1]

Operation:

(W) + (f) + (C)  dest

Status Affected:

Description:

C, DC, Z

Add W, the Carry flag and data mem-

ory location ‘f’. If ‘d’ is ‘0’, the result is

placed in W. If ‘d’ is ‘1’, the result is

placed in data memory location ‘f’.

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BTFSC

Bit Test f, Skip if Clear

BCF

Bit Clear f

Syntax:

[ label ] BTFSC f,b

Syntax:

[ label ] BCF f,b

Operands:

0  f  127

0  b  7

Operands:

0  f  127

0  b  7

Operation:

skip if (f<b>) = 0

Operation:

0 (f<b>)

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

Bit ‘b’ in register ‘f’ is cleared.

If bit ‘b’, in register ‘f’, is ‘0’, the next

instruction is discarded, and a NOPis

executed instead, making this a 2-

cycle instruction.

BRA

Relative Branch

BTFSS

Bit Test f, Skip if Set

Syntax:

[ label ] BRA label

[ label ] BRA $+k

Syntax:

[ label ] BTFSS f,b

Operands:

0  f  127

0  b < 7

Operands:

-256  label - PC + 1  255

-256  k  255

Operation:

skip if (f<b>) = 1

Operation:

(PC) + 1 + k  PC

Status Affected:

Description:

None

Status Affected:

Description:

None

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next instruction

is discarded and a NOPis executed

instead, making this a 2-cycle

instruction.

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 1 + k. This instruction is a 2-

cycle instruction. This branch has a

limited range.

BRW

Relative Branch with W

Syntax:

[ label ] BRW

None

Operands:

Operation:

Status Affected:

Description:

(PC) + (W)  PC

None

Add the contents of W (unsigned) to

the PC. Since the PC will have

incremented to fetch the next

instruction, the new address will be

PC + 1 + (W). This instruction is a 2-

cycle instruction.

BSF

Bit Set f

Syntax:

[ label ] BSF f,b

Operands:

0  f  127

0  b  7

Operation:

1 (f<b>)

Status Affected:

Description:

None

Bit ‘b’ in register ‘f’ is set.

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CALL

Call Subroutine

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CALL

0  k  2047

k

Syntax:

[ label ] CLRWDT

Operands:

Operation:

Operands:

Operation:

None

(PC)+ 1 TOS,

k  PC<10:0>,

(PCLATH<6:3>)  PC<14:11>

00h  WDT

0 WDT prescaler,

1 TO

1 PD

Status Affected:

Description:

None

Status Affected:

Description:

TO, PD

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The 11-bit immediate address is

loaded into PC bits <10:0>. The upper

bits of the PC are loaded from

PCLATH. CALLis a 2-cycle

instruction.

CLRWDTinstruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

CALLW

Subroutine Call With W

COMF

Complement f

Syntax:

[ label ] CALLW

Syntax:

[ label ] COMF f,d

Operands:

Operation:

None

Operands:

0  f  127

d  [0,1]

(PC) +1  TOS,

(W)  PC<7:0>,

(PCLATH<6:0>) PC<14:8>

Operation:

(f)  (destination)

Status Affected:

Description:

Z

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the result is

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

Status Affected:

Description:

None

Subroutine call with W. First, the

return address (PC + 1) is pushed

onto the return stack. Then, the

contents of W is loaded into PC<7:0>,

and the contents of PCLATH into

PC<14:8>. CALLWis a 2-cycle

instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0  f  127

f

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

00h  (f)

1 Z

Operation:

(f) - 1  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in

register ‘f’.

The contents of register ‘f’ are cleared

and the Z bit is set.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h  (W)

1 Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z) is

set.

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DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) - 1  (destination);

skip if result = 0

Operation:

(f) + 1  (destination),

skip if result = 0

Status Affected:

Description:

None

Status Affected:

Description:

None

The contents of register ‘f’ are decre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, then a

NOPis executed instead, making it a

2-cycle instruction.

If the result is ‘1’, the next instruction is

executed. If the result is ‘0’, a NOPis

executed instead, making it a 2-cycle

instruction.

GOTO

Unconditional Branch

IORLW

Inclusive OR literal with W

Syntax:

[ label ] GOTO

0  k  2047

k

Syntax:

[ label ] IORLW

0  k  255

(W) .OR. k  (W)

Z

k

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k  PC<10:0>

PCLATH<6:3>  PC<14:11>

Status Affected:

Description:

None

The contents of the W register are

OR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

GOTOis an unconditional branch. The

11-bit immediate value is loaded into

PC bits <10:0>. The upper bits of PC

are loaded from PCLATH<4:3>. GOTO

is a 2-cycle instruction.

INCF

Increment f

IORWF

Inclusive OR W with f

Syntax:

[ label ] INCF f,d

Syntax:

[ label ] IORWF f,d

Operands:

0  f  127

d  [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f) + 1  (destination)

Operation:

(W) .OR. (f)  (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

The contents of register ‘f’ are incre-

mented. If ‘d’ is ‘0’, the result is placed

in the W register. If ‘d’ is ‘1’, the result

is placed back in register ‘f’.

Inclusive OR the W register with regis-

ter ‘f’. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

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LSLF

Logical Left Shift

MOVF

Move f

Syntax:

[ label ] LSLF f {,d}

Syntax:

[ label ] MOVF f,d

Operands:

0  f  127

d [0,1]

Operands:

0  f  127

d  [0,1]

Operation:

(f<7>)  C

Operation:

(f)  (dest)

(f<6:0>)  dest<7:1>

0  dest<0>

Status Affected:

Description:

Z

The contents of register f is moved to

a destination dependent upon the

status of d. If d = 0, destination is W

register. If d = 1, the destination is file

register f itself. d = 1is useful to test a

file register since status flag Z is

affected.

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the left through the Carry flag.

A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’,

the result is placed in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

Words:

1

C

register f

0

Cycles:

Example:

MOVF

FSR, 0

After Instruction

LSRF

Logical Right Shift

W

Z

=

value in FSR register

1

Syntax:

[ label ] LSRF f {,d}

Operands:

0  f  127

d [0,1]

Operation:

0  dest<7>

(f<7:1>)  dest<6:0>,

(f<0>)  C,

Status Affected:

Description:

C, Z

The contents of register ‘f’ are shifted

one bit to the right through the Carry

flag. A ‘0’ is shifted into the MSb. If ‘d’ is

‘0’, the result is placed in W. If ‘d’ is ‘1’,

the result is stored back in register ‘f’.

0

C

register f

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MOVIW

Move INDFn to W

MOVLP

Move literal to PCLATH

Syntax:

[ label ] MOVIW ++FSRn

[ label ] MOVIW --FSRn

[ label ] MOVIW FSRn++

[ label ] MOVIW FSRn--

[ label ] MOVIW k[FSRn]

Syntax:

[ label ] MOVLP

0  k  127

k  PCLATH

None

k

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

The 7-bit literal ‘k’ is loaded into the

PCLATH register.

INDFn  W

Effective address is determined by

MOVLW

Move literal to W

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

Syntax:

[ label ] MOVLW

0  k  255

k  (W)

k

Operands:

Operation:

Status Affected:

Description:

After the Move, the FSR value will be

either:

None

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Unchanged

The 8-bit literal ‘k’ is loaded into W reg-

ister. The “don’t cares” will assemble as

‘0’s.

Status Affected:

Z

Words:

1

Cycles:

Example:

Mode

Syntax

mm

00

01

10

11

MOVLW

0x5A

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

After Instruction

W

=

0x5A

MOVWF

Move W to f

[ label ] MOVWF

0  f  127

(W)  (f)

Syntax:

f

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

Status Affected:

Description:

None

Move data from W register to register

‘f’.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

Words:

1

Cycles:

Example:

MOVWF

Before Instruction

LATA = 0xFF

LATA

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

W = 0x4F

After Instruction

LATA = 0x4F

W = 0x4F

MOVLB

Move literal to BSR

Syntax:

[ label ] MOVLB

0  k 

k

Operands:

Operation:

Status Affected:

Description:

k  BSR

None

The 6-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

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PIC16(L)F15354/55

NOP

No Operation

MOVWI

Move W to INDFn

Syntax:

[ label ] NOP

Syntax:

[ label ] MOVWI ++FSRn

[ label ] MOVWI --FSRn

[ label ] MOVWI FSRn++

[ label ] MOVWI FSRn--

[ label ] MOVWI k[FSRn]

Operands:

Operation:

Status Affected:

Description:

Words:

None

No operation

None

No operation.

Operands:

Operation:

n  [0,1]

mm  [00,01, 10, 11]

-32  k  31

1

Cycles:

1

W  INDFn

Effective address is determined by

Example:

NOP

•

FSR + 1 (preincrement)

FSR - 1 (predecrement)

FSR + k (relative offset)

After the Move, the FSR value will be

either:

RESET

Software Reset

•

FSR + 1 (all increments)

FSR - 1 (all decrements)

Syntax:

[ label ] RESET

Operands:

Operation:

None

Unchanged

Execute a device Reset. Resets the

RI flag of the PCON register.

Status Affected:

None

Status Affected:

Description:

None

Mode

Syntax

mm

00

01

10

11

This instruction provides a way to

execute a hardware Reset by

software.

Preincrement

Predecrement

Postincrement

Postdecrement

++FSRn

--FSRn

FSRn++

FSRn--

RETFIE

Syntax:

Return from Interrupt

[ label ] RETFIE k

None

Description:

This instruction is used to move data

between W and one of the indirect

registers (INDFn). Before/after this

move, the pointer (FSRn) is updated by

pre/post incrementing/decrementing it.

Operands:

Operation:

TOS  PC,

1 GIE

Status Affected:

Description:

None

Return from Interrupt. Stack is POPed

and Top-of-Stack (TOS) is loaded in

the PC. Interrupts are enabled by

setting Global Interrupt Enable bit,

GIE (INTCON<7>). This is a 2-cycle

instruction.

Note: The INDFn registers are not

physical registers. Any instruction that

accesses an INDFn register actually

accesses the register at the address

specified by the FSRn.

FSRn is limited to the range 0000h-

FFFFh. Incrementing/decrementing it

beyond these bounds will cause it to

wrap-around.

Words:

1

Cycles:

Example:

2

RETFIE

After Interrupt

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

PC

GIE =

=

TOS

1

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PIC16(L)F15354/55

RLF

Rotate Left f through Carry

RETLW

Syntax:

Return with literal in W

Syntax:

[ label ]

RLF f,d

[ label ] RETLW

0  k  255

k

Operands:

0  f  127

d  [0,1]

Operands:

Operation:

k  (W);

TOS  PC

Operation:

See description below

C

Status Affected:

Description:

Status Affected:

Description:

None

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The W register is loaded with the 8-bit

literal ‘k’. The program counter is

loaded from the top of the stack (the

return address). This is a 2-cycle

instruction.

C

Register f

Words:

1

2

Cycles:

Example:

Words:

1

CALL TABLE;W contains table

;offset value

Cycles:

Example:

RLF

REG1,0

•

;W now has table value

TABLE

Before Instruction

REG1

C

=

1110 0110

0

ADDWF PC ;W = offset

RETLW k1 ;Begin table

After Instruction

RETLW k2

;

REG1

W

C

=

1110 0110

1100 1100

1

•

RETLW kn ; End of table

RRF

Rotate Right f through Carry

Before Instruction

Syntax:

[ label ] RRF f,d

W

=

0x07

After Instruction

Operands:

0  f  127

d  [0,1]

W

=

value of k8

Operation:

See description below

C

Status Affected:

Description:

RETURN

Return from Subroutine

The contents of register ‘f’ are rotated

one bit to the right through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

the W register. If ‘d’ is ‘1’, the result is

placed back in register ‘f’.

Syntax:

[ label ] RETURN

None

Operands:

Operation:

Status Affected:

Description:

TOS  PC

None

C

Register f

Return from subroutine. The stack is

POPed and the top of the stack (TOS)

is loaded into the program counter.

This is a 2-cycle instruction.

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PIC16(L)F15354/55

SUBWF

Subtract W from f

Syntax:

[ label ] SUBWF f,d

SLEEP

Enter Sleep mode

[ label ] SLEEP

None

Operands:

0 f 127

d  [0,1]

Syntax:

Operands:

Operation:

(f) - (W) destination)

00h  WDT,

0 WDT prescaler,

1 TO,

Status Affected:

Description:

C, DC, Z

Subtract (2’s complement method) W

register from register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W

register. If ‘d’ is ‘1’, the result is stored

back in register ‘f.

0 PD

Status Affected:

Description:

TO, PD

The power-down Status bit, PD is

cleared. Time-out Status bit, TO is

set. Watchdog Timer and its

prescaler are cleared.

See Section 11.2 “Sleep Mode” for

more information.

C = 0

W  f

C = 1

W  f

DC = 0

DC = 1

W<3:0>  f<3:0>

W<3:0>  f<3:0>

SUBWFB

Subtract W from f with Borrow

SUBWFB f {,d}

Syntax:

Operands:

0  f  127

d  [0,1]

Operation:

(f) – (W) – (B) dest

Status Affected:

Description:

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s

complement method). If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

SUBLW

Subtract W from literal

Syntax:

[ label ] SUBLW

0 k 255

k

Operands:

Operation:

Status Affected:

Description:

SWAPF

Swap Nibbles in f

k - (W) W)

C, DC, Z

Syntax:

[ label ] SWAPF f,d

Operands:

0  f  127

d  [0,1]

The W register is subtracted (2’s

complement method) from the 8-bit

literal ‘k’. The result is placed in the W

register.

Operation:

(f<3:0>)  (destination<7:4>),

(f<7:4>)  (destination<3:0>)

Status Affected:

Description:

None

C = 0

W  k

The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is ‘0’,

the result is placed in the W register. If

‘d’ is ‘1’, the result is placed in register

‘f’.

C = 1

W  k

DC = 0

DC = 1

W<3:0>  k<3:0>

W<3:0>  k<3:0>

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PIC16(L)F15354/55

TRIS

Load TRIS Register with W

XORLW

Exclusive OR literal with W

Syntax:

[ label ] TRIS f

5  f  7

Syntax:

[ label ] XORLW

0 k 255

k

Operands:

Operation:

Status Affected:

Description:

Operands:

Operation:

Status Affected:

Description:

(W)  TRIS register ‘f’

None

(W) .XOR. k W)

Z

Move data from W register to TRIS

register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

The contents of the W register are

XOR’ed with the 8-bit literal ‘k’. The

result is placed in the W register.

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f,d

Operands:

0  f  127

d  [0,1]

Operation:

(W) .XOR. (f) destination)

Status Affected:

Description:

Z

Exclusive OR the contents of the W

register with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If ‘d’

is ‘1’, the result is stored back in

register ‘f’.

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PIC16(L)F15354/55

37.0 ELECTRICAL SPECIFICATIONS

(†)

37.1 Absolute Maximum Ratings

Ambient temperature under bias...................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on pins with respect to VSS

on VDD pin

PIC16F15354/55 ....................................................................................................... -0.3V to +6.5V

PIC16LF15354/55 ..................................................................................................... -0.3V to +4.0V

on MCLR pin ........................................................................................................................... -0.3V to +9.0V

on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V)

Maximum current

on VSS pin⁽¹⁾

-40°C  TA  +85°C .............................................................................................................. 350 mA

85°C  TA  +125°C ............................................................................................................. 120 mA

on VDD pin for 28-Pin devices⁽¹⁾

-40°C  TA  +85°C .............................................................................................................. 250 mA

85°C  TA  +125°C ............................................................................................................... 85 mA

on VDD pin for 40-Pin devices⁽¹⁾

-40°C  TA  +85°C .............................................................................................................. 350 mA

85°C  TA  +125°C ............................................................................................................. 120 mA

on any standard I/O pin ...................................................................................................................... 50 mA

Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA

Total power dissipation⁽²⁾................................................................................................................................ 800 mW

Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be

limited by the device package power dissipation characterizations, see Table 37-6 to calculate device

specifications.

2: Power dissipation is calculated as follows:

PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for

extended periods may affect device reliability.

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PIC16(L)F15354/55

37.2 Standard Operating Conditions

The standard operating conditions for any device are defined as:

Operating Voltage:

Operating Temperature:

VDDMIN VDD VDDMAX

TA_MIN TA TA_MAX

VDD — Operating Supply Voltage⁽¹⁾

PIC16LF15354/55

VDDMIN (Fosc  16 MHz) ......................................................................................................... +1.8V

VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V

VDDMAX .................................................................................................................................... +3.6V

PIC16F15354/55

VDDMIN (Fosc  16 MHz) ......................................................................................................... +2.3V

VDDMIN (Fosc  32 MHz) ......................................................................................................... +2.5V

VDDMAX .................................................................................................................................... +5.5V

TA — Operating Ambient Temperature Range

Industrial Temperature

TA_MIN...................................................................................................................................... -40°C

TA_MAX.................................................................................................................................... +85°C

Extended Temperature

TA_MIN...................................................................................................................................... -40°C

TA_MAX.................................................................................................................................. +125°C

Note 1: See Parameter Supply Voltage, DS Characteristics: Supply Voltage.

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PIC16(L)F15354/55

FIGURE 37-1:

VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16F15354/55 ONLY

5.5

2.5

2.3

0

4

10

16

32

Frequency (MHz)

Note 1:The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.

FIGURE 37-2:

VOLTAGE FREQUENCY GRAPH, -40°C  TA +125°C, PIC16LF15354/55 ONLY

3.6

2.5

1.8

0

4

10

16

32

Frequency (MHz)

Note 1:The shaded region indicates the permissible combinations of voltage and frequency.

2: Refer to Table 37-7 for each Oscillator mode’s supported frequencies.

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PIC16(L)F15354/55

37.3 DC Characteristics

TABLE 37-1: SUPPLY VOLTAGE

PIC16LF15354/55

Standard Operating Conditions (unless otherwise stated)

PIC16F15354/55

Param.

Sym.

Characteristic

Min. Typ.† Max. Units

Conditions

No.

Supply Voltage

D002

VDD

1.8

2.5

—

3.6

V

FOSC  16 MHz

FOSC  16 MHz

D002

VDD

2.3

2.5

—

5.5

V

FOSC  16 MHz

FOSC 16 MHz

RAM Data Retention⁽¹⁾

D003

VDR

1.5

1.7

—

V

Device in Sleep mode

VDR

Power-on Reset Release Voltage⁽²⁾

D004

VPOR

—

1.6

—

V

BOR or LPBOR disabled⁽³⁾

D004

VPOR

Power-on Reset Rearm Voltage⁽²⁾

D005

VPORR

—

0.8

1.5

—

V

BOR or LPBOR disabled⁽³⁾

D005

VPORR

VDD Rise Rate to ensure internal Power-on Reset signal⁽²⁾

D006

SVDD

0.05

—

V

BOR or LPBOR disabled⁽³⁾

†

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.

3: See Table 37-11 for BOR and LPBOR trip point information.

4:

= F device

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PIC16(L)F15354/55

FIGURE 37-3:

POR AND POR REARM WITH SLOW RISING VDD

VDD

VPOR

VPORR

SVDD

VSS

(1)

NPOR

POR REARM

VSS

(2)

(3)

TPOR

TVLOW

Note 1: When NPOR is low, the device is held in Reset.

2: TPOR 1 s typical.

3: TVLOW 2.7 s typical.

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PIC16(L)F15354/55

TABLE 37-2: SUPPLY CURRENT (IDD)^(1,2,4)

Standard Operating Conditions (unless otherwise

stated)

PIC16LF15354/55

PIC16F15354/55

Param.

Conditions

Symbol

Device Characteristics

Min. Typ.† Max. Units

No.

VDD

Note

D100

D101

D102

D103

D104

D105

IDD

XT = 4 MHz

—

360

380

1.4

1.5

2.6

2.7

2.6

2.7

—

470

480

2.3

3.6

3.7

3.6

3.7

—

A

3.0V

XT4

IDD

XT4

HFINTOSC = 16 MHz

mA

HFO16

HFOPLL

HSPLL32

IDLE

HFINTOSC = 16 MHz

HFINTOSC = 32 MHz

3.0V 32 MHz PIC16

3.0V

HFINTOSC = 32 MHz

HS+PLL = 32 MHz

IDLE mode, HFINTOSC = 16 MHz

—

3.0V

IDLE

(3)

DOZE mode, HFINTOSC = 16 MHz, Doze

Ratio = 16

—

3.0V Typical value only.

DOZE

(3)

D105

IDD

DOZE mode, HFINTOSC = 16 MHz, Doze

Ratio = 16

—

mA

3.0V Typical value only.

DOZE

†

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from

rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current

consumption.

3: IDD

= [IDD

*(N-1)/N] + IDD

16/N where N = DOZE Ratio (Register 11-2).

DOZE

IDLE

HFO

4: PMD bits are all in the default state, no modules are disabled.

5: = F device

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PIC16(L)F15354/55

TABLE 37-3: POWER-DOWN CURRENT (IPD)^(1,2,3)

PIC16LF15354/55

Standard Operating Conditions (unless otherwise stated)

VREGPM = 1

PIC16F15354/55

Conditions

Param.

No.

Max.

+85°C +125°C

Max.

Symbol

Device Characteristics

IPD Base

Min. Typ.†

Units

VDD

3.0V

Note

D200

IPD

—

0.05

2

6

A

D200

D200A

IPD

IPD Base

—

0.4

18

2.5

22

9

27

9

A

3.0V VREGPM = 0

D201

IPD_WDT

Low-Frequency Internal Oscillator/

WDT

0.4

2.9

3.0V

Low-Frequency Internal Oscillator/

WDT

—

0.5

3.3

13

A

3.0V

D202

D203

D204

D205

D206

D207

IPD_SOSC

IPD_FVR

IPD_BOR

Secondary Oscillator (SOSC)

FVR

—

0.6

0.8

33

2.8

3.2

47

44

17

18

4

13

15

47

44

19

20

10

11

—

93

98

A

3.0V

FVR

28

3.0V

Brown-out Reset (BOR)

10

3.0V

14

3.0V

IPD_LPBOR Low-Power Brown-out Reset (LPBOR)

0.5

0.7

250

280

30

3.0V

5

3.0V

(4)

IPD_ADCA

IPD_CMP

ADC - Active

Comparator

—

90

93

3.0V ADC is converting

3.0V

33

†

Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:

2:

The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The

peripheral ∆ current can be determined by subtracting the base IDD or IPD current from this limit. Max. values should be used

when calculating total current consumption.

The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part

in Sleep mode with all I/O pins in high-impedance state and tied to VSS.

3:

4:

All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available.

ADC clock source is FRC.

5:

= F device

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PIC16(L)F15354/55

TABLE 37-4: I/O PORTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VIL

Input Low Voltage

I/O PORT:

D300

D301

D302

D303

D304

D305

with TTL buffer

—

0.8

V

4.5V  VDD  5.5V

0.15 VDD

0.2 VDD

0.3 VDD

0.8

1.8V  VDD  4.5V

2.0V  VDD  5.5V

with Schmitt Trigger buffer

2

with I C levels

with SMBus levels

MCLR

2.7V  VDD  5.5V

0.2 VDD

VIH

Input High Voltage

I/O PORT:

D320

D321

with TTL buffer

2

—

V

4.5V  VDD 5.5V

1.8V  VDD  4.5V

0.25 VDD +

0.8

D322

D323

D324

D325

with Schmitt Trigger buffer

0.8 VDD

0.7 VDD

2.1

—

V

2.0V  VDD  5.5V

2.7V  VDD  5.5V

2

with I C levels

with SMBus levels

MCLR

0.7 VDD

(1)

IIL

Input Leakage Current

D340

D341

D342

I/O Ports

—

± 5

± 125

± 1000

± 200

nA

VSS  VPIN  VDD,

Pin at high-impedance, 85°C

VSS  VPIN  VDD,

Pin at high-impedance, 125°C

(2)

MCLR

± 50

VSS  VPIN  VDD,

Pin at high-impedance, 85°C

IPUR

VOL

VOH

CIO

Weak Pull-up Current

D350

D360

25

—

100

—

200

0.6

A

VDD = 3.0V, VPIN = VSS

IOL = 10.0 mA, VDD = 3.0V

IOH = 6.0 mA, VDD = 3.0V

Output Low Voltage

I/O ports

V

Output High Voltage

I/O ports

D370

D380

VDD - 0.7

—

5

—

V

All I/O pins

50

pF

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1:Negative current is defined as current sourced by the pin.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

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TABLE 37-5: MEMORY PROGRAMMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

High Voltage Entry Programming Mode Specifications

MEM01

V

Voltage on MCLR/VPP pin to enter

programming mode

8

—

1

9

V

(Note 2, Note 3)

IHH

MEM02

I

Current on MCLR/VPP pin during

programming mode

—

mA

(Note 2)

PPGM

Programming Mode Specifications

MEM10

MEM11

V

VDD for Bulk Erase

—

2.7

—

V

BE

I

Supply Current during Programming

operation

10

mA

DDPGM

Program Flash Memory Specifications

MEM30

E

Flash Memory Cell Endurance

10k

—

E/W

Year

-40C  TA  +85C

(Note 1)

P

MEM32

T

Characteristic Retention

40

—

Provided no other

P_RET

specifications are violated

MEM33

MEM34

V

VDD for Read operation

VDDMIN

—

VDDMAX

V

P_RD

VDD for Row Erase or Write

operation

P_REW

MEM35

T

Self-Timed Row Erase or Self-Timed

Write

—

2.0

2.5

ms

P_REW

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed

Write. HEF feature applies only to the last 128 words of the Program Flash Memory.

2: Required only if CONFIG4, bit LVP is disabled.

®

3: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed

between the ICD2 and target system when programming or debugging with the ICD2.

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TABLE 37-6: THERMAL CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param.

No.

Sym.

Characteristic

Typ.

Units

Conditions

28-pin SPDIP package

TH01

^JA

Thermal Resistance Junction to Ambient

60

80

C/W

28-pin SOIC package

90

28-pin SSOP package

48

28-pin UQFN 4x4 mm package

TH02

^JC

Thermal Resistance Junction to Case

31.4

28-pin SPDIP package

28-pin SOIC package

24

12

150

—

C/W

C

28-pin SSOP package

28-pin UQFN 4x4 mm package

TH03

TH04

TH05

TH06

TH07

TJMAX

PD

Maximum Junction Temperature

Power Dissipation

W

PD = PINTERNAL + PI/O

(1)

PINTERNAL Internal Power Dissipation

—

W

PINTERNAL = IDD x VDD

PI/O

I/O Power Dissipation

Derated Power

—

W

PI/O =  (IOL * VOL) +  (IOH * (VDD - VOH))

(2)

PDER

—

W

PDER = PDMAX (TJ - TA)/JA

Note 1:IDD is current to run the chip alone without driving any load on the output pins.

2: TA = Ambient Temperature, TJ = Junction Temperature

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37.4 AC Characteristics

FIGURE 37-4:

LOAD CONDITIONS

Rev. 10-000133A

8/1/2013

Load Condition

CL

VSS

Legend: CL=50 pF for all pins

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FIGURE 37-5:

CLOCK TIMING

Q1

Q4

Q1

Q2

Q3

Q4

CLKIN

OS12

OS03

OS11

OS02

CLKOUT

(CLKOUT Mode)

Note 1:

See Table 37-7.

TABLE 37-7: EXTERNAL CLOCK/OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

No.

ECL Oscillator

OS1

OS2

F

T

Clock Frequency

—

500

60

kHz

%

ECL

Clock Duty Cycle

40

ECL_DC

ECM Oscillator

OS3

OS4

F

T

Clock Frequency

Clock Duty Cycle

—

4

MHz

%

ECM

40

60

ECM_DC

ECH Oscillator

OS5

OS6

F

T

Clock Frequency

Clock Duty Cycle

—

32

60

MHz

%

ECH

40

ECH_DC

LP Oscillator

OS7

XT Oscillator

OS8

HS Oscillator

OS9

System Oscillator

F

Clock Frequency

—

100

4

kHz

MHz

Note 4

LP

F

Note 4

XT

F

20

HS

OS20

OS21

OS22

F

T

System Clock Frequency

Instruction Frequency

Instruction Period

—

32

—

MHz

ns

(Note 2, Note 3)

OSC

CY

FOSC/4

125

1/F

CY

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing

code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected

current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin.

When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

2: The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in Section 9.0

“Oscillator Module (with Fail-Safe Clock Monitor)”.

3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 “Standard

Operating Conditions”.

4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking

the device with the external square wave, one of the EC mode selections must be used.

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TABLE 37-8: INTERNAL OSCILLATOR PARAMETERS⁽¹⁾

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

OS50

FHFOSC

Precision Calibrated HFINTOSC

Frequency

—

4

8

—

MHz (Note 2)

12

16

32

OS51

OS52

FHFOSCLP Low-Power Optimized HFINTOSC

Frequency

0.93

1.86

1

2

1.07 MHz

2.14 MHz

FMFOSC

Internal Calibrated MFINTOSC

Frequency

—

500

—

kHz (Note 3)

OS53

OS54

FLFOSC

Internal LFINTOSC Frequency

—

31

—

kHz

THFOSCST HFINTOSC

Wake-up from Sleep Start-up

—

11

50

20

—

s VREGPM = 0

s VREGPM = 1

Time

OS56

TLFOSCST LFINTOSC

—

0.2

—

ms

Wake-up from Sleep Start-up Time

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 F and 0.01 F values in parallel are recommended.

2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Tempera-

ture.

FIGURE 37-6:

PRECISION CALIBRATED HFINTOSC FREQUENCY ACCURACY OVER DEVICE

VDD AND TEMPERATURE

125

85

± 5%

± 3%

60

± 2%

0

± 5%

-40

1.8

2.0

2.3

3.5

4.0

VDD (V)

4.5

5.0

5.5

3.0

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TABLE 37-9: PLL SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated) VDD 2.5V

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max.

Units Conditions

PLL01 FPLLIN

PLL Input Frequency Range

4

16

—

8

32

MHz

PLL02 FPLLOUT PLL Output Frequency Range

MHz Note 1

PLL03 TPLLST

PLL04 FPLLJIT

PLL Lock Time from Start-up

—

200

—

s

PLL Output Frequency Stability (Jitter)

-0.25

0.25

%

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002.

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FIGURE 37-7:

CLKOUT AND I/O TIMING

Cycle

Write

Q4

Fetch

Q1

Read

Q2

Execute

Q3

FOSC

IO2

IO1

IO10

IO5

CLKOUT

IO8, IO9

IO6, IO7

IO4

I/O pin

(Input)

IO3

I/O pin

(Output)

New Value

Old Value

IO6, IO7, IO8, IO9

TABLE 37-10: I/O AND CLKOUT TIMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

IO1*

T_CLKOUTH

CLKOUT rising edge delay (rising

edge FOSC (Q1 cycle) to falling edge

CLKOUT

—

70

72

ns

IO2*

T_CLKOUTL

CLKOUT falling edge delay (rising

edge FOSC (Q3 cycle) to rising edge

CLKOUT

ns

IO3*

IO4*

IO5*

T_{IO_VALID}

T_{IO_SETUP}

T_{IO_HOLD}

Port output valid time (rising edge

Fosc (Q1 cycle) to port valid)

—

20

50

—

70

—

ns

Port input setup time (Setup time

before rising edge Fosc – Q2 cycle)

Port input hold time (Hold time after

rising edge Fosc – Q2 cycle)

IO6*

IO7*

IO8*

IO9*

IO10*

T_{IOR_SLREN}Port I/O rise time, slew rate enabled

T_{IOR_SLRDIS}Port I/O rise time, slew rate disabled

T_{IOF_SLREN}Port I/O fall time, slew rate enabled

T_{IOF_SLRDIS}Port I/O fall time, slew rate disabled

—

25

5

—

ns VDD = 3.0V

ns

25

5

T_INT

INT pin high or low time to trigger an

interrupt

—

IO11*

T_IOC

Interrupt-on-Change minimum high or

low time to trigger interrupt

25

—

ns

*These parameters are characterized but not tested.

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FIGURE 37-8:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

VDD

MCLR

RST01

Internal

POR

RST04

PWRT

Time-out

RST05

OSC

Start-up Time

Internal Reset⁽¹⁾

Watchdog Timer

Reset⁽¹⁾

RST03

RST02

I/O pins

Note 1:Asserted low.

FIGURE 37-9:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR + VHYST

VBOR

(Device in Brown-out Reset)

(Device not in Brown-out Reset)

(RST08)⁽¹⁾

Reset

(RST04)⁽¹⁾

(due to BOR)

Note 1:64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms

delay if PWRTE = 0.

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TABLE 37-11: RESET, WDT, OSCILLATOR START-UP TIMER, POWER-UP TIMER, BROWN-OUT

RESET AND LOW-POWER BROWN-OUT RESET SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

RST01* TMCLR

RST02* TIOZ

MCLR Pulse Width Low to ensure Reset

I/O high-impedance from Reset detection

Watchdog Timer Time-out Period

Power-up Timer Period

2

—

2

s

—

RST03

TWDT

16

—

ms 16 ms Nominal Reset Time

RST04* TPWRT

65

ms

(1,2)

RST05

RST06

TOST

Oscillator Start-up Timer Period

1024

TOSC

VBOR

Brown-out Reset Voltage

2.55

2.30

1.80

2.70

2.45

1.90

2.85

2.60

2.10

V

BORV = 0

BORV = 1(F devices)

BORV = 1(LF devices)

RST07

RST08

RST09

VBORHYS Brown-out Reset Hysteresis

—

40

3

—

mV

s

V

TBORDC

VLPBOR

Brown-out Reset Response Time

Low-Power Brown-out Reset Voltage

1.8

2.0

2.2

LF Devices Only

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency.

2: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible.

0.1 F and 0.01 F values in parallel are recommended.

TABLE 37-12: ANALOG-TO-DIGITAL CONVERTER (ADC) ACCURACY SPECIFICATIONS^(1,2)

:

Standard Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristic

Resolution

Min.

Typ†

Max. Units

Conditions

AD01

AD02

AD03

AD04

AD05

NR

—

10

bit

EIL

Integral Error

Differential Error

Offset Error

±0.1

0.5

±1.0

2.0

LSb ADCREF+ = 3.0V, ADCREF-= 0V

V

EDL

EOFF

EGN

—

Gain Error

—

±0.2

—

±1.0

VDD

AD06 VADREF ADC Reference Voltage

1.8

(3)

(ADREF+)

AD07

AD08

VAIN

ZAIN

Full-Scale Range

ADREF-

—

ADREF+

—

V

Recommended Impedance of

Analog Voltage Source

10

k

AD09 RVREF ADC Voltage Reference Ladder

Impedance

—

50

—

k Note 3

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors.

2: The ADC conversion result never decreases with an increase in the input and has no missing codes.

3: This is the impedance seen by the VREF pads when the external reference pads are selected.

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TABLE 37-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CONVERSION TIMING SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

AD20

TAD

ADC Clock Period

1

—

9

s

The requirement is to set ADCCS

correctly to produce this period/

frequency.

AD21

AD22

1

2

6

s

Using FRC as the ADC clock

source ADOSC = 1

TCNV Conversion Time

TACQ Acquisition Time

—

11

—

TAD Set of GO/DONE bit to Clear of GO/

DONE bit

AD23

AD24

—

2

—

s

THCD Sample and Hold Capacitor

Disconnect Time

—

s

FOSC-based clock source

FRC-based clock source

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

FIGURE 37-10:

ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED)

BSF ADCON0, GO

AD24

Q4

1 TCY

AD22

7

9

8

6

3

2

1

0

ADC Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

AD23

Sample

FIGURE 37-11:

ADC CONVERSION TIMING (ADC CLOCK FROM ADCRC)

BSF ADCON0, GO

AD24

1 TCY

AD22

Q4

AD20

ADC_clk

9

8

7

3

2

1

0

6

ADC Data

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

Sampling Stopped

AD23

Sample

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TABLE 37-14: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristics

Input Offset Voltage

Min.

Typ.

Max.

Units

Comments

VICM = VDD/2

CM01

VIOFF

—

GND

—

±50

VDD

—

mV

V

CM02

CM03

CM04

CM05

VICM

Input Common Mode Range

Common Mode Input Rejection Ratio

Comparator Hysteresis

CMRR

VHYST

50

dB

mV

ns

µs

15

25

35

(1)

TRESP

Response Time, Rising Edge

Response Time, Falling Edge

Mode Change to Valid Output

—

300

220

—

600

500

10

—

(2)

CMOS6

TMCV2VO

—

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.

2: A mode change includes changing any of the control register values, including module enable.

TABLE 37-15: 5-BIT DAC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristics

Step Size

Min.

Typ.

Max.

Units

Comments

DSB01

DSB03*

DSB04*

VLSB

—

(VDACREF+ -VDACREF-) /32

—

 0.5

—

V

LSb



VACC

RUNIT

TST

Absolute Accuracy

Unit Resistor Value

—

5000

—

(1)

Settling Time

10

s

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Settling time measured while DACR<4:0> transitions from ‘00000’ to ‘01111’.

TABLE 37-16: FIXED VOLTAGE REFERENCE (FVR) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

VFVR1

Characteristic

1x Gain (1.024V)

Min.

Typ. Max. Units

Conditions

FVR01

-4

—

+4

+6

%

VDD  2.5V, -40°C to

85°C

FVR02

FVR03

VFVR2

VFVR4

TFVRST

2x Gain (2.048V)

4x Gain (4.096V)

FVR Start-up Time

-4

-6

VDD  2.5V, -40°C to

85°C

VDD  4.75V, -40°C

to 85°C

FVR04

FVR05

—

25

—

us

FVRA1X/FVRC1X FVR output voltage for 1x setting stored in

the DIA

1024

mV

FVR06

FVR07

FVRA2X/FVRC2X FVR output voltage for 2x setting stored in

the DIA

—

2048

4096

—

mV

FVRA4X/FVRC4X FVR output voltage for 4x setting stored in

the DIA

Note 1

Note 1: Available only on PIC16F15354/55.

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TABLE 37-17: ZERO CROSS DETECT (ZCD) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VDD = 3.0V, TA = 25°C

Param.

No.

Sym.

Characteristics

Min.

Typ†

Max.

Units

Comments

ZC01

ZPCINV

ZCDRV

ZCISW

Voltage on Zero Cross Pin

—

0.75

—

1

—

600

—

V

ZC02

ZC04

Maximum source or sink current

Response Time, Rising Edge

Response Time, Falling Edge

Response Time, Rising Edge

Response Time, Falling Edge

A

s

1

—

ZC05

ZCOUT

1

—

1

—

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

FIGURE 37-12:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

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TABLE 37-18: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Sym.

TT0H

Characteristic

T0CKI High-Pulse Width

Min.

Typ†

Max.

Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

TT0L

T0CKI Low-Pulse Width

T0CKI Period

42*

45*

TT0P

TT1H

Greater of: 20

or (TCY +40)*N

ns N = prescale value

(2, 4,...256)

T1CKI High Synchronous, No Prescaler

0.5 TCY + 20

—

ns

Time

Synchronous, with Prescaler

Asynchronous

15

30

46*

47*

TT1L

T1CKI Low Synchronous, No Prescaler

0.5 TCY + 20

Time

Synchronous, with Prescaler

Asynchronous

15

30

TT1P

FT1

T1CKI Input Synchronous

Period

Greater of: 30

or (TCY +40)*N

ns N = prescale value

(2, 4,...256)

Asynchronous

60

—

ns

48

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

32.4

32.768

33.1

kHz

49*

TCKEZTMR1 Delay from External Clock Edge to Timer

Increment

2 TOSC

—

7 TOSC

—

Timers in Sync

mode

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

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FIGURE 37-13:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCPx

(Capture mode)

CC01

CC02

CC03

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-19: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C  TA  +125°C

Param.

No.

Sym.

Characteristic

Min.

Typ† Max. Units

Conditions

CC01* TccL CCPx Input Low Time

CC02* TccH CCPx Input High Time

CC03* TccP CCPx Input Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5TCY + 20

20

—

ns

0.5TCY + 20

20

(3TCY +40)*N

N = prescale value (1,4 or 16)

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

 2016-2017 Microchip Technology Inc.

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PIC16(L)F15354/55

FIGURE 37-14:

CLC PROPAGATION TIMING

Rev. 10-000031A

6/16/2016

LCx_in[n]⁽¹⁾

CLC

CLCxINn

CLCx

LCx_out⁽¹⁾

Input time

Module

Output time

CLC

Module

CLC

Output time

CLCx

LCx_in[n]⁽¹⁾

LCx_out⁽¹⁾

Input time

CLC01

CLC02

CLC03

Note 1: See Figure 31-1 to identify specific CLC signals.

TABLE 37-20: CONFIGURABLE LOGIC CELL (CLC) CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C TA +125°C

Param.

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

CLC01* TCLCIN

CLC02* TCLC

CLC input pin (CKCxIN) to CKC Module Input

select (LCx_IN) propagation time

—

7

IO5

ns (Note 1)

CLC Module input to output propagation delay

—

24

12

—

ns VDD = 1.8V

ns VDD > 3.6V

CLC03* TCLCOUT CLC Module output time

—

IO7

IO8

32

—

Rise Time (Note 1)

Fall Time (Note 1)

CLC04* FCLCMAX CLC Maximum switching frequency

FOSC MHz

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1:See Table 37-10 for IO5, IO7 and IO8 rise and fall times.

 2016-2017 Microchip Technology Inc.

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FIGURE 37-15:

EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

CK

DT

US121

US122

US120

Refer to Figure 37-4 for load conditions.

Note:

TABLE 37-21: EUSART SYNCHRONOUS TRANSMISSION CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

US120

TCKH2DTV

SYNC XMIT (Master and Slave)

Clock high to data-out valid

—

80

100

45

ns

3.0V  VDD  5.5V

1.8V  VDD  5.5V

3.0V  VDD  5.5V

1.8V  VDD  5.5V

3.0V  VDD  5.5V

1.8V  VDD  5.5V

US121

US122

TCKRF

TDTRF

Clock out rise time and fall time

(Master mode)

50

Data-out rise time and fall time

45

50

FIGURE 37-16:

EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

CK

DT

US125

US126

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C TA +125°C

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

US125 TDTV2CKL

US126 TCKL2DTL

SYNC RCV (Master and Slave)

Data-setup before CK  (DT hold time)

10

15

—

ns

Data-hold after CK  (DT hold time)

 2016-2017 Microchip Technology Inc.

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PIC16(L)F15354/55

FIGURE 37-17:

SPI MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

SP81

SCK

(CKP = 0)

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP80

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

LSb In

SP74

SP73

Note: Refer to Figure 37-4 for load conditions.

FIGURE 37-18:

SPI MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

SP81

SCK

(CKP = 0)

SP71

SP73

SP72

SP79

SCK

(CKP = 1)

SP80

SP78

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

SP73

Note: Refer to Figure 37-4 for load conditions.

 2016-2017 Microchip Technology Inc.

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PIC16(L)F15354/55

FIGURE 37-19:

SPI SLAVE MODE TIMING (CKE = 0)

SS

SP70

SCK

(CKP = 0)

SP83

SP71

SP72

SP78

SP79

SCK

(CKP = 1)

SP78

LSb

SP79

SP80

MSb

SDO

SDI

bit 6 - - - - - -1

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

SP73

Note: Refer to Figure 37-4 for load conditions.

FIGURE 37-20:

SPI SLAVE MODE TIMING (CKE = 1)

SP82

SP70

SS

SP83

SCK

(CKP = 0)

SP72

SP71

SCK

(CKP = 1)

SP80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

SP77

SP75, SP76

bit 6 - - - -1

MSb In

SP74

LSb In

SP73

Note: Refer to Figure 37-4 for load conditions.

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TABLE 37-23: SPI MODE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Typ† Max. Units

Conditions

SP70* TSSL2SCH,

TSSL2SCL

SS to SCK or SCK input

2.25*TCY

—

ns

SP71* TSCH

SP72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

SP73* TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK

edge

SP74* TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge

100

—

ns

SP75* TDOR

SDO data output rise time

—

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

SP76* TDOF

SDO data output fall time

—

ns

SP77* TSSH2DOZ

SP78* TSCR

SS to SDO output high impedance

10

ns

SCK output rise time

(Master mode)

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

ns

—

SP79* TSCF

SCK output fall time (Master mode)

SDO data output valid after SCK edge

—

SP80* TSCH2DOV,

TSCL2DOV

—

ns 3.0V  VDD  5.5V

ns 1.8V  VDD  5.5V

ns

—

SP81* TDOV2SCH,

TDOV2SCL

SDO data output setup to SCK edge

1 Tcy

SP82* TSSL2DOV

SDO data output valid after SS edge

SS after SCK edge

—

50

—

ns

SP83* TSCH2SSH,

TSCL2SSH

1.5 TCY + 40

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 496

PIC16(L)F15354/55

FIGURE 37-21:

I²C BUS START/STOP BITS TIMING

SCL

SP93

SP91

SP90

SP92

SDA

Stop

Condition

Start

Condition

Note: Refer to Figure 37-4 for load conditions.

TABLE 37-24: I²C BUS START/STOP BITS REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Typ Max. Units

Conditions

SP90*

TSU:STA

Start condition

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated Start

condition

Setup time

SP91*

SP92*

SP93

THD:STA

TSU:STO

THD:STO

Start condition

Hold time

4000

600

ns After this period, the first clock

pulse is generated

Stop condition

Setup time

4700

600

ns

Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 37-22:

I²C BUS DATA TIMING

SP100

SP102

SP103

SP101

SCL

SP90

SP91

SP106

SP107

SP92

SDA

In

SP110

SP109

SDA

Out

Note: Refer to Figure 37-4 for load conditions.

 2016-2017 Microchip Technology Inc.

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PIC16(L)F15354/55

TABLE 37-25: I²C BUS DATA REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param.

No.

Symbol

Characteristic

Min.

Max.

Units

Conditions

SP100*

THIGH

Clock high time

Clock low time

100 kHz mode

4.0

—

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

s

Device must operate at a

minimum of 10 MHz

SSP module

1.5TCY

4.7

—

SP101*

TLOW

100 kHz mode

s

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

1.3

—

Device must operate at a

minimum of 10 MHz

SSP module

1.5 TCY

—

SP102*

SP103*

TR

TF

SDA and SCL rise

time

100 kHz mode

400 kHz mode

1000

300

ns

20 + 0.1 CB

CB is specified to be from

10-400 pF

SDA and SCL fall time 100 kHz mode

400 kHz mode

—

250

ns

20 + 0.1 CB

CB is specified to be from

10-400 pF

SP106*

SP107*

SP109*

SP110*

THD:DAT

TSU:DAT

TAA

Data input hold time

100 kHz mode

400 kHz mode

0

—

0.9

—

ns

s

ns

s

Data input setup time 100 kHz mode

400 kHz mode

250

100

—

(Note 2)

(Note 1)

—

Output valid from

clock

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

3500

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

SP111

CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)

of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2

2: A Fast mode (400 kHz) I C bus device can be used in a Standard mode (100 kHz) I C bus system, but the requirement

TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of

the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA

2

line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification), before the SCL

line is released.

TABLE 37-26: TEMPERATURE INDICATOR REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Param No. Symbol

Characteristic

Min.

Typ†

Max.

Units

Conditions

TS01

TS02

TACQMIN Minimum ADC Acquisition Time Delay

—

25

—

s

MV

Voltage Sensitivity

High Range

Low Range

-3.684

-2.456

mV/°C TSRNG = 1

mV/°C TSRNG = 0

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

 2016-2017 Microchip Technology Inc.

DS40001853C-page 498

PIC16LF15354/55

38.0 DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

The graphs and tables provided in this section are for design guidance and are not tested.

In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD

range). This is for information only and devices are ensured to operate properly only within the specified range.

Unless otherwise noted, all graphs apply to both the L and LF devices.

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

“Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.”

represents (mean + 3) or (mean - 3) respectively, where  is a standard deviation, over each

temperature range.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 499

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

0

128

256

384

512

640

768

896

1024

0

128

256

384

512

640

768

896

1024

Output Code

FIGURE 38-1:

ADC 10-bit Mode,

FIGURE 38-2:

ADC 10-bit Mode,

Single-Ended DNL, VDD= 3.0V, VREF = 3.0V,

TAD = 1 uS, 25°C.

TAD = 4 uS, 25°C.

1.0

0.5

1.0

0.5

0.0

-0.5

-1.0

-0.5

-1.0

0

128

256

384

512

640

768

896

1024

0

128

256

384

512

640

768

896

1024

Output Code

FIGURE 38-3:

ADC 10-bit Mode,

FIGURE 38-4:

ADC 10-bit Mode,

Single-Ended DNL, VDD= 3.0V, VREF = 3.0V,

Single-Ended INL, VDD= 3.0V, VREF = 3.0V,

TAD = 8 uS, 25°C.

TAD = 1 uS, 25°C.

2.0

1.0

2.0

1.0

1.5

1.0

0.5

0.0

-0.5

0.0

-1.0

-1.5

-2.0

-0.5

-2.0

-0.5

0

512

128

1024

256

1536

384

2048

2560

640

3072

768

3584

896

4096

1024

0

512

128

1024

256

1536

384

2048

2560

640

3072

768

3584

896

4096

1024

Output Code

-1.0

512

Output Code

FIGURE 38-5:

ADC 10-bit Mode,

FIGURE 38-6:

ADC 10-bit Mode,

Single-Ended INL, VDD= 3.0V, VREF = 3.0V,

TAD = 4 uS, 25°C.

TAD = 8 uS, 25°C.

DS40001853C-page 500

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

1

0.5

0

1

0.5

0

-0.5

-1

-0.5

-1

Max 25°C

Min 25°C

Max -40°C

Min -40°C

Max 85°C

Min 85°C

Max 25°C

Min 25°C

Max -40°C

Min -40°C

Max 85°C

Min 85°C

0.5

0.8

1

2

4

8

0.5

0.8

1

2

4

8

TADs

FIGURE 38-7:

ADC 10-bit Mode,

FIGURE 38-8:

ADC 10-bit Mode,

Single-Ended DNL, VDD= 3.0V, VREF = 3.0V

Single-Ended INL, VDD= 3.0V, VREF = 3.0V

1

0.5

0

2

1.5

1

0.5

0

-0.5

-1

-0.5

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

Max -40°C

-1.5

-2

Min 85°C

Min 25°C

Min -40°C

-1

1.8

2.3

2.5

3

1.8

2.3

2.5

3

VREF

FIGURE 38-9:

ADC 10-bit Mode,

FIGURE 38-10:

ADC 10-bit Mode,

Single-Ended DNL, VDD= 3.0V, TAD = 1 uS

Single-Ended INL, VDD= 3.0V, TAD = 1 uS

6

5

3

2.5

2

4

3

1.5

1

2

1

0.5

0

-1

-2

-3

-0.5

-1

-1.5

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

-4

-5

-6

-2

-2.5

-3

1.8

2.3

2.5

3

1.8

2.3

2.5

3

VREF

FIGURE 38-11:

ADC 10-bit Mode,

FIGURE 38-12:

ADC 10-bit Mode,

Single-Ended Gain Error, VDD= 3.0V, TAD = 1 uS

Single-Ended Offset Error, VDD= 3.0V,

TAD = 1 uS

 2016-2018 Microchip Technology Inc.

DS40001853C-page 501

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

1

0.5

0

1

0.5

0

-0.5

-1

-0.5

-1

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

1.8

2.3

2.5

3

1.8

2.3

2.5

3

VREF

FIGURE 38-13:

ADC 10-bit Mode,

FIGURE 38-14:

ADC 10-bit Mode,

Single-Ended DNL, VDD= 3.0V, TAD = 4 uS.

Single-Ended INL, VDD= 3.0V, TAD = 4 uS.

6

5

1

0.5

0

4

3

2

1

0

-1

-2

-3

-0.5

Max 85°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

Max 25°C

Max -40°C

Min 85°C

Min 25°C

Min -40°C

-4

-5

-6

-1

1.8

2.3

2.5

3

1.8

2.3

2.5

3

VREF

FIGURE 38-15:

ADC 10-bit Mode,

FIGURE 38-16:

ADC 10-bit Mode,

Single-Ended Gain Error, VDD= 3.0V, TAD = 4 uS

Single-Ended Offset Error, VDD= 3.0V,

TAD = 4 uS

2

1.5

1

2

1.5

1

0.5

0

0.5

0

-0.5

-1

Max

Typical

Min

Max

-1.5

-2

Typical

Min

-2

0.5

0.8

1

2

4

8

0.5

0.8

1

2

4

8

TADs

FIGURE 38-17:

ADC 10-bit Mode,

FIGURE 38-18:

ADC 10-bit Mode,

Single-Ended Gain Error, VDD= 3.0V,

Single-Ended Offset Error, VDD= 3.0V,

VREF = 3.0V, -40°C to 85°C.

VREF = 3.0V, -40°C to 85°C

DS40001853C-page 502

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

VDD (V)

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6

VDD (V)

FIGURE 38-19:

ADC RC Oscillator Period,

FIGURE 38-20:

ADC RC Oscillator Period,

PIC16F15354/55 devices only.

5.0

70

60

50

40

30

20

10

Typical 25°C

4.5

+3 Sigma 125°C

+3ı (-40°C to +125°C)

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8

2.6

2.7

2.8

2.9

3.0

3.1

DD (V)

3.2

3.3

3.4

3.5

3.6

3.7

V

VDD (V)

FIGURE 38-21:

Band Gap Ready

FIGURE 38-22:

Brown-out Reset Response

Time, PIC16LF15354/55 devices only.

7

3.00

Typical 25°C

+3 Sigma

2.95

+3 Sigma 125°C

6

5

4

3

2

1

0

-3 Sigma

2.90

Typical

2.85

2.80

2.75

2.70

2.65

2.60

2.55

2.50

2.45

2.40

-60

-40

-20

0

20

40

60

80

100

120

140

2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6

Temperature (°C)

VDD (V)

FIGURE 38-23:

Brown-out Reset Response

FIGURE 38-24:

Brown-out Reset Voltage,

Time, PIC16F15354/55 devices only.

Trip Point (BORV = 00)

 2016-2018 Microchip Technology Inc.

DS40001853C-page 503

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

70.0

2.00

Typical

+3 Sigma

60.0

-3 Sigma

1.95

50.0

40.0

1.90

30.0

20.0

1.85

+3 Sigma

-3 Sigma

Typical

10.0

1.80

0.0

-60

-40

-20

0

20

40

60

80

100

120

140

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 38-25:

Brown-out Reset

FIGURE 38-26:

Brown-out Reset Voltage,

Hysteresis, Low-Trip Point (BORV = 00)

Trip Point (BORV = 01)

2.60

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

+3 Sigma

2.50

Typical

-3 Sigma

2.40

2.30

2.20

2.10

2.00

1.90

1.80

1.70

Typical

+3 Sigma

-3 Sigma

0.0

-60

-40

-20

0

20

40

60

80

100

120

140

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (°C)

FIGURE 38-27:

Brown-out Reset

FIGURE 38-28:

LPBOR Reset Voltage

Hysteresis, Trip Point (BORV = 01)

300

250

200

150

100

50

Typical 25°C

+3 Sigma 125°C

Typical

45

+3 Sigma

40

-3 Sigma

35

30

25

20

15

10

5

0

-60

-40

-20

0

20

40

60

80

100

120

140

0

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

Temperature (°C)

VDD (V)

FIGURE 38-29:

LPBOR Reset Hysteresis

FIGURE 38-30:

Comparator Response Time

Falling Edge, PIC16LF15354/55 devices only.

DS40001853C-page 504

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

700

600

500

400

300

200

100

0

250

200

150

100

50

Typical 25°C

+3 Sigma 125°C

0

1.7

1.9

2.1

2.3

2.5

2.7

2.9

3.1

3.3

3.5

3.7

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

VDD (V)

FIGURE 38-31:

Comparator Response Time

FIGURE 38-32:

Comparator Response Time

Falling Edge, PIC16F15354/55 devices only.

Rising Edge, PIC16LF15354/55 devices only.

45

900

Typical 25°C

43

800

-40°C

+3 Sigma 125°C

41

700

600

500

400

300

200

100

39

25°C

85°C

37

35

33

31

29

27

25

125°

0

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VDD (V)

Common Mode Voltage (V)

FIGURE 38-33:

Comparator Response Time

FIGURE 38-34:

Comparator Hysteresis,

Rising Edge, PIC16F15354/55 devices only.

Normal Power Mode (CxSP = 1), VDD = 3.0V,

Typical Measured Values

30

25

20

15

10

30

25

20

15

10

MAX

5

0

-5

MIN

-5

MIN

-10

-15

-20

-15

-20

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Common Mode Voltage (V)

FIGURE 38-35:

Comparator Offset, Normal

FIGURE 38-36:

Comparator Offset, Normal

Power Mode (CxSP = 1), VDD = 3.0V, Typical

Measured Values at 25°C.

Measured Values from -40°C to 125°C.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 505

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

30

50

25

45

20

15

40

MAX

10

5

25°C

125°

85°

35

30

25

20

0

-5

-40°C

-10

-15

-20

MIN

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Common Mode Voltage (V)

FIGURE 38-37:

Comparator Hysteresis,

FIGURE 38-38:

Comparator Offset, Normal

Normal Power Mode (CxSP = 1), VDD = 5.5V,

Typical Measured Values, PIC16F15354/55

devices only.

Power Mode (CxSP = 1), VDD = 5.0V, Typical

Measured Values at 25°C, PIC16F15354/55

devices only.

140

40

30

20

Max: Typical + 3ı (-40°C to +125°C)

Typical; statistical mean @ 25°C

120

Min: Typical - 3ı (-40°C to +125°C)

100

125°C

80

MAX

10

25°C

60

0

40

-40°C

-10

20

MIN

-20

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

1.7

2.0

2.3

2.6

VDD (V)

2.9

3.2

3.5

Common Mode Voltage (V)

FIGURE 38-39:

Comparator Offset, Normal

FIGURE 38-40:

Comparator Response Time

Power Mode (CxSP = 1), VDD = 5.5V, Typical

Measured Values from -40°C to 125°C,

PIC16F15354/55 devices only.

Over Voltage, Normal Power Mode (CxSP = 1),

Typical Measured Values, PIC16F15354/55

devices only.

90

1,400

Max: Typical + 3ı (-40°C to +125°C)

80

70

60

50

40

30

20

10

0

Typical; statistical mean @ 25°C

1,200

1,000

800

600

400

200

0

Min: Typical - 3ı (-40°C to +125°C)

125°C

25°C

125°C

25°C

-40°C

2.2

2.5

2.8

3.1

3.4

3.7

4.0

4.3

4.6

4.9

5.2

5.5

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

VDD (V)

FIGURE 38-41:

Comparator Response Time

FIGURE 38-42:

Comparator Output Filter

Over Voltage, Normal Power Mode (CxSP = 1),

Typical Measured Values, PIC16F15354/55

devices only.

Delay Time Over Temperature, Normal Power

Mode (CxSP = 1), Typical Measured Values,

PIC16F15354/55 devices only.

DS40001853C-page 506

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

0.025

0.02

800

700

600

500

400

300

200

100

0

Max: Typical + 3ı (-40°C to +125°C)

Typical; statistical mean @ 25°C

Min: Typical - 3ı (-40°C to +125°C)

0.015

0.01

0.005

0

125°C

-40°C

25°C

85°C

25°C

125°C

-0.005

-0.01

-0.015

-0.02

-40°C

3.4

2.2

2.5

2.8

3.1

3.7

4

4.3

4.6

4.9

5.2

5.5

0

16 32 48 64 80 96 112 128 144 160 176 192 208 224 240

VDD (V)

Output Code

FIGURE 38-43:

Comparator Output Filter

FIGURE 38-44:

Typical DAC DNL Error,

Delay Time Over Temperature, Normal Power

Mode (CxSP = 1), Typical Measured Values,

PIC16F15354/55 devices only

VDD = 3.0V, VREF = External 3V

0.00

-0.05

-0.10

-0.15

-0.20

0.45

Vref = Int. Vdd

0.4

Vref = Ext. 1.8V

Vref = Ext. 2.0V

Vref = Ext. 3.0V

0.35

0.3

0.25

0.2

Vref = Int. Vdd

Vref = Ext. 1.8V

Vref = Ext. 2.0V

Vref = Ext. 3.0V

-40°C

0.15

0.2

0.1

25°C

85°C

125°C

-0.25

-0.30

-0.35

-0.40

-0.45

0.05

0

0.1

-50

0

50

100

150

Temperature (°C)

0.0

0

14 28 42 56 70 84 98 112126140154168182196210224238252

-60

-40

-20

0

20

40

60

80

100

120

140

Output Code

Temperature (°C)

FIGURE 38-45:

Typical DAC INL Error,

FIGURE 38-46:

Absolute Value of DAC DNL

VDD = 3.0V, VREF = External 3V

Error, VDD = 3.0V, VREF= VDD

0.90

Vref = Int. Vdd

-2.1

70

60

50

40

30

20

Vref = Ext. 1.8V

Typical 25°C

-2.3

Vref = Ext. 2.0V

Vref = Ext. 3.0V

0.88

+3ı (-40°C to +125°C)

-2.5

-40

25

-2.7

0.86

-2.9

85

0.84

-3.1

125

-3.3

0.82

-3.5

0.0

1.0

2.0

3.0

4.0

5.0

Temperature (°C)

Note:

10

0.80

The FVR Stabiliztion Period applies when coming out of

RESET or exiting sleep mode.

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

0.78

-60.0

-40.0

-20.0

0.0

20.0

40.0

60.0

80.0

100.0 120.0 140.0

VDD (MV)

Temperature (°C)

FIGURE 38-47:

Absolute Value of DAC INL

FIGURE 38-48:

FVR Stabilization Period,

Error, VDD = 3.0V, VREF= VDD

PIC16LF15354/55 devices only

 2016-2018 Microchip Technology Inc.

DS40001853C-page 507

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

1.1%

1.0%

0.9%

0.8%

0.7%

0.6%

0.5%

0.4%

0.3%

0.2%

0.1%

0.0%

1.2%

1.0%

0.8%

0.6%

0.4%

0.2%

0.0%

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

V

DD (V)

VDD (V)

FIGURE 38-49:

Typical FVR Voltage 1X,

FIGURE 38-50:

FVR Voltage Error 1X,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

1.0%

0.8%

0.6%

0.4%

0.2%

0.0%

-0.2%

-0.4%

1.0%

0.8%

0.6%

0.4%

0.2%

0.0%

-0.2%

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

Typical -40°C

Typical 25°C

Typical 85°C

Typical 125°C

2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

VDD (V)

FIGURE 38-51:

FVR Voltage Error 2X,

FIGURE 38-52:

FVR Voltage Error 2X,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

1.0%

3.0%

2.0%

1.0%

0.0%

-1.0%

-2.0%

-3.0%

-4.0%

-5.0%

Typical -40°C

Typical 25°C

Typical 85°C

0.8%

Typical 125°C

0.6%

0.4%

0.2%

0.0%

-0.2%

-0.4%

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

4.7

4.8

4.9

5.0

5.1

5.2

5.3

5.4

5.5

5.6

VDD (V)

FIGURE 38-53:

FVR Voltage Error 4X,

FIGURE 38-54:

HFINTOSC Typical

PIC16F15354/55 devices only

Frequency Error, PIC16LF15354/55 devices only

DS40001853C-page 508

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

500

450

400

350

300

250

200

150

100

50

500

450

400

350

300

250

200

150

100

50

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max

Typical

Max

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

VDD (V)

2.8

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

4.0

DD (V)

4.5

5.0

5.5

6.0

V

FIGURE 38-55:

IDD, XT Oscillator 4 MHz,

FIGURE 38-56:

IDD, XT Oscillator 4 MHz,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

4.0

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

3.5

3.0

Max

2.5

2.0

2.5

Max

2.0

Typical

1.5

1.0

0.5

0.0

1.0

0.5

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

1.5

2.0

2.5

3.0

3.5

DD (V)

4.0

4.5

5.0

5.5

6.0

VDD (V)

V

FIGURE 38-57:

IDD, HS Oscillator 32 MHz,

FIGURE 38-58:

IDD, HS Oscillator 32 MHz,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

4.0

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

3.5

3.0

Max

3.0

2.5

2.0

1.5

1.0

0.5

0.0

Max

2.5

2.0

1.5

1.0

0.5

0.0

Typical

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 38-59:

IDD, HFINTOSC Mode,

FIGURE 38-60:

IDD, HFINTOSC Mode,

FOSC = 32 MHz, PIC16LF15354/55 devices only

FOSC = 32 MHz, PIC16F15354/55 devices only

 2016-2018 Microchip Technology Inc.

DS40001853C-page 509

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Max: 85°C + 3ı

Max

Typical: 25°C

Max

Typical-

Typical

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 38-61:

IDD, HFINTOSC Mode,

FIGURE 38-62:

IDD, HFINTOSC Mode,

FOSC = 16 MHz, PIC16LF15354/55 devices only

1,200

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max

1,000

Max

800

Typical

600

400

200

0

600

Typical

400

200

0

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 38-63:

IDD, HFINTOSC Idle Mode,

FIGURE 38-64:

IDD, HFINTOSC Idle Mode,

FOSC = 16 MHz, PIC16LF15354/55 devices only

FOSC = 16 MHz, PIC16F15354/55 devices only

1,200

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

Max

1,000

800

600

400

200

0

Max

800

Typical

600

400

200

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

VDD (V)

FIGURE 38-65:

IDD, HFINTOSC Doze

FIGURE 38-66:

IDD, HFINTOSC Doze

Mode, FOSC = 16 MHz, PIC16LF15354/55

devices only

Mode, FOSC = 16 MHz, PIC16F15354/55 devices

only

DS40001853C-page 510

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

4

3.5

3

2.5

2

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

1.5

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-67:

Schmitt Trigger High Values

FIGURE 38-68:

Schmitt Trigger Low Values

50

45

40

35

30

25

20

15

10

5

1.8

Typical 25°C

1.6

1.4

1.2

1

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

+3 Sigma (-40°C to

125°C)

0.8

0.6

0.4

0.2

0

1.5

2.5

3.5

VDD (V)

4.5

5.5

1.5

2.0

2.5

3.0

3.5

VDD (V)

4.0

4.5

5.0

5.5

FIGURE 38-69:

Input Level TTL Trip

FIGURE 38-70:

Rise Time, Slew Rate

Thresholds

Control Enabled

30

25

20

15

10

5

60

50

40

30

20

10

0

Typical 25°C

+3 Sigma (-40°C to

125°C)

+3 Sigma (-40°C to

125°C)

0

1.5

2.5

3.5

VDD (V)

4.5

5.5

1.5

2.5

3.5

VDD (V)

4.5

5.5

FIGURE 38-71:

Fall Time, Slew Rate Control

FIGURE 38-72:

Rise Time, Slew Rate

Enabled

Control Disabled

 2016-2018 Microchip Technology Inc.

DS40001853C-page 511

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

600

20

Typical 25°C

Max.

Max: 85°C + 3ı

18

16

14

12

10

8

500

400

300

200

100

0

+3 Sigma (-40°C to

125°C)

Typical: 25°C

6

4

Typical

3.0

2

0

1.5

2.5

3.5

VDD (V)

4.5

5.5

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.2

3.4

3.6

3.8

VDD (V)

FIGURE 38-73:

Rise Time, Slew Rate

FIGURE 38-74:

IPD Base, Low-Power Sleep

Control Disabled

Mode, PIC16LF15354/55 devices only

1.0

1.4

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

0.9

1.2

1.0

0.8

0.6

0.4

0.2

Max.

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Typical

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-75:

IPD, Watchdog Timer

FIGURE 38-76:

IPD, Watchdog Timer

(WDT), PIC16LF15354/55 devices only

(WDT), PIC16F15354/55 devices only

60

Max: 85°C + 3ı

55

50

45

40

35

30

25

20

15

10

Typical: 25°C

55

50

45

40

Max.

35

30

25

20

Max.

Typical

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

V

VDD (V)

FIGURE 38-77:

IPD, Fixed Voltage

FIGURE 38-78:

IPD, Fixed Voltage

Reference (FVR), PIC16LF15354/55 devices

only

Reference (FVR), PIC16F15354/55 devices only

DS40001853C-page 512

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

14

13

12

11

10

9

16

14

12

10

8

Max: 85°C + 3ı

Typical: 25°C

Typical

3.6

6

8

4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-79:

IPD, Brown-out Reset

FIGURE 38-80:

IPD, Brown-out Reset

(BOR), BORV = 1, PIC16LF15354/55 devices

only

(BOR), BORV = 1, PIC16F15354/55 devices

only

1.2

1.4

Max.

Max: 85°C + 3ı

Typical: 25°C

Max: 85°C + 3ı

Typical: 25°C

1.2

1

Max.

1.0

0.8

0.6

0.4

0.6

Typical

0.4

0.2

0.0

0.2

Typical

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-81:

IPD, Low-Power Brown-out

FIGURE 38-82:

IPD, Low-Power Brown-out

Reset (LPBOR = 0), PIC16LF15354/55 devices

only

Reset (LPBOR = 0), PIC16F15354/55 devices

only

40

Max: 85°C + 3ı

39

Typical: 25°C

38

36

34

32

30

28

26

24

Typical: 25°C

38

Max.

37

Max.

36

35

Typical

34

Typical

33

32

31

30

1.6

1.8

2.0

2.2

2.4

2.6

2.8

DD (V)

3.0

3.2

3.4

3.6

3.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

V

VDD (V)

FIGURE 38-83:

IPD, Comparator,

FIGURE 38-84:

IPD, Comparator,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

 2016-2018 Microchip Technology Inc.

DS40001853C-page 513

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

30

25

20

15

10

5

1

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Max.

Max: 85°C + 3ı

Max.

Max: 85°C + 3ı

Typical: 25°C

Typical

0

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

6.0

2.0

2.5

3.0

3.5

4.0

VDD (V)

4.5

5.0

5.5

6.0

FIGURE 38-85:

Ipd Base, 01,

FIGURE 38-86:

Ipd Base, 11,

PIC16F15354/55 devices only

36,000

35,000

34,000

33,000

32,000

31,000

30,000

29,000

28,000

36,000

35,000

34,000

33,000

32,000

31,000

30,000

29,000

28,000

Typical 25°C

+3 Sigma (-40°C to 125°C)

-3 Sigma (-40°C to 125°C)

+3 Sigma (-40°C to 125°C)

-3 Sigma (-40°C to 125°C)

2.2 2.4 2.6 2.8

3

3.2 3.4 3.6 3.8

4

4.2 4.4 4.6 4.8

5

5.2 5.4 5.6

1.7

2.0

2.3

2.6

VDD (V)

2.9

3.2

3.5

VDD (V)

FIGURE 38-87:

LFINTOSC Frequency,

FIGURE 38-88:

LFINTOSC Frequency,

PIC16LF15354/55 devices only

PIC16F15354/55 devices only

4.00%

1.6

1.55

1.5

Max: Typical + 3ı (-40°C to +125°C)

Typical; statistical mean @ 25°C

3.00%

Min: Typical - 3ı (-40°C to +125°C)

+3 Sigma

2.00%

1.00%

0.00%

-1.00%

-2.00%

-3.00%

-4.00%

1.45

Typical

1.4

1.35

1.3

-3 Sigma

Max

1.25

1.2

Min

Average

-60

-40

-20

0

20

40

60

80

100

120

140

-32

-24

-16

-8

Center

OSCTUNE Setting

0

8

16

24

32

Max

Min

Temperature (°C)

FIGURE 38-89:

OCSTUNE Center

FIGURE 38-90:

Power-on Reset Release

Frequency, PIC16LF15354/55 devices only

Voltage

DS40001853C-page 514

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

1.64

1.8

Max: Typical + 3ı

Typical: 25°C

74.0

72.0

70.0

68.0

66.0

64.0

62.0

60.0

1.63

1.75

Min: Typical - 3ı

1.62

+3 Sigma

1.7

1.61

Typical

1.6

1.65

1.59

1.6

1.58

1.55

-3 Sigma

60

-40

-60

-20

0

20

40

80

100

120

140

Typical 25°C

+ 3ı (-40°C to +125°C)

- 3ı (-40°C to +125°C)

Temperature (°C)

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-40

-20

0

20

40

60

80

100

120

VDD (V)

Temperature (°C)

FIGURE 38-91:

Power-on Reset Rearm

FIGURE 38-92:

PWRT Period,

Voltage, Normal Power Mode, PIC16F15354/55

devices only

PIC16F15354/55 devices only

6

Graph represents 3ı Limits

75.0

73.0

71.0

69.0

67.0

65.0

63.0

5

-40°C

4

Typical

3

125°C

2

1

0

61.0

Typical 25°C

+ 3ı (-40°C to +125°C)

- 3ı (-40°C to +125°C)

59.0

57.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

-45

-40

-35

-30

-25

-20

-15

-10

-5

0

VDD (V)

I

OH (mA)

FIGURE 38-93:

PWRT Period,

FIGURE 38-94:

VOH Vs. IOH Over

PIC16LF15354/55 devices only

Temperature, VDD = 5.5V, PIC16F15354/55

devices only

3.5

3

Graph represents 3ı Limits

3.0

2.5

2

1

0

-40°C

2.0

1.5

1.0

0.5

0.0

Typical

125°C

Typical

-40°C

-30

-25

-20

-15

IOH (mA)

-10

-5

0

10

20

30

IOL (mA)

40

50

60

FIGURE 38-95:

VOL Vs. IOL Over

FIGURE 38-96:

VOH Vs. IOH Over

Temperature, VDD = 5.5V, PIC16F15354/55

devices only

Temperature, VDD = 3.0V

 2016-2018 Microchip Technology Inc.

DS40001853C-page 515

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Graph represents 3ı Limits

Typical

-40°C

125°C

Typical

-40°C

-8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5

0

5

10

15

20

25

30

IOL (mA)

35

40

45

50

55

60

IOH (mA)

FIGURE 38-97:

VOL Vs. IOL Over

FIGURE 38-98:

VOH Vs. IOH Over

Temperature, VDD = 3.0V

Temperature, VDD = 1.8V, PIC16LF15354/55

devices only

1.8

18

Graph represents 3ı Limits

Typical 25°C

1.6

+3ı (-40°C to +125°C)

17

1.4

1.2

16

15

14

13

12

Typical

125°C

-40°C

1

0.8

0.6

0.4

0.2

0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

VDD (V)

IOL (mA)

FIGURE 38-99:

VOL Vs. IOL Over

FIGURE 38-100:

Wake From Sleep,

Temperature, VDD = 3.0V, PIC16LF15354/55

devices only

VREGPM = 0, HFINTOSC = 4 MHz,

PIC16F15354/55 devices only

28

27

26

25

24

23

22

21

20

120

Typical 25°C

+3ı (-40°C to +125°C)

110

+3ı (-40°C to +125°C)

100

90

80

70

60

50

40

30

20

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-101:

Wake from Sleep,

FIGURE 38-102:

Wake from Sleep,

VREGPM = 1, HFINTOSC = 4 MHz,

PIC16F15354/55 devices only

VREGPM = 1, HFINTOSC = 16 MHZ,

PIC16F15354/55 devices only

DS40001853C-page 516

 2016-2018 Microchip Technology Inc.

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

700

650

600

550

500

450

400

350

300

120

110

100

90

Typical 25°C

+3ı (-40°C to +125°C)

+ 3ı (-40°C to +125°C)

80

70

60

50

40

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

VDD (V)

FIGURE 38-103:

Wake from Sleep,

FIGURE 38-104:

Wake from Sleep,

VREGPM = 1, HFINTOSC = 16 MHz,

PIC16F15354/55 devices only

VREGPM = 1, PIC16F15354/55 devices only

700

Typical 25°C

+ 3ı (-40°C to +125°C)

650

600

550

500

450

400

350

300

650

600

550

500

450

400

350

300

+ 3ı (-40°C to +125°C)

2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6

1.7

2.2

2.7

VDD (V)

3.2

3.7

VDD (V)

FIGURE 38-105:

Wake from Sleep,

FIGURE 38-106:

Wake from Sleep,

PIC16LF15354/55 devices only

VREGPM = 1, LFINTOSC, PIC16F15354/55

devices only

700

650

600

550

500

450

400

350

300

4.2

4.1

4.0

3.9

Typical 25°C

+ 3ı (-40°C to +125°C)

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

3.8

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

1.7

2.2

2.7

VDD (V)

3.2

3.7

VDD (V)

FIGURE 38-107:

Wake from Sleep,

FIGURE 38-108:

Watchdog Timer Time-out

LFINTOSC, PIC16LF15354/55 devices only

Period, PIC16F15354/55 devices only

 2016-2018 Microchip Technology Inc.

DS40001853C-page 517

PIC16LF15354/55

Note: Unless otherwise noted, VIN = 5V, FOSC = 300 kHz, CIN = 0.1 µF, TA = 25°C.

300.0

4.2

Typical 25°C

+ 3ı (-40°C to +125°C)

- 3ı (-40°C to +125°C)

250.0

200.0

150.0

100.0

50.0

4.1

4.0

3.9

3.8

Typical 25°C

+3ı (-40°C to +125°C)

-3ı (-40°C to +125°C)

0.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

2.1

2.4

2.7

3.0

3.3

3.6

3.9

4.2

4.5

4.8

5.1

5.4

5.7

VDD (V)

FIGURE 38-109:

Watchdog Timer Time-out

FIGURE 38-110:

Weak Pull-up Current,

Period, PIC16LF15354/55 devices only

PIC16F15354/55 devices only

180.0

-3.450

-3.500

-3.550

-3.600

-3.650

-3.700

-3.750

-3.800

-3.850

-3.900

Typical 25°C

160.0

+ 3ı (-40°C to +125°C)

Typical

- 3ı (-40°C to +125°C)

140.0

120.0

100.0

80.0

60.0

40.0

20.0

0.0

+3 Sigma

-3 Sigma

-60

-40

-20

0

20

40

60

80

100

120

140

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

Temperature (^oC)

VDD (V)

FIGURE 38-111:

Weak Pull-up Current,

FIGURE 38-112:

High Range Temperature

PIC16LF15354/55 devices only

Indicator Voltage Sensitivity Across Temperature

-2.300

-2.350

-2.400

-2.450

-2.500

-2.550

-2.600

Typical

+3 Sigma

-3 Sigma

-60

-40

-20

0

20

40

60

80

100

120

140

Temperature (^oC)

FIGURE 38-113:

Low Range Temperature

Indicator Voltage Sensitivity Across Temperature

DS40001853C-page 518

 2016-2018 Microchip Technology Inc.

PIC16(L)F15354/55

39.1 MPLAB X Integrated Development

Environment Software

39.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

hardware development tool that runs on Windows^®,

Linux and Mac OS^®X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

• Integrated Development Environment

- MPLAB^®X IDE Software

- MPLAB^®XPRESS IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

• Color syntax highlighting

- PICkit™ 3

• Smart code completion makes suggestions and

provides hints as you type

• Device Programmers

- MPLAB PM3 Device Programmer

• Automatic code formatting based on user-defined

rules

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Live parsing

• Third-party development tools

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

 2016-2018 Microchip Technology Inc.

DS40001853C-page 519

PIC16(L)F15354/55

39.2 MPLAB XC Compilers

39.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16, and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other relo-

catable object files and archives to create an execut-

able file. MPLAB XC Compiler uses the assembler to

produce its object file. Notable features of the assem-

bler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

39.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

39.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

 2016-2018 Microchip Technology Inc.

DS40001853C-page 520

PIC16(L)F15354/55

39.6 MPLAB X SIM Software Simulator

39.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PIC MCUs and dsPIC DSCs on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a comprehensive stimulus controller. Registers can be

logged to files for further run-time analysis. The trace

buffer and logic analyzer display extend the power of

the simulator to record and track program execution,

actions on I/O, most peripherals and internal registers.

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the MPLAB

IDE.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The soft-

ware simulator offers the flexibility to develop and

debug code outside of the hardware laboratory envi-

ronment, making it an excellent, economical software

development tool.

39.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit 3 allows debugging and program-

ming of PIC and dsPIC Flash microcontrollers at a most

affordable price point using the powerful graphical user

interface of the MPLAB IDE. The MPLAB PICkit 3 is

connected to the design engineer’s PC using a full-

speed USB interface and can be connected to the tar-

get via a Microchip debug (RJ-11) connector (compati-

ble with MPLAB ICD 3 and MPLAB REAL ICE). The

connector uses two device I/O pins and the Reset line

to implement in-circuit debugging and In-Circuit Serial

Programming™ (ICSP™).

39.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

39.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a mod-

ular, detachable socket assembly to support various

package types. The ICSP cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set

code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradeable through future firm-

ware downloads in MPLAB X IDE. MPLAB REAL ICE

offers significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 521

PIC16(L)F15354/55

39.11 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

39.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide applica-

tion firmware and source code for examination and

modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent^®and Olimex

• Embedded Ethernet Solutions from companies,

such as EZ Web Lynx, WIZnet and IPLogika^®

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has a line of evaluation kits and demonstra-

®

tion software for analog filter design, KEELOQ security

ICs, CAN, IrDA^®, PowerSmart battery management,

SEEVAL^®evaluation system, Sigma-Delta ADC, flow

rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 522

PIC16(L)F15354/55

40.0 PACKAGING INFORMATION

40.1 Package Marking Information

28-Lead SPDIP (.300”)

Example

PIC16F15354

/SP

e

3

YYWWNNN

28-Lead SOIC (7.50 mm)

Example

XXXXXXXXXXXXXXXXXXXX

PIC16LF15354

/SO _e

3

YYWWNNN

1525017

28-Lead SSOP (5.30 mm)

Example

PIC16F15354

/SS

e

3

1525017

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 523

PIC16(L)F15354/55

40.1 Package Marking Information (Continued)

28-Lead UQFN (4x4x0.5 mm) and (6x6 mm)

Example

PIC16

PIN 1

F15354

e

3

/MV

525017

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC^®designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 524

PIC16(L)F15354/55

The following sections give the technical details of the packages.

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 2016-2018 Microchip Technology Inc.

DS40001853C-page 525

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 526

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 527

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 528

PIC16(L)F15354/55

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 2016-2018 Microchip Technology Inc.

DS40001853C-page 529

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 530

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 531

PIC16(L)F15354/55

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2016-2018 Microchip Technology Inc.

DS40001853C-page 532

PIC16(L)F15354/55

 2016-2018 Microchip Technology Inc.

DS40001853C-page 533

PIC16(L)F15354/55

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A (07/2016)

Initial release of the document.

Revision B (09/2016)

Updated SFR table. Updated cover page. Added

Figure 4-2. Updated Example 13-5; Figures 4-1, 4-3, 7-

1, 8-3, 13-4,13-8, 17-1, 18-1 and 22-1; Registers 5-3,

5-4, 5-7, 9-5, 10-13, 11-4, 13-1, 13-3, 13-5, 14-5, 14-9,

14-11, 14-13, 14-26,15-3, and 20-3; Sections 1.0, 3.0,

3.4, 4.1.1, 4.2, 4.2.5, 4.3, 4.3.1, 4.3.2, 4.3.2.1, 5.1, 5.4,

6.1, 6.2, 6.3, 7.0, 7.1, 7.14, 8.4, 8.4.2, 8.5.1, 8.11, 8.12,

10.1, 13.2.2., 13.3.2, 13.3.6, 14.8, 14.8.1, 14.8.2, 16.0,

18.2, 19.5, 29.0, 29.1.1, and 33.0; Tables 3-4, 4-2, 4-4,

4-5, 4-6, 4-7, 4-8, 4-10, 5-1, 7-3, 7-4, 13-2, 13-3, 15-2,

15-3 and 37-6. Added Section 3.2.5. Removed Figure

13-7. General typo and formatting corrections.

Revision C (01/2018)

Updated Table 3, 4-5 and 6-1. Updated Register 5-4.

Added second Indirect addressing figure in memory

chapter. Updated Equation 19-1 (sensor Temperature)

Updated Register 18-1 (FVRCON), Updated 19.2.1.1,

Removed Example 19-1 (Temp Sens)

Replaced PGC/PGD with ICSPCLK/ICSPDAT;

Revised Section 9.2.2.3 LFINSTOSC; Revised Table

15-1 and 15-2 (PPS Input Signal Routing Options);

Table 15-6 Summary of Registers/PPS Module;

Revised Example 20-1 ADC Conversion; Added note

to Section 20.1.2 Channel Selection; Revised Section

27.0 Timer2 Module; Table 37-11, revised RST06.

Removed Section 20.2.3 (Terminating a Conversation)

Added char graphs. Updated the Electrical Specs

chapter: Absolute Maximum Ratings and Tables 37-1,

37-2, 37-3, 37-4, 37-5, 37-6, 37-7, 37-8, 37-11, 37-12,

37-14, 37-16, 37-17, 37-18, 37-19, 37-20, 37-21, 37-

22. General typo and formatting corrections.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 534

PIC16(L)F15354/55

THE MICROCHIP WEBSITE

CUSTOMER SUPPORT

Microchip provides online support via our website at

www.microchip.com. This website is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the website contains the following information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata, appli-

cation notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers should contact their distributor, representa-

tive or Field Application Engineer (FAE) for support.

Local sales offices are also available to help custom-

ers. A listing of sales offices and locations is included in

the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the website

at: http://www.microchip.com/support

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of Micro-

chip sales offices, distributors and factory repre-

sentatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a spec-

ified product family or development tool of interest.

To register, access the Microchip website at

www.microchip.com. Under “Support”, click on “Cus-

tomer Change Notification” and follow the registration

instructions.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 535

PIC16(L)F15354/55

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

(1)

[X]

PART NO.

X

/XX

XXX

-

Examples:

a) PIC16F15354- E/P

Device Tape and Reel

Option

Temperature

Range

Package

Pattern

Extended temperature

PDIP package

Device:

PIC16F15354, PIC16LF15354

PIC16F15355, PIC16LF15355

Tape and Reel

Option:

Blank = Standard packaging (tube or tray)

T

= Tape and Reel⁽¹⁾

Temperature

Range:

I

E

=

-40C to +85C (Industrial)

-40C to +125C (Extended)

Package:⁽²⁾

MV

SO

SP

SS

= 28-lead UQFN 4x4mm

= 28-lead SOIC

= 28-lead SPDIP

= 28-lead SSOP

Note 1:

Tape and Reel identifier only appears in

the catalog part number description. This

identifier is used for ordering purposes and

is not printed on the device package.

Check with your Microchip Sales Office

for package availability with the Tape and

Reel option.

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

2:

Small form-factor packaging options may

be available. Check

www.microchip.com/packaging for small-

form factor package availability, or contact

your local Sales Office.

 2016-2018 Microchip Technology Inc.

DS40001853C-page 536

PIC16(L)F15354/55

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT

logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,

Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK

MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST

logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32

logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,

SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are

registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,

CryptoAuthentication, CryptoCompanion, CryptoController,

dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,

ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-

Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,

MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,

PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,

RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial

Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,

Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-2562-5

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

== ISO/TS 16949 ==

 2016-2018 Microchip Technology Inc.

DS40001853C-page 537

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-67-3636

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7289-7561

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

 2016-2018 Microchip Technology Inc.

DS40001853C-page 538

10/25/17


型号：	PIC16F15354T-I/MVQTP
厂家：	MICROCHIP
描述：	Full-Featured 28-Pin Microcontrollers 微控制器
文件：	总538页 (文件大小：5877K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F15354T-I/MVQTP [MICROCHIP]

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