PIC16F628A-I/ML [MICROCHIP]
FLASH-Based 8-Bit CMOS Microcontrollers; 基于闪存的8位CMOS微控制器
| 型号： | PIC16F628A-I/ML |
| 厂家： | 
MICROCHIP |
| 描述： | FLASH-Based 8-Bit CMOS Microcontrollers |
| 文件： | 总168页 (文件大小：3574K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16F627A/628A/648A
Data Sheet
FLASH-Based
8-Bit CMOS Microcontrollers
2002 Microchip Technology Inc.
Preliminary
DS40044A
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-
edge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
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Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical com-
ponents in life support systems is not authorized except with
express written approval by Microchip. No licenses are con-
veyed, implicitly or otherwise, under any intellectual property
rights.
Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,
MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
®
PICmicro 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS40044A - page ii
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
18-pin FLASH-Based 8-Bit CMOS Microcontrollers
High Performance RISC CPU:
Low Power Features:
• Operating speeds from DC - 20 MHz
• Interrupt capability
• Standby Current:
- ±00 nA @ 2.0V, typical
• Operating Current:
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• 35 single word instructions
- ±2 µA @ 32 kHz, 2.0V, typical
- ±20 µA @ ± MHz, 2.0V, typical
• Watchdog Timer Current
- ± µA @ 2.0V, typical
- All instructions single cycle except branches
Special Microcontroller Features:
• Timer± oscillator current:
- ±.2 µA @ 32 kHz, 2.0V, typical
• Dual Speed Internal Oscillator:
• Internal and external oscillator options
- Precision Internal 4 MHz oscillator factory
calibrated to ±±1
- Run-time selectable between 4 MHz and
37 kHz
- Low Power Internal 37 kHz oscillator
- External Oscillator support for crystals and
resonators.
- 4 µs wake-up from SLEEP, 3.0V, typical
Peripheral Features:
• Power saving SLEEP mode
• Programmable weak pull-ups on PORTB
• Multiplexed Master Clear/Input-pin
• ±6 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
• Watchdog Timer with independent oscillator for
reliable operation
- Two analog comparators
• Low voltage programming
- Programmable on-chip voltage reference
(VREF) module
• In-Circuit Serial Programming™ (via two pins)
• Programmable code protection
• Brown-out Reset
- Selectable internal or external reference
- Comparator outputs are externally accessible
• Power-on Reset
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• Power-up Timer and Oscillator Start-up Timer
• Wide operating voltage range. (2.0 - 5.5V)
• Industrial and extended temperature range
• High Endurance FLASH/EEPROM Cell
- ±00,000 write FLASH endurance
- ±,000,000 write EEPROM endurance
- ±00 year data retention
• Timer±: ±6-bit timer/counter with external crystal/
clock capability
• Timer2: 8-bit timer/counter with 8-bit period regis-
ter, prescaler and postscaler
• Capture, Compare, PWM module
- ±6-bit Capture/Compare
- ±0-bit PWM
• Addressable Universal Synchronous/Asynchro-
nous Receiver/Transmitter USART/SCI
Program
Data Memory
Memory
CCP
Timers
8/16-bit
Device
I/O
USART
Comparators
(PWM)
FLASH
(words)
SRAM
EEPROM
(bytes)
(bytes)
PIC16F627A
PIC16F628A
PIC16F648A
1024
2048
4096
224
224
256
128
128
256
16
16
16
1
1
1
Y
Y
Y
2
2
2
2/1
2/1
2/1
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 1
PIC16F627A/628A/648A
Pin Diagrams
PDIP, SOIC
1
18
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/TOCKI/CMP2
RA5/MCLR/VPP
VSS
RA1/AN1
RA0/AN0
17
16
2
3
4
5
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
15
14
13
12
VDD
RB0/INT
6
RB7/T1OSI/PGD
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
RB6/T1OSO/T1CKI/PGC
7
8
RB5
11
10
9
RB4/PGM
SSOP
28-Pin QFN
RA5/MCLR/VDD
VSS
1
21
20
19
18
17
16
15
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
PIC16F627A/628A/648A
NC
NC
2
3
PIC16F627A/628A
PIC16F648A
4
NC
VSS
VDD
5
6
7
NC
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB0/INT
DS40044A-page 2
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16F627A/628A/648A Device Varieties................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 31
6.0 Timer0 Module ........................................................................................................................................................................... 45
7.0 Timer1 Module ........................................................................................................................................................................... 48
8.0 Timer2 Module ........................................................................................................................................................................... 52
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 55
10.0 Comparator Module.................................................................................................................................................................... 61
11.0 Voltage Reference Module......................................................................................................................................................... 67
12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 69
13.0 Data EEPROM Memory ............................................................................................................................................................. 89
14.0 Special Features of the CPU...................................................................................................................................................... 93
15.0 Instruction Set Summary.......................................................................................................................................................... 111
16.0 Development Support............................................................................................................................................................... 125
17.0 Electrical Specifications............................................................................................................................................................ 131
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 147
19.0 Packaging Information.............................................................................................................................................................. 149
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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2002 Microchip Technology Inc.
Preliminary
DS40044A-page 3
PIC16F627A/628A/648A
NOTES:
DS40044A-page 4
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
HS is for High-Speed crystals. The EC mode is for an
external clock source.
1.0
GENERAL DESCRIPTION
The PIC±6F627A/628A/648A are ±8-Pin FLASH-
based members of the versatile PIC±6CXX family of
low cost, high performance, CMOS, fully-static, 8-bit
microcontrollers.
The SLEEP (Power-down) mode offers power savings.
Users can wake-up the chip from SLEEP through sev-
eral external interrupts, internal interrupts and
RESETS.
®
All PICmicro microcontrollers employ an advanced
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lock-
up.
RISC architecture. The PIC±6F627A/628A/648A have
enhanced core features, eight-level deep stack, and
multiple internal and external interrupt sources. The
separate instruction and data buses of the Harvard
architecture allow a ±4-bit wide instruction word with
the separate 8-bit wide data. The two-stage instruction
pipeline allows all instructions to execute in a single-
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available, complemented by a large register
set.
Table ±-± shows the features of the PIC±6F627A/
628A/648A mid-range microcontroller families.
A simplified block diagram of the PIC±6F627A/628A/
648A is shown in Figure 3-±.
The PIC±6F627A/628A/648A series fits in applications
ranging from battery chargers to low power remote
sensors. The FLASH technology makes customizing
application programs (detection levels, pulse genera-
tion, timers, etc.) extremely fast and convenient. The
small footprint packages makes this microcontroller
series ideal for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC±6F627A/628A/648A
very versatile.
PIC±6F627A/628A/648A microcontrollers typically
achieve a 2:± code compression and a 4:± speed
improvement over other 8-bit microcontrollers in their
class.
PIC±6F627A/628A/648A devices have integrated fea-
tures to reduce external components, thus reducing
system cost, enhancing system reliability and reducing
power consumption.
1.1
Development Support
The PIC±6F627A/628A/648A has 8 oscillator configu-
rations. The single-pin RC oscillator provides a low cost
solution. The LP oscillator minimizes power consump-
tion, XT is a standard crystal, and INTOSC is a self-
contained precision two-speed internal oscillator. The
The PIC±6F627A/628A/648A family is supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a low cost in-circuit debugger, a low
cost development programmer and a full-featured pro-
grammer. A Third Party “C” compiler support tool is
also available.
TABLE 1-1:
PIC16F627A/628A/648A FAMILY OF DEVICES
PIC16F627A
PIC16F628A
PIC16F648A
PIC16LF627A
4
PIC16LF628A
4
PIC16LF648A
4
Clock
Maximum Frequency
of Operation (MHz)
20
20
20
FLASH Program Mem-
ory (words)
1024
224
2048
224
4096
256
1024
224
2048
224
4096
256
Memory
RAM Data Memory
(bytes)
EEPROM Data Mem-
ory (bytes)
128
128
256
128
128
256
Timer module(s)
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
TMR0, TMR1,
TMR2
Comparator(s)
2
1
2
1
2
1
2
1
2
1
2
1
Peripherals Capture/Compare/
PWM modules
Serial Communications
USART
Yes
USART
Yes
USART
Yes
USART
Yes
USART
Yes
USART
Yes
Internal Voltage
Reference
Interrupt Sources
I/O Pins
10
16
10
16
10
16
10
16
10
16
10
16
Features
Voltage Range (Volts)
Brown-out Reset
Packages
3.0-5.5
Yes
3.0-5.5
Yes
3.0-5.5
Yes
2.0-5.5
Yes
2.0-5.5
Yes
2.0-5.5
Yes
18-pin DIP,
SOIC, 20-pin
SSOP,
18-pin DIP,
SOIC, 20-pin
SSOP,
18-pin DIP,
SOIC, 20-pin
SSOP,
18-pin DIP,
SOIC, 20-pin
SSOP,
18-pin DIP,
SOIC, 20-pin
SSOP,
18-pin DIP,
SOIC, 20-pin
SSOP,
28-pin QFN
28-pin QFN
28-pin QFN
28-pin QFN
28-pin QFN
28-pin QFN
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability.
All PIC16F627A/628A/648A Family devices use serial programming with clock pin RB6 and data pin RB7.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 5
PIC16F627A/628A/648A
NOTES:
DS40044A-page 6
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
2.0
PIC16F627A/628A/648A
DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC±6F627A/628A/648A
Product Identification System, at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1
FLASH Devices
FLASH devices can be erased and re-programmed
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
A further advantage of the electrically erasable FLASH
is that it can be erased and reprogrammed in-circuit, or
by device programmers, such as Microchip's
®
®
PICSTART Plus, or PRO MATE II programmers.
2.2
Quick-Turnaround-Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are standard FLASH devices
but with all program locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more
details.
2.3
Serialized Quick-Turnaround-
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number, which can serve as an entry-code,
password or ID number.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 7
PIC16F627A/628A/648A
NOTES:
DS40044A-page 8
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC±6F627A/628A/648A
family can be attributed to a number of architectural
features commonly found in RISC microprocessors. To
begin with, the PIC±6F627A/628A/648A uses a Har-
vard architecture, in which program and data are
accessed from separate memories using separate bus-
ses. This improves bandwidth over traditional von Neu-
mann architecture where program and data are fetched
from the same memory. Separating program and data
memory further allows instructions to be sized differ-
ently than 8-bit wide data word. Instruction opcodes are
±4-bits wide making it possible to have all single word
instructions. A ±4-bit wide program memory access
bus fetches a ±4-bit instruction in a single cycle. A two-
stage pipeline overlaps fetch and execution of instruc-
tions. Consequently, all instructions (35) execute in a
single-cycle (200 ns @ 20 MHz) except for program
branches.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, bit in subtraction. See the SUBLW and
SUBWFinstructions for examples.
A simplified block diagram is shown in Figure 3-±, and
a description of the device pins in Table 3-2.
Two types of data memory are provided on the
Non-volatile
Table 3-± lists device memory sizes (FLASH, Data and
EEPROM).
PIC±6F627A/628A/648A
devices.
EEPROM data memory is provided for long term stor-
age of data such as calibration values, look up table
data, and any other data which may require periodic
updating in the field. These data are not lost when
power is removed. The other data memory provided is
regular RAM data memory. Regular RAM data memory
is provided for temporary storage of data during normal
operation. Data are lost when power is removed.
TABLE 3-1:
DEVICE MEMORY LIST
Memory
Device
FLASH
RAM
Data
EEPROM
Data
Program
PIC16F627A
PIC16F628A
PIC16F648A
PIC16LF627A
PIC16LF628A
PIC16LF648A
1024 x 14
2048 x 14
4096 x 14
1024 x 14
2048 x 14
4096 x 14
224 x 8
224 x 8
256 x 8
224 x 8
224 x 8
256 x 8
128 x 8
128 x 8
256 x 8
128 x 8
128 x 8
256 x 8
The PIC±6F627A/628A/648A can directly or indirectly
address its register files or data memory. All Special
Function Registers, including the program counter, are
mapped in the data memory. The PIC±6F627A/628A/
648A have an orthogonal (symmetrical) instruction set
that makes it possible to carry out any operation, on
any register, using any Addressing mode. This sym-
metrical nature and lack of ‘special optimal situations’
make programming with the PIC±6F627A/628A/648A
simple yet efficient. In addition, the learning curve is
reduced significantly.
The PIC±6F627A/628A/648A devices contain an 8-bit
ALU and working register. The ALU is a general pur-
pose arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 9
PIC16F627A/628A/648A
FIGURE 3-1:
BLOCK DIAGRAM
13
8
Data Bus
Program Counter
FLASH
Program
Memory
RAM
8-Level Stack
(13-bit)
File
Registers
Program
Bus
14
PORTA
RAM Addr (1)
9
Addr MUX
RA0/AN0
Instruction reg
RA1/AN1
Indirect
Addr
7
Direct Addr
RA2/AN2/VREF
RA3/AN3/CMP1
RA4/T0CK1/CMP2
RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
8
FSR reg
STATUS reg
8
3
PORTB
MUX
Power-up
Timer
RB0/INT
RB1/RX/DT
RB2/TX/CK
RB3/CCP1
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
Power-on
Reset
RB4/PGM
RB5
8
Timing
Generation
Watchdog
Timer
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Detect
Low-Voltage
Programming
MCLR VDD, VSS
Timer0
Timer1
Timer2
Comparator
CCP1
USART
Data EEPROM
VREF
Note: Higher order bits are from the STATUS register.
DS40044A-page 10
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 3-2:
Name
PIC16F627A/628A/648A PINOUT DESCRIPTION
Function Input Type Output Type
Description
Bi-directional I/O port
RA0/AN0
RA0
AN0
ST
AN
ST
AN
ST
AN
—
CMOS
—
Analog comparator input
Bi-directional I/O port
Analog comparator input
Bi-directional I/O port
Analog comparator input
VREF output
RA±/AN±
RA±
CMOS
—
AN±
RA2/AN2/VREF
RA2
CMOS
—
AN2
VREF
RA3
AN
RA3/AN3/CMP±
ST
AN
—
CMOS
—
Bi-directional I/O port
Analog comparator input
Comparator ± output
Bi-directional I/O port
Timer0 clock input
AN3
CMP±
RA4
CMOS
OD
RA4/T0CKI/CMP2
ST
ST
—
T0CKI
CMP2
—
OD
Comparator 2 output
Input port
ST
—
RA5/MCLR/VPP
RA5
Master clear. When configured as MCLR, this
pin is an active low RESET to the device.
Voltage on MCLR/VPP must not exceed VDD
during normal device operation.
MCLR
ST
—
VPP
RA6
—
ST
—
—
Programming voltage input.
Bi-directional I/O port
RA6/OSC2/CLKOUT
CMOS
XTAL
OSC2
Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT
—
CMOS
In RC/INTOSC mode, OSC2 pin can output
CLKOUT, which has ±/4 the frequency of
OSC±
RA7/OSC±/CLKIN
RA7
OSC±
CLKIN
RB0
ST
XTAL
ST
CMOS
—
Bi-directional I/O port
Oscillator crystal input
—
External clock source input. RC biasing pin.
RB0/INT
TTL
CMOS
Bi-directional I/O port. Can be software pro-
grammed for internal weak pull-up.
INT
ST
—
External interrupt.
RB±/RX/DT
RB±
TTL
CMOS
Bi-directional I/O port. Can be software pro-
grammed for internal weak pull-up.
RX
DT
ST
ST
—
USART receive pin
CMOS
CMOS
Synchronous data I/O.
RB2/TX/CK
RB3/CCP±
RB2
TTL
Bi-directional I/O port. Can be software pro-
grammed for internal weak pull-up.
TX
CK
—
ST
CMOS
CMOS
CMOS
USART transmit pin
Synchronous clock I/O.
RB3
TTL
Bi-directional I/O port. Can be software pro-
grammed for internal weak pull-up.
CCP±
ST
CMOS
Capture/Compare/PWM I/O
Legend:
O = Output
— = Not used
TTL = TTL Input
CMOS = CMOS Output
P
= Power
I
OD
= Input
= Open Drain Output
ST = Schmitt Trigger Input
AN = Analog
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 11
PIC16F627A/628A/648A
TABLE 3-2:
Name
PIC16F627A/628A/648A PINOUT DESCRIPTION
Function Input Type Output Type
Description
RB4/PGM
RB4
TTL
ST
CMOS
—
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
PGM
Low voltage programming input pin. When
low voltage programming is enabled, the
interrupt-on-pin change and weak pull-up
resistor are disabled.
RB5
RB5
RB6
TTL
TTL
CMOS
CMOS
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
RB6/T±OSO/T±CKI/PGC
T±OSO
T±CKI
PGC
—
ST
XTAL
—
Timer± oscillator output.
Timer± clock input.
ST
—
ICSP Programming Clock.
RB7/T±OSI/PGD
RB7
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
T±OSI
PGD
VSS
XTAL
ST
—
CMOS
—
Timer± oscillator input.
ICSP Data I/O
VSS
VDD
Power
Power
Ground reference for logic and I/O pins
Positive supply for logic and I/O pins
VDD
—
Legend:
O = Output
— = Not used
TTL = TTL Input
CMOS = CMOS Output
P
= Power
I
OD
= Input
= Open Drain Output
ST = Schmitt Trigger Input
AN = Analog
DS40044A-page 12
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
3.1
Clocking Scheme/Instruction
Cycle
3.2
Instruction Flow/Pipelining
An instruction cycle consists of four Q cycles (Q±, Q2,
Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO)
then two cycles are required to complete the instruction
(Example 3-±).
The clock input (OSC±/CLKIN/RA7 pin) is internally
divided by four to generate four non-overlapping
quadrature clocks namely Q±, Q2, Q3 and Q4. Inter-
nally, the program counter (PC) is incremented every
Q±, the instruction is fetched from the program memory
and latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q± through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
A fetch cycle begins with the program counter (PC)
incrementing in Q±.
In the execution cycle, the fetched instruction is latched
into the Instruction Register (IR) in cycle Q±. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Internal
phase
clock
Q4
PC
PC
PC+1
PC+2
CLKOUT
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, 3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 13
PIC16F627A/628A/648A
NOTES:
DS40044A-page 14
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2
Data Memory Organization
4.0
MEMORY ORGANIZATION
The data memory (Figure 4-2 and Figure 4-3) is
partitioned into four banks, which contain the general
purpose registers and the Special Function Registers
(SFR). The SFR’s are located in the first 32 locations of
each Bank. There are general purpose registers imple-
mented as static RAM in each Bank. Table 4-± lists the
general purpose register available in each of the four
banks.
4.1
Program Memory Organization
The PIC±6F627A/628A/648A has a ±3-bit program
counter capable of addressing an 8K x ±4 program
memory space. Only the first ±K x ±4 (0000h - 03FFh)
for the PIC±6F627A, 2K x ±4 (0000h - 07FFh) for the
PIC±6F628A and 4K x ±4 (0000h - 0FFFh) for the
PIC±6F648A are physically implemented. Accessing a
location above these boundaries will cause a wrap-
around within the first ±K x ±4 space (PIC±6F627A), 2K
TABLE 4-1:
GENERAL PURPOSE STATIC
RAM REGISTERS
x
±4 space (PIC±6F628A) or 4K x ±4 space
(PIC±6F648A). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 4-±).
PIC16F627A/628A
PIC16F648A
Bank0
Bank±
Bank2
Bank3
20-7Fh
A0h-FF
20-7Fh
A0h-FF
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK
±20h-±4Fh, ±70h-±7Fh
±F0h-±FFh
±20h-±7Fh
±F0h-±FFh
PC<±2:0>
±3
CALL, RETURN
RETFIE, RETLW
Addresses F0h-FFh, ±70h-±7Fh and ±F0h-±FFh are
implemented as common RAM and mapped back to
addresses 70h-7Fh.
Stack Level ±
Stack Level 2
Table 4-2 lists how to access the four banks of registers
via the STATUS Register bits RP± and RP0.
Stack Level 8
RESET Vector
TABLE 4-2:
ACCESS TO BANKS OF
REGISTERS
000h
RP1
RP0
Bank0
Bank±
Bank2
Bank3
0
0
1
1
0
1
0
1
Interrupt Vector
0004
0005
On-chip Program
Memory
PIC±6F627A,
PIC±6F628A and
PIC±6F648A
4.2.1
GENERAL PURPOSE REGISTER
FILE
03FFh
07FFh
On-chip Program
Memory
The register file is organized as 224 x 8 in the
PIC±6F627A/628A and 256 x 8 in the PIC±6F648A.
Each is accessed either directly or indirectly through
the File Select Register (FSR), See Section 4.4.
PIC±6F628A and
PIC±6F648A
On-chip Program
Memory
PIC±6F648A only
0FFFh
±FFFh
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 15
PIC16F627A/628A/648A
FIGURE 4-2:
DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A
File
Address
Indirect addr.(1)
Indirect addr.(1)
OPTION
PCL
Indirect addr.(1)
Indirect addr.(1)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PIR1
PCLATH
INTCON
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2(1)
1Ch
1Dh
1Eh
1Fh
CMCON
VRCON
11Fh
120h
General
Purpose
Register
48 Bytes
20h
A0h
General
Purpose
Register
General
Purpose
Register
80 Bytes
14Fh
150h
80 Bytes
1EFh
1F0h
6Fh
70h
EFh
F0h
16Fh
170h
accesses
70h-7Fh
accesses
70h - 7Fh
accesses
70h-7Fh
16 Bytes
Bank 0
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40044A-page 16
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 4-3:
DATA MEMORY MAP OF THE PIC16F648A
File
Address
Indirect addr.(1)
Indirect addr.(1)
OPTION
PCL
Indirect addr.(1)
Indirect addr.(1)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
TMR0
PCL
TMR0
PCL
OPTION
PCL
STATUS
FSR
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
TRISA
TRISB
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PIR1
PCLATH
INTCON
PCLATH
INTCON
PIE1
TMR1L
TMR1H
T1CON
TMR2
PCON
T2CON
PR2
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2(1)
1Ch
1Dh
1Eh
1Fh
CMCON
VRCON
11Fh
120h
20h
A0h
General
Purpose
Register
80 Bytes
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
1EFh
1F0h
6Fh
70h
EFh
F0h
16Fh
170h
accesses
70h-7Fh
accesses
70h - 7Fh
accesses
70h-7Fh
16 Bytes
Bank 0
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 17
PIC16F627A/628A/648A
4.2.2
SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 4-3). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 4-3:
SPECIAL REGISTERS SUMMARY BANK0
Value on Details
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
(1)
Reset
on
Page
Bank 0
00h
01h
02h
03h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s Register
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
28
45
28
22
TMR0
PCL
Program Counter's (PC) Least Significant Byte
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
FSR
Indirect data memory address pointer
xxxx xxxx
xxxx 0000
xxxx xxxx
—
28
31
36
—
—
—
28
24
26
—
48
48
PORTA
PORTB
—
RA7
RB7
RA6
RB6
RA5
RB5
RA4
RB4
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
PCLATH
INTCON
PIR1
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
0000 000x
GIE
EEIF
PEIE
CMIF
T0IE
RCIF
INTE
TXIF
RBIE
—
T0IF
INTF
RBIF
CCP1IF
TMR2IF
TMR1IF 0000 -000
—
—
Unimplemented
TMR1L
TMR1H
Holding register for the Least Significant Byte of the 16-bit TMR1
Holding register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx
xxxx xxxx
10h
T1CON
TMR2
T2CON
—
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000
48
52
52
—
—
55
55
55
69
76
79
—
—
—
—
61
11h
TMR2 module’s register
0000 0000
12h
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
13h
Unimplemented
—
—
14h
—
Unimplemented
15h
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
—
Capture/Compare/PWM register (LSB)
Capture/Compare/PWM register (MSB)
xxxx xxxx
16h
xxxx xxxx
17h
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1
ADEN FERR OERR
CCP1M0 --00 0000
18h
SPEN
RX9
RX9D
0000 000x
19h
USART Transmit data register
USART Receive data register
Unimplemented
0000 0000
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
0000 0000
—
—
Unimplemented
—
—
Unimplemented
—
—
—
Unimplemented
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0000
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
DS40044A-page 18
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-4:
SPECIAL FUNCTION REGISTERS SUMMARY BANK1
Value on Details
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
(1)
Reset
on
Page
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
28
81h
82h
OPTION
PCL
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
C
1111 1111
0000 0000
23
28
Program Counter's (PC) Least Significant Byte
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
STATUS
FSR
IRP
RP1
RP0
TO
PD
Z
DC
0001 1xxx
xxxx xxxx
22
28
31
36
—
—
—
28
24
25
—
Indirect data memory address pointer
TRISA
TRISB
—
TRISA7
TRISB7
TRISA6
TRISB6
TRISA5
TRISB5
TRISA4
TRISB4
TRISA3
TRISB3
TRISA2
TRISB2
TRISA1
TRISB1
TRISA0 1111 1111
TRISB0 1111 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
PCLATH
INTCON
PIE1
—
—
—
Write buffer for upper 5 bits of program counter
---0 0000
GIE
PEIE
CMIE
T0IE
RCIE
INTE
TXIE
RBIE
—
T0IF
INTF
RBIF
0000 000x
EEIE
CCP1IE
TMR2IE
TMR1IE 0000 -000
Unimplemented
—
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
PCON
—
—
—
—
—
OSCF
—
POR
BOR
---- 1-0x
27
—
—
—
52
—
—
—
—
—
71
71
89
90
90
90
—
67
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
PR2
Timer2 Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
1111 1111
—
—
—
—
—
—
—
—
—
—
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
xxxx xxxx
xxxx xxxx
---- x000
---- ----
—
Baud Rate Generator Register
EEPROM data register
EEPROM address register
—
—
—
—
WRERR
WREN
VR2
WR
RD
EEPROM control register 2 (not a physical register)
Unimplemented
VRCON
VREN
VROE
VRR
—
VR3
VR1
VR0
000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 19
PIC16F627A/628A/648A
TABLE 4-5:
SPECIAL FUNCTION REGISTERS SUMMARY BANK2
Value on Details
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
(1)
Reset
on
Page
Bank 2
100h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
28
Timer0 module’s Register
xxxx xxxx
101h
102h
TMR0
PCL
45
28
22
Program Counter's (PC) Least Significant Byte
0000 0000
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx
FSR
—
Indirect data memory address pointer
Unimplemented
xxxx xxxx
28
—
36
—
—
—
28
24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PORTB
—
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of program counter
INTE RBIE T0IF INTF RBIF
---0 0000
GIE
PEIE
T0IE
0000 000x
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented.
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
DS40044A-page 20
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 4-6:
SPECIAL FUNCTION REGISTERS SUMMARY BANK3
Value on Details
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
(1)
Reset
on
Page
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx
28
181h
182h
OPTION
PCL
RBPU
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
0000 0000
23
28
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
STATUS
PD
Z
DC
C
0001 1xxx
xxxx xxxx
—
22
28
—
36
—
—
—
28
24
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FSR
—
Indirect data memory address pointer
Unimplemented
TRISB
—
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0 1111 1111
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
PCLATH
INTCON
—
—
—
Write buffer for upper 5 bits of program counter
INTE RBIE T0IF INTF
---0 0000
GIE
PEIE
T0IE
RBIF
0000 000x
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded =
unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 21
PIC16F627A/628A/648A
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the status register
as “000uu1uu”(where u= unchanged).
4.2.2.1
STATUS Register
The STATUS register, shown in Register 4-±, contains
the arithmetic status of the ALU; the RESET status and
the bank select bits for data memory (SRAM).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any STATUS bit. For other instructions, not
affecting any STATUS bits, see the “Instruction Set
Summary”.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are non-
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 4-1:
STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP±
R/W-0
RP0
R-±
TO
R-±
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (±00h - ±FFh)
0= Bank 0, ± (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
00= Bank 0 (00h - 7Fh)
01= Bank ± (80h - FFh)
10= Bank 2 (±00h - ±7Fh)
11= Bank 3 (±80h - ±FFh)
bit 4
bit 3
bit 2
bit ±
TO: Time out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions) (for borrow the polarity
is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 22
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.2
OPTION Register
Note: To achieve a ±:± prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = ±). See Section 6.3.±.
The OPTION register is a readable and writable
register, which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION REGISTER (ADDRESS: 81h, 181h)
R/W-±
RBPU
R/W-±
R/W-±
T0CS
R/W-±
T0SE
R/W-±
PSA
R/W-±
PS2
R/W-±
PS±
R/W-±
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 1
1 : 2
1 : 8
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 23
PIC16F627A/628A/648A
4.2.2.3
INTCON Register
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for
description of the comparator enable and flag bits.
a
REGISTER 4-3:
INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit ±
bit 0
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1= When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 24
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.4
PIE1 Register
This register contains interrupt enable bits.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS: 8Ch)
R/W-0
EEIE
R/W-0
CMIE
R/W-0
RCIE
R/W-0
TXIE
U-0
—
R/W-0
R/W-0
R/W-0
CCP±IE TMR2IE TMR±IE
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
EEIE: EE Write Complete Interrupt Enable Bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IE: CCP± Interrupt Enable bit
1= Enables the CCP± interrupt
0= Disables the CCP± interrupt
bit ±
bit 0
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR± Overflow Interrupt Enable bit
1= Enables the TMR± overflow interrupt
0= Disables the TMR± overflow interrupt
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 25
PIC16F627A/628A/648A
4.2.2.5
PIR1 Register
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
This register contains interrupt flag bits.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS: 0Ch)
R/W-0
EEIF
R/W-0
CMIF
R-0
R-0
U-0
—
R/W-0
R/W-0
R/W-0
RCIF
TXIF
CCP±IF TMR2IF TMR±IF
bit 0
bit 7
bit 7
bit 6
bit 5
bit 4
EEIF: EEPROM Write Operation Interrupt Flag bit
1= The write operation completed (must be cleared in software)
0= The write operation has not completed or has not been started
CMIF: Comparator Interrupt Flag bit
1= Comparator output has changed
0= Comparator output has not changed
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
bit 3
bit 2
Unimplemented: Read as ‘0’
CCP1IF: CCP± Interrupt Flag bit
Capture Mode
1= A TMR± register capture occurred (must be cleared in software)
0= No TMR± register capture occurred
Compare Mode
1= A TMR± register compare match occurred (must be cleared in software)
0= No TMR± register compare match occurred
PWM Mode
Unused in this mode
bit ±
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR± Overflow Interrupt Flag bit
1= TMR± register overflowed (must be cleared in software)
0= TMR± register did not overflow
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 26
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
4.2.2.6
PCON Register
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR Reset,
WDT Reset or a Brown-out Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
cleared, indicating
a
brown-out has
occurred. The BOR STATUS bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BOREN bit in the
Configuration word).
REGISTER 4-6:
PCON REGISTER (ADDRESS: 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-±
OSCF
U-0
—
R/W-0
POR
R/W-x
BOR
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
OSCF: INTOSC oscillator frequency
1= 4 MHz typical
0= 37 kHz typical
bit 2
bit ±
Unimplemented: Read as '0'
POR: Power-on Reset STATUS bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset STATUS bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 27
PIC16F627A/628A/648A
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
4.3
PCL and PCLATH
The program counter (PC) is ±3-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<±2:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 4-4 shows
the two situations for loading the PC. The upper exam-
ple in Figure 4-4 shows how the PC is loaded on a write
to PCL (PCLATH<4:0> → PCH). The lower example in
Figure 4-4 shows how the PC is loaded during a CALL
or GOTOinstruction (PCLATH<4:3> → PCH).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
FIGURE 4-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
4.4
Indirect Addressing, INDF and
FSR Registers
PCH
PCL
12
8
7
0
Instruction with
PCL as
Destination
PC
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
8
PCLATH<4:0>
PCLATH
5
ALU result
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no-
operation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-5.
PCH
12 11 10
PC
PCL
8
7
0
GOTO, CALL
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-±.
EXAMPLE 4-1:
Indirect Addressing
4.3.1
COMPUTED GOTO
MOVLW
MOVWF
0x20
FSR
;initialize pointer
;to RAM
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note “Implementing a Table Read” (AN556).
NEXT
CLRF
INCF
BTFSS
GOTO
INDF
FSR
;clear INDF register
;inc pointer
;all done?
FSR,4
NEXT
;no clear next
;yes continue
4.3.2
STACK
The PIC±6F627A/628A/648A family has an 8-level
deep x ±3-bit wide hardware stack (Figure 4-±). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALLinstruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLWor a RET-
FIEinstruction execution. PCLATH is not affected by a
PUSH or POP operation.
DS40044A-page 28
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 4-5:
DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A
STATUS
Register
STATUS
Register
Direct Addressing
from opcode
Indirect Addressing
7
RP1 RP0
bank select
6
0
0
IRP
FSR Register
bank select
180h
location select
location select
00
01
10
11
00h
RAM
File
Registers
7Fh
1FFh
Bank 0
Bank ± Bank 2
Bank 3
Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-±.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 29
PIC16F627A/628A/648A
NOTES:
DS40044A-page 30
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high-impedance output. The user must configure
TRISA<2> bit as an input and use high-impedance
loads.
5.0
I/O PORTS
The PIC±6F627A/628A/648A have two ports, PORTA
and PORTB. Some pins for these I/O ports are multi-
plexed with alternate functions for the peripheral fea-
tures on the device. In general, when a peripheral is
enabled, that pin may not be used as a general pur-
pose I/O pin.
In one of the Comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
5.1
IPORTA and TRISA Registers
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. Port RA4 is multiplexed
EXAMPLE 5-1:
PORTA
Initializing PORTA
;Initialize PORTA by
;setting
CLRF
(1)
with the T0CKI clock input. RA5 is a Schmitt Trigger
input only and has no output drivers. All other RA port
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS
registers) which can configure these pins as input or
output.
;output data latches
;Turn comparators off and
;enable pins for I/O
;functions
MOVLW
MOVWF
0x07
CMCON
BCF
BSF
STATUS, RP1
STATUS, RP0;Select Bank1
A '±' in the TRISA register puts the corresponding out-
put driver in a High-impedance mode. A '0' in the
TRISA register puts the contents of the output latch on
the selected pin(s).
MOVLW
0x1F
;Value used to initialize
;data direction
;Set RA<4:0> as inputs
;TRISA<5> always
;read as ‘1’.
MOVWF
TRISA
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
;TRISA<7:6>
;depend on oscillator
;mode
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
Data
Bus
D
Q
Q
VDD
WR
PORTA
CK
Data Latch
D
Q
I/O Pin
WR
TRISA
Note 1: RA5 shares function with VPP. When VPP
voltage levels are applied to RA5, the
device will enter Programming mode.
CK
Q
Analog
Input Mode
TRIS Latch
VSS
(CMCON Reg.)
2: On RESET, the TRISA register is set to all
inputs. The digital inputs (RA<3:0>) are
disabled and the comparator inputs are
forced to ground to reduce current con-
sumption.
RD
TRISA
Schmitt Trigger
Input Buffer
3: TRISA<6:7> is overridden by oscillator
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
TRISA<6:7> bits are ignored.
Q
D
EN
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
RD PORTA
To Comparator
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 31
PIC16F627A/628A/648A
FIGURE 5-2:
BLOCK DIAGRAM OF
RA2/VREF PIN
Data
Bus
D
Q
Q
VDD
WR
PORTA
CK
Data Latch
D
Q
RA2 Pin
WR
TRISA
Analog
Input Mode
(CMCON Reg.)
CK
TRIS Latch
Q
VSS
RD
TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
VROE
VREF
FIGURE 5-3:
BLOCK DIAGRAM OF THE RA3/AN3 PIN
Data
Bus
(CMCON Reg.)
Comparator Mode = 110
Comparator Output
VDD
D
Q
Q
WR
PORTA
1
0
CK
Data Latch
D
Q
RA3 Pin
WR
TRISA
Analog
Input Mode
(CMCON Reg.)
CK
TRIS Latch
Q
VSS
RD
TRISA
Schmitt Trigger
Input Buffer
Q
D
EN
RD PORTA
To Comparator
DS40044A-page 32
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-4:
BLOCK DIAGRAM OF RA4/T0CKI PIN
Data
Bus
Comparator Mode = 110
(CMCON Reg.)
D
Q
Q
Comparator Output
VDD
WR
PORTA
1
0
CK
Data Latch
D
Q
RA4 Pin
WR
TRISA
N
CK
Q
Vss
Vss
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
FIGURE 5-5:
BLOCK DIAGRAM OF THE
FIGURE 5-6:
BLOCK DIAGRAM OF
RA6/OSC2/CLKOUT PIN
RA5/MCLR/VPP PIN
From OSC1
OSC
Circuit
VDD
CLKOUT(FOSC/4)
1
0
(Configuration Bit)
MCLRE
MCLR
circuit
D
Q
Q
WR
MCLR Filter
PORTA
CK
VSS
Schmitt Trigger
Input Buffer
Program
mode
(FOSC =
Data Latch
101, 111) (2)
HV Detect
RA5/MCLR/VPP
D
Q
Q
WR
TRISA
Data
Bus
CK
TRIS Latch
VSS
RD
TRISA
Schmitt
Trigger
Input Buffer
FOSC =
011, 100, 110
(1)
RD
TRISA
VSS
Q
D
Q
D
EN
RD PORTA
EN
RD
PORTA
Note 1: INTOSC with RA6 = I/O or RC with RA6 = I/O.
2: INTOSC with RA6 = CLKOUT or RC with RA6 =
CLKOUT.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 33
PIC16F627A/628A/648A
FIGURE 5-7:
BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To Clock Circuits
VDD
Data Bus
D
Q
Q
RA7/OSC1/CLKIN Pin
WR PORTA
CK
Data Latch
D
VSS
Q
WR TRISA
CK
Q
TRIS Latch
RD TRISA
FOSC = 100, 101(1)
Q
D
Schmitt Trigger
Input Buffer
EN
RD PORTA
Note 1: INTOSC with CLKOUT, and INTOSC with I/O.
DS40044A-page 34
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 5-1:
Name
PORTA FUNCTIONS
Input
Function
Output
Type
Description
Type
RA0/AN0
RA0
AN0
ST
AN
ST
AN
ST
AN
—
CMOS Bi-directional I/O port
Analog comparator input
CMOS Bi-directional I/O port
Analog comparator input
CMOS Bi-directional I/O port
—
RA±/AN±
RA±
AN±
—
RA2/AN2/VREF
RA2
AN2
—
Analog comparator input
VREF
RA3
AN
VREF output
RA3/AN3/CMP±
ST
AN
—
CMOS Bi-directional I/O port
Analog comparator input
CMOS Comparator ± output
AN3
—
CMP±
RA4
RA4/T0CKI/CMP2
ST
ST
—
OD
—
Bi-directional I/O port. Output is open drain type.
T0CKI
CMP2
External clock input for TMR0 or comparator output
Comparator 2 output
OD
Input port
RA5/MCLR/VPP
RA5
ST
ST
—
—
Master clear. When configured as MCLR, this pin is an
active low RESET to the device. Voltage on MCLR/VPP
must not exceed VDD during normal device operation.
MCLR
Programming voltage input.
VPP
RA6
HV
ST
—
—
RA6/OSC2/CLKOUT
RA7/OSC±/CLKIN
CMOS Bi-directional I/O port
XTAL Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
OSC2
CLKOUT
—
CMOS In RC or INTOSC mode. OSC2 pin can output CLKOUT,
which has ±/4 the frequency of OSC±
RA7
ST
CMOS Bi-directional I/O port
OSC±
XTAL
—
Oscillator crystal input. Connects to crystal resonator in
Crystal Oscillator mode.
CLKIN
ST
—
External clock source input. RC biasing pin.
Legend:
O = Output
— = Not used
TTL = TTL Input
CMOS = CMOS Output
P
= Power
I
OD
= Input
= Open Drain Output
ST = Schmitt Trigger Input
AN = Analog
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 35
PIC16F627A/628A/648A
(1)
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on
All Other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA5(2)
05h
85h
1Fh
9Fh
PORTA
TRISA
RA7
RA6
RA4
RA3
RA2
RA1
RA0
xxxx 0000
1111 1111
0000 0000
000- 0000
qqqu 0000
1111 1111
0000 0000
000- 0000
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
CMCON
VRCON
C2OUT
VREN
C1OUT
VROE
C2INV
VRR
C1INV
—
CIS
CM2
VR2
CM1
VR1
CM0
VR0
VR3
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Shaded bits are not used by PORTA.
2: MCLRE Configuration Bit sets RA5 functionality.
This interrupt on mismatch feature, together with
5.2
PORTB and TRISB Registers
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552)
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '±' in
the TRISB register puts the corresponding output driver
in a High-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Note: If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR± clock input/output.
The standard port functions and the alternate port func-
tions are shown in Table 5-3. Alternate port functions
may override TRIS setting when enabled.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
DS40044A-page 36
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-8:
BLOCK DIAGRAM OF
RB0/INT PIN
VDD
FIGURE 5-9:
BLOCK DIAGRAM OF
RB1/RX/DT PIN
VDD
RBPU
RBPU
SPEN
Weak
Pull-up
P Weak Pull-up
VDD
P
VDD
USART Data Output
1
0
Data Bus
Data Bus
D
RB1/
Q
Q
D
Q
Q
RX/DT
WR PORTB
RB0/INT
WR PORTB
CK
CK
Data Latch
VSS
VSS
Data Latch
D
Q
Q
D
Q
Q
WR TRISB
CK
WR TRISB
CK
TRIS Latch
Peripheral OE(1)
RD TRISB
TRIS Latch
TTL
Input
Buffer
TTL
Input
Buffer
RD TRISB
Q
D
Q
D
EN
RD PORTB
EN
USART Receive Input
RD PORTB
INT
Schmitt
Trigger
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
Schmitt
Trigger
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 37
PIC16F627A/628A/648A
FIGURE 5-10:
BLOCK DIAGRAM OF
RB2/TX/CK PIN
VDD
FIGURE 5-11:
BLOCK DIAGRAM OF
RB3/CCP1 PIN
VDD
RBPU
SPEN
RBPU
Weak
Pull-up
Weak
Pull-up
P
P
CCP1CON
VDD
VDD
USART TX/CK Output
CCP output
1
0
0
1
Data Bus
Data Bus
RB2/
TX/CK
RB3/
CCP1
D
D
Q
Q
Q
Q
WR PORTB
WR PORTB
CK
CK
Data Latch
Data Latch
VSS
VSS
D
D
Q
Q
Q
Q
WR TRISB
WR TRISB
CK
CK
TRIS Latch
TRIS Latch
Peripheral OE(1)
RD TRISB
Peripheral OE(2)
RD TRISB
TTL
Input
Buffer
TTL
Input
Buffer
Q
D
Q
D
EN
EN
RD PORTB
RD PORTB
CCP In
USART Slave Clock In
Schmitt
Trigger
Schmitt
Trigger
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
Note 1: Peripheral OE (output enable) is only active if
peripheral select is active.
DS40044A-page 38
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-12:
BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P
weak pull-up
Data Bus
D
Q
Q
VDD
WR PORTB
CK
Data Latch
RB4/PGM
D
Q
Q
WR TRISB
RD TRISB
CK
VSS
TRIS Latch
LVP (Configuration Bit)
RD PORTB
PGM input
TTL
input
buffer
Schmitt
Trigger
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
Q3
EN
Note:
The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 39
PIC16F627A/628A/648A
FIGURE 5-13:
BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
VDD
weak
pull-up
P
Data Bus
D
Q
Q
RB5 pin
WR PORTB
CK
Data Latch
VSS
D
Q
Q
WR TRISB
CK
TRIS Latch
TTL
input
buffer
RD TRISB
Q
D
RD PORTB
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
Q3
EN
DS40044A-page 40
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 5-14:
BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD
RBPU
P
weak pull-up
Data Bus
D
Q
Q
VDD
WR PORTB
CK
Data Latch
RB6/
D
Q
Q
T1OSO/
T1CKI
pin
WR TRISB
CK
VSS
TRIS Latch
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
Schmitt
Trigger
From RB7
TMR1 oscillator
Serial programming clock
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
Q3
EN
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 41
PIC16F627A/628A/648A
FIGURE 5-15:
BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD
weak pull-up
RBPU
P
TMR1 oscillator
To RB6
VDD
Data Bus
D
Q
Q
WR PORTB
RB7/T1OSI
pin
CK
Data Latch
D
Q
Q
VSS
WR TRISB
CK
TRIS Latch
RD TRISB
T10SCEN
TTL
input
buffer
RD PORTB
Serial programming input
Schmitt
Trigger
Q
D
Q1
EN
Set RBIF
Q
D
From other
RB<7:4> pins
Q3
EN
DS40044A-page 42
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 5-3:
PORTB FUNCTIONS
Output
Type
Name
Function Input Type
Description
RB0/INT
RB0
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
INT
ST
—
External interrupt.
RB±/RX/DT
RB±
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
RX
DT
ST
ST
TTL
—
—
USART Receive Pin
Synchronous data I/O
Bi-directional I/O port
USART Transmit Pin
CMOS
CMOS
CMOS
CMOS
RB2/TX/CK
RB2
TX
CK
ST
Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP±
RB4/PGM
RB3
TTL
CMOS
Bi-directional I/O port. Can be software programmed for
internal weak pull-up.
CCP±
RB4
ST
CMOS
CMOS
Capture/Compare/PWM/I/O
TTL
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
PGM
ST
—
Low voltage programming input pin. When low voltage
programming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5
RB5
RB6
TTL
TTL
CMOS
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T±OSO/T±CKI/
PGC
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T±OSO
T±CKI
PGC
—
ST
XTAL
—
Timer± Oscillator Output
Timer± Clock Input
ST
—
ICSP Programming Clock
RB7/T±OSI/PGD
RB7
TTL
CMOS
Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T±OSI
PGD
XTAL
ST
—
Timer± Oscillator Input
ICSP Data I/O
CMOS
Legend:
O = Output
— = Not used
TTL = TTL Input
CMOS = CMOS Output
P
= Power
I
OD
= Input
= Open Drain Output
ST = Schmitt Trigger Input
AN = Analog
(1)
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on
All Other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
06h, 106h PORTB
RB7
RB6
RB5
RB4(2)
RB3
RB2
RB1
RB0
xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG
Legend: u = unchanged, x = unknown
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
Note 1: Shaded bits are not used by PORTB.
2: LVP Configuration Bit sets RB4 functionality.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 43
PIC16F627A/628A/648A
EXAMPLE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.3
I/O Programming Considerations
5.3.1
BI-DIRECTIONAL I/O PORTS
;Initial PORT settings:PORTB<7:4> Inputs
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-up and are
Any instruction that writes, operates internally as a read
followed by a write operation. The BCFand BSFinstruc-
tions, for example, read the register into the CPU, exe-
cute the bit operation and write the result back to the
register. Caution must be used when these instructions
are applied to a port with both inputs and outputs
defined. For example, a BSF operation on bit5 of
PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSFoperation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the Input mode, no problem occurs. However,
if bit0 is switched into Output mode later on, the content
of the data latch may now be unknown.
;
;not connected to other circuitry
;
;
PORT latchPORT Pins
---------- ----------
;
BCF STATUS, RP0
BCF PORTB, 7
;01pp pppp 11pp pppp
;
BSF STATUS, RP0
BCF TRISB, 7
BCF TRISB, 6
;10pp pppp 11pp pppp
;10pp pppp 10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(High).
5.3.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
Reading a port register reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle (Figure 5-
±6). Therefore, care must be exercised if a write fol-
lowed by a read operation is carried out on the same I/
O port. The sequence of instructions should be such to
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the previ-
ous state of that pin may be read into the CPU rather
than the new state. When in doubt, it is better to sepa-
rate these instructions with a NOPor another instruction
not accessing this I/O port.
Example 5-2 shows the effect of two sequential read-
modify-write instructions (ex., BCF, BSF, etc.) on an
I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-16:
SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC
PC + 1
PC + 2
PC + 3
MOVFPORTB, W
Read to PORTB
NOP
NOP
MOVWFPORTB
Write to PORTB
Port pin
sampled here
TPD
Execute
MOVWF
Execute
MOVF
PORTB, W
Execute
NOP
PORTB
Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Therefore, at higher clock frequencies, a write followed by a read may be problematic.
DS40044A-page 44
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
6.2
Using Timer0 with External Clock
6.0
TIMER0 MODULE
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Read/Write capabilities
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
6.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 6-±). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
Figure 6-± is a simplified block diagram of the Timer0
module. Additional information is available in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual, DS33023.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In Timer mode, the TMR0 register value
will increment every instruction cycle (without pres-
caler). If the TMR0 register is written to, the increment
is inhibited for the following two cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of ±0 ns. Refer to
parameters 40, 4± and 42 in the electrical specification
of the desired device. See Table ±7-9.
Counter mode is selected by setting the T0CS bit. In
this mode the TMR0 register value will increment either
on every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the source edge
(T0SE) control bit (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.2.
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of ±:2, ±:4,..., ±:256 are
selectable. Section 6.3 details the operation of the
prescaler.
6.1
Timer0 Interrupt
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by clear-
ing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 45
PIC16F627A/628A/648A
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
6.3
Timer0 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. A prescaler assignment for the Timer0 module
means that there is no postscaler for the Watchdog
Timer, and vice-versa.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1, x....etc.) will clear the pres-
caler. When assigned to WDT, a CLRWDT instruction
will clear the prescaler along with the Watchdog Timer.
The prescaler is not readable or writable.
FIGURE 6-1:
BLOCK DIAGRAM OF THE TIMER0/WDT
DATA BUS
FOSC/4
8
0
1
T0CKI
PIN
1
0
SYNC
2
CYCLES
TMR0 REG
T0SE
T0CS
SET FLAG BIT T0IF
ON OVERFLOW
PSA
TMR1 Clock Source
0
1
WDT POSTSCALER/
TMR0 PRESCALER
WATCHDOG
TIMER
8
PSA
8-TO-1MUX
PS0 - PS2
WDT ENABLE BIT
1
0
WDT
TIME OUT
PSA
Note: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option Register.
.
DS40044A-page 46
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
6.3.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). Use the instruction sequences
shown in Example 6-± when changing the prescaler
assignment from Timer0 to WDT, to avoid an unin-
tended device RESET.
EXAMPLE 6-2:
CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
;Select TMR0, new
;prescale value and
;clock source
EXAMPLE 6-1:
CHANGING PRESCALER
(TIMER0→WDT)
MOVWF
BCF
OPTION_REG
STATUS, RP0
BCF
STATUS, RP0
;Skip if already in
;Bank 0
;Clear WDT
CLRWDT
CLRF
TMR0
;Clear TMR0 and
;Prescaler
;Bank 1
BSF
MOVLW
STATUS, RP0
'00101111’b
;These 3 lines
;(5, 6, 7)
MOVWF
OPTION_REG
;are required only
;if desired PS<2:0>
;are
CLRWDT
MOVLW
MOVWF
BCF
;000 or 001
'00101xxx’b
OPTION_REG
STATUS, RP0
;Set Postscaler to
;desired WDT rate
;Return to Bank 0
TABLE 6-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
All Other
RESETS
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h, 101h
TMR0
Timer0 module register
GIE PEIE T0IE
RBPU INTEDG T0CS
TRISA7 TRISA6
xxxx xxxx uuuu uuuu
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
0Bh, 8Bh,
INTCON
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
10Bh, 18Bh
OPTION(2)
TRISA
81h, 181h
85h
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISA5
Legend:
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by Timer0 module.
2: Option is referred by OPTION_REGin MPLAB®.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 47
PIC16F627A/628A/648A
The Operating mode is determined by the clock select
bit, TMR±CS (T±CON<±>).
7.0
TIMER1 MODULE
The Timer± module is a ±6-bit timer/counter consisting
of two 8-bit registers (TMR±H and TMR±L) which are
readable and writable. The TMR± register pair
(TMR±H:TMR±L) increments from 0000h to FFFFh
and rolls over to 0000h. The Timer± Interrupt, if
enabled, is generated on overflow of the TMR± register
pair which latches the interrupt flag bit TMR±IF
(PIR±<0>). This interrupt can be enabled/disabled by
setting/clearing the Timer± interrupt enable bit TMR±IE
(PIE±<0>).
In Timer mode, the TMR± register pair value incre-
ments every instruction cycle. In Counter mode, it
increments on every rising edge of the external clock
input.
Timer± can be enabled/disabled by setting/clearing
control bit TMR±ON (T±CON<0>).
Timer± also has an internal “RESET input”. This
RESET can be generated by the CCP module
(Section 9.0). Register 7-± shows the Timer± control
register.
Timer± can operate in one of two modes:
For the PIC±6F627A/628A/648A, when the Timer±
oscillator is enabled (T±OSCEN is set), the RB7/T±OSI
and RB6/T±OSO/T±CKI pins become inputs. That is,
the TRISB<7:6> value is ignored.
• As a timer
• As a counter
REGISTER 7-1:
T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T±CKPS± T±CKPS0 T±OSCEN T±SYNC TMR±CS TMR±ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
T1CKPS1:T1CKPS0: Timer± Input Clock Prescale Select bits
11= ±:8 Prescale value
10= ±:4 Prescale value
01= ±:2 Prescale value
00= ±:± Prescale value
bit 3
bit 2
T1OSCEN: Timer± Oscillator Enable Control bit
1= Oscillator is enabled
(1)
0= Oscillator is shut off
T1SYNC: Timer± External Clock Input Synchronization Control bit
TMR±CS = ±
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR±CS = 0
This bit is ignored. Timer± uses the internal clock when TMR±CS = 0.
bit ±
bit 0
TMR1CS: Timer± Clock Source Select bit
1= External clock from pin RB6/T±OSO/T±CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer± On bit
1= Disables Timer±
0= Stops Timer±
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 48
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
7.2.1
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
7.1
Timer1 Operation in Timer Mode
Timer mode is selected by clearing the TMR±CS
(T±CON<±>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T±SYNC
(T±CON<2>) has no effect since the internal clock is
always in sync.
When an external clock input is used for Timer± in syn-
chronized Counter mode, it must meet certain require-
ments. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of the TMR± reg-
ister pair value after synchronization.
7.2
Timer1 Operation in Synchronized
Counter Mode
When the prescaler is ±:±, the external clock input is
the same as the prescaler output. The synchronization
of T±CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T±CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
Counter mode is selected by setting bit TMR±CS. In
this mode the TMR± register pair value increments on
every rising edge of clock input on pin RB7/T±OSI
when bit T±OSCEN is set or pin RB6/T±OSO/T±CKI
when bit T±OSCEN is cleared.
If T±SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple-counter.
When a prescaler other than ±:± is used, the external
clock input is divided by the asynchronous ripple-
counter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T±CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T±CKI high and low time is that they do
not violate the minimum pulse width requirements of ±0
ns). Refer to the appropriate electrical specifications,
parameters 45, 46, and 47.
In this configuration, during SLEEP mode, the TMR±
register pair value will not increment even if the exter-
nal clock is present, since the synchronization circuit is
shut off. The prescaler however will continue to incre-
ment.
FIGURE 7-1:
TIMER1 BLOCK DIAGRAM
Set flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
T1OSC
1
TMR1ON
T1SYNC
RB6/T1OSO/T1CKI
1
0
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator(1)
FOSC/4
Internal
RB7/T1OSI
Clock
2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 49
PIC16F627A/628A/648A
EXAMPLE 7-1:
READING A 16-BIT FREE-
RUNNING TIMER
7.3
Timer1 Operation in
Asynchronous Counter Mode
; All interrupts are disabled
TMR1H, W
TMPH
If control bit T±SYNC (T±CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 7.3.2).
MOVF
MOVWF
MOVF
;Read high byte
;
TMR1L, W
TMPL
;Read low byte
;
MOVWF
MOVF
SUBWF
TMR1H, W
TMPH, W
;Read high byte
;Sub 1st read with
;2nd read
BTFSC
GOTO
STATUS,Z
CONTINUE
;Is result = 0
;Good 16-bit read
Note: In Asynchronous Counter mode, Timer±
cannot be used as a time-base for capture
or compare operations.
;
; TMR1L may have rolled over between the
; read of the high and low bytes. Reading
; the high and low bytes now will read a good
7.3.1
EXTERNAL CLOCK INPUT TIMING
WITH UNSYNCHRONIZED CLOCK
; value.
;
MOVF
TMR1H, W
TMPH
;Read high byte
;
If control bit T±SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high and low time requirements. Refer
to Table ±7-9 in the Electrical Specifications Section,
timing parameters 45, 46, and 47.
MOVWF
MOVF
MOVWF
TMR1L, W
TMPL
;Read low byte
;
; Re-enable the Interrupts (if required)
;Continue with your
;code
CONTINUE
7.3.2
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading the TMR±H or TMR±L register while the timer
is running, from an external asynchronous clock, will
produce a valid read (taken care of in hardware). How-
ever, the user should keep in mind that reading the ±6-
bit timer in two 8-bit values itself poses certain prob-
lems since the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers while the
register is incrementing. This may produce an unpre-
dictable value in the timer register.
Reading the ±6-bit value requires some care.
Example 7-± is an example routine to read the ±6-bit
timer value. This is useful if the timer cannot be
stopped.
DS40044A-page 50
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
7.4
Timer1 Oscillator
7.5
Resetting Timer1 Using a CCP
Trigger Output
A crystal oscillator circuit is built in between pins T±OSI
(input) and T±OSO (amplifier output). It is enabled by
setting control bit T±OSCEN (T±CON<3>). It will con-
tinue to run during SLEEP. It is primarily intended for a
32.768 kHz watch crystal. Table 7-± shows the capaci-
tor selection for the Timer± oscillator.
If the CCP± module is configured in Compare mode to
generate a “special event trigger” (CCP±M3:CCP±M0
= 1011), this signal will RESET Timer±.
Note: The special event triggers from the CCP±
module will not set interrupt flag bit
TMR±IF (PIR±<0>).
The user must provide a software time delay to ensure
proper oscillator start-up.
Timer± must be configured for either timer or synchro-
nized Counter mode to take advantage of this feature.
If Timer± is running in Asynchronous Counter mode,
this RESET operation may not work.
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
In the event that a write to Timer± coincides with a spe-
cial event trigger from CCP±, the write will take prece-
dence.
Freq
C1
C2
32.768 kHz
±5 pF
±5 pF
These values are for design guidance only.
Consult AN826 (DS00826) for further information
on Crystal/Capacitor Selection.
In this mode of operation, the CCPRxH:CCPRxL regis-
ters pair effectively becomes the period register for
Timer±.
7.6
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR±H and TMR±L registers are not reset to 00h on a
POR or any other RESET except by the CCP± special
event triggers.
T±CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a ±:± prescale. In all other RESETS, the register
is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR±H or TMR±L registers.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
Value on
POR
Address Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
PIR1
PIE1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
0000 -000 0000 -000
0000 -000 0000 -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0Eh
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
0Fh
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 51
PIC16F627A/628A/648A
8.1
Timer2 Prescaler and Postscaler
8.0
TIMER2 MODULE
The prescaler and postscaler counters are cleared
when any of the following occurs:
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
PWM mode of the CCP module. The TMR2 register is
readable and writable, and is cleared on any device
RESET.
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset)
The input clock (FOSC/4) has a prescale option of ±:±,
control
±:4
or
±:±6,
selected
by
T2CKPS±:T2CKPS0 (T2CON<±:0>).
bits
The TMR2 register is not cleared when T2CON is writ-
ten.
The Timer2 module has an 8-bit period register PR2.
The TMR2 register value increments from 00h until it
matches the PR2 register value and then resets to 00h
on the next increment cycle. The PR2 register is a
readable and writable register. The PR2 register is ini-
tialized to FFh upon RESET.
8.2
TMR2 Output
The TMR2 output (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
The match output of Timer2 goes through a 4-bit
postscaler (which gives a ±:± to ±:±6 scaling inclusive)
to generate a Timer2 interrupt (latched in flag bit
TMR2IF, (PIR±<±>)).
FIGURE 8-1:
TIMER2 BLOCK DIAGRAM
Sets flag
bit TMR2IF
TMR2
output
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
RESET
Prescaler
Register 8-± shows the Timer2 control register.
TMR2 reg
FOSC/4
1:1, 1:4, 1:16
Postscaler
2
Comparator
1:1 to 1:16
EQ
T2CKPS<1:0>
4
PR2 reg
TOUTPS<3:0>
DS40044A-page 52
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
REGISTER 8-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS: 12h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS±
TOUTPS0 TMR2ON T2CKPS± T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as '0'
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= ±:± Postscale Value
0001= ±:2 Postscale Value
•
•
•
1111= ±:±6 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit ±-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= ±:± Prescaler Value
01= ±:4 Prescaler Value
1x= ±:±6 Prescaler Value
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
TABLE 8-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 -000 0000 -000
0000 -000 0000 -000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
8Ch
11h
12h
92h
PIR1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
PIE1
TMR2
T2CON
PR2
Timer2 module’s register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 53
PIC16F627A/628A/648A
NOTES:
DS40044A-page 54
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 9-1:
CCP MODE - TIMER
RESOURCE
9.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
CCP Mode
Timer Resource
The CCP (Capture/Compare/PWM) module contains a
±6-bit register which can operate as a ±6-bit capture
register, as a ±6-bit compare register or as a PWM
master/slave Duty Cycle register. Table 9-± shows the
timer resources of the CCP module modes.
Capture
Compare
PWM
Timer±
Timer±
Timer2
CCP± Module
Capture/Compare/PWM Register± (CCPR±) is com-
prised of two 8-bit registers: CCPR±L (low byte) and
CCPR±H (high byte). The CCP±CON register controls
the operation of CCP±. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 9-1:
CCP1CON REGISTER (ADDRESS: 17h)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CCP±X
CCP±Y
CCP±M3
CCP±M2 CCP±M± CCP±M0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
bit 3-0
CCP1M3:CCP1M0: CCPx Mode Select bits
0000= Capture/Compare/PWM off (resets CCP± module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every ±6th rising edge
1000= Compare mode, set output on match (CCP±IF bit is set)
1001= Compare mode, clear output on match (CCP±IF bit is set)
1010= Compare mode, generate software interrupt on match (CCP±IF bit is set, CCP± pin is
unaffected)
1011= Compare mode, trigger special event (CCP±IF bit is set; CCP± resets TMR±
11xx= PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 55
PIC16F627A/628A/648A
9.1.4
CCP PRESCALER
9.1
Capture Mode
There are four prescaler settings, specified by bits
CCP±M3:CCP±M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
In Capture mode, CCPR±H:CCPR±L captures the
±6-bit value of the TMR± register when an event occurs
on pin RB3/CCP±. An event is defined as:
• Every falling edge
• Every rising edge
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 9-± shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
• Every 4th rising edge
• Every ±6th rising edge
An event is selected by control bits CCP±M3:CCP±M0
(CCP±CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP±IF (PIR±<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR± is read, the old captured
value will be lost.
EXAMPLE 9-1:
CHANGING BETWEEN
CAPTURE PRESCALERS
;Turn CCP module off
9.1.1
CCP PIN CONFIGURATION
CLRF
MOVLW
CCP1CON
NEW_CAPT_PS;Load the W reg with
; the new prescaler
; mode value and CCP ON
In Capture mode, the RB3/CCP± pin should be config-
ured as an input by setting the TRISB<3> bit.
Note: If the RB3/CCP± is configured as an out-
put, a write to the port can cause a capture
condition.
MOVWF
CCP1CON
;Load CCP1CON with this
; value
9.2
Compare Mode
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
In Compare mode, the ±6-bit CCPR± register value is
constantly compared against the TMR± register pair
value. When a match occurs, the RB3/CCP± pin is:
Set flag bit CCP1IF
(PIR1<2>)
• Driven High
Prescaler
• Driven Low
³ 1, 4, 16
• Remains Unchanged
RB3/CCP1
Pin
CCPR1H
CCPR1L
The action on the pin is based on the value of control
bits CCP±M3:CCP±M0 (CCP±CON<3:0>). At the
same time, interrupt flag bit CCP±IF is set.
Capture
Enable
and
edge detect
TMR1H
TMR1L
CCP1CON<3:0>
FIGURE 9-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Q’s
9.1.2
TIMER1 MODE SELECTION
Set flag bit CCP1IF
(PIR1<2>)
Timer± must be running in Timer mode or synchronized
Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture
operation may not work.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RB3/CCP1
Pin
TRISB<3>
Output Enable
9.1.3
SOFTWARE INTERRUPT
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP±IE (PIE±<2>) clear to avoid false interrupts and
should clear the flag bit CCP±IF following any such
change in Operating mode.
Note:
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>)
DS40044A-page 56
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
9.2.1
CCP PIN CONFIGURATION
9.2.3
SOFTWARE INTERRUPT MODE
The user must configure the RB3/CCP± pin as an out-
put by clearing the TRISB<3> bit.
When generate software interrupt is chosen the CCP±
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Note: Clearing the CCP±CON register will force
the RB3/CCP± compare output latch to the
default low level. This is not the data latch.
9.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
9.2.2
TIMER1 MODE SELECTION
The special event trigger output of CCP± resets the
TMR± register pair. This allows the CCPR± register to
effectively be a ±6-bit programmable period register for
Timer±.
Timer± must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TABLE 9-2:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
Value on
POR
Address
Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
RESETS
0Bh, 8Bh, INTCON
10Bh, 18Bh
0000 000x 0000 000u
GIE PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0Ch
8Ch
PIR1
PIE1
0000 -000 0000 -000
0000 -000 0000 -000
EEIF CMIF
EEIE CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
86h, 186h TRISB
PORTB Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0Eh
0Fh
10h
TMR1L
TMR1H
T1CON
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
15h
16h
17h
CCPR1L
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
CCP1CON --00 0000 --00 0000
CCP1M3 CCP1M2 CCP1M1 CCP1M0
—
—
CCP1X
CCP1Y
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 57
PIC16F627A/628A/648A
A PWM output (Figure 9-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period (fre-
quency = ±/period).
9.3
PWM Mode
In Pulse Width Modulation (PWM) mode, the CCP± pin
produces up to a ±0-bit resolution PWM output. Since
the CCP± pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP±
pin an output.
FIGURE 9-4:
PWM OUTPUT
Note: Clearing the CCP±CON register will force
the CCP± PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Period
Duty Cycle
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
TMR2 = PR2
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
TMR2 = Duty Cycle
TMR2 = PR2
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
9.3.1
PWM PERIOD
CCP1CON<5:4>
Duty cycle registers
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
CCPR1L
PWM period = [(PR2) + 1] ⋅ 4 ⋅ Tosc ⋅ TMR2 prescale
value
CCPR1H (Slave)
Comparator
PWM frequency is defined as ± / [PWM period].
Q
R
S
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
RB3/CCP1
(1)
• TMR2 is cleared
TMR2
• The CCP± pin is set (exception: if PWM duty
cycle = 01, the CCP± pin will not be set)
TRISB<3>
Comparator
PR2
• The PWM duty cycle is latched from CCPR±L into
CCPR±H
Clear Timer,
CCP1 pin and
latch D.C.
Note: The Timer2 postscaler (see Section 8.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
Note 1: 8-bit timer is concatenated with 2-bit internal Q
clock or 2 bits of the prescaler to create 10-bit
time-base.
DS40044A-page 58
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Maximum PWM resolution (bits) for a given PWM
frequency:
9.3.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR±L register and to the CCP±CON<5:4> bits. Up
to ±0-bit resolution is available: the CCPR±L contains
the eight MSbs and the CCP±CON<5:4> contains the
two LSbs. This ±0-bit value is represented by
CCPR±L:CCP±CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Fosc
-------------------------------------------------------------
log
PWM
Resolution =
Fpwm × TMR2 Prescaler
log(2)
---------------------------------------------------------------------------
bits
Note: If the PWM duty cycle value is longer than
the PWM period the CCP± pin will not be
cleared.
PWM duty cycle =
(CCPR1L:CCP1CON<5:4>) ⋅ Tosc ⋅ TMR2 prescale
value
For an example PWM period and duty cycle calcula-
tion, see the PICmicro™ Mid-Range Reference Man-
ual (DS33023).
CCPR±L and CCP±CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR±H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR±H is a read-only register.
9.3.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
The CCPR±H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitch less PWM operation.
±. Set the PWM period by writing to the PR2 regis-
ter.
2. Set the PWM duty cycle by writing to the
CCPR±L register and CCP±CON<5:4> bits.
When the CCPR±H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP± pin is cleared.
3. Make the CCP± pin an output by clearing the
TRISB<3> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP± module for PWM operation.
TABLE 9-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (±, 4, ±6)
PR2 Value
±6
0xFF
±0
4
±
±
0x3F
8
±
0x±F
7
±
0xFF
±0
0xFF
±0
0x±7
6.5
Maximum Resolution (bits)
TABLE 9-4:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
RESETS
Value on
POR
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh,
10Bh, 18Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF
CCP1IE
TMR2IF TMR1IF 0000 -000 0000 -000
TMR2IE TMR1IE 0000 -000 0000 -000
1111 1111 1111 1111
8Ch
PIE1
86h, 186h
11h
TRISB
TMR2
PORTB Data Direction Register
Timer2 module’s register
0000 0000 0000 0000
92h
PR2
Timer2 module’s period register
1111 1111 1111 1111
12h
T2CON
CCPR1L
CCPR1H
CCP1CON
—
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu uuuu
15h
Capture/Compare/PWM register1 (LSB)
Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
17h
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 59
PIC16F627A/628A/648A
NOTES:
DS40044A-page 60
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The CMCON register, shown in Register ±0-±, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure ±0-±.
10.0 COMPARATOR MODULE
The Comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The on-
chip Voltage Reference (Section ±±.0) can also be an
input to the comparators.
REGISTER 10-1: CMCON REGISTER (ADDRESS: 01Fh)
R-0
R-0
R/W-0
C2INV
R/W-0
C±INV
R/W-0
CIS
R/W-0
CM2
R/W-0
CM±
R/W-0
CM0
C2OUT
C±OUT
bit 7
bit 0
bit 7
C2OUT: Comparator 2 Output
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = ±:
1= C2 VIN+ < C2 VIN-
0= C2 VIN+ > C2 VIN-
bit 6
C1OUT: Comparator ± Output
When C±INV = 0:
1= C± VIN+ > C± VIN-
0= C± VIN+ < C± VIN-
When C±INV = ±:
1= C± VIN+ < C± VIN-
0= C± VIN+ > C± VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion
1= C2 Output inverted
0= C2 Output not inverted
C1INV: Comparator ± Output Inversion
1= C± Output inverted
0= C± Output not inverted
CIS: Comparator Input Switch
When CM2:CM0: = 00±
Then:
1= C± VIN- connects to RA3
0= C± VIN- connects to RA0
When CM2:CM0 = 0±0
Then:
1= C± VIN- connects to RA3
C2 VIN- connects to RA2
0= C± VIN- connects to RA0
C2 VIN- connects to RA±
bit 2-0
CM2:CM0: Comparator Mode
Figure ±0-± shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 61
PIC16F627A/628A/648A
tor mode is changed, the comparator output level may
not be valid for the specified mode change delay
shown in Table ±7-2.
10.1 Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure ±0-± shows the eight possible
modes. The TRISA register controls the data direction
of the comparator pins for each mode. If the Compara-
Note 1: Comparator interrupts should be disabled
during a Comparator mode change, other-
wise a false interrupt may occur.
2: Comparators can have an inverted out-
put. See Figure ±0-3.
FIGURE 10-1:
COMPARATOR I/O OPERATING MODES
Comparators Off
CM2:CM0 = 111
Comparators Reset (POR Default Value)
CM2:CM0 = 000
D
D
VIN-
RA0/AN0
A
A
VIN-
RA0/AN0
Off (Read as '0')
Off (Read as '0')
C1
C2
VIN+
RA3/AN3/CMP1
Off (Read as '0')
Off (Read as '0')
C1
C2
VIN+
RA3/AN3/CMP1
D
D
VIN-
A
A
VIN-
RA1/AN1
RA1/AN1
VIN+
RA2/AN2/VREF
VIN+
RA2/AN2/VREF
VSS
Four Inputs Multiplexed to Two Comparators
CM2:CM0 = 010
Two Independent Comparators
CM2:CM0 = 100
A
RA0/AN0
CIS = 0
CIS = 1
VIN-
A
A
VIN-
RA0/AN0
A
RA3/AN3/CMP1
C1VOUT
C1VOUT
C2VOUT
C1
C1
VIN+
VIN+
RA3/AN3/CMP1
A
A
RA1/AN1
VIN-
CIS = 0
CIS = 1
A
A
VIN-
RA2/AN2/VREF
RA1/AN1
C2VOUT
C2
VIN+
C2
VIN+
RA2/AN2/VREF
From VREF
Module
Two Common Reference Comparators
CM2:CM0 = 011
Two Common Reference Comparators with Outputs
CM2:CM0 = 110
A
D
VIN-
RA0/AN0
A
D
VIN-
RA0/AN0
C1VOUT
C2VOUT
C1
VIN+
C1VOUT
C2VOUT
C1
C2
RA3/AN3/CMP1
VIN+
RA3/AN3/CMP1
A
A
VIN-
RA1/AN1
A
A
VIN-
RA1/AN1
C2
VIN+
RA2/AN2/VREF
VIN+
RA2/AN2/VREF
Open Drain
RA4/T0CKI/CMP2
Three Inputs Multiplexed to Two Comparators
CM2:CM0 = 001
One Independent Comparator
CM2:CM0 = 101
D
D
VIN-
A
RA0/AN0
RA0/AN0
CIS = 0
CIS = 1
VIN-
Off (Read as '0')
C1
VIN+
A
RA3/AN3/CMP1
RA3/AN3/CMP1
C1VOUT
C1
C2
VIN+
VSS
A
A
VIN-
A
A
VIN-
RA1/AN1
RA1/AN1
C2VOUT
C2VOUT
C2
VIN+
VIN+
RA2/AN2/VREF
RA2/AN2/VREF
D = Digital Input.
A = Analog Input, port reads zeros always.
CIS (CMCON<3>) is the Comparator Input Switch.
DS40044A-page 62
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The code example in Example ±0-± depicts the steps
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA± are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
FIGURE 10-2:
SINGLE COMPARATOR
Vin+
Vin-
+
Result
–
EXAMPLE 10-1:
INITIALIZING
COMPARATOR MODULE
FLAG_REG
EQU
0X20
;Init flag register
;Init PORTA
VIN-
CLRF
CLRF
MOVF
ANDLW
IORWF
MOVLW
MOVWF
BSF
FLAG_REG
PORTA
CMCON, W ;Load comparator bits
0xC0 ;Mask comparator bits
FLAG_REG,F ;Store bits in flag register
VIN+
0x03
CMCON
STATUS,RP0 ;Select Bank1
;Init comparator mode
;CM<2:0> = 011
MOVLW
MOVWF
0x07
TRISA
;Initialize data direction
;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’
Result
BCF
CALL
MOVF
STATUS,RP0 ;Select Bank 0
;10µs delay
;Read CMCONto end change
;condition
PIR1,CMIF ;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE ;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
10.3.1
EXTERNAL REFERENCE SIGNAL
DELAY10
CMCON,F
When external voltage references are used, the
Comparator module can be configured to have the
comparators operate from the same or different
reference sources. However, threshold detector
applications may require the same reference. The
reference signal must be between VSS and VDD, and
can be applied to either pin of the comparator(s).
BCF
BSF
BSF
BCF
BSF
BSF
10.2 Comparator Operation
10.3.2
INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure ±0-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure ±0-2 represent
the uncertainty due to input offsets and response time.
See Table ±7-2 for Common Mode Voltage.
The Comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section ±±.0, Voltage Reference Manual,
contains a detailed description of the Voltage Refer-
ence Module that provides this signal. The internal ref-
erence signal is used when the comparators are in
mode CM<2:0>=0±0 (Figure ±0-±). In this mode, the
internal voltage reference is applied to the VIN+ pin of
both comparators.
10.3 Comparator Reference
10.4 Comparator Response Time
An external or internal reference signal may be used
depending on the comparator Operating mode. The
analog signal that is present at VIN- is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure ±0-2).
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is to have a valid level. If the internal
reference is changed, the maximum delay of the inter-
nal voltage reference must be considered when using
the comparator outputs. Otherwise, the maximum
delay of the comparators should be used (Table ±7-2).
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 63
PIC16F627A/628A/648A
10.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = ±±0 or 00±, multiplexors
in the output path of the RA3 and RA4/T0CK± pins will
switch and the output of each pin will be the unsynchro-
nized output of the comparator. The uncertainty of each
of the comparators is related to the input offset voltage
and the response time given in the specifications.
Figure ±0-3 shows the comparator output block
diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4/T0CK± pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input, according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is speci-
fied.
FIGURE 10-3:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
CnINV
To RA3 or RA4/T0CK1 pin
CnVOUT
To Data Bus
Q
D
CMCON<7:6>
Q3
EN
RD CMCON
Set CMIF bit
Q
D
EN
CL
Q1
From other Comparator
RESET
DS40044A-page 64
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
10.6 Comparator Interrupts
10.7 Comparator Operation During
SLEEP
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR±<6>, is the comparator interrupt flag.
The CMIF bit must be RESET by clearing ‘0’. Since it is
also possible to write a '±' to this register, a simulated
interrupt may be initiated.
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
wake-up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher SLEEP
currents than shown in the power-down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = ±±±, before entering SLEEP.
If the device wakes up from SLEEP, the contents of the
CMCON register are not affected.
The CMIE bit (PIE±<6>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note: If
a change in the CMCON register
10.8 Effects of a RESET
(C±OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR±<6>)
interrupt flag may not get set.
A device RESET forces the CMCON register to its
RESET state. This forces the Comparator module to be
in the comparator RESET mode, CM2:CM0 = 000.
This ensures that all potential inputs are analog inputs.
Device current is minimized when analog inputs are
present at RESET time. The comparators will be
powered-down during the RESET interval.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any write or read of CMCON. This will end the
mismatch condition.
10.9 Analog Input Connection
Considerations
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition and
allow flag bit CMIF to be cleared.
A simplified circuit for an analog input is shown in
Figure ±0-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
±0 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 65
PIC16F627A/628A/648A
FIGURE 10-4:
ANALOG INPUT MODE
VDD
VT = 0.6 V
RIC
RS < ±0 K
AIN
ILEAKAGE
±500 nA
CPIN
5 pF
VA
VT = 0.6 V
VSS
Legend
CPIN
= Input Capacitance
= Threshold Voltage
VT
ILEAKAGE
RIC
RS
= Leakage Current At The Pin
= Interconnect Resistance
= Source Impedance
= Analog Voltage
VA
TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
All Other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1Fh
CMCON C2OUT C1OUT C2INV
C1NV
INTE
CIS
CM2
T0IF
CM1
INTF
CM0
RBIF
0000 0000 0000 0000
0000 000x 0000 000u
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
RBIE
10Bh, 18Bh
0Ch
PIR1
PIE1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
8Ch
85h
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend:
x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’
DS40044A-page 66
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The equations used to calculate the output of the
Voltage Reference are as follows:
11.0 VOLTAGE REFERENCE
MODULE
if VRR = ±:
The Voltage Reference is a ±6-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure ±±-±. The block diagram
is given in Figure ±±-±.
VR<3:0>
---------------------
24
VREF =
× VDD
if VRR = 0:
1
--
VR<3:0>
---------------------
× VDD
VREF = VDD ×
+
4
32
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table ±7-3). Example ±±-± demonstrates how Voltage
Reference is configured for an output voltage of ±.25V
with VDD = 5.0V.
11.1 Voltage Reference Configuration
The Voltage Reference can output ±6 distinct voltage
levels for each range.
REGISTER 11-1: VRCON REGISTER (ADDRESS: 9Fh)
R/W-0
VREN
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
VROE
VRR
VR3
VR2
VR±
VR0
bit 7
bit 0
bit 7
bit 6
bit 5
VREN: VREF Enable
1= VREF circuit powered on
0= VREF circuit powered down, no IDD drain
VROE: VREF Output Enable
1= VREF is output on RA2 pin
0= VREF is disconnected from RA2 pin
VRR: VREF Range selection
1= Low Range
0= High Range
bit 4
Unimplemented: Read as '0'
bit 3-0
VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ ±5
When VRR = ±: VREF = (VR<3:0>/ 24) * VDD
When VRR = 0: VREF = ±/4 * VDD + (VR<3:0>/ 32) * VDD
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
FIGURE 11-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages
VREN
R
R
R
R
8R
8R
VRR
VSS
VSS
VR3
(From VRCON<3:0>)
VREF
16-1 Analog Mux
VR0
Note:
R is defined in Table 17-3.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 67
PIC16F627A/628A/648A
EXAMPLE 11-1:
VOLTAGE REFERENCE
CONFIGURATION
11.4 Effects of a RESET
A device RESET disables the Voltage Reference by
clearing bit VREN (VRCON<7>). This RESET also
disconnects the reference from the RA2 pin by clearing
bit VROE (VRCON<6>) and selects the high voltage
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
MOVLW
MOVWF
BSF
0x02
;4 Inputs Muxed
;to 2 comps.
STATUS,RP0 ;go to Bank 1
CMCON
MOVLW
MOVWF
MOVLW
MOVWF
BCF
0x07
;RA3-RA0 are
;outputs
TRISA
0xA6
VRCON
;enable VREF
;low range set VR<3:0>=6
STATUS,RP0 ;go to Bank 0
DELAY10 ;10µs delay
11.5 Connection Considerations
CALL
The
Voltage
Reference
Module
operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA<2> bit is set and the VROE bit,
VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
11.2 Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure ±±-±) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
tested absolute accuracy of the Voltage Reference can
be found in Table ±7-3.
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure ±±-2 shows an example buffering
technique.
11.3 Operation During SLEEP
When the device wakes up from SLEEP through an
interrupt or a Watchdog Timer time out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 11-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
Opamp
R(1)
RA2
VREF
Module
+
VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 11-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Value On
All Other
RESETS
Value On
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9Fh
1Fh
85h
VRCON VREN
VROE
VRR
—
VR3
CIS
VR2
CM2
VR1
CM1
VR0
CM0
000- 0000 000- 0000
0000 0000 0000 0000
CMCON C2OUT C1OUT C2INV
TRISA
C1INV
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Note: — = Unimplemented, read as ‘0’.
DS40044A-page 68
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The USART can be configured in the following modes:
12.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
• Asynchronous (full-duplex)
• Synchronous - Master (half-duplex)
• Synchronous - Slave (half-duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:±>, have to
be set in order to configure pins RB2/TX/CK and RB±/
RX/DT as the Universal Synchronous Asynchronous
Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) is also known as a Serial Com-
munications Interface or SCI. The USART can be con-
figured as a full-duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
minals and personal computers, or it can be configured
as a half-duplex synchronous system that can commu-
nicate with peripheral devices such as A/D or D/A inte-
grated circuits, Serial EEPROMs, etc.
Register ±2-± shows the Transmit Status and Control
Register (TXSTA) and Register ±2-2 shows the
Receive Status and Control Register (RCSTA).
REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-±
R/W-0
TX9D
TRMT
bit 7
bit 0
bit 7
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6
bit 5
bit 4
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
(1)
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode
1= High speed
0= Low speed
Synchronous mode
Unused in this mode
bit ±
bit 0
TRMT: Transmit Shift Register STATUS bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
Note: SREN/CREN overrides TXEN in SYNC mode.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 69
PIC16F627A/628A/648A
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
R/W-0
ADEN
R-0
R-0
R-x
FERR
OERR
RX9D
bit 7
bit 0
bit 7
SPEN: Serial Port Enable bit
(Configures RB±/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:±> are set)
1= Serial port enabled
0= Serial port disabled
bit 6
bit 5
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = ±):
1= Enables address detection, enable interrupt and load of the receive buffer when RSR<8>
is set
0= Disables address detection, all bytes are received, and ninth bit can be used as parity bit
Asynchronous mode 8-bit (RX9=0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2
bit ±
bit 0
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of received data (Can be parity bit)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 70
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
EXAMPLE 12-1:
CALCULATING BAUD
RATE ERROR
12.1 USART Baud Rate Generator
(BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode bit BRGH is ignored.
Table ±2-± shows the formula for computation of the
baud rate for different USART modes, which only apply
in Master mode (internal clock).
Fosc
----------------------
Desired Baud Rate =
64(x + 1)
16000000
-----------------------
64(x + 1)
9600 =
x = 25.042
16000000
--------------------------
64(25 + 1)
Given the desired baud rate and FOSC, the nearest
integer value for the SPBRG register can be calculated
using the formula in Table ±2-±. From this, the error in
baud rate can be determined.
Calculated Baud Rate =
= 9615
(Calculated Baud Rate - Desired Baud Rate)
----------------------------------------------------------------------------------------------------------
Desired Baud Rate
Example ±2-± shows the calculation of the baud rate
error for the following conditions:
Error =
FOSC = ±6 MHz
Desired Baud Rate = 9600
BRGH = 0
9615 – 9600
-----------------------------
9600
=
= 0.16%
SYNC = 0
It may be advantageous to use the high baud rate
(BRGH = ±) even for slower baud clocks. This is
because the FOSC/(±6(X + ±)) equation can reduce the
baud rate error in some cases.
Writing a new value to the SPBRG register, causes the
BRG timer to be RESET (or cleared), this ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
TABLE 12-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+±))
(Synchronous) Baud Rate = FOSC/(4(X+±))
Baud Rate= FOSC/(±6(X+±))
NA
Legend: X = value in SPBRG (0 to 255)
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on all
other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
98h
18h
99h
TXSTA
RCSTA
SPBRG
CSRC
SPEN
TX9
RX9
TXEN SYNC
SREN CREN
—
BRGH
FERR
TRMT TX9D 0000 -010
OERR RX9D 0000 000x
0000 0000
0000 -010
0000 000x
0000 0000
ADEN
Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'.
Shaded cells are not used by the BRG.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 71
PIC16F627A/628A/648A
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
SPBRG 16 MHz
value
SPBRG 10 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
NA
—
—
—
—
NA
NA
—
—
—
—
NA
—
—
—
—
NA
2.4
NA
—
—
NA
—
—
NA
—
—
9.6
NA
—
—
NA
—
—
9.766
19.23
75.76
96.15
312.5
500
+1.73%
+0.16%
-1.36%
+0.16%
+4.17%
0
255
129
32
25
7
19.2
76.8
96
19.53
76.92
96.15
294.1
500
+1.73%
+0.16%
+0.16%
-1.96
0
255
64
51
16
9
19.23
76.92
95.24
307.69
500
+0.16%
+0.16%
-0.79%
+2.56%
0
207
51
41
12
7
300
500
HIGH
LOW
4
5000
19.53
—
0
4000
15.625
—
0
2500
9.766
—
0
—
255
—
255
—
255
FOSC = 7.15909 MHz
SPBRG 5.0688 MHz
value
KBAUD
SPBRG 4 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
—
—
—
—
NA
NA
—
—
—
—
NA
NA
—
—
—
—
103
51
12
9
NA
—
2.4
NA
—
—
NA
—
—
NA
—
9.6
9.622
19.24
77.82
94.20
298.3
+0.23%
+0.23%
+1.32
-1.88
-0.57
185
92
22
18
5
9.6
0
131
65
15
12
3
9.615
19.231
75.923
1000
NA
+0.16%
+0.16%
+0.16%
+4.17%
19.2
76.8
96
19.2
79.2
97.48
316.8
0
+3.13%
+1.54%
5.60%
300
—
—
—
500
NA
—
—
NA
—
NA
—
—
—
—
HIGH
LOW
1789.8
6.991
—
—
0
1267
0
100
—
—
0
255
4.950
255
3.906
255
FOSC = 3.579545 MHz
SPBRG 1 MHz
value
SPBRG 32.768 kHz
value
KBAUD
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
2.4
NA
NA
NA
—
—
—
—
—
—
NA
—
—
0.303
1.170
NA
+1.14%
-2.48%
26
6
1.202
2.404
+0.16%
+0.16%
207
103
—
—
—
—
—
—
—
9.6
9.622
19.04
74.57
+0.23%
-0.83%
-2.90%
92
46
11
9.615
19.24
83.34
+0.16%
+0.16%
+8.51%
25
12
2
NA
NA
NA
19.2
76.8
—
—
96
99.43
+3.57%
0.57%
8
NA
NA
NA
—
—
—
—
—
—
—
—
—
300
500
298.3
NA
2
NA
NA
—
—
—
—
—
—
HIGH
LOW
894.9
3.496
0
250
—
—
0
8.192
0.032
—
—
0
255
0.9766
255
255
DS40044A-page 72
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
SPBRG 16 MHz
value
SPBRG 10 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
—
—
255
129
32
15
3
NA
1.202
2.404
9.615
19.23
83.33
NA
—
+0.16%
+0.16%
+0.16%
+0.16%
+8.51%
—
—
207
103
25
12
2
NA
1.202
2.404
9.766
19.53
78.13
NA
—
+0.16%
+0.16%
+1.73%
+1.73V
+1.73%
—
—
129
64
15
7
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
+1.73%
+0.16%
-1.36%
+1.73%
+1.73%
+8.51%
+4.17%
—
2.4
9.6
19.2
76.8
96
1
2
—
—
—
—
0
300
500
HIGH
LOW
0
NA
—
—
NA
—
—
0
NA
—
—
NA
—
312.5
1.221
—
250
—
0
156.3
0.6104
—
—
255
0.977
—
255
—
255
FOSC = 7.15909 MHz
SPBRG 5.0688 MHz
value
KBAUD
SPBRG 4 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
NA
1.203
2.380
9.322
18.64
NA
—
+0.23%
-0.83%
-2.90%
-2.90%
—
—
92
46
11
5
0.31
1.2
+3.13%
255
65
32
7
0.3005
1.202
2.404
NA
-0.17%
+1.67%
+1.67%
—
207
51
25
—
0
0
2.4
2.4
9.6
9.9
+3.13%
+3.13%
+3.13%
—
19.2
76.8
96
19.8
79.2
NA
3
NA
—
—
—
—
—
—
0
0
NA
—
—
NA
—
—
—
—
0
NA
—
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
—
NA
—
NA
—
NA
—
—
111.9
0.437
—
79.2
0.3094
—
62.500
3.906
—
0
—
255
—
255
—
255
FOSC = 3.579545 MHz
SPBRG 1 MHz
value
SPBRG 32.768 kHz
value
KBAUD
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
ERROR
(decimal)
(decimal)
(decimal)
0.3
1.2
0.301
1.190
2.432
9.322
18.64
NA
+0.23%
-0.83%
+1.32%
-2.90%
-2.90%
—
185
46
22
5
0.300
1.202
2.232
NA
+0.16%
+0.16%
-6.99%
—
51
12
6
0.256
NA
-14.67%
—
1
—
—
—
—
—
—
—
—
0
2.4
NA
—
9.6
—
—
—
—
—
—
0
NA
—
19.2
76.8
96
2
NA
—
NA
—
—
—
—
—
0
NA
—
NA
—
NA
—
NA
—
NA
—
300
500
HIGH
LOW
NA
—
NA
—
NA
—
NA
—
NA
—
NA
—
55.93
0.2185
—
15.63
0.0610
—
0.512
0.0020
—
—
255
—
255
—
255
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 73
PIC16F627A/628A/648A
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
SPBRG 16 MHz
value
SPBRG 10 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
9600
9.615
19.230
37.878
56.818
113.636
250
+0.16%
+0.16%
-1.36%
-1.36%
-1.36%
0
129
64
32
21
10
4
9.615
19.230
38.461
58.823
111.111
250
+0.16%
+0.16%
+0.16%
+2.12%
-3.55%
0
103
51
25
16
8
9.615
18.939
39.062
56.818
125
+0.16%
-1.36%
+1.7%
-1.36%
+8.51%
—
64
32
15
10
4
19200
38400
57600
115200
250000
625000
1250000
3
NA
—
0
625
0
1
NA
—
—
—
625
0
1250
0
0
NA
—
NA
—
—
FOSC = 7.16 MHz
SPBRG 5.068 MHz
value
KBAUD
SPBRG 4 MHz
value
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
ERROR
KBAUD
ERROR
(decimal)
(decimal)
(decimal)
9600
9.520
19.454
37.286
55.930
111.860
NA
-0.83%
+1.32%
-2.90%
-2.90%
-2.90%
—
46
22
11
7
9598.485
18632.35
39593.75
52791.67
105583.3
316750
NA
0.016%
-2.956%
3.109%
-8.348%
-8.348%
26.700%
—
32
16
7
9615.385
19230.77
35714.29
62500
0.160%
0.160%
-6.994%
8.507%
8.507%
0.000%
—
25
12
6
19200
38400
57600
115200
250000
625000
1250000
5
3
3
2
125000
250000
NA
1
—
—
—
0
0
NA
—
—
—
—
—
NA
—
NA
—
NA
—
FOSC = 3.579 MHz
SPBRG 1 MHz
value
SPBRG 32.768 kHz
value
KBAUD
SPBRG
value
BAUD
RATE (K)
KBAUD
ERROR
KBAUD
ERROR
ERROR
(decimal)
(decimal)
(decimal)
9600
9725.543
18640.63
37281.25
55921.88
111243.8
223687.5
NA
1.308%
-2.913%
-2.913%
-2.913%
-2.913%
-10.525%
—
22
11
5
8.928
20833.3
31250
62500
NA
-6.994%
8.507%
-18.620%
+8.507
—
6
2
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
19200
38400
57600
115200
250000
625000
1250000
1
3
0
1
—
—
—
—
0
NA
—
—
—
NA
—
NA
—
NA
—
DS40044A-page 74
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The data on the RB±/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth fall-
ing edges of a x±6 clock (Figure ±2-3). If bit BRGH is
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure ±2-4 and
Figure ±2-5).
FIGURE 12-1:
RX PIN SAMPLING SCHEME. BRGH = 0
RX
(RB1/RX/DT pin)
START bit
bit0
Baud CLK for all but START bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
FIGURE 12-2:
RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
bit0
bit1
START Bit
Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1
2
3
4
1
2
3
4
1
2
Q2, Q4 CLK
Samples
Samples
Samples
FIGURE 12-3:
RX PIN SAMPLING SCHEME, BRGH = 1
RX pin
START Bit
bit0
Baud CLK for all but START bit
Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1
2
3
4
Q2, Q4 CLK
Samples
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 75
PIC16F627A/628A/648A
FIGURE 12-4:
RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1
RX
(RB1/RX/DT pin)
START bit
bit0
Baud CLK for all but START bit
Baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
1
2
3
Samples
ware. It will RESET only when new data is loaded into
the TXREG register. While flag bit TXIF indicated the
status of the TXREG register, another bit TRMT
(TXSTA<±>) shows the status of the TSR register.
STATUS bit TRMT is a read only bit which is set when
the TSR register is empty. No interrupt logic is tied to
this bit, so the user has to poll this bit in order to deter-
mine if the TSR register is empty.
12.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits and one STOP bit). The most common data format
is 8-bit. A dedicated 8-bit baud rate generator is used
to derive baud rate frequencies from the oscillator. The
USART transmits and receives the LSb first. The
USART’s transmitter and receiver are functionally inde-
pendent but use the same data format and baud rate.
The baud rate generator produces a clock either x±6 or
x64 of the bit shift rate, depending on bit BRGH
(TXSTA<2>). Parity is not supported by the hardware,
but can be implemented in software (and stored as the
ninth data bit). Asynchronous mode is stopped during
SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure ±2-5). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate trans-
fer to TSR resulting in an empty TXREG. A back-to-
back transfer is thus possible (Figure ±2-7). Clearing
enable bit TXEN during a transmission will cause the
transmission to be aborted and will RESET the trans-
mitter. As a result the RB2/TX/CK pin will revert to hi-
impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
12.2.1
USART ASYNCHRONOUS
TRANSMITTER
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit maybe loaded in the TSR regis-
ter.
The USART transmitter block diagram is shown in
Figure ±2-5. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR±<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE±<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
DS40044A-page 76
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 12-5:
USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
8
TXIE
MSb
(8)
LSb
0
Pin Buffer
and Control
²
² ²
TSR register
RB2/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
Follow these steps when setting up an Asynchronous
Transmission:
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section ±2.±)
3. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set transmit
bit TX9.
6. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Load data to the TXREG register (starts trans-
mission).
FIGURE 12-6:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
START Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 77
PIC16F627A/628A/648A
FIGURE 12-7:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
START Bit
START Bit
WORD 2
Bit 0
Bit 1
Bit 7/8
Bit 0
STOP Bit
TXIF bit
(interrupt reg. flag)
WORD 1
TRMT bit
(Transmit shift
reg. empty flag)
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
.
This timing diagram shows two consecutive transmissions.
Note:
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
all other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
19h
8Ch
98h
99h
PIR1
EEIF
CMIF
RX9
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA
SPEN
SREN CREN ADEN
FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
TXREG USART Transmit data register
PIE1
EEIE
CMIE
TX9
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
CSRC
TXEN
SYNC
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.
DS40044A-page 78
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
double buffered register, (i.e., it is a two deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR register. On the detection of the
STOP bit of the third byte, if the RCREG register is still
full then overrun error bit OERR (RCSTA<±>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
so it is essential to clear error bit OERR if it is set. Fram-
ing error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with new
values, therefore it is essential for the user to read the
RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
12.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure ±2-8.
The data is received on the RB±/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at x±6 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate or at FOSC.
When Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR±<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE±<5>). Flag bit RCIF is a read-only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
FIGURE 12-8:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
³ 64
or
³ 16
SPBRG
RSR register
LSb
MSb
0
Baud Rate Generator
1
7
Stop (8)
Start
² ² ²
RB1/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9
Enable
Load of
ADEN
Receive
Buffer
RX9
ADEN
RSR<8>
8
RX9D
RX9D
RCREG register
RCREG register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 79
PIC16F627A/628A/648A
FIGURE 12-9:
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START
BIT
START
BIT8 STOP BIT BIT0
BIT
RB1/RX/DT (PIN)
BIT0 BIT1
STOP
BIT
BIT8
RCV SHIFT REG
RCV BUFFER REG
WORD 1
RCREG
BIT8 = 0, DATA BYTE
BIT8 = 1, ADDRESS BYTE
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
'1'
'1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
FIGURE 12-10:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START
BIT
START
BIT8 STOP BIT BIT0
BIT
RB1/RX/DT (PIN)
BIT0 BIT1
STOP
BIT
BIT8
RCV SHIFT
REG
RCV BUFFER REG
WORD 1
RCREG
BIT8 = 1, ADDRESS BYTE
BIT8 = 0, DATA BYTE
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
'1'
'1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
FIGURE 12-11:
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY
VALID DATA BYTE
START
BIT
START
BIT8 STOP BIT BIT0
BIT
RB1/RX/DT (PIN)
BIT0 BIT1
STOP
BIT
BIT8
RCV SHIFT
REG
RCV BUFFER REG
WORD 1
RCREG
WORD 2
RCREG
BIT8 = 1, ADDRESS BYTE
BIT8 = 0, DATA BYTE
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN
(ADDRESS MATCH
ENABLE)
Note:
This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents
of the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.
DS40044A-page 80
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Follow these steps when setting up an Asynchronous
Reception:
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH. (Section ±2.±).
3. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. Enable the reception by setting bit CREN.
7. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
±0. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA
RCREG
PIE1
EEIF
CMIF RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
SPEN
RX9 SREN CREN ADEN FERR
OERR
RX9D 0000 000x 0000 000x
USART Receive data register
0000 0000 0000 0000
EEIE
CMIE RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA
CSRC
TX9 TXEN SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 81
PIC16F627A/628A/648A
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '±'). When ADEN is
disabled (='0'), all data bytes are received and the 9th
bit can be used as the parity bit.
12.3 USART Address Detect Function
12.3.1
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
The receive block diagram is shown in Figure ±2-8.
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a spe-
cial provision for multi-processor communication. Mul-
tiprocessor communication is enabled by setting the
ADEN bit (RCSTA<3>) along with the RX9 bit. The port
is now programmed such that when the last bit is
received, the contents of the receive shift register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the
receive interrupt is set if and only if RSR<8> = ±. This
feature can be used in a multi-processor system as fol-
lows:
Reception is enabled by setting bit CREN
(RCSTA<4>).
12.3.1.1
Setting up 9-bit mode with Address
Detect
Follow these steps when setting up Asynchronous
Reception with Address Detect Enabled:
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a '±'
(instead of a '0' for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling mul-
tiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘±’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
3. Enable asynchronous communication by setting
or clearing bit SYNC and setting bit SPEN.
4. If interrupts are desired, then set enable bit
RCIE.
5. Set bit RX9 to enable 9-bit reception.
6. Set ADEN to enable address detect.
7. Enable the reception by setting enable bit CREN
or SREN.
8. Flag bit RCIF will be set when reception is com-
plete, and an interrupt will be generated if
enable bit RCIE was set.
9. Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
When ADEN is enabled (='±'), all data bytes are
ignored. Following the STOP bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
±0. If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
±±. If the device has been addressed (RSR<8> = ‘±’
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and inter-
rupt the CPU.
TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on
all other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA SPEN RX9
RCREG USART Receive data register
EEIF CMIF
RCIF
TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
SREN CREN ADEN FERR
OERR
RX9D 0000 000x 0000 000x
0000 0000 0000 0000
PIE1
EEIE CMIE
RCIE
TXIE
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA CSRC TX9
SPBRG
TXEN
SYNC
BRGH
TRMT
TX9D 0000 -010 0000 -010
Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
DS40044A-page 82
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will RESET
the transmitter. The DT and CK pins will revert to hi-
impedance. If either bit CREN or bit SREN is set, dur-
ing a transmission, the transmission is aborted and the
DT pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic however is not
RESET although it is disconnected from the pins. In
order to RESET the transmitter, the user has to clear bit
TXEN. If bit SREN is set (to interrupt an on-going trans-
mission and receive a single word), then after the sin-
gle word is received, bit SREN will be cleared and the
serial port will revert back to transmitting since bit
TXEN is still set. The DT line will immediately switch
from hi-impedance Receive mode to transmit and start
driving. To avoid this, bit TXEN should be cleared.
12.4 USART Synchronous Master
Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RB2/TX/CK and RB±/RX/DT I/O pins to
CK (clock) and DT (data) lines respectively. The Master
mode indicates that the processor transmits the master
clock on the CK line. The Master mode is entered by
setting bit CSRC (TXSTA<7>).
12.4.1
USART SYNCHRONOUS MASTER
TRANSMISSION
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
The USART transmitter block diagram is shown in
Figure ±2-5. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit, TXIF (PIR±<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE±<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will RESET only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the
status of the TXREG register, another bit TRMT
(TXSTA<±>) shows the status of the TSR register.
TRMT is a read only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty. The TSR is not mapped in data memory
so it is not available to the user.
Follow these steps when setting up a Synchronous
Master Transmission:
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate (Section ±2.±).
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
4. If interrupts are desired, then set enable bit
TXIE.
5. If 9-bit transmission is desired, then set bit TX9.
6. Enable the transmission by setting bit TXEN.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure ±2-±2). The transmission can also be started
by first loading the TXREG register and then setting bit
TXEN (Figure ±2-±3). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN, and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
8. Start transmission by loading data to the TXREG
register.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 83
PIC16F627A/628A/648A
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on all
other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
19h
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit data register
0000 0000 0000 0000
PIE1
EEIE
CMIE RCIE TXIE
TX9 TXEN SYNC
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA CSRC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
FIGURE 12-12:
SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q1Q2Q3Q4
BIT 0
BIT 1
BIT 2
BIT 7
BIT 0
BIT 1
BIT 7
RB1/RX/DT PIN
RB2/TX/CK PIN
WORD 2
WORD 1
WRITE TO
TXREG REG
WRITE WORD1
WRITE WORD2
TXIF BIT
(INTERRUPT FLAG)
T
TRMT BIT
'1'
'1'
TXEN BIT
Note:
Sync Master Mode; SPBRG = ‘0’. Continuous transmission of two 8-bit words.
FIGURE 12-13:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB1/RX/DT PIN
BIT0
BIT2
BIT1
BIT6
BIT7
RB2/TX/CK PIN
WRITE TO
TXREG REG
TXIF BIT
TRMT BIT
TXEN BIT
DS40044A-page 84
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
12.4.2
USART SYNCHRONOUS MASTER
RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB±/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR±<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE±<5>). Flag bit RCIF is a read only bit which is
RESET by the hardware. In this case it is RESET when
the RCREG register has been read and is empty. The
RCREG is a double buffered register, (i.e., it is a two
deep FIFO). It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<±>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
Follow these steps when setting up a Synchronous
Master Reception:
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Initialize the SPBRG register for the appropriate
baud rate. (Section ±2.±)
3. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
4. Ensure bits CREN and SREN are clear.
5. If interrupts are desired, then set enable bit
RCIE.
6. If 9-bit reception is desired, then set bit RX9.
7. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
8. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
9. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
±0. Read the 8-bit received data by reading the
RCREG register.
±±. If any error occurred, clear the error by clearing
bit CREN.
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on all
other
Value on:
Address Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
RESETS
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA SPEN
RCREG USART Receive data register
PIE1 EEPIE CMIE RCIE TXIE
TXSTA CSRC TX9 TXEN SYNC
SPBRG Baud Rate Generator Register
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 000x 0000 000x
0000 0000 0000 0000
—
—
CCP1IE TMR2IE TMR1IE -000 0000 -000 -000
BRGH
TRMT
TX9D 0000 -010 0000 -010
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 85
PIC16F627A/628A/648A
FIGURE 12-14:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
RB1/RX/DT PIN
RB2/TX/CK PIN
WRITE TO
BIT SREN
SREN BIT
'0'
'0'
CREN BIT
RCIF BIT
(INTERRUPT)
READ
RXREG
Note:
Timing diagram demonstrates Sync Master Mode with bit SREN = ‘1’ and bit BRG = ‘0’.
Follow these steps when setting up a Synchronous
Slave Transmission:
12.5 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RB2/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
12.5.1
USART SYNCHRONOUS SLAVE
TRANSMIT
3. Clear bits CREN and SREN.
4. If interrupts are desired, then set enable bit
TXIE.
The operation of the synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
5. If 9-bit transmission is desired, then set bit TX9.
6. Enable the transmission by setting enable bit
TXEN.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
7. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
a) The first word will immediately transfer to the
TSR register and transmit.
8. Start transmission by loading data to the TXREG
register.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
DS40044A-page 86
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
2. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
12.5.2
USART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Mlave
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode.
3. If interrupts are desired, then set enable bit
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. To enable reception, set enable bit CREN.
If receive is enabled, by setting bit CREN, prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
Follow these steps when setting up a Synchronous
Slave Reception:
9. If any error occurred, clear the error by clearing
bit CREN.
±. TRISB<±> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB±/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on all
other
RESETS
Value on
POR
Address Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
18h
19h
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA SPEN
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 000x 0000 000x
TXREG USART Transmit data register
0000 0000 0000 0000
PIE1
EEIE
CMIE RCIE TXIE
TX9 TXEN SYNC
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA CSRC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on all
Value on
other
Address Name
Bit 7
Bit 6 Bit 5 Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR
RESETS
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
EEIF
CMIF RCIF TXIF
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
RCSTA SPEN
RCREG USART Receive data register
RX9 SREN CREN ADEN
FERR
OERR
RX9D 0000 000x 0000 000x
0000 0000 0000 0000
PIE1
EEIE
CMIE RCIE TXIE
TX9 TXEN SYNC
—
—
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
TXSTA CSRC
BRGH
TRMT
TX9D 0000 -010 0000 -010
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 87
PIC16F627A/628A/648A
NOTES:
DS40044A-page 88
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
13.0 DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers (SFRs). There are four SFRs used to read
and write this memory. These registers are:
• EECON±
When the device is code protected, the CPU can
continue to read and write the data EEPROM memory.
• EECON2 (Not a physically implemented register)
A device programmer can no longer access
this memory.
• EEDATA
• EEADR
Additional information on the Data EEPROM is avail-
able in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. PIC±6F627A/628A devices have ±28
bytes of data EEPROM with an address range from 0h
to 7Fh. PIC±6F648A device has 256 bytes of data
EEPROM with an address range from 0h to FFh.
REGISTER 13-1: EEDATA REGISTER (ADDRESS: 9Ah)
R/W-x R/W-x R/W-x R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EEDAT7 EEDAT6 EEDAT5 EEDAT4
bit 7
EEDAT3
EEDAT2 EEDAT± EEDAT0
bit 0
bit 7-0
EEDATn: Byte value to write to or read from Data EEPROM memory location.
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
REGISTER 13-2: EEADR REGISTER (ADDRESS: 9Bh)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EADR7
EADR6
EADR5
EADR4
EADR3
EADR2 EADR±
EADR0
bit 7
bit 0
bit 7
PIC16F627A/628A - Unimplemented Address: Must be set to ‘0’
PIC16F648A - EEADR: Set to ‘±’ specifies top ±28 locations (±28-256) of EEPROM Read/Write
Operation
bit 6-0
EEADR: Specifies one of ±28 locations of EEPROM Read/Write Operation
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 89
PIC16F627A/628A/648A
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
13.1 EEADR
The PIC±6F648A EEADR register addresses 256
bytes of data EEPROM. All eight bits in the register
(EEADR<7:0>) are required.
The PIC±6F627A/628A EEADR register addresses
only the first ±28 bytes of data EEPROM so only seven
of the eight bits in the register (EEADR<6:0>) are
required. The upper bit is address decoded. This
means that this bit should always be '0' to ensure that
the address is in the ±28 byte memory space.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset or a WDT Time out Reset during normal opera-
tion. In these situations, following RESET, the user can
check the WRERR bit and rewrite the location. The
data and address will be unchanged in the EEDATA
and EEADR registers.
13.2 EECON1 AND EECON2
REGISTERS
Interrupt flag bit EEIF in the PIR± register is set when
write is complete. This bit must be cleared in software.
EECON± is the control register with four low order bits
physically implemented. The upper-four bits are non-
existent and read as '0's.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
REGISTER 13-3: EECON1 REGISTER (ADDRESS: 9Ch) DEVICES
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-0
WREN
R/S-0
WR
R/S-0
RD
WRERR
bit 7
bit 0
bit 7-4
bit 3
Unimplemented: Read as '0'
WRERR: EEPROM Error Flag bit
1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during nor-
mal operation or BOR Reset)
0= The write operation completed
bit 2
bit ±
WREN: EEPROM Write Enable bit
1= Allows write cycles
0= Inhibits write to the data EEPROM
WR: Write Control bit
1= initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1= Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0= Does not initiate an EEPROM read
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS40044A-page 90
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit in the
PIR± registers must be cleared by software.
13.3 READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON±<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user
(during a write operation).
13.5 WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the Data
EEPROM should be verified (Example ±3-3) to the
desired value to be written. This should be used in
applications where an EEPROM bit will be stressed
near the specification limit.
EXAMPLE 13-1:
BSF
DATA EEPROM READ
;Bank 1
STATUS, RP0
CONFIG_ADDR
EEADR
MOVLW
MOVWF
BSF
;
;Address to read
;EE Read
;W = EEDATA
;Bank 0
EXAMPLE 13-3:
WRITE VERIFY
EECON1, RD
EEDATA, W
STATUS, RP0
MOVF
BCF
BSF STATUS, RP0;Bank 1
MOVF EEDATA, W
BSF
EECON1, RD ;Read the
;value written
;
;Is the value written (in W reg) and
13.4 WRITING TO THE EEPROM DATA
MEMORY
;read (in EEDATA) the same?
;
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte.
SUBWF EEDATA, W
;
BTFSS STATUS, Z ;Is difference 0?
GOTO WRITE_ERR ;NO, Write error
:
:
;YES, Good write
;Continue program
EXAMPLE 13-2:
DATA EEPROM WRITE
BSF
BSF
STATUS, RP0
EECON1, WREN
;Bank 1
;Enable write
;Disable INTs.
;
13.6 PROTECTION AGAINST
SPURIOUS WRITE
BCF
INTCON, GIE
55h
MOVLW
MOVWF
MOVLW
MOVWF
BSF
EECON2
AAh
;Write 55h
;
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also
when enabled, the Power-up Timer (72 ms duration)
prevents EEPROM write.
EECON2
EECON1,WR
;Write AAh
;Set WR bit
;begin write
;Enable INTs.
BSF INTCON, GIE
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number what is not equal to
the required cycles to execute the required sequence
will cause the data not to be written into the EEPROM.
The write initiate sequence, and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
Additionally, the WREN bit in EECON± must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 91
PIC16F627A/628A/648A
that change infrequently (such as constants, IDs, cali-
bration, etc.) should be stored in FLASH program
memory.
13.7 Using the Data EEPROM
The data EEPROM is a high endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program vari-
ables or other data that are updated often). Frequently
changing values will typically be updated more often
than specification D±24. If this is not the case, an array
refresh must be performed. For this reason, variables
A simple data EEPROM refresh routine is shown in
Example ±3-4.
Note: If data EEPROM is only used to store con-
stants and/or data that changes rarely, an
array refresh is likely not required. See
specification D±24.
EXAMPLE 13-4:
DATA EEPROM REFRESH ROUTINE
clrf
bcf
bcf
EEADR
; Start at address 0
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
EECON1,CFGS
EECON1,EEPGD
INTCON,GIE
EECON1,WREN
bcf
bsf
Loop
bsf
; Loop to refresh array
; Read current address
;
EECON1,RD
55h
movlw
movwf
movlw
movwf
bsf
EECON2
AAh
; Write 55h
;
; Write AAh
EECON2
EECON1,WR
EECON1,WR
$-2
; Set WR bit to begin write
; Wait for write to complete
btfsc
bra
incfsz EEADR,F
Loop
; Increment address
; Not zero, do it again
bra
bcf
bsf
EECON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
13.8 DATA EEPROM OPERATION
DURING CODE PROTECT
When the device is code protected, the CPU is able to
read and write data to the Data EEPROM.
TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on
Power-on
Reset
Value on all
other
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESETS
9Ah
EEDATA
EEADR
EEPROM data register
xxxx xxxx
xxxx xxxx
---- x000
---- ----
uuuu uuuu
uuuu uuuu
---- q000
---- ----
9Bh
9Ch
9Dh
EEPROM address register
EECON1
—
—
—
—
WRERR WREN
WR
RD
EECON2(1) EEPROM control register 2
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register
DS40044A-page 92
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
14.1 Configuration Bits
14.0 SPECIAL FEATURES OF THE
CPU
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '±') to select various
device configurations. These bits are mapped in
program memory location 2007h.
Special circuits to deal with the needs of real-time
applications are what sets a microcontroller apart from
other processors. The PIC±6F627A/628A/648A family
has a host of such features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving Operating
modes and offer code protection.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special configuration memory space (2000h –
3FFFh), which can be accessed only during program-
ming. See Programming Specification (DS4±±96) for
additional information.
These are:
±. OSC selection
2. RESET
3. Power-on Reset (POR)
4. Power-up Timer (PWRT)
5. Oscillator Start-Up Timer (OST)
6. Brown-out Reset (BOR)
7. Interrupts
8. Watchdog Timer (WDT)
9. SLEEP
±0. Code protection
±±. ID Locations
±2. In-Circuit Serial Programming™ (ICSP™)
The PIC±6F627A/628A/648A has a Watchdog Timer
which is controlled by configuration bits. It runs off its
own RC oscillator for added reliability. There are two
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which pro-
vides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in RESET while the
power supply stabilizes. There is also circuitry to
RESET the device if a Brown-out occurs. With these
three functions on-chip, most applications need no
external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 93
PIC16F627A/628A/648A
REGISTER 14-1: CONFIGURATION WORD
CP
—
—
—
—
CPD
LVP
BOREN MCLRE FOSC2 PWRTE
WDTE
F0SC1
F0SC0
bit 13
bit 0
bit 13:
CP: FLASH Program Memory Code Protection bit(2)
(PIC16F648A)
1= Code protection off
0= 0000h to 0FFFh code protected
(PIC16F628A)
1= Code protection off
0= 0000h to 07FFh code protected
(PIC16F627A)
1= Code protection off
0= 0000h to 03FFh code protected
bit 12-9:
bit 8:
Unimplemented: Read as ‘0’
CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code protected
bit 7:
LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6:
BOREN: Brown-out Reset Enable bit (1)
1 = BOR Reset enabled
0 = BOR Reset disabled
bit 5:
MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to VDD
bit 3:
PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0:
FOSC2:FOSC0: Oscillator Selection bits(4)
111 = RC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
110 = RC oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor and Capacitor on RA7/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer (PWRT) the way it did in the PIC16F627/628.
2: The code protection scheme has changed from the code protection scheme used in the PIC16F627/628. The entire FLASH program
memory needs to be bulk erased to set the CP bit, turning the code protection off. See Programming Specification DS41196 for details.
3: The entire data EEPROM needs to be bulk erased to set the CPD bit, turning the code protection off. See Programming Specification
DS41196 for details.
4: When MCLR is asserted in INTOSC mode, the internal clock oscillator is disabled.
Legend
R = Readable bit
-n = Value at POR
W = Writable bit
1 = bit is set
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
DS40044A-page 94
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 14-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
14.2 Oscillator Configurations
14.2.1
OSCILLATOR TYPES
Mode
Freq
OSC1(C1)
OSC2(C2)
The PIC±6F627A/628A/648A can be operated in eight
different oscillator options. The user can program three
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
XT
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
• LP
• XT
• HS
• RC
Low Power Crystal
Note:
Higher capacitance increases the stability of the oscil-
lator but also increases the start-up time. These values
are for design guidance only. Since each resonator has
its own characteristics, the user should consult the res-
onator manufacturer for appropriate values of external
components.
Crystal/Resonator
High Speed Crystal/Resonator
External Resistor/Capacitor (2 modes)
• INTOSC Internal Precision Oscillator (2 modes)
• EC
External Clock In
TABLE 14-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
14.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Mode
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
15 - 30 pF
0 - 15 pF
15 - 30 pF
0 - 15 pF
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC± and OSC2 pins to establish
oscillation (Figure ±4-±). The PIC±6F627A/628A/648A
oscillator design requires the use of a parallel cut crys-
tal. Use of a series cut crystal may give a frequency out
of the crystal manufacturers specifications. When in
XT, LP or HS modes, the device can have an external
clock source to drive the OSC± pin (Figure ±4-4).
XT
HS
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
Note:
Higher capacitance increases the stability of the oscil-
lator but also increases the start-up time. These values
are for design guidance only. A series resistor (RS)
may be required in HS mode as well as XT mode to
avoid overdriving crystals with low drive level specifica-
tion. Since each crystal has its own characteristics, the
user should consult the crystal manufacturer for appro-
priate values of external components.
FIGURE 14-1:
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
CONFIGURATION)
14.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
OSC1
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used; one with series resonance, or one with parallel
resonance.
C1
XTAL
SLEEP
RF
OSC2
RS(1)
FOSC
C2
PIC16F627A/628A/648A
Note 1: A series resistor may be required for AT strip cut
crystals.
Figure ±4-2 shows implementation of a parallel reso-
nant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the ±80° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The ±0 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
2: See Table 14-1 and Table 14-2 for recommended
values of C1 and C2.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 95
PIC16F627A/628A/648A
FIGURE 14-2:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
FIGURE 14-4:
EXTERNAL CLOCK INPUT
OPERATION (EC, HS, XT
OR LP OSC
CONFIGURATION)
+5V
TO OTHER
DEVICES
Clock From
ext. system
RA7/OSC1/CLKIN
10K
4.7K
74AS04
PIC16F627A/628A/648A
PIC16F627A/628A/648A
RA6/OSC2/CLKOUT
CLKIN
74AS04
RA6
10K
14.2.6
RC OSCILLATOR
XTAL
For applications where precise timing is not a require-
ment, the RC oscillator option is available. The opera-
tion and functionality of the RC oscillator is dependent
upon a number of variables. The RC oscillator fre-
quency is a function of:
10K
C1
C2
• Supply voltage
Figure ±4-3 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a ±80°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias
the inverters in their linear region.
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature.
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure ±4-5 shows how the R/C combination is con-
nected.
FIGURE 14-3:
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
TO OTHER
DEVICES
330 KΩ
330 KΩ
74AS04
FIGURE 14-5:
RC OSCILLATOR MODE
74AS04
74AS04
CLKIN
VDD
PIC16F627A/628A/648A
0.1 PF
PIC16F627A/
628A/648A
REXT
RA7/OSC1/
CLKIN
Internal
Clock
XTAL
CEXT
VSS
14.2.4
PRECISION INTERNAL 4 MHZ
OSCILLATOR
FOSC/4
RA6/OSC2/CLKOUT
The internal precision oscillator provides a fixed 4 MHz
(nominal) system clock at VDD = 5 V and 25°C. See
Section ±7.0, Electrical Specifications, for information
on variation over voltage and temperature.
The RC Oscillator mode has two options that control
the unused OSC2 pin. The first allows it to be used as
a general purpose I/O port. The other configures the
pin as an output providing the Fosc signal (internal
clock divided by 4) for test or external synchronization
purposes.
14.2.5
EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the PIC±6F627A/
628A/648A provided that this external clock source
meets the AC/DC timing requirements listed in
Section ±7.6. Figure ±4-4 below shows how an exter-
nal clock circuit should be configured.
14.2.7
CLKOUT
The PIC±6F627A/628A/648A can be configured to pro-
vide a clock out signal by programming the configura-
tion word. The oscillator frequency, divided by 4 can be
used for test purposes or to synchronize other logic.
DS40044A-page 96
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
14.2.8
SPECIAL FEATURE: DUAL SPEED
OSCILLATOR MODES
14.3 RESET
The PIC±6F627A/628A/648A differentiates between
various kinds of RESET:
A software programmable dual speed Oscillator mode
is provided when the PIC±6F627A/628A/648A is con-
figured in the INTOSC Oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz nominal in the INTOSC
mode. Applications that require low current power sav-
ings, but cannot tolerate putting the part into SLEEP,
may use this mode.
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during SLEEP
d) WDT Reset (normal operation)
e) WDT wake-up (SLEEP)
f) Brown-out Reset (BOR)
There is a time delay associated with the transition
between Fast and Slow oscillator speeds. This Oscilla-
tor Speed Transition delay consists of two existing
clock pulses and eight new speed clock pulses. During
this Clock Speed Transition Delay the System Clock is
halted causing the processor to be frozen in time. Dur-
ing this delay the Program Counter and the Clock Out
stop.
Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, Brown-out Reset,
MCLR Reset, WDT Reset and MCLR Reset during
SLEEP. They are not affected by a WDT wake-up,
since this is viewed as the resumption of normal oper-
ation. TO and PD bits are set or cleared differently in
different RESET situations as indicated in Table ±4-4.
These bits are used in software to determine the nature
of the RESET. See Table ±4-7 for a full description of
RESET states of all registers.
The OSCF bit in the PCON register is used to control
Dual Speed mode. See Section 4.2.2.6, Register 4-6.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure ±4-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table ±7-7 for pulse width
specification.
FIGURE 14-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
Schmitt Trigger Input
SLEEP
MCLR/
VPP Pin
WDT
WDT
Module
Time out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
detect Reset
S
Q
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R
Q
OSC1/
CLKIN
Pin
PWRT
10-bit Ripple-counter
On-chip(1)
OSC
See Table 14-3 for time out situations.
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the INTOSC/RC oscillator.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 97
PIC16F627A/628A/648A
The Power-Up Time delay will vary from chip to chip
and due to VDD, temperature and process variation.
See DC parameters Table ±7-7 for details.
14.4 Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
14.4.3
OSCILLATOR START-UP TIMER
(OST)
14.4.1
POWER-ON RESET (POR)
The OST provides a ±024 oscillator cycle (from OSC±
input) delay after the PWRT delay is over. Program
execution will not start until the OST time out is com-
plete. This ensures that the crystal oscillator or resona-
tor has started and stabilized.
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper oper-
ation. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate exter-
nal RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
Electrical Specifications for details.
The OST time out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP. See Table ±7-7.
The POR circuit does not produce an internal RESET
when VDD declines.
14.4.4
BROWN-OUT RESET (BOR)
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
The PIC±6F627A/628A/648A have on-chip BOR cir-
cuitry. A configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the BOR Reset circuitry.
If VDD falls below VBOR for longer than TBOR, the
brown-out situation will RESET the chip. A RESET is
not guaranteed to occur if VDD falls below VBOR for
shorter than TBOR. VBOR and TBOR are defined in
Table ±7-2 and Table ±7-7, respectively.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until VDD rises
above BVDD (see Figure ±4-7). The Power-up Timer
will now be invoked, if enabled, and will keep the chip
in RESET an additional 72 ms.
14.4.2
POWER-UP TIMER (PWRT)
The PWRT provides a fixed 72 ms (nominal) time out
on power-up (POR) or if enabled from a Brown-out
Reset. The PWRT operates on an internal RC oscilla-
tor. The chip is kept in RESET as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE can
disable (if set) or enable (if cleared or programmed) the
PWRT. It is recommended that the PWRT be enabled
when Brown-out Reset is enabled.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-Up Timer will execute a
72 ms RESET. Figure ±4-7 shows typical Brown-out
situations.
FIGURE 14-7:
BROWN-OUT SITUATIONS WITH PWRT ENABLED
VDD
VBOR
≥ TBOR
INTERNAL
RESET
72 ms
VDD
VBOR
INTERNAL
RESET
<72 ms
72 ms
VDD
VBOR
INTERNAL
RESET
72 ms
Note: 72 ms delay only if PWRTE bit is programmed to ‘0’.
DS40044A-page 98
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
14.4.5
TIME OUT SEQUENCE
14.4.6
POWER CONTROL (PCON) STATUS
REGISTER
On power-up the time out sequence is as follows: First
PWRT time out is invoked after POR has expired. Then
OST is activated. The total time out will vary based on
oscillator configuration and PWRTE bit STATUS. For
example, in RC mode with PWRTE bit set (PWRT dis-
abled), there will be no time out at all. Figure ±4-8,
Figure ±4-9 and Figure ±4-±0 depict time out
sequences.
The power control/STATUS register, PCON (address
8Eh) has two bits.
Bit0 is BOR (Brown-out Reset). BOR is unknown on
Power-on-Reset. It must then be set by the user and
checked on subsequent RESETS to see if BOR = 0
indicating that a brown-out has occurred. The BOR
STATUS bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BOREN bit = 0 in the Configuration word).
Since the time outs occur from the POR pulse, if MCLR
is kept low long enough, the time outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure ±4-9). This is useful for testing purposes or
to synchronize more than one PIC±6F627A/628A/
648A device operating in parallel.
Bit± is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘±’ to this bit following a Power-on Reset. On a subse-
quent RESET if POR is ‘0’, it will indicate that a Power-
on Reset must have occurred (VDD may have gone too
low).
Table ±4-6 shows the RESET conditions for some spe-
cial registers, while Table ±4-7 shows the RESET con-
ditions for all the registers.
TABLE 14-3: TIME OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Reset
Wake-up
from SLEEP
Oscillator Configuration
PWRTEN = 0
PWRTEN = 1
PWRTEN = 0
PWRTEN = 1
XT, HS, LP
72 ms +
±024•TOSC
±024•TOSC
72 ms +
±024•TOSC
±024•TOSC
±024•TOSC
RC, EC
72 ms
72 ms
—
—
72 ms
72 ms
—
—
—
INTOSC
6 µs
TABLE 14-4: STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
1
PD
1
Condition
0
0
X
X
Power-on Reset
0
X
Illegal, TO is set on POR
0
1
1
1
X
0
1
1
X
X
0
0
0
X
u
0
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
1
1
1
1
u
1
u
0
MCLR Reset during normal operation
MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 99
PIC16F627A/628A/648A
TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET
Value on all
other
RESETS(1)
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Reset
03h, 83h, STATUS
103h, 183h
IRP
—
RP1
—
RPO
—
TO
—
PD
Z
DC
C
0001 1xxx 000q quuu
---- 1-0x ---- u-uq
8Eh
PCON
OSCF
—
POR
BOR
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by Brown-out Reset.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
TABLE 14-6: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Condition
Register
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
---- 1-0x
---- 1-uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
0001 0uuu
0000 uuuu
uuu0 0uuu
000x xuuu
uuu1 0uuu
---- 1-uu
---- 1-uu
---- u-uu
---- 1-u0
---- u-uu
WDT Wake-up
PC + 1
000h
Brown-out Reset
Interrupt Wake-up from SLEEP
PC + 1(1)
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
DS40044A-page 100
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 14-7: INITIALIZATION CONDITION FOR REGISTERS
•
MCLR Reset during normal
operation
•
•
Wake-up from SLEEP(7)
through interrupt
Wake-up from SLEEP(7)
Power-on
Reset
Register
Address
•
•
•
MCLR Reset during SLEEP
through WDT time out
WDT Reset
Brown-out Reset (1)
W
—
00h
xxxx xxxx
—
uuuu uuuu
—
uuuu uuuu
—
INDF
TMR0
PCL
01h, 101h
xxxx xxxx
0000 0000
uuuu uuuu
0000 0000
uuuu uuuu
PC + 1(3)
02h, 82h,
102h, 182h
STATUS
FSR
03h, 83h,
0001 1xxx
xxxx xxxx
000q quuu(4)
uuuu uuuu
uuuq 0uuu(4)
uuuu uuuu
103h, 183h
04h, 84h,
104h, 184h
PORTA
PORTB
PCLATH
05h
xxxx 0000
xxxx xxxx
---0 0000
xxxx 0000
uuuu uuuu
---0 0000
uuuu uuuu
uuuu uuuu
---u uuuu
06h, 106h
0Ah, 8Ah,
10Ah, 18Ah
INTCON
0Bh, 8Bh,
0000 000x
0000 000u
uuuu uqqq(2)
10Bh,18Bh
PIR1
0Ch
0Eh
0000 -000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
0000 -000
---- 1-0x
1111 1111
0000 -010
0000 0000
xxxx xxxx
xxxx xxxx
---- x000
—
0000 -000
uuuu uuuu
uuuu uuuu
--uu uuuu(6)
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
1111 1111
0000 -000
---- 1-uq(1,5)
1111 1111
0000 -010
0000 0000
uuuu uuuu
uuuu uuuu
---- q000
—
qqqq -qqq(2)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uu-- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
---- u-uu
uuuu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- uuuu
—
TMR1L
TMR1H
T1CON
TMR2
0Fh
10h
11h
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CMCON
OPTION
TRISA
12h
15h
16h
17h
18h
19h
1Ah
1Fh
81h,181h
85h
TRISB
86h, 186h
8Ch
8Eh
PIE1
PCON
PR2
92h
TXSTA
SPBRG
EEDATA
EEADR
EECON1
EECON2
VRCON
98h
99h
9Ah
9Bh
9Ch
9Dh
9Fh
000- 0000
000- 0000
uuu- uuuu
Legend: u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-6 for RESET value for specific condition.
5: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.
6: Reset to ‘--00 0000’ on a Brown-out Reset (BOR).
7: Peripherals generating interrupts for wake-up from SLEEP will change the resulting bits in the associated registers.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 101
PIC16F627A/628A/648A
FIGURE 14-8:
TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIME OUT
OST TIME OUT
Tost
INTERNAL RESET
FIGURE 14-9:
TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIME OUT
OST TIME OUT
Tost
INTERNAL RESET
FIGURE 14-10:
TIME OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIME OUT
OST TIME OUT
Tost
INTERNAL RESET
DS40044A-page 102
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 14-11:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
FIGURE 14-13:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
VDD
VDD
R1
Q1
D
MCLR
R
PIC16F627A/628A/648A
R2
R1
40k
PIC16F627A/628A/648A
MCLR
C
Note 1: This Brown-out Circuit is less expensive,
albeit less accurate. Transistor Q1 turns off
when VDD is below a certain level such that:
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
R1
VDD x
= 0.7 V
R1 + R2
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the device’s electrical specification.
2: Internal Brown-out Reset should be dis-
abled when using this circuit.
3: Resistors should be adjusted for the charac-
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
teristics of the transistor.
FIGURE 14-12:
EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
33k
10k
MCLR
40k
PIC16F627A/628A/648A
Note 1: This circuit will activate RESET when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Reset circuitry should
be disabled when using this circuit.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 103
PIC16F627A/628A/648A
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
14.5 Interrupts
The PIC±6F627A/628A/648A has ±0 sources of inter-
rupt:
• External Interrupt RB0/INT
• TMR0 Overflow Interrupt
• PORTB Change Interrupts (pins RB7:RB4)
• Comparator Interrupt
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure ±4-
±5). The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
• USART Interrupt TX
• USART Interrupt RX
• CCP Interrupt
• TMR± Overflow Interrupt
• TMR2 Match Interrupt
• Data EEPROM Interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
The “return from interrupt” instruction, RETFIE, exits
interrupt routine as well as sets the GIE bit, which re-
enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR±. The corresponding interrupt enable bit is
contained in special registers PIE±.
FIGURE 14-14:
INTERRUPT LOGIC
TMR1IF
TMR1IE
T0IF
T0IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
TMR2IF
TMR2IE
INTF
INTE
CCP1IF
CCP1IE
CMIF
RBIF
RBIE
CMIE
PEIE
TXIF
TXIE
RCIF
RCIE
GIE
EEIF
EEIE
DS40044A-page 104
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
14.5.1
RB0/INT INTERRUPT
14.5.3
PORTB INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<±>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before re-
enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section ±4.8
for details on SLEEP, and Figure ±4-±7 for timing of
wake-up from SLEEP through RB0/INT interrupt.
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
Note: If a change on the I/O pin should occur
when the read operation is being executed
(starts during the Q2 cycle and ends before
the start of the Q3 cycle), then the RBIF
interrupt flag may not get set.
14.5.4
COMPARATOR INTERRUPT
See Section ±0.6 for complete description of compara-
tor interrupts.
14.5.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
FIGURE 14-15:
INT PIN INTERRUPT TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1)
(5)
Interrupt Latency
INTF flag
(INTCON<1>)
(2)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
0004h
PC+1
PC+1
—
0005h
PC
Instruction
Fetched
Inst (PC)
Inst (PC+1)
Inst (0004h)
Inst (0005h)
Inst (0004h)
Instruction
Executed
Dummy Cycle
Dummy Cycle
Inst (PC)
Inst (PC-1)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available in RC and INTOSC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 105
PIC16F627A/628A/648A
TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS
Value on all
other
RESETS(1)
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Reset
0Bh, 8Bh, INTCON
10Bh, 18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
8Ch
PIR1
PIE1
EEIF
EEIE
CMIF
CMIE
RCIF
RCIE
TXIF
TXIE
—
—
CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal oper-
ation.
14.6 Context Saving During Interrupts
14.7 Watchdog Timer (WDT)
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (e.g., W register and STATUS
register). This must be implemented in software.
The watchdog timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC± and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
time out generates a device RESET. If the device is in
SLEEP mode, a WDT time out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section ±4.±).
Example ±4-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x±70 and 0x±F0). The Example ±4-2:
• Stores the W register
• Stores the STATUS register
• Executes the ISR code
14.7.1
WDT PERIOD
• Restores the STATUS (and bank select bit regis-
ter)
The WDT has a nominal time out period of ±8 ms (with
no prescaler). The time out periods vary with tempera-
• Restores the W register
DD
ture, V and process variations from part to part (see
DC Specifications, Table ±7-7). If longer time out peri-
ods are desired, a postscaler with a division ratio of up
to ±:±28 can be assigned to the WDT under software
control by writing to the OPTION register. Thus, time
out periods up to 2.3 seconds can be realized.
EXAMPLE 14-2:
SAVING THE STATUS
AND W REGISTERS IN
RAM
MOVWF W_TEMP
;copy W to temp register,
;could be in any bank
;swap status to be saved
;into W
SWAPF STATUS,W
The CLRWDTand SLEEPinstructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
BCF
STATUS,RP0 ;change to bank 0
;regardless of current
;bank
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
MOVWF STATUS_TEMP ;save status to bank 0
;register
:
14.7.2
WDT PROGRAMMING
CONSIDERATIONS
:(ISR)
:
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time out occurs.
SWAPFSTATUS_TEMP,W;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF STATUS
;move W into STATUS register
;swap W_TEMP
SWAPF W_TEMP,F
SWAPF W_TEMP,W
;swap W_TEMP into W
DS40044A-page 106
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 14-16:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
M
WDT POSTSCALER/
TMR0 PRESCALER
U
X
Watchdog
Timer
1
8
8 to 1 MUX
PS<2:0>
To TMR0
PSA
3
WDT
Enable Bit
(Figure 6-1)
0
1
PSA
MUX
WDT
Time out
Note:
T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 14-9: SUMMARY OF WATCHDOG TIMER REGISTERS
Value on all
other
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR Reset
RESETS
2007h
Config.
bits
LVP
BOREN MCLRE FOSC2 PWRTE
WDTE
PS2
FOSC1
PS1
FOSC0 uuuu uuuu uuuu uuuu
81h, 181h
OPTION
RBPU INTEDG
T0CS
T0SE
PSA
PS0
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Note: Shaded cells are not used by the Watchdog Timer.
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the com-
parators, and VREF should be disabled. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by float-
ing inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on chip pull-ups on PORTB should be considered.
14.8 Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEPwas executed (driving high, low, or hi-
impedance).
The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a RESET generated
by a WDT time out does not drive MCLR
pin low.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 107
PIC16F627A/628A/648A
ing interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEPinstruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOPafter the SLEEPinstruction.
14.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
±. External RESET input on MCLR pin
2. Watchdog Timer wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
any Peripheral Interrupt.
The first event will cause a device RESET. The two lat-
ter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT wake-up
occurred.
Note: If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will not
enter SLEEP. The SLEEP instruction is
executed as a NOPinstruction.
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
When the SLEEP instruction is being executed, the
next instruction (PC + ±) is pre-fetched. For the device
to wake-up through an interrupt event, the correspond-
FIGURE 14-17:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Tost(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Fetched
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
Instruction
Executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for RC Osc mode.
3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
in-line.
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
14.9 Code Protection
14.10 User ID Locations
With the Code Protect bit is cleared (Code Protect
enabled) the contents of the program memory locations
are read out as “00”. See Programing Specification,
DS4±±96, for details.
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store check-
sum or other code-identification numbers. These loca-
tions are not accessible during normal execution but
are readable and writable during program/verify. Only
the Least Significant 4 bits of the user ID locations are
used.
Note: Only a Bulk Erase function can set the CP
and CPD bits by turning off the code pro-
tection. The entire data EEPROM and
FLASH program memory will be erased to
turn the code protection off.
DS40044A-page 108
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
14.11 In-Circuit Serial Programming
14.12 Low Voltage Programming
The PIC±6F627A/628A/648A microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data,
and three other lines for power, ground, and the pro-
gramming voltage. This allows customers to manufac-
ture boards with unprogrammed devices and then
program the microcontroller just before shipping the
product. This also allows the most recent firmware, or
a custom firmware to be programmed.
The LVP bit of the configuration word, enables the low
voltage programming. This mode allows the microcon-
troller to be programmed via ICSP using only a 5V
source. This mode removes the requirement of VIHH to
be placed on the MCLR pin. The LVP bit is normally
erased to '±' which enables the low voltage program-
ming. In this mode, the RB4/PGM pin is dedicated to
the programming function and ceases to be a general
purpose I/O pin. The device will enter Programming
mode when a '±' is placed on the RB4/PGM pin. The
HV Programming mode is still available by placing VIHH
on the MCLR pin.
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
Note 1: While in this mode the RB4 pin can no
longer be used as a general purpose I/O
pin.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, ±4 bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the Pro-
gramming Specifications (DS4±±96).
2: VDD must be 5.0V +±01 during erase
operations.
If Low-voltage Programming mode is not used, the LVP
bit should be programmed to a '0' so that RB4/PGM
becomes a digital I/O pin. To program the device, VIHH
must be placed onto MCLR during programming. The
LVP bit may only be programmed when programming
is entered with VIHH on MCLR. The LVP bit cannot be
programmed when programming is entered with RB4/
PGM.
A typical In-Circuit Serial Programming connection is
shown in Figure ±4-±8.
It should be noted, that once the LVP bit is programmed
to 0, only high voltage Programming mode can be used
to program the device.
FIGURE 14-18:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
External
Connector
Signals
PIC16F627A/628A/648A
+5V
0V
VDD
VSS
VPP
RA5/MCLR/VPP
RB6/PGC
RB7/PGD
CLK
Data I/O
VDD
To Normal
Connections
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 109
PIC16F627A/628A/648A
NOTES:
DS40044A-page 110
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The instruction set is highly orthogonal and is grouped
into three basic categories:
15.0 INSTRUCTION SET SUMMARY
Each PIC±6F627A/628A/648A instruction is a ±4-bit
word divided into an OPCODE which specifies the
instruction type and one or more operands which fur-
ther specify the operation of the instruction. The
PIC±6F627A/628A/648A instruction set summary in
Table ±5-2 lists byte-oriented, bit-oriented, and lit-
eral and control operations. Table ±5-± shows the
opcode field descriptions.
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
normal instruction execution time is ± µs. If
a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
Table ±5-2 lists the instructions recognized by the
MPASM™ assembler.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
Figure ±5-± shows the three general formats that the
instructions can have.
Note 1: Any unused opcode is reserved. Use of
any reserved opcode may cause unex-
pected operation.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
2: To maintain upward compatibility with
future PICmicro products, do not use the
OPTIONand TRISinstructions.
TABLE 15-1: OPCODE FIELD
DESCRIPTIONS
Field
Description
All examples use the following format to represent a
hexadecimal number:
f
Register file address (0x00 to 0x7F)
Working register (accumulator)
W
b
0xhh
Bit address within an 8-bit file register
Literal field, constant data or label
where h signifies a hexadecimal digit.
k
x
Don't care location (= 0 or 1)
FIGURE 15-1:
GENERAL FORMAT FOR
INSTRUCTIONS
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
Byte-oriented file register operations
13
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
8
7
6
0
OPCODE
d
f (FILE #)
label
TOS
PC
Label name
d = 0 for destination W
d = 1 for destination f
Top of Stack
f = 7-bit file register address
Program Counter
PCLATH Program Counter High Latch
Bit-oriented file register operations
13 10 9
b (BIT #)
7 6
0
GIE
WDT
TO
Global Interrupt Enable bit
Watchdog Timer/Counter
Time out bit
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
PD
Power-down bit
dest
Destination either the W register or the specified regis-
ter file location
Literal and control operations
General
13
[ ]
Options
8 7
0
0
( )
→
Contents
OPCODE
k (literal)
Assigned to
k = 8-bit immediate value
< >
∈
Register bit field
In the set of
CALLand GOTOinstructions only
13
11 10
italics
User defined term (font is courier)
OPCODE
k (literal)
k = 11-bit immediate value
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 111
PIC16F627A/628A/648A
TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Status
Description
Cycles
Notes
Operands
Affected
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
f, d
f, d
f
Add W and f
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
AND W with f
0101 dfff ffff
0001 lfff ffff
0001 0000 0011
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
Clear f
1
CLRW
COMF
DECF
—
Clear W
1
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
Complement f
1
1,2
1,2
Decrement f
1
1(2)
DECFSZ
INCF
Decrement f, Skip if 0
Increment f
1,2,3
1,2
1
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
Increment f, Skip if 0
Inclusive OR W with f
Move f
1(2)
1
1,2,3
1,2
Z
Z
1
1,2
Move W to f
1
—
No Operation
1
RLF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
C
C
1,2
1,2
1,2
1,2
1,2
RRF
1
SUBWF
SWAPF
XORWF
1
0010 dfff ffff C,DC,Z
1
1110 dfff ffff
1
0110 dfff ffff Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
f, b
f, b
f, b
Bit Clear f
1
01
01
01
01
00bb bfff ffff
01bb bfff ffff
10bb bfff ffff
11bb bfff ffff
1,2
1,2
3
BSF
Bit Set f
1
BTFSC
BTFSS
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1(2)
1(2)
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
k
Add literal and W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x kkkk kkkk C,DC,Z
AND literal with W
1001 kkkk kkkk
0kkk kkkk kkkk
Z
k
Call subroutine
CLRWDT
GOTO
—
k
Clear Watchdog Timer
Go to address
0000 0110 0100 TO,PD
1kkk kkkk kkkk
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
Inclusive OR literal with W
Move literal to W
1000 kkkk kkkk
00xx kkkk kkkk
0000 0000 1001
01xx kkkk kkkk
0000 0000 1000
Z
k
—
k
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
—
—
k
0000 0110 0011 TO,PD
110x kkkk kkkk C,DC,Z
k
1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data
will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.
DS40044A-page 112
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15.1 Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[ label ] ADDLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] ANDLW
0 ≤ k ≤ 255
k
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) + k → (W)
C, DC, Z
(W) .AND. (k) → (W)
Z
11
111x
kkkk
kkkk
11
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and
the result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'.
The result is placed in the W regis-
ter.
Words:
Cycles:
Example
±
±
Words:
Cycles:
Example
±
±
ADDLW
0x15
ANDLW
0x5F
Before Instruction
W = 0x±0
Before Instruction
W = 0xA3
After Instruction
W = 0x25
After Instruction
W = 0x03
ANDWF
AND W with f
ADDWF
Add W and f
Syntax:
[ label ] ANDWF f,d
Syntax:
[ label ] ADDWF f,d
Operands:
0 ≤ f ≤ ±27
d ∈ [0,1]
Operands:
0 ≤ f ≤ ±27
d ∈ [0,1]
Operation:
(W) .AND. (f) → (dest)
Operation:
(W) + (f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
C, DC, Z
00
0101
dfff
ffff
00
0111
dfff
ffff
Description:
AND the W register with register 'f'.
If 'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Cycles:
Example
±
±
Words:
Cycles:
Example
±
±
ANDWF
REG1, 1
ADDWF
REG1, 0
Before Instruction
Before Instruction
W = 0x±7
REG± = 0xC2
W = 0x±7
REG± = 0xC2
After Instruction
= 0x±7
REG± = 0x02
After Instruction
= 0xD9
REG± = 0xC2
W
W
Z
= 0
= 0
= 0
C
DC
2002 Microchip Technology Inc.
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BCF
Bit Clear f
BTFSC
Bit Test f, Skip if Clear
Syntax:
[ label ] BCF f,b
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ ±27
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ ±27
0 ≤ b ≤ 7
Operation:
Status Affected:
Encoding:
Description:
Words:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
None
None
Status Affected:
Encoding:
01
00bb
bfff
ffff
01
10bb
bfff
ffff
Bit 'b' in register 'f' is cleared.
Description:
If bit 'b' in register 'f' is '0' then the
next instruction is skipped.
±
±
If bit 'b' is '0' then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a two-
cycle instruction.
Cycles:
BCF
Before Instruction
REG± = 0xC7
After Instruction
REG± = 0x47
REG1, 7
Example
Words:
Cycles:
Example
±
±(2)
HERE
FALSE
TRUE
BTFSC
REG1
GOTO
PROCESS_CODE
BSF
Bit Set f
•
•
•
Syntax:
[ label ] BSF f,b
Operands:
0 ≤ f ≤ ±27
0 ≤ b ≤ 7
Before Instruction
PC = address HERE
After Instruction
if REG<±> = 0,
Operation:
Status Affected:
Encoding:
Description:
Words:
± → (f<b>)
None
PC = address TRUE
if REG<±>=±,
PC = address FALSE
01
01bb
bfff
ffff
Bit 'b' in register 'f' is set.
±
±
Cycles:
BSF
Before Instruction
REG± = 0x0A
After Instruction
REG± = 0x8A
REG1, 7
Example
DS40044A-page 114
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BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL
0 ≤ k ≤ 2047
k
Operands:
0 ≤ f ≤ ±27
0 ≤ b < 7
Operands:
Operation:
(PC)+ ±→ TOS,
k → PC<±0:0>,
(PCLATH<4:3>) → PC<±2:±±>
Operation:
skip if (f<b>) = ±
None
Status Affected:
Encoding:
Status Affected:
Encoding:
None
01
11bb
bfff
ffff
10
0kkk
kkkk
kkkk
Description:
If bit 'b' in register 'f' is '±' then the
next instruction is skipped.
If bit 'b' is '±', then the next instruc-
tion fetched during the current
instruction execution, is discarded
and a NOPis executed instead,
making this a two-cycle instruc-
tion.
Description:
Call Subroutine. First, return
address (PC+±) is pushed onto
the stack. The eleven bit imme-
diate address is loaded into PC
bits <±0:0>. The upper bits of
the PC are loaded from
PCLATH. CALLis a two-cycle
instruction.
Words:
Cycles:
Example
±
Words:
Cycles:
Example
±
2
±(2)
HERE
FALSE
TRUE
BTFSS
REG1
GOTO
PROCESS_CODE
HERE
Before Instruction
PC Address HERE
After Instruction
PC Address THERE
TOS = Address HERE+1
CALL
THERE
•
•
•
=
Before Instruction
PC = address HERE
After Instruction
=
if FLAG<±> = 0,
PC = address FALSE
CLRF
Clear f
if FLAG<±> = ±,
PC = address TRUE
Syntax:
[ label ] CLRF
0 ≤ f ≤ ±27
f
Operands:
Operation:
00h → (f)
± → Z
Status Affected:
Encoding:
Z
00
0001
1fff
ffff
Description:
The contents of register 'f' are
cleared and the Z bit is set.
Words:
Cycles:
Example
±
±
CLRF
Before Instruction
REG±
After Instruction
REG1
=
0x5A
REG±
Z
=
0x00
±
=
2002 Microchip Technology Inc.
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CLRW
Clear W
COMF
Complement f
Syntax:
[ label ] CLRW
Syntax:
[ label ] COMF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
00h → (W)
± → Z
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0001
0000
0011
00
1001
dfff
ffff
Description:
W register is cleared. Zero bit
(Z) is set.
Description:
The contents of register 'f' are
complemented. If 'd' is 0 the
result is stored in W. If 'd' is ± the
result is stored back in register
'f'.
Words:
Cycles:
Example
±
±
CLRW
Words:
Cycles:
Example
±
±
Before Instruction
W = 0x5A
COMF
Before Instruction
REG± = 0x±3
After Instruction
REG± = 0x±3
REG1, 0
After Instruction
W = 0x00
Z
= ±
W
= 0xEC
CLRWDT
Clear Watchdog Timer
DECF
Decrement f
Syntax:
[ label ] CLRWDT
Syntax:
[ label ] DECF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
00h → WDT
0 → WDT prescaler,
± → TO
Operation:
(f) - ± → (dest)
Status Affected:
Encoding:
Z
± → PD
00
0011
dfff
ffff
Status Affected:
Encoding:
TO, PD
Description:
Decrement register 'f'. If 'd' is 0
the result is stored in the W reg-
ister. If 'd' is ± the result is stored
back in register 'f'.
00
0000
0110
0100
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
Words:
Cycles:
Example
±
±
Words:
Cycles:
Example
±
DECF
Before Instruction
CNT = 0x0±
= 0
After Instruction
CNT = 0x00
= ±
CNT, 1
±
CLRWDT
Before Instruction
WDT counter = ?
After Instruction
Z
WDT counter = 0x00
WDT prescaler = 0
Z
TO
PD
= ±
= ±
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DECFSZ
Syntax:
Decrement f, Skip if 0
GOTO
Unconditional Branch
[ label ] DECFSZ f,d
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operands:
Operation:
k → PC<±0:0>
PCLATH<4:3> → PC<±2:±±>
Operation:
(f) - ± → (dest); skip if result =
0
Status Affected:
Encoding:
None
Status Affected:
Encoding:
None
10
1kkk
kkkk
kkkk
00
1011
dfff
ffff
Description:
GOTOis an unconditional
Description:
The contents of register 'f' are
decremented. If 'd' is 0 the result
is placed in the W register. If 'd'
is ± the result is placed back in
register 'f'.
branch. The eleven-bit immedi-
ate value is loaded into PC bits
<±0:0>. The upper bits of PC
are loaded from PCLATH<4:3>.
GOTOis a two-cycle instruction.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOPis executed
instead making it a two-cycle
instruction.
Words:
Cycles:
Example
±
2
GOTO THERE
After Instruction
Words:
Cycles:
Example
±
PC = Address THERE
±(2)
HERE
DECFSZ
GOTO
REG1, 1
LOOP
CONTINUE •
•
•
Before Instruction
PC
After Instruction
REG± = REG± - ±
= address HERE
if REG± = 0,
PC = address CONTINUE
if REG± ≠ 0,
PC
= address HERE+1
2002 Microchip Technology Inc.
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INCF
Increment f
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] INCF f,d
Syntax:
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operation:
(f) + ± → (dest)
Operation:
(f) + ± → (dest), skip if result = 0
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
None
00
1010
dfff
ffff
00
1111
dfff
ffff
Description:
The contents of register 'f' are
incremented. If 'd' is 0 the result
is placed in the W register. If 'd'
is ± the result is placed back in
register 'f'.
Description:
The contents of register 'f' are
incremented. If 'd' is 0 the result
is placed in the W register. If 'd'
is ± the result is placed back in
register 'f'.
If the result is 0, the next instruc-
tion, which is already fetched, is
discarded. A NOPis executed
instead making it a two-cycle
instruction.
Words:
Cycles:
Example
±
±
INCF
Before Instruction
REG± = 0xFF
REG1, 1
Words:
Cycles:
Example
±
Z
= 0
±(2)
After Instruction
REG± = 0x00
HERE
INCFSZ
GOTO
REG1, 1
LOOP
Z
= ±
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
REG± = REG± + ±
if CNT = 0,
PC = address CONTINUE
if REG±≠ 0,
PC
= address HERE +1
DS40044A-page 118
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IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Syntax:
[ label ] MOVLW k
0 ≤ k ≤ 255
k → (W)
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) .OR. k → (W)
Z
None
11
1000
kkkk
kkkk
11
00xx
kkkk
kkkk
Description:
The contents of the W register is
OR’ed with the eight bit literal 'k'.
The result is placed in the W
register.
Description:
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
Words:
Cycles:
Example
±
±
Words:
Cycles:
Example
±
±
MOVLW
0x5A
IORLW
0x35
After Instruction
W = 0x5A
Before Instruction
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF
Inclusive OR W with f
MOVF
Move f
Syntax:
[ label ] IORWF f,d
Syntax:
[ label ] MOVF f,d
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operation:
(W) .OR. (f) → (dest)
Operation:
(f) → (dest)
Status Affected:
Encoding:
Z
Status Affected:
Encoding:
Z
00
0100
dfff
ffff
00
1000
dfff
ffff
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is
± the result is placed back in
register 'f'.
Description:
The contents of register f is
moved to a destination depen-
dent upon the status of d. If d =
0, destination is W register. If d
= ±, the destination is file regis-
ter f itself. d = ± is useful to test
a file register since status flag Z
is affected.
Words:
Cycles:
Example
±
±
IORWF
REG1, 0
Words:
Cycles:
Example
±
±
Before Instruction
REG± = 0x±3
MOVF
After Instruction
W= value in REG± register
Z =
REG1, 0
W
= 0x9±
After Instruction
REG± = 0x±3
W
Z
= 0x93
= ±
±
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MOVWF
Move W to f
OPTION
Load Option Register
Syntax:
[ label ] OPTION
None
Syntax:
[ label ] MOVWF
0 ≤ f ≤ ±27
(W) → (f)
f
Operands:
Operation:
Status Affected:
Encoding:
Operands:
Operation:
Status Affected:
Encoding:
(W) → OPTION
None
None
00
0000
0110
0010
00
0000
1fff
ffff
Description:
The contents of the W register are
loaded in the OPTION register.
This instruction is supported for
code compatibility with PIC±6C5X
products. Since OPTION is a
readable/writable register, the
user can directly address it. Using
only register instruction such as
MOVWF.
Description:
Move data from W register to regis-
ter 'f'.
Words:
Cycles:
Example
±
±
MOVWF
REG1
Before Instruction
REG± = 0xFF
W
= 0x4F
Words:
Cycles:
Example
±
±
After Instruction
REG± = 0x4F
W
= 0x4F
To maintain upward compatibil-
®
ity with future PICmicro prod-
ucts, do not use this
instruction.
RETFIE
Return from Interrupt
NOP
No Operation
Syntax:
[ label ] RETFIE
Syntax:
[ label ] NOP
None
Operands:
Operation:
None
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
TOS → PC,
± → GIE
No operation
None
Status Affected:
Encoding:
None
00
0000
0xx0
0000
00
0000
0000
1001
No operation.
Description:
Return from Interrupt. Stack is
POPed and Top of Stack (TOS)
is loaded in the PC. Interrupts
are enabled by setting Global
Interrupt Enable bit, GIE
±
Cycles:
±
NOP
Example
(INTCON<7>). This is a two-
cycle instruction.
Words:
Cycles:
Example
±
2
RETFIE
After Interrupt
PC = TOS
GIE =
±
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RETLW
Return with Literal in W
RLF
Rotate Left f through Carry
Syntax:
[ label ] RETLW
0 ≤ k ≤ 255
k
Syntax:
[ label ] RLF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected:
Encoding:
None
Status Affected:
Encoding:
11
01xx
kkkk
kkkk
00
1101
dfff
ffff
Description:
The W register is loaded with
the eight bit literal 'k'. The pro-
gram counter is loaded from the
top of the stack (the return
address). This is a two-cycle
instruction.
Description:
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result
is placed in the W register. If 'd' is
± the result is stored back in reg-
ister 'f'.
C
REGISTER F
Words:
Cycles:
Example
±
2
Words:
Cycles:
Example
±
CALL TABLE;W contains table
;offset value
±
•
•
•
;W now has table value
RLF
REG1, 0
Before Instruction
REG1=1110 0110
TABLE
ADDWF PC;W = offset
C
= 0
After Instruction
REG1=1110 0110
RETLW k1;Begin table
RETLW k2;
•
•
W
C
= 1100 1100
= 1
•
RETLW kn; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN
None
Operands:
Operation:
Status Affected:
Encoding:
TOS → PC
None
00
0000
0000
1000
Description:
Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
two-cycle instruction.
Words:
Cycles:
Example
±
2
RETURN
After Interrupt
PC = TOS
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RRF
Rotate Right f through Carry
SUBLW
Subtract W from Literal
Syntax:
[ label ] RRF f,d
Syntax:
[ label ]
SUBLW
k
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operands:
Operation:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
See description below
C
Status
Affected:
C, DC, Z
Status Affected:
Encoding:
00
1100
dfff
ffff
11
110x
kkkk
kkkk
Encoding:
Description:
The contents of register 'f' are
rotated one bit to the right
Description:
The W register is subtracted (2’s
complement method) from the eight
bit literal 'k'. The result is placed in
the W register.
through the Carry Flag. If 'd' is 0
the result is placed in the W reg-
ister. If 'd' is ± the result is
Words:
±
±
placed back in register 'f'.
Cycles:
C
REGISTER F
SUBLW
0x02
Example ±:
Before Instruction
W = ±
Words:
Cycles:
Example
±
±
C
= ?
RRF
REG1, 0
After Instruction
W = ±
Before Instruction
REG± = 1110 0110
= 0
After Instruction
REG± = 1110 0110
C
= ±; result is positive
C
Example 2:
Before Instruction
W =
C =
2
?
W
C
= 0111 0011
= 0
After Instruction
W =
C = ±; result is zero
Before Instruction
W =
C =
0
SLEEP
Example 3:
Syntax:
[ label ] SLEEP
3
Operands:
Operation:
None
?
00h → WDT,
0 → WDT prescaler,
± → TO,
After Instruction
W = 0xFF
0 → PD
C = 0; result is negative
Status Affected:
Encoding:
TO, PD
00
0000
0110
0011
Description:
The power-down STATUS bit,
PD is cleared. Time out STA-
TUS bit, TO is set. Watchdog
Timer and its prescaler are
cleared.
The processor is put into
SLEEP mode with the oscilla-
tor stopped. See Section ±4.8
for more details.
Words:
±
Cycles:
Example:
±
SLEEP
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SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
SUBWF f,d
Syntax:
[ label ]
SWAPF f,d
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
Operation:
(f) - (W) → (dest)
Operation:
(f<3:0>) → (dest<7:4>),
(f<7:4>) → (dest<3:0>)
Status
Affected:
C, DC, Z
Status Affected:
Encoding:
None
00
0010
dfff
ffff
00
1110
dfff
ffff
Encoding:
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0
the result is stored in the W register.
If 'd' is ± the result is stored back in
register 'f'.
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0 the result is placed in W regis-
ter. If 'd' is ± the result is placed in
register 'f'.
Words:
±
±
Words:
Cycles:
Example
±
±
Cycles:
SUBWF
REG1, 1
SWAPF
Before Instruction
REG± = 0xA5
After Instruction
REG± = 0xA5
0x5A
REG1, 0
Example ±:
Before Instruction
REG± = 3
W
C
= 2
= ?
After Instruction
REG± = ±
W
=
W
C
Z
= 2
= ±; result is positive
= DC = ±
TRIS
Load TRIS Register
Syntax:
[ label ] TRIS
5 ≤ f ≤ 7
f
Example 2:
Before Instruction
REG± = 2
Operands:
Operation:
Status Affected:
Encoding:
Description:
(W) → TRIS register f;
W
C
= 2
= ?
None
00
0000
0110
0fff
After Instruction
REG± = 0
The instruction is supported for
code compatibility with the
PIC±6C5X products. Since TRIS
registers are readable and writ-
able, the user can directly
address them.
W
C
Z
= 2
= ±; result is zero
= DC = ±
Example 3:
Before Instruction
Words:
Cycles:
Example
±
±
REG± = ±
W
C
= 2
= ?
After Instruction
REG± = 0xFF
To maintain upward compatibil-
®
ity with future PICmicro prod-
ucts, do not use this
instruction.
W
C
Z
= 2
= 0; result is negative
= DC = 0
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 123
PIC16F627A/628A/648A
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[ label ] XORLW k
0 ≤ k ≤ 255
Syntax:
[ label ]
XORWF f,d
Operands:
Operation:
Status Affected:
Encoding:
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
(W) .XOR. k → (W)
Z
Operation:
(W) .XOR. (f) → (dest)
Status Affected:
Encoding:
Z
11
1010
kkkk
kkkk
00
0110
dfff
ffff
Description:
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
Description:
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0 the result is stored in the W reg-
ister. If 'd' is ± the result is stored
back in register 'f'.
Words:
±
Cycles:
Example:
±
Words:
Cycles:
Example
±
±
XORLW 0xAF
Before Instruction
W = 0xB5
XORWF
Before Instruction
REG± = 0xAF
0xB5
REG1, 1
After Instruction
W = 0x±A
W
=
After Instruction
REG± = 0x±A
0xB5
W
=
DS40044A-page 124
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
The MPLAB IDE allows you to:
16.0 DEVELOPMENT SUPPORT
• Edit your source files (either assembly or ‘C’)
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (auto-
matically updates all project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- absolute listing file
- machine code
- MPLAB C±7 and MPLAB C±8 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the cost-
effective simulator to a full-featured emulator with
minimal retraining.
• Simulators
- MPLAB SIM Software Simulator
• Emulators
16.2 MPASM Assembler
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
- MPLAB ICD
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assem-
bler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an abso-
lute LST file that contains source lines and generated
machine code, and a COD file for debugging.
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM ± Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM ±7 Demonstration Board
- KEELOQ® Demonstration Board
The MPASM assembler features include:
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
16.1 MPLAB Integrated Development
Environment Software
• Conditional assembly for multi-purpose source
files.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. The MPLAB IDE is a Windows®-based
application that contains:
• Directives that allow complete control over the
assembly process.
16.3 MPLAB C17 and MPLAB C18
C Compilers
• An interface to debugging tools
- simulator
The MPLAB C±7 and MPLAB C±8 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC±7CXXX and PIC±8CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
• Customizable toolbar and key mapping
• A status bar
• On-line help
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 125
PIC16F627A/628A/648A
16.4 MPLINK Object Linker/
MPLIB Object Librarian
16.6 MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C±7 and MPLAB C±8 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLIB object librarian is a librarian for pre-
compiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLAB ICE 2000 is a full-featured emulator sys-
tem with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of differ-
ent processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C±7 and MPLAB C±8 C compilers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
16.7 ICEPIC In-Circuit Emulator
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC±6C5X, PIC±6C6X,
PIC±6C7X and PIC±6CXXX families of 8-bit One-
Time-Programmable (OTP) microcontrollers. The mod-
ular system can support different subsets of PIC±6C5X
or PIC±6CXXX products through the use of inter-
changeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
16.5 MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code devel-
opment in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic debug-
ging using the MPLAB C±7 and the MPLAB C±8 C com-
pilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multi-
project software development tool.
DS40044A-page 126
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
16.8 MPLAB ICD In-Circuit Debugger
16.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
Microchip's In-Circuit Debugger, MPLAB ICD, is a pow-
erful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capa-
bility built into the FLASH devices. This feature, along
with Microchip's In-Circuit Serial ProgrammingTM proto-
col, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watch-
ing variables, single-stepping and setting break points.
Running at full speed enables testing hardware in real-
time.
The PICDEM ± demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers sup-
ported are: PIC±6C5X (PIC±6C54 to PIC±6C58A),
PIC±6C6±, PIC±6C62X, PIC±6C7±, PIC±6C8X,
PIC±7C42, PIC±7C43 and PIC±7C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcon-
trollers provided with the PICDEM ± demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM ± demonstration board to the MPLAB ICE in-
circuit emulator and download the firmware to the emu-
lator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simu-
lated analog input, push button switches and eight
LEDs connected to PORTB.
16.9 PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
Stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has program-
mable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for max-
imum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In Stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
16.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple dem-
onstration board that supports the PIC±6C62,
PIC±6C64, PIC±6C65, PIC±6C73 and PIC±6C74
microcontrollers. All the necessary hardware and soft-
ware is included to run the basic demonstration pro-
grams. The user can program the sample
microcontrollers provided with the PICDEM 2 demon-
stration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
16.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It con-
nects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
2
serial EEPROM to demonstrate usage of the I CTM bus
The PICSTART Plus development programmer sup-
ports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC±6C92X and
PIC±7C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
and separate headers for connection to an LCD
module and a keypad.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 127
PIC16F627A/628A/648A
16.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
16.14 PICDEM 17 Demonstration Board
The PICDEM ±7 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC±7C752,
PIC±7C756A, PIC±7C762 and PIC±7C766. All neces-
sary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM ±7 dem-
onstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM ±7 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Addition-
ally, a generous prototype area is available for user
hardware.
The PICDEM 3 demonstration board is a simple dem-
onstration board that supports the PIC±6C923 and
PIC±6C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Mod-
ule. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers pro-
vided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emula-
tor may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been pro-
vided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and ±2 segments, that is capable of display-
ing time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
16.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS eval-
uation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a pro-
gramming interface to program test transmitters.
DS40044A-page 128
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP
M C P 2 5 1 0
M C R F X X X
S X X H X C
9 3 C X X
2 5 C X X /
2 4 C X X /
P I C 1 8 F X X X
P I C 1 8 C X X 2
P I C 1 7 C 7 X X
P I C 1 7 C 4 X
P I C 1 6 C 9 X X
P I C 1 6 F 8 X X
P I C 1 6 C 8 X
P I C 1 6 C 7 X X
P I C 1 6 C 7 X
P I C 1 6 F 6 2 X
P I C 1 6 C X X X
P I C 1 6 C 6 X
P I C 1 6 C 5 X
P I C 1 4 0 0 0
P I C 1 2 C X X X
S o E
P
D e m o B o a r d s a n d E v a l K i t s
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 129
PIC16F627A/628A/648A
NOTES:
DS40044A-page 130
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Ambient temperature under bias.................................................................................................................-40 to +±25°C
Storage temperature .............................................................................................................................. -65°C to +±50°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +±4V
Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V
(1)
Total power dissipation .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)............................................................................................................... 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB (Combined)................................................................................200 mA
Maximum current sourced by PORTA and PORTB (Combined)...........................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-±00 Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 131
PIC16F627A/628A/648A
FIGURE 17-1:
PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
VDD
(VOLTS)
0
4
±0
20
25
FREQUENCY (MHz)
Note: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2:
6.0
PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
2.0
20
0
4
±0
25
FREQUENCY (MHz)
Note: The shaded region indicates the permissible combinations of voltage and frequency.
DS40044A-page 132
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
17.1 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
PIC16LF627A/628A/648A
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial
(Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC16F627A/628A/648A
Operating temperature
-40°C ≤ Ta ≤ +85°C for industrial and
-40°C ≤ Ta ≤ +125°C for extended
(Industrial, Extended)
Param
Sym
Characteristic/Device
Min
Typ†
Max
Units
Conditions
No.
VDD
Supply Voltage
PIC16LF627A/628A/648A
PIC16F627A/628A/648A
RAM Data Retention
Voltage(1)
D001
2.0
3.0
—
—
—
5.5
5.5
—
V
V
V
D002
D003
D004
D005
VDR
1.5*
Device in SLEEP mode
VPOR VDD Start Voltage
to ensure Power-on Reset
SVDD VDD Rise Rate
to ensure Power-on Reset
VBOR Brown-out Reset Voltage
—
VSS
—
—
V
See Section 14.4 on Power-on
Reset for details
0.05*
—
V/ms
See Section 14.4 on Power-on
Reset for details
3.65
3.65
4.0
4.0
4.35
4.4
V
V
BOREN configuration bit is set
BOREN configuration bit is set,
Extended
Legend: Rows with standard voltage device data only are shaded for improved readability.
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0 V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 133
PIC16F627A/628A/648A
17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial)
PIC16LF627A/628A/648A (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ Ta ≤ +85°C for industrial
Conditions
Param
No.
LF and F Device
Characteristics
Min†
Typ
Max
Units
VDD
Note
Supply Voltage (VDD)
2.0
3.0
—
—
5.5
5.5
V
V
—
—
LF
D001
LF/F
Power-down Base Current (IPD)
—
—
—
0.1
0.1
0.2
0.80
0.85
0.95
µA
µA
µA
2.0
3.0
5.0
WDT, BOR, Comparators, VREF, and
LF
T1OSC: disabled
D020
LF/F
Peripheral Module Current (∆IMOD)(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2.0
3.4
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
2.0
3.0
5.0
4.5
5.0
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
WDT Current
LF
D021
2
LF/F
9
12.5
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
2.0
32
33
15
27
49
34
50
80
1.2
1.3
1.8
BOR Current
D022
D023
LF/F
LF
Comparator Current
LF/F
LF
VREF Current
D024
LF/F
LF
T1OSC Current
D025
2.2
LF/F
2.9
Supply Current (IDD)
—
—
—
—
—
—
—
—
—
—
—
12
21
15
25
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
2.0
3.0
5.0
2.0
3.0
5.0
2.0
3.0
5.0
4.5
5.0
FOSC = 32 kHz
LF
LF/F
LF
LP Oscillator Mode
D010
38
48
120
180
290
240
370
670
2.6
3
160
250
370
300
470
780
2.9
3.3
FOSC = 1 MHz
XT Oscillator Mode
D011
LF/F
LF
FOSC = 4 MHz
XT Oscillator Mode
D012
D013
LF/F
FOSC = 20 MHz
LF/F
HS Oscillator Mode
Note 1: The “∆“ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement. Max values should be used when calculating total current consumption.
DS40044A-page 134
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
17.3
DC Characteristics: PIC16F627A/628A/648A (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ Ta ≤ +125°C for extended
Conditions
Param
No.
Device Characteristics
Min†
Typ
Max
Units
VDD
Note
Supply Voltage (VDD)
D001
—
3.0
—
5.5
V
—
Power-down Base Current (IPD)
D020E
Peripheral Module Current (∆IMOD)(1)
—
—
0.1
0.2
TBD
TBD
µA
µA
3.0
5.0
WDT, BOR, Comparators, VREF, and
T1OSC: disabled
—
—
—
—
—
—
—
—
—
—
—
2
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
3.0
5.0
4.5
5.0
3.0
5.0
3.0
5.0
3.0
5.0
WDT Current
D021E
D022E
D023E
D024E
—
—
—
—
—
9
32
33
27
49
50
83
1.3
1.8
BOR Current
Comparator Current
VREF Current
T1OSC Current
D025E
Supply Current (IDD)
D010E
—
—
—
—
—
—
—
—
21
38
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
µA
µA
µA
µA
µA
µA
mA
mA
3.0
5.0
3.0
5.0
3.0
5.0
4.5
5.0
FOSC = 32 kHz
—
—
—
—
LP Oscillator Mode
182
293
371
668
2.6
3
FOSC = 1 MHz
D011E
D012E
D013E
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 20 MHz
HS Oscillator Mode
Note 1: The “∆“ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement. Max values should be used when calculating total current consumption.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 135
PIC16F627A/628A/648A
17.4 DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial and
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3
Param.
Sym
Characteristic/Device
Min
Typ†
Max
Unit
Conditions
No.
VIL
Input Low Voltage
I/O ports
D030
with TTL buffer
VSS
VSS
VSS
VSS
—
—
—
—
0.8
V
V
V
V
VDD = 4.5V to 5.5V
0.15 VDD
0.2 VDD
0.2 VDD
otherwise
D031
D032
with Schmitt Trigger input(4)
MCLR, RA4/T0CKI,OSC1
(in RC mode)
(Note1)
D033
OSC1 (in HS)
VSS
VSS
—
—
0.3 VDD
V
V
OSC1 (in LP and XT)
0.8
VIH
Input High Voltage
I/O ports
D040
with TTL buffer
2.0 V
.25 VDD + 0.8 V
0.8 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
VDD = 4.5V to 5.5V
otherwise
D041
D042
D043
D043A
with Schmitt Trigger input(4)
MCLR RA4/T0CKI
0.8 VDD
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
0.7 VDD
0.9 VDD
(Note1)
D070
IPURB
PORTB weak pull-up
current
50
200
400
µA VDD = 5.0V, VPIN = VSS
IIL
Input Leakage Current(2), (3)
I/O ports (Except PORTA)
PORTA(4)
—
—
—
—
—
—
—
—
1.0
0.5
1.0
5.0
µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
µA VSS ≤ VPIN ≤ VDD
D060
D061
D063
RA4/T0CKI
OSC1, MCLR
µA VSS ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL
Output Low Voltage
—
—
—
—
0.6
0.6
V
V
IOL=8.5 mA, VDD=4.5 V, -40° to +85°C
IOL=7.0 mA, VDD=4.5 V, +85° to +125°C
D080
D090
I/O ports(4)
VOH
Output High Voltage(3)
I/O ports (Except RA4(4)
VDD-0.7
—
—
—
—
V
V
IOH=-3.0 mA, VDD=4.5 V, -40° to +85°C
IOH=-2.5 mA, VDD=4.5 V, +85° to
+125°C
VDD-0.7
D150
VOD
Open-Drain High Voltage
—
—
8.5*
V
RA4 pin PIC16F627A/628A/648A,
PIC16LF627A/628A/648A
Capacitive Loading Specs on Output Pins
D100*
D101*
COSC2 OSC2 pin
—
—
—
15
50
pF In XT, HS and LP modes when external
clock used to drive OSC1.
pF
Cio All I/O pins/OSC2 (in RC mode)
—
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
†
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F627A/628A/648A be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
4: Includes OSC1 and OSC2 when configured as I/O pins, CLKIN, or CLKOUT.
DS40044A-page 136
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended)
PIC16LF627A/628A/648A (Industrial)
Standard Operating Conditions (unless otherwise stated)
DC Characteristics
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial and
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-2 and Table 17-3
Parameter
Sym
Characteristic
Min
Typ†
Max Units
Conditions
No.
Data EEPROM Memory
Endurance
Endurance
D120
D120A
D121
ED
ED
100K
10K
1M
100K
—
—
E/W -40°C ≤ TA ≤ 85°C
E/W 85°C ≤ TA ≤ 125°C
VDRW VDD for read/write
VMIN
5.5
V
VMIN = Minimum operating
voltage
D122
D123
TDEW Erase/Write cycle time
TRETD Characteristic Retention
—
100
4
—
8*
—
ms
Year Provided no other
specifications are violated
D124
TREF Number of Total Erase/Write
(1)
Cycles before Refresh
1M
10M
—
E/W -40°C to +85°C
Program FLASH Memory
D130
D130A
D131
EP
Endurance
Endurance
VDD for read
10K
1000
VMIN
100K
10K
—
—
—
E/W -40°C ≤ TA ≤ 85°C
E/W 85°C ≤ TA ≤ 125°C
EP
VPR
5.5
V
VMIN = Minimum operating
voltage
D132
D132A
VIE
VDD for Block erase
4.5
—
—
5.5
5.5
V
V
VPEW VDD for write
VMIN
VMIN = Minimum operating
voltage
D133
D133A
D134
TIE
Block Erase cycle time
TPEW Write cycle time
TRETP Characteristic Retention
—
—
4
2
8*
4*
—
ms VDD > 4.5V
ms
year Provided no other
100
—
specifications are violated
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0 V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Refer to Section 13.7 for a more detailed discussion on data EEPROM endurance.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 137
PIC16F627A/628A/648A
TABLE 17-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 2.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
No.
Characteristics
Sym
Min
Typ
Max
Units
Comments
D300
Input Offset Voltage
VIOFF
VICM
—
0
5.0
—
10
VDD - 1.5*
—
mV
V
D301
D302
Input Common Mode Voltage
Common Mode Rejection Ratio
CMRR
55*
—
db
(1)
D303
Response Time
TRESP
—
—
—
300
400
400
400*
600*
600*
ns
ns
ns
VDD = 3.0V to 5.5V
-40° to +85°C
VDD = 3.0V to 5.5V
-85° to +125°C
VDD = 2.0V to 3.0V
-40° to +85°C
D304
Comparator Mode Change to
Output Valid
TMC2OV
—
300
10*
µs
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 17-3: VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 2.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Spec
No.
Characteristics
Resolution
Sym
Min
Typ
Max
Units
Comments
D310
VRES
—
—
VDD/24
VDD/32
(2)
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
D311
Absolute Accuracy
VRAA
—
—
—
—
1/4
1/2
*
*
LSb Low Range (VRR = 1)
LSb High Range (VRR = 0)
(2)
D312
D313
Unit Resistor Value (R)
VRUR
TSET
—
—
2k*
—
—
Ω
(1)
Settling Time
10*
µs
*
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
2: When VDD is between 2.0V and 3.0V the VREF output voltage levels on RA2 descirbed by the equa-
tion:[VDD/2 ± (3-VDD)/2] may cause the Absolute Accuracy (VRAA) of the VREF output signal on RA2 to be
greater than the stated max.
DS40044A-page 138
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
17.5 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
T
Time
Lowercase subscripts (pp) and their meanings:
pp
ck
io
CLKOUT
I/O port
MCLR
osc
t0
OSC1
T0CKI
mc
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-Impedance
FIGURE 17-3:
LOAD CONDITIONS
LOAD CONDITION 1
VDD/2
LOAD CONDITION 2
RL
CL
CL
PIN
PIN
VSS
VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 139
PIC16F627A/628A/648A
17.6 Timing Diagrams and Specifications
FIGURE 17-4:
EXTERNAL CLOCK TIMING
Q4
Q3
Q4
Q1
Q1
Q2
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
(1)
Fosc External CLKIN Frequency
DC
—
4
MHz XT and RC Osc mode,
VDD = 5.0 V
DC
DC
—
—
—
—
—
20
200
4
MHz HS Osc mode
kHz LP Osc mode
(1)
Oscillator Frequency
MHz RC Osc mode, VDD = 5.0V
MHz XT Osc mode
0.1
4
1
—
—
—
20
200
MHz HS Osc mode
kHz LP Osc mode
—
—
4
37
—
—
—
—
—
—
—
MHz INTOSC mode (fast)
kHz INTOSC mode (slow)
ns XT and RC Osc mode
ns HS Osc mode
(1)
1
Tosc External CLKIN Period
250
50
—
5
—
µs LP Osc mode
(1)
Oscillator Period
250
250
50
—
ns RC Osc mode
—
10,000
1,000
—
ns XT Osc mode
—
ns HS Osc mode
5
—
µs LP Osc mode
—
250
27
TCY
—
—
ns INTOSC mode (fast)
µs INTOSC mode (slow)
ns TCY = 4/FOSC
—
—
2
3
Tcy
Instruction Cycle Time
1.0
100*
DC
—
TosL, External CLKIN (OSC1) High
TosH External CLKIN Low
ns XT oscillator, TOSC L/H duty
cycle
4
RC
External Biased RC Fre-
quency
10 kHz*
—
4 MHz
—
VDD = 5.0V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note: Instruction cycle period (Tcy) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-
ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values
with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max” cycle time
limit is “DC” (no clock) for all devices.
DS40044A-page 140
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 17-5:
PRECISION INTERNAL OSCILLATOR PARAMETERS
Parameter
No.
Sym
Characteristic
Min
Typ
Max Units
Conditions
—
4
—
MHz
F10
F13
FIOSC Oscillator Center frequency
∆IOSC Oscillator Stability (jitter)
—
—
—
—
1
%
%
VDD = 3.5 V, 25°C
2
2.0 V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
—
—
5
%
2.0 V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (IND)
-40°C ≤ TA ≤ +125°C (EXT)
—
—
—
6
4
3
TBD
TBD
TBD
µs VDD = 2.0V, -40°C to +85°C
µs VDD = 3.0V, -40°C to +85°C
µs VDD = 5.0V, -40°C to +85°C
TIOSCST
F14
Oscillator Wake-up from
SLEEP start-up time
FIGURE 17-5:
OSC1
CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
11
10
22
23
CLKOUT
13
12
16
19
18
14
I/O PIN
(INPUT)
15
17
I/O PIN
(OUTPUT)
NEW VALUE
OLD VALUE
20, 21
TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units
10
10A
11
11A
12
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
PIC16F62X
—
—
—
—
—
—
—
—
—
75
—
75
—
35
—
35
—
—
—
—
200*
400*
200*
400*
100*
200*
100*
200*
20*
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LF62X
PIC16F62X
PIC16LF62X
PIC16F62X
PIC16LF62X
PIC16F62X
PIC16LF62X
TckR
TckF
CLKOUT rise time
CLKOUT fall time
12A
13
13A
14
TckL2ioV CLKOUT ↓ to Port out valid
15
TioV2ckH Port in valid before
PIC16F62X Tosc+200 ns*
—
18
TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
100*
200*
—
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 141
PIC16F627A/628A/648A
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units
CLKOUT ↑
PIC16LF62X Tosc+400 ns*
0
—
—
50
—
—
—
—
ns
ns
ns
ns
ns
16
17
TckH2ioI Port in hold after CLKOUT ↑
TosH2ioV OSC1↑ (Q1 cycle) to
Port out valid
PIC16F62X
—
—
150*
300*
—
PIC16LF62X
18
TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
100*
200*
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
FIGURE 17-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time out
32
OST
Time out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 17-7:
BROWN-OUT DETECT TIMING
VBOR
VDD
35
DS40044A-page 142
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
TABLE 17-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
2000
TBD
—
—
ns
VDD = 5V, -40°C to +85°C
TBD
TBD
ms Extended temperature
31
Twdt
Tost
Watchdog Timer Time out Period
7*
18
33*
ms VDD = 5V, -40°C to +85°C
ms Extended temperature
(No Prescaler)
TBD
TBD
TBD
32
33
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Tpwrt Power-up Timer Period
28*
72
132*
TBD
ms VDD = 5V, -40°C to +85°C
ms Extended temperature
TBD
TBD
34
TIOZ
TBOR
I/O Hi-impedance from MCLR Low
—
—
—
2.0*
—
µs
or Watchdog Timer Reset
35
*
Brown-out Reset pulse width
100*
µs
VDD ≤ VBOR (D005)
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RB6/T1OSO/T1CKI
46
45
47
48
TMR0 OR
TMR1
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 143
PIC16F627A/628A/648A
TABLE 17-9: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
40
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler 0.5TCY + 20*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
With Prescaler
10*
41
42
No Prescaler 0.5TCY + 20*
With Prescaler
10*
Greater of:
TCY + 40*
N
N = prescale
value (2, 4, ...,
256)
45
46
47
Tt1H T1CKI High
Time
Synchronous, No Prescaler
Synchronous, PIC16F62X
with Prescaler
0.5TCY + 20*
15*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LF62X
25*
Asynchronous PIC16F62X
PIC16LF62X
30*
50*
Tt1L T1CKI Low
Time
Synchronous, No Prescaler
Synchronous, PIC16F62X
with Prescaler
0.5TCY + 20*
15*
PIC16LF62X
25*
Asynchronous PIC16F62X
PIC16LF62X
30*
50*
Tt1P T1CKI input
period
Synchronous PIC16F62X
Greater of:
TCY + 40*
N
N = prescale
value (1, 2, 4, 8)
PIC16LF62X
Greater of:
TCY + 40*
N
—
—
—
Asynchronous PIC16F62X
PIC16LF62X
60*
—
—
—
—
—
ns
ns
100*
(1)
Ft1 Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
—
32.7
kHz
48 TCKEZt Delay from external clock edge to timer
mr1 increment
2Tosc
—
7Tosc
—
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This oscillator is intended to work only with 32.768 kHz watch crystals and their manufactured tolerances.
Higher value crystal frequencies may not be compatible with this crystal driver.
DS40044A-page 144
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
FIGURE 17-10:
CAPTURE/COMPARE/PWM TIMINGS
RB3/CCP1
(CAPTURE MODE)
50
51
52
RB3/CCP1
(COMPARE OR PWM MODE)
53
54
TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
50
TccL CCP
No Prescaler
0.5TCY + 20*
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
input low time
PIC16F62X
10*
20*
With Prescaler
No Prescaler
PIC16LF62X
51 TccH CCP
input high time
0.5TCY + 20*
10*
PIC16F62X
With Prescaler
PIC16LF62X
20*
52
53
TccP CCP input period
3TCY + 40*
N
N = prescale
value (1,4 or 16)
TccR CCP output rise time
TccF CCP output fall time
PIC16F62X
PIC16LF62X
PIC16F62X
PIC16LF62X
10 25*
25 45*
10 25*
25 45*
ns
ns
ns
ns
54
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 145
PIC16F627A/628A/648A
FIGURE 17-11:
RA4/T0CKI
TIMER0 CLOCK TIMING
41
40
42
TMR0
TABLE 17-9: TIMER0 CLOCK REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40
Tt0H T0CKI High Pulse Width
Tt0L T0CKI Low Pulse Width
Tt0P T0CKI Period
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
41
42
0.5 TCY + 20*
10*
TCY + 40*
N
N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS40044A-page 146
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
Not Available at this time.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 147
PIC16F627A/628A/648A
NOTES:
DS40044A-page 148
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
18-LEAD PDIP (.300")
EXAMPLE
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16F627A-I/P
0210017
YYWWNNN
18-LEAD SOIC (.300")
EXAMPLE
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F628A
-E/SO
0210017
YYWWNNN
20-LEAD SSOP
EXAMPLE
XXXXXXXXXXX
XXXXXXXXXXX
PIC16F648A
-I/SS
YYWWNNN
0210017
28-LEAD QFN
EXAMPLE
XXXXXXXX
XXXXXXXX
YYWWNNN
16F628A
-I/ML
0210017
*
Legend: XX...X
YY
Customer specific information
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried
over to the next line thus limiting the number of available characters for customer specific
information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code.
For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 149
PIC16F627A/628A/648A
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS40044A-page 150
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
1
B
n
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 151
PIC16F627A/628A/648A
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS40044A-page 152
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN)
EXPOSED
METAL
PADS
E
E1
Q
D1
D
D2
p
2
1
B
n
R
E2
BOTTOM VIEW
CH x 45
L
TOP VIEW
α
A2
A
A1
A3
Units
Dimension Limits
INCHES
NOM
MILLIMETERS*
NOM
MIN
MAX
MIN
MAX
n
Number of Pins
Pitch
28
28
p
.026 BSC
.033
0.65 BSC
0.85
Overall Height
A
A2
A1
A3
E
.039
1.00
Molded Package Thickness
Standoff
.026
.0004
.031
.002
0.65
0.80
0.05
.000
.140
0.00
0.01
0.20 REF.
Base Thickness
Overall Width
.008 REF.
.236 BSC
.226 BSC
.146
6.00 BSC
5.75 BSC
Molded Package Width
Exposed Pad Width
Overall Length
E1
E2
D
.152
3.55
3.70
3.85
.236 BSC
.226 BSC
.146
6.00 BSC
5.75 BSC
Molded Package Length
Exposed Pad Length
Lead Width
D1
D2
B
.140
.009
.020
.005
.012
.009
.152
.014
.030
.010
.026
.024
12
3.55
0.23
0.50
0.13
0.30
0.24
3.70
3.85
0.35
0.75
0.23
0.65
0.60
12
.011
0.28
0.60
0.17
0.40
0.42
Lead Length
L
.024
Tie Bar Width
R
.007
Q
Tie Bar Length
.016
Chamfer
CH
.017
α
Mold Draft Angle Top
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: M0-220
Drawing No. C04-114
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 153
PIC16F627A/628A/648A
NOTES:
DS40044A-page 154
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
APPENDIX A: DATA SHEET
REVISION HISTORY
APPENDIX B: DEVICE
DIFFERENCES
The differences between the PIC16F627A/628A/648A
devices listed in this data sheet are shown in Table B-1.
Revision A
This is a new data sheet.
TABLE B-1:
DEVICE DIFFERENCES
Memory
Device
FLASH
Program
RAM
Data
EEPROM
Data
PIC16F627A
PIC16F628A
PIC16F648A
1024 x 14 224 x 8
2048 x 14 224 x 8
4096 x 14 256 x 8
128 x 8
128 x 8
256 x 8
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 155
PIC16F627A/628A/648A
APPENDIX C: DEVICE MIGRATIONS
APPENDIX D: MIGRATING FROM
OTHER PICmicro
DEVICES
This section describes the functional and electrical
specification differences when migrating between func-
tionally similar devices. (such as from a PIC16F627 to
a PIC16F627A).
This discusses some of the issues in migrating from
other PICmicro devices to the PIC16F627A/628A/648A
family of devices.
C.1
PIC16F627/628 to a PIC16F627A/628A
1. ER mode is now RC mode.
D.1
PIC16C62X/CE62X to PIC16F627A/628A/
648A Migration
2. Code Protection for the Program Memory has
changed from Code Protect sections of memory
to Code Protect of the whole memory. The Con-
figuration bits CP0 and CP1 in the PIC16F627/
628 do not exist in the PIC16F627A/628A. They
have been replaced with one Configuration
bit<13> CP.
See
(www.microchip.com).
Microchip
web
site
for
availability
D.2
PIC16C622A to PIC16F627A/628A/648A
Migration
See
(www.microchip.com).
Microchip
web
site
for
availability
3. “Brown-out Detect (BOD)” terminology has
changed to “Brown-out Reset (BOR)” to better
represent the function of the Brown-out circuitry.
4. Enabling Brown-out Reset (BOR) does not auto-
matically enable the Power-up Timer (PWRT)
the way it did in the PIC16F627/628.
Note: This device has been designed to perform
to the parameters of its data sheet. It has
been tested to an electrical specification
designed to determine its conformance
with these parameters. Due to process
differences in the manufacture of this
device, this device may have different
performance characteristics than its earlier
version. These differences may cause this
device to perform differently in your
application than the earlier version of this
device.
5. INTRC is now called INTOSC.
6. Timer1 Oscillator is now designed for
32.768 kHz operation. In the PIC16F627/628
the Timer1 Oscillator was designed to run up to
200 kHz.
7. The Dual Speed Oscillator mode only works in
the INTOSC Oscillator mode. In the PIC16F627/
628 the Dual Speed Oscillator mode worked in
both the INTRC and ER Oscillator modes.
DS40044A-page 156
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
APPENDIX E: DEVELOPMENT
TOOL VERSION
REQUIREMENTS
This lists the minimum requirements (software/
firmware) of the specified development tool to support
the devices listed in this data sheet.
MPLAB® IDE:
TBD
TBD
MPLAB® SIMULATOR:
MPLAB® ICE 3000:
PIC16F627A/628A/648A Processor Module:
Part Number - TBD
PIC16F627A/628A/648A Device Adapter:
Socket
Part Number
TBD
TBD
18-pin PDIP
18-pin SOIC
20-pin SSOP
28-pin QFN
TBD
TBD
MPLAB® ICD:
TBD
TBD
TBD
TBD
PRO MATE® II:
PICSTART® Plus:
TM
MPASM Assembler:
MPLAB® C18 C Compiler: TBD
Note: Please read all associated README.TXT
files that are supplied with the develop-
ment tools. These "read me" files will dis-
cuss product support and any known
limitations.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 157
PIC16F627A/628A/648A
NOTES:
DS40044A-page 158
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
ON-LINE SUPPORT
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
Microchip provides on-line support on the Microchip
World Wide Web site.
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
®
®
and a web browser, such as Netscape or Microsoft
Internet Explorer. Files are also available for FTP
download from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 159
PIC16F627A/628A/648A
organization, clarity, subject matter, and ways in which
our documentation can better serve you, please FAX
your comments to the Technical Publications Manager
at (480) 792-4150.
READER RESPONSE
It is our intention to provide you with the best documen-
tation possible to ensure successful use of your Micro-
chip product. If you wish to provide your comments on
Please list the following information, and use this outline to provide us with your comments about this document.
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Would you like a reply?
Y
N
Literature Number:
DS40044A
Device:
PIC16F627A/628A/648A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40044A-page 160
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
Clocking Scheme/Instruction Cycle .................................... 13
CLRF Instruction............................................................... 115
CLRW Instruction.............................................................. 116
CLRWDT Instruction......................................................... 116
Code Examples
INDEX
A
A/D
Special Event Trigger (CCP)....................................... 57
Data EEPROM Refresh Routine ................................ 92
Code Protection................................................................ 108
COMF Instruction.............................................................. 116
Comparator
Absolute Maximum Ratings .............................................. 131
ADDLW Instruction ........................................................... 113
ADDWF Instruction ........................................................... 113
ANDLW Instruction ........................................................... 113
ANDWF Instruction ........................................................... 113
Architectural Overview.......................................................... 9
Assembler
Block Diagrams
I/O Operating Modes .......................................... 62
Modified Comparator Output .............................. 64
Comparator Module.................................................... 61
Configuration .............................................................. 62
Interrupts .................................................................... 65
Operation.................................................................... 63
Reference................................................................... 63
Compare (CCP Module) ..................................................... 56
Block Diagram ............................................................ 56
CCP Pin Configuration ............................................... 57
CCPR1H:CCPR1L Registers ..................................... 56
Software Interrupt....................................................... 57
Special Event Trigger ................................................. 57
Timer1 Mode Selection............................................... 57
Configuration Bits ............................................................... 93
Crystal Operation................................................................ 95
MPASM Assembler................................................... 125
B
Baud Rate Error.................................................................. 71
Baud Rate Formula............................................................. 71
BCF Instruction ................................................................. 114
Block Diagrams
Comparator
I/O Operating Modes .......................................... 62
Modified Comparator Output .............................. 64
I/O Ports
RB0/INT Pin........................................................ 37
RB1/RX/DT Pin................................................... 37
RB2/TX/CK Pin................................................... 38
RB3/CCP1 Pin.................................................... 38
RB4/PGM Pin ..................................................... 39
RB5 Pin............................................................... 40
RB6/T1OSO/T1CKI Pin ...................................... 41
RB7/T1OSI Pin ................................................... 42
RC Oscillator Mode..................................................... 96
USART Receive.......................................................... 79
USART Transmit......................................................... 77
BRGH bit............................................................................. 71
Brown-Out Reset (BOR) ..................................................... 98
BSF Instruction ................................................................. 114
BTFSC Instruction............................................................. 114
BTFSS Instruction............................................................. 115
D
Data EEPROM Memory...................................................... 89
EECON1 Register ...................................................... 89
EECON2 Register ...................................................... 89
Operation During Code Protection ............................. 92
Reading ...................................................................... 91
Spurious Write Protection........................................... 91
Using .......................................................................... 92
Write Verify ................................................................. 91
Writing to .................................................................... 91
Data Memory Organization................................................. 15
DECF Instruction .............................................................. 116
DECFSZ Instruction.......................................................... 117
Development Support....................................................... 125
Development Tool Version Requirements........................ 157
Device Differences............................................................ 155
Device Migrations ............................................................. 156
Dual-speed Oscillator Modes.............................................. 97
C
CALL Instruction ............................................................... 115
Capture (CCP Module) ....................................................... 56
Block Diagram............................................................. 56
CCP Pin Configuration................................................ 56
CCPR1H:CCPR1L Registers...................................... 56
Changing Between Capture Prescalers...................... 56
Prescaler..................................................................... 56
Software Interrupt ....................................................... 56
Timer1 Mode Selection ............................................... 56
Capture/Compare/PWM (CCP)........................................... 55
Capture Mode. See Capture
E
EECON1 register................................................................ 90
EECON2 register................................................................ 90
Errata.................................................................................... 3
External Crystal Oscillator Circuit ....................................... 95
G
CCP1 .......................................................................... 55
CCPR1H Register............................................... 55
CCPR1L Register ............................................... 55
CCP2 .......................................................................... 55
Compare Mode. See Compare
General-Purpose Register File ........................................... 15
GOTO Instruction.............................................................. 117
I
I/O Ports ............................................................................. 31
Bi-Directional .............................................................. 44
Block Diagrams
PWM Mode. See PWM
Timer Resources......................................................... 55
CCP1CON Register
RB0/INT Pin........................................................ 37
RB1/RX/DT Pin................................................... 37
RB2/TX/CK Pin................................................... 38
RB3/CCP1 Pin.................................................... 38
RB4/PGM Pin ..................................................... 39
CCP1M3:CCP1M0 Bits............................................... 55
CCP1X:CCP1Y Bits.................................................... 55
CCP2CON Register
CCP2M3:CCP2M0 Bits............................................... 55
CCP2X:CCP2Y Bits.................................................... 55
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 161
PIC16F627A/628A/648A
RB5 Pin...............................................................40
RB6/T1OSO/T1CKI Pin ......................................41
RB7/T1OSI Pin ...................................................42
PORTA........................................................................31
PORTB........................................................................36
Programming Considerations .....................................44
Successive Operations ...............................................44
TRISA .........................................................................31
TRISB .........................................................................36
ICEPIC In-Circuit Emulator ...............................................126
ID Locations ......................................................................108
INCF Instruction ................................................................118
INCFSZ Instruction............................................................118
In-Circuit Serial Programming...........................................109
Indirect Addressing, INDF and FSR Registers....................28
Instruction Flow/Pipelining ..................................................13
Instruction Set
CCP1 Flag (CCP1IF Bit)............................................. 56
IORLW Instruction ............................................................ 119
IORWF Instruction ............................................................ 119
K
KeeLoq Evaluation and Programming Tools .................... 128
M
Memory Organization
Data EEPROM Memory.................................. 89, 91, 92
Migrating from other PICmicro Devices............................ 156
MOVF Instruction.............................................................. 119
MOVLW Instruction........................................................... 119
MOVWF Instruction .......................................................... 120
MPLAB C17 and MPLAB C18 C Compilers ..................... 125
MPLAB ICD In-Circuit Debugger ...................................... 127
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE ............................................................... 126
MPLAB Integrated Development Environment Software.. 125
MPLINK Object Linker/MPLIB Object Librarian................ 126
ADDLW .....................................................................113
ADDWF.....................................................................113
ANDLW .....................................................................113
ANDWF.....................................................................113
BCF...........................................................................114
BSF...........................................................................114
BTFSC ......................................................................114
BTFSS ......................................................................115
CALL.........................................................................115
CLRF.........................................................................115
CLRW........................................................................116
CLRWDT...................................................................116
COMF .......................................................................116
DECF ........................................................................116
DECFSZ....................................................................117
GOTO........................................................................117
INCF..........................................................................118
INCFSZ.....................................................................118
IORLW.......................................................................119
IORWF ......................................................................119
MOVF........................................................................119
MOVLW.....................................................................119
MOVWF ....................................................................120
NOP ..........................................................................120
OPTION ....................................................................120
RETFIE .....................................................................120
RETLW......................................................................121
RETURN...................................................................121
RLF ...........................................................................121
RRF...........................................................................122
SLEEP ......................................................................122
SUBLW......................................................................122
SUBWF.....................................................................123
SWAPF .....................................................................123
TRIS..........................................................................123
XORLW .....................................................................124
XORWF.....................................................................124
Instruction Set Summary...................................................111
INT Interrupt......................................................................105
INTCON Register................................................................24
Interrupt Sources
N
NOP Instruction ................................................................ 120
O
OPTION Instruction .......................................................... 120
OPTION Register................................................................ 23
Oscillator Configurations..................................................... 95
Oscillator Start-up Timer (OST).......................................... 98
P
Package Marking Information........................................... 149
Packaging Information...................................................... 149
PCL and PCLATH............................................................... 28
Stack........................................................................... 28
PCON Register................................................................... 27
PICDEM 1 Low Cost PICmicro Demonstration Board...... 127
PICDEM 17 Demonstration Board.................................... 128
PICDEM 2 Low Cost PIC16CXX Demonstration Board ... 127
PICDEM 3 Low Cost PIC16CXXX Demonstration Board. 128
PICSTART Plus Entry Level Development Programmer.. 127
PIE1 Register...................................................................... 25
Pin Functions
RC6/TX/CK........................................................... 69–86
RC7/RX/DT........................................................... 69–86
PIR1 Register ..................................................................... 26
Port RB Interrupt............................................................... 105
PORTA ............................................................................... 31
PORTB ............................................................................... 36
Power Control/Status Register (PCON).............................. 99
Power-Down Mode (SLEEP) ............................................ 107
Power-On Reset (POR)...................................................... 98
Power-up Timer (PWRT) .................................................... 98
PR2 Register ................................................................ 52, 58
PRO MATE II Universal Device Programmer................... 127
Program Memory Organization........................................... 15
PWM (CCP Module) ........................................................... 58
Block Diagram ............................................................ 58
Simplified PWM .................................................. 58
Capture Complete (CCP)............................................56
Compare Complete (CCP)..........................................57
TMR2 to PR2 Match (PWM) .......................................58
Interrupts...........................................................................104
Interrupts, Enable Bits
CCPR1H:CCPR1L Registers...................................... 58
Duty Cycle .................................................................. 59
Example Frequencies/Resolutions ............................. 59
Period ......................................................................... 58
Set-Up for PWM Operation......................................... 59
TMR2 to PR2 Match ................................................... 58
CCP1 Enable (CCP1IE Bit).........................................56
Interrupts, Flag Bits
DS40044A-page 162
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
PR2 register................................................................ 52
Prescaler .............................................................. 52, 59
Timer2 Module............................................................ 52
TMR2 output............................................................... 52
TMR2 to PR2 Match Interrupt..................................... 58
Timing Diagrams
Q
Q-Clock............................................................................... 59
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator....................................................................... 96
RC Oscillator Mode
Timer0....................................................................... 143
Timer1....................................................................... 143
USART
Block Diagram............................................................. 96
Registers
Asynchronous Receiver...................................... 80
USART Asynchronous Master Transmission ............. 77
USART Asynchronous Reception .............................. 80
USART RX Pin Sampling ..................................... 75, 76
USART Synchronous Reception ................................ 86
USART Synchronous Transmission ........................... 84
Timing Diagrams and Specifications ................................ 140
TMR0 Interrupt.................................................................. 105
TMR1CS bit ........................................................................ 48
TMR1ON bit........................................................................ 48
TMR2ON bit........................................................................ 53
TOUTPS0 bit ...................................................................... 53
TOUTPS1 bit ...................................................................... 53
TOUTPS2 bit ...................................................................... 53
TOUTPS3 bit ...................................................................... 53
TRIS Instruction................................................................ 123
TRISA................................................................................. 31
TRISB................................................................................. 36
Maps
PIC16F627A ................................................. 16, 17
PIC16F628A ................................................. 16, 17
Reset................................................................................... 97
RETFIE Instruction............................................................ 120
RETLW Instruction............................................................ 121
RETURN Instruction ......................................................... 121
Revision History................................................................ 155
RLF Instruction.................................................................. 121
RRF Instruction................................................................. 122
S
Serial Communication Interface (SCI) Module, See USART
Serialized Quick-Turnaround-Production (SQTP) Devices... 7
SLEEP Instruction............................................................. 122
Software Simulator (MPLAB SIM)..................................... 126
Special Event Trigger. See Compare
Special Features of the CPU .............................................. 93
Special Function Registers ................................................. 18
Status Register ................................................................... 22
SUBLW Instruction............................................................ 122
SUBWF Instruction ........................................................... 123
SWAPF Instruction............................................................ 123
U
Universal Synchronous Asynchronous Receiver Transmitter
(USART)............................................................................. 69
Asynchronous Receiver
Setting Up Reception.......................................... 82
Asynchronous Receiver Mode
T
Address Detect................................................... 82
Block Diagram.................................................... 82
USART
T1CKPS0 bit ....................................................................... 48
T1CKPS1 bit ....................................................................... 48
T1OSCEN bit ...................................................................... 48
T1SYNC bit......................................................................... 48
T2CKPS0 bit ....................................................................... 53
T2CKPS1 bit ....................................................................... 53
Timer0
Asynchronous Mode................................................... 76
Asynchronous Receiver.............................................. 79
Asynchronous Reception............................................ 81
Asynchronous Transmission....................................... 77
Asynchronous Transmitter.......................................... 76
Baud Rate Generator (BRG) ...................................... 71
Block Diagrams
Block Diagrams
Timer0/WDT ....................................................... 46
External Clock Input.................................................... 45
Interrupt....................................................................... 45
Prescaler..................................................................... 46
Switching Prescaler Assignment................................. 47
Timer0 Module ............................................................ 45
Timer1
Transmit.............................................................. 77
USART Receive ................................................. 79
BRGH bit .................................................................... 71
Sampling......................................................... 72, 73, 74
Synchronous Master Mode......................................... 83
Synchronous Master Reception ................................. 85
Synchronous Master Transmission ............................ 83
Synchronous Slave Mode........................................... 86
Synchronous Slave Reception ................................... 87
Synchronous Slave Transmit...................................... 86
Asynchronous Counter Mode ..................................... 50
Capacitor Selection..................................................... 51
External Clock Input.................................................... 49
External Clock Input Timing ........................................ 50
Oscillator..................................................................... 51
Prescaler............................................................... 49, 51
Resetting Timer1......................................................... 51
Resetting Timer1 Registers......................................... 51
Special Event Trigger (CCP)....................................... 57
Synchronized Counter Mode ...................................... 49
Timer Mode................................................................. 49
TMR1H........................................................................ 50
TMR1L ........................................................................ 50
Timer2
V
Voltage Reference
Configuration .............................................................. 67
Voltage Reference Module ......................................... 67
W
Watchdog Timer (WDT).................................................... 106
WWW, On-Line Support ....................................................... 3
Block Diagram............................................................. 52
Postscaler ................................................................... 52
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 163
PIC16F627A/628A/648A
X
XORLW Instruction ...........................................................124
XORWF Instruction ...........................................................124
DS40044A-page 164
Preliminary
2002 Microchip Technology Inc.
PIC16F627A/628A/648A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
PIC16F627A - E/P 301 = Extended Temp.,
PDIP package, 20 MHz, normal VDD limits,
QTP pattern #301.
b)
PIC16LF627A - I/SO = Industrial Temp.,
Device
PIC16F627A/628A/648A:Standard VDD range 3.0V to 5.5V
PIC16F627A/628A/648ATVDD range 3.0V to 5.5V (Tape
and Reel)
SOIC package, 20 MHz, extended VDD limits.
PIC16LF627A/628A/648A:VDD range 2.0V to 5.5V
PIC16LF627A/628A/648AT:VDD range 2.0V to 5.5V (Tape
and Reel)
Temperature Range
Package
I
E
=
=
-40°C to
-40°C to
+85°C
+125°C
P
=
=
=
=
PDIP
SO
SS
ML
SOIC (Gull Wing, 300 mil body)
SSOP (209 mil)
QFN (28 Lead)
Pattern
3-Digit Pattern Code for QTP (blank otherwise).
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2002 Microchip Technology Inc.
Preliminary
DS40044A-page 165
WORLDWIDE SALES AND SERVICE
Japan
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
AMERICAS
ASIA/PACIFIC
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Australia
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
China - Beijing
Rocky Mountain
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-4338
Bei Hai Wan Tai Bldg.
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Atlanta
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034 Fax: 770-640-0307
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
China - Chengdu
Boston
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Taiwan
Microchip Technology (Barbados) Inc.,
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
Chengdu 610016, China
Tel: 86-28-86766200 Fax: 86-28-86766599
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Microchip Technology Austria GmbH
Durisolstrasse 2
A-4600 Wels
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Los Angeles
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 15-16, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-82350361 Fax: 86-755-82366086
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
China - Hong Kong SAR
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
Tel: 408-436-7950 Fax: 408-436-7955
Germany
Microchip Technology GmbH
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
11/15/02
DS40044A-page 166
Preliminary
2002 Microchip Technology Inc.
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FLASH-Based 8-Bit CMOS Microcontroller, -40C to +85C, 20-SSOP 208mil, TUBE
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