PIC16F73T-I/L301 [MICROCHIP]
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC;型号: | PIC16F73T-I/L301 |
厂家: | MICROCHIP |
描述: | IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,44PIN,PLASTIC |
文件: | 总168页 (文件大小:3738K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PIC16F7X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
Pin Diagram
PDIP
• PIC16F73
• PIC16F74
• PIC16F76
• PIC16F77
MCLR/VPP
RA0/AN0
1
40
39
38
37
36
35
34
33
32
31
RB7
RB6
2
Microcontroller Core Features:
RA1/AN1
RA2/AN2
3
RB5
RB4
RB3
RB2
• High-performance RISC CPU
4
RA3/AN3/VREF
RA4/T0CKI
5
• Only 35 single word instructions to learn
6
• All single cycle instructions except for program
branches which are two cycle
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
7
RB1
8
RB0/INT
VDD
9
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
10
11
12
13
14
15
16
17
18
19
20
VSS
30
29
28
RD7/PSP7
VSS
• Up to 8K x 14 words of FLASH Program Memory,
Up to 368 x 8 bytes of Data Memory (RAM)
RD6/PSP6
RD5/PSP5
RD4/PSP4
OSC1/CLKIN
OSC2/CLKOUT
27
26
25
24
23
22
21
• Pinout compatible to the PIC16C73B/74B/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Eight level deep hardware stack
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC3/SCK/SCL
RD0/PSP0
RC4/SDI/SDA
RD3/PSP3
RD1/PSP1
RD2/PSP2
• Direct, Indirect and Relative Addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
Peripheral Features:
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low power, high speed CMOS FLASH technology
• Fully static design
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• In-Circuit Serial Programming (ICSP) via two
pins
• Processor read access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Industrial temperature range
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI (Master
mode) and I2C (Slave)
• Low power consumption:
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
- < 2 mA typical @ 5V, 4 MHz
- 20 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 1
PIC16F7X
Pin Diagrams
DIP, SOIC, SSOP
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
VSS
RB1
RB0/INT
VDD
OSC1/CLKIN
VSS
10
11
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
12
13
14
RC3/SCK/SCL
PLCC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
VDD
39
38
37
RB3
7
RB2
8
RB1
9
RB0/INT
VDD
36
35
34
33
32
31
30
29
10
11
12
13
14
15
16
17
PIC16F77
PIC16F74
VSS
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
QFP
NC
33
1
2
3
4
5
6
7
8
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
RC0/T1OSO/T1CKI
32
31
30
29
28
27
26
OSC2/CLKOUT
OSC1/CLKIN
VSS
PIC16F77
PIC16F74
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
VDD
RB0/INT
RB1
9
10
11
25
24
23
RB2
RB3
DS30325A-page 2
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
Key Features
PICmicro™ Mid-Range Reference Manual
(DS33023)
PIC16F73
PIC16F74
PIC16F76
PIC16F77
Operating Frequency
RESETS (and Delays)
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
DC - 20 MHz
POR, BOR
POR, BOR
POR, BOR
POR, BOR
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
(PWRT, OST)
FLASH Program Memory
4K
4K
8K
8K
(14-bit words, 100 E/W cycles)
Data Memory (bytes)
Interrupts
192
192
368
368
11
12
11
12
I/O Ports
Ports A,B,C
Ports A,B,C,D,E
Ports A,B,C
Ports A,B,C,D,E
Timers
3
3
3
3
Capture/Compare/PWM Modules
Serial Communications
Parallel Communications
8-bit Analog-to-Digital Module
Instruction Set
2
SSP, USART
—
2
2
SSP, USART
—
2
SSP, USART
PSP
SSP, USART
PSP
5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
35 Instructions
35 Instructions
35 Instructions
35 Instructions
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 3
PIC16F7X
Table of Contents
1.0
Device Overview............................................................................................................................................................ 5
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
Memory Organization .................................................................................................................................................. 11
I/O Ports....................................................................................................................................................................... 29
Reading Program Memory........................................................................................................................................... 41
Timer0 Module............................................................................................................................................................. 45
Timer1 Module............................................................................................................................................................. 49
Timer2 Module............................................................................................................................................................. 53
Capture/Compare/PWM Modules................................................................................................................................ 55
Synchronous Serial Port (SSP) Module....................................................................................................................... 61
Universal Synchronous Asynchronous Receiver Transmitter (USART) ...................................................................... 73
Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89
Special Features of the CPU ....................................................................................................................................... 95
Instruction Set Summary ........................................................................................................................................... 111
Development Support................................................................................................................................................ 119
Electrical Characteristics ........................................................................................................................................... 125
DC and AC Characteristics Graphs and Tables ........................................................................................................ 147
Packaging Information ............................................................................................................................................... 149
Appendix A: Revision History......................................................................................................................................................... 157
Appendix B: Device Differences..................................................................................................................................................... 157
Appendix C: Conversion Considerations ....................................................................................................................................... 157
Index .................................................................................................................................................................................................. 159
On-Line Support................................................................................................................................................................................. 165
Reader Response .............................................................................................................................................................................. 166
PIC16F7X Product Identification System........................................................................................................................................... 167
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS30325A-page 4
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
There are four devices (PIC16F73, PIC16F74,
PIC16F76 and PIC16F77) covered by this data sheet.
The PIC16F76/73 devices are available in 28-pin pack-
ages and the PIC16F77/74 devices are available in
40-pin packages. The 28-pin devices do not have a
Parallel Slave Port implemented.
1.0
DEVICE OVERVIEW
This document contains device specific information.
Additional information may be found in the PICmicro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Represen-
tative or downloaded from the Microchip web site. The
Reference Manual should be considered a comple-
mentary document to this data sheet, and is highly rec-
ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2, respectively.
FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM
Program
FLASH
Device
Data Memory
PIC16F73
PIC16F76
4K
192 Bytes
368 Bytes
8K
13
8
PORTA
Data Bus
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2/
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
FLASH
Program
Memory
RAM
File
Registers
8 Level Stack
(13-bit)
Program
Bus
14
RAM Addr (1)
PORTB
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
PORTC
8
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
RC6/TX/CK
RC7/RX/DT
ALU
Power-on
Reset
8
Timing
Generation
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
MCLR VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
Synchronous
Serial Port
USART
CCP1,2
Note 1: Higher order bits are from the STATUS register.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 5
PIC16F7X
FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM
Program
FLASH
Device
Data Memory
PIC16F74
PIC16F77
4K
192 Bytes
368 Bytes
8K
13
8
PORTA
Data Bus
RAM
Program Counter
RA0/AN0
RA1/AN1
RA2/AN2
FLASH
Program
Memory
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
8 Level Stack
(13-bit)
File
Registers
Program
Bus
14
PORTB
RAM Addr (1)
9
RB0/INT
RB1
RB2
RB3/PGM
RB4
Addr MUX
Instruction reg
Indirect
Addr
7
Direct Addr
8
RB5
FSR reg
RB6/PGC
RB7/PGD
STATUS reg
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
3
MUX
Power-up
Timer
Oscillator
Start-up Timer
Instruction
Decode &
Control
ALU
RC6/TX/CK
RC7/RX/DT
Power-on
Reset
8
PORTD
Timing
Generation
Watchdog
Timer
W reg
RD0/PSP0
RD1/PSP1
RD2/PSP2
OSC1/CLKIN
OSC2/CLKOUT
Brown-out
Reset
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Parallel Slave Port
MCLR VDD, VSS
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
Timer0
Timer1
Timer2
8-bit A/D
USART
Synchronous
Serial Port
CCP1,2
Note 1: Higher order bits are from the STATUS register.
DS30325A-page 6
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 1-1:
PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
SSOP
SOIC
Pin#
DIP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(3)
OSC1/CLKIN
9
9
I
ST/CMOS
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
10
10
O
—
Oscillator crystal output. Connects to crystal or resonator in Crys-
tal Oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and denotes the instruction
cycle rate.
MCLR/VPP
1
1
I/P
ST
Master clear (RESET) input or programming voltage input or High
Voltage Test mode control. This pin is an active low RESET to the
device.
PORTA is a bi-directional I/O port.
RA0/AN0
2
3
4
5
6
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA0 can also be analog input0.
RA1/AN1
RA1 can also be analog input1.
RA2/AN2
RA2 can also be analog input2.
RA3/AN3/VREF
RA4/T0CKI
RA3 can also be analog input3 or analog reference voltage.
RA4 can also be the clock input to the Timer0 module. Output
is open drain type.
RA5/SS/AN4
7
7
I/O
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
21
21
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
RB2
RB3
RB4
RB5
RB6
22
23
24
25
26
27
22
23
24
25
26
27
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
Interrupt-on-change pin.
TTL
Interrupt-on-change pin.
(2)
Interrupt-on-change pin or Serial programming clock.
TTL/ST
TTL/ST
(2)
RB7
28
28
I/O
Interrupt-on-change pin or Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
11
12
13
14
15
11
12
13
14
15
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1 can also be the Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output for
2
both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
Data I/O (I C mode).
RC5/SDO
16
17
16
17
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
18
18
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
VSS
8, 19
20
8, 19
20
P
P
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
VDD
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 7
PIC16F7X
TABLE 1-2:
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
(4)
OSC1/CLKIN
13
14
14
15
30
31
I
Oscillator crystal input/external clock source input.
ST/CMOS
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
Crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear (RESET) input or programming voltage input or
High Voltage Test mode control. This pin is an active low
RESET to the device.
PORTA is a bi-directional I/O port.
RA0 can also be analog input0.
RA1 can also be analog input1.
RA2 can also be analog input2.
RA0/AN0
2
3
4
5
3
4
5
6
19
20
21
22
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA3 can also be analog input3 or analog reference
voltage.
RA4/T0CKI
6
7
7
8
23
24
I/O
I/O
ST
RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS/AN4
TTL
RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
RB0/INT
33
36
8
I/O
RB0 can also be the external interrupt pin.
TTL/ST
TTL
RB1
RB2
RB3
RB4
RB5
RB6
34
35
36
37
38
39
37
38
39
41
42
43
9
I/O
I/O
I/O
I/O
I/O
I/O
10
11
14
15
16
TTL
TTL
TTL
Interrupt-on-change pin.
TTL
Interrupt-on-change pin.
(2)
Interrupt-on-change pin or Serial programming clock.
TTL/ST
TTL/ST
(2)
RB7
40
44
17
I/O
Interrupt-on-change pin or Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
15
16
17
18
23
16
18
19
20
25
32
35
36
37
42
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
RC0 can also be the Timer1 oscillator output or a Timer1
clock input.
RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
RC4/SDI/SDA
RC3 can also be the synchronous serial clock input/output
2
for both SPI and I C modes.
RC4 can also be the SPI Data In (SPI mode) or
2
Data I/O (I C mode).
RC5/SDO
24
25
26
27
43
44
I/O
I/O
ST
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK
RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS30325A-page 8
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 1-2:
PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Pin Name
Description
PORTD is a bi-directional I/O port or parallel slave port when
interfacing to a microprocessor bus.
(3)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
(3)
(3)
(3)
(3)
(3)
(3)
(3)
3
4
5
PORTE is a bi-directional I/O port.
(3)
(3)
(3)
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
8
9
9
25
26
27
I/O
I/O
I/O
RE0 can also be read control for the parallel slave port, or
analog input5.
ST/TTL
ST/TTL
ST/TTL
10
11
RE1 can also be write control for the parallel slave port, or
analog input6.
10
RE2 can also be select control for the parallel slave port,
or analog input7.
VSS
VDD
NC
12,31
11,32
—
13,34
12,35
6,29
7,28
P
P
—
—
—
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
1,17,28, 12,13,
40 33,34
These pins are not internally connected. These pins should be
left unconnected.
Legend: I = input
O = output
— = Not used
I/O = input/output
TTL = TTL input
P = power
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 9
PIC16F7X
NOTES:
DS30325A-page 10
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 2-2: PIC16F74/73 PROGRAM
2.0
MEMORY ORGANIZATION
MEMORY MAP AND STACK
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 4.0).
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
Stack Level 1
Stack Level 2
Stack Level 8
2.1
Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The PIC16F77/76 devices have 8K x 14 words
of FLASH program memory and the PIC16F73/74
devices have 4K x 14. Accessing a location above the
physically implemented address will cause a wrap-
around.
RESET Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
On-Chip
Program
Memory
07FFh
0800h
FIGURE 2-1: PIC16F77/76 PROGRAM
MEMORY MAP AND STACK
Page 1
0FFFh
1000h
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
1FFFh
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
Interrupt Vector
Page 0
0004h
0005h
07FFh
0800h
Page 1
On-Chip
Program
Memory
0FFFh
1000h
Page 2
Page 3
17FFh
1800h
1FFFh
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 11
PIC16F7X
2.2
Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP1:RP0
Bank
00
01
10
11
0
1
2
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly, through the File Select Register FSR.
DS30325A-page 12
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 2-3: PIC16F77/76 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
180h
OPTION_REG
181h
Indirect addr.(*)
80h
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr.(*)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
TMR0
PCL
TMR0
PCL
OPTION_REG 81h
PCL
STATUS
FSR
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PMCON1
PCLATH
INTCON
PIE1
PMDATA
PMADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
PMDATH
PMADRH
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
PR2
SSPADD
SSPSTAT
General
Purpose
Register
General
Purpose
Register
RCSTA
TXREG
TXSTA
16 Bytes
16 Bytes
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
ADCON1
1A0h
A0h
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
General
Purpose
Register
80 Bytes
80 Bytes
80 Bytes
1EFh
1F0h
96 Bytes
EFh
F0h
16Fh
170h
accesses
70h - 7Fh
accesses
70h-7Fh
accesses
70h-7Fh
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 13
PIC16F7X
FIGURE 2-4: PIC16F74/73 REGISTER FILE MAP
File
Address
File
Address
File
Address
File
Address
Indirect addr.(*)
Indirect addr.(*)
OPTION_REG
PCL
Indirect addr.(*)
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
Indirect addr.(*)
TMR0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
80h
TMR0
PCL
OPTION_REG 81h
PCL
PCL
STATUS
FSR
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
STATUS
FSR
STATUS
FSR
STATUS
FSR
PORTA
PORTB
PORTC
PORTD(1)
PORTE(1)
PCLATH
INTCON
PIR1
TRISA
TRISB
TRISC
TRISD(1)
TRISE(1)
TRISB
PORTB
PCLATH
INTCON
PCLATH
INTCON
PMCON1
PCLATH
INTCON
PIE1
PMDATA
PMADR
PIR2
PIE2
TMR1L
TMR1H
T1CON
TMR2
PCON
PMDATH
PMADRH
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
PR2
SSPADD
SSPSTAT
RCSTA
TXREG
TXSTA
SPBRG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
ADCON1
1A0h
120h
A0h
General
Purpose
Register
General
Purpose
Register
accesses
20h-7Fh
accesses
A0h - FFh
1EFh
1F0h
96 Bytes
96 Bytes
16Fh
170h
17Fh
1FFh
7Fh
FFh
Bank 3
Bank 1
Bank 2
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
DS30325A-page 14
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
Bank 0
(4)
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
00h
01h
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
(4)
Program Counter's (PC) Least Significant Byte
02h
(4)
STATUS
FSR
IRP
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
03h
(4)
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
04h
05h
06h
07h
PORTA
PORTB
PORTC
PORTD
—
—
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
(5)
08h
(5)
PORTE
PCLATH
INTCON
PIR1
—
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
09h
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
0Ah
(4)
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0Bh
(3)
0Ch
TMR1IF 0000 0000 0000 0000
PSPIF
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR2
—
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1H
T1CON
TMR2
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Timer2 Module’s Register
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
—
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result Register Byte
xxxx xxxx uuuu uuuu
GO/
DONE
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 15
PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
Bank 1
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
80h
OPTION_
REG
81h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
(4)
PCL
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO
Indirect data memory address pointer
PORTA Data Direction Register
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
82h
(4)
STATUS
PD
Z
DC
C
83h
(4)
FSR
84h
85h
86h
87h
TRISA
TRISB
TRISC
TRISD
—
—
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
(5)
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
88h
(5)
TRISE
IBF
—
OBF
—
IBOV
—
PSPMODE
—
PORTE Data Direction Bits
89h
(1,4)
PCLATH
INTCON
Write Buffer for the upper 5 bits of the Program Counter
8Ah
(4)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
8Bh
(3)
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
PIE1
PIE2
PCON
—
ADIE
—
RCIE
—
TXIE
—
SSPIE
—
CCP1IE
TMR2IE
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
PSPIE
—
—
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
Unimplemented
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
PR2
Timer2 Period Register
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
2
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
SSPADD
Synchronous Serial Port (I C mode) Address Register
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
TXSTA
SPBRG
—
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
Baud Rate Generator Register
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
—
Unimplemented
—
Unimplemented
ADCON1
—
—
—
—
—
PCFG2
PCFG1
PCFG0 -----000 ---- -000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
DS30325A-page 16
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
Bank 2
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
0000 0000
0000 0000
100h
101h
TMR0
PCL
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
(4)
Program Counter's (PC) Least Significant Byte
102h
(4)
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
103h
(4)
FSR
—
Indirect Data Memory Address Pointer
Unimplemented
104h
105h
106h
107h
108h
109h
—
—
PORTB
—
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
(1,4)
PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
10Ah
(4)
INTCON
PMDATA
PMADR
GIE
PEIE
T0IE
10Bh
10Ch
10Dh
10Eh
10Fh
Data Register Low Byte
Address Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
PMDATH
PMADRH
—
—
—
—
Data Register High Byte
Address Register High Byte
—
Bank 3
(4)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
180h
OPTION_
REG
181h
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
(4)
PCL
Program Counter's (PC) Least Significant Byte
IRP RP1 RP0 TO
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
182h
(4)
STATUS
FSR
PD
Z
DC
C
183h
(4)
Indirect Data Memory Address Pointer
184h
185h
186h
187h
188h
189h
—
Unimplemented
—
—
TRISB
—
PORTB Data Direction Register
Unimplemented
1111 1111 1111 1111
—
—
—
—
—
—
—
Unimplemented
—
Unimplemented
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
PCLATH
—
—
PEIE
—
—
T0IE
—
---0 0000 ---0 0000
0000 000x 0000 000u
1--- ---0 1--- ---0
18Ah
(4)
INTCON
GIE
INTE
RBIE
T0IF
INTF
RBIF
RD
18Bh
(6)
18Ch
18Dh
18Eh
18Fh
PMCON1
—
—
—
—
—
—
—
—
Unimplemented
—
—
Reserved maintain clear
Reserved maintain clear
0000 0000 0000 0000
0000 0000 0000 0000
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 17
PIC16F7X
2.2.2.1
STATUS Register
For example, CLRF STATUSwill clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu(where u= unchanged).
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, or DC bits from the STATUS register.
For other instructions not affecting any status bits, see
the "Instruction Set Summary."
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in sub-
traction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
IRP
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1= Bank 2, 3 (100h - 1FFh)
0= Bank 0, 1 (00h - FFh)
bit 6-5
RP1:RP0: Register Bank Select bits (used for direct addressing)
11= Bank 3 (180h - 1FFh)
10= Bank 2 (100h - 17Fh)
01= Bank 1 (80h - FFh)
00= Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
bit 3
bit 2
bit 1
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
(for borrow the polarity is reversed)
1= A carry-out from the 4th low order bit of the result occurred
0= No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWFinstructions)
1= A carry-out from the most significant bit of the result occurred
0= No carry-out from the most significant bit of the result occurred
Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30325A-page 18
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.2.2.2
OPTION_REG Register
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
The OPTION_REG register is a readable and writable
register, which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assign-
able register known also as the prescaler), the External
INT Interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
RBPU: PORTB Pull-up Enable bit
1= PORTB pull-ups are disabled
0= PORTB pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of RB0/INT pin
0= Interrupt on falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on RA4/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on RA4/T0CKI pin
0= Increment on low-to-high transition on RA4/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 19
PIC16F7X
2.2.2.3
INTCON Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
GIE: Global Interrupt Enable bit
1= Enables all un-masked interrupts
0= Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1= Enables all un-masked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1= Enables the TMR0 interrupt
0= Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1= Enables the RB0/INT external interrupt
0= Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1= Enables the RB port change interrupt
0= Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1= The RB0/INT external interrupt occurred (must be cleared in software)
0= The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1= At least one of the RB7:RB4 pins changed state (must be cleared in software)
0= None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325A-page 20
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.2.2.4
PIE1 Register
Note: Bit PEIE (INTCON<6>) must be set to
The PIE1 register contains the individual enable bits for
the peripheral interrupts.
enable any peripheral interrupt.
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0
PSPIE(1)
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
R/W-0
R/W-0
TMR1IE
bit 0
CCP1IE
TMR2IE
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit
1= Enables the PSP read/write interrupt
0= Disables the PSP read/write interrupt
ADIE: A/D Converter Interrupt Enable bit
1= Enables the A/D converter interrupt
0= Disables the A/D converter interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1= Enables the SSP interrupt
0= Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 21
PIC16F7X
2.2.2.5
PIR1 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate interrupt
bits are clear prior to enabling an interrupt.
The PIR1 register contains the individual flag bits for
the peripheral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0
R/W-0
ADIF
R-0
R-0
R/W-0
SSPIF
R/W-0
R/W-0
R/W-0
(1)
PSPIF
bit 7
RCIF
TXIF
CCP1IF
TMR2IF
TMR1IF
bit 0
(1)
bit 7
bit 6
bit 5
bit 4
bit 3
PSPIF : Parallel Slave Port Read/Write Interrupt Flag bit
1= A read or a write operation has taken place (must be cleared in software)
0= No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1= An A/D conversion completed
0= The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1= The USART receive buffer is full
0= The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1= The USART transmit buffer is empty
0= The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
1= The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place.
2
I C Slave
A transmission/reception has taken place.
2
I C Master
A transmission/reception has taken place.
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system).
0= No SSP interrupt condition has occurred.
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
bit 0
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1= TMR2 to PR2 match occurred (must be cleared in software)
0= No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1= TMR1 register overflowed (must be cleared in software)
0= TMR1 register did not overflow
Note 1: PSPIF is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325A-page 22
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bits for
the CCP2 peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IE
bit 0
—
—
—
—
—
—
—
bit 7
bit 7-1
bit 0
Unimplemented: Read as ’0’
CCP2IE: CCP2 Interrupt Enable bit
1= Enables the CCP2 interrupt
0= Disables the CCP2 interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 23
PIC16F7X
.
2.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
The PIR2 register contains the flag bits for the CCP2
interrupt.
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
CCP2IF
bit 0
—
—
—
—
—
—
—
bit 7
bit 7-1
bit 0
Unimplemented: Read as '0'
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1= A TMR1 register capture occurred (must be cleared in software)
0= No TMR1 register capture occurred
Compare Mode
1= A TMR1 register compare match occurred (must be cleared in software)
0= No TMR1 register compare match occurred
PWM Mode
Unused
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325A-page 24
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.2.2.8
PCON Register
Note: BOR is unknown on POR. It must be set by
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurred. The BOR status
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clear-
ing the BODEN bit in the configuration
word).
The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR Reset.
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
POR
R/W-1
BOR
—
—
—
—
—
—
bit 7
bit 0
bit 7-2
bit 1
Unimplemented: Read as '0'
POR: Power-on Reset Status bit
1= No Power-on Reset occurred
0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1= No Brown-out Reset occurred
0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 25
PIC16F7X
2.3
PCL and PCLATH
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the fig-
ure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the fig-
ure shows how the PC is loaded during a CALLor GOTO
instruction (PCLATH<4:3> → PCH).
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an interrupt
address.
2.4
Program Memory Paging
PIC16F7X devices are capable of addressing a contin-
uous 8K word block of program memory. The CALLand
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction, the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALLor GOTOinstruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
Instruction with
PCL as
PC
Destination
8
PCLATH<4:0>
PCLATH
5
ALU
PCH
12 11 10
PCL
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLSor GOTOS.
8
7
0
GOTO,CALL
PC
PCLATH<4:3>
PCLATH
11
2
Opcode <10:0>
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that PCLATH is saved and restored by the Interrupt
Service Routine (if interrupts are used).
2.3.1
COMPUTED GOTO
EXAMPLE 2-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
A computed GOTOis accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3
CALLSUB1_P1
;Select page 1 (800h-FFFh)
;Call subroutine in
application note, “Implementing
a Table Read"
(AN556).
:
;page 1 (800h-FFFh)
:
2.3.2
STACK
ORG 0x900
;page 1 (800h-FFFh)
SUB1_P1
The PIC16F7X family has an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
:
:
:
;called subroutine
;page 1 (800h-FFFh)
RETURN
;return to Call subroutine
;in page 0 (000h-7FFh)
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30325A-page 26
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
2.5
Indirect Addressing, INDF and FSR
Registers
EXAMPLE 2-2: INDIRECT ADDRESSING
movlw
movwf
clrf
incf
btfss
goto
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
NEXT
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly results in a no-operation (although status bits
may be affected). An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the IRP bit
(STATUS<7>), as shown in Figure 2-6.
CONTINUE
:
;yes continue
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
from opcode
7
RP1:RP0
6
0
0
IRP
FSR register
bank select
location select
bank select
location select
00
01
80h
10
100h
11
00h
180h
Data
Memory
(1)
7Fh
Bank 0
FFh
Bank 1
17Fh
Bank 2
1FFh
Bank 3
Note 1: For register file map detail see Figure 2-3.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 27
PIC16F7X
NOTES:
DS30325A-page 28
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 3-1: BLOCK DIAGRAM OF
3.0
I/O PORTS
RA3:RA0 AND RA5 PINS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
VDD
WR
Additional information on I/O ports may be found in the
PICmicro™
Port
Q
CK
Mid-Range
Reference
Manual,
P
(DS33023).
Data Latch
D
3.1
PORTA and the TRISA Register
I/O pin(1)
N
Q
PORTA is a 6-bit wide, bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
WR
TRIS
VSS
Q
CK
Analog
Input
Mode
TRIS Latch
TTL
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Input
Buffer
Q
D
EN
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
Other PORTA pins are multiplexed with analog inputs
and analog VREF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
Data
Bus
figured as analog inputs and read as '0'.
D
Q
Q
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set, when using them as analog inputs.
WR
PORT
CK
I/O pin(1)
N
Data Latch
D
Q
VSS
EXAMPLE 3-1: INITIALIZING PORTA
WR
TRIS
Schmitt
Trigger
Input
Q
CK
BCF
BCF
CLRF
STATUS, RP0
STATUS, RP1
PORTA
;
; Bank0
TRIS Latch
Buffer
; Initialize PORTA by
; clearing output
; data latches
; Select Bank 1
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
RD TRIS
BSF
STATUS, RP0
0x06
ADCON1
0xCF
MOVLW
MOVWF
MOVLW
Q
D
EN
RD PORT
MOVWF
TRISA
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 29
PIC16F7X
TABLE 3-1:
Name
PORTA FUNCTIONS
Bit#
Buffer
Function
RA0/AN0
bit0
bit1
bit2
bit3
bit4
bit5
TTL
TTL
TTL
TTL
ST
Input/output or analog input.
Input/output or analog input.
Input/output or analog input.
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
Input/output or analog input or VREF.
Input/output or external clock input for Timer0. Output is open drain type.
Input/output or slave select input for synchronous serial port or analog input.
TTL
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 3-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Value on: Value on all
Address Name
Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
05h
85h
9Fh
PORTA
TRISA
—
—
—
—
—
—
RA5
RA4
RA3
RA2
RA1
RA0
PORTA Data Direction Register
PCFG2 PCFG1 PCFG0
ADCON1
—
—
—
Legend: x= unknown, u= unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
DS30325A-page 30
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
3.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are dis-
abled on a Power-on Reset.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
This interrupt on mismatch feature, together with soft-
ware configureable pull-ups on these four pins, allow
easy interface to a keypad and make it possible for
wake-up on key depression. Refer to the Embedded
Control Handbook, “Implementing Wake-Up on Key
Stroke” (AN552).
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
VDD
RBPU(2)
Weak
P
Pull-up
Data Latch
Data Bus
RB0/INT is an external interrupt input pin and is config-
ured using the INTEDG bit (OPTION_REG<6>).
D
Q
I/O
WR Port
pin(1)
CK
TRIS Latch
RB0/INT is discussed in detail in Section 12.10.1.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
D
Q
TTL
Input
Buffer
WR TRIS
CK
VDD
RBPU(2)
Weak
P
Pull-up
RD TRIS
RD Port
Data Latch
Data Bus
D
Q
Q
D
I/O
pin(1)
WR Port
CK
TRIS Latch
EN
D
Q
RB0/INT
WR TRIS
TTL
Input
Buffer
Schmitt Trigger
Buffer
CK
RD Port
ST
Buffer
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
RD TRIS
RD Port
Latch
and clear the RBPU bit (OPTION_REG<7>).
Q
Q
D
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
EN
Q1
Set RBIF
D
From other
RB7:RB4 pins
RD Port
Q3
EN
RB7:RB6 in Serial Programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU bit (OPTION_REG<7>).
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 31
PIC16F7X
TABLE 3-3:
Name
PORTB FUNCTIONS
Bit#
Buffer
Function
RB0/INT
bit0
TTL/ST(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
RB6
RB7
bit5
bit6
bit7
TTL
Input/output pin (with interrupt-on-change). Internal software programmable
weak pull-up.
TTL/ST(2)
TTL/ST(2)
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming clock.
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 3-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
other
RESETS
06h, 106h
86h, 186h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
PS2
RB1
PS1
RB0 xxxx xxxx uuuu uuuu
TRISB
PORTB Data Direction Register
RBPU INTEDG T0CS T0SE PSA
1111 1111 1111 1111
81h, 181h
OPTION_REG
PS0 1111 1111 1111 1111
Legend: x= unknown, u= unchanged. Shaded cells are not used by PORTB.
DS30325A-page 32
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
3.3
PORTC and the TRISC Register
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
Port/Peripheral Select(2)
Peripheral Data Out
VDD
0
Data Bus
D
Q
Q
P
WR
1
Port
CK
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
Data Latch
I/O
pin(1)
D
Q
Q
WR
TRIS
CK
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
Q
D
EN
RD
Port
Peripheral Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port data
and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
TABLE 3-5:
Name
PORTC FUNCTIONS
Bit# Buffer Type
Function
RC0/T1OSO/T1CKI bit0
ST
ST
Input/output port pin or Timer1 oscillator output/Timer1 clock input.
RC1/T1OSI/CCP2
bit1
Input/output port pin or Timer1 oscillator input or Capture2 input/
Compare2 output/PWM2 output.
RC2/CCP1
bit2
bit3
ST
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output.
RC3 can also be the synchronous serial clock for both SPI and I2C
RC3/SCK/SCL
modes.
RC4/SDI/SDA
RC5/SDO
bit4
bit5
bit6
ST
ST
ST
RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2C mode).
Input/output port pin or Synchronous Serial Port data output.
RC6/TX/CK
Input/output port pin or USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive or
Synchronous Data.
Legend: ST = Schmitt Trigger input
TABLE 3-6:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on:
POR,
Value on
all other
RESETS
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
07h
87h
PORTC RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
TRISC PORTC Data Direction Register
Legend: x= unknown, u= unchanged
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 33
PIC16F7X
3.4
PORTD and TRISD Registers
FIGURE 3-6: PORTD BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F73 or
PIC16F76.
Data
Bus
D
Q
PORTD is an 8-bit port with Schmitt Trigger input buff-
ers. Each pin is individually configureable as an input or
output.
WR
Port
I/O pin(1)
CK
Data Latch
PORTD can be configured as an 8-bit wide micropro-
cessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
D
Q
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Q
D
EN
RD Port
Note 1: I/O pins have protection diodes to Vdd and Vss.
TABLE 3-7:
PORTD FUNCTIONS
Name
Bit#
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
Buffer Type
Function
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
ST/TTL(1)
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
Input/output port pin or parallel slave port bit0
Input/output port pin or parallel slave port bit1
Input/output port pin or parallel slave port bit2
Input/output port pin or parallel slave port bit3
Input/output port pin or parallel slave port bit4
Input/output port pin or parallel slave port bit5
Input/output port pin or parallel slave port bit6
Input/output port pin or parallel slave port bit7
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.
TABLE 3-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
RD3
—
Bit 2
Bit 1
Bit 0
08h
88h
89h
PORTD
TRISD
TRISE
RD7
RD6
RD5
RD4
RD2
RD1
RD0
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
0000 -111 0000 -111
PORTD Data Direction Register
IBF OBF IBOV PSPMODE
PORTE Data Direction bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTD.
DS30325A-page 34
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
3.5
PORTE and TRISE Register
FIGURE 3-7: PORTE BLOCK DIAGRAM (IN
I/O PORT MODE)
This section is not applicable to the PIC16F73 or
PIC16F76.
Data
Bus
D
Q
PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6
and RE2/CS/AN7, which are individually configureable
as inputs or outputs. These pins have Schmitt Trigger
input buffers.
WR
PORT
I/O pin(1)
CK
Data Latch
D
Q
I/O PORTE becomes control inputs for the micropro-
cessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). Ensure ADCON1 is configured for digital I/O. In
this mode, the input buffers are TTL.
WR
TRIS
Schmitt
Trigger
Input
CK
TRIS Latch
Buffer
RD TRIS
Register 3-1 shows the TRISE register, which also con-
trols the parallel slave port operation.
Q
D
PORTE pins are multiplexed with analog inputs. When
selected as an analog input, these pins will read as ’0’s.
EN
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
RD PORT
Note 1: I/O pins have protection diodes to Vdd and Vss.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as ‘0’.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 35
PIC16F7X
REGISTER 3-1: TRISE REGISTER (ADDRESS 89h)
R-0
IBF
R-0
R/W-0
IBOV
R/W-0
U-0
R/W-1
bit2
R/W-1
bit1
R/W-1
bit0
OBF
PSPMODE
—
bit 7
bit 0
bit 7
Parallel Slave Port Status/Control Bits
IBF: Input Buffer Full Status bit
1= A word has been received and is waiting to be read by the CPU
0= No word has been received
bit 6
bit 5
OBF: Output Buffer Full Status bit
1= The output buffer still holds a previously written word
0= The output buffer has been read
IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)
1= A write occurred when a previously input word has not been read
(must be cleared in software)
0= No overflow occurred
bit 4
PSPMODE: Parallel Slave Port Mode Select bit
1= Parallel Slave Port mode
0= General Purpose I/O mode
bit 3
bit 2
Unimplemented: Read as '0'
PORTE Data Direction Bits
Bit2: Direction Control bit for pin RE2/CS/AN7
1= Input
0= Output
bit 1
bit 0
Bit1: Direction Control bit for pin RE1/WR/AN6
1= Input
0= Output
Bit0: Direction Control bit for pin RE0/RD/AN5
1= Input
0= Output
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325A-page 36
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 3-9:
Name
PORTE FUNCTIONS
Bit#
Buffer Type
Function
ST/TTL(1)
Input/output port pin or read control input in Parallel Slave Port mode or
analog input:
RE0/RD/AN5
bit0
RD
1= Idle
0= Read operation. Contents of PORTD register output to PORTD I/O
pins (if chip selected).
Input/output port pin or write control input in Parallel Slave Port mode
or analog input:
WR
1= Idle
RE1/WR/AN6
RE2/CS/AN7
bit1
bit2
ST/TTL(1)
0= Write operation. Value of PORTD I/O pins latched into PORTD
register (if chip selected).
ST/TTL(1)
Input/output port pin or chip select control input in Parallel Slave Port
mode or analog input:
CS
1= Device is not selected
0= Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on:
POR,
Value on all
Addr
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
09h
89h
9Fh
PORTE
TRISE
—
IBF
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
0000 -111
---- -uuu
0000 -111
---- -000
OBF IBOV PSPMODE
PORTE Data Direction Bits
ADCON1
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by PORTE.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 37
PIC16F7X
3.6
Parallel Slave Port
FIGURE 3-8: PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL SLAVE
PORT)
The Parallel Slave Port is not implemented on the
PIC16F73 or PIC16F76.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In Slave mode, it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
Data Bus
D
Q
WR
Port
RDx
pin
CK
TTL
Q
D
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG3:PCFG0 (ADCON1<3:0>) must be
set to configure pins RE2:RE0 as digital I/O.
RD
Port
EN
One bit of PORTD
Set Interrupt Flag
PSPIF (PIR1<7>)
There are actually two 8-bit latches. One for data out-
put and one for data input. The user writes 8-bit data to
the PORTD data latch and reads data from the port pin
latch (note that they have the same address). In this
mode, the TRISD register is ignored, since the external
device is controlling the direction of data flow.
Read
RD
CS
WR
TTL
Chip Select
TTL
Write
TTL
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), the Input Buffer Full
(IBF) status flag bit (TRISE<7>) is set on the Q4 clock
cycle, following the next Q2 cycle, to signal the write is
complete (Figure 3-9). The interrupt flag bit PSPIF
(PIR1<7>) is also set on the same Q4 clock cycle. IBF
can only be cleared by reading the PORTD input latch.
The Input Buffer Overflow (IBOV) status flag bit
(TRISE<5>) is set if a second write to the PSP is
attempted when the previous byte has not been read
out of the buffer.
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full
(OBF) status flag bit (TRISE<6>) is cleared immedi-
ately (Figure 3-10) indicating that the PORTD latch is
waiting to be read by the external bus. When either the
CS or RD pin becomes high (level triggered), the inter-
rupt flag bit PSPIF is set on the Q4 clock cycle, follow-
ing the next Q2 cycle, indicating that the read is
complete. OBF remains low until data is written to
PORTD by the user firmware.
When not in PSP mode, the IBF and OBF bits are held
clear. However, if flag bit IBOV was previously set, it
must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
DS30325A-page 38
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Value on:
POR,
Value on all
other
Address
Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
08h
09h
89h
0Ch
PORTD Port data latch when written: Port pins when read
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
0000 -111 0000 -111
PORTE
TRISE
PIR1
—
—
—
—
—
—
RE2
RE1
RE0
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
(1)
(1)
ADIF RCIF
ADIE RCIE
TXIF
TXIE
—
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PSPIF
8Ch
9Fh
PIE1
PSPIE
ADCON1
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 39
PIC16F7X
NOTES:
DS30325A-page 40
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
When interfacing to the program memory block, the
PMDATH:PMDATA registers form a two byte word,
which holds the 14-bit data for reads. The
PMADRH:PMADR registers form a two byte word,
which holds the 13-bit address of the FLASH location
being accessed. These devices can have up to 8K
words of program FLASH, with an address range from
0h to 3FFFh. The unused upper bits in both the
PMDATH and PMADRH registers are not implemented
and read as “0’s”.
4.0
READING PROGRAM MEMORY
The FLASH Program Memory is readable during nor-
mal operation over the entire VDD range. It is indirectly
addressed through Special Function Registers (SFR).
Up to 14-bit numbers can be stored in memory for use
as calibration parameters, serial numbers, packed 7-bit
ASCII, etc. Executing a program memory location con-
taining data that forms an invalid instruction results in
a NOP.
There are five SFRs used to read the program and
memory. These registers are:
4.1
PMADR
• PMCON1
• PMDATA
• PMDATH
• PMADR
The address registers can address up to a maximum of
8K words of program FLASH.
When selecting a program address value, the MSByte
of the address is written to the PMADRH register and
the LSByte is written to the PMADR register. The upper
MSbits of PMADRH must always be clear.
• PMADRH
The program memory allows word reads. Program
memory access allows for checksum calculation and
reading calibration tables.
4.2
PMCON1 Register
PMCON1 is the control register for memory accesses.
The control bit RD initiates read operations. This bit
cannot be cleared, only set, in software. It is cleared in
hardware at the completion of the read operation.
REGISTER 4-1: PMCON1 REGISTER (ADDRESS 18Ch)
R-1
U-0
U-0
U-0
U-x
U-0
U-0
R/S-0
RD
—
—
—
—
—
—
—
bit 7
bit 0
bit 7
Reserved: Read as ‘1’
bit 6-1
bit 0
Unimplemented: Read as '0'
RD: Read Control bit
1= Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared)
in software.
0= Does not initiate a FLASH read
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 41
PIC16F7X
data is available in the PMDATA and PMDATH regis-
ters after the second NOPinstruction. Therefore, it can
be read as two bytes in the following instructions. The
PMDATA and PMDATH registers will hold this value
until another read operation.
4.3
Reading the FLASH Program Memory
A program memory location may be read by writing two
bytes of the address to the PMADR and PMADRH reg-
isters and then setting control bit RD (PMCON1<0>).
Once the read control bit is set, the microcontroller will
use the next two instruction cycles to read the data. The
EXAMPLE 4-1: FLASH PROGRAM READ
BSF
STATUS, RP1
STATUS, RP0
ADDRH, W
PMADRH
;
BCF
; Bank 2
;
MOVF
MOVWF
MOVF
MOVWF
BSF
; MSByte of Program Address to read
ADDRL, W
PMADR
;
; LSByte of Program Address to read
; Bank 3
STATUS, RP0
PMCON1, RD
Required
Sequence
BSF
; EEPROM Read
NOP
NOP
; memory is read in the next two cycles after BSF PMCON1,RD
;
BCF
STATUS, RP0
; Bank 2
MOVF
MOVF
PMDATA, W
PMDATH, W
; W = LSByte of Program PMDATA
; W = MSByte of Program PMDATA
DS30325A-page 42
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PIC16F7X
4.4
Operation During Code Protect
FLASH program memory has its own code protect
mechanism. External Read and Write operations are
disabled if this mechanism is enabled.
The microcontroller can read and execute instructions
out of the internal FLASH program memory, regardless
of the state of the code protect configuration bits.
TABLE 4-1:
REGISTERS ASSOCIATED WITH PROGRAM FLASH
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
10Dh
10Fh
10Ch
10Eh
18Ch
PMADR
Address Register Low Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1--- ---0 1--- ---0
PMADRH
—
—
—
Address Register High Byte
PMDATA Data Register Low Byte
PMDATH
PMCON1
—
—
—
Data Register High Byte
(1)
—
—
—
—
—
—
RD
Legend: x= unknown, u= unchanged, r = reserved, -= unimplemented read as ’0’. Shaded cells are not used during FLASH access.
Note 1: This bit always reads as a ‘1’.
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NOTES:
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Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In Counter mode, Timer0 will
increment, either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the ris-
ing edge. Restrictions on the external clock input are
discussed in detail in Section 5.2.
5.0
TIMER0 MODULE
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The pres-
caler is not readable or writable. Section 5.3 details the
operation of the prescaler.
Figure 5-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
5.1
Timer0 Interrupt
Additional information on the Timer0 module is avail-
able in the PICmicro™ Mid-Range MCU Family Refer-
ence Manual (DS33023).
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interrupt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module Interrupt Ser-
vice Routine, before re-enabling this interrupt. The
TMR0 interrupt cannot awaken the processor from
SLEEP, since the timer is shut off during SLEEP.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In Timer mode, the Timer0 mod-
ule will increment every instruction cycle (without pres-
caler). If the TMR0 register is written, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
8
CLKOUT (= FOSC/4)
M
U
X
1
0
0
1
M
U
X
RA4/T0CKI
pin
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
Set Flag bit T0IF
on Overflow
PSA
PRESCALER
0
1
8-bit Prescaler
M
U
X
Watchdog
Timer
8
8 - to - 1MUX
PS2:PS0
PSA
1
0
WDT Enable bit
M U X
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
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PIC16F7X
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 5-1).
5.2
Using Timer0 with an External Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF1, MOVWF1,
BSF1,x....etc.) will clear the prescaler. When assigned
to WDT, a CLRWDT instruction will clear the prescaler
along with the Watchdog Timer. The prescaler is not
readable or writable.
5.3
Prescaler
Note: Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
REGISTER 5-1: OPTION_REG REGISTER
R/W-1
RBPU
R/W-1
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
R/W-1
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
RBPU
INTEDG
T0CS: TMR0 Clock Source Select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
Note: To avoid an unintended device RESET, the instruction sequence shown in the
PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed
when changing the prescaler assignment from Timer0 to the WDT. This sequence must
be followed even if the WDT is disabled.
DS30325A-page 46
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PIC16F7X
TABLE 5-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on: Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
01h,101h
TMR0
INTCON
OPTION_REG RBPU INTEDG T0CS
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
GIE PEIE T0IE
INTE
T0SE
RBIE
PSA
T0IF
PS2
INTF
PS1
RBIF 0000 000x 0000 000u
PS0 1111 1111 1111 1111
81h,181h
Legend: x= unknown, u= unchanged, -= unimplemented locations read as '0'. Shaded cells are not used by Timer0.
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PIC16F7X
NOTES:
DS30325A-page 48
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In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
6.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by either of the two CCP
modules (Section 8.0). Register 6-1 shows the Timer1
Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs. That is, the TRISC<1:0> value is
ignored and these pins read as ‘0’.
Timer1 can operate in one of two modes:
• As a timer
• As a counter
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
REGISTER 6-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as ‘0’
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11= 1:8 Prescale value
10= 1:4 Prescale value
01= 1:2 Prescale value
00= 1:1 Prescale value
bit 3
bit 2
T1OSCEN: Timer1 Oscillator Enable Control bit
1= Oscillator is enabled
0= Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1= Do not synchronize external clock input
0= Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
bit 0
TMR1CS: Timer1 Clock Source Select bit
1= External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0= Internal clock (FOSC/4)
TMR1ON: Timer1 On bit
1= Enables Timer1
0= Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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PIC16F7X
6.1
Timer1 Operation in Timer Mode
6.2
Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 6-1: TIMER1 INCREMENTING EDGE
T1CKI
(Default high)
T1CKI
(Default low)
Note: Arrows indicate counter increments.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The pres-
caler stage is an asynchronous ripple counter.
6.3
Timer1 Operation in Synchronized
Counter Mode
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI/CCP2, when bit
T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when
bit T1OSCEN is cleared.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The
prescaler however, will continue to increment.
FIGURE 6-2: TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
Synchronized
0
TMR1
Clock Input
TMR1L
TMR1H
T1OSC
1
TMR1ON
On/Off
T1SYNC
(2)
RC0/T1OSO/T1CKI
1
Synchronize
det
Prescaler
1, 2, 4, 8
T1OSCEN
Enable
Oscillator
Fosc/4
Internal
Clock
0
(1)
(2)
RC1/T1OSI/CCP2
2
Q Clock
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.
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6.4
Timer1 Operation in Asynchronous
Counter Mode
TABLE 6-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in soft-
ware are needed to read/write the timer (Section 6.4.1).
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
In Asynchronous Counter mode, Timer1 can not be
used as a time base for capture or compare operations.
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
200 kHz
Epson C-2 100.00 KC-P
STD XTL 200.000 kHz
± 20 PPM
± 20 PPM
6.4.1
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
Note 1: Higher capacitance increases the stability of
the oscillator, but also increases the start-up
time.
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will guarantee a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems since
the timer may overflow between the reads.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropri-
ate values of external components.
6.6
Resetting Timer1 using a CCP Trigger
Output
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write conten-
tion may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
If the CCP1 or CCP2 module is configured in Compare
mode to generate “special event trigger”
(CCP1M3:CCP1M0 = 1011), this signal will reset
a
Reading the 16-bit value requires some care. Exam-
ples 12-2 and 12-3 in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023) show how to
read and write Timer1 when it is running in Asynchro-
nous mode.
Timer1.
Note: The special event triggers from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode, to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
6.5
Timer1 Oscillator
A crystal oscillator circuit is built-in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscilla-
tor is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for use with a 32 kHz crystal. Table 6-1 shows the
capacitor selection for the Timer1 oscillator.
In the event that a write to Timer1 coincides with a spe-
cial event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL regis-
ter pair effectively becomes the period register for
Timer1.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
6.7
Resetting of Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 and
CCP2 special event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
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PIC16F7X
TABLE 6-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
8Ch
0Eh
0Fh
10h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CON
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325A-page 52
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PIC16F7X
7.1
Timer2 Prescaler and Postscaler
7.0
TIMER2 MODULE
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time base for the
PWM mode of the CCP module(s). The TMR2 register
is readable and writable, and is cleared on any device
RESET.
The prescaler and postscaler counters are cleared
when any of the following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device RESET (POR, MCLR Reset, WDT
Reset or BOR)
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
TMR2 is not cleared when T2CON is written.
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
SSP module, which optionally uses it to generate shift
clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF, (PIR1<1>)).
FIGURE 7-1: TIMER2 BLOCK DIAGRAM
Sets Flag
TMR2
Output(1)
bit TMR2IF
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
Reset
Prescaler
1:1, 1:4, 1:16
TMR2 reg
FOSC/4
Register 7-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16
2
Comparator
EQ
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
T2CKPS1:
T2CKPS0
4
PR2 reg
T2OUTPS3:
T2OUTPS0
Note 1: TMR2 register output can be software selected by the
SSP module as a baud clock.
REGISTER 7-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 0
bit 7
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000= 1:1 Postscale
0001= 1:2 Postscale
0010= 1:3 Postscale
•
•
•
1111= 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1= Timer2 is on
0= Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00= Prescaler is 1
01= Prescaler is 4
1x= Prescaler is 16
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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PIC16F7X
TABLE 7-1:
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000 000x 0000 000u
0Bh,8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
10Bh,18Bh
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
-000 0000 -000 0000
1111 1111 1111 1111
0Ch
8Ch
11h
12h
PIR1
PSPIF(1)
PSPIE(1)
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
PIE1
TMR2
T2CON
PR2
Timer2 Module’s Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
Timer2 Period Register
—
92h
Legend:
x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the Timer2 module.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325A-page 54
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PIC16F7X
8.2
CCP2 Module
8.0
CAPTURE/COMPARE/PWM
MODULES
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP2CON register controls
the operation of CCP2. The special event trigger is
generated by a compare match and will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
Each Capture/Compare/PWM (CCP) module contains
a 16-bit register which can operate as a:
• 16-bit Capture register
• 16-bit Compare register
• PWM Master/Slave Duty Cycle register
Both the CCP1 and CCP2 modules are identical in
operation, with the exception being the operation of the
special event trigger. Table 8-1 and Table 8-2 show the
resources and interactions of the CCP module(s). In
the following sections, the operation of a CCP module
is described with respect to CCP1. CCP2 operates the
same as CCP1, except where noted.
Additional information on CCP modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023) and in Application Note 594, “Using
the CCP Modules” (DS00594).
TABLE 8-1:
CCP MODE - TIMER
RESOURCES REQUIRED
CCP Mode
Timer Resource
8.1
CCP1 Module
Capture
Compare
PWM
Timer1
Timer1
Timer2
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match and will reset Timer1.
TABLE 8-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
Capture
Compare
Compare
PWM
Same TMR1 time base.
The compare should be configured for the special event trigger, which clears TMR1.
The compare(s) should be configured for the special event trigger, which clears TMR1.
The PWMs will have the same frequency and update rate (TMR2 interrupt).
PWM
Capture
Compare
None.
None.
PWM
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PIC16F7X
REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS: 17h/1Dh)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCPxX
CCPxY
CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 0
bit 7
bit 7-6
bit 5-4
Unimplemented: Read as '0'
CCPxX:CCPxY: PWM Least Significant bits
Capture Mode:
Unused
Compare Mode:
Unused
PWM Mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCPxM3:CCPxM0: CCPx Mode Select bits
0000= Capture/Compare/PWM disabled (resets CCPx module)
0100= Capture mode, every falling edge
0101= Capture mode, every rising edge
0110= Capture mode, every 4th rising edge
0111= Capture mode, every 16th rising edge
1000= Compare mode, set output on match (CCPxIF bit is set)
1001= Compare mode, clear output on match (CCPxIF bit is set)
1010= Compare mode, generate software interrupt on match (CCPxIF bit is set,
CCPx pin is unaffected)
1011= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);
CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion
(if A/D module is enabled)
11xx= PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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8.3.2
TIMER1 MODE SELECTION
8.3
Capture Mode
Timer1 must be running in Timer mode or Synchro-
nized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1. An event is defined as one of the fol-
lowing and is configured by CCPxCON<3:0>:
• Every falling edge
• Every rising edge
8.3.3
SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF following any such
change in operating mode.
• Every 4th rising edge
• Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the inter-
rupt request flag bit CCP1IF (PIR1<2>) is set. The
interrupt flag must be cleared in software. If another
capture occurs before the value in register CCPR1 is
read, the old captured value is overwritten by the new
captured value.
8.3.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. Any RESET will clear
the prescaler counter.
8.3.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be config-
ured as an input by setting the TRISC<2> bit.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 8-1 shows the recom-
mended method for switching between capture pres-
calers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
Note: If the RC2/CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
FIGURE 8-1: CAPTURE MODE OPERATION
BLOCK DIAGRAM
EXAMPLE 8-1: CHANGING BETWEEN
CAPTURE PRESCALERS
Set Flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
CLRF
CCP1CON
;Turn CCP module off
RC2/CCP1
Pin
MOVLW
NEW_CAPT_PS ;Load the W reg with
; the new prescaler
CCPR1H
CCPR1L
TMR1L
; move value and CCP ON
Capture
Enable
and
edge detect
MOVWF
CCP1CON
;Load CCP1CON with this
; value
TMR1H
CCP1CON<3:0>
Q’s
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PIC16F7X
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
8.4
Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: The special event trigger from the CCP1
and CCP2 modules will not set interrupt
flag bit TMR1IF (PIR1<0>).
• Driven high
• Driven low
8.5
PWM Mode (PWM)
• Remains unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
In Pulse Width Modulation mode, the CCPx pin pro-
duces up to a 10-bit resolution PWM output. Since the
CCP1 pin is multiplexed with the PORTC data latch, the
TRISC<2> bit must be cleared to make the CCP1 pin
an output.
FIGURE 8-2: COMPARE MODE OPERATION
BLOCK DIAGRAM
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
Set Flag bit CCP1IF
(PIR1<2>)
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.5.3.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
Match
RC2/CCP1
Pin
FIGURE 8-3: SIMPLIFIED PWM BLOCK
DIAGRAM
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
8.4.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
CCPR1H (Slave)
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC
I/O data latch.
Q
R
S
Comparator
RC2/CCP1
(Note 1)
TMR2
8.4.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
8.4.3
SOFTWARE INTERRUPT MODE
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time base.
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set causing
a CCP interrupt (if enabled).
8.4.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
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PIC16F7X
A PWM output (Figure 8-4) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
8.5.2
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
FIGURE 8-4: PWM OUTPUT
TMR2
RESET
TMR2
RESET
Period
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
TMR2 = PR2
8.5.1
PWM PERIOD
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
Maximum PWM resolution (bits) for a given PWM
frequency:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
FOSC
log( )
FPWM
PWM frequency is defined as 1 / [PWM period].
Resolution
bits
=
log(2)
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
Note: If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
8.5.3
SET-UP FOR PWM OPERATION
The following steps should be taken when configuring
the CCP module for PWM operation:
Note: The Timer2 postscaler (see Section 8.3) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
1. Set the PWM period by writing to the PR2 register.
2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
3. Make the CCP1 pin an output by clearing the
TRISC<2> bit.
4. Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
5. Configure the CCP1 module for PWM operation.
TABLE 8-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
Timer Prescale (1, 4, 16)
PR2 Value
16
0xFF
10
4
1
1
0x3F
8
1
0x1F
7
1
0xFF
10
0xFF
10
0x17
5.5
Maximum Resolution (bits)
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PIC16F7X
TABLE 8-4:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Ch
0Dh
8Ch
8Dh
87h
0Eh
0Fh
10h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF(1) ADIF
RCIF
—
TXIF
—
SSPIF
—
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR2
—
—
—
—
PIE1
PSPIE(1) ADIE
RCIE
—
TXIE
—
SSPIE
—
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TRISC
TMR1L
TMR1H
T1CON
PORTC Data Direction Register
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.
TABLE 8-5:
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
0Dh
8Ch
8Dh
87h
11h
92h
12h
15h
16h
17h
1Bh
1Ch
1Dh
PIR1
PSPIF(1)
—
ADIF
—
RCIF
—
TXIF
—
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
PIR2
—
—
—
PIE1
PSPIE(1)
ADIE
—
RCIE
—
TXIE
—
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2
—
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
TRISC
TMR2
PR2
PORTC Data Direction Register
Timer2 module’s register
Timer2 module’s period register
T2CON
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
CCPR1L Capture/Compare/PWM register1 (LSB)
CCPR1H Capture/Compare/PWM register1 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1CON
—
—
CCP1X
CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
CCPR2L Capture/Compare/PWM register2 (LSB)
CCPR2H Capture/Compare/PWM register2 (MSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by PWM and Timer2.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325A-page 60
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PIC16F7X
9.2
SPI Mode
9.0
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
This section contains register definitions and opera-
tional characteristics of the SPI module. Additional
information on the SPI module can be found in the
PICmicro™ Mid-Range MCU Family Reference Man-
ual (DS33023A).
9.1
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other periph-
eral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, dis-
play drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To accom-
plish communication, typically three pins are used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional informa-
tion on the SSP module can be found in the PICmicro™
Additionally, a fourth pin may be used when in a Slave
mode of operation:
Mid-Range
(DS33023).
MCU
Family
Reference Manual
• Slave Select (SS) RA5/SS/AN4
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the fol-
lowing to be specified:
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment.”
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
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REGISTER 9-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
SMP
R/W-0
CKE
R-0
D/A
R-0
P
R-0
S
R-0
R-0
UA
R-0
BF
R/W
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase
SPI Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time (Microwire®)
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode
I2C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3, and Figure 9-4)
SPI mode:
CKP = 0
1= Data transmitted on rising edge of SCK (Microwire® alternate)
0= Data transmitted on falling edge of SCK
CKP = 1
1= Data transmitted on falling edge of SCK (Microwire® default)
0= Data transmitted on rising edge of SCK
I2C mode:
This bit must be maintained clear
bit 5
bit 4
D/A: Data/Address bit (I2C mode only)
1= Indicates that the last byte received or transmitted was data
0= Indicates that the last byte received or transmitted was address
P: STOP bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the START bit is detected last.
SSPEN is cleared.
1= Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0= STOP bit was not detected last
bit 3
bit 2
S: START bit (I2C mode only)
This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last.
SSPEN is cleared.
1= Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0= START bit was not detected last
R/W: Read/Write bit Information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or ACK bit.
1= Read
0 = Write
bit 1
bit 0
UA: Update Address (10-bit I2C mode only)
1= Indicates that the user needs to update the address in the SSPADD register
0= Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I2C modes):
1= Receive complete, SSPBUF is full
0= Receive not complete, SSPBUF is empty
Transmit (I2C mode only):
1= Transmit in progress, SSPBUF is full
0= Transmit complete, SSPBUF is empty
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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REGISTER 9-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
R/W-0
R/W-0
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
SSPOV
SSPEN
SSPM3
SSPM2
SSPM1
SSPM0
bit 0
bit 7
bit 7
bit 6
WCOL: Write Collision Detect bit
1= The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0= No collision
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1= A new byte is received while the SSPBUF register is still holding the previous data. In case
of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user
must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In
Master mode, the overflow bit is not set since each new reception (and transmission) is
initiated by writing to the SSPBUF register.
0= No overflow
In I2C mode:
1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV
is a "don’t care" in Transmit mode. SSPOV must be cleared in software in either mode.
0= No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1= Enables serial port and configures SCK, SDO, and SDI as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In I2C mode:
1= Enables the serial port and configures the SDA and SCL pins as serial port pins
0= Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1= Idle state for clock is a high level (Microwire® default)
0= Idle state for clock is a low level (Microwire® alternate)
In I2C mode:
SCK release control
1= Enable clock
0= Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000= SPI Master mode, clock = FOSC/4
0001= SPI Master mode, clock = FOSC/16
0010= SPI Master mode, clock = FOSC/64
0011= SPI Master mode, clock = TMR2 output/2
0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110= I2C Slave mode, 7-bit address
0111= I2C Slave mode, 10-bit address
1011= I2C firmware controlled Master mode (slave idle)
1110= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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PIC16F7X
To enable the serial port, SSP enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON reg-
ister, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appro-
priately programmed. That is:
FIGURE 9-1: SSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SSPSR reg
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
Shift
Clock
cleared
RC4/SDI/SDA
RC5/SDO
bit0
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set and ADCON must
be configured such that RA5 is a digital I/O
.
Control
Enable
SS
Note 1: When the SPI is in Slave mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
RA5/SS/AN4
Edge
Select
2
2: If the SPI is used in Slave mode with
CKE = '1', then the SS pin control must be
enabled.
Clock Select
SSPM3:SSPM0
4
TMR2 Output
2
Edge
Select
TCY
Prescaler
4, 16, 64
RC3/SCK/
SCL
TRISC<3>
DS30325A-page 64
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 9-2: SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
SSPIF
bit7
bit0
FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDO
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit2
bit7
bit6
bit5
bit3
bit1
bit0
bit4
SDI (SMP = 0)
SSPIF
bit7
bit0
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 65
PIC16F7X
TABLE 9-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh.
10Bh,18Bh
INTCON
PIR1
GIE
PEIE
T0IE
INTE RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
PSPIF
PSPIE
ADIF
ADIE
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
8Ch
87h
PIE1
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
13h
14h
85h
94h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
SSPCON WCOL
SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
TRISA
—
—
PORTA Data Direction Register
D/A R/W
--11 1111 --11 1111
0000 0000 0000 0000
SSPSTAT
SMP
CKE
P
S
UA
BF
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325A-page 66
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
The SSPCON register allows control of the I2C opera-
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I2C modes to be selected:
• I2C Slave mode (7-bit address)
• I2C Slave mode (10-bit address)
• I2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
9.3
SSP I2C Operation
The SSP module in I2C mode, fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facil-
itate firmware implementations of the master functions.
The SSP module implements the standard mode speci-
fications as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the RC3/
SCK/SCL pin, which is the clock (SCL), and the RC4/
SDI/SDA pin, which is the data (SDA). The user must
configure these pins as inputs or outputs through the
TRISC<4:3> bits.
• I2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
• I2C START and STOP bit interrupts enabled to
support firmware Master mode, Slave is idle
The SSP module functions are enabled by setting SSP
enable bit SSPEN (SSPCON<5>).
Selection of any I2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, pro-
vided these pins are programmed to inputs by setting
the appropriate TRISC bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
Additional information on SSP I2C operation can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023A).
FIGURE 9-5: SSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
SSPBUF reg
SSPSR reg
RC3/SCK/SCL
9.3.1
SLAVE MODE
Shift
Clock
In Slave mode, the SCL and SDA pins must be config-
ured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
RC4/
SDI/
MSb
LSb
When an address is matched, or the data transfer after
an address match is received, the hardware automati-
cally will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
SDA
Addr Match
Match Detect
SSPADD reg
There are certain conditions that will cause the SSP
module not to give this ACK pulse. They include (either
or both):
Set, RESET
S, P bits
(SSPSTAT reg)
START and
STOP bit Detect
a) The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The SSP module has five registers for I2C operation.
These are the:
b) The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
• SSP Control Register (SSPCON)
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 9-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condi-
tion. Flag bit BF is cleared by reading the SSPBUF reg-
ister while bit SSPOV is cleared through software.
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirements of the
SSP module, are shown in timing parameter #100 and
parameter #101.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 67
PIC16F7X
9.3.1.1
Addressing
1. Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
2. Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
3. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
4. Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
5. Update the SSPADD register with the first (high)
byte of address, if match releases SCL line, this
will clear bit UA.
a) The SSPSR register value is loaded into the
SSPBUF register.
6. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
b) The buffer full bit, BF is set.
c) An ACK pulse is generated.
7. Receive Repeated START condition.
d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
8. Receive first (high) byte of address (bits SSPIF
and BF are set).
9. Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 9-7). The five Most Sig-
nificant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the sec-
ond address byte. For a 10-bit address, the first byte
would equal ‘1111 0 A9 A8 0’, where A9and A8are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7 - 9 for
slave-transmitter:
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
Generate ACK
(SSP Interrupt occurs
Pulse
SSPSR → SSPBUF
if enabled)
BF
SSPOV
0
1
1
0
0
0
1
1
Yes
No
No
No
Yes
No
No
No
Yes
Yes
Yes
Yes
Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
DS30325A-page 68
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
9.3.1.2
Reception
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft-
ware. The SSPSTAT register is used to determine the
status of the byte.
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
FIGURE 9-6:
I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
A7 A6 A5 A4
R/W=0
Receiving Data
Receiving Data
ACK
9
ACK
9
ACK
9
SDA
SCL
A3 A2 A1
D5
D2
D0
8
D5
D2
D0
8
D7 D6
D4 D3
D7 D6
D4 D3
D1
7
D1
7
3
7
1
2
4
5
4
3
6
5
6
1
2
3
6
1
2
4
8
5
P
S
SSPIF (PIR1<3>)
Cleared in software
Bus Master
terminates
transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
2000 Microchip Technology Inc.
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DS30325A-page 69
PIC16F7X
9.3.1.3
Transmission
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR regis-
ter. Then, pin RC3/SCK/SCL should be enabled by set-
ting bit CKP (SSPCON<4>). The master must monitor
the SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretch-
ing the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the
SDA signal is valid during the SCL high time (Figure 9-7).
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave, the slave logic is reset (resets SSPSTAT
register) and the slave then monitors for another occur-
rence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF reg-
ister, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
R/W = 1
ACK
Transmitting Data
ACK
9
SDA
SCL
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
S
P
SCL held low
while CPU
responds to SSPIF
Data in
sampled
Cleared in software
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
From SSP Interrupt
Service Routine
SSPBUF is written in software
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30325A-page 70
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PIC16F7X
9.3.2
MASTER MODE
9.3.3
MULTI-MASTER MODE
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a RESET or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP condi-
tions. Control of the I2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions, allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a RESET or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
In Master mode, the SCL and SDA lines are manipu-
lated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
’1’ data bit must have the TRISC<4> bit set (input) and
a ’0’ data bit must have the TRISC<4> bit cleared (out-
put). The same scenario is true for the SCL line with the
TRISC<3> bit. Pull-up resistors must be provided
externally to the SCL and SDA pins for proper opera-
tion of the I2C module.
In Multi-Master operation, the SDA line must be moni-
tored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
• Address Transfer
• Data Transfer
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt will occur if enabled):
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address trans-
fer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be gener-
ated. If arbitration was lost during the data transfer
stage, the device will need to re-transfer the data at a
later time.
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode of operation can be done with either the
Slave mode idle (SSPM3:SSPM0 = 1011), or with the
Slave active. When both Master and Slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 9-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Value on:
POR,
Value on all
other
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BOR
RESETS
0Bh, 8Bh,
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
10Bh,18Bh
(1)
0Ch
8Ch
13h
93h
14h
94h
87h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
(1)
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
0000 0000
0000 0000
0000 0000
1111 1111
uuuu uuuu
0000 0000
0000 0000
0000 0000
2
SSPADD Synchronous Serial Port (I C mode) Address Register
SSPCON
SSPSTAT
TRISC
WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
(2)
(2)
SMP
CKE
D/A
P
S
R/W
UA
BF
PORTC Data Direction register
1111 1111
2
Legend: x= unknown, u= unchanged, -= unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I C mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.
2
2: Maintain these bits clear in I C mode.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 71
PIC16F7X
NOTES:
DS30325A-page 72
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
The USART can be configured in the following modes:
10.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Com-
munications Interface or SCI.) The USART can be con-
figured as a full duplex asynchronous system that can
communicate with peripheral devices, such as CRT ter-
minals and personal computers, or it can be configured
as a half duplex synchronous system that can commu-
nicate with peripheral devices, such as A/D or D/A inte-
grated circuits, serial EEPROMs, etc.
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchro-
nous Receiver Transmitter.
REGISTER 10-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
R/W-0
BRGH
R-1
R/W-0
TX9D
bit 0
—
TRMT
bit 7
bit 7
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1= Master mode (Clock generated internally from BRG)
0= Slave mode (Clock from external source)
bit 6
bit 5
TX9: 9-bit Transmit Enable bit
1= Selects 9-bit transmission
0= Selects 8-bit transmission
TXEN: Transmit Enable bit
1= Transmit enabled
0= Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4
SYNC: USART Mode Select bit
1= Synchronous mode
0= Asynchronous mode
bit 3
bit 2
Unimplemented: Read as '0'
BRGH: High Baud Rate Select bit
Asynchronous mode:
1= High speed
0= Low speed
Synchronous mode:
Unused in this mode
bit 1
bit 0
TRMT: Transmit Shift Register Status bit
1= TSR empty
0= TSR full
TX9D: 9th bit of transmit data. Can be parity bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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PIC16F7X
REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
R-0
R-0
R-x
—
FERR
OERR
RX9D
bit 7
bit 0
bit 7
bit 6
bit 5
SPEN: Serial Port Enable bit
1= Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)
0= Serial port disabled
RX9: 9-bit Receive Enable bit
1= Selects 9-bit reception
0= Selects 8-bit reception
SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - Master:
1= Enables single receive
0= Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - Slave:
Don’t care
bit 4
CREN: Continuous Receive Enable bit
Asynchronous mode:
1= Enables continuous receive
0= Disables continuous receive
Synchronous mode:
1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0= Disables continuous receive
bit 3
bit 2
Unimplemented: Read as '0'
FERR: Framing Error bit
1= Framing error (Can be updated by reading RCREG register and receive next valid byte)
0= No framing error
bit 1
bit 0
OERR: Overrun Error bit
1= Overrun error (Can be cleared by clearing bit CREN)
0= No overrun error
RX9D: 9th bit of Received Data
Can be parity bit (parity to be calculated by firmware)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
DS30325A-page 74
AdvanceInformation
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PIC16F7X
It may be advantageous to use the high baud rate
(BRGH = 1), even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
10.1
USART Baud Rate Generator (BRG)
The BRG supports both the Asynchronous and Syn-
chronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In Asynchronous
mode, bit BRGH (TXSTA<2>) also controls the baud
rate. In Synchronous mode, bit BRGH is ignored.
Table 10-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in Master mode (internal clock).
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before output-
ting the new baud rate.
10.1.1 SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin.
Given the desired baud rate and Fosc, the nearest inte-
ger value for the SPBRG register can be calculated
using the formula in Table 10-1. From this, the error in
baud rate can be determined.
TABLE 10-1: BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
1
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
Baud Rate= FOSC/(16(X+1))
N/A
X = value in SPBRG (0 to 255)
TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Value on: Value on all
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 Bit 0
POR,
BOR
other
RESETS
0000 -010 0000 -010
0000 -00x 0000 -00x
0000 0000 0000 0000
98h
18h
99h
TXSTA
CSRC TX9 TXEN SYNC
—
—
BRGH TRMT TX9D
FERR OERR RX9D
RCSTA SPEN RX9 SREN CREN
SPBRG Baud Rate Generator Register
Legend: x = unknown, -= unimplemented read as '0'. Shaded cells are not used by the BRG.
2000 Microchip Technology Inc.
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PIC16F7X
TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
%
%
%
KBAUD ERROR
KBAUD ERROR
KBAUD ERROR
(DECIMAL)
(DECIMAL)
(DECIMAL)
0.3
1.2
-
-
-
255
129
31
15
9
-
-
-
207
103
25
12
8
-
-
-
129
64
15
7
1.221
2.404
9.766
19.531
31.250
34.722
62.500
1.221
1.75
0.17
1.73
1.72
8.51
3.34
8.51
-
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.202
0.17
0.17
1.73
1.72
8.51
6.99
9.58
-
2.4
2.404
2.404
9.6
9.615
9.766
19.2
28.8
33.6
57.6
HIGH
19.231
27.778
35.714
62.500
0.977
19.531
31.250
31.250
52.083
0.610
4
8
6
4
4
3
2
255
0
255
0
255
0
LOW 312.500
-
250.000
-
156.250
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
%
%
ERROR
ERROR
KBAUD
(DECIMAL) KBAUD
(DECIMAL)
0.3
1.2
0.300
1.202
2.404
8.929
20.833
31.250
-
0
207
51
25
6
0.301
1.216
2.432
9.322
18.643
-
0.33
1.33
1.33
2.90
2.90
-
185
46
22
5
0.17
0.17
6.99
8.51
8.51
-
2.4
9.6
19.2
28.8
33.6
57.6
HIGH
LOW
2
2
1
-
-
-
-
-
62.500
0.244
62.500
8.51
-
0
55.930
0.218
55.930
2.90
-
0
255
0
255
0
-
-
-
TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
FOSC = 16 MHz
FOSC = 10 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
SPBRG
VALUE
%
%
%
KBAUD
ERROR
KBAUD
ERROR
KBAUD
ERROR
(DECIMAL)
(DECIMAL)
(DECIMAL)
0.3
1.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2.4
-
-
-
-
-
-
2.441
9.615
19.531
28.409
32.895
56.818
2.441
625.000
1.71
0.16
1.72
1.36
2.10
1.36
-
255
64
31
21
18
10
255
0
9.6
9.615
19.231
29.070
33.784
59.524
4.883
0.16
0.16
0.94
0.55
3.34
-
129
64
42
36
20
255
0
9.615
19.231
29.412
33.333
58.824
3.906
1000.000
0.16
0.16
2.13
0.79
2.13
-
103
51
33
29
16
255
0
19.2
28.8
33.6
57.6
HIGH
LOW 1250.000
-
-
FOSC = 4 MHz
FOSC = 3.6864 MHz
BAUD
RATE
(K)
SPBRG
VALUE
SPBRG
VALUE
%
%
ERROR
ERROR
KBAUD
(DECIMAL) KBAUD
(DECIMAL)
0.3
1.2
-
-
-
207
103
25
12
8
-
-
-
185
92
22
11
7
1.202
0.17
0.17
0.16
0.16
3.55
6.29
8.51
-
1.203
0.25
0.25
1.32
2.90
2.90
4.88
2.90
-
2.4
2.404
2.406
9.6
9.615
9.727
19.2
28.8
33.6
57.6
HIGH
LOW
19.231
27.798
35.714
62.500
0.977
18.643
27.965
31.960
55.930
0.874
6
6
3
3
255
0
255
0
250.000
-
273.722
-
DS30325A-page 76
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
(PIE1<4>). Flag bit TXIF will be set, regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit, which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR reg-
ister is empty.
10.2
USART Asynchronous Mode
In this mode, the USART uses standard non-return-to-
zero (NRZ) format (one START bit, eight or nine data
bits, and one STOP bit). The most common data format
is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-
ator can be used to derive standard baud rate frequen-
cies from the oscillator. The USART transmits and
receives the LSb first. The USART’s transmitter and
receiver are functionally independent, but use the
same data format and baud rate. The baud rate gener-
ator produces a clock either x16 or x64 of the bit shift
rate, depending on bit BRGH (TXSTA<2>). Parity is not
supported by the hardware, but can be implemented in
software (and stored as the ninth data bit). Asynchro-
nous mode is stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory, so it is not available to the user.
2: Flag bit TXIF is set when enable bit TXEN
is set. TXIF is cleared by loading TXREG.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 10-2). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally, when transmission
is first started, the TSR register is empty. At that point,
transfer to the TXREG register will result in an immedi-
ate transfer to TSR, resulting in an empty TXREG. A
back-to-back transfer is thus possible (Figure 10-3).
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result, the RC6/TX/CK pin will revert
to hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver
10.2.1 USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 10-1. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG register (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG reg-
ister. This is because a data write to the TXREG regis-
ter can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit may be loaded in the TSR
register.
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXREG register
TXIF
TXIE
8
MSb
(8)
LSb
0
Pin Buffer
and Control
•
• •
TSR Register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
SPBRG
TRMT
SPEN
TX9
TX9D
Baud Rate Generator
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 77
PIC16F7X
Steps to follow when setting up an Asynchronous
Transmission:
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 10.1)
7. Load data to the TXREG register (starts trans-
mission).
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
3. If interrupts are desired, then set enable bit TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
STOP Bit
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG
Word 2
Word 1
BRG Output
(Shift Clock)
RC6/TX/CK (pin)
TXIF bit
(Interrupt Reg. Flag)
START Bit
START Bit
Bit 0
Bit 1
Word 1
Bit 7/8
Bit 0
STOP Bit
Word 2
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
T0IE
RCIF
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
DS30325A-page 78
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
10.2.2 USART ASYNCHRONOUS RECEIVER
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the STOP bit of the third byte, if the RCREG register is
still full, the overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG reg-
ister can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited
and no further data will be received, therefore, it is
essential to clear error bit OERR if it is set. Framing
error bit FERR (RCSTA<2>) is set if a STOP bit is
detected as clear. Bit FERR and the 9th receive bit are
buffered the same way as the receive data. Reading
the RCREG will load bits RX9D and FERR with new
values, therefore, it is essential for the user to read the
RCSTA register before reading RCREG register, in
order not to lose the old FERR and RX9D information.
The receiver block diagram is shown in Figure 10-4.
The data is received on the RC7/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter oper-
ates at the bit rate, or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift reg-
ister (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register (i.e., it is a two deep FIFO). It
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
CREN
FERR
OERR
FOSC
SPBRG
RSR Register
LSb
MSb
÷64
or
÷16
0
Baud Rate Generator
1
7
STOP (8)
START
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
FIGURE 10-5: ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
reg
Rcv Buffer reg
WORD 2
RCREG
WORD 1
RCREG
Read Rcv
Buffer reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 79
PIC16F7X
Steps to follow when setting up an Asynchronous
Reception:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
10. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
T0IE
RCIF
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
DS30325A-page 80
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
FOSC
SPBRG
RSR Register
MSb
LSb
÷64
or
÷16
0
Baud Rate Generator
7
1
STOP (8)
START
• • •
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
8
SPEN
RX9D
RCREG Register
FIFO
8
RCIF
RCIE
Interrupt
Data Bus
TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
TXIF
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 81
PIC16F7X
Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-
impedance. If either bit CREN or bit SREN is set during
a transmission, the transmission is aborted and the DT
pin reverts to a hi-impedance state (for a reception).
The CK pin will remain an output if bit CSRC is set
(internal clock). The transmitter logic, however, is not
reset, although it is disconnected from the pins. In order
to reset the transmitter, the user has to clear bit TXEN.
If bit SREN is set (to interrupt an on-going transmission
and receive a single word), then after the single word is
received, bit SREN will be cleared and the serial port
will revert back to transmitting, since bit TXEN is still
set. The DT line will immediately switch from hi-
impedance receive mode to transmit and start driving.
To avoid this, bit TXEN should be cleared.
10.3
USART Synchronous Master Mode
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
10.3.1 USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 10-6. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory, so it is not
available to the user.
In order to select 9-bit transmission, the TX9
(TXSTA<6>) bit should be set and the ninth bit should
be written to bit TX9D (TXSTA<0>). The ninth bit must
be written before writing the 8-bit data to the TXREG
register. This is because a data write to the TXREG can
result in an immediate transfer of the data to the TSR
register (if the TSR is empty). If the TSR was empty and
the TXREG was written before writing the “new” TX9D,
the “present” value of bit TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. If interrupts are desired, set enable bit TXIE.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting bit TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 10-7). The transmission can also be started by
first loading the TXREG register and then setting bit
TXEN (Figure 10-8). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally, when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
DS30325A-page 82
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on:
POR,
Value on all
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
other
BOR
RESETS
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x
0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
FIGURE 10-7: SYNCHRONOUS TRANSMISSION
Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4
Q3Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3 Q4
RC7/RX/DT pin
RC6/TX/CK pin
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
Word 2
bit 7
Word 1
Write to
TXREG reg
Write Word1
Write Word2
TXIF bit
(Interrupt Flag)
T
TRMT bit
’1’
’1’
TXEN bit
Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.
FIGURE 10-8: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RC7/RX/DT pin
RC6/TX/CK pin
bit0
bit2
bit1
bit6
bit7
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
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PIC16F7X
10.3.2 USART SYNCHRONOUS MASTER
RECEPTION
receive data. Reading the RCREG register will load bit
RX9D with a new value, therefore, it is essential for the
user to read the RCSTA register before reading RCREG,
in order not to lose the old RX9D information.
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>),
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is con-
tinuous until CREN is cleared. If both bits are set, CREN
takes precedence. After clocking the last bit, the
received data in the Receive Shift Register (RSR) is
transferred to the RCREG register (if it is empty). When
the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled by setting/clearing enable bit RCIE (PIE1<5>).
Flag bit RCIF is a read only bit, which is reset by the
hardware. In this case, it is reset when the RCREG reg-
ister has been read and is empty. The RCREG is a dou-
ble buffered register (i.e., it is a two deep FIFO). It is
possible for two bytes of data to be received and trans-
ferred to the RCREG FIFO and a third byte to begin shift-
ing into the RSR register. On the clocking of the last bit
of the third byte, if the RCREG register is still full, then
overrun error bit OERR (RCSTA<1>) is set. The word in
the RSR will be lost. The RCREG register can be read
twice to retrieve the two bytes in the FIFO. Bit OERR has
to be cleared in software (by clearing bit CREN). If bit
OERR is set, transfers from the RSR to the RCREG are
inhibited, so it is essential to clear bit OERR if it is set.
The ninth receive bit is buffered the same way as the
Steps to follow when setting up a Synchronous Master
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate (Section 10.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
7. Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
bit CREN.
11. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Value on all
other
RESETS
Value on:
POR, BOR
Address
Name
Bit 7
Bit 6
Bit 5
T0IE
RCIF
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
DS30325A-page 84
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PIC16F7X
FIGURE 10-9: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2Q3Q4 Q1Q2Q3Q4 Q1 Q2Q3Q4 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4
bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7
RC7/RX/DT pin
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit
’0’
’0’
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.
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10.4.2 USART SYNCHRONOUS SLAVE
RECEPTION
10.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master
mode, in the fact that the shift clock is supplied exter-
nally at the RC6/TX/CK pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in SLEEP mode. Slave
mode is entered by clearing bit CSRC (TXSTA<7>).
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEPinstruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
10.4.1 USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
Steps to follow when setting up a Synchronous Slave
Reception:
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
2. If interrupts are desired, set enable bit RCIE.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the inter-
rupt vector (0004h).
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREG register.
Steps to follow when setting up a Synchronous Slave
Transmission:
8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
9. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
2. Clear bits CREN and SREN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
8. If using interrupts, ensure that GIE and PIE in
the INTCON register are set.
DS30325A-page 86
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TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
T0IE
RCIF
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
19h
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
SREN CREN ADDEN FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
TXREG USART Transmit Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.
TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Value on:
POR,
BOR
Value on all
other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
T0IE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
RCSTA
RX9 SREN CREN ADDEN FERR
OERR
RX9D
0000 000x 0000 000x
0000 0000 0000 0000
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
TXSTA
TX9 TXEN SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.
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PIC16F7X
NOTES:
DS30325A-page 88
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The A/D module has three registers. These registers
are:
11.0 ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The 8-bit analog-to-digital (A/D) converter module has
five inputs for the PIC16F73/76 and eight for the
PIC16F74/77.
• A/D Result Register (ADRES)
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, con-
trols the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the func-
tions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference),
or as digital I/O.
The A/D allows conversion of an analog input signal to
a corresponding 8-bit digital number. The output of the
sample and hold is the input into the converter, which
generates the result via successive approximation. The
analog reference voltage is software selectable to
either the device’s positive supply voltage (VDD), or the
voltage level on the RA3/AN3/VREF pin.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family Ref-
erence Manual (DS33023) and in Application Note,
AN546.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To oper-
ate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
REGISTER 11-1: ADCON0 REGISTER (ADDRESS 1Fh)
R/W-0
ADCS1
bit 7
R/W-0
R/W-0
CHS2
R/W-0
CHS1
R/W-0
CHS0
R/W-0
U-0
R/W-0
ADON
bit 0
ADCS0
GO/DONE
—
bit 7-6
bit 5-3
ADCS1:ADCS0: A/D Conversion Clock Select bits
00= FOSC/2
01= FOSC/8
10= FOSC/32
11= FRC (clock derived from the internal A/D module RC oscillator)
CHS2:CHS0: Analog Channel Select bits
000= channel 0, (RA0/AN0)
001= channel 1, (RA1/AN1)
010= channel 2, (RA2/AN2)
011= channel 3, (RA3/AN3)
100= channel 4, (RA5/AN4)
101= channel 5, (RE0/AN5)(1)
110= channel 6, (RE1/AN6)(1)
111= channel 7, (RE2/AN7)(1)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1= A/D conversion in progress (setting this bit starts the A/D conversion)
0= A/D conversion not in progress (This bit is automatically cleared by hardware when
the A/D conversion is complete)
bit 1
bit 0
Unimplemented: Read as '0'
ADON: A/D On bit
1= A/D converter module is operating
0= A/D converter module is shutoff and consumes no operating current
Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR reset
’1’ = Bit is set
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REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
PCFG2
PCFG1 PCFG0
bit 0
bit 7
bit 7-3
bit 2-0
Unimplemented: Read as '0'
PCFG2:PCFG0: A/D Port Configuration Control bits
PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0(1) RE1(1) RE2(1) VREF
000
001
010
011
100
101
11x
A
A
A
A
A
A
D
A
A
A
A
A
A
D
A
A
A
A
D
D
D
A
A
A
A
D
D
D
A
VREF
A
A
A
D
D
D
D
D
A
A
D
D
D
D
D
A
A
D
D
D
D
D
VDD
RA3
VDD
RA3
VDD
RA3
VDD
VREF
A
VREF
D
A = Analog input
D = Digital I/O
Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only.
Legend:
R = Readable bit
- n = Value at POR reset
W = Writable bit
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
’1’ = Bit is set
DS30325A-page 90
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The following steps should be followed for doing an
A/D conversion:
3. Wait the required acquisition time.
4. Start conversion:
1. Configure the A/D module:
• Set GO/DONE bit (ADCON0)
5. Wait for A/D conversion to complete, by either:
• Configure analog pins / voltage reference /
and digital I/O (ADCON1)
• Polling for the GO/DONE bit to be cleared
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
2. Configure A/D interrupt (if desired):
• Clear ADIF bit
(interrupts disabled)
OR
• Waiting for the A/D interrupt
6. Read A/D result register (ADRES), clear bit
ADIF if required.
• Set ADIE bit
7. For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
• Set PEIE bit
• Set GIE bit
FIGURE 11-1: A/D BLOCK DIAGRAM
CHS2:CHS0
111
(1)
RE2/AN7
110
(1)
RE1/AN6
101
(1)
RE0/AN5
100
RA5/AN4
VIN
011
(Input Voltage)
RA3/AN3/VREF
010
RA2/AN2
A/D
Converter
001
RA1/AN1
000
VDD
RA0/AN0
000or
010or
100or
11x
VREF
(Reference
Voltage)
001or
011or
101
PCFG2:PCFG0
Note 1: Not available on PIC16F73/76.
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PIC16F7X
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed), the acquisition must pass before
the conversion can be started.
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD),
Figure 11-2. The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023A). In general, however, given a max
of 10kΩ and at a temperature of 100°C, TACQ will be no
more than 16µsec.
FIGURE 11-2: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
ANx
SS
RIC ≤ 1k
RSS
RS
CHOLD
= DAC Capacitance
= 51.2 pF
CPIN
5 pF
VA
I leakage
± 500 nA
VT = 0.6V
VSS
Legend CPIN
VT
= input capacitance
= threshold voltage
6V
5V
VDD 4V
3V
= leakage current at the pin due to
various junctions
I leakage
2V
= interconnect resistance
= sampling switch
RIC
SS
5 6 7 8 9 10 11
Sampling Switch
= sample/hold capacitance (from DAC)
CHOLD
(kΩ)
TABLE 11-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
ADCS1:ADCS0
Maximum Device Frequency
Max.
Operation
2TOSC
8TOSC
00
01
10
11
1.25 MHz
5 MHz
32TOSC
RC(1, 2, 3)
20 MHz
(Note 1)
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
DS30325A-page 92
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11.2
Selecting the A/D Conversion Clock
11.5
A/D Operation During SLEEP
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The four possible options for TAD are:
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
• 2TOSC
• 8TOSC
• 32TOSC
• Internal RC oscillator (2-6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
of 1.6 µs.
11.3
Configuring Analog Port Pins
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
The ADCON1, TRISA and TRISE registers control the
operation of the A/D port pins. The port pins that are
desired as analog inputs must have their correspond-
ing TRIS bits set (input). If the TRIS bit is cleared (out-
put), the digital output level (VOH or VOL) will be
converted.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the instruc-
tion that sets the GO/DONE bit.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the TRIS bits.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins config-
ured as digital inputs will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
11.6
Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
2: Analog levels on any pin that is defined as
a digital input, but not as an analog input,
may cause the input buffer to consume
current that is out of the devices specifica-
tion.
The ADRES register will contain unknown data after a
Power-on Reset.
11.7
Use of the CCP Trigger
11.4
A/D Conversions
An A/D conversion can be started by the “special event
trigger” of the CCP2 module. This requires that the
CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-
grammed as 1011and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The ADRES register will
NOT be updated with the partially completed A/D con-
version sample. That is, the ADRES register will con-
tinue to contain the value of the last completed
conversion (or the last value written to the ADRES reg-
ister). After the A/D conversion is aborted, a 2TAD wait
is required before the next acquisition is started. After
this 2TAD wait, an acquisition is automatically started on
the selected channel. The GO/DONE bit can then be
set to start the conversion.
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
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TABLE 11-2: SUMMARY OF A/D REGISTERS
Value on: Value on all
Address
Name
INTCON
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
INTE
TXIF
Bit 3
Bit 2
Bit 1
Bit 0
POR,
BOR
other
RESETS
GIE
PEIE
T0IE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000u
0Bh,8Bh,
10Bh,18Bh
(1)
PSPIF
ADIF RCIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
0Ch
0Dh
PIR2
PIE1
—
—
—
—
—
—
—
(1)
PSPIE
ADIE RCIE
TXIE
8Ch
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
ADRES
A/D Result Register
1Eh
1Fh
9Fh
05h
85h
09h
89h
ADCON0 ADCS1 ADCS0 CHS2
CHS1
CHS0 GO/DONE
—
ADON 0000 00-0 0000 00-0
ADCON1
—
—
—
—
—
—
—
PCFG2
RA2
PCFG1 PCFG0 ---- -000 ---- -000
--0x 0000 --0u 0000
PORTA
TRISA
RA5
RA4
RA3
RA1
RA0
--11 1111 --11 1111
---- -xxx ---- -uuu
0000 -111 0000 -111
—
—
—
—
PORTA Data Direction Register
(2)
—
—
—
—
PORTE
RE2
RE1
RE0
(2)
TRISE
IBF
OBF IBOV PSPMODE
PORTE Data Direction Bits
Legend: x= unknown, u= unchanged, -= unimplemented read as '0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.
2: These registers are reserved on the PIC16F73/76.
DS30325A-page 94
AdvanceInformation
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PIC16F7X
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake-up from SLEEP
through external RESET, Watchdog Timer Wake-up, or
through an interrupt.
12.0 SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to max-
imize system reliability, minimize cost through elimina-
tion of external components, provide power saving
operating modes and offer code protection. These are:
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. A set of configuration bits are used to
select various options.
• Oscillator Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
12.1
Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped in pro-
gram memory location 2007h.
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
The user will note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
• In-Circuit Serial Programming
These devices have a Watchdog Timer, which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nomi-
nal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes. With these
two timers on-chip, most applications need no external
RESET circuitry.
2000 Microchip Technology Inc.
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DS30325A-page 95
PIC16F7X
REGISTER 12-1: CONFIGURATION WORD
BODEN
CP0 PWRTE WDTE F0SC1 F0SC0
bit0
Register:
Address
Erased Value: 3FFFh
CONFIG
2007h
—
—
—
—
—
—
—
—
bit13
bit 13-7: Unimplemented: Read as ‘1’
(1)
bit 6:
BODEN: Brown-out Reset Enable bit
1= BOR enabled
0= BOR disabled
bit 5:
bit 4
Unimplemented: Read as ‘1’
CP0: Flash Program Memory Code Protection bit
1= Code protection off
0= All memory locations code protected
(1)
bit 3:
bit 2:
PWRTE: Power-up Timer Enable bit
1= PWRT disabled
0= PWRT enabled
WDTE: Watchdog Timer Enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator Selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.
DS30325A-page 96
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PIC16F7X
12.2
Oscillator Configurations
FIGURE 12-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
12.2.1
OSCILLATOR TYPES
OSC CONFIGURATION)
The PIC16F7X can be operated in four different oscil-
lator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
OSC1
OSC2
Clock from
ext. system
PIC16F7X
• LP
• XT
• HS
• RC
Low Power Crystal
Open
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 12-1: CERAMIC RESONATORS
Ranges Tested:
12.2.2 CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 12-1). The
PIC16F7X oscillator design requires the use of a paral-
lel cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source to drive the OSC1/CLKIN pin
(Figure 12-2). See Table 15-1 for valid external clock
frequencies.
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF 68 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only.
See notes at bottom of page.
Resonators Used:
FIGURE 12-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
455 kHz Panasonic EFO-A455K04B
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
2.0 MHz
4.0 MHz
8.0 MHz
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
OSC CONFIGURATION)
(1)
C1
OSC1
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
To
internal
logic
XTAL
RF(3)
OSC2
SLEEP
PIC16F7X
(2)
RS
C2(1)
Note 1: See Table 12-1 and Table 12-2 for recom-
mended values of C1 and C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen.
2000 Microchip Technology Inc.
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DS30325A-page 97
PIC16F7X
12.2.3 RC OSCILLATOR
TABLE 12-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
For timing insensitive applications, the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used. Figure 12-3 shows how the R/C combina-
tion is connected to the PIC16F7X.
Cap.
Range
C2
Crystal
Freq
Cap. Range
C1
Osc Type
LP
32 kHz
200 kHz
200 kHz
1 MHz
33 pF
15 pF
33 pF
15 pF
XT
47-68 pF
15 pF
47-68 pF
15 pF
4 MHz
15 pF
15 pF
HS
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
15-33 pF
15-33 pF
20 MHz
FIGURE 12-3: RC OSCILLATOR MODE
These values are for design guidance only.
See notes at bottom of page.
VDD
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
± 20 PPM
± 50 PPM
± 50 PPM
± 30 PPM
REXT
Internal
OSC1
200 kHz STD XTL 200.000KHz
Clock
1 MHz
4 MHz
8 MHz
20 MHz
ECS ECS-10-13-1
CEXT
VSS
PIC16F7X
ECS ECS-40-20-1
EPSON CA-301 8.000M-C
OSC2/CLKOUT
FOSC/4
Recommended values:
EPSON CA-301 20.000M-C ± 30 PPM
3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20pF
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the start-
up time.
2: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external compo-
nents.
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: When migrating from other PICmicro
devices, oscillator performance should be
verified.
DS30325A-page 98
AdvanceInformation
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PIC16F7X
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situa-
tions, as indicated in Table 12-4. These bits are used in
software to determine the nature of the RESET. See
Table 12-6 for a full description of RESET states of all
registers.
12.3
RESET
The PIC16F7X differentiates between various kinds of
RESET:
• Power-on Reset (POR)
• MCLR Reset during normal operation
• MCLR Reset during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
• Brown-out Reset (BOR)
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 12-4.
These devices have a MCLR noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
SLEEP
WDT
WDT
Module
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
R
BODEN
OST/PWRT
OST
Chip_Reset
Q
10-bit Ripple counter
OSC1
(1)
On-chip
RC OSC
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 99
PIC16F7X
12.4
Power-on Reset (POR)
12.8
Time-out Sequence
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin directly
(or through a resistor) to VDD. This will eliminate exter-
nal RC components usually needed to create a Power-
on Reset. A maximum rise time for VDD is specified.
See Electrical Specifications for details.
On power-up, the time-out sequence is as follows: The
PWRT delay starts (if enabled) when a POR Reset
occurs. Then OST starts counting 1024 oscillator
cycles when PWRT ends (LP, XT, HS). When the OST
ends, the device comes out of RESET.
If MCLR is kept low long enough, the time-outs will
expire. Bringing MCLR high will begin execution imme-
diately. This is useful for testing purposes or to synchro-
nize more than one PIC16F7X device operating in
parallel.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. Brown-out Reset may be used to meet the
start-up conditions. For additional information, refer to
Application Note, AN007, “Power-up Trouble Shoot-
ing”, (DS00007).
Table 12-5 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 12-6
shows the RESET conditions for all the registers.
12.9
Power Control/Status Register
(PCON)
12.5
Power-up Timer (PWRT)
The Power Control/Status Register, PCON, has up to
two bits depending upon the device.
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only from the POR. The Power-
up Timer operates on an internal RC oscillator. The
chip is kept in RESET as long as the PWRT is active.
The PWRT’s time delay allows VDD to rise to an accept-
able level. A configuration bit is provided to enable/
disable the PWRT.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see
if bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable and therefore, not
valid at any time.
The power-up time delay will vary from chip to chip due
to VDD, temperature and process variation. See DC
parameters for details (TPWRT, parameter #33).
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
12.7
Brown-out Reset (BOR)
The configuration bit, BODEN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100µS), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer then keeps the device in RESET for
TPWRT (parameter #33, about 72mS). If VDD should fall
below VBOR during TPWRT, the Brown-out Reset pro-
cess will restart when VDD rises above VBOR, with the
Power-up Timer Reset. The Power-up Timer is always
enabled when the Brown-out Reset circuit is enabled,
regardless of the state of the PWRT configuration bit.
DS30325A-page 100
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 12-3: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0
Brown-out
Wake-up from
SLEEP
PWRTE = 1
1024TOSC
—
XT, HS, LP
RC
72 ms + 1024TOSC
72 ms
72 ms + 1024TOSC
72 ms
1024TOSC
—
TABLE 12-4: STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
0
0
1
1
1
1
1
x
x
x
0
1
1
1
1
1
0
x
1
0
0
u
1
1
x
0
1
1
0
u
0
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
TABLE 12-5: RESET CONDITION FOR SPECIAL REGISTERS
Program
STATUS
Register
PCON
Register
Condition
Counter
Power-on Reset
000h
000h
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
0001 1uuu
uuu1 0uuu
---- --0x
---- --uu
---- --uu
---- --uu
---- --uu
---- --u0
---- --uu
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset
000h
000h
WDT Wake-up
PC + 1
Brown-out Reset
000h
PC + 1(1)
Interrupt wake-up from SLEEP
Legend: u= unchanged, x= unknown, -= unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 101
PIC16F7X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
W
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
77
xxxx xxxx
N/A
uuuu uuuu
N/A
uuuu uuuu
N/A
INDF
TMR0
xxxx xxxx
0000h
uuuu uuuu
uuuu uuuu
PC + 1(2)
uuuq quuu(3)
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---u uuuu
uuuu uuuu(1)
ruuu uuuu(1)
uuuu uuuu(1)
---- ---u(1)
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu uuuu
-uuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--uu uuuu
uuuu -uuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uu-u
uuuu uuuu
--uu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu -uuu
ruuu uuuu
uuuu uuuu
---- ---u
PCL
0000h
STATUS
FSR
0001 1xxx
xxxx xxxx
--0x 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
---- -xxx
---0 0000
0000 000x
r000 0000
0000 0000
---- ---0
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
---- ---0
000q quuu(3)
uuuu uuuu
--0u 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
---- -uuu
---0 0000
0000 000u
r000 0000
0000 0000
---- ---0
uuuu uuuu
uuuu uuuu
--uu uuuu
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 -00x
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
uuuu uuuu
0000 00-0
1111 1111
--11 1111
1111 1111
1111 1111
1111 1111
0000 -111
r000 0000
0000 0000
---- ---0
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
OPTION_REG
TRISA
TRISB
TRISC
TRISD
TRISE
PIE1
PIE2
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET value for specific condition.
DS30325A-page 102
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 12-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Reset,
WDT Reset
Wake-up via WDT or
Interrupt
PCON
73
73
73
73
73
73
73
73
73
73
73
73
74
74
74
74
74
74
74
74
74
74
74
74
76
76
76
76
76
76
76
76
76
76
76
76
77
77
77
77
77
77
77
77
77
77
77
77
---- --qq
1111 1111
--00 0000
0000 0000
0000 -010
0000 0000
---- -000
0--- 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
1--- ---0
---- --uu
1111 1111
--00 0000
0000 0000
0000 -010
0000 0000
---- -000
0--- 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
1--- ---0
---- --uu
1111 1111
--uu uuuu
uuuu uuuu
uuuu -uuu
uuuu uuuu
---- -uuu
u--- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
1--- ---u
PR2
SSPSTAT
SSPADD
TXSTA
SPBRG
ADCON1
PMDATA
PMADR
PMDATH
PMADRH
PMCON1
Legend: u = unchanged, x = unknown, -= unimplemented bit, read as ’0’, q= value depends on condition,
r= reserved maintain clear.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
3: See Table 12-5 for RESET value for specific condition.
FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
2000 Microchip Technology Inc.
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DS30325A-page 103
PIC16F7X
FIGURE 12-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
TOST
INTERNAL RESET
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-8: SLOW RISE TIME (MCLR TIED TO VDD)
5V
1V
VDD
0V
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30325A-page 104
AdvanceInformation
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PIC16F7X
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
12.10 Interrupts
The PIC16F7X family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
The peripheral interrupt flags are contained in the Spe-
cial Function Registers, PIR1 and PIR2. The corre-
sponding interrupt enable bits are contained in Special
Function Registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in Special Function
Register INTCON.
Note: Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit, PEIE bit, or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-9: INTERRUPT LOGIC
PSPIF
PSPIE
Wake-up (If in SLEEP mode)
ADIF
ADIE
T0IF
T0IE
RCIF
RCIE
INTF
INTE
Interrupt to CPU
TXIF
TXIE
RBIF
RBIE
SSPIF
SSPIE
PEIE
GIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16F76/73
PIC16F77/74
Yes Yes Yes
Yes Yes Yes
-
Yes
Yes
Yes Yes
Yes Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 105
PIC16F7X
12.10.1 INT INTERRUPT
12.11 Context Saving During Interrupts
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION_REG<6>) is set,
or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT inter-
rupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the pro-
cessor branches to the interrupt vector following wake-
up. See Section 12.13 for details on SLEEP mode.
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e., W register and STATUS
register). This will have to be implemented in software.
For the PIC16F73/74 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., If W_TEMP is defined at 0x20 in bank 0, it must
also be defined at 0xA0 in bank 1.). The registers,
PCLATH_TEMP and STATUS_TEMP, are only defined
in bank 0.
Since the upper 16 bytes of each bank are common in
the PIC16F76/77 devices, temporary holding registers
W_TEMP, STATUS_TEMP and PCLATH_TEMP
should be placed in here. These 16 locations don’t
require banking and therefore, make it easier for con-
text save and restore. The same code shown in
Example 12-1 can be used.
12.10.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>). (Section 5.0)
12.10.3 PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>).
(Section 3.2)
EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
:
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
;Copy W to TEMP register
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
:(ISR)
:
;Insert user code here
MOVF
MOVWF
SWAPF
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap W_TEMP into W
DS30325A-page 106
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
WDT time-out period values may be found in the Elec-
trical Specifications section under parameter #31. Val-
ues for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION_REG register.
12.12 Watchdog Timer (WDT)
The Watchdog Timer is as a free running on-chip RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device has been stopped,
for example, by execution of a SLEEPinstruction.
Note: The CLRWDTand SLEEPinstructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out
and generating a device RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS regis-
ter will be cleared upon a Watchdog Timer time-out.
.
Note: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 12.1).
FIGURE 12-10: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 5-1)
0
Postscaler
8
M
1
U
WDT Timer
X
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 5-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
(1)
2007h
Config. bits
(1)
BODEN
—
CP0
PWRTE
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
81h,181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
2000 Microchip Technology Inc.
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PIC16F7X
When the SLEEPinstruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEPinstruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the inter-
rupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOPafter the SLEEPinstruction.
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external cir-
cuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
12.13.2 WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEPinstruction, the SLEEPinstruction will com-
plete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1 WAKE-UP FROM SLEEP
• If the interrupt occurs during or after the execu-
tion of a SLEEPinstruction, the device will imme-
diately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
The device can wake up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer wake-up (if WDT was
enabled).
3. Interrupt from INT pin, RB port change or a
Peripheral Interrupt.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEPinstruction completes. To
determine whether a SLEEPinstruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
To ensure that the WDT is cleared, a CLRWDTinstruc-
tion should be executed before a SLEEPinstruction.
The following peripheral interrupts can wake the device
from SLEEP:
1. PSP read or write (PIC16F74/77 only).
2. TMR1 interrupt. Timer1 must be operating as
an asynchronous counter.
3. CCP Capture mode interrupt.
4. Special event trigger (Timer1 in Asynchronous
mode using an external clock).
5. SSP (START/STOP) bit detect interrupt.
6. SSP transmit or receive in Slave mode
(SPI/I2C).
7. USART RX or TX (Synchronous Slave mode).
8. A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts since dur-
ing SLEEP, no on-chip clocks are present.
DS30325A-page 108
AdvanceInformation
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PIC16F7X
FIGURE 12-11: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(2)
TOST
CLKOUT(4)
INT pin
INTF flag
Interrupt Latency
(INTCON<1>)
(Note 2)
GIE bit
Processor in
SLEEP
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
PC+1
PC+2
PC+2
PC + 2
0004h
0005h
Instruction
Inst(0004h)
Inst(PC + 1)
Inst(PC + 2)
Inst(0005h)
Inst(PC) = SLEEP
fetched
Instruction
executed
Dummy cycle
Dummy cycle
SLEEP
Inst(PC + 1)
Inst(PC - 1)
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine.
If GIE = ’0’, execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
2000 Microchip Technology Inc.
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PIC16F7X
12.14 Program Verification/Code Protection
12.16 In-Circuit Serial Programming
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
PIC16F7X microcontrollers can be serially pro-
grammed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
12.15 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 least significant bits of the ID
location are used.
For complete details of serial programming, please
refer to the In-Circuit Serial Programming (ICSP™)
Guide, (DS30277).
DS30325A-page 110
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruc-
tion cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruc-
tion, the instruction execution time is 2 µs.
13.0 INSTRUCTION SET SUMMARY
Each PIC16F7X instruction is a 14-bit word divided into
an OPCODE, which specifies the instruction type and
one or more operands, which further specify the oper-
ation of the instruction. The PIC16F7X instruction set
summary in Table 13-2 lists byte-oriented, bit-ori-
ented, and literal and control operations. Table 13-1
shows the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file reg-
ister designator and ’d’ represents a destination desig-
nator. The file register designator specifies which file
register is to be used by the instruction.
Table 13-2 lists the instructions recognized by the
MPASM assembler.
Figure 13-1 shows the general formats that the instruc-
tions can have.
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is zero, the result is
placed in the W register. If ’d’ is one, the result is placed
in the file register specified in the instruction.
Note: To maintain upward compatibility with
future PIC16F7X products, do not use the
OPTIONand TRISinstructions.
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the address of the
file in which the bit is located.
All examples use the following format to represent a
hexadecimal number:
0xhh
For literal and control operations, ’k’ represents an
eight or eleven bit constant or literal value.
where h signifies a hexadecimal digit.
FIGURE 13-1: GENERAL FORMAT FOR
INSTRUCTIONS
TABLE 13-1: OPCODE FIELD
DESCRIPTIONS
Byte-oriented file register operations
Field
Description
13
8
7
6
0
0
f
W
b
k
x
OPCODE
d
f (FILE #)
Register file address (0x00 to 0x7F)
Working register (accumulator)
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0or 1)
Bit-oriented file register operations
13 10 9
b (BIT #)
The assembler will generate code with x = 0.
It is the recommended form of use for compat-
ibility with all Microchip software tools.
7
6
OPCODE
f (FILE #)
b = 3-bit bit address
f = 7-bit file register address
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
Literal and control operations
General
PC
TO
PD
Program Counter
Time-out bit
13
8
7
0
0
Power-down bit
OPCODE
k (literal)
The instruction set is highly orthogonal and is grouped
into three basic categories:
k = 8-bit immediate value
• Byte-oriented operations
• Bit-oriented operations
CALLand GOTOinstructions only
13 11 10
OPCODE
k = 11-bit immediate value
• Literal and control operations
k (literal)
A description of each instruction is available in the
PICmicro™ Mid-Range Reference Manual, (DS33023).
2000 Microchip Technology Inc.
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DS30325A-page 111
PIC16F7X
TABLE 13-2: PIC16F7X INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles 14-Bit Opcode
MSb
Status
Affected
Notes
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f, d
f, d
f
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111 dfff ffff C,DC,Z
1,2
1,2
2
0101 dfff ffff
0001 lfff ffff
0001 0xxx xxxx
1001 dfff ffff
0011 dfff ffff
1011 dfff ffff
1010 dfff ffff
1111 dfff ffff
0100 dfff ffff
1000 dfff ffff
0000 lfff ffff
0000 0xx0 0000
1101 dfff ffff
1100 dfff ffff
Z
Z
Z
Z
Z
-
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
Z
Z
Z
Move W to f
No Operation
-
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
C
C
1,2
1,2
1,2
1,2
1,2
0010 dfff ffff C,DC,Z
1110 dfff ffff
0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01 00bb bfff ffff
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
-
k
k
k
-
k
-
-
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
TO,PD
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ’0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS30325A-page 112
AdvanceInformation
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PIC16F7X
13.1
Instruction Descriptions
Add Literal and W
ADDLW
ANDWF
Syntax:
AND W with f
Syntax:
[label] ADDLW
0 ≤ k ≤ 255
k
[label] ANDWF f,d
Operands:
Operation:
Status Affected:
Description:
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
(W) + k → (W)
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
Status Affected:
Description:
Z
The contents of the W register
are added to the eight bit literal ’k’
and the result is placed in the W
register.
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
ADDWF
Syntax:
Add W and f
BCF
Bit Clear f
[label] ADDWF f,d
Syntax:
Operands:
[label] BCF f,b
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operation:
(W) + (f) → (destination)
Operation:
0 → (f<b>)
Status Affected: C, DC, Z
Status Affected: None
Description:
Add the contents of the W register
Description:
Bit 'b' in register 'f' is cleared.
with register ’f’. If ’d’ is 0, the result
is stored in the W register. If ’d’ is
1, the result is stored back in reg-
ister ’f’.
BSF
Bit Set f
ANDLW
AND Literal with W
Syntax:
Operands:
[label] BSF f,b
Syntax:
[label] ANDLW
0 ≤ k ≤ 255
k
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
Status Affected:
Description:
(W) .AND. (k) → (W)
Operation:
1 → (f<b>)
Z
Status Affected: None
The contents of W register are
AND’ed with the eight bit literal
'k'. The result is placed in the W
register.
Description:
Bit 'b' in register 'f' is set.
2000 Microchip Technology Inc.
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PIC16F7X
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’0’, the next
The contents of register ’f’ are
instruction is executed.
cleared and the Z bit is set.
If bit ’b’ is ’1’, then the next instruc-
tion is discarded and a NOPis exe-
cuted instead making this a 2TCY
instruction.
BTFSC
Bit Test, Skip if Clear
CLRW
Clear W
Syntax:
[label] BTFSC f,b
Syntax:
[ label ] CLRW
None
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
Operands:
Operation:
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected: None
Status Affected:
Description:
Z
Description:
If bit ’b’ in register ’f’ is ’1’, the next
W register is cleared. Zero bit (Z)
is set.
instruction is executed.
If bit ’b’, in register ’f’, is ’0’, the
next instruction is discarded, and
a NOPis executed instead, making
this a 2TCY instruction.
CALL
Call Subroutine
[ label ] CALL k
0 ≤ k ≤ 2047
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
Operands:
Operation:
Operands:
Operation:
(PC) + 1 → TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven bit immedi-
ate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two cycle instruction.
Description: CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT. Status
bits TO and PD are set.
DS30325A-page 114
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
COMF
Complement f
GOTO
Unconditional Branch
Syntax:
Operands:
[ label ] COMF f,d
Syntax:
[ label ] GOTO k
0 ≤ k ≤ 2047
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected: None
The contents of register ’f’ are
complemented. If ’d’ is 0, the
result is stored in W. If ’d’ is 1, the
result is stored back in register ’f’.
Description:
GOTOis an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTOis a two
cycle instruction.
INCF
Increment f
DECF
Decrement f
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
Operands:
[label] DECF f,d
0 ≤ f ≤ 127
d ∈ [0,1]
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination)
Operation:
(f) - 1 → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register ’f’ are
incremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
Decrement register ’f’. If ’d’ is 0,
the result is stored in the W regis-
ter. If ’d’ is 1, the result is stored
back in register ’f’.
DECFSZ
Syntax:
Decrement f, Skip if 0
INCFSZ
Syntax:
Increment f, Skip if 0
[ label ] DECFSZ f,d
[ label ] INCFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected: None
Status Affected: None
Description: The contents of register ’f’ are
Description:
The contents of register ’f’ are
decremented. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
incremented. If ’d’ is 0, the result is
placed in the W register. If ’d’ is 1,
the result is placed back in regis-
ter ’f’.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
then a NOPis executed instead
making it a 2TCY instruction.
If the result is 1, the next instruc-
tion is executed. If the result is 0,
a NOPis executed instead making
it a 2TCY instruction.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 115
PIC16F7X
IORLW
Inclusive OR Literal with W
MOVLW
Syntax:
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
Operands:
Operation:
Status Affected:
Description:
Operands:
Operation:
(W) .OR. k → (W)
Z
k → (W)
Status Affected: None
The contents of the W register are
OR’ed with the eight bit literal 'k'.
The result is placed in the W reg-
ister.
Description:
The eight bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
IORWF
Inclusive OR W with f
MOVWF
Syntax:
Move W to f
Syntax:
[ label ] IORWF f,d
[ label ] MOVWF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
(W) → (f)
Operation:
(W) .OR. (f) → (destination)
Status Affected: None
Status Affected:
Description:
Z
Description:
Move data from W register to reg-
ister 'f'.
Inclusive OR the W register with
register 'f'. If 'd' is 0 the result is
placed in the W register. If 'd' is 1
the result is placed back in regis-
ter 'f'.
MOVF
Move f
NOP
No Operation
[ label ] NOP
None
Syntax:
Operands:
[ label ] MOVF f,d
Syntax:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
No operation
Operation:
(f) → (destination)
Status Affected: None
Description: No operation.
Status Affected:
Description:
Z
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0, des-
tination is W register. If d = 1, the
destination is file register f itself. d
= 1 is useful to test a file register
since status flag Z is affected.
DS30325A-page 116
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2000 Microchip Technology Inc.
PIC16F7X
RETFIE
Return from Interrupt
[ label ] RETFIE
None
RLF
Rotate Left f through Carry
Syntax:
Syntax:
Operands:
[ label ] RLF f,d
Operands:
Operation:
0 ≤ f ≤ 127
d ∈ [0,1]
TOS → PC,
1 → GIE
Operation:
See description below
C
Status Affected: None
Status Affected:
Description:
The contents of register ’f’ are
rotated one bit to the left through
the Carry Flag. If ’d’ is 0, the
result is placed in the W register.
If ’d’ is 1, the result is stored back
in register ’f’.
C
Register f
RRF
Rotate Right f through Carry
RETLW
Return with Literal in W
Syntax:
Operands:
[ label ] RRF f,d
Syntax:
[ label ] RETLW k
0 ≤ k ≤ 255
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
Operation:
k → (W);
TOS → PC
Operation:
See description below
C
Status Affected:
Description:
Status Affected: None
The contents of register ’f’ are
rotated one bit to the right through
the Carry Flag. If ’d’ is 0, the result
is placed in the W register. If ’d’ is
1, the result is placed back in reg-
ister ’f’.
Description:
The W register is loaded with the
eight bit literal ’k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two cycle instruction.
C
Register f
SLEEP
RETURN
Syntax:
Return from Subroutine
[ label ] RETURN
None
Syntax:
[ label ] SLEEP
Operands:
Operation:
None
Operands:
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
TOS → PC
Status Affected: None
Description: Return from subroutine. The stack
0 → PD
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two cycle
instruction.
Status Affected:
Description:
TO, PD
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 117
PIC16F7X
SUBLW
Subtract W from Literal
XORLW
Exclusive OR Literal with W
[label] XORLW k
Syntax:
[ label ]
SUBLW k
Syntax:
Operands:
Operation:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
The W register is subtracted (2’s
The contents of the W register
are XOR’ed with the eight bit lit-
eral 'k'. The result is placed in
the W register.
complement method) from the
eight bit literal 'k'. The result is
placed in the W register.
XORWF
Syntax:
Exclusive OR W with f
SUBWF
Subtract W from f
Syntax:
[ label ]
SUBWF f,d
[label] XORWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (destination)
Operation:
(W) .XOR. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Description:
Z
Description:
Subtract (2’s complement method)
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
W register from register 'f'. If 'd' is 0,
the result is stored in the W regis-
ter. If 'd' is 1, the result is stored
back in register 'f'.
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected: None
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in W regis-
ter. If 'd' is 1, the result is placed in
register 'f'.
DS30325A-page 118
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
MPLAB allows you to:
14.0 DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- ICEPIC™
14.2
MPASM Assembler
• In-Circuit Debugger
MPASM is a full featured universal macro assembler
for all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- MPLAB-ICD for PIC16F87X
• Device Programmers
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
• Low-Cost Demonstration Boards
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- KEELOQ
MPASM features include:
14.1
MPLAB Integrated Development
Environment Software
• MPASM and MPLINK are integrated into MPLAB
projects.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows-based applica-
tion which contains:
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi pur-
pose source files.
• Multiple functionality
- editor
• MPASM directives allow complete control over the
assembly process.
- simulator
14.3
MPLAB-C17 and MPLAB-C18
C Compilers
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
• On-line help
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 119
PIC16F7X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
14.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive
development tools. The PC platform and Microsoft®
Windows 3.x/95/98 environment were chosen to best
make these features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
14.7
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of interchange-
able personality modules or daughter boards. The
emulator is capable of emulating without target applica-
tion circuitry being present.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
14.5
MPLAB-SIM Software Simulator
14.8
MPLAB-ICD In-Circuit Debugger
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
14.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30325A-page 120
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
14.9
PRO MATE II Universal Programmer
14.12 PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
14.10 PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
14.13 PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A
simple serial interface allows the user to construct a
hardware demultiplexer for the LCD signals.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
14.11 PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 121
PIC16F7X
14.14 PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS30325A-page 122
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 14-1: DEVELOPMENT TOOLS FROM MICROCHIP
0 1 5 2 P M C
X X X C R M F
H C S X X X
X X C 9 3
/ X X 2 5 C
/ X X 2 4 C
X X C 8 2 C 1 P I
X 7 X 7 C 1 C I P
X 4 1 7 C I C P
X 9 X 6 C 1 C I P
X 8 X 6 F 1 C I P
X 8 1 6 C I C P
X 7 X 6 C 1 C I P
X 7 1 6 C I C P
X 6 2 1 6 C I F P
X
X X C 6 C 1 P I
X 6 1 6 C I C P
X 5 1 6 C I C P
0 0 1 4 C I 0 P
X
X X C 2 C 1 P I
s o l T e o r a w f t S o o t r a s
E m r u l g e b e u g D s r
m m r a e P r o
t i s K a v l d E a n d s a r o B o m e D
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 123
PIC16F7X
NOTES:
DS30325A-page 124
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias.................................................................................................................-55 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR with respect to VSS (Note 2)...............................................................................................0 to +13.5V
Voltage on RA4 with respect to Vss...................................................................................................................0 to +12V
Total power dissipation (Note 1)................................................................................................................................1.0W
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA
Maximum current sunk by PORTC and PORTD (combined) (Note 3)..................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined) (Note 3).............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than pulling
this pin directly to VSS.
3: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 125
PIC16F7X
FIGURE 15-1: PIC16F7X VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
16 MHz
20 MHz
Frequency
FIGURE 15-2: PIC16LF7X VOLTAGE-FREQUENCY GRAPH
6.0 V
5.5 V
5.0 V
4.5 V
4.0 V
3.5 V
3.0 V
2.5 V
2.0 V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5 V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10MHz.
DS30325A-page 126
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
15.1
DC Characteristics
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16LF73/74/76/77
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16F73/74/76/77
(Industrial)
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D001
VDD
Supply Voltage
PIC16LF7X 2.0
PIC16F7X 4.0
-
5.5
V
All osc configurations (DC - 10 MHz)
D001
-
-
5.5
5.5
V
V
All configurations
BOR enabled (Note 7)
D001A
VBOR*
D002* VDR
D003
RAM Data Retention
Voltage (Note 1)
-
1.5
-
V
VPOR VDD Start Voltage to
ensure internal Power-on
Reset signal
-
VSS
-
V
See section on Power-on Reset for details
D004* SVDD VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05
-
-
V/ms See section on Power-on Reset for details
D005
D010
VBOR Brown-out Reset Voltage 3.65
4.0 4.35
0.6 2.0
V
BODEN bit in configuration word enabled
IDD
Supply Current (Note 2, 5)
PIC16LF7X
-
-
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
µA LP osc configuration
D010A
20
35
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
D010
D013
PIC16F7X
-
-
1.6
7
4
mA XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
mA HS osc configuration
15
FOSC = 20 MHz, VDD = 5.5V
D015* DIBOR Brown-out Reset Current
-
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 127
PIC16F7X
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16LF73/74/76/77
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
PIC16F73/74/76/77
(Industrial)
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
D020
IPD
Power-down Current (Note 3, 5)
PIC16LF7X
PIC16F7X
-
-
7.5
0.9
30
5
µA VDD = 3.0V, WDT enabled, -40°C to +85°C
µA VDD = 3.0V, WDT disabled, -40°C to +85°C
D021
D020
D021
-
-
10.5 42
1.5 19
µA VDD = 4.0V, WDT enabled, -40°C to +85°C
µA VDD = 4.0V, WDT disabled, -40°C to +85°C
D023* DIBOR Brown-out Reset Current
-
85 200 µA BOR enabled VDD = 5.0V
(Note 6)
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be esti-
mated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from character-
ization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
DS30325A-page 128
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
15.2
DC Characteristics:
PIC16F73/74/76/77 (Industrial)
PIC16LF73/74/76/77 (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
Operating voltage VDD range as described in DC spec Section 15.1
and Section 15.2.
DC CHARACTERISTICS
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
VIL
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
VSS
VSS
VSS
-
-
-
0.15VDD
0.8V
0.2VDD
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
with Schmitt Trigger buffer
D032
D033
MCLR, OSC1 (in RC mode)
OSC1 (in XT and LP mode)
OSC1 (in HS mode)
VSS
VSS
VSS
-
-
-
0.2VDD
0.3V
0.3VDD
V
V
V
(Note 1)
(Note 1)
Ports RC3 and RC4
D034
with Schmitt Trigger buffer
VSS
-
0.3VDD
V
For entire VDD range
VIH Input High Voltage
I/O ports
-
-
-
D040
D040A
with TTL buffer
2.0
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
0.25VDD
+ 0.8V
0.8VDD
D041
with Schmitt Trigger buffer
-
VDD
V
For entire VDD range
D042
D042A
MCLR
0.8VDD
1.6V
0.7VDD
0.9VDD
-
-
-
-
VDD
VDD
VDD
VDD
V
V
V
V
OSC1 (in XT and LP mode)
OSC1 (in HS mode)
OSC1 (in RC mode)
(Note 1)
(Note 1)
D043
Ports RC3 and RC4
D044
D070
with Schmitt Trigger buffer
IPURB PORTB Weak Pull-up Current
0.7VDD
50
-
VDD
400
V
For entire VDD range
250
µA VDD = 5V, VPIN = VSS
IIL Input Leakage Current (Notes 2, 3)
D060
I/O ports
-
-
±1
µA Vss ≤ VPIN ≤ VDD, Pin at
hi-impedance
D061
D063
MCLR, RA4/T0CKI
OSC1
-
-
-
-
±5
±5
µA Vss ≤ VPIN ≤ VDD
µA Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
VOL Output Low Voltage
D080
D083
I/O ports
-
-
-
-
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
OSC2/CLKOUT (RC osc config)
-40°C to +85°C
VOH Output High Voltage
D090
D092
D150*
I/O ports (Note 3)
OSC2/CLKOUT (RC osc config) VDD - 0.7
VOD Open-Drain High Voltage
VDD - 0.7
-
-
-
-
-
V
V
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
RA4 pin
-
12
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 129
PIC16F7X
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
Operating voltage VDD range as described in DC spec Section 15.1
and Section 15.2.
DC CHARACTERISTICS
Param Sym
No.
Characteristic
Min Typ† Max Units
Conditions
Capacitive Loading Specs on Output Pins
D100
D101
D102
COSC2 OSC2 pin
-
-
-
-
-
-
15
50
pF In XT, HS and LP modes when
external clock is used to drive OSC1
pF
CIO All I/O pins and OSC2
(in RC mode)
SCL, SDA in I2C mode
CB
400
pF
Program FLASH Memory
EP Endurance
VPR VDD for read
D130
D131
-
-
-
100
5.5
E/W 25°C at 5V
V
2.0
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16F7X be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30325A-page 130
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
15.3
Timing Parameter Symbology
The timing parameter symbols have been created fol-
lowing one of the following formats:
1. TppS2ppS
2. TppS
T
3. TCC:ST
4. Ts
(I2C specifications only)
(I2C specifications only)
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
T
Time
CCP1
CLKOUT
CS
osc
rd
OSC1
RD
ck
cs
di
rw
sc
ss
t0
RD or WR
SCK
SDI
do
dt
SDO
SS
Data in
I/O port
MCLR
T0CKI
T1CKI
WR
io
t1
mc
wr
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
I2C only
AA
output access
Bus free
High
Low
High
Low
BUF
TCC:ST (I2C specifications only)
CC
HD
ST
DAT
STA
Hold
SU
Setup
DATA input hold
START condition
STO
STOP condition
FIGURE 15-3: LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
CL
Pin
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16F73/76 devices.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 131
PIC16F7X
FIGURE 15-4: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
4
Q1
OSC1
1
3
4
3
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS
Parameter Sym Characteristic
No.
Min Typ†
Max
Units Conditions
FOSC External CLKIN Frequency
DC
DC
DC
DC
0.1
—
—
—
—
—
1
20
32
4
MHz XT osc mode
MHz HS osc mode
kHz LP osc mode
MHz RC osc mode
MHz XT osc mode
(Note 1)
Oscillator Frequency
(Note 1)
4
4
5
—
—
20
200
MHz HS osc mode
kHz LP osc mode
1
TOSC External CLKIN Period
1000
50
—
—
—
—
ns XT osc mode
ns HS osc mode
ms LP osc mode
ns RC osc mode
ns XT osc mode
ns HS osc mode
ms LP osc mode
ns TCY = 4/FOSC
(Note 1)
5
—
—
Oscillator Period
(Note 1)
250
250
50
—
—
—
10,000
250
—
—
5
—
2
3
TCY Instruction Cycle Time
200
TCY
DC
(Note 1)
TosL, External Clock in (OSC1) High 500
TosH or Low Time
—
—
—
—
—
—
—
—
—
25
50
15
ns XT oscillator
ms LP oscillator
ns HS oscillator
ns XT oscillator
ns LP oscillator
ns HS oscillator
2.5
15
—
4
TosR, External Clock in (OSC1) Rise
TosF or Fall Time
—
—
Legend: † Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at "min." values with an external
clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is
"DC" (no clock) for all devices.
DS30325A-page 132
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-5: CLKOUT AND I/O TIMING
Q1
Q2
Q3
Q4
OSC1
11
10
CLKOUT
13
14
12
18
19
16
I/O Pin
(input)
15
17
I/O Pin
new value
old value
(output)
20, 21
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
10*
11*
12*
13*
14*
15*
16*
17*
TosH2ckL OSC1↑ to CLKOUT↓
TosH2ckH OSC1↑ to CLKOUT↑
—
75
75
35
35
—
200
200
ns
ns
ns
ns
ns
ns
ns
ns
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
—
TckR
TckF
CLKOUT rise time
CLKOUT fall time
—
100
—
100
TckL2ioV CLKOUT ↓ to Port out valid
TioV2ckH Port in valid before CLKOUT ↑
—
0.5TCY + 20
—
TOSC + 200
—
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
TosH2ioV OSC1↑ (Q1 cycle) to
—
100
255
Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
Standard (F)
100
200
—
—
—
—
ns
ns
Extended (LF)
19*
20*
TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
10
—
10
—
—
—
—
40
ns
ns
ns
ns
ns
ns
ns
TioR
Port output rise time
Port output fall time
INT pin high or low time
Standard (F)
Extended (LF)
Standard (F)
Extended (LF)
—
—
145
40
21*
TioF
—
—
145
—
22††* Tinp
23††* Trbp
Tcy
Tcy
RB7:RB4 change INT high or low time
—
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 133
PIC16F7X
FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-7: BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
Watchdog Timer Time-out Period
(No Prescaler)
2
7
—
—
µs
VDD = 5V, -40°C to +85°C
31*
Twdt
18
33
ms VDD = 5V, -40°C to +85°C
32
Tost
Oscillation Start-up Timer Period
Power-up Timer Period
—
1024 TOSC
72
—
—
TOSC = OSC1 period
33*
Tpwrt
28
132
ms VDD = 5V, -40°C to +85°C
µs
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
—
—
2.1
35
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
VDD ≤ VBOR (D005)
Legend:
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS30325A-page 134
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units
Conditions
40* Tt0H
41* Tt0L
42* Tt0P
T0CKI High Pulse Width
No Prescaler
With Prescaler
No Prescaler
With Prescaler
No Prescaler
With Prescaler
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 42
10
ns
T0CKI Low Pulse Width
T0CKI Period
0.5TCY + 20
ns Must also meet
parameter 42
10
ns
ns
TCY + 40
Greater of:
20 or TCY + 40
ns N = prescale value
(2, 4, ..., 256)
N
45* Tt1H
46* Tt1L
47* Tt1P
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Must also meet
parameter 47
Synchronous,
Standard(F)
15
ns
ns
ns
ns
Prescaler = 2,4,8
Extended(LF)
25
Asynchronous Standard(F)
Extended(LF)
30
50
T1CKI Low Time Synchronous, Prescaler = 1
0.5TCY + 20
ns Must also meet
parameter 47
Synchronous,
Standard(F)
15
ns
ns
ns
ns
Prescaler = 2,4,8
Extended(LF)
25
Asynchronous Standard(F)
Extended(LF)
30
50
T1CKIinputperiod Synchronous
Standard(F)
Greater of:
30 OR TCY + 40
ns N = prescale value
(1, 2, 4, 8)
N
Extended(LF)
Greater of:
50 OR TCY + 40
N = prescale value
(1, 2, 4, 8)
N
60
Asynchronous Standard(F)
Extended(LF)
—
—
—
—
—
ns
ns
100
DC
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
200 kHz
48
2Tosc
—
7Tosc
—
Legend:
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 135
PIC16F7X
FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or PWM Mode)
53
Note: Refer to Figure 15-3 for load conditions.
54
TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Param Sym
No.
Characteristic
Min
Typ† Max Units
Conditions
50* TccL CCP1 and CCP2 No Prescaler
input low time
0.5TCY + 20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Standard(F)
10
With Prescaler
Extended(LF)
20
0.5TCY + 20
10
51* TccH CCP1 and CCP2 No Prescaler
input high time
Standard(F)
With Prescaler
Extended(LF)
20
52* TccP CCP1 and CCP2 input period
3TCY + 40
N
ns N = prescale
value (1,4 or 16)
53* TccR CCP1 and CCP2 output rise time Standard(F)
Extended(LF)
—
—
—
—
10
25
10
25
25
50
25
45
ns
ns
ns
ns
54* TccF CCP1 and CCP2 output fall time
Standard(F)
Extended(LF)
Legend:
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS30325A-page 136
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-10: PARALLEL SLAVE PORT TIMING (PIC16F74/77 DEVICES ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F74/77 DEVICES ONLY)
Parameter
No.
Sym
Characteristic
Min Typ† Max Units Conditions
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
25
—
—
—
—
ns
ns Extended
Range Only
63*
64
TwrH2dtI
TrdL2dtV
WR↑ or CS↑ to data in invalid (hold time) Standard(F)
Extended(LF)
20
35
—
—
—
—
—
—
—
—
80
90
ns
ns
ns
RD↓ and CS↓ to data out valid
ns Extended
Range Only
65
TrdH2dtI
RD↑ or CS↓ to data out invalid
10
—
30
ns
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 137
PIC16F7X
FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
SCK
(CKP = 1)
78
80
BIT6 - - - - - -1
MSb
LSb
SDO
SDI
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 15-3 for load conditions.
DS30325A-page 138
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
SCK
(CKP = 1)
78
80
MSb
LSb
SDO
SDI
BIT6 - - - - - -1
77
75, 76
MSb IN
74
BIT6 - - - -1
LSb IN
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-14: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
70
SCK
83
(CKP = 0)
71
72
SCK
(CKP = 1)
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
MSb IN
74
LSb IN
Note: Refer to Figure 15-3 for load conditions.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 139
PIC16F7X
TABLE 15-7: SPI MODE REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max Units Conditions
70*
TssL2scH,
TssL2scL
TscH
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71*
72*
73*
SCK input high time (Slave mode)
SCK input low time (Slave mode)
Setup time of SDI data input to SCK edge
TCY + 20
TCY + 20
100
—
—
—
—
—
—
ns
ns
ns
TscL
TdiV2scH,
TdiV2scL
TscH2diL,
TscL2diL
TdoR
74*
75*
76*
Hold time of SDI data input to SCK edge
100
—
—
ns
SDO data output rise time
Standard(F)
Extended(LF)
—
—
—
10
25
10
25
50
25
ns
ns
ns
TdoF
SDO data output fall time
77*
78*
TssH2doZ
TscR
SS↑ to SDO output hi-impedance
SCK output rise time (Master mode) Standard(F)
Extended(LF)
10
—
—
—
—
—
—
10
25
10
—
—
50
25
50
ns
ns
ns
ns
ns
ns
79*
80*
TscF
SCK output fall time (Master mode)
SDO data output valid after SCK Standard(F)
edge
25
TscH2doV,
50
145
Extended(LF)
TscL2doV
81*
TdoV2scH,
SDO data output setup to SCK edge
TCY
—
—
ns
TdoV2scL
TssL2doV
82*
83*
SDO data output valid after SS↓ edge
SS ↑ after SCK edge
—
—
—
50
ns
ns
TscH2ssH,
TscL2ssH
1.5TCY + 40
—
Legend: * These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 15-15: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 15-3 for load conditions.
DS30325A-page 140
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
TABLE 15-8: I2C BUS START/STOP BITS REQUIREMENTS
Param
Sym
Characteristic
Min Typ Max Units
Conditions
No.
90*
TSU:STA START condition 100 kHz mode
Setup time 400 kHz mode
THD:STA START condition 100 kHz mode
4700
600
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns Only relevant for Repeated
START condition
91*
92*
93
4000
600
ns After this period the first clock
pulse is generated
Hold time
TSU:STO STOP condition
Setup time
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
ns
THD:STO STOP condition
Hold time
4000
600
ns
* These parameters are characterized but not tested.
FIGURE 15-16: I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 15-3 for load conditions.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 141
PIC16F7X
TABLE 15-9: I2C BUS DATA REQUIREMENTS
Param.
Sym
Characteristic
Min
Max Units
Conditions
No.
100*
THIGH
Clock high time
100 kHz mode
4.0
—
—
µs
µs
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
0.6
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
101*
TLOW
Clock low time
µs
µs
Device must operate at a
minimum of 1.5 MHz
Device must operate at a
minimum of 10 MHz
400 kHz mode
SSP Module
1.3
—
1.5TCY
—
102*
103*
TR
TF
SDA and SCL rise 100 kHz mode
—
1000
ns
ns
time
400 kHz mode
20 + 0.1Cb 300
Cb is specified to be from
10-400 pF
SDA and SCL fall
time
100 kHz mode
400 kHz mode
—
300
ns
ns
20 + 0.1Cb 300
Cb is specified to be from
10-400 pF
90*
91*
TSU:STA START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
—
—
—
—
—
0.9
—
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Only relevant for Repeated
START condition
THD:STA START condition
hold time
After this period the first
clock pulse is generated
106*
107*
92*
THD:DAT Data input hold time 100 kHz mode
400 kHz mode
TSU:DAT Data input setup
time
0
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
250
100
4.7
0.6
—
—
4.7
1.3
(Note 2)
TSU:STO STOP condition
setup time
109*
110*
TAA
Output valid from
clock
3500
—
—
(Note 1)
TBUF
Bus free time
Time the bus must be free
before a new transmission
can start
—
Cb
Bus capacitive loading
—
400
pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast mode (400 kHz) I2C-bus device can be used in a standard mode (100 kHz) I2C bus system, but the
requirement Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the
standard mode I2C bus specification), before the SCL line is released.
DS30325A-page 142
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
Pin
121
121
RC7/RX/DT
Pin
120
122
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ† Max Units Conditions
120
TckH2dtV
SYNC XMIT (MASTER &
Standard(F)
SLAVE)
Clock high to data out valid
—
—
—
—
—
—
—
—
—
—
—
—
80
100
45
ns
ns
ns
ns
ns
ns
Extended(LF)
121
122
Tckrf
Tdtrf
Clock out rise time and fall time Standard(F)
(Master mode)
Extended(LF)
50
Data out rise time and fall time Standard(F)
Extended(LF)
45
50
†: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 15-18: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
125
pin
RC7/RX/DT
pin
126
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
15
—
—
—
—
ns
ns
126
TckL2dtl
Data hold after CK ↓ (DT hold time)
†:
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 143
PIC16F7X
TABLE 15-12: A/D CONVERTER CHARACTERISTICS: PIC16F7X (INDUSTRIAL)
PIC16LF7X (INDUSTRIAL)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR Resolution
PIC16F7X
—
—
8 bits
bit VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
PIC16LF7X
—
—
—
—
8 bits
< ± 1
bit VREF = VDD = 2.0V
A02
A03
A04
A05
A06
EABS Total Absolute error
EIL Integral linearity error
EDL Differential linearity error
EFS Full scale error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
—
—
—
—
—
—
—
—
< ± 1
< ± 1
< ± 1
< ± 1
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
EOFF Offset error
LSb VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
A20
A25
A30
—
Monotonicity (Note 3)
—
2.0V
guaranteed
—
—
V
VSS ≤ VAIN ≤ VREF
VREF Reference voltage
VAIN Analog input voltage
—
—
—
VDD + 0.3
VREF + 0.3
10.0
VSS - 0.3
—
V
ZAIN Recommended impedance of
analog voltage source
kΩ
A40
A50
IAD A/D conversion PIC16F7X
—
—
180
90
—
—
µA Average current con-
current (VDD)
sumption when A/D is
PIC16LF7X
µA
on (Note 1).
IREF VREF input current (Note 2)
10
—
1000
µA During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see
Section 12.1.
During A/D Conversion
cycle.
10
µA
—
—
* These parameters are characterized but not tested.
†Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current
spec includes any such leakage from the A/D module.
2: VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS30325A-page 144
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
FIGURE 15-19: A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2)(1)
134
131
130
Q4
132
A/D CLK
7
6
5
4
3
2
1
0
A/D DATA
NEW_DATA
DONE
OLD_DATA
ADRES
ADIF
GO
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param
Sym
Characteristic
Min
Typ† Max Units
Conditions
No.
130
TAD A/D clock period
PIC16F7X
1.6
2.0
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
PIC16LF7X
µs TOSC based,
2.0V ≤ VREF ≤ 5.5V
PIC16F7X
2.0
3.0
9
4.0
6.0
—
6.0
9.0
9
µs A/D RC mode
µs A/D RC mode
TAD
PIC16LF7X
131 TCNV Conversion time (not including S/H
time) (Note 1)
132 TACQ Acquisition time
5*
—
—
µs The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1 LSb
(i.e., 20.0 mV @ 5.12V) from
the last sampled voltage (as
stated on CHOLD).
134
TGO Q4 to A/D clock start
—
TOSC/2
—
—
—
If the A/D clock source is
selected as RC, a time of TCY
is added before the A/D clock
starts. This allows the SLEEP
instruction to be executed.
135 TSWC Switching from convert → sample time 1.5 §
—
TAD
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 12.1 for min. conditions.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 145
PIC16F7X
NOTES:
DS30325A-page 146
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
16.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
The graphs and tables provided in this section are for
design guidance and are not tested.
In some graphs or tables, the data presented are out-
side specified operating range (i.e., outside specified
VDD range). This is for information only and devices
are ensured to operate properly only within the speci-
fied range.
The data presented in this section is a statistical sum-
mary of data collected on units from different lots over
a period of time and matrix samples. ’Typical’ repre-
sents the mean of the distribution at 25°C. ’Max’ or ’Min’
represents (mean + 3σ) or (mean - 3σ), respectively,
where σ is standard deviation over the whole tempera-
ture range.
Graphs and Tables not available at this time.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 147
PIC16F7X
NOTES:
DS30325A-page 148
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
17.0 PACKAGING INFORMATION
17.1
Package Marking Information
28-Lead PDIP (Skinny DIP)
Example
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16F77-I/SP
YYWWNNN
0017HAT
28-Lead SOIC
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
PIC16F76-I/SO
0010SAA
YYWWNNN
28-Lead SSOP
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16F73-I/SS
0010SBP
YYWWNNN
Legend: XX...X Customer specific information*
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, and traceability code. For
marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For
QTP devices, any special marking adders are included in QTP price.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 149
PIC16F7X
Package Marking Information (Cont’d)
40-Lead PDIP
Example
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F77-I/P
0012SAA
44-Lead TQFP
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F77-
I/PT
0011HAT
44-Lead PLCC
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
PIC16F77-I/L
0003SAT
DS30325A-page 150
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
17.2
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 151
PIC16F7X
17.3
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
1
n
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS30325A-page 152
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
17.4
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
NOM MAX
Dimension Limits
MIN
MAX
MIN
n
p
Number of Pins
Pitch
28
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
Overall Height
A
.068
.078
1.73
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.63
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 153
PIC16F7X
17.5
40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
1
α
n
E
A2
A
L
c
B1
B
β
A1
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
40
MAX
n
p
Number of Pins
Pitch
40
.100
.175
.150
2.54
Top to Seating Plane
A
.160
.190
.160
4.06
3.56
4.45
3.81
4.83
4.06
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.530
2.045
.120
.008
.030
.014
.620
5
0.38
15.11
13.46
51.94
3.05
0.20
0.76
0.36
15.75
5
.600
.545
2.058
.130
.012
.050
.018
.650
10
.625
.560
2.065
.135
.015
.070
.022
.680
15
15.24
13.84
52.26
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
52.45
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
§
eB
α
β
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
5
10
15
5
10
15
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-016
DS30325A-page 154
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
17.6
44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)
E
E1
#leads=n1
p
D1
D
2
1
B
n
°
CH x 45
α
A
c
φ
β
A1
A2
L
(F)
Units
INCHES
NOM
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.031
11
0.80
11
Pins per Side
Overall Height
n1
A
.039
.037
.002
.018
.043
.039
.004
.024
.039
3.5
.047
1.00
0.95
1.10
1.00
0.10
0.60
1.20
Molded Package Thickness
Standoff
A2
A1
L
(F)
φ
.041
.006
.030
1.05
0.15
0.75
§
0.05
0.45
1.00
0
Foot Length
Footprint (Reference)
Foot Angle
0
.463
.463
.390
.390
.004
.012
.025
5
7
.482
.482
.398
.398
.008
.017
.045
15
3.5
12.00
12.00
10.00
10.00
0.15
0.38
0.89
10
7
12.25
12.25
10.10
10.10
0.20
0.44
1.14
15
Overall Width
E
D
.472
.472
.394
.394
.006
.015
.035
10
11.75
11.75
9.90
9.90
0.09
0.30
0.64
5
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
E1
D1
c
Lead Width
B
CH
α
Pin 1 Corner Chamfer
Mold Draft Angle Top
Mold Draft Angle Bottom
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-026
Drawing No. C04-076
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 155
PIC16F7X
17.7
44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)
E
E1
#leads=n1
D
D1
n 1 2
CH2 x 45°
CH1 x 45°
α
A3
A2
A
35°
B1
B
c
A1
β
p
E2
D2
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
44
MAX
n
p
Number of Pins
Pitch
44
.050
11
1.27
11
Pins per Side
Overall Height
n1
A
.165
.145
.020
.024
.040
.000
.685
.685
.650
.650
.590
.590
.008
.026
.013
0
.173
.153
.028
.029
.045
.005
.690
.690
.653
.653
.620
.620
.011
.029
.020
5
.180
4.19
3.68
0.51
0.61
1.02
0.00
17.40
17.40
16.51
16.51
14.99
14.99
0.20
0.66
0.33
0
4.39
3.87
0.71
0.74
1.14
0.13
17.53
17.53
16.59
16.59
15.75
15.75
0.27
0.74
0.51
5
4.57
Molded Package Thickness
Standoff
A2
A1
A3
CH1
CH2
E
.160
.035
.034
.050
.010
.695
.695
.656
.656
.630
.630
.013
.032
.021
10
4.06
0.89
0.86
1.27
0.25
17.65
17.65
16.66
16.66
16.00
16.00
0.33
0.81
0.53
10
§
Side 1 Chamfer Height
Corner Chamfer 1
Corner Chamfer (others)
Overall Width
Overall Length
D
Molded Package Width
Molded Package Length
Footprint Width
E1
D1
E2
D2
c
Footprint Length
Lead Thickness
Upper Lead Width
Lower Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
B1
B
α
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-047
Drawing No. C04-048
DS30325A-page 156
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
APPENDIX A: REVISION HISTORY
Version
Date
Revision Description
A
2000
This is a new data sheet. However, these devices are similar to the PIC16C7X
devices found in the PIC16C7X Data Sheet (DS30390) or the PIC16F87X
devices (DS30292).
APPENDIX B: DEVICE DIFFERENCES
The differences between the devices in this data sheet
are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Difference
PIC16F76/73
5 channels, 8-bits
PIC16F77/74
8 channels, 8-bits
A/D
Parallel Slave Port
Packages
no
yes
28-pin PDIP, 28-pin SOIC, 28-pin SSOP 40-pin PDIP, 44-pin TQFP, 44-pin PLCC
APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions
of devices to the ones listed in this data sheet are listed
in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16C7X
Characteristic
PIC16F87X
PIC16F7X
Pins
28/40
3
28/40
28/40
3
Timers
3
Interrupts
Communication
11 or 12
13 or 14
11 or 12
PSP, USART, SSP (SPI,
I2C Slave)
PSP, USART, SSP (SPI,
I2C Master/Slave)
PSP, USART, SSP (SPI,
I2C Slave)
Frequency
A/D
20 MHz
20 MHz
10-bit
2
20 MHz
8-bit
2
8-bit
CCP
2
Program Memory
4K, 8K EPROM
4K, 8K FLASH
4K, 8K FLASH
(1,000 E/W cycles)
(100 E/W cycles)
RAM
192, 368 bytes
192, 368 bytes
128, 256 bytes
192, 368 bytes
EEPROM Data
Other
None
None
—
In-Circuit Debugger,
—
Low Voltage Programming
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 157
PIC16F7X
NOTES:
DS30325A-page 158
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
INDEX
A
C
A/D ..................................................................................... 89
ADCON0 Register ...................................................... 89
ADCON1 Register ...................................................... 90
Analog Input Model Block Diagram ............................ 92
Analog Port Pins ...................................... 7, 8, 9, 37, 38
Analog-to-Digital Converter ........................................ 89
Block Diagram ............................................................ 91
Configuring Analog Port Pins ..................................... 93
Configuring the Interrupt ............................................ 91
Configuring the Module .............................................. 91
Conversion Clock ....................................................... 93
Conversions ............................................................... 93
Converter Characteristics ........................................ 144
Effects of a RESET .................................................... 93
Faster Conversion - Lower Resolution Trade-off ....... 93
Internal Sampling Switch (Rss) Impedance ............... 92
Operation During SLEEP ........................................... 93
Sampling Requirements ............................................. 92
Source Impedance ..................................................... 92
Timing Diagram ........................................................ 145
Using the CCP Trigger ............................................... 93
Absolute Maximum Ratings ............................................. 125
ACK .............................................................................. 67, 69
ADRES Register .......................................................... 15, 89
Analog Port Pins. See A/D
Capture/Compare/PWM
Capture
Block Diagram ................................................... 57
CCP1CON Register ........................................... 56
CCP1IF .............................................................. 57
Mode ................................................................. 57
Prescaler ........................................................... 57
CCP Timer Resources ............................................... 55
Compare
Block Diagram ................................................... 58
Mode ................................................................. 58
Software Interrupt Mode .................................... 58
Special Event Trigger ........................................ 58
Special Trigger Output of CCP1 ........................ 58
Special Trigger Output of CCP2 ........................ 58
Interaction of Two CCP Modules ............................... 55
Section ....................................................................... 55
Special Event Trigger and A/D Conversions ............. 58
Capture/Compare/PWM (CCP)
CCP1
RC2/CCP1 Pin ................................................. 7, 8
CCP2
RC1/T1OSI/CCP2 Pin ..................................... 7, 8
PWM Block Diagram ................................................. 58
PWM Mode ................................................................ 58
CCP1CON ......................................................................... 17
CCP2CON ......................................................................... 17
CCPR1H Register .................................................. 15, 17, 55
CCPR1L Register ........................................................ 17, 55
CCPR2H Register ........................................................ 15, 17
CCPR2L Register ........................................................ 15, 17
CCPxM0 bit ........................................................................ 56
CCPxM1 bit ........................................................................ 56
CCPxM2 bit ........................................................................ 56
CCPxM3 bit ........................................................................ 56
CCPxX bit .......................................................................... 56
CCPxY bit .......................................................................... 56
CKE ................................................................................... 62
CKP ................................................................................... 63
Clock Polarity Select bit, CKP ............................................ 63
Code Examples
Application Notes
AN552 (Implementing Wake-up on Key Strokes
Using PIC16F7X) ....................................................... 31
AN556 (Table Reading Using PIC16CXX) ................. 26
2
AN578 (Use of the SSP Module in the I C
Multi-Master Environment) ......................................... 61
Architecture
PIC16F73/PIC16F76 Block Diagram ........................... 5
PIC16F74/PIC16F77 Block Diagram ........................... 6
Assembler
MPASM Assembler .................................................. 119
B
Banking, Data Memory ...................................................... 12
BF ................................................................................ 62, 67
Block Diagrams
A/D ............................................................................. 91
Analog Input Model .................................................... 92
Capture ...................................................................... 57
Compare .................................................................... 58
Call of a Subroutine in Page 1 from Page 0 .............. 26
Indirect Addressing .................................................... 27
Code Protection ......................................................... 95, 110
Computed GOTO ............................................................... 26
Configuration Bits .............................................................. 95
Conversion Considerations .............................................. 157
2
I C Mode .................................................................... 67
PWM .......................................................................... 58
2
SSP in I C Mode ........................................................ 67
D
SSP in SPI Mode ....................................................... 64
Timer0/WDT Prescaler .............................................. 45
Timer2 ........................................................................ 53
USART Receive ......................................................... 79
USART Transmit ........................................................ 77
BOR. See Brown-out Reset
BRGH bit ............................................................................ 75
Brown-out Reset (BOR) ............................... 95, 99, 101, 102
Buffer Full Status bit, BF .................................................... 62
D/A ..................................................................................... 62
Data Memory ..................................................................... 12
Bank Select (RP1:RP0 Bits) ...................................... 12
General Purpose Registers ....................................... 12
Register File Map ................................................ 13, 14
Special Function Registers ........................................ 15
Data/Address bit, D/A ........................................................ 62
DC Characteristics ........................................................... 127
Development Support ...................................................... 119
Device Differences ........................................................... 157
Device Overview .................................................................. 5
Direct Addressing .............................................................. 27
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 159
PIC16F7X
SLEEP ..................................................................... 117
SUBLW .................................................................... 118
SUBWF .................................................................... 118
SWAPF .................................................................... 118
XORLW ................................................................... 118
XORWF ................................................................... 118
Summary Table ....................................................... 112
INT Interrupt (RB0/INT). See Interrupt Sources
INTCON ............................................................................. 17
INTCON Register ............................................................... 20
GIE Bit ....................................................................... 20
INTE Bit ......................................................... 20, 21, 22
INTF Bit ..................................................................... 20
RBIF Bit ......................................................... 20, 21, 31
T0IE Bit ...................................................................... 20
Internal Sampling Switch (Rss) Impedance ....................... 92
Interrupt Sources ....................................................... 95, 105
Block Diagram ......................................................... 105
Interrupt on Change (RB7:RB4 ) ............................... 31
RB0/INT Pin, External ...................................... 7, 8, 106
TMR0 Overflow ........................................................ 106
USART Receive/Transmit Complete ......................... 73
Interrupts
E
Electrical Characteristics ..................................................125
Errata ...................................................................................4
External Clock Input (RA4/T0CKI). See Timer0
External Interrupt Input (RB0/INT). See Interrupt Sources
F
Firmware Instructions .......................................................111
FSR Register ....................................................15, 16, 17, 27
I
I/O Ports .............................................................................29
2
I C
Addressing .................................................................68
Block Diagram ............................................................67
I C Operation .............................................................67
2
Master Mode ..............................................................71
Mode ..........................................................................67
Mode Selection ..........................................................67
Multi-Master Mode .....................................................71
Reception ...................................................................69
Reception Timing Diagram ........................................69
SCL and SDA pins .....................................................67
Slave Mode ................................................................67
Transmission ..............................................................70
Synchronous Serial Port Interrupt .............................. 22
Interrupts, Context Saving During .................................... 106
Interrupts, Enable Bits
2
I C (SSP Module)
Global Interrupt Enable (GIE Bit) ....................... 20, 105
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ................................................................. 106
RB0/INT Enable (INTE Bit) ............................ 20, 21, 22
TMR0 Overflow Enable (T0IE Bit) ............................. 20
Interrupts, Flag Bits
Timing Diagram, Data ..............................................141
Timing Diagram, Start/Stop Bits ...............................140
ID Locations ............................................................... 95, 110
In-Circuit Serial Programming (ICSP) ........................95, 110
INDF ...................................................................................17
INDF Register ........................................................ 15, 16, 27
Indirect Addressing ............................................................27
FSR Register .............................................................12
Instruction Format ............................................................111
Instruction Set ..................................................................111
ADDLW ....................................................................113
ADDWF ....................................................................113
ANDLW ....................................................................113
ANDWF ....................................................................113
BCF ..........................................................................113
BSF ..........................................................................113
BTFSC .....................................................................114
BTFSS .....................................................................114
CALL ........................................................................114
CLRF ........................................................................114
CLRW ......................................................................114
CLRWDT ..................................................................114
COMF ......................................................................115
DECF .......................................................................115
DECFSZ ...................................................................115
GOTO ......................................................................115
INCF .........................................................................115
INCFSZ ....................................................................115
IORLW .....................................................................116
IORWF .....................................................................116
MOVF .......................................................................116
MOVLW ...................................................................116
MOVWF ...................................................................116
NOP .........................................................................116
RETFIE ....................................................................117
RETLW ....................................................................117
RETURN ..................................................................117
RLF ..........................................................................117
RRF ..........................................................................117
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ............................................... 20, 21, 31, 106
RB0/INT Flag (INTF Bit) ............................................ 20
TMR0 Overflow Flag (T0IF Bit) ................................ 106
K
KEELOQ Evaluation and Programming Tools ................ 122
L
Loading of PC .................................................................... 26
M
Master Clear (MCLR) ....................................................... 7, 8
MCLR Reset, Normal Operation ................ 99, 101, 102
MCLR Reset, SLEEP ................................. 99, 101, 102
Memory Organization
Data Memory ............................................................. 12
Program Memory ....................................................... 11
MPLAB Integrated Development
Environment Software ..................................................... 119
O
OPCODE Field Descriptions ............................................ 111
OPTION ............................................................................. 17
OPTION_REG Register ..................................................... 19
INTEDG Bit ................................................................ 19
PS2:PS0 Bits ............................................................. 19
PSA Bit ................................................................ 19, 20
RBPU Bit ................................................................... 19
T0CS Bit .................................................................... 19
T0SE Bit .................................................................... 19
OSC1/CLKIN Pin ............................................................. 7, 8
OSC2/CLKOUT Pin ......................................................... 7, 8
DS30325A-page 160
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
Oscillator Configuration ................................................ 95, 97
HS ...................................................................... 97, 101
LP ....................................................................... 97, 101
RC ................................................................ 97, 98, 101
XT ...................................................................... 97, 101
Oscillator, WDT ................................................................ 107
Output of TMR2 ................................................................. 53
PORTB Register ................................................................ 15
PORTC ...................................................................... 7, 8, 17
Block Diagram ........................................................... 33
PORTC Register ........................................................ 33
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin ............................................. 7, 8
RC2/CCP1 Pin ......................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 8
RC4/SDI/SDA Pin .................................................... 7, 8
RC5/SDO Pin .......................................................... 7, 8
RC6/TX/CK Pin .................................................. 7, 8, 74
RC7/RX/DT Pin ........................................... 7, 8, 74, 75
TRISC Register ................................................... 33, 73
PORTC Register ................................................................ 15
PORTD .................................................................... 9, 17, 38
Block Diagram ........................................................... 34
Parallel Slave Port (PSP) Function ............................ 34
PORTD Register ........................................................ 34
TRISD Register ......................................................... 34
PORTD Register ................................................................ 15
PORTE .......................................................................... 9, 17
Analog Port Pins .............................................. 9, 37, 38
Block Diagram ........................................................... 35
Input Buffer Full Status (IBF Bit) ................................ 36
Input Buffer Overflow (IBOV Bit) ................................ 36
PORTE Register ........................................................ 35
PSP Mode Select (PSPMODE Bit) ................ 34, 35, 38
RE0/RD/AN5 Pin ............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................ 9, 37, 38
RE2/CS/AN7 Pin ............................................. 9, 37, 38
TRISE Register .......................................................... 35
PORTE Register ................................................................ 15
Postscaler, WDT
P
P ......................................................................................... 62
Packaging ........................................................................ 149
Paging, Program Memory ............................................ 11, 26
Parallel Slave Port (PSP) ......................................... 9, 34, 38
Block Diagram ............................................................ 38
RE0/RD/AN5 Pin .............................................. 9, 37, 38
RE1/WR/AN6 Pin ............................................. 9, 37, 38
RE2/CS/AN7 Pin .............................................. 9, 37, 38
Read Waveforms ....................................................... 39
Select (PSPMODE Bit) .................................. 34, 35, 38
Write Waveforms ....................................................... 39
PCFG0 bit .......................................................................... 90
PCFG1 bit .......................................................................... 90
PCFG2 bit .......................................................................... 90
PCL Register .................................................... 15, 16, 17, 26
PCLATH Register ............................................ 15, 16, 17, 26
PCON Register .................................................... 17, 25, 100
POR Bit ...................................................................... 25
PIC16F76 Pinout Description ............................................... 7
PICDEM-1 Low-Cost PICmicro Demo Board ................... 121
PICDEM-2 Low-Cost PIC16CXX Demo Board ................ 121
PICDEM-3 Low-Cost PIC16CXXX Demo Board .............. 121
PICSTART Plus Entry Level Development System ...... 121
PIE1 Register ............................................................... 17, 21
PIE2 Register ............................................................... 17, 23
Pinout Descriptions
PIC16F73/PIC16F76 .................................................... 7
PIC16F74/PIC16F77 .................................................... 8
PIR1 Register ..................................................................... 22
PIR2 Register ..................................................................... 24
POP ................................................................................... 26
POR. See Power-on Reset
PORTA ....................................................................... 7, 8, 17
Analog Port Pins ...................................................... 7, 8
Initialization ................................................................ 29
PORTA Register ........................................................ 29
RA3
Assignment (PSA Bit) .......................................... 19, 20
Rate Select (PS2:PS0 Bits) ....................................... 19
Power-down Mode. See SLEEP
Power-on Reset (POR) ........................ 95, 99, 100, 101, 102
Oscillator Start-up Timer (OST) ......................... 95, 100
POR Status (POR Bit) ............................................... 25
Power Control (PCON) Register .............................. 100
Power-down (PD Bit) ................................................. 99
Power-up Timer (PWRT) ................................... 95, 100
Time-out (TO Bit) ................................................. 18, 99
Time-out Sequence on Power-up .................... 103, 104
PR2 .................................................................................... 17
PR2 Register ............................................................... 16, 53
Prescaler, Timer0
RA0 and RA5 Port Pins ..................................... 29
RA4/T0CKI Pin ................................................... 7, 8, 29
RA5/SS/AN4 Pin ...................................................... 7, 8
TRISA Register .......................................................... 29
PORTA Register ................................................................ 15
PORTB ....................................................................... 7, 8, 17
PORTB Register ........................................................ 31
Pull-up Enable (RBPU Bit) ......................................... 19
RB0/INT Edge Select (INTEDG Bit) ........................... 19
RB0/INT Pin, External ...................................... 7, 8, 106
RB3:RB0 Port Pins .................................................... 31
RB7:RB4 Interrupt-on-Change ................................. 106
RB7:RB4 Interrupt-on-Change Enable
Assignment (PSA Bit) .......................................... 19, 20
Rate Select (PS2:PS0 Bits) ....................................... 19
PRO MATE II Universal Programmer ............................ 121
Program Counter
RESET Conditions ................................................... 101
Program Memory ............................................................... 11
Interrupt Vector .......................................................... 11
Paging ................................................................. 11, 26
Program Memory Map ............................................... 11
Reset Vector .............................................................. 11
Program Verification ........................................................ 110
Programming Pin (VPP) ................................................... 7, 8
Programming, Device Instructions ................................... 111
PUSH ................................................................................. 26
(RBIE Bit) ................................................................. 106
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ............................................... 20, 21, 31, 106
RB7:RB4 Port Pins .................................................... 31
TRISB Register .......................................................... 31
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 161
PIC16F7X
Special Function Registers ................................................ 15
PIC16F73 .................................................................. 15
PIC16F74 .................................................................. 15
Speed, Operating ................................................................. 1
SPI
R
R/W ....................................................................................62
R/W bit ................................................................... 68, 69, 70
RAM. See Data Memory
RCREG ..............................................................................17
RCSTA Register ........................................................... 17, 74
OERR Bit ...................................................................74
SPEN Bit ....................................................................73
SREN Bit ....................................................................74
Read/Write bit Information, R/W ........................................62
Receive Overflow Indicator bit, SSPOV .............................63
Register File .......................................................................12
Register File Map ......................................................... 13, 14
Registers
Block Diagram ........................................................... 64
Master Mode Timing .................................................. 65
Serial Clock ................................................................ 61
Serial Data In ............................................................. 61
Serial Data Out .......................................................... 61
Slave Mode Timing .................................................... 65
Slave Mode Timing Diagram ..................................... 65
Slave Select ............................................................... 61
SPI Mode ................................................................... 61
SSPCON ................................................................... 63
SSPSTAT .................................................................. 62
SPI Clock Edge Select bit, CKE ........................................ 62
SPI Data Input Sample Phase Select bit, SMP ................. 62
SSP
FSR
Summary ............................................................17
INDF
Summary ............................................................17
INTCON
Module Overview ....................................................... 61
RA5/SS/AN4 Pin ...................................................... 7, 8
RC3/SCK/SCL Pin ................................................... 7, 8
RC4/SDI/SDA Pin .................................................... 7, 8
RC5/SDO Pin ........................................................... 7, 8
Section ....................................................................... 61
SSPCON ................................................................... 63
SSPSTAT .................................................................. 62
SSPADD Register .............................................................. 17
SSPBUF ............................................................................ 17
SSPBUF Register .............................................................. 15
SSPCON ............................................................................ 63
SSPCON Register ............................................................. 15
SSPEN ............................................................................... 63
SSPIF ................................................................................ 22
SSPM3:SSPM0 ................................................................. 63
SSPOV ........................................................................ 63, 67
SSPSTAT Register ................................................ 16, 17, 62
Stack .................................................................................. 26
Overflows ................................................................... 26
Underflow .................................................................. 26
START bit, S ...................................................................... 62
STATUS Register ........................................................ 17, 18
DC Bit .................................................................. 18, 36
IRP Bit ....................................................................... 18
PD Bit ........................................................................ 99
TO Bit .................................................................. 18, 99
Z Bit ..................................................................... 18, 36
STOP bit, P ........................................................................ 62
Synchronous Serial Port Enable bit, SSPEN ..................... 63
Synchronous Serial Port Interrupt ...................................... 22
Synchronous Serial Port Mode Select bits,
Summary ............................................................17
OPTION
Summary ............................................................17
PCL
Summary ............................................................17
PCLATH
Summary ............................................................17
PORTB
Summary ............................................................17
SSPSTAT ...................................................................62
STATUS
Summary ............................................................17
Summary ....................................................................15
TMR0
Summary ............................................................17
TRISB
Summary ............................................................17
RESET ......................................................................... 95, 99
RESET
Block Diagram ............................................................99
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
RESET Conditions for All Registers .........................102
RESET Conditions for PCON Register ....................101
RESET Conditions for Program Counter .................101
RESET Conditions for STATUS Register ................101
WDT Reset. See Watchdog Timer (WDT)
Revision History ...............................................................157
S
S .........................................................................................62
SCI. See USART
SCL ....................................................................................67
Serial Communication Interface. See USART
SSPM3:SSPM0 ................................................................. 63
Synchronous Serial Port Module ....................................... 61
Synchronous Serial Port Status Register .......................... 62
Slave Mode
SCL ............................................................................67
SDA ............................................................................67
SLEEP .................................................................. 95, 99, 108
SMP ...................................................................................62
Software Simulator (MPLAB-SIM) ....................................120
SPBRG ...............................................................................17
SPBRG Register ................................................................16
Special Features of the CPU ..............................................95
DS30325A-page 162
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
USART Asynchronous Master Transmission ............ 78
USART Asynchronous Reception ............................. 79
USART Synchronous Receive ................................ 143
USART Synchronous Reception ............................... 85
USART Synchronous Transmission .................. 83, 143
Wake-up from SLEEP via Interrupt ......................... 109
Watchdog Timer ...................................................... 134
Timing Diagrams and Specifications
T
T1CKPS0 bit ...................................................................... 49
T1CKPS1 bit ...................................................................... 49
T1CON ............................................................................... 17
T1CON Register .......................................................... 17, 49
T1OSCEN bit ..................................................................... 49
T1SYNC bit ........................................................................ 49
T2CKPS0 bit ...................................................................... 54
T2CKPS1 bit ...................................................................... 54
T2CON Register .......................................................... 17, 54
TAD ..................................................................................... 93
Timer0
A/D Conversion ....................................................... 145
2
I C Bus Data ............................................................ 141
2
I C Bus START/STOP Bits ...................................... 140
TMR0 ................................................................................. 17
TMR0 Register ................................................................... 15
TMR1CS bit ....................................................................... 49
TMR1H .............................................................................. 17
TMR1H Register ................................................................ 15
TMR1L ............................................................................... 17
TMR1L Register ................................................................. 15
TMR1ON bit ....................................................................... 49
TMR2 ................................................................................. 17
TMR2 Register ................................................................... 15
TMR2ON bit ....................................................................... 54
TOUTPS0 bit ..................................................................... 54
TOUTPS1 bit ..................................................................... 54
TOUTPS2 bit ..................................................................... 54
TOUTPS3 bit ..................................................................... 54
TRISA ................................................................................ 17
TRISA Register .................................................................. 16
TRISB ................................................................................ 17
TRISB Register .................................................................. 16
TRISC ................................................................................ 17
TRISC Register .................................................................. 16
TRISD ................................................................................ 17
TRISD Register .................................................................. 16
TRISE ................................................................................ 17
TRISE Register ............................................................ 16, 35
IBF Bit ........................................................................ 36
IBOV Bit ..................................................................... 36
PSPMODE Bit ............................................... 34, 35, 38
TXREG .............................................................................. 17
TXSTA ............................................................................... 17
TXSTA Register ................................................................. 73
SYNC Bit ............................................................. 73, 74
TRMT Bit ................................................................... 73
TX9 Bit ....................................................................... 73
TX9D Bit .................................................................... 73
TXEN Bit .............................................................. 73, 89
Clock Source Edge Select (T0SE Bit) ........................ 19
Clock Source Select (T0CS Bit) ................................. 19
Overflow Enable (T0IE Bit) ........................................ 20
Overflow Flag (T0IF Bit) ........................................... 106
Overflow Interrupt .................................................... 106
RA4/T0CKI Pin, External Clock ............................... 7, 8
Timer1 ................................................................................ 49
RC0/T1OSO/T1CKI Pin ........................................... 7, 8
RC1/T1OSI/CCP2 Pin .............................................. 7, 8
Timers
Timer0
External Clock .................................................... 46
Interrupt ............................................................. 45
Prescaler ............................................................ 46
Prescaler Block Diagram ................................... 45
Section ............................................................... 45
T0CKI ................................................................. 46
Timer1
Asynchronous Counter Mode ............................ 51
Capacitor Selection ............................................ 51
Operation in Timer Mode ................................... 50
Oscillator ............................................................ 51
Prescaler ............................................................ 51
Resetting of Timer1 Registers ........................... 51
Resetting Timer1 Using a
CCP Trigger Output ........................................... 51
Synchronized Counter Mode ............................. 50
T1CON ............................................................... 49
TMR1H .............................................................. 51
TMR1L ............................................................... 51
Timer2
Block Diagram ................................................... 53
Postscaler .......................................................... 53
Prescaler ............................................................ 53
T2CON ............................................................... 54
Timing Diagrams
Brown-out Reset ...................................................... 134
Capture/Compare/PWM ........................................... 136
CLKOUT and I/O ...................................................... 133
2
I C Reception (7-bit Address) .................................... 69
Power-up Timer ....................................................... 134
RESET ..................................................................... 134
SPI Master Mode ....................................................... 65
SPI Slave Mode (CKE = 1) ........................................ 65
SPI Slave Mode Timing (CKE = 0) ............................ 65
Start-up Timer .......................................................... 134
Time-out Sequence on Power-up .................... 103, 104
Timer0 ...................................................................... 135
Timer1 ...................................................................... 135
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 163
PIC16F7X
U
W
UA ......................................................................................62
Universal Synchronous Asynchronous
Receiver Transmitter. See USART
Wake-up from SLEEP ................................................ 95, 108
Interrupts ......................................................... 101, 102
MCLR Reset ............................................................ 102
Timing Diagram ....................................................... 109
WDT Reset .............................................................. 102
Watchdog Timer (WDT) ............................................. 95, 107
Block Diagram ......................................................... 107
Enable (WDTE Bit) .................................................. 107
Postscaler. See Postscaler, WDT
Programming Considerations .................................. 107
RC Oscillator ............................................................ 107
Time-out Period ....................................................... 107
WDT Reset, Normal Operation .................. 99, 101, 102
WDT Reset, SLEEP ................................... 99, 101, 102
WCOL ................................................................................ 63
Write Collision Detect bit, WCOL ....................................... 63
WWW, On-Line Support ...................................................... 4
Update Address bit, UA ......................................................62
USART ...............................................................................73
Asynchronous Mode ..................................................77
Receive Block Diagram ......................................81
Asynchronous Receiver .............................................79
Asynchronous Reception ...........................................80
Asynchronous Transmitter .........................................77
Baud Rate Generator (BRG) ......................................75
Baud Rate Formula ............................................75
Baud Rates, Asynchronous Mode (BRGH=0) ...76
Sampling ............................................................75
Mode Select (SYNC Bit) ...................................... 73, 74
Overrun Error (OERR Bit) ..........................................74
RC6/TX/CK Pin ........................................................7, 8
RC7/RX/DT Pin ........................................................7, 8
RCSTA Register ........................................................74
Receive Block Diagram ..............................................79
Serial Port Enable (SPEN Bit) ....................................73
Single Receive Enable (SREN Bit) ............................74
Synchronous Master Mode ........................................82
Synchronous Master Reception .................................84
Synchronous Master Transmission ............................82
Synchronous Slave Mode ..........................................86
Transmit Block Diagram .............................................77
Transmit Data, 9th Bit (TX9D) ....................................73
Transmit Enable (TXEN Bit) ................................. 73, 89
Transmit Enable, Nine-bit (TX9 Bit) ...........................73
Transmit Shift Register Status (TRMT Bit) .................73
TXSTA Register .........................................................73
DS30325A-page 164
AdvanceInformation
2000 Microchip Technology Inc.
PIC16F7X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
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Plus, this line provides information on how customers
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000815
The Microchip web site is available by using your
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The file transfer site is available by using an FTP ser-
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The web site and file transfer site provide a variety of
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DS30325A-page 165
PIC16F7X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
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DS30325A-page 166
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PIC16F7X
PIC16F7X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a)
b)
c)
PIC16F77-I/P 301 = Commercial temp., PDIP
package, normal VDD limits, QTP pattern #301.
PIC16LF76-I/SO
package, 200 kHz, Extended VDD limits.
PIC16F74-I/P = Industrial temp., PDIP pack-
age, normal VDD limits.
= Industrial temp., SOIC
Device
PIC16F7X(1), PIC16F7XT(1); VDD range 4.0V to 5.5V
PIC16LF7X(1), PIC16LF7XT(1); VDD range 2.0V to 5.5V
Temperature Range
Package
I
=
-40°C to +85°C (Industrial)
Note 1:
F
= CMOS FLASH
PT
SO
SP
P
L
SS
=
=
=
=
=
=
TQFP (Thin Quad Flatpack)
LF = Low Power CMOS FLASH
T
SOIC
= in tape and reel - SOIC, PLCC,
SSOP, TQFP packages only.
Skinny plastic dip
PDIP
PLCC
SSOP
Pattern
QTP, SQTP, Code or Special Requirements
(blank otherwise)
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DS30325A-page 167
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC (continued)
Corporate Office
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All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 9/00
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It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by
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DS30325A-page 168
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2000 Microchip Technology Inc.
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