PIC16F785-I/P_技术文档

PIC16F785

Data Sheet

20-Pin Flash-Based, 8-Bit

CMOS Microcontroller with

Two-Phase Asynchronous Feedback PWM

Dual High-Speed Comparators and

Dual Operational Amplifiers

Preliminary

DS41249B

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DS41249B-page ii

Preliminary

PIC16F785

20-Pin Flash-Based 8-Bit CMOS Microcontroller

High-Performance RISC CPU:

Peripheral Features:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Interrupt capability

• High-speed Comparator module with:

- Two independent analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- 1.2V band gap voltage reference

- Comparator inputs and outputs externally

accessible

• 8-level deep hardware stack

• Direct, Indirect and Relative Addressing modes

- < 40 ns propagation delay

- 2 mv offset, typical

• Operational Amplifier module with 2 independent

op amps:

Special Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%

- Software selectable frequency range of

8 MHz to 32 kHz

- Software tunable

- 3 MHz GBWP, typical

- All I/O pins externally accessible

• Two-Phase Asynchronous Feedback PWM

module:

- Complementary output with programmable

dead band delay

- Infinite resolution analog duty cycle

- Sync Output/Input for multi-phase PWM

- FOSC/2 maximum PWM frequency

• A/D Converter:

- 10-bit resolution and 14 channels (2 internal)

• 17 I/O pins and 1 input-only pin:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External gate Input mode

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

• Power-saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended temperature range

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR) with software control

option

• Enhanced Low-Current Watchdog Timer (WDT)

with on-chip oscillator (software selectable

nominal 268 seconds with full prescaler) with

software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

- Option to use OSC1 and OSC2 in LP mode

as Timer1 oscillator, if INTOSC mode

selected

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Capture, Compare, PWM module:

- 16-bit Capture, max resolution 12.5 ns

- Compare, max resolution 200 ns

- 10-bit PWM with 1 output channel, max

frequency 20 kHz

Low-Power Features:

• Standby Current:

- 30 nA @ 2.0V, typical

• Operating Current:

- 8.5 μA @ 32 kHz, 2.0V, typical

- 100 μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

- 1 μA @ 2.0V, typical

• In-Circuit Serial Programming^TM(ICSP^TM) via two

pins

• Timer1 Oscillator Current:

- 2 μA @ 32 kHz, 2.0V, typical

Preliminary

DS41249B-page 1

PIC16F785

Program

Memory

Data Memory

SRAM EEPROM

Two-

Comparators CCP Phase

PWM

10-bitA/D Operational

Timers

8/16-bit

Device

I/O

(ch)

Amplifiers

Flash

(words) (bytes) (bytes)

PIC16F785

2048 128 256

17+1

12+2

2

1

2/1

Pin Diagram

20-pin PDIP, SOIC, SSOP

VDD

1

2

3

4

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

VSS

RA5/T1CKI/OSC1/CLKIN

RA4/AN3/T1G/OSC2/CLKOUT

RA3/MCLR/VPP

RA0/AN0/C1IN+/ICSPDAT

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RB4/AN10/OP2-

RC5/CCP1

RC4/C2OUT/PH2

RC3/AN7/C12IN3-/OP1

RC6/AN8/OP1-

RC7/AN9/OP1+

RB5/AN11/OP2+

RB6

RB7/SYNC

10

DS41249B-page 2

Preliminary

PIC16F785

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 5

2.0 Memory Organization................................................................................................................................................................... 9

3.0 Clock Sources ............................................................................................................................................................................ 23

4.0 I/O Ports ..................................................................................................................................................................................... 35

5.0 Timer0 Module ........................................................................................................................................................................... 49

6.0 Timer1 Module with Gate Control............................................................................................................................................... 51

7.0 Timer2 Module ........................................................................................................................................................................... 55

8.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 57

9.0 Comparator Module.................................................................................................................................................................... 63

10.0 Voltage References.................................................................................................................................................................... 71

11.0 Operational Amplifier (OPA) Module.......................................................................................................................................... 75

12.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 79

13.0 Two-Phase PWM ....................................................................................................................................................................... 91

14.0 Data EEPROM Memory ........................................................................................................................................................... 103

15.0 Special Features of the CPU.................................................................................................................................................... 107

16.0 Instruction Set Summary.......................................................................................................................................................... 127

17.0 Development Support............................................................................................................................................................... 137

18.0 Electrical Specifications............................................................................................................................................................ 143

19.0 AC and DC Characterization.................................................................................................................................................... 165

20.0 Packaging Information.............................................................................................................................................................. 167

Appendix A: Data Sheet Revision History.......................................................................................................................................... 171

Appendix B: Migrating from other PICmicro® DeviceS...................................................................................................................... 171

Index .................................................................................................................................................................................................. 173

On-Line Support................................................................................................................................................................................. 179

Systems Information and Upgrade Hot Line ...................................................................................................................................... 179

Reader Response.............................................................................................................................................................................. 180

Product Identification System ............................................................................................................................................................ 181

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Preliminary

DS41249B-page 3

PIC16F785

NOTES:

DS41249B-page 4

Preliminary

PIC16F785

this Data Sheet and is highly recommended reading for

a better understanding of the device architecture and

operation of the peripheral modules.

1.0

DEVICE OVERVIEW

This document contains device specific information for

the PIC16F785. Additional information may be found in

the “PICmicro^®Mid-Range MCU Family Reference

Manual” (DS33023), which may be obtained from your

local Microchip Sales Representative or downloaded

from the Microchip web site. The Reference Manual

should be considered a complementary document to

The PIC16F785 is covered by this Data Sheet. It is

available in 20-pin PDIP, SOIC and SSOP packages.

Figure 1-1 shows a block diagram of the PIC16F785

device. Table 1-1 shows the pinout description.

FIGURE 1-1:

PIC16F785 Block Diagram

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

RA0

RA1

Flash

2k X 14

Program

Memory

RA2

RAM

128 bytes

8-Level Stack

(13-bit)

RA3

RA4

RA5

File

Registers

Program

Bus

14

RAM Addr

9

PORTB

PORTC

ADDR MUX

RB4

RB5

RB6

RB7

Instruction reg

Indirect

Addr

7

Direct Addr

8

FSR Reg

Status Reg

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

8

3

MUX

Power-up

Timer

32 kHz Internal

Oscillator

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

Power-on

Reset

OSC1/CLKIN

8

Timing

Generation

OSC2/CLKOUT

Watchdog

Timer

W Reg

OP1

OP1+

OP1-

OP2

Brown-out

Reset

8 Mhz Internal

Oscillator

Dual

Op Amps

OP2+

OP2-

CCP1

T1G

VDD

VSS

MCLR

EEDATA

256 bytes

Data

EEPROM

T1CKI

PH1

PH2

Two-Phase

PWM

CCP

Timer0

Timer1

Timer2

T0CKI

EEADDR

8

SYNC

Voltage

Reference

2 Analog

Comparators

Analog-to-Digital Converter

AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN3 AN8 AN9 AN10 AN11

VREF

C1IN- C1IN+ C1OUT C2IN- C2IN+ C2OUT

Preliminary

DS41249B-page 5

PIC16F785

TABLE 1-1:

PIC16F785 PINOUT DESCRIPTION

Input Output

Name

Pin Function

Description

Type

RA0/AN0/C1IN+/ICSPDAT

19

RA0

AN0

TTL

AN

ST

CMOS PORTA I/O with prog. pull-up and interrupt-on-change

—

A/D Channel 0 input

C1IN+

ICSPDAT

RA1

Comparator 1 non-inverting input

CMOS Serial Programming Data I/O

RA1/AN1/C12IN0-/VREF/ICSP-

CLK

18

TTL

AN

CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN1

—

A/D Channel 1 input

C12IN0-

VREF

Comparator 1 and 2 inverting input

AN

External Voltage Reference for A/D, buffered reference

output

ICSPCLK

RA2

ST

AN

ST

—

Serial Programming Clock

RA2/AN2/T0CKI/INT/C1OUT

17

CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN2

—

A/D Channel 2 input

Timer0 clock input

External Interrupt

T0CKI

INT

C1OUT

RA3

CMOS Comparator 1 output

RA3/MCLR/VPP

4

3

TTL

ST

HV

TTL

AN

ST

—

PORTA input with prog. pull-up and interrupt-on-change

MCLR

VPP

Master Clear with internal pull-up

Programming voltage

RA4/AN3/T1G/OSC2/CLKOUT

RA4

CMOS PORTA I/O with prog. pull-up and interrupt-on-change

AN3

—

A/D Channel 3 input

Timer1 gate

T1G

OSC2

CLKOUT

XTAL Crystal/Resonator

CMOS FOSC/4 output

—

RA5/T1CKI/OSC1/CLKIN

2

RA5

T1CKI

OSC1

CLKIN

RB4

TTL

ST

CMOS PORTA I/O with prog. pull-up and interrupt-on-change

—

Timer1 clock

XTAL

ST

Crystal/Resonator

External clock input/RC oscillator connection

RB4/AN10/OP2-

RB5/AN11/OP2+

13

12

TTL

AN

—

CMOS PORTB I/O

AN10

OP2-

RB5

—

A/D Channel 10 input

Op Amp 2 inverting input

AN

TTL

AN

—

CMOS PORTB I/O

AN11

OP2+

RB6

—

A/D Channel 11 input

AN

OD

Op Amp 2 non-inverting input

PORTB I/O. Open drain output

RB6

11

10

TTL

ST

RB7/SYNC

RB7

CMOS PORTB I/O

SYNC

RC0

CMOS Master PWM Sync output or slave PWM Sync input

CMOS PORTC I/O

RC0/AN4/C2IN+

16

15

TTL

AN

TTL

AN

—

AN4

—

A/D Channel 4 input

C2IN+

RC1

Comparator 2 non-inverting input

RC1/AN5/C12IN1-/PH1

CMOS PORTC I/O

AN5

—

A/D Channel 5 input

Comparator 1 and 2 inverting input

C12IN1-

PH1

CMOS PWM phase 1 output

CMOS PORTC I/O

RC2/AN6/C12IN2-/OP2

14

RC2

TTL

AN

—

AN6

—

A/D Channel 6 input

C12IN2-

OP2

Comparator 1 and 2 inverting input

Op Amp 2 output

AN

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output, HV = High Voltage

DS41249B-page 6

Preliminary

PIC16F785

TABLE 1-1:

PIC16F785 PINOUT DESCRIPTION (CONTINUED)

Input Output

Name

Pin Function

Description

Type

RC3/AN7/C12IN3-/OP1

7

RC3

AN7

TTL

AN

—

CMOS PORTC I/O

—

A/D Channel 7 input

C12IN3-

OP1

Comparator 1 and 2 inverting input

Op Amp 1 output

AN

RC4/C2OUT/PH2

6

RC4

TTL

—

CMOS PORTC I/O

C2OUT

PH2

CMOS Comparator 2 output

CMOS PWM phase 2 output

CMOS PORTC I/O

—

RC5/CCP1

5

8

RC5

TTL

ST

CCP1

RC6

CMOS Capture input/Compare output

CMOS PORTC I/O

RC6/AN8/OP1-

TTL

AN

AN8

—

A/D Channel 8 input

OP1-

RC7

Op Amp 1 inverting input

RC7/AN9/OP1+

9

CMOS PORTC I/O

AN9

AN

—

A/D Channel 9 input

OP1+

VSS

Op Amp 1 non-inverting input

Ground reference

VSS

VDD

20

1

Power

VDD

Positive supply

Legend:

TTL = TTL input buffer, ST = Schmitt Trigger input buffer, AN = Analog, OD = Open Drain output, HV = High Voltage

TABLE 1-2:

PIC16F785 PIN USAGE SUMMARY

I/O

19

Analog

Comp. Op Amps PWM Timers

CCP Interrupt Pull-ups

Basic

RA0

RA1

RA2

RA3⁽¹⁾

RA4

RA5

RB4

RB5

RB6⁽²⁾

RB7

RC0

RC1

RC2

RC3

RC4

RC5

RC6

RC7

—

AN0

C1IN+

—

IOC

INT/IOC

IOC

—

Y

ICSPDAT

18 AN1/VREF C12IN0-

ICSPCLK

17

4

AN2

—

C1OUT

—

T0CKI

—

Y

—

Y

MCLR

3

AN3

—

T1G

T1CKI

—

Y

OSC2/CLKOUT

2

—

Y

OSC1/CLKIN

13

12

11

10

16

15

14

7

AN10

AN11

—

OP2-

OP2+

—

SYNC

—

AN4

AN5

AN6

AN7

—

C2IN+

C12IN1-

C12IN2-

C12IN3-

C2OUT

—

PH1

—

OP2

OP1

—

6

PH2

—

5

—

CCP1

—

8

AN8

AN9

—

OP1-

OP1+

—

9

—

1

—

VDD

VSS

—

20

—

Note 1: Input only.

2: Open drain.

Preliminary

DS41249B-page 7

PIC16F785

NOTES:

DS41249B-page 8

Preliminary

PIC16F785

2.2

Data Memory Organization

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The data memory (see Figure 2-2) is partitioned into

four banks, which contain the General Purpose

Registers (GPR) and the Special Function Registers

(SFR). The Special Function Registers are located in

the first 32 locations of each bank. Register locations

20h-7Fh in Bank 0 and A0h-BFh in Bank 1 are General

Purpose Registers, implemented as static RAM. The

last sixteen register locations in Bank 1 (F0h-FFh),

Bank 2 (170h-17Fh), and Bank 3 (1F0h-1FFh) point to

addresses 70h-7Fh in Bank 0. All other RAM is

unimplemented and returns ‘0’ when read.

The PIC16F785 has a 13-bit program counter capable

of addressing an 8k x 14 program memory space. Only

the first 2k x 14 (0000h-07FFh) for the PIC16F785 is

physically implemented. Accessing a location above

these boundaries will cause a wrap around within the

first 2k x 14 space. The Reset vector is at 0000h and

the interrupt vector is at 0004h (see Figure 2-1).

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F785

Seven address bits are required to access any location

in a data memory bank. Two additional bits are required

to access the four banks. When data memory is

accessed directly, the seven Least Significant address

bits are contained within the opcode and the two Most

Significant bits are contained in the STATUS register.

RP0 and RP1 (STATUS<5> and STATUS<6>) are the

two Most Significant data memory address bits and are

also known as the bank select bits. Table 2-1 lists how

to access the four banks of registers.

PC<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

TABLE 2-1:

BANK SELECTION

RP1

RP0

000H

Bank0

Bank1

Bank2

Bank3

0

1

0

1

0

1

Interrupt Vector

0004

0005

On-chip Program

Memory

2.2.1

GENERAL PURPOSE REGISTER

FILE

07FFH

0800H

The register file banks are organized as 128 x 8 in the

PIC16F785. Each register is accessed, either directly, by

seven address bits within the opcode, or indirectly,

through the File Select Register (FSR). When the FSR is

used to access data memory, the eight Least Significant

data memory address bits are contained in the FSR and

the ninth Most Significant address bit is contained in the

IRP bit (STATUS<7>) of the STATUS register. (see

Section 2.4 “Indirect Addressing, INDF and FSR

Registers”).

1FFFH

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Table 2-2). These

registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

Preliminary

DS41249B-page 9

PIC16F785

FIGURE 2-2:

DATA MEMORY MAP OF THE PIC16F785

File

Address

Indirect addr.⁽¹⁾00h

Indirect addr.⁽¹⁾80h

OPTION_REG 81h

Indirect addr.⁽¹⁾100h

Indirect addr.⁽¹⁾180h

OPTION_REG 181h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

120h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

1A0h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

PCLATH

INTCON

PIR1

PCLATH

INTCON

PIE1

PCLATH

INTCON

PCLATH

INTCON

TMR1L

TMR1H

T1CON

PCON

OSCCON

OSCTUNE

ANSEL0

PR2

PWMCON1

PWMCON0

PWMCLK

PWMPH1

PWMPH2

TMR2

T2CON

CCPR1L

CCPR1H

CCP1CON

ANSEL1

WPUA

IOCA

WDTCON

REFCON

VRCON

CM1CON0

CM2CON0

CM2CON1

OPA1CON

OPA2CON

EEDAT

EEADR

EECON1

EECON2⁽¹⁾

ADRESL

ADCON1

ADRESH

ADCON0

General

Purpose

Register

General

Purpose

Register

32 Bytes

BFh

C0h

96 Bytes

6Fh

70h

7Fh

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

accesses

Bank 0

accesses

Bank 0

accesses

Bank 0

Bank1

Bank2

Bank3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

DS41249B-page 10

Preliminary

PIC16F785

TABLE 2-2:

PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module’s Register

xxxx xxxx 22,114

xxxx xxxx 49,114

0000 0000 21,114

0001 1xxx 15,114

xxxx xxxx 22,114

--x0 x000 35,114

xx00 ---- 42,114

00xx 0000 45,114

TMR0

PCL

Program Counter's (PC) Least Significant Byte

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

FSR

Indirect Data Memory Address Pointer

PORTA⁽¹⁾

PORTB⁽¹⁾

PORTC⁽¹⁾

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

RB7

RB6

RC6

RC7

RC3

RC2

RC1

RC0

Unimplemented

—

PCLATH

INTCON

PIR1

—

Write Buffer for Upper 5 bits of Program Counter

---0 0000 21,114

0000 0000 17,114

GIE

PEIE

ADIF

T0IE

INTE

C2IF

RAIE

C1IF

T0IF

INTF

RAIF

EEIF

CCP1IF

OSFIF

TMR2IF

TMR1IF 0000 0000 19,114

—

Unimplemented

—

TMR1L

TMR1H

Holding Register for the Least Significant Byte of the 16-bit TMR1

Holding Register for the Most Significant Byte of the 16-bit TMR1

xxxx xxxx 51,114

53,114

TMR1ON 0000 0000

10h

11h

12h

13h

T1CON

TMR2

T1GINV

TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS

Timer2 Module Register

0000 0000 55,114

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 55,114

T2CON

—

57,114

CCPR1L

CCPR1H

Capture/Compare/PWM Register1 Low Byte

Capture/Compare/PWM Register1 High Byte

xxxx xxxx

14h

15h

—

CCP1CON

DC1B1

DC1B0

CCP1M3

WDTPS2

CCP1M2

WDTPS1

CCP1M1

CCP1M0 --00 0000

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

—

Unimplemented

—

WDTCON

WDTPS3

WDTPS0 SWDTEN

122,114

—

---0 1000

—

Unimplemented

—

ADRESH

Most Significant 8 bits of the left justified A/D result or 2 bits of right justified result

ADFM VCFG CHS3 CHS2 CHS1 CHS0 GO/DONE

xxxx xxxx 81,114

83,114

1Fh

ADCON0

ADON

0000 0000

Legend:

Note 1:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

Preliminary

DS41249B-page 11

PIC16F785

TABLE 2-3:

PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 1

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx 22,114

1111 1111 16,114

0000 0000 21,114

0001 1xxx 15,114

xxxx xxxx 22,114

--11 1111 36,114

1111 ---- 42,114

1111 1111 45,114

OPTION_REG

PCL

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

Program Counter's (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

TRISA

TRISB

TRISC

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA3

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

TRISC2

TRISC1

TRISC0

Unimplemented

—

PCLATH

INTCON

PIE1

—

Write Buffer for Upper 5 bits of Program Counter

---0 0000 21,114

0000 0000 17,114

GIE

PEIE

ADIE

T0IE

INTE

C2IE

RAIE

C1IE

T0IF

INTF

RAIF

EEIE

CCP1IE

OSFIE

TMR2IE

TMR1IE 0000 0000 18,114

—

Unimplemented

—

PCON

OSCCON

OSCTUNE

ANSEL0

PR2

—

IRCF1

—

SBOREN

IRCF0

TUN4

—

POR

LTS

BOR

SCS

---1 --qq 20,114

-110 q000 33,114

---0 0000 28,114

1111 1111 82,114

1111 1111 55,114

---- 1111 82,115

—

IRCF2

—

OSTS⁽¹⁾

TUN3

ANS3

HTS

TUN2

ANS2

TUN1

ANS1

TUN0

ANS0

ANS7

ANS6

ANS5

ANS4

Timer2 Module Period Register

ANSEL1

—

ANS11

ANS10

ANS9

ANS8

Unimplemented

—

WPUA

IOCA

—

WPUA5

IOCA5

WPUA4 WPUA3⁽²⁾

WPUA2

IOCA2

WPUA1

IOCA1

WPUA0

IOCA0

--11 1111 36,115

--00 0000 37,115

—

IOCA4

IOCA3

—

Unimplemented

—

REFCON

VRCON

EEDAT

EEADR

EECON1

EECON2

ADRESL

ADCON1

—

BGST

VRR

VRBB

—

VREN

VR3

VROE

VR2

CVROE

VR1

—

--00 000- 73,115

000- 0000 72,115

C1VREN

EEDAT7

EEADR7

—

C2VREN

EEDAT6

EEADR6

—

VR0

EEDAT5

EEDAT4

EEDAT3

EEDAT2

EEADR2

WREN

EEDAT1

EEADR1

WR

EEDAT0 0000 0000 103,115

EEADR0 0000 0000 103,115

EEADR5 EEADR4 EEADR3

WRERR

—

RD

---- x000 104,115

---- ---- 104,115

xxxx xxxx 80,115

-000 ---- 84,115

EEPROM Control Register 2 (not a physical register)

Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result

ADCS2 ADCS1 ADCS0

—

Legend:

Note 1:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe mode is enabled, otherwise this

bit resets to ‘1’.

2:

RA3 pull-up is enabled when MCLRE is ‘1’ in Configuration Word.

DS41249B-page 12

Preliminary

PIC16F785

TABLE 2-4:

PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 2

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module’s Register

xxxx xxxx 22,114

xxxx xxxx 49,114

0000 0000 21,114

0001 1xxx 15,114

xxxx xxxx 22,114

--x0 x000 35,114

xx00 ---- 42,114

00xx 0000 45,114

TMR0

PCL

Program Counter's (PC) Least Significant Byte

STATUS

IRP

RP1

RP0

TO

PD

Z

DC

C

FSR

Indirect Data Memory Address Pointer

PORTA⁽¹⁾

PORTB⁽¹⁾

PORTC⁽¹⁾

—

RA5

RB5

RC5

RA4

RB4

RC4

RA3

—

RA2

—

RA1

—

RA0

—

RB7

RB6

RC6

RC7

RC3

RC2

RC1

RC0

Unimplemented

—

PCLATH

INTCON

—

Write Buffer for Upper 5 bits of Program Counter

---0 0000 21,114

0000 0000 17,114

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

Unimplemented

—

PWMCON1

PWMCON0

PWMCLK

PWMPH1

PWMPH2

—

PRSEN

PWMASE

POL

COMOD1 COMOD0 CMDLY4

CMDLY3

SYNC1

PER3

PH3

CMDLY2

SYNC0

PER2

PH2

CMDLY1

PH2EN

PER1

PH1

CMDLY0 -000 0000 100,115

PASEN

PWMP1

C2EN

BLANK2

PWMP0

C1EN

BLANK1

PER4

PH4

PH1EN

PER0

PH0

0000 0000 93,115

0000 0000 94,115

0000 0000 95,115

0000 0000 96,115

POL

C2EN

C1EN

PH4

PH3

PH2

PH1

PH0

Unimplemented

—

CM1CON0

CM2CON0

CM2CON1

OPA1CON

OPA2CON

—

C1ON

C2ON

C1OUT

C1OE

C2OE

—

C1POL

C2POL

—

C1SP

C2SP

—

C1R

C2R

—

C1CH1

C2CH1

T1GSS

—

C1CH0

C2CH0

0000 0000 65,115

0000 0000 67,115

C2OUT

MC2OUT

—

MC1OUT

OPAON

C2SYNC 00-- --10 68,115

—

0--- ---- 76,115

—

Unimplemented

—

Legend:

Note 1:

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Port pins with analog functions controlled by the ANSEL0 and ANSEL1 registers will read ‘0’ immediately after a Reset even though the

data latches are either undefined (POR) or unchanged (other Resets).

Preliminary

DS41249B-page 13

PIC16F785

TABLE 2-5:

PIC16F785 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

Bank 3

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

Legend:

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

xxxx xxxx 22,114

1111 1111 16,114

0000 0000 21,114

0001 1xxx 15,114

xxxx xxxx 22,114

--11 1111 36,114

1111 ---- 42,114

1111 1111 45,114

OPTION_REG

RAPU

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

PCL

STATUS

FSR

TRISA

TRISB

TRISC

—

Program Counter's (PC) Least Significant Byte

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

—

TRISA5

TRISB5

TRISC5

TRISA4

TRISB4

TRISC4

TRISA3

—

TRISA2

—

TRISA1

—

TRISA0

—

TRISB7

TRISC7

TRISB6

TRISC6

TRISC3

TRISC2

TRISC1

TRISC0

Unimplemented

—

PCLATH

INTCON

PIE1

—

Write Buffer for Upper 5 bits of Program Counter

---0 0000 21,114

0000 0000 17,114

GIE

PEIE

ADIE

T0IE

INTE

C2IE

RAIE

C1IE

T0IF

INTF

RAIF

EEIE

CCP1IE

OSFIE

TMR2IE

TMR1IE 0000 0000 18,114

Unimplemented

—

– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

DS41249B-page 14

Preliminary

PIC16F785

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu(where u= unchanged).

2.2.2.1

STATUS Register

The STATUS register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits, see Section 16.0

“Instruction Set Summary”.

• the bank select bits for data memory (SRAM)

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

register is the destination for an instruction that affects

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

Note:

The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

REGISTER 2-1:

STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h OR 183h)

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC⁽¹⁾

R/W-x

C⁽¹⁾

bit 7

bit 0

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2,3 (100h-1FFh)

0= Bank 0,1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

11= Bank 3 (180h-1FFh)

10= Bank 2 (100h-17Fh)

01= Bank 1 (80h-FFh)

00= Bank 0 (00h-7Fh)

bit 4

bit 3

bit 2

bit 1

TO: Time-out bit

1= After power-up, CLRWDTinstruction, or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

For borrow, the polarity is reversed.

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

bit 0

C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high-order or low-order bit of the source register.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 15

PIC16F785

2.2.2.2

Option Register

Note:

To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by

setting PSA bit to ‘1’ (OPTION_REG<3>).

See Section 5.4 “Prescaler”.

The Option (OPTION_REG) register, shown in

Register 2-2, is a readable and writable register, which

contains various control bits to configure:

• TMR0/WDT prescaler

• External RA2/INT interrupt

• TMR0

• Weak pull-ups on PORTA

REGISTER 2-2:

OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)

R/W-1

RAPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RAPU: PORTA Pull-up Enable bit

1= PORTA pull-ups are disabled

0= PORTA pull-ups are enabled by individual port latch values in WPUA register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RA2/AN2/T0CKI/INT/C1OUT pin

0= Interrupt on falling edge of RA2/AN2/T0CKI/INT/C1OUT pin

T0CS: TMR0 Clock Source Select bit

1= Transition on RA2/AN2/T0CKI/INT/C1OUT pin

0= Internal instruction cycle clock (CLKOUT)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on RA2/AN2/T0CKI/INT/C1OUT pin

0= Increment on low-to-high transition on RA2/AN2/T0CKI/INT/C1OUT pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate⁽¹⁾

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F785. See

Section 15.5 “Watchdog Timer (WDT)” for more information.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 16

Preliminary

PIC16F785

2.2.2.3

INTCON Register

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

The Interrupt Control (INTCON) register, shown in

Register 2-3, is a readable and writable register, which

contains the various enable and flag bits for TMR0

register overflow, PORTA change and external RA2/INT

pin interrupts.

REGISTER 2-3:

INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 103h OR

183h)

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RAIE⁽¹⁾

R/W-0

T0IF⁽²⁾

R/W-0

INTF

R/W-0

RAIF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 interrupt

0= Disables the TMR0 interrupt

INTE: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Enable bit

1= Enables the RA2/AN2/T0CKI/INT/C1OUT external interrupt

0= Disables the RA2/AN2/T0CKI/INT/C1OUT external interrupt

RAIE: PORTA Change Interrupt Enable bit⁽¹⁾

1= Enables the PORTA change interrupt

0= Disables the PORTA change interrupt

T0IF: TMR0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RA2/AN2/T0CKI/INT/C1OUT External Interrupt Flag bit

1= The RA2/AN2/T0CKI/INT/C1OUT external interrupt occurred (must be cleared in software)

0= The RA2/AN2/T0CKI/INT/C1OUT external interrupt did not occur

RAIF: PORTA Change Interrupt Flag bit

1= When at least one of the PORTA <5:0> pins changed state (must be cleared in software)

0= None of the PORTA <5:0> pins have changed state

Note 1: IOCA register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing T0IF bit.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 17

PIC16F785

2.2.2.4

PIE1 Register

The Peripheral Interrupt Enable (PIE1) Register 1,

shown in Register 2-4, contains the interrupt enable

bits, as shown in Register 2-4.

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4:

PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)

R/W-0

EEIE

R/W-0

ADIE

R/W-0

C2IE

R/W-0

C1IE

R/W-0

OSFIE

R/W-0

TMR1IE

bit 0

CCP1IE

TMR2IE

bit 7

EEIE: EE Write Complete Interrupt Enable bit

1= Enables the EE write complete interrupt

0= Disables the EE write complete interrupt

bit 6

bit 5

ADIE: A/D Converter Interrupt Enable bit

1= Enables the A/D converter interrupt

0= Disables the A/D converter interrupt

CCP1IE: CCP1 Interrupt Enable bit

1= Enables the CCP1 interrupt

0= Disables the CCP1 interrupt

bit 4

bit 3

bit 2

bit 1

bit 0

C2IE: Comparator 2 Interrupt Enable bit

1= Enables the Comparator 2 interrupt

0= Disables the Comparator 2 interrupt

C1IE: Comparator 1 Interrupt Enable bit

1= Enables the Comparator 1 interrupt

0= Disables the Comparator 1 interrupt

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enables the Oscillator Fail interrupt

0= Disables the Oscillator Fail interrupt

TMR2IE: Timer2 to PR2 Match Interrupt Enable bit

1= Enables the Timer2 to PR2 match interrupt

0= Disables the Timer2 to PR2 match interrupt

TMR1IE: Timer1 Overflow Interrupt Enable bit

1= Enables the Timer1 overflow interrupt

0= Disables the Timer1 overflow interrupt

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 18

Preliminary

PIC16F785

2.2.2.5

PIR1 Register

The Peripheral Interrupt (PIR1) Register 1 contains the

interrupt flag bits, as shown in Register 2-5.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

REGISTER 2-5:

PIR1 – PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)

R/W-0

EEIF

R/W-0

ADIF

R/W-0

C2IF

R/W-0

C1IF

R/W-0

OSFIF

R/W-0

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

bit 7

bit 6

bit 5

EEIF: EEPROM Write Operation Interrupt Flag bit

1= The write operation completed (must be cleared in software)

0= The write operation has not completed or has not been started

ADIF: A/D Interrupt Flag bit

1= A/D conversion complete

0= A/D conversion has not completed or has not been started

CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare mode:

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode:

Unused in this mode

bit 4

bit 3

bit 2

bit 1

bit 0

C2IF: Comparator 2 Interrupt Flag bit

1= Comparator 2 output has changed (must be cleared in software)

0= Comparator 2 output has not changed

C1IF: Comparator 1 Interrupt Flag bit

1= Comparator 1 output has changed (must be cleared in software)

0= Comparator 1 output has not changed

OSFIF: Oscillator Fail Interrupt Flag bit

1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0= System clock operating

TMR2IF: Timer2 to PR2 Match Interrupt Flag bit

1= Timer2 to PR2 match occurred (must be cleared in software)

0= Timer2 to PR2 match has not occurred

TMR1IF: Timer1 Overflow Interrupt Flag bit

1= Timer1 register overflowed (must be cleared in software)

0= Timer1 has not overflowed

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 19

PIC16F785

2.2.2.6

PCON Register

The Power Control (PCON) register (see Table 15-2)

contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register bits are shown in Register 2-6.

REGISTER 2-6:

PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)

U-0

—

U-0

—

U-0

—

R/W-1

SBOREN⁽¹⁾

U-0

—

U-0

—

R/W-0

POR

R/W-x

BOR

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as ‘0’

SBOREN: Software BOR Enable bit⁽¹⁾

1= BOR enabled

0= BOR disabled

bit 3-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01in Configuration Word for this bit to control the BOR.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 20

Preliminary

PIC16F785

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.3

PCL and PCLATH

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The program counter

is 13 bits wide. The low byte is called the PCL register.

The PCL register is readable and writable. The high

byte of the PC (PC<12:8>) is called the PCH register.

This register contains PC<12:8> bits which are not

directly readable or writable. All updates to the PCH

register go through the PCLATH register.

PCH

PCL

Instruction with

12

8

7

0

PCL as

Destination

PC

8

PCLATH<4:0>

PCLATH

5

ALU result

On any Reset, the PC is cleared. Figure 2-3 shows the

two situations for the loading of the PC. The upper

example in Figure 2-3 shows how the PC is loaded on

a write to PCL (PCLATH<4:0> → PCH). The lower

example in Figure 2-3 shows how the PC is loaded

during a CALL or GOTO instruction (PCLATH<4:3> →

PCH).

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

PCLATH<4:3>

11

2

Opcode <10:0>

PCLATH

2.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by first

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are then written to the PCL

register, all 13 bits of the program counter will change

to the values contained in the PCLATH register and

those being written to the PCL register.

2.3.3

STACK

The PIC16F785 family has an 8-level x 13-bit wide

hardware stack (see Figure 2-1). The stack space is

not part of either program or data space and the Stack

Pointer is not readable or writable. The PC is PUSHed

onto the stack when a CALLinstruction is executed or

an interrupt causes a branch. The stack is POPed in

the event of a RETURN,

instruction execution. PCLATH is not affected by a

PUSH or POP operation.

RETLW or a RETFIE

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions, or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

Note 1: There are no Status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLWand RETFIEinstructions

or the vectoring to an interrupt address.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2

PROGRAM MEMORY PAGING

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When doing a CALLor GOTOinstruction,

the upper bit of the address is provided by PCLATH<3>

(page select bit). When doing a CALLor GOTOinstruction

the user must ensure that the page select bit is

programmed so that the desired destination program

memory page is addressed. When the CALLinstruction

(or interrupt) is executed, the entire 13-bit PC return

address is PUSHed onto the stack. Therefore,

manipulation of the PCLATH<3> bit is not required for

the RETURN or RETFIE instructions which POP the

address from the stack.

Preliminary

DS41249B-page 21

PIC16F785

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-1.

2.4

Indirect Addressing, INDF and

FSR Registers

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

EXAMPLE 2-1:

INDIRECT ADDRESSING

MOVLW 0x20

MOVWF FSR

;initialize pointer

;to RAM

;clear INDF register

;increment pointer

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR and the IRP bit

(STATUS<7>), as shown in Figure 2-4.

INCF

INDF

FSR

BTFSS FSR,4 ;all done?

GOTO

CONTINUE

;yes continue

FIGURE 2-4:

DIRECT/INDIRECT ADDRESSING PIC16F785

Direct Addressing

Indirect Addressing

File Select Register

From Opcode

RP1

6

0

RP0

0

IRP

7

Bank Select

180H

Location Select

Bank Select

Location Select

00H

00

01

10

11

Data

Memory

7FH

1FFH

Bank 0

Bank 1

Bank 2

Bank 3

Note:

For memory map detail see Figure 2-2.

DS41249B-page 22

Preliminary

PIC16F785

The PIC16F785 can be configured in one of eight clock

modes.

3.0

3.1

CLOCK SOURCES

Overview

1. EC – External clock with I/O on RA4.

2. LP – 32.768 kHz Watch Crystal or Ceramic

Resonator Oscillator mode.

The PIC16F785 has a wide variety of clock sources

and selection features to allow it to be used in a wide

range of applications while maximizing performance

and minimizing power consumption. Figure 3-1

illustrates a block diagram of the PIC16F785 clock

sources.

3. XT – Medium Gain Crystal or Ceramic Resona-

tor Oscillator mode.

4. HS – High Gain Crystal or Ceramic Resonator

mode.

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on RA4

Clock sources can be configured from external

oscillators, quartz crystal resonators, ceramic

resonators and Resistor-Capacitor (RC) circuits. In

addition, the system clock source can be configured

from one of two internal oscillators, with a choice of

speeds selectable via software. Additional clock

features include:

6. RCIO – External Resistor-Capacitor with I/O on

RA4.

7. INTOSC – Internal Oscillator with FOSC/4 output

on RA4 and I/O on RA5.

8. INTOSCIO – Internal Oscillator with I/O on RA4

and RA5.

• Selectable system clock source between external

or internal via software.

Clock Source modes are configured by the FOSC<2:0>

bits in the Configuration Word (see Section 15.0

“Special Features of the CPU”). Once the PIC16F785

is programmed and the Clock Source mode configured,

it cannot be changed in software.

• Two-speed Clock Start-up mode, which minimizes

latency between external oscillator start-up and

code execution.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch to the

internal oscillator.

FIGURE 3-1:

PIC16F785 CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word)

External Oscillator

SCS

(OSCCON<0>)

OSC2

OSC1

Sleep

LP, XT, HS, RC, RCIO, EC

IRCF<2:0>

(OSCCON<6:4>)

System Clock

(CPU and Peripherals)

8 MHz

111

110

101

Internal Oscillator

4 MHz

2 MHz

1 MHz

HFINTOSC

8 MHz

100

011

010

001

000

500 kHz

250 kHz

125 kHz

31 kHz

LFINTOSC

31 kHz

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

Preliminary

DS41249B-page 23

PIC16F785

3.2

Clock Source Modes

3.3

External Clock Modes

Clock Source modes can be classified as external or

internal.

3.3.1 OSCILLATOR START-UP TIMER (OST)

When the PIC16F785 is configured for any of the

Crystal Oscillator modes (LP, XT or HS), the Oscillator

Start-up Timer (OST) is enabled, which extends the

reset period to allow the oscillator additional time to

stabilize. The OST counts 1024 clock periods present

on the OSC1 pin following a Power-on Reset (POR), a

wake from Sleep, or when the Power-up Timer (PWRT)

has expired (if the PWRT is enabled). During this time,

the program counter does not increment and program

execution is suspended. The OST ensures that the

oscillator circuit, using a quartz crystal resonator or

ceramic resonator, has started and is providing a stable

system clock to the PIC16F785. Table 3-1 shows

examples where the oscillator delay is invoked.

• External Clock modes rely on external circuitry for

the clock source. Examples are oscillator modules

(EC mode), quartz crystal resonators or ceramic

resonators (LP, XT, and HS modes), and resistor-

capacitor (RC mode) circuits.

• Internal clock sources are contained internally

within the PIC16F785. The PIC16F785 has two

internal oscillators; the 8 MHz High-frequency

Internal Oscillator (HFINTOSC) and 31 kHz Low-

frequency Internal Oscillator (LFINTOSC).

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 3.5 “Clock Switching”).

In order to minimize latency between external oscillator

start-up and code execution, the Two-speed Clock

Start-up mode can be selected (see Section 3.6 “Two-

Speed Clock Start-up Mode”).

TABLE 3-1:

OSCILLATOR DELAY EXAMPLES

Switch From

Switch To

Frequency

Oscillator Delay

Comments

INTRC

INTOSC

31 kHz

125 kHz-8 MHz

Sleep/POR

Sleep

Following a wake-up from Sleep mode or POR,

CPU start-up is invoked to allow the CPU to

become ready for code execution.

5 μs-10 μs (approx.)

CPU Start-up

EC, RC

DC – 20 MHz

(1)

LFINTOSC

(31 kHz)

Sleep/POR

LP, XT, HS

INTOSC

31 kHz-20 MHz

125 kHz-8 MHz

1024 Clock Cycles

(OST)

LFINTOSC

(31 kHz)

1 μs (approx.)

Note 1: The 5 μs-10 μs start-up delay is based on a 1 MHz System Clock.

3.3.2

EC MODE

FIGURE 3-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

The External Clock (EC) mode allows an externally

generated logic level as the system clock source.

When operating in this mode, an external clock source

is connected to OSC1 pin and the RA4 pin is available

for general purpose I/O. Figure 3-2 shows the pin

connections for EC mode.

OSC1/CLKIN

Clock from

Ext. System

PIC16F785

I/O (OSC2)

RA4

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC16F785 design is fully

static, stopping the external clock input will have the

effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will

resume operation as if no time had elapsed.

DS41249B-page 24

Preliminary

PIC16F785

3.3.3

LP, XT, HS MODES

FIGURE 3-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

the OSC1 and OSC2 pins (Figure 3-1). The mode

selects a low, medium, or high gain setting of the

internal inverter-amplifier to support various resonator

types and speed.

OSC1

PIC16F785

C1

(3)

(2)

RF

Sleep

RP

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is best suited

to drive resonators with a low drive level specification, for

example, tuning fork type crystals.

OSC2

(1)

RS

C2

Ceramic

Resonator

To Internal

Logic

Note 1: A series resistor (RS) may be required for

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification, for example, AT-cut

quartz crystal resonators.

ceramic resonators with low drive level.

2: The value of RF varies with the Oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

3: An additional parallel feedback resistor (RP)

may be required for proper ceramic resonator

operation (typical value 1 MΩ).

HS Oscillator mode selects the highest gain setting of

the internal inverter-amplifier. HS mode current

consumption is the highest of the three modes. This

mode is best suited for resonators that require a high

drive setting, for example, AT-cut quartz crystal

resonators or ceramic resonators.

Figure 3-3 and Figure 3-4 show typical circuits for

quartz crystal and ceramic resonators, respectively.

FIGURE 3-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

OSC1

PIC16F785

C1

C2

Quartz

Crystal

(2)

RF

Sleep

OSC2

(1)

RS

To Internal

Logic

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

2: The value of RF varies with the Oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

Note 1: Quartz

crystal

characteristics

vary

according to type, package and

manufacturer. The user should consult the

manufacturer data sheets for specifications

and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

Preliminary

DS41249B-page 25

PIC16F785

TABLE 3-2:

Mode

CERAMIC RESONATORS

3.3.4

EXTERNAL RC MODES

The External Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes, RC and RCIO.

Freq

OSC1 (C1)

OSC2 (C2)

XT

455 kHz

2.0 MHz

68-100 pF

15-68 pF

68-100 pF

15-68 pF

HS

4.0 MHz

8.0 MHz

16.0 MHz

10-68 pF

15-68 pF

10-22 pF

10-68 pF

15-68 pF

10-22 pF

In RC mode, the RC circuit connects to the OSC1 pin.

The OSC2/CLKOUT pin outputs the RC oscillator

frequency divided by 4. This signal may be used to

provide a clock for external circuitry, synchronization,

calibration, test or other application requirements.

Figure 3-5 shows the RC mode connections.

Note:

These values are for design guidance

only. See notes following this table.

TABLE 3-3:

Osc Type

CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

FIGURE 3-5:

RC MODE

Crystal Cap. Range Cap. Range

VDD

Freq

C1

C2

LP

XT

32 kHz

200 kHz

1 MHz

4 MHz

8 MHz

20 MHz

15-33 pF

47-68 pF

15-33 pF

47-68 pF

15-33 pF

REXT

Internal

Clock

OSC1

CEXT

VSS

PIC16F785

HS

OSC2/CLKOUT

FOSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ L ≤ 100 kΩ (VDD < 3.0V)

CEXT > 20 pF

Note:

These values are for design guidance

only. See notes following this table.

In RCIO mode, the RC circuit is connected to the OSC1

pin. The OSC2 pin becomes an additional general

purpose I/O pin. The I/O pin becomes bit 4 of PORTA

(RA4). Figure 3-6 shows the RCIO mode connections.

Note 1: Higher capacitance increases the stability

of the oscillator, but also increases the

start-up time.

FIGURE 3-6:

RCIO MODE

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

VDD

appropriate

components.

values

of

external

REXT

Internal

Clock

OSC1

3: RS may be required to avoid overdriving

CEXT

crystals with low drive level specification.

PIC16F785

VSS

I/O (OSC2)

RA4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ (VDD ≥ 3.0V)

10 kΩ ≤ REXT ≤ 100 kΩ (VDD < 3.0V)

CEXT > 20 pF

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT)

values and the operating temperature. In addition to

this, the oscillator frequency will vary from unit-to-unit

due to normal threshold voltage. Furthermore, the dif-

ference in lead frame capacitance between package

types will also affect the oscillation frequency or low

CEXT values. The user also needs to take into account

variation due to tolerance of external RC components

used.

DS41249B-page 26

Preliminary

PIC16F785

3.4.2.1

Calibration Bits

3.4

Internal Clock Modes

The 8 MHz High-frequency Internal Oscillator

(HFINTOSC) is factory calibrated. The HFINTOSC

calibration bits are stored in the Calibration Word (CALIB)

located in program memory location 2008h. The

Calibration Word is not erased using the specified bulk

erase sequence in the “PIC16F785/PS200 Memory

Programming Specification” (DS41237) and does not

require reprogramming. Reference the “PIC16F785/

PS200 Memory Programming Specification” (DS41237)

for more information on the Calibration Word register.

The PIC16F785 has two independent, internal

oscillators that can be configured or selected as the

system clock source.

1. The HFINTOSC (High-frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The frequency of the HFINTOSC can be

user adjusted ±12% via software using the

OSCTUNE register (Register 3-1).

2. The LFINTOSC (Low-frequency Internal

Oscillator) is uncalibrated and operates at

approximately 31 kHz.

Note:

Address 2008h is beyond the user program

memory space. It belongs to the special

Configuration Memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/PS200

Memory Programming Specification”

(DS41237) for more information.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select (IRCF)

bits.

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 3.5 “Clock Switching”).

3.4.1

INTRC AND INTRCIO MODES

The INTRC and INTRCIO modes configure the internal

oscillators as the system clock source when the device

is programmed using the Oscillator Selection (FOSC)

bits in the Configuration Word (Register 12-1).

In INTRC mode, the OSC1 pin is available for general

purpose I/O. The OSC2/CLKOUT pin outputs the

selected internal oscillator frequency divided by 4. The

CLKOUT signal may be used to provide a clock for

external circuitry, synchronization, calibration, test or

other application requirements.

In INTRCIO mode, the OSC1 and OSC2 pins are

available for general purpose I/O.

3.4.2

HFINTOSC

The High-frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered

approximately ±12% via software using the OSCTUNE

register (Register 3-1).

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). One of seven

frequencies can be selected via software using the

IRCF bits (see Section 3.4.4 “Frequency Select Bits

(IRCF)”).

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz (IRCF ≠ 000) as the

system clock source (SCS = 1) or when Two-Speed

Start-up is enabled (IESO = 1and IRCF ≠ 000).

The HF Internal Oscillator (HTS) bit, (OSCCON<2>),

indicates whether the HFINTOSC is stable or not.

Preliminary

DS41249B-page 27

PIC16F785

When the OSCTUNE register is modified, the

HFINTOSC frequency will begin shifting to the new

frequency. The HFINTOSC clock will stabilize within

1 ms. Code execution continues during this shift. There

is no indication that the shift has occurred.

3.4.2.2

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

register (Register 3-1).

The OSCTUNE register has a tuning range of ±12%.

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number. Due to

process variation, the monotonicity and frequency step

cannot be specified.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

REGISTER 3-1:

OSCTUNE – OSCILLATOR TUNING REGISTER (ADDRESS 90h)

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Center frequency. Oscillator module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 28

Preliminary

PIC16F785

3.4.3

LFINTOSC

3.4.5

HF AND LF INTOSC CLOCK

SWITCH TIMING

The Low-frequency Internal Oscillator (LFINTOSC) is

an uncalibrated (approximate) 31 kHz internal clock

source.

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power. If this is the case, there is a 10 μs

delay after the IRCF bits are modified before the

frequency selection takes place. The LTS/HTS bits will

reflect the current active status of the LFINTOSC and

the HFINTOSC oscillators. The timing of a frequency

selection is as follows:

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 3-1). 31 kHz can be

selected via software using the IRCF bits (see

Section 3.4.4 “Frequency Select Bits (IRCF)”). The

LFINTOSC is also the frequency for the Power-up

Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe

Clock Monitor (FSCM).

1. IRCF bits are modified.

2. If the new clock is shut down, a 10 μs clock start-

The LFINTOSC is enabled by selecting 31 kHz

(IRCF = 000) as the system clock source (SCS = 1), or

when any of the following are enabled:

up delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

• Two-Speed Start-up (IESO = 1and IRCF = 000)

• Power-up Timer (PWRT)

4. CLKOUT is held low and the clock switch

circuitry waits for a rising edge in the new clock.

• Watchdog Timer (WDT)

5. CLKOUT is now connected with the new clock.

HTS/LTS bits are updated as required.

• Fail-Safe Clock Monitor (FSCM)

The LF Internal Oscillator (LTS) bit, (OSCCON<1>),

indicates whether the LFINTOSC is stable or not.

6. Clock switch is complete.

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and the new frequencies are derived from the

HFINTOSC via the postscaler and multiplexer.

3.4.4

FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connect to a postscaler and multiplexer

(see Figure 3-1). The Internal Oscillator Frequency

select bits IRCF<2:0> (OSCCON<6:4>) select the

frequency output of the internal oscillators. One of eight

frequencies can be selected via software:

Note:

Care must be taken to ensure an invalid

voltage or frequency selection is not

selected. An example of an invalid

configuration is selecting 8 MHz when

VDD is 2.0V.

• 8 MHz

• 4 MHz (Default after Reset)

• 2 MHz

• 1 MHz

• 500 kHz

• 250 kHz

• 125 kHz

• 31 kHz

Note:

Following any Reset, the IRCF bits are set

to ‘110’ and the frequency selection is

forced to 4 MHz. The user can modify the

IRCF bits to select a different frequency.

Preliminary

DS41249B-page 29

PIC16F785

When the PIC16F785 is configured for LP, XT or HS

modes, the Oscillator Start-up Timer (OST) is enabled

(see Section 3.3.1 “Oscillator Start-up Timer

(OST)”). The OST timer will suspend program

execution until 1024 oscillations are counted. Two-

Speed Start-up mode minimizes the delay in code

execution by operating from the internal oscillator as

the OST is counting. When the OST count reaches

1024 and the OSTS bit (OSCCON<3>) is set, program

execution switches to the external oscillator.

3.5

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit.

3.5.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit, (OSCCON<0>),

selects the system clock source that is used for the

CPU and peripherals.

• When SCS = 0, the system clock source is

determined by configuration of the FOSC<2:0>

bits in Configuration Word (CONFIG).

3.6.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the

following settings:

• When SCS = 1, the system clock source is

chosen by the internal oscillator frequency

selected by the IRCF bits. After a Reset, SCS is

always cleared.

• IESO = 1(CONFIG<10>) Internal/External Switch

Over bit.

• SCS = 0.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bit. The user can monitor the

OSTS (OSCCON<3>) to determine the

current system clock source.

• FOSC configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

PWRT has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be

anything other than LP, XT or HS mode, then Two-

Speed Start-up is disabled. This is because the external

clock oscillator does not require any stabilization time

after POR or an exit from Sleep.

3.5.2

OSCILLATOR START-UP TIME-OUT

STATUS BIT

The Oscillator Start-up Time-out Status (OSTS) bit,

(OSCCON<3>), indicates whether the system clock is

running from the external clock source as defined by

the FOSC bits, or from internal clock source. In

particular, OSTS indicates that the Oscillator Start-up

Timer (OST) has timed out for LP, XT or HS modes.

3.6.2

TWO-SPEED START-UP

SEQUENCE

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF bits

(OSCCON<6:4>).

3.6

Two-Speed Clock Start-up Mode

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up time

from the time spent awake and can reduce the overall

power consumption of the device.

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

5. OSTS is set.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC as

the clock source and go back to Sleep without waiting

for the primary oscillator to become stable.

7. System clock is switched to external clock

source.

3.6.3

CHECKING EXTERNAL/INTERNAL

CLOCK STATUS

Note:

Executing a SLEEP instruction will abort

the Oscillator Start-up Time and will cause

the OSTS bit (OSCCON<3>) to remain

clear.

Checking the state of the OSTS bit (OSCCON<3>) will

confirm if the PIC16F785 is running from the external

clock source as defined by the FOSC bits in the

Configuration Word (CONFIG) or the internal oscillator.

DS41249B-page 30

Preliminary

PIC16F785

FIGURE 3-7:

TWO-SPEED START-UP

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

INTOSC

TOST

OSC1

0

1

1022 1023

OSC2

Program Counter

PC

PC + 1

PC + 2

System Clock

The frequency of the internal oscillator will depend upon

the value contained in the IRCF bits (OSCCON<6:4>).

Upon entering the Fail-Safe condition, the OSTS bit

(OSCCON<3>) is automatically cleared to reflect that

the internal oscillator is active and the WDT is cleared.

The SCS bit (OSCCON<0>) is not updated. Enabling

FSCM does not affect the LTS bit.

3.7

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to

allow the device to continue to operate in the event of

an oscillator failure. The FSCM can detect oscillator

failure at any point after the device has exited a Reset

or Sleep condition and the Oscillator Start-up Timer

(OST) has expired.

The FSCM sample clock is generated by dividing the

LFINTOSC clock by 64. This will allow enough time

between FSCM sample clocks for a system clock edge

to occur. Figure 3-8 shows the FSCM block diagram.

FIGURE 3-8:

FSCM BLOCK DIAGRAM

Clock Monitor

Latch (CM)

On the rising edge of the sample clock, the monitoring

latch (CM = 0) will be cleared. On a falling edge of the

primary system clock, the monitoring latch will be set

(CM = 1). In the event that a falling edge of the sample

clock occurs, and the monitoring latch is not set, a clock

failure has been detected. The assigned internal

oscillator is enabled when FSCM is enabled as

reflected by the IRCF bits.

(edge-triggered)

Primary

Clock

S

Q

LFINTOSC

Oscillator

÷ 64

C

Q

31 kHz

(~32 μs)

488 Hz

(~2 ms)

Note:

Two-Speed Start-up is automatically

enabled when the Fail-Safe Clock Monitor

mode is enabled.

Clock

Failure

Detected

The FSCM function is enabled by setting the FCMEN

bit in Configuration Word (CONFIG). It is applicable to

all external clock options (LP, XT, HS, EC, RC or I/O

modes).

In the event of an external clock failure, the FSCM will

set the OSFIF bit (PIR1<2>) and generate an oscillator

fail interrupt if the OSFIE bit (PIE1<2>) is set. The

device will then switch the system clock to the internal

oscillator. The system clock will continue to come from

the internal oscillator unless the external clock recovers

and the Fail-Safe condition is exited.

Preliminary

DS41249B-page 31

PIC16F785

3.7.1

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the

execution of a SLEEP instruction, or a modification of

the SCS bit. While in Fail-Safe condition, the

PIC16F785 uses the internal oscillator as the system

clock source. The IRCF bits (OSCCON<6:4>) can be

modified to adjust the internal oscillator frequency

without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the

OSFIF flag can be cleared.

FIGURE 3-9:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

CM Output

(Q)

Failure

Detected

OSCFIF

CM Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative

frequencies in this example have been chosen for clarity.

3.7.2

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at

any point after the device has exited a Reset or Sleep

condition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

For LP, XT or HS mode, the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time; a false clock failure may be

detected (see Figure 3-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable

(the OST has timed out). This is identical to Two-

Speed Start-up mode. Once the external oscillator is

stable, the LFINTOSC returns to its role as the FSCM

source.

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit (OSCCON<3>) to verify the

oscillator start-up and system clock

switchover has successfully completed.

DS41249B-page 32

Preliminary

PIC16F785

REGISTER 3-2:

OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)

U-0

—

R/W-1

IRCF2

R/W-1

IRCF1

R/W-0

IRCF0

R-q

OSTS⁽¹⁾

R-0

LTS

R/W-0

SCS

HTS

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

000= 31 kHz

001= 125 kHz

010= 250 kHz

011= 500 kHz

100= 1 MHz

101= 2 MHz

110= 4 MHz

111= 8 MHz

bit 3

bit 2

bit 1

bit 0

OSTS: Oscillator Start-up Time-out Status bit⁽¹⁾

1= Device is running from the external system clock defined by FOSC<2:0>

0= Device is running from the internal system clock (HFINTOSC or LFINTOSC)

HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit

1= HFINTOSC is stable

0= HFINTOSC is not stable

LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

1= LFINTOSC is stable

0= LFINTOSC is not stable

SCS: System Clock Select bit

1= Internal oscillator is used for system clock

0= Clock source defined by FOSC<2:0>

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator

mode or Fail-Safe mode is enabled, otherwise this bit resets to ‘1’.

Legend:

q = value depends on condition

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

TABLE 3-4:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ch

PIR1

EEIF

EEIE

—

ADIF

ADIE

IRCF2

—

CCP1IF

CCP1IE

IRCF1

—

C2IF

C2IE

C1IF

C1IE

OSFIF

OSFIE

HTS

TMR2IF TMR1IF

TMR2IE TMR1IE

0000 0000

-110 q000

---0 0000

—

0000 0000

-110 q000

---u uuuu

—

8Ch

PIE1

8Fh

OSCCON

OSCTUNE

CONFIG

IRCF0

TUN4

OSTS

TUN3

WDTE

LTS

SCS

TUN0

90h

—

TUN2

FOSC2

TUN1

FOSC1

2007h⁽¹⁾

Legend:

CPD

CP

MCLRE PWRTE

FOSC0

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’, q= value depends on condition. Shaded cells are not used by

oscillators.

Note 1:

See Register 15-1 for operation of all Configuration Word bits.

Preliminary

DS41249B-page 33

PIC16F785

NOTES:

DS41249B-page 34

Preliminary

PIC16F785

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

register are maintained set when using them as analog

inputs. I/O pins configured as analog inputs always

read ‘0’.

4.0

I/O PORTS

There are seventeen general purpose I/O pins and one

input only pin available. Depending on which peripher-

als are enabled, some or all of the pins may not be

available as general purpose I/O. In general, when a

peripheral is enabled, the associated pin may not be

used as a general purpose I/O pin.

When RA1 is configured as a voltage reference output,

the RA1 digital output driver will automatically be

disabled while not affecting the TRISA<1> value.

Note:

Additional information on I/O ports may be

found in the “PICmicro^®Mid-Range MCU

Family Reference Manual” (DS33023).

Note:

The ANSEL0 (91h) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

4.1

PORTA and TRISA Registers

PORTA is

a 6-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 4-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., put the

corresponding output driver in a High-impedance mode).

Clearing a TRISA bit (= 0) will make the corresponding

PORTA pin an output (i.e., put the contents of the output

latch on the selected pin). The exception is RA3, which is

input only and its TRIS bit will always read as ‘1’.

Example 4-1 shows how to initialize PORTA.

EXAMPLE 4-1:

INITIALIZING PORTA

BCF

STATUS,RP0 ;Bank 0

BCF

STATUS,RP1

;

CLRF

MOVLW

ANDWF

BSF

PORTA

F8h

ANSEL0,f

;Init PORTA

;Set RA<2:0> to

; digital I/O

STATUS,RP0 ;Bank 1

MOVLW

MOVWF

0Ch

TRISA

;Set RA<3:2> as inputs

; and set RA<5:4,1:0>

; as outputs

Reading the PORTA register (Register 4-1) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read; this value is modified and then

written to the port data latch. RA3 reads ‘0’ when

MCLRE = 1.

BCF

STATUS,RP0 ;Bank 0

REGISTER 4-1:

PORTA – PORTA REGISTER (ADDRESS: 05h, 105h)

U-0

—

U-0

—

R/W-x

RA5

R/W-x⁽¹⁾

R/W-x

RA3

R/W-x⁽¹⁾R/W-x⁽¹⁾R/W-x⁽¹⁾

RA2 RA1 RA0

bit 0

RA4

bit 7

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RA<5:0>: PORTA I/O Pin bits

1= Port pin is greater than VIH

0= Port pin is less than VIL

Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the

corresponding analog select bit is ‘1’ (see Register 12-1).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 35

PIC16F785

REGISTER 4-2:

TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h, 185h)

U-0

—

U-0

—

R/W-1

R-1

R/W-1

TRISA5⁽²⁾TRISA4⁽²⁾TRISA3⁽¹⁾TRISA2

TRISA1

TRISA0

bit 7

bit 0

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

TRISA<5:0>: PORTA Tri-State Control bit^{(1, 2)}

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note 1: TRISA<3> always reads ‘1’.

2: TRISA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

4.2.1

WEAK PULL-UPS

4.2

Additional Pin Functions

Each of the PORTA pins has an individually

configurable internal weak pull-up. Control bits WPUAx

enable or disable each pull-up. Refer to Register 4-3.

Each weak pull-up is automatically turned off when the

port pin is configured as an output. The pull-ups are

disabled on a Power-on Reset by the RAPU bit

(OPTION_REG<7>). The weak pull-up on RA3 is

automatically enabled when RA3 is configured as

MCLR.

Every PORTA pin on the PIC16F785 has an interrupt-

on-change option and a weak pull-up option. The next

three sections describe these functions.

REGISTER 4-3:

WPUA – WEAK PULL-UP REGISTER (ADDRESS: 95h)^{(1, 2)}

U-0

—

U-0

—

R/W-1

WPUA5⁽⁴⁾WPUA4⁽⁴⁾WPUA3⁽³⁾WPUA2

WPUA1

WPUA0

bit 7

bit 0

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

WPUA<5:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISA = 0).

3: The RA3 pull-up is automatically enabled when configured as MCLR in the

Configuration Word.

4: WPUA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 36

Preliminary

PIC16F785

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, clears the

interrupt by:

4.2.2

INTERRUPT-ON-CHANGE

Each of the PORTA pins is individually configurable as

an interrupt-on-change pin. Control bits IOCAx enable

or disable the interrupt function for each pin. Refer to

Register 4-4. The interrupt-on-change is disabled on a

Power-on Reset.

a) Any read or write of PORTA. This will end the

mismatch condition, then,

b) Clear the flag bit RAIF.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTA. The ‘mismatch’ outputs of the last read are

OR'd together to set, the PORTA Change Interrupt flag

bit (RAIF) in the INTCON register (Register 2-3).

A mismatch condition will continue to set flag bit RAIF.

Reading PORTA will end the mismatch condition and

allow flag bit RAIF to be cleared. The latch holding the

last read value is neither affected by an MCLR nor BOR

Reset. After these resets, the RAIF flag will continue to

be set if a mismatch is present.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

REGISTER 4-4:

IOCA – INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)⁽¹⁾

U-0

—

U-0

—

R/W-0

IOCA5⁽²⁾IOCA4⁽²⁾

R/W-0

IOCA3

R/W-0

IOCA2

R/W-0

IOCA1

R/W-0

IOCA0

bit 7

bit 0

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

IOCA<5:0>: Interrupt-on-change PORTA Control bits⁽²⁾

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be

recognized.

2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 37

PIC16F785

4.2.3

PORTA PIN DESCRIPTIONS AND

DIAGRAMS

4.2.3.2

RA1/AN1/C12IN0-/VREF/ICSPCLK

Figure 4-1 shows the diagram for this pin. The RA1 pin

is configurable to function as one of the following:

Each PORTA pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individ-

ual functions such as the comparator or the A/D, refer

to the appropriate section in this Data Sheet.

• a general purpose I/O

• an analog input for the A/D

• an analog input to Comparators 1 and 2

• a voltage reference input for the A/D

• a buffered or unbuffered voltage reference output

• In-Circuit Serial Programming clock

4.2.3.1

RA0/AN0/C1IN+/ICSPDAT

Figure 4-1 shows the diagram for this pin. The RA0 pin

is configurable to function as one of the following:

FIGURE 4-2:

BLOCK DIAGRAM OF RA1

• a general purpose I/O

• an analog input for the A/D

• an analog input to Comparator 1

• In-Circuit Serial Programming^™data

VROUT

VROE*VREN

CVROE

ANS1

VDD

FIGURE 4-1:

BLOCK DIAGRAM OF RA0

Data Bus

D

Weak

Q

ANS0

Data Bus

D

WR

WPUA

CK

Q

VDD

RAPU

WR

WPUA

CK

Weak

RD

WPUA

RAPU

RD

WPUA

VDD

D

Q

WR

PORTA

CK

VDD

D

Q

I/O pin

D

Q

WR

PORTA

CK

WR

TRISA

CK

VSS

I/O pin

D

Q

RD

TRISA

WR

TRISA

CK

VSS

ANS0

RD

PORTA

RD

TRISA

Q

D

EN

D

Q

RD

PORTA

CK

WR

IOCA

Q

D

EN

D

Q

Q1

RD

IOCA

EN

D

CK

WR

IOCA

Q1

Q3

Interrupt-on-

change

RD

IOCA

EN

D

EN

RD PORTA

Q3

Interrupt-on-

change

EN

To Comparators

To A/D Converter

RD PORTA

To Comparator

To A/D Converter

DS41249B-page 38

Preliminary

PIC16F785

4.2.3.3

RA2/AN2/T0CKI/INT/C1OUT

4.2.3.4

RA3/MCLR/VPP

Figure 4-3 shows the diagram for this pin. The RA2 pin

is configurable to function as one of the following:

Figure 4-4 shows the diagram for this pin. The RA3 pin

is configurable to function as one of the following:

• a general purpose I/O

• a general purpose input

• an analog input for the A/D

• the clock input for TMR0

• as Master Clear Reset with weak pull-up

FIGURE 4-4:

BLOCK DIAGRAM OF RA3

• an external edge triggered interrupt

• a digital output from Comparator 1

Data Bus

D

Q

MCLRE

VDD

WR

WPUA

CK

FIGURE 4-3:

BLOCK DIAGRAM OF RA2

Weak

C1OE

RAPU

RD

WPUA

MCLRE

C1OUT

Reset

VSS

Input

ANS2

VDD

RD

TRISA

Data Bus

D

MCLRE

VSS

Weak

Q

RD

PORTA

WR

WPUA

CK

D

Q

RAPU

Q

D

CK

WR

IOCA

RD

WPUA

EN

D

VDD

D

Q

RD

IOCA

WR

PORTA

CK

Q1

1

EN

D

Interrupt-on-

Change

0

I/O pin

D

Q

Q3

EN

WR

TRISA

CK

VSS

RD PORTA

ANS2

RD

TRISA

RD

PORTA

Q

D

EN

D

Q

CK

WR

IOCA

Q1

RD

IOCA

EN

D

Q3

Interrupt-on-

Change

EN

RD PORTA

To TMR0

To INT

To A/D Converter

Preliminary

DS41249B-page 39

PIC16F785

4.2.3.5

RA4/AN3/T1G/OSC2/CLKOUT

4.2.3.6

RA5/T1CKI/OSC1/CLKIN

Figure 4-5 shows the diagram for this pin. The RA4 pin

is configurable to function as one of the following:

Figure 4-6 shows the diagram for this pin. The RA5 pin

is configurable to function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• a TMR1 gate input

• a general purpose I/O

• a TMR1 clock input

• a crystal/resonator connection

• a clock input

• a crystal/resonator connection

• a clock output

FIGURE 4-6:

BLOCK DIAGRAM OF RA5

FIGURE 4-5:

BLOCK DIAGRAM OF RA4

ANS3

CLK⁽¹⁾

Modes

INTOSC

Mode

Data Bus

D

CLK modes⁽¹⁾

Q

VDD

Data Bus

D

VDD

Q

WR

CK

Weak

WPUA

WR

CK

Weak

WPUA

RAPU

RD

WPUA

RAPU

RD

WPUA

Oscillator

Circuit

VDD

Oscillator

Circuit

VDD

OSC1

OSC2

FOSC/4

1

0

D

Q

I/O pin

D

Q

I/O pin

WR

PORTA

CK

CLKOUT

Enable

WR

CK

PORTA

VSS

INTOSC/

RC/EC⁽²⁾

VSS

S

D

Q

S

D

Q

WR

TRISA

CK

WR

TRISA

CK

INTOSC

Mode

RD

TRISA

CLKOUT

Enable

RD

TRISA

(2)

ANS3

RD

PORTA

RD

D

Q

PORTA

Q

D

EN

D

Q

D

EN

D

Q

CK

WR

IOCA

CK

WR

IOCA

RD

IOCA

Q1

RD

IOCA

EN

D

Q1

EN

D

Interrupt-on-

Change

Q3

Interrupt-on-

CHANGE

Q3

EN

RD PORTA

To TMR1 or CLKGEN

RD PORTA

To T1G

To A/D Converter

Note 1: CLK modes are XT, HS, LP and LPTMR1.

2: When using Timer1 with LP oscillator, the

Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT

Schmitt Trigger is bypassed.

Enable.

2: With CLKOUT option.

DS41249B-page 40

Preliminary

PIC16F785

TABLE 4-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on:

POR, BOR

Value on all

other Resets

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h, 105h PORTA

—

RA5

RA4

RA3

RA2

RA1

RA0

--xx xxxx

--uu uuuu

0000 0000

1111 1111

--11 1111

1111 1111

--11 1111

10h

T1CON

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000

0Bh, 8Bh

INTCON

GIE

RAPU

—

PEIE

INTEDG

—

T0IE

INTE

RAIE

PSA

T0IF

PS2

INTF

PS1

RAIF

PS0

0000 0000

1111 1111

--11 1111

1111 1111

--11 1111

81h, 181h OPTION_REG

85h, 185h TRISA

T0CS

T0SE

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

ANS5 ANS4 ANS3 ANS2 ANS1 ANS0

WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0

91h

95h

ANSEL0

WPUA

ANS7

—

ANS6

—

96h

IOCA

—

IOCA5

BGST

IOCA4

VRBB

IOCA3

VREN

IOCA2

VROE

IOCA1

IOCA0

—

--00 0000

--00 000-

--00 0000

--00 000-

98h

REFCON

CM1CON0

CM2CON1

CVROE

119h

11Bh

Legend:

C1ON

C1OUT

C1OE

—

C1POL

—

C1SP

—

C1R

—

C1CH1

C1CH0

0000 0000

00-- --10

MC1OUT MC2OUT

T1GSS C2SYNC 00-- --10

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Preliminary

DS41249B-page 41

PIC16F785

The TRISB register controls the direction of the

PORTB pins, even when they are being used as

analog inputs. The user must ensure the bits in the

TRISB register are maintained set when using them as

analog inputs. I/O pins configured as analog input

always read ‘0’.

4.3

PORTB and TRISB Registers

PORTB is

a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISB

(Register 4-6). Setting a TRISB bit (= 1) will make the

corresponding PORTB pin an input (i.e., put the

corresponding output driver in a High-impedance

mode). Clearing a TRISB bit (= 0) will make the

corresponding PORTB pin an output (i.e., put the

contents of the output latch on the selected pin).

Example 4-2 shows how to initialize PORTB.

Note:

The ANSEL1 (93h) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

Reading the PORTB register (Register 4-5) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the port data latch.

EXAMPLE 4-2:

INITIALIZING PORTB

BCF

CLRF

BSF

BCF

STATUS,RP0

STATUS,RP1

PORTB

STATUS,RP0

ANSEL1,2

ANSEL1,3

;Bank 0

;

;Init PORTB

;Bank 1

;digital I/O - RB4

;digital I/O - RB5

;Set RB<5:4> as inputs

;and set RB<7:6>

;as outputs

;Bank 0

Pin RB6 is an open drain output. All other PORTB pins

have full CMOS output drivers.

MOVLW 30h

MOVWF TRISB

BCF

STATUS,RP0

REGISTER 4-5:

PORTB – PORTB REGISTER (ADDRESS: 06h, 106h)

(1)

R/W-x

RB7

R/W-x

RB6

R/W-x

RB5

R/W-x

RB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7-4

bit 3-0

RB<7:4>: PORTB General Purpose I/O Pin bits

1= Port pin is greater than VIH

0= Port pin is less than VIL

Unimplemented: Read as ‘0’

Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the

corresponding analog select bit is ‘1’ (see Register 12-2 on page 82).

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 4-6:

TRISB – PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h)

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

TRISB7

TRISB6

TRISB5

TRISB4

bit 7

bit 0

bit 7-4

bit 3-0

TRISB<7:4>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 42

Preliminary

PIC16F785

4.3.1

PORTB PIN DESCRIPTIONS AND

DIAGRAMS

4.3.1.3

RB6

The RB6 pin is configurable to function as the

following:

Each PORTB pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about

individual functions such as the PWM, operational

amplifier, or the A/D, refer to the appropriate section in

this Data Sheet.

• an open drain general purpose I/O

FIGURE 4-8:

BLOCK DIAGRAM OF RB6

Data Bus

4.3.1.1

RB4/AN10/OP2-

D

Q

The RB4/AN10/OP2- pin is configurable to function as

one of the following:

WR

PORTB

CK

• a general purpose I/O

I/O Pin

N

• an analog input to the A/D

• an analog input to Op Amp 2

D

Q

WR

TRISB

CK

VSS

4.3.1.2

RB5/AN11/OP2+

RD

TRISB

The RB5/AN11/OP2+ pin is configurable to function as

one of the following:

Q

D

• a general purpose I/O

• an analog input to the A/D

• an analog input to Op Amp 2

EN

RD

PORTB

FIGURE 4-7:

BLOCK DIAGRAM OF RB4

AND RB5

4.3.1.4

RB7/SYNC

The RB7/SYNC pin is configurable to function as one

of the following:

Data Bus

• a general purpose I/O

VDD

D

Q

• PWM synchronization input and output

WR

CK

PORTB

FIGURE 4-9:

BLOCK DIAGRAM OF RB7

I/O Pin

PH1EN

PH2EN

D

Q

PWM Master

Sync out

WR

TRISB

CK

VSS

ANS10 (RB4)

ANS11 (RB5)

Data Bus

RD

TRISB

VDD

D

Q

D

WR

PORTB

CK

EN

1

RD

PORTB

0

I/O Pin

D

Q

To A/D Converter

To Op Amp 2

WR

TRISB

CK

VSS

RD

TRISB

Q

D

EN

RD

PORTB

to PWM Sync Input

Preliminary

DS41249B-page 43

PIC16F785

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on:

POR, BOR

Value on all

other Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h, 106h PORTB

86h, 186h TRISB

RB7

RB6

RB5

RB4

—

xxxx ----

1111 ----

uuuu ----

1111 ----

TRISB7 TRISB6 TRISB5 TRISB4

93h

ANSEL1

—

ANS11

ANS10

SYNC0

—

ANS9

PH2EN

—

ANS8

PH1EN

—

---- 1111

0000 0000

0--- ----

---- 1111

0000 0000

0--- ----

111h

PWMCON0

OPA2CON

PRSEN

OPAON

PASEN BLANK2 BLANK1 SYNC1

11Dh

Legend:

—

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

DS41249B-page 44

Preliminary

PIC16F785

When RC4 or RC5 is configured as an op amp output,

the corresponding RC4 or RC5 digital output driver will

automatically be disabled regardless of the TRISC<4>

or TRISC<5> value.

4.4

PORTC and TRISC Registers

PORTC is an 8-bit wide, bidirectional port. The

corresponding data direction register is TRISC

(Register 4-8). Setting a TRISC bit (= 1) will make the

corresponding PORTC pin an input (i.e., put the

corresponding output driver in a High-impedance

mode). Clearing a TRISC bit (= 0) will make the

corresponding PORTC pin an output (i.e., put the

contents of the output latch on the selected pin).

Example 4-3 shows how to initialize PORTC.

Note:

The ANSEL0 (91h) and ANSEL1 (93h)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

EXAMPLE 4-3:

INITIALIZING PORTC

Reading the PORTC register (Register 4-7) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the port data latch.

BCF

STATUS,RP0

;Bank 0

BCF

CLRF

BSF

CLRF

MOVLW

MOVWF

STATUS,RP1

PORTC

STATUS,RP0

ANSEL0

ANSEL1

0Ch

;Init PORTC

;Bank 1

;digital I/O

;Set RC<3:2> as inputs

; and set RC<5:4,1:0>

; as outputs

;Bank 0

The TRISC register controls the direction of the

PORTC pins, even when they are being used as

analog inputs. The user must ensure the bits in the

TRISC register are maintained set when using them as

analog inputs. I/O pins configured as analog input

always read ‘0’.

TRISC

BCF

STATUS,RP0

REGISTER 4-7:

PORTC – PORTC REGISTER (ADDRESS: 07h, 107h)

R/W-x⁽¹⁾

R/W-x

RC5

R/W-x

RC4

R/W-x⁽¹⁾

RC1

R/W-x⁽¹⁾

RC0

RC7

RC6

RC3

RC2

bit 7

bit 0

bit 7-0

RC<7:0>: PORTC General Purpose I/O Pin bits

1= Port pin is greater than VIH

0= Port pin is less than VIL

Note 1: Data latches are unknown after a POR, but each port bit reads ‘0’ when the

corresponding analog select bit is ‘1’ (see Registers 12-1 and 12-2 on page 82).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 4-8:

TRISC – PORTC TRI-STATE REGISTER (ADDRESS: 87h, 187h)

R/W-1

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 45

PIC16F785

4.4.1

PORTC PIN DESCRIPTIONS AND

DIAGRAMS

4.4.1.4

RC1/AN5/C12IN1-/PH1

The RC1 is configurable to function as one of the

following:

Each PORTC pin is multiplexed with other functions.

The pins and their combined functions are briefly

described here. For specific information about individual

functions such as the comparator or the A/D, refer to the

appropriate section in this Data Sheet.

• a general purpose I/O

• an analog input for the A/D Converter

• an analog input to Comparators 1 and 2

• a digital output from the Two-Phase PWM

4.4.1.1

RC0/AN4/C2IN+

FIGURE 4-11:

PH1EN

BLOCK DIAGRAM OF RC1

The RC0 is configurable to function as one of the

following:

• a general purpose I/O

PH1

• an analog input for the A/D Converter

• the non-inverting input to Comparator 2

Data Bus

VDD

D

Q

4.4.1.2

RC6/AN8/OP1-

WR

PORTC

CK

Q

The RC6/AN8/OP1- pin is configurable to function as

one of the following:

1

0

I/O Pin

• a general purpose I/O

D

Q

• an analog input for the A/D

• the inverting input for Op Amp 1

WR

TRISC

CK

VSS

ANS5

4.4.1.3

RC7/AN9/OP1+

RD

TRISC

The RC7/AN9/OP1+ pin is configurable to function as

one of the following:

Q

D

• a general purpose I/O

EN

• an analog input for the A/D

• the non-inverting input for Op Amp 1

RD

PORTC

To Comparators

To A/D Converter

FIGURE 4-10:

BLOCK DIAGRAM OF

RC0, RC6 AND RC7

Data Bus

VDD

D

Q

WR

PORTC

CK

I/O Pin

D

Q

WR

TRISC

CK

VSS

ANS4 (RC0)

ANS8 (RC6)

ANS9 (RC7)

RD

TRISC

Q

D

EN

RD

PORTC

To Comparators (RC0)

To A/D Converter

To Op Amp1 (RC6, RC7)

DS41249B-page 46

Preliminary

PIC16F785

4.4.1.5

RC2/AN6/C12IN2-/OP2

4.4.1.7

RC4/C2OUT/PH2

The RC2 is configurable to function as one of the

following:

The RC4 is configurable to function as one of the

following:

• a general purpose I/O

• an analog input for the A/D Converter

• an analog input to Comparators 1 and 2

• an analog output from Op Amp 2

• a digital output from Comparator 2

• a digital output from the Two-Phase PWM

FIGURE 4-13:

BLOCK DIAGRAM OF RC4

4.4.1.6

RC3/AN7/C12IN3-/OP1

C2OE

The RC3 is configurable to function as one of the

following:

PH2EN

PH2

1

0

• a general purpose I/O

C2OUT

Data Bus

• an analog input for the A/D Converter

• an analog input to Comparators 1 and 2

• an analog output for Op Amp 1

VDD

D

Q

FIGURE 4-12:

BLOCK DIAGRAM OF RC2

AND RC3

WR

PORTC

CK

Q

1

Op Amp out

OPAON

0

I/O Pin

Data Bus

D

Q

WR

TRISC

CK

VSS

VDD

D

Q

WR

PORTC

CK

RD

TRISC

I/O Pin

Q

D

Q

EN

WR

CK

VSS

TRISC

RD

ANS6 (RC2)

ANS7 (RC3)

PORTC

RD

TRISC

Q

D

EN

RD

PORTC

To Comparators

To A/D Converter

Preliminary

DS41249B-page 47

PIC16F785

4.4.1.8

RC5/CCP1

FIGURE 4-14:

BLOCK DIAGRAM OF RC5

CCP1CON<1>

CCP1CON<3>

The RC5 is configurable to function as one of the

following:

CCP1CON<2>

CCP out

• a general purpose I/O

• a digital input for the capture/compare

• a digital output for the CCP

Data Bus

VDD

D

Q

WR

PORTC

CK

Q

1

0

I/O Pin

D

Q

WR

TRISC

CK

VSS

RD

TRISC

Q

D

EN

RD

PORTC

to CCP Capture Input

TABLE 4-3:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on:

POR, BOR

Value on all

other Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

07h, 107h PORTC

RC7

—

RC6

—

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx

uuuu uuuu

0000 0000

1111 1111

---- 1111

0000 0000

0--- ----

15h

CCP1CON

DC1B1

DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000

87h, 187h TRISC

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

1111 1111

---- 1111

0000 0000

0--- ----

91h

93h

ANSEL0

ANS7

—

ANS6

—

ANS5

—

ANS4

—

ANS3

ANS2

ANS10

SYNC0

—

ANS1

ANS9

PH2EN

—

ANS0

ANS8

PH1EN

—

ANSEL1

ANS11

111h

PWMCON0

OPA1CON

OPA2CON

PRSEN

OPAON

PASEN BLANK2 BLANK1 SYNC1

11Ch

—

11Dh

—

Legend:

x= unknown, u= unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

DS41249B-page 48

Preliminary

PIC16F785

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode, the Timer0 module

will increment either on every rising or falling edge of

pin RA2/AN2/T0CKI/INT/C1OUT. The incrementing

edge is determined by the source edge (T0SE) control

bit (OPTION_REG<4>). Clearing the T0SE bit selects

the rising edge.

5.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Note 1: Counter mode has specific external clock

requirements. Additional information on

these requirements is available in the

“PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023).

Figure 5-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

2: The ANSEL0 (91h) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

Note:

Additional information on the Timer0

module is available in the “PICmicro^®Mid-

Range MCU Family Reference Manual”

(DS33023).

5.2

Timer0 Interrupt

5.1

Timer0 Operation

A Timer0 interrupt is generated when the TMR0

register timer/counter overflows from FFh to 00h. This

overflow sets the T0IF bit (INTCON<2>). The interrupt

can be masked by clearing the T0IE bit (INTCON<5>).

The T0IF bit must be cleared in software by the Timer0

module Interrupt Service Routine before re-enabling

this interrupt. The Timer0 interrupt cannot wake the

processor from Sleep since the timer is shut-off during

Sleep.

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescaler). If TMR0 is written, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT

(= FOSC/4)

Data Bus

0

1

8

RA2/AN2/T0CKI/INT/C1OUT

1

SYNC 2

Cycles

TMR0

0

1

(1)

Set Flag bit T0IF

on Overflow

(1)

T0CS

T0SE

8-bit

Prescaler

(1)

PSA

8

(1)

WDTE

SWDTEN

PSA

(1)

1

0

PS<0:2>

WDT

Time-out

16-bit

Prescaler

16

31 kHz

INTRC

Watchdog

Timer

(1)

PSA

(2)

WDTPS<3:0>

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the OPTION_REG (see Register 2-2).

2: WDTPS<3:0> are bits in the WDTCON register (see Register 15-2).

Preliminary

DS41249B-page 49

PIC16F785

EXAMPLE 5-1:

CHANGING PRESCALER

(TIMER0→WDT)

5.3

Using Timer0 with an External

Clock

BCF

CLRWDT

CLRF

STATUS,RP0

STATUS,RP1

;Bank 0

;

;Clear WDT

;Clear TMR0 and

; prescaler

;Bank 1

When no prescaler is used, the external clock input is the

same as the prescaler output. The synchronization of

T0CKI, with the internal phase clocks, is accomplished

by sampling the prescaler output on the Q2 and Q4

cycles of the internal phase clocks. Therefore, it is

necessary for T0CKI to be high for at least 2TOSC (and a

small RC delay of 20 ns) and low for at least 2TOSC (and

a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

TMR0

BSF

STATUS,RP0

MOVLW

MOVWF

CLRWDT

b’00101111’

OPTION_REG

;Required if desired

; PS2:PS0 is

; 000 or 001

;

MOVLW

MOVWF

BCF

b’00101xxx’

OPTION_REG

STATUS,RP0

;Set postscaler to

; desired WDT rate

;Bank 0

5.4

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this Data Sheet. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION_REG<3>). Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

selectable via the PS<2:0> bits (OPTION_REG<2:0>).

To change prescaler from the WDT to the TMR0

module, use the sequence shown in Example 5-2. This

precaution must be taken even if the WDT is disabled.

EXAMPLE 5-2:

CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT

;Clear WDT and

; prescaler

;Bank 1

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

BSF

BCF

STATUS,RP0

STATUS,RP1

;

MOVLW

b’xxxx0xxx’

;Select TMR0,

; prescale, and

; clock source

;

5.4.1

SWITCHING PRESCALER

ASSIGNMENT

MOVWF

BCF

OPTION_REG

STATUS,RP0

;Bank 0

The prescaler assignment is fully under software control

(i.e., it can be changed “on the fly” during program

execution). To avoid an unintended device Reset, the

following instruction sequence (Example 5-1 and

Example 5-2) must be executed when changing the

prescaler assignment between Timer0 and WDT.

TABLE 5-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h,

101h

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

0Bh,

8Bh

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

PS0

81h,

181h

INT-

EDG

OPTION_REG RAPU

T0CS

ANS5

T0SE

ANS4

PSA

PS2

PS1

91h

ANSEL0

TRISA

ANS7

—

ANS6

ANS3

ANS2

ANS1

ANS0 1111 1111 1111 1111

85h,

185h

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

Legend:

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0

module.

DS41249B-page 50

Preliminary

PIC16F785

The Timer1 Control register (T1CON), shown in

Register 6-1, is used to enable/disable Timer1 and

select the various features of the Timer1 module.

6.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is the 16-bit counter of the

PIC16F785. Figure 6-1 shows the basic block diagram

of the Timer1 module. Timer1 has the following

features:

Note:

Additional information on timer modules is

available in the “PICmicro^®Mid-Range

MCU

Family

Reference

Manual”

(DS33023).

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt on overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input:

- Selectable gate source; T1G or C2 output

(T1GSS)

- Selectable gate polarity (T1GINV)

• Optional LP oscillator

FIGURE 6-1:

TIMER1 ON THE PIC16F785 BLOCK DIAGRAM

TMR1ON

TMR1GE

T1GINV

TMR1ON

TMR1GE

Set flag bit

To C2 Comparator Module

TMR1 Clock

TMR1IF on

Overflow

(1)

TMR1

Synchronized

clock input

0

TMR1L

TMR1H

1

Oscillator

RA5/T1CKI/OSC1/CLKIN

T1SYNC

*

1

0

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

RA4/AN3/T1G/OSC2/CLKOUT

2

Sleep input

T1CKPS<1:0>

T1OSCEN

INTOSC

TMR1CS

Without CLKOUT

1

LP

Sleep

(2)

0

SYNCC2OUT

T1GSS

*

ST Buffer is low power type when using LP OSC, or high-speed type when using

T1CKI.

Note 1: Timer1 increments on the rising edge.

2: SYNCC2OUT is the synchronized output from Comparator 2 (See Figure 9-2 on

66).

Preliminary

DS41249B-page 51

PIC16F785

The interrupt is cleared by clearing the TMR1IF in the

Interrupt Service Routine.

6.1

Timer1 Modes of Operation

Timer1 can operate in one of three modes:

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

• 16-bit Timer with prescaler

• 16-bit Synchronous counter

• 16-bit Asynchronous counter

6.3

Timer1 Prescaler

In Timer mode, Timer1 is incremented on every instruc-

tion cycle. In Counter mode, Timer1 is incremented on

the rising edge of the external clock input T1CKI. In

addition, the Counter mode clock can be synchronized

to the microcontroller system clock or run

asynchronously.

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits

(T1CON<5:4>) control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

In Counter and Timer modules, the counter/timer clock

can be gated by the Timer1 gate, which can be

selected as either the T1G pin or Comparator 2 output.

6.4

Timer1 Gate

If an external clock oscillator is needed (and the

microcontroller is using the LP oscillator or INTOSC

without CLKOUT), Timer1 can use the LP oscillator as

a clock source.

Timer1 gate source is software configurable to be T1G

pin or the output of Comparator 2. This allows the

device to directly time external events using T1G or

analog events using Comparator 2. See CM2CON1

(Register 9-3) for selecting the Timer1 gate source.

This feature can simplify the software for a Delta-Sigma

A/D Converter and many other applications. For more

information on Delta-Sigma A/D Converters, see the

Microchip web site (www.microchip.com).

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge after any one or

more of the following conditions.

•Timer1 enabled after POR Reset

•Write to TMR1H or TMR1L

Note:

TMR1GE bit (T1CON<6>) must be set to

use either T1G or C2OUT as the Timer1

gate source. See Register 9-3 for more

information on selecting the Timer1 gate

source.

•Timer1 is disabled (TMR1ON = 0)

when T1CKI is high then Timer1 is

enabled (TMR1ON = 1) when T1CKI

is low.

Timer1 gate can be inverted using the T1GINV bit

(T1CON<7>), whether it originates from the T1G pin or

Comparator 2 output. This configures Timer1 to

measure either the active high or active low time

between events.

See Figure 6-2.

6.2

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 interrupt flag bit (PIR1<0>) is set. To

enable the interrupt on rollover, you must set these bits:

• Timer1 Interrupt Enable bit (PIE1<0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>)

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

T1CKI =

1

when TMR1

Enabled

T1CKI =

0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: See note box in Section 6.1.

DS41249B-page 52

Preliminary

PIC16F785

REGISTER 6-1:

T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)

R/W-0

(2)

(1)

T1GINV

bit 7

TMR1GE

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC

TMR1CS TMR1ON

bit 0

(1)

bit 7

bit 6

T1GINV: Timer1 Gate Invert bit

1= Timer1 gate is high true (see bit 6)

0= Timer1 gate is low true (see bit 6)

(2)

TMR1GE: Timer1 Gate Enable bit

If TMR1ON = 0:

This bit is ignored

If TMR1ON = 1:

1= Timer1 is on if Timer1 gate is true (see bit 7)

0= Timer1 is on independent of Timer1 gate

bit 5-4

bit 3

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

T1OSCEN: LP Oscillator Enable Control bit

If System Clock is INTOSC without CLKOUT or LP mode:

1= LP oscillator is enabled for Timer1 clock

0= LP oscillator is off

Else:

This bit is ignored

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from T1CKI pin (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: TMR1GE bit must be set to use either T1G pin or C2OUT, as selected by T1GSS bit

(CM2CON1<1>), as a Timer1 gate source.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 53

PIC16F785

6.5

Timer1 Operation in

Asynchronous Counter Mode

6.6

Timer1 Oscillator

A crystal oscillator circuit is built-in between pins OSC1

(input) and OSC2 (amplifier output). It is enabled by

setting control bit T1OSCEN (T1CON<3>). The

oscillator is a low power oscillator rated for 32.768 kHz.

It will continue to run during Sleep. It is primarily

intended for a 32.768 kHz tuning fork crystal.

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt on overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer

(Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

The Timer1 oscillator is shared with the system LP

oscillator. Thus, Timer1 can use this mode only when

the primary system clock is also the LP oscillator or is

derived from the internal oscillator. As with the system

LP oscillator, the user must provide a software time

delay to ensure proper oscillator start-up.

Note:

The ANSEL0 (91h) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

Sleep mode will not disable the system clock when the

system clock and Timer1 share the LP oscillator.

TRISA<5> and TRISA<4> bits are set when the Timer1

oscillator is enabled. RA5 and RA4 read as ‘0’ and

TRISA<5> and TRISA<4> bits read as ‘1’.

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Note:

The oscillator requires a start-up and

stabilization time before use. Thus,

T1OSCEN should be set and a suitable

delay observed prior to enabling Timer1.

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock will ensure a valid

read (taken care of in hardware). However, the user

should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the

timer may overflow between the reads.

6.7

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To setup the timer to wake the device:

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the timer register.

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6>) must be set

Reading the 16-bit value requires some care.

Examples in the “PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023) show how to read and

write Timer1 when it is running in Asynchronous mode.

The device will wake-up on an overflow. If the GIE bit

(INTCON<7>) is set, the device will wake-up and jump

to the Interrupt Service Routine (0004h) on an overflow.

If the GIE bit is clear, execution will continue with the

next instruction.

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER1

Value on

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

0Bh,

8Bh

INTCON

GIE

PEIE

ADIF

T0IE

INTE

C2IF

RAIE

C1IF

T0IF

INTF

RAIF

0000 0000 0000 0000

0Ch

PIR1

EEIF

CCP1IF

OSFIF

TMR2IF

TMR1IF

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0Eh

TMR1L

TMR1H

T1CON

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

0Fh

10h

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

11Bh

8Ch

CM2CON1 MC1OUT MC2OUT

—

T1GSS

TMR2IE

ANS1

C2SYNC 00-- --10 00-- --10

PIE1

EEIE

ADIE

CCP1IE

ANS5

C2IE

ANS4

C1IE

ANS3

OSFIE

ANS2

TMR1IE

ANS0

0000 0000 0000 0000

1111 1111 1111 1111

91h

ANSEL0

ANS7

ANS6

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

DS41249B-page 54

Preliminary

PIC16F785

7.1

Timer2 Operation

7.0

TIMER2 MODULE

Timer2 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

Reset. The input clock (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits

T2CKPS<1:0> (T2CON<1:0>). The match output of

TMR2 goes through a 4-bit postscaler (which gives a

1:1 to 1:16 scaling inclusive) to generate a TMR2

interrupt (latched in flag bit TMR2IF, (PIR1<1>)).

The Timer2 module timer is an 8-bit timer with the

following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16

by 1’s)

• Interrupt on TMR2 match with PR2

The prescaler and postscaler counters are cleared

when any of the following occurs:

Timer2 has a control register shown in Register 7-1.

TMR2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 7-1 is a simplified block diagram of the Timer2

module. The prescaler and postscaler selection of

Timer2 are controlled by this register.

• A write to the TMR2 register

• A write to the T2CON register

• Any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 7-1:

T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)

U-0

—

R/W-0

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits

0000= 1:1 Postscale

0001= 1:2 Postscale

•

1111= 1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00= Prescaler is 1

01= Prescaler is 4

1x= Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 55

PIC16F785

7.2

Timer2 Interrupt

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon Reset.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

TMR2

Output

Prescaler

Reset

EQ

TMR2

FOSC/4

1:1, 1:4, 1:16

Postscaler

1:1 to 1:16

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

TABLE 7-1:

REGISTERS ASSOCIATED WITH TIMER2

Value on

all other

Resets

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,

8Bh

INTCON

GIE

PEIE

ADIF

T0IE

INTE

C2IF

RAIE

C1IF

T0IF

INTF

RAIF

0000 0000 0000 0000

0Ch

PIR1

EEIF

CCP1IF

OSFIF

TMR2IF

TMR1IF

0000 0000 0000 0000

11h

TMR2

T2CON

PIE1

Holding Register for the 8-bit TMR2 Register

12h

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

8Ch

EEIE

ADIE

CCP1IE

C2IE

C1IE

OSFIE

TMR2IE

TMR1IE

0000 0000 0000 0000

1111 1111 1111 1111

92h

PR2

Timer2 Module Period register

Legend:

x= unknown, u= unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

DS41249B-page 56

Preliminary

PIC16F785

TABLE 8-1:

CCP MODE – TIMER

RESOURCES REQUIRED

8.0

CAPTURE/COMPARE/PWM

(CCP) MODULE

CCP Mode

Capture

Timer Resource

The Capture/Compare/PWM (CCP) module contains a

16-bit register which can operate as a:

Timer1

Timer2

Compare

PWM

• 16-bit Capture register

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Capture/Compare/PWM Register

1

(CCPR1) is

comprised of two 8-bit registers: CCPR1L (low byte)

and CCPR1H (high byte). The CCP1CON register

controls the operation of CCP. The special event

trigger is generated by a compare match and will clear

both TMR1H and TMR1L registers.

REGISTER 8-1:

CCP1CON – CCP OPERATION REGISTER (ADDRESS: 15h)

U-0

—

U-0

—

R/W-0

DC1B1

DC1B0

CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 0

bit 7

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’.

DC1B<1:0>: PWM Duty Cycle Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0

CCP1M<3:0>: CCP Mode Select bits

0000= Capture/Compare/PWM off (resets CCP module)

0001= Unused (reserved)

0010= Compare mode, toggle output on match (CCP1IF bit is set)

0011= Unused (reserved)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCP1IF bit is set)

1001= Compare mode, clear output on match (CCP1IF bit is set)

1010= Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin

is unaffected)

1011= Compare mode, trigger special event (CCP1IF bit is set; TMR1 is reset, and A/D

conversion is started if the A/D module is enabled. CCP1 pin is unaffected.)

110x= PWM mode: CCP1 output is high true.

111x= PWM mode: CCP1 output is low true.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 57

PIC16F785

8.1.4

CCP PRESCALER

8.1

Capture Mode

There are four prescaler settings specified by bits

CCP1M<3:0> (CCP1CON<3:0>). Whenever the CCP

module is turned off, or the CCP module is not in

Capture mode, the prescaler counter is cleared. Any

Reset will clear the prescaler counter.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC5/CCP1. An event is defined as one of the

following and is configured by CCP1CON<3:0>:

• Every falling edge

• Every rising edge

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will not

be cleared, therefore, the first capture may be from a non-

zero prescaler. Example 8-1 shows the recommended

method for switching between capture prescalers. This

example also clears the prescaler counter and will not

generate the “false” interrupt.

• Every 4th rising edge

• Every 16th rising edge

When a capture is made, the interrupt request flag bit

CCP1IF (PIR1<5>) is set. The interrupt flag must be

cleared in software. If another capture occurs before

the value in register CCPR1 is read, the old captured

value is overwritten by the new captured value.

EXAMPLE 8-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

8.1.1

CCP1 PIN CONFIGURATION

CLRF

CCP1CON

;Turn CCP module off

MOVLW

NEW_CAPT_PS;Load the W reg with

; the new prescaler

In Capture mode, the RC5/CCP1 pin should be

configured as an input by setting the TRISC<5> bit.

; move value and CCP ON

Note:

If the RC5/CCP1 pin is configured as an

output, a write to the port can cause a

capture condition.

MOVWF

CCP1CON

;Load CCP1CON with this

; value

8.2

Compare Mode

FIGURE 8-1:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the RC5/CCP1 pin is:

Set Flag bit CCP1IF

(PIR1<5>)

Prescaler

÷ 1, 4, 16

• Driven high

• Driven low

RC5/CCP1

CCPR1H

CCPR1L

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF (PIR1<5>) is set.

Capture

Enable

and

Edge Detect

TMR1H

TMR1L

CCP1CON<3:0>

Q’s

FIGURE 8-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

8.1.2

TIMER1 MODE SELECTION

CCP1CON<3:0>

Mode Select

Timer1 must be running in Timer mode or Synchronized

Counter mode for the CCP module to use the capture

feature. In Asynchronous Counter mode, the capture

operation may not work.

Set Flag bit CCP1IF

(PIR1<5>)

4

RC5/CCP1

CCPR1H CCPR1L

Comparator

8.1.3

SOFTWARE INTERRUPT

Q

S

R

Output

Logic

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<5>) clear to avoid false interrupts and

should clear the flag bit CCP1IF (PIR1<5>) following

any such change in Operating mode.

Match

TMR1H TMR1L

TRISC<5>

Output Enable

Special Event Trigger

Special Event Trigger will:

•

clear TMR1H and TMR1L registers

NOT set interrupt flag bit TMR1F (PIR1<0>)

set the GO/DONE bit (ADCON0<1>)

DS41249B-page 58

Preliminary

PIC16F785

8.2.1

CCP1 PIN CONFIGURATION

8.2.4

SPECIAL EVENT TRIGGER

The user must configure the RC5/CCP1 pin as an

output by clearing the TRISC<5> bit.

In this mode (CCP1M<3:0> = 1011), an internal

hardware trigger is generated, which may be used to

initiate an action. See Register 8-1.

Note:

Clearing the CCP1CON register will force

the RC5/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

The special event trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and CCPR1H, CCPR1L register

pair. The TMR1H, TMR1L register pair is not reset until

the next rising edge of the TMR1 clock. This allows the

CCPR1H, CCPR1L register pair to effectively provide a

16-bit programmable period register for Timer1. The

special event trigger output also starts an A/D

conversion provided that the A/D module is enabled.

8.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or

Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

Note 1: The special event trigger from the CCP

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

8.2.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the RC5/CCP1 pin is not

affected. The CCP1IF (PIR1<5>) bit is set, causing a

CCP interrupt (if enabled). See Register 8-1.

2: Removing the match condition by

changing the contents of the CCPR1H

and CCPR1L register pair between the

clock edge that generates the special

event trigger and the clock edge that

generates the TMR1 Reset, will preclude

the Reset from occurring.

TABLE 8-2:

REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Value on

all other

Resets

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh

INTCON

GIE

PEIE

ADIF

T0IE

INTE

C2IF

RAIE

C1IF

T0IF

INTF

RAIF

0000 0000

8Bh

0Ch

0Eh

0Fh

PIR1

EEIF

CCP1IF

OSFIF

TMR2IF

TMR1IF

0000 0000

xxxx xxxx

0000 0000

uuuu uuuu

TMR1L

TMR1H

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

10h

11Bh

13h

14h

15h

T1CON

T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000

uuuu uuuu

00-- --10

uuuu uuuu

--00 0000

--11 1111

CM2CON1 MC1OUT MC2OUT

—

T1GSS

C2SYNC 00-- --10

xxxx xxxx

CCPR1L

CCPR1H

CCP1CON

TRISC

Capture/Compare/PWM Register 1 Low Byte

Capture/Compare/PWM Register 1 High Byte

xxxx xxxx

—

DC1B1

TRISC5

DC1B0

CCP1M3

TRISC3

CCP1M2 CCP1M1 CCP1M0 --00 0000

87h,

TRISC7

TRISC6

TRISC4

TRISC2

TRISC1

TRISC0

--11 1111

187h

8Ch

PIE1

EEIE

ADIE

CCP1IE

C2IE

C1IE

OSFIE

TMR2IE

TMR1IE

0000 0000

Legend:

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Capture, Compare or Timer1

module.

Preliminary

DS41249B-page 59

PIC16F785

8.3.1

PWM PERIOD

8.3

CCP PWM Mode

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

formula of Equation 8-1.

In Pulse Width Modulation (PWM) mode, the CCP

module produces up to a 10-bit resolution PWM output

on the RC5/CCP1 pin. Since the RC5/CCP1 pin is

multiplexed with the PORTC data latch, the TRISC<5>

must be cleared to make the RC5/CCP1 pin an output.

EQUATION 8-1:

PWM PERIOD

Note:

Clearing the CCP1CON register will force

the PWM output latch to the default

inactive levels. This is not the PORTC I/O

data latch.

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1/[PWM period].

Figure 8-3 shows a simplified block diagram of PWM

operation.

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

For a step by step procedure on how to set up the CCP

module for PWM operation, see Section 8.3.5 “Setup

for PWM Operation”.

• TMR2 is cleared

• The RC5/CCP1 pin is set. (exception: if PWM

duty cycle = 0%, the pin will not be set)

FIGURE 8-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

CCP1CON<5:4>

Duty Cycle Registers

Note:

The Timer2 postscaler (see Section 7.1

“Timer2 Operation”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

CCPR1L

CCPR1H (Slave)

Comparator

RC5/CCP1

R

S

Q

(1)

TMR2

TRISC<5>

Comparator

PR2

Clear Timer2,

toggle PWM pin and

latch duty cycle

Note 1: The 8-bit timer TMR2 register is concate-

nated with the 2-bit internal Q clock, or 2 bits

of the prescaler, to create the 10-bit time

base.

The PWM output (Figure 8-4) has a time base

(period) and a time that the output stays high (duty

cycle). The frequency of the PWM is the inverse of

the period (1/period).

FIGURE 8-4:

CCP PWM OUTPUT

Period

Duty Cycle

TMR2 = 0

TMR2 = PR2

TMR2 = Duty Cycle

DS41249B-page 60

Preliminary

PIC16F785

CCPR1L and DC1B<1:0> can be written to at any time,

but the duty cycle value is not latched into CCPR1H

until after a match between PR2 and TMR2 occurs

(i.e. the period is complete). In PWM mode, CCPR1H

is a read only register.

8.3.2

The PWM duty cycle is specified by writing to the

CCPR1L register and to the DC1B<1:0>

(CCP1CON<5:4>) bits. Up to 10 bits of resolution is

available. The CCPR1L contains the eight MSbs and

the DC1B<1:0> contains the two LSbs. CCPR1L and

DC1B<1:0> can be written to at any time. In PWM

mode, CCPR1H is a read-only register. This 10-bit

value is represented by CCPR1L (CCP1CON<5:4>).

PWM DUTY CYCLE

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitchless PWM operation.

Because of the buffering, the module waits until the

timer resets, instead of starting immediately. This

means that enhanced PWM waveforms do not exactly

match the standard PWM waveforms, but are instead

offset by one full instruction cycle (4 TOSC).

Equation 8-2 is used to calculate the PWM duty cycle

in time.

EQUATION 8-2:

PWM DUTY CYCLE

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the RC5/CCP1 pin is cleared.

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

The maximum PWM resolution is a function of PR2 as

shown by Equation 8-3.

EQUATION 8-3:

PWM RESOLUTION

log[4(PR2 + 1)]

Resolution = ----------------------------------------- b i t s

log(2)

Note:

If the PWM duty cycle value is longer than

the PWM period, the assigned PWM pin(s)

will remain unchanged.

TABLE 8-3:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency

1.22 kHz⁽¹⁾

4.88 kHz⁽¹⁾

19.53 kHz

78.12 kHz

156.3 kHz

208.3 kHz

Timer Prescale (1, 4, 16)

PR2 Value

16

0xFF

10

4

1

0x3F

8

1

0x1F

7

1

0xFF

10

0xFF

10

0x17

6.6

Maximum Resolution (bits)

Note 1: Changing duty cycle will cause a glitch.

Preliminary

DS41249B-page 61

PIC16F785

8.3.3

OPERATION IN SLEEP MODE

8.3.5

SETUP FOR PWM OPERATION

In Sleep mode, all clock sources are disabled. Timer2

will not increment and the state of the module will not

change. If the RC5/CCP1 pin is driving a value, it will

continue to drive that value. When the device wakes

up, it will continue from this state.

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Configure the PWM pin (RC5/CCP1) as an input

by setting the TRISC<5> bit.

2. Set the PWM period by loading the PR2 register.

3. Configure the CCP module for the PWM mode

by loading the CCP1CON register with the

appropriate values.

8.3.3.1

OPERATION WITH FAIL-SAFE

CLOCK MONITOR

If the Fail-Safe Clock Monitor is enabled, a clock failure

will force the CCP to be clocked from the internal

oscillator clock source, which may have a different

clock frequency than the primary clock.

4. Set the PWM duty cycle by loading the CCPR1L

register and CCP1CON<5:4> bits.

5. Configure and start TMR2:

• Clear the TMR2 interrupt flag bit by clearing

the TMR2IF bit (PIR1<1>).

See Section 3.0 “Clock Sources” for additional

details.

• Set the TMR2 prescale value by loading the

T2CKPS bits (T2CON<1:0>).

8.3.4

EFFECTS OF RESET

• Enable Timer2 by setting the TMR2ON bit

(T2CON<2>).

Any Reset will force all ports to Input mode and the

CCP registers to their Reset states.

6. Enable PWM output after a new PWM cycle has

started:

• Wait until TMR2 overflows (TMR2IF bit is

set).

• Enable the RC5/CCP1 pin output by clearing

the TRISC<5> bit.

TABLE 8-4:

REGISTERS ASSOCIATED WITH CCP AND TIMER2

Value on

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

0Bh, INTCON

8Bh

GIE

PEIE

ADIF

T0IE

INTE

C2IF

RAIE

C1IF

T0IF

INTF

RAIF

0000 0000

0Ch PIR1

EEIF

CCP1IF

OSFIF

TMR2IF

TMR1IF

0000 0000

-000 0000

uuuu uuuu

0000 0000

--11 1111

0000 0000

1111 1111

11h

12h

13h

14h

15h

87h

TMR2

Timer2 Module Register

T2CON

CCPR1L

CCPR1H

CCP1CON

TRISC

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000

Capture/Compare/PWM Register 1 Low Byte

Capture/Compare/PWM Register 1 High Byte

xxxx xxxx

—

DC1B1

TRISC5

CCP1IE

DC1B0

TRISC4

C2IE

CCP1M3

TRISC3

C1IE

CCP1M2 CCP1M1 CCP1M0 0000 0000

TRISC7

EEIE

TRISC6

ADIE

TRISC2

OSFIE

TRISC1

TMR2IE

TRISC0

TMR1IE

--11 1111

0000 0000

1111 1111

8Ch PIE1

92h PR2

Legend:

Timer2 Module Period Register

– = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the CCP or Timer2 modules.

DS41249B-page 62

Preliminary

PIC16F785

The polarity of the comparator output can be inverted

by setting the C1POL bit (CM1CON0<4>). Clearing

C1POL results in a non-inverted output.

9.0

COMPARATOR MODULE

The Comparator module has two separate voltage

comparators: Comparator 1 (C1) and Comparator 2

(C2).

A complete table showing the output state versus input

conditions and the polarity bit is shown in Table 9-1.

Each comparator offers the following list of features:

• Control and Configuration register

• Comparator output available externally

• Programmable output polarity

TABLE 9-1:

C1 OUTPUT STATE VERSUS

INPUT CONDITIONS

Input Condition

C1POL

C1OUT

• Interrupt-on-change flags

C1VN > C1VP

C1VN < C1VP

C1VN > C1VP

C1VN < C1VP

0

1

0

1

0

• Wake-up from Sleep

• Configurable as feedback input to the PWM

• Programmable four input multiplexer

• Programmable two input reference selections

• Programmable speed/power

• Output synchronization to Timer1 clock input

(Comparator C2 only)

Note 1: The internal output of the comparator is

latched at the end of each instruction

cycle. External outputs are not latched.

9.1

Control Registers

2: The C1 interrupt will operate correctly

Both comparators have separate control and

Configuration registers: CM1CON0 for C1 and

CM2CON0 for C2. In addition, Comparator C2 has a

second control register, CM2CON1, for synchronization

control and simultaneous reading of both comparator

outputs.

with C1OE set or cleared.

3: To output C1 on RA2/AN2/T0CKI/INT/

C1OUT:(C1OE = 1) and (C1ON = 1) and

(TRISA<2> = 0).

C1SP (CM1CON0<3>) configures the speed of the

comparator. When C1SP is set, the comparator

operates at its normal speed. Clearing C1SP operates

the comparator in a slower, low-power mode.

9.1.1

COMPARATOR C1 CONTROL

REGISTER

The CM1CON0 register (shown in Register 9-1)

contains the control and Status bits for the following:

• Comparator enable

• Comparator input selection

• Comparator reference selection

• Output mode

• Comparator speed

Setting C1ON (CM1CON0<7>) enables Comparator

C1 for operation.

Bits C1CH<1:0> (CM1CON0<1:0>) select the

comparator input from the four analog pins AN<7:5,1>.

Note:

To use AN<7:5,1> as analog inputs the

appropriate bits must be programmed to

‘1’ in the ANSEL0 register.

Setting C1R (CM1CON0<2>) selects the C1VREF

output of the comparator voltage reference module as

the reference voltage for the comparator. Clearing C1R

selects the C1IN+ input on the RA0/AN0/C1IN+/

ICSPDAT pin.

The output of the comparator is available internally via

the C1OUT flag (CM1CON0<6>). To make the output

available for an external connection, the C1OE bit

(CM1CON0<5>) must be set.

Preliminary

DS41249B-page 63

PIC16F785

FIGURE 9-1:

COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM

C1CH<1:0>

C1POL

To

Data Bus

2

D

Q

Q1

EN

RA1/AN1/C12IN0-/VREF/ICSPCLK

RC1/AN5/C12IN1-/PH1

0

RD_CM1CON0

Set C1IF

1

MUX

2

D

Q

RC2/AN6/C12IN2-/OP2

Q3*RD_CM1CON0

EN

CL

To PWM Logic

C1OE

RC3/AN7/C12IN3-/OP1

3

NRESET

(1)

C1ON

C1R

C1SP

C1VN

C1VP

0

MUX

1

RA0/AN0/C1IN+/ICSPDAT

C1VREF

C1OUT

C1

(2)

RA2/AN2/T0CKI/INT/C1OUT

C1POL

Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.

2: Output shown for reference only. For more detail, see Figure 4-3.

DS41249B-page 64

Preliminary

PIC16F785

REGISTER 9-1:

CM1CON0 – COMPARATOR C1 CONTROL REGISTER 0 (ADDRESS: 119h)

R/W-0

C1ON

R-0

R/W-0

C1OE

R/W-0

C1SP

R/W-0

C1R

R/W-0

C1CH0

bit 0

C1OUT

C1POL

C1CH1

bit 7

bit 6

C1ON: Comparator C1 Enable bit

1= C1 Comparator is enabled

0= C1 Comparator is disabled

C1OUT: Comparator C1 Output bit

If C1POL = 1(inverted polarity):

C1OUT = 1, C1VP < C1VN

C1OUT = 0, C1VP > C1VN

If C1POL = 0(non-inverted polarity):

C1OUT = 1, C1VP > C1VN

C1OUT = 0, C1VP < C1VN

bit 5

bit 4

bit 3

bit 2

bit 1-0

C1OE: Comparator C1 Output Enable bit

1= C1OUT is present on the RA2/AN2/T0CKI/INT/C1OUT pin⁽¹⁾

0= C1OUT is internal only

C1POL: Comparator C1 Output Polarity Select bit

1= C1OUT logic is inverted

0= C1OUT logic is not inverted

C1SP: Comparator C1 Speed Select bit

1= C1 operates in normal speed mode

0= C1 operates in low-power, slow speed mode

C1R: Comparator C1 Reference Select bit (non-inverting input)

1= C1VP connects to C1VREF output

0= C1VP connects to RA0/AN0/C1IN+/ICSPDAT

C1CH<1:0>: Comparator C1 Channel Select bits

00= C1VN of C1 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK

01= C1VN of C1 connects to RC1/AN5/C12IN1-/PH1

10= C1VN of C1 connects to RC2/AN6/C12IN2-/OP2

11= C1VN of C1 connects to RC3/AN7/C12IN3-/OP1

Note 1: C1OUT will only drive RA2/AN2/T0CKI/INT/C1OUT if:

(C1OE = 1) and (C1ON = 1) and (TRISA<2> = 0)

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 65

PIC16F785

The comparator output, C2OUT, can be inverted by

setting the C2POL bit (CM2CON0<4>). Clearing

C2POL results in a non-inverted output.

9.1.2

COMPARATOR C2 CONTROL

REGISTERS

The CM2CON0 register is a functional copy of the

CM1CON0 register described in Section 9.1.1

“Comparator C1 Control Register”. A second control

register, CM2CON1, is also present for control of an

additional synchronizing feature, as well as mirrors of

both comparator outputs.

A complete table showing the output state versus input

conditions and the polarity bit is shown in Table 9-2.

TABLE 9-2:

C2 OUTPUT STATE VERSUS

INPUT CONDITIONS

9.1.2.1

Control Register CM2CON0

Input Condition

C2POL

C2OUT

The CM2CON0 register, shown in Register 9-2, con-

tains the control and Status bits for Comparator C2.

C2VN > C2VP

C2VN < C2VP

C2VN > C2VP

C2VN < C2VP

0

1

0

1

0

Setting C2ON (CM2CON0<7>) enables Comparator

C2 for operation.

Bits C2CH<1:0> (CM2CON0<1:0>) select the

comparator input from the four analog pins, AN<7:5,1>.

Note:

To use AN<7:5,1> as analog inputs, the

appropriate bits must be programmed to 1

in the ANSEL0 register.

Note 1: The internal output of the comparator is

latched at the end of each instruction

cycle. External outputs are not latched.

C2R (CM2CON0<2>) selects the reference to be used

with the comparator. Setting C2R (CM2CON0<2>)

selects the C2VREF output of the comparator voltage

reference module as the reference voltage for the

comparator. Clearing C2R selects the C2IN+ input on

the RC0/AN4/C2IN+ pin.

2: The C2 interrupt will operate correctly

with C2OE set or cleared. An external

output is not required for the C2 interrupt.

3: For C2 output on RC4/C2OUT/PH2:

(C2OE = 1) and (C2ON = 1) and

(TRISA<4> = 0).

The output of the comparator is available internally via

the C2OUT bit (CM2CON0<6>). To make the output

available for an external connection, the C2OE bit

(CM2CON0<5>) must be set.

C2SP (CM2CON0<3>) configures the speed of the

comparator. When C2SP is set, the comparator

operates at its normal speed. Clearing C2SP operates

the comparator in low-power mode.

FIGURE 9-2:

COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM

C2POL

To

Data Bus

D

Q

Q1

EN

RD_CM2CON0

2

C2CH<1:0>

Set C2IF

D

Q

Q3*RD_CM2CON0

EN

CL

C2ON⁽¹⁾

C2SP

RA1/AN1/C12IN0-/VREF/ICSPCLK

RC1/AN5/C12IN1-/PH1

0

1

NRESET

C2OUT

C2VN

C2VP

MUX

To PWM Logic

C2

RC2/AN6/C12IN2-/OP2

2

RC3/AN7/C12IN3-/OP1

3

C2SYNC

C20E

C2POL

0

C2R

MUX

D

Q

1

(3)

RC4/C2OUT/PH2

SYNCC2OUT⁽²⁾

RC0/AN4/C2IN+

0

From TMR1

Clock

MUX

1

C2VREF

Note 1:

When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.

Timer1 gate control (see Figure 6-1).

Output shown for reference only. For more detail, see Figure 4-13.

2:

3:

DS41249B-page 66

Preliminary

PIC16F785

REGISTER 9-2:

CM2CON0 – COMPARATOR C2 CONTROL REGISTER 0 (ADDRESS: 11AH)

R/W-0

C2ON

R-0

R/W-0

C2OE

R/W-0

C2SP

R/W-0

C2R

R/W-0

C2CH0

bit 0

C2OUT

C2POL

C2CH1

bit 7

bit 6

C2ON: Comparator C2 Enable bit

1= C2 Comparator is enabled

0= C2 Comparator is disabled

C2OUT: Comparator C2 Output bit

If C2POL = 1(inverted polarity):

C2OUT = 1, C2VP < C2VN

C2OUT = 0, C2VP > C2VN

If C2POL = 0(non-inverted polarity):

C2OUT = 1, C2VP > C2VN

C2OUT = 0, C2VP < C2VN

bit 5

bit 4

bit 3

bit 2

bit 1-0

C2OE: Comparator C2 Output Enable bit

1= C2OUT is present on RC4/C2OUT/PH2⁽¹⁾

0= C2OUT is internal only

C2POL: Comparator C2 Output Polarity Select bit

1= C2OUT logic is inverted

0= C2OUT logic is not inverted

C2SP: Comparator C2 Speed Select bit

1= C2 operates in normal speed mode

0= C2 operates in low power, slow speed mode.

C2R: Comparator C2 Reference Select bits (non-inverting input)

1= C2VP connects to C2VREF

0= C2VP connects to RC0/AN4/C2IN+

C2CH<1:0>: Comparator C2 Channel Select bits

00= C2VN of C2 connects to RA1/AN1/C12IN0-/VREF/ICSPCLK

01= C2VN of C2 connects to RC1/AN5/C12IN1-/PH1

10= C2VN of C2 connects to RC2/AN6/C12IN2-/OP2

11= C2VN of C2 connects to RC3/AN7/C12IN3-/OP1

Note 1: C2OUT will only drive RC4/C2OUT/PH2 if:

(C2OE = 1) and (C2ON = 1) and (TRISC<4> = 0).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 67

PIC16F785

The CM2CON1 register also contains mirror copies of

both comparator outputs, MC1OUT and MC2OUT

(CM2CON1<7:6>). The ability to read both outputs

simultaneously from a single register eliminates the

timing skew of reading separate registers.

9.1.2.2

Control Register CM2CON1

Comparator C2 has one additional feature: its output

can be synchronized to the Timer1 clock input. Setting

C2SYNC (CM2CON1<0>) synchronizes the output of

Comparator 2 to the falling edge of Timer1’s clock input

(see Figure 9-2 and Register 9-3).

Note:

Obtaining the status of C1OUT or C2OUT

by reading CM2CON1 does not affect the

comparator interrupt mismatch registers.

REGISTER 9-3:

CM2CON1 – COMPARATOR C2 CONTROL REGISTER 1 (ADDRESS: 11Bh)

R-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

MC1OUT MC2OUT

bit 7

T1GSS C2SYNC

bit 0

bit 7

MC1OUT: Mirror Copy of C1OUT bit (CM1CON0<6>)

MC2OUT: Mirror Copy of C2OUT bit (CM2CON0<6>)

Unimplemented: Read as ‘0’

bit 6

bit 5-2

bit 1

T1GSS: Timer1 Gate Source Select bit

1= Timer1 gate source is RA4/AN3/T1G/OSC2/CLKOUT

0= Timer1 gate source is SYNCC2OUT.

bit 0

C2SYNC: C2 Output Synchronous Mode bit

1= C2 output is synchronous to falling edge of TMR1 clock

0= C2 output is asynchronous

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 68

Preliminary

PIC16F785

9.2

Comparator Outputs

9.3

Comparator Interrupts

The comparator outputs are read through the

CM1CON0, COM2CON0 or CM2CON1 registers.

CM1CON0 and CM2CON0 each contain the individual

comparator output of Comparator 1 and Comparator 2,

respectively. CM2CON2 contains a mirror copy of both

comparator outputs facilitating a simultaneous read of

both comparators. These bits are read-only. The

comparator outputs may also be directly output to the

RA2/AN2/T0CKI/INT/C1OUT and RC4/C2OUT/PH2

I/O pins. When enabled, multiplexers in the output path

of the RA2 and RC4 pins will switch and the output of

each pin will be the unsynchronized output of the com-

parator. The uncertainty of each of the comparators is

related to the input offset voltage and the response time

given in the specifications. Figure 9-1 and Figure 9-2

show the output block diagrams for Comparators 1 and

2, respectively.

The comparator interrupt flags are set whenever there

is a change in the output value of its respective

comparator. Software will need to maintain information

about the status of the output bits, as read from

CM2CON0<7:6>, to determine the actual change that

has occurred. The CxIF bits, PIR1<4:3>, are the

Comparator Interrupt Flags. Each comparator interrupt

bit must be reset in software by clearing it to ‘0’. Since

it is also possible to write a ‘1’ to this register, a

simulated interrupt may be initiated.

The CxIE bits (PIE1<4:3>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CxIF bits will still be set if an interrupt condition occurs.

The comparator interrupt of the PIC16F785 differs from

previous designs in that the interrupt flag is set by the

mismatch edge and not the mismatch level. This

means that the interrupt flag can be reset without the

additional step of reading or writing the CMxCON0

register to clear the mismatch registers. When the

mismatch registers are not cleared, an interrupt will not

occur when the comparator output returns to the

previous state. When the mismatch registers are

cleared, an interrupt will occur when the comparator

returns to the previous state.

The TRIS bits will still function as an output enable/

disable for the RA2/AN2/T0CKI/INT/C1OUT and RC4/

C2OUT/PH2 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C1POL and C2POL bits (CMxCON0<4>).

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS bit

(CM2CON1<1>). The Timer1 gate feature can be used

to time the duration or interval of analog events. The

output of Comparator 2 can also be synchronized with

Timer1 by setting the C2SYNC bit (CM2CON1<0>).

When enabled, the output of Comparator 2 is latched on

the falling edge of Timer1 clock source. If a prescaler is

used with Timer1, Comparator 2 is latched after the

prescaler. To prevent a race condition, the Comparator 2

output is latched on the falling edge of the Timer1 clock

source and Timer1 increments on the rising edge of its

clock source. See the Comparator 2 Block Diagram

(Figure 9-2) and the Timer1 Block Diagram (Figure 6-1)

for more information.

Note 1: If a change in the CMxCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF (PIR1<4:3>)

interrupt flag may not get set.

2: When either comparator is first enabled,

bias circuitry in the Comparator module

may cause an invalid output from the

comparator until the bias circuitry is sta-

ble. Allow about 1 μs for bias settling then

clear the mismatch condition and inter-

rupt flags before enabling comparator

interrupts.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

9.4

Effects of Reset

A Reset forces all registers to their Reset state. This

disables both comparators.

Preliminary

DS41249B-page 69

PIC16F785

NOTES:

DS41249B-page 70

Preliminary

PIC16F785

10.1.2

VOLTAGE REFERENCE

ACCURACY/ERROR

10.0 VOLTAGE REFERENCES

There are two voltage references available in the

PIC16F785: The voltage referred to as the comparator

reference (CVREF) is a variable voltage based on VDD;

The voltage referred to as the VR reference (VR) is a

fixed voltage derived from a stable band gap source.

Each source may be individually routed internally to the

comparators or output, buffered or unbuffered, on the

RA1/AN1/C12IN0-/VREF/ICSPCLK pin.

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 10-1) keep CVREF from approaching VSS or

VDD. The exception is when the module is disabled by

clearing all CVROE, C1VREN and C2VREN bits. When

disabled, the reference voltage is VSS when VR<3:0>

is ‘0000’ and the VRR (VRCON<5>) bit is set. This

allows the comparators to detect a zero-crossing and

not consume CVREF module current.

10.1 Comparator Reference

The comparator module also allows the selection of an

internally generated voltage reference for one of the

comparator inputs. The VRCON register

(Register 10-1) controls the voltage reference module

shown in Figure 10-1.

The voltage reference is VDD derived and therefore, the

CVREF output changes with fluctuations in VDD. The

tested absolute accuracy of the comparator voltage

reference can be found in Table 18-8.

10.1.1

CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels, 16 in a high range and 16 in a low range.

The following equation determines the output voltages:

EQUATION 10-1: CVREF OUTPUT VOLTAGE

VRR = 1 (low range):

CVREF = VR<3:0> X VDD/24

VRR = 0 (high range):

CVREF = (VDD/4) + (VR<3:0> X VDD/32)

FIGURE 10-1:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

VRR

8R

16-1 Analog

MUX

(1)

CVREN

15

CVREF

·

0

VR3:VR0

CVROE

C1VREN

C2VREN

C1VREF to

Comparator 1

Input

1

0

C2VREF to

1

0

Comparator 2

VR

1.2 V

Input

Note 1: See Register 10-1, bits 3-0.

Preliminary

DS41249B-page 71

PIC16F785

REGISTER 10-1: VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99H)

R/W-0

C1VREN⁽¹⁾C2VREN⁽¹⁾

R/W-0

VRR

U-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

bit 7

bit 0

bit 7

bit 6

bit 5

C1VREN: Comparator 1 Voltage Reference Enable bit⁽¹⁾

1= CVREF circuit powered on and routed to C1VREF input of comparator 1

0= 1.2 Volt VR routed to C1VREF input of comparator 1

C2VREN: Comparator 2 Voltage Reference Enable bit⁽¹⁾

1= CVREF circuit powered on and routed to C2VREF input of comparator 2

0= 1.2 Volt VR routed to C2VREF input of comparator 2

VRR: Comparator Voltage Reference CVREF Range Selection bit

1= Low Range

0= High Range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: Comparator Voltage Reference CVREF Value Selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1and CVREN = 1: CVREF = (VR<3:0> x VDD/24)

When VRR = 0and CVREN = 1: CVREF = (VDD/4) + (VR<3:0> x VDD/32)

When CxVREN = 0and VREN = 1: CxVREF = 1.2V from VR module

Note 1: When C1VREN, C2VREN and CVROE (Register 10-2) are all low, the CVREF circuit

is powered down and does not contribute to IDD current.

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = bit is cleared x = bit is unknown

DS41249B-page 72

Preliminary

PIC16F785

10.2 VR Reference Module

The VR Reference module generates a 1.2V nominal

output voltage for use by the ADC and comparators. The

output voltage can also be brought out to the VREF pin

for user applications. This module uses a band gap as a

reference. See Table 18-9 for detailed specifications.

Register 10-2 shows the control register for the VR

module.

REGISTER 10-2: REFCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 98h)

U-0

—

U-0

—

R-0

R/W-0

VRBB

R/W-0

VREN

R/W-0

VROE

R/W-0

U-0

—

BGST

CVROE

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as ‘0’

BGST: Band Gap Reference Voltage Stable Flag bit

1= Reference is stable

0= Reference is not stable

bit 4

bit 3

bit 2

VRBB: Voltage Reference Buffer Bypass bit

1= VREF output is not buffered. Power is removed from buffer amplifier.

0= VREF output is buffered⁽¹⁾

VREN: Voltage Reference Enable bit (VR = 1.2V nominal)

1= VR reference is enabled

0= VR reference is disabled and does not consume any current

VROE: Voltage Reference Output Enable bit

If CVROE = 0:

1= VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is 1.2 volt VR analog reference

0= Disabled, 1.2 volt VR analog reference is used internally only

If CVROE = 1:

VROE has no effect.

bit 1

bit 0

CVROE: Comparator Voltage Reference Output Enable bit (see Figure 10-2)

1= VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is CVREF voltage

0= VREF output on RA1/AN1/C12IN0-/VREF/ICSPCLK pin is controlled by VROE

Unimplemented: Read as ‘0’

Note 1: Buffer amplifier common mode limitations require VREF ≤ (VDD - 1.4)V for buffered

output.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 73

PIC16F785

10.2.1

VR STABILIZATION PERIOD

When the Voltage Reference module is enabled, it will

require some time for the reference and its amplifier

circuits to stabilize. The user program must include a

small delay routine to allow the module to settle. See

Section 18.0 “Electrical Specifications” for the

minimum delay requirement.

FIGURE 10-2:

VR REFERENCE BLOCK DIAGRAM

(1)

VREN

VRBB

CVREF

CVROE

(CVROE + (VREN*VROE))

VROUT

1

0

EN

1

0

RA1/AN1/C12IN0-/VREF

1X

VRIN

Voltage

Reference

Analog

Buffer

RDY

VR

BGST

To CVREF MUX

Note 1: Buffered output requires VRIN = (VDD - 1.4)V.

TABLE 10-1: REGISTERS ASSOCIATED WITH THE COMPARATOR AND VOLTAGE REFERENCE

MODULES

Value on

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

119h

11Ah

11Bh

CM1CON0 C1ON

CM2CON0 C2ON

C1OUT C1OE C1POL C1SP

C2OUT C2OE C2POL C2SP

C1R

C2R

—

C1CH1

C2CH1

C1CH0

C2CH0

0000 0000 0000 0000

CM2CON1 MC1OUT MC2OUT

—

T1GSS C2SYNC 00-- --10 00-- --10

85h,

185h

TRISA

TRISC

PORTA

PORTC

—

TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111

87h,

187h

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

05h,

105h

—

RA5

RC5

RA4

RC4

RA3

RC3

RA2

RC2

RA1

RC1

RA0

RC0

--xx xxxx --uu uuuu

xxxx xxxx uuuu uuuu

1111 1111 1111 1111

07h,

107h

RC7

RC6

91h

0Ch

8Ch

98h

99h

ANSEL0

PIR1

ANS7

EEIF

EEIE

—

ANS6

ADIF

ADIE

—

ANS5

ANS4

ANS3

C1IF

C1IE

ANS2

ANS1

ANS0

CCP1IF C2IF

CCP1IE C2IE

OSFIF TMR2IF TMR1IF 0000 ---0 0000 ---0

OSFIE TMR2IE TMR1IE 0000 ---0 0000 ---0

PIE1

REFCON

VRCON

BGST VRBB VREN VROE CVROE

VR3 VR2 VR1

—

--00 000- --00 000-

000- 0000 000- 0000

C1VREN C2VREN VRR

—

VR0

Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for comparator.

DS41249B-page 74

Preliminary

PIC16F785

11.2 OPAxCON Register

11.0 OPERATIONAL AMPLIFIER

(OPA) MODULE

The OPA module is enabled by setting the OPAON bit

(OPAxCON<7>). When enabled, OPAON forces the

output driver of RC3/AN7/C12IN3-/OP1 for OPA1, and

RC2/AN6/C12IN2-/OP2 for OPA2, into tri-state to prevent

contention between the driver and the OPA output.

The OPA module has the following features:

• Two independent Operational Amplifiers

• External connections to all ports

• 3 MHz Gain Bandwidth Product (GBWP)

Note:

When OPA1 or OPA2 is enabled, the

RC3/AN7/C12IN3-/OP1 pin, or

11.1 Control Registers

The OPA1CON register, shown in Register 11-1,

controls OPA1. OPA2CON, shown in Register 11-2,

controls OPA2.

RC2/AN6/C12IN2-/OP2 pin, respectively,

is driven by the op amp output, not by the

PORTC driver. Refer to Table 18-11 for the

electrical specifications for the op amp

output drive capability.

FIGURE 11-1:

OPA MODULE BLOCK DIAGRAM

OPA1CON<OPAON>

RC7/AN9/OP1+

OPA1

RC6/AN8/OP1-

RC3/AN7/C12IN3-/OP1

TO ADC and Comparator MUXs

OPA2CON<OPAON>

RB5/AN11/OP2+

OPA2

RB4/AN10/OP2-

RC2/AN6/C12IN2-/OP2

TO ADC and Comparator MUXs

Preliminary

DS41249B-page 75

PIC16F785

REGISTER 11-1: OPA1CON – OP AMP 1 CONTROL REGISTER (ADDRESS: 11Ch)

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OPAON

bit 7

bit 0

bit 7

OPAON: Op Amp Enable bit

1= Op Amp 1 is enabled

0= Op Amp 1 is disabled

bit 6-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 11-2:

OPA2CON – OP AMP 2 CONTROL REGISTER (ADDRESS: 11Dh)

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

OPAON

bit 7

bit 0

bit 7

OPAON: Op Amp Enable bit

1= Op Amp 2 is enabled

0= Op Amp 2 is disabled

bit 6-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 76

Preliminary

PIC16F785

Leakage current is a measure of the small source or

sink currents on the OPA+ and OPA- inputs. To minimize

the effect of leakage currents, the effective impedances

connected to the OPA+ and OPA- inputs should be kept

as small as possible and equal.

11.3 Effects of a Reset

A device Reset forces all registers to their Reset state.

This disables both op amps.

11.4 OPA Module Performance

Input offset voltage is a measure of the voltage

difference between the OPA+ and OPA- inputs in a

closed loop circuit with the OPA in its linear region. The

offset voltage will appear as a DC offset in the output

equal to the input offset voltage, multiplied by the gain

of the circuit. The input offset voltage is also affected by

the common mode voltage.

Common AC and DC performance specifications for

the OPA module:

• Common Mode Voltage Range

• Leakage Current

• Input Offset Voltage

• Open Loop Gain

Open loop gain is the ratio of the output voltage to the

differential input voltage, (OPA+) - (OPA-). The gain is

greatest at DC and falls off with frequency.

• Gain Bandwidth Product (GBWP)

Common mode voltage range is the specified voltage

range for the OPA+ and OPA- inputs, for which the OPA

module will perform to within its specifications. The

OPA module is designed to operate with input voltages

between 0 and VDD-1.4V. Behavior for common mode

voltages greater than VDD-1.4V, or below 0V, are

beyond the normal operating range.

Gain Bandwidth Product or GBWP is the frequency

at which the open loop gain falls off to 0 dB.

11.5 Effects of Sleep

When enabled, the op amps continue to operate and

consume current while the processor is in Sleep mode.

TABLE 11-1: REGISTERS ASSOCIATED WITH THE OPA MODULE

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

11Ch

11Dh

91h

OPA1CON

OPA2CON

ANSEL0

OPAON

ANS7

—

0--- ---- 0--- ----

ANS6

—

ANS5

—

ANS4

—

ANS3

ANS2

ANS1

ANS0 1111 1111 1111 1111

ANS8 ---- 1111 ---- 1111

93h

ANSEL1

ANS11 ANS10 ANS9

86h, 186h TRISB

87h, 187h TRISC

TRISB7 TRISB6 TRISB5 TRISB4

—

1111 ---- 1111 ----

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used for the OPA module.

Preliminary

DS41249B-page 77

PIC16F785

NOTES:

DS41249B-page 78

Preliminary

PIC16F785

12.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The analog-to-digital converter (A/D) allows conversion

of an analog input signal to

a 10-bit binary

representation of that signal. The PIC16F785 has

twelve analog I/O inputs, plus two internal inputs,

multiplexed into one sample and hold circuit. The output

of the sample and hold is connected to the input of the

converter. The converter generates a binary result via

successive approximation and stores the result in a

10-bit register. The voltage reference used in the

conversion is software selectable to either VDD or a

voltage applied by the VREF pin. Figure 12-1 shows the

block diagram of the A/D on the PIC16F785.

FIGURE 12-1:

A/D BLOCK DIAGRAM

VDD

VCFG = 0

VCFG = 1

VREF

RA0/AN0/C1IN+/ICSPDAT

0

RA1/AN1/C12IN0-/VREF/ICSPCLK

RA2/AN2/T0CKI/INT/C1OUT

RA4/AN3/T1G/OSC2/CLKOUT

RC0/AN4/C2IN+

RC1/AN5/C12IN1-/PH1

RC2/AN6/C12IN2-/OP2

RC3/AN7/C12IN3-/OP1

RC6/AN8/OP1-

A/D

10

GO/DONE

RC7/AN9/OP1+

ADFM

RB4/AN10/OP2-

(1)

ADON

RB5/AN11/OP2+

ADRESH ADRESL

CVREF

VSS

13

VR

CHS<3:0>

Note 1: When ADON = 0 all input channels are disconnected from

ADC (no loading).

Preliminary

DS41249B-page 79

PIC16F785

12.1.3

VOLTAGE REFERENCE

12.1 A/D Configuration and Operation

There are two options for the voltage reference to the

A/D converter: either VDD is used or an analog voltage

applied to VREF is used. The VCFG bit (ADCON0<6>)

controls the voltage reference selection. If VCFG is set,

then the voltage on the VREF pin is the reference;

otherwise, VDD is the reference.

There are four registers available to control the

functionality of the A/D module:

1. ANSEL0 (Register 12-1)

2. ANSEL1 (Register 12-2)

3. ADCON0 (Register 12-3)

4. ADCON1 (Register 12-4)

12.1.4

CONVERSION CLOCK

12.1.1

The

ANALOG PORT PINS

ANS<11:0> bits (ANSEL1<3:0>

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

and

ANSEL0<7:0>) and the TRISA<4,2:0>, TRISB<5:4>

and TRISC<7:6,3:0>> bits control the operation of the

A/D port pins. Set the corresponding TRISx bits to ‘1’ to

set the pin output driver to its high-impedance state.

Likewise, set the corresponding ANSx bit to disable the

digital input buffer.

• FOSC/2

• FOSC/4

• FOSC/8

• FOSC/16

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

• FOSC/32

• FOSC/64

• FRC (dedicated internal oscillator)

12.1.2

CHANNEL SELECTION

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of

1.6 μs. Table 12-1 shows a few TAD calculations for

selected frequencies.

There are fourteen analog channels on the PIC16F785.

The CHS<3:0> bits (ADCON0<5:2>) control which

channel is connected to the sample and hold circuit.

TABLE 12-1: TAD VS. DEVICE OPERATING FREQUENCIES

Device Frequency

A/D Clock Source (TAD)

Operation

ADCS2:ADCS0

20 MHz

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

5 MHz

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

4 MHz

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

1.25 MHz

1.6 μs

3.2 μs

2 TOSC

4 TOSC

000

100

001

101

010

110

x11

8 TOSC

6.4 μs

16 TOSC

32 TOSC

64 TOSC

A/D RC

3.2 μs

6.4 μs

12.8 μs⁽³⁾

2-6 μs^(1,4)

4.0 μs

12.8 μs⁽³⁾

25.6 μs⁽³⁾

51.2 μs⁽³⁾

2-6 μs^(1,4)

8.0 μs⁽³⁾

16.0 μs⁽³⁾

2-6 μs^(1,4)

3.2 μs

2-6 μs^(1,4)

Legend: Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be performed during Sleep.

DS41249B-page 80

Preliminary

PIC16F785

If the conversion must be aborted, the GO/DONE bit can

be cleared in software. The ADRESH:ADRESL registers

will not be updated with the partially complete A/D

conversion sample. Instead, the ADRESH:ADRESL

registers will retain the value of the previous conversion.

After an aborted conversion, a 2 TAD delay is required

before another acquisition can be initiated. Following the

delay, an input acquisition is automatically started on the

selected channel.

12.1.5

STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bit (ADCON0<1>). When the conversion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6>)

• Generates an interrupt (if enabled)

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

FIGURE 12-2:

A/D CONVERSION TAD CYCLES

TCY to TAD

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6

TAD

7

TAD

8

TAD9 TAD10 TAD11

b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Conversion Starts

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

Set GO bit

ADRESH and ADRESL registers are loaded,

GO bit is cleared,

ADIF bit is set,

Holding capacitor is connected to analog input

12.1.6

CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right justified. The ADFM bit (ADCON0<7>) controls

the output format. Figure 12-3 shows the output

formats.

FIGURE 12-3:

10-BIT A/D RESULT FORMAT

ADRESH (ADDRESS:1Eh)

ADRESL (ADDRESS:9Eh)

LSB

(ADFM = 0)

MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

Unimplemented: Read as ‘0’

(ADFM = 1)

MSB

LSB

bit 0

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

10-bit A/D Result

Preliminary

DS41249B-page 81

PIC16F785

REGISTER 12-1:

ANSEL0 – ANALOG SELECT REGISTER (ADDRESS: 91h)

R/W-1

ANS7

R/W-1

ANS6

R/W-1

ANS5

R/W-1

ANS4

R/W-1

ANS3

R/W-1

ANS2

R/W-1

ANS1

R/W-1

ANS0

bit 7

bit 0

bit 7-0

ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.

1= Analog input. Pin is assigned as analog input.⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak

pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be

set to Input mode in order to allow external control of the voltage on the pin. Port

reads of pins configured assigned as analog inputs will read as ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 12-2: ANSEL1 – ANALOG SELECT REGISTER (ADDRESS: 93h)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

ANS11

R/W-1

ANS9

R/W-1

ANS8

ANS10

bit 7

bit 0

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

ANS<11:8>: Analog Select bits

Analog select between analog or digital function on pins AN<11:8>, respectively.

1= Analog input. Pin is assigned as analog input.⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak

pull-ups, and interrupt-on-change, if available. The corresponding TRIS bit must be

set to Input mode in order to allow external control of the voltage on the pin. Port

reads of pins assigned as analog inputs will read as ‘0’.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 12-2: ANALOG SELECT CROSS REFERENCE

Mode

Reference

Analog

Select

ANS11 ANS10

ANS9

ANS8

ANS7

ANS6

ANS5

ANS4

ANS3

ANS2

ANS1

ANS0

Analog

Channel

AN11

RB5

AN10

RB4

AN9

RC7

AN8

RC6

AN7

RC3

AN6

RC2

AN5

RC1

AN4

RC0

AN3

RA4

AN2

RA2

AN1

RA1

AN0

RA0

I/O Pin

DS41249B-page 82

Preliminary

PIC16F785

REGISTER 12-3: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh)

R/W-0

ADFM

R/W-0

VCFG

R/W-0

CHS3

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0 GO/DONE ADON

bit 0

R/W-0

bit 7

ADFM: A/D Result Formed Select bit

1= Right justified

0= Left justified

bit 6

VCFG: Voltage Reference bit

1= VREF pin

0= VDD

bit 5-2

CHS<3:0>: Analog Channel Select bits

0000= Channel 00 (AN0)

0001= Channel 01 (AN1)

0010= Channel 02 (AN2)

0011= Channel 03 (AN3)

0100= Channel 04 (AN4)

0101= Channel 05 (AN5)

0110= Channel 06 (AN6)

0111= Channel 07 (AN7)

1000= Channel 08 (AN8)

1001= Channel 09 (AN9)

1010= Channel 10 (AN10)

1011= Channel 11 (AN11)

1100= CVREF

1101= VR

1110= Reserved. Do not use.

1111= Reserved. Do not use.

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: A/D Enable bit

1= A/D converter module is enabled

0= A/D converter is shut-off and consumes no operating current

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 83

PIC16F785

REGISTER 12-4: ADCON1 – A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

ADCS2

ADCS1

ADCS0

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100= FOSC/4

101= FOSC/16

110= FOSC/64

bit 3-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 84

Preliminary

PIC16F785

12.1.7

CONFIGURING THE A/D

EXAMPLE 12-1:

A/D CONVERSION

;This code block configures the A/D

;for polling, Vdd reference, R/C clock

;and RA0 input.

;

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

;Conversion start and wait for complete

To determine sample time, see Tables 18-15 and 18-16.

After this sample time has elapsed, the A/D conversion

can be started.

;polling code included.

;

BCF

BSF

STATUS,RP1 ;Bank 1

STATUS,RP0

;

These steps should be followed for an A/D conversion:

MOVLW B’01110000’ ;A/D RC clock

MOVWF ADCON1

1. Configure the A/D module:

BSF

BCF

TRISA,0

ANSEL0,0

STATUS,RP0 ;Bank 0

;Set RA0 to input

;Set RA0 to analog

• Configure analog/digital I/O (ANSx)

• Select A/D conversion clock (ADCON1<6:4>)

• Configure voltage reference (ADCON0<6>)

• Select A/D input channel (ADCON0<5:2>)

• Select result format (ADCON0<7>)

• Turn on A/D module (ADCON0<0>)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit (PIR1<6>)

MOVLW B’10000001’ ;Right, Vdd Vref, AN0

MOVWF ADCON0

CALL

BSF

SampleTime ;Wait min sample time

ADCON0,GO

;Start conversion

;Is conversion done?

;No, test again

BTFSC ADCON0,GO

GOTO

MOVF

$-1

ADRESH,W

;Read upper 2 bits

MOVWF RESULTHI

• Set ADIE bit (PIE1<6>)

BSF

STATUS,RP0 ;Bank 1

MOVF

BCF

MOVWF RESULTLO

ADRESL,W

STATUS,RP0 ;Bank 0

;Read lower 8 bits

• Set PEIE and GIE bits (INTCON<7:6>)

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(with interrupts disabled); OR

• Waiting for the A/D interrupt

6. Read A/D Result register pair

(ADRESH:ADRESL), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

Preliminary

DS41249B-page 85

PIC16F785

be decreased. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

12.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 12-4. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD), see Figure 12-4. The maximum recom-

mended impedance for analog sources is 10 kΩ. As

the impedance is decreased, the acquisition time may

To calculate the minimum acquisition time, Equation 12-1

may be used. This equation assumes that 1/2 LSb error is

used (1024 steps for the A/D). The 1/2 LSb error is the

maximum error allowed for the A/D to meet its specified

resolution.

To calculate the minimum acquisition time, TACQ, see

the “PICmicro^®Mid-Range MCU Family Reference

Manual” (DS33023).

EQUATION 12-1: ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10kΩ 5.0V VDD

Assumptions:

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]

The value for TC can be approximated with the following equations:

1

2047

⎛

⎞

⎠

-----------

;[1] VCHOLD charged to within 1/2 lsb

VAPPLIED 1 –

= VCHOLD

⎝

–TC

---------

⎛

⎞

V^APPLIED1 – e ^RC= VCHOLD

;[2] VCHOLD charge response to VAPPLIED

⎜

⎝

⎟

⎠

–Tc

--------

⎛

⎞

1

2047

VAPPLIED 1 – e ^RC= V^APPLIED1 –

⎛

⎞

;combining [1] and [2]

-----------

⎜

⎝

⎟

⎠

⎝

⎠

Solving for TC:

TC = –CHOLD(RIC + RSS + RS) ln(1/2047)

= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885)

= 1.37µs

Therefore:

TACQ = 2µS + 1.37µS + [(50°C- 25°C)(0.05µS/°C)]

= 4.67µS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

DS41249B-page 86

Preliminary

PIC16F785

FIGURE 12-4:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

RS

CHOLD

= DAC capacitance

= 10 pF

CPIN

5 pF

VA

ILEAKAGE

± 500 nA

VT = 0.6V

VSS

6V

5V

RSS

VDD 4V

3V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

5 6 7 8 9 10 11

Sampling Switch

(kΩ)

Preliminary

DS41249B-page 87

PIC16F785

When the A/D clock source is something other than

RC, a SLEEPinstruction causes the present conversion

to be aborted and the A/D module is turned off. The

ADON bit remains set.

12.3 A/D Operation During Sleep

The A/D Converter module can operate during Sleep.

This requires the A/D clock source to be set to the FRC

option. When the RC clock source is selected, the A/D

waits one instruction before starting the conversion.

This allows the SLEEPinstruction to be executed, thus

eliminating much of the switching noise from the

conversion. When the conversion is complete, the

GO/DONE bit is cleared and the result is loaded into

the ADRESH:ADRESL registers. If the A/D interrupt is

enabled (ADIE and PEIE bits set), the device awakens

from Sleep. If the GIE bit (INTCON<7>) is set, the

program counter is set to the interrupt vector (0004h).

If GIE is clear, the next instruction is executed. If the

A/D interrupt is not enabled, the A/D module is turned

off, although the ADON bit remains set.

FIGURE 12-5:

A/D TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

1 LSB ideal

Full-Scale

Transition

004h

003h

002h

001h

000h

Analog Input Voltage

1 LSB ideal

VREF

Zero-Scale

Transition

0V

DS41249B-page 88

Preliminary

PIC16F785

The appropriate analog input channel must be selected

and the minimum acquisition done before the “special

12.4 Effects of Reset

A device Reset forces all registers to their Reset state.

Thus, the A/D module is turned off and any pending

conversion is aborted. The ADRESH:ADRESL

registers are unchanged.

event trigger” sets the GO/DONE bit (starts

conversion).

a

If the A/D module is not enabled (ADON is cleared), then

the “special event trigger” will be ignored by the A/D

module, but will still reset the Timer1 counter. See

Section 8.0 “Capture/Compare/PWM (CCP) Module”

for more information.

12.5 Use of the CCP Trigger

An A/D conversion can be started by the “special event

trigger” of the CCP module. This requires that the

CCP1M3:CCP1M0

bits

(CCP1CON<3:0>)

be

programmed as ‘1011’ and that the A/D module is

enabled (ADON bit is set). When the trigger occurs, the

GO/DONE bit will be set, starting the A/D conversion

and the Timer1 counter will be reset to zero. Timer1 is

reset to automatically repeat the A/D acquisition period

with minimal software overhead (moving the

ADRESH:ADRESL to the desired location).

TABLE 12-3: SUMMARY OF A/D REGISTERS

Value on

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

05h,105h PORTA

06h,106h PORTB

07h,107h PORTC

—

RA5

RB5

RC5

T0IE

RA4

RB4

RC4

INTE

RA3

—

RA2

—

RA1

—

RA0

—

--xx xxxx

xxxx ----

xxxx xxxx

0000 0000

--uu uuuu

uuuu ----

uuuu uuuu

0000 0000

RB7

RC7

GIE

RB6

RC6

PEIE

RC3

RAIE

RC2

T0IF

RC1

INTF

RC0

RAIF

0Bh,8Bh, INTCON

10Bh,18Bh

0Ch

1Eh

1Fh

PIR1

EEIF

ADIF

CCP1IF

C2IF

C1IF

OSFIF

TMR2IF

TMR1IF

0000 0000

xxxx xxxx

0000 0000

--11 1111

1111 ----

1111 1111

0000 0000

1111 1111

---- 1111

xxxx xxxx

-000 ----

0000 0000

uuuu uuuu

0000 0000

--11 1111

1111 ----

1111 1111

0000 0000

1111 1111

---- 1111

uuuu uuuu

-000 ----

ADRESH Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result

ADCON0

ADFM

—

VCFG

—

CHS3

TRISA5

TRISB5

TRISC5

CCP1IE

ANS5

CHS2

TRISA4

TRISB4

TRISC4

C2IE

CHS1

TRISA3

—

CHS0

TRISA2

—

GO/DONE ADON

85h,185h TRISA

86h,186h TRISB

87h,187h TRISC

TRISA1

—

TRISA0

—

TRISB7

TRISC7

EEIE

ANS7

—

TRISB6

TRISC6

ADIE

ANS6

—

TRISC3

C1IE

TRISC2

OSFIE

ANS2

ANS10

TRISC1

TMR2IE

ANS1

ANS9

TRISC0

TMR1IE

ANS0

ANS8

8Ch

PIE1

91h

ANSEL0

ANSEL1

ANS4

—

ANS3

ANS11

93h

—

9Eh

ADRESL Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result

ADCON1 ADCS2 ADCS1 ADCS0

9Fh

—

Legend:

x= unknown, u= unchanged, – = unimplemented read as ‘0’. Shaded cells are not used for A/D module.

Preliminary

DS41249B-page 89

PIC16F785

NOTES:

DS41249B-page 90

Preliminary

PIC16F785

EQUATION 13-2: PHASE RESOLUTION

13.0 TWO-PHASE PWM

The two-phase PWM (Pulse Width Modulator) is a

stand-alone peripheral that supports:

360

(PER + 1)

Phase_DEG= -------------------------

• Single or dual-phase PWM

• Single complementary output PWM with overlap/

delay

13.3 PWM Duty Cycle

• Sync input/output to cascade devices for

additional phases

Each PWM output is driven inactive, terminating the

drive period, by asynchronous feedback through the

internal comparators. The duty cycle resolution is in

effect infinitely adjustable. Either or both comparators

can be used to reset the PWM by setting the

corresponding comparator enable bit (CxEN, see

Register 13-3). Duty cycles of 100% can be obtained

by suppressing the feedback which would otherwise

terminate the pulse.

Setting either, or both, of the PH1EN or PH2EN bits of

the PWMCON0 register will activate the PWM module

(see Register 13-1). If PH1 is used then TRISC<1>

must be cleared to configure the pin as an output. The

same is true for TRISC<4> when using PH2. Both

PH1EN and PH2EN must be set when using

Complementary mode.

The comparator outputs can be “held off”, or blanked,

by enabling the corresponding BLANK bit (BLANKx,

see Register 13-1) for each phase. The blank bit

disables the comparator outputs for 1/2 of a system

clock (FOSC), thus ensuring at least Tosc/2 active time

for the PWM output. Blanking avoids early termination

of the PWM output which may result due to switching

transients at the beginning of the cycle.

13.1 PWM Period

The PWM period is derived from the main clock (FOSC),

the PWM prescaler and the period counter (see

Figure 13-1). The prescale bits (PWMP<1:0>, see

Register 13-2) determine the value of the clock divider

which divides the system clock (FOSC) to the pwm_clk.

This pwm_clk is used to drive the PWM counter. In

Master mode, the PWM counter is reset when the

count reaches the period count (PER<4:0>, see

Register 13-2), which determines the frequency of the

PWM. The relationship between the PWM frequency,

prescale and period count is shown in Equation 13-1.

13.4 Master/Slave Operation

Multiple chips can operate together to achieve

additional phases by operating one as the master and

the others as slaves. When the PWM is configured as

a master, the RB7/SYNC pin is an output and

generates a high output for one pwm_clk period at the

end of each PWM period (see Figure 13-4).

EQUATION 13-1: PWM FREQUENCY

Fosc

PWM_FREQ= ---------------------------------------------------

When the PWM is configured as a slave, the RB7/

SYNC pin is an input. The high input from a master in

this configuration resets the PWM period counter which

synchronizes the slave unit at the end of each PWM

period. Proper operation of a slave device requires a

common external FOSC clock source to drive the

master and slave. The PWM prescale value of the

slave device must also be identical to that of the

master. As mentioned previously, the slave period

count value must be greater than or equal to that of the

master.

(2^PWMP⋅ (PER + 1))

The maximum PWM frequency is FOSC/2, since the

period count must be greater than zero.

In Slave mode, the period counter is reset by the SYNC

input, which is the master device period counter reset.

For proper operation, the slave period count should be

equal to or greater than that of the master.

13.2 PWM Phase

The PWM Counter will be reset and held at zero when

both PH1EN and PH2EN (PWMCON0<1:0>) are false.

If the PWM is configured as a slave, the PWM Counter

will remain reset at zero until the first SYNC input is

received.

Each enabled phase output is driven active when the

phase counter matches the corresponding PWM phase

count (PH<4:0>, see Register 13-3 and Register 13-4).

The phase output remains true until terminated by a

feedback signal from either of the comparators or the

auto-shutdown activates.

Phase granularity is a function of the period count

value. For example, if PER<4:0> = 3, each output can

be shifted in 90° steps (see Equation 13-2).

Preliminary

DS41249B-page 91

PIC16F785

The PWMASE bit (see Register 13-2) is set by hard-

ware when a shutdown event occurs. If automatic

restarts are not enabled (PRSEN = 0, see

Register 13-1), PWM operation will not resume until the

PWMASE bit is cleared by firmware after the shutdown

condition clears. The PWMASE bit can not be cleared

as long as the shutdown condition exists. If automatic

restarts are not enabled, the auto-shutdown mode can

be forced by writing a ‘1’ to the PWMASE bit.

13.5 Active PWM Output Level

The PWM output signal can be made active high or low

by setting or resetting the corresponding POL bit (see

Register 13-3 and Register 13-4). When POL is ‘1’ the

active output state is VOL. When POL is ‘0’ the active

output state is VOH.

13.6 Auto-Shutdown and Auto-Restart

If automatic restarts are enabled (PRSEN = 1), the

PWMASE bit is automatically cleared and PWM opera-

tion resumes when the auto-shutdown event clears

(VIH on the RA2/AN2/T0CKI/INT/C1OUT pin).

When the PWM is enabled, the PWM outputs may be

configured for auto-shutdown by setting the PASEN bit

(see Register 13-1). VIL on the RA2/AN2/T0CKI/INT/

C1OUT pin will cause a shutdown event if auto-shutdown

is enabled. An auto-shutdown event immediately places

the PWM outputs in the inactive state (see Section 13.5

“Active PWM Output Level”) and the PWM phase and

period counters are reset and held to zero.

FIGURE 13-1:

TWO-PHASE PWM SIMPLIFIED BLOCK DIAGRAM

PH1EN

PH2EN

PWMASE

PASEN

PWMP<1:0>

MASTER

S

SHUTDOWN

÷1,2,4,8

FOSC

pwm_clk

Phase

Counter

0

Res

Prescale

1

M

RB7/SYNC

5

PER<4:0>

pwm_count

5

PWMPH1<POL>

5

S

PWMPH1<4:0>

BLANK1

pha1

Q

SHUTDOWN

PH1EN

(1)

R

RC1/AN5/C12IN1-/PH1

PWMPH1<C1EN>

PWMPH1<C2EN>

C1OUT

C2OUT

PWMPH2<POL>

5

PWMPH2<4:0>

SHUTDOWN

PH2EN

S

R

BLANK2

pha2

Q

(1)

RC4/C2OUT/PH2

PWMPH2<C1EN>

PWMPH2<C2EN>

Note 1: Reset dominant.

DS41249B-page 92

Preliminary

PIC16F785

REGISTER 13-1: PWMCON0 – PWM CONTROL REGISTER 0 (ADDRESS: 111h)

R/W-0

PRSEN

PASEN

BLANK2 BLANK1

SYNC1

SYNC0

PH2EN

PH1EN

bit 7

bit 0

bit 7

PRSEN: PWM Restart Enable bit

1= Upon auto-shutdown, the PWMASE shutdown bit clears automatically once the shutdown

condition goes away. The PWM restarts automatically.

0= Upon auto-shutdown, the PWMASE must be cleared in firmware to restart the PWM.

bit 6

PASEN: PWM Auto-Shutdown Enable bit

0= PWM auto-shutdown is disabled

1= VIL on INT pin will cause auto-shutdown event

bit 5

BLANK2: PH2 Blanking bit⁽¹⁾

1= The PH2 pin is active for a minimum of 1/2 of an FOSC clock period after it is set

0= The PH2 pin is reset as soon as the comparator trigger is active

bit 4

BLANK1: PH1 Blanking bit⁽¹⁾

1= The PH1 pin is active for a minimum of 1/2 of an FOSC clock period after it is set

0= The PH1 pin is reset as soon as the comparator trigger is active

bit 3-2

SYNC<1:0>: SYNC Pin Function bits

0X= SYNC pin not used for PWM. PWM acts as its own master. RB7/SYNC pin is available

for general purpose I/O.

10= SYNC pin acts as system slave, receiving the PWM counter reset pulse

11= SYNC pin acts as system master, driving the PWM counter reset pulse

bit 1

bit 0

PH2EN: PH2 Pin Enabled bit

1= The PH2 pin is driven by the PWM signal

0= The PH2 pin is not used for PWM functions

PH1EN: PH1 Pin Enabled bit

1= The PH1 pin is driven by the PWM signal

0= The PH1 pin is not used for PWM functions

Note 1: Blanking is disabled when operating in complementary mode. See COMOD<1:0>

bits in the PWMCON1 register (Register 13-5) for more information.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 93

PIC16F785

REGISTER 13-2: PWMCLK – PWM CLOCK CONTROL REGISTER (ADDRESS: 112h)

R/W-0

PER4

R/W-0

PER3

R/W-0

PER2

R/W-0

PER1

R/W-0

PER0

PWMASE PWMP1 PWMP0

bit 7

bit 0

bit 7

PWMASE: PWM Auto-Shutdown event Status bit

0= PWM outputs are operating

1= A shutdown event has occured. PWM outputs are inactive.

bit 6-5

PWMP<1:0>: PWM Clock Prescaler bits

00= pwm_clk = FOSC ÷ 1

01= pwm_clk = FOSC ÷ 2

10= pwm_clk = FOSC ÷ 4

11= pwm_clk = FOSC ÷ 8

bit 4-0

PER<4:0>: PWM Period bits

00000= Not used. (Period = 1/pwm_clk)

00001= Period = 2/pwm_clk2

0....= . . .

01111= Period = 16/pwm_clk

10000= Period = 17/pwm_clk

1....= . . .

11110= Period = 31/pwm_clk

11111= Period = 32/pwm_clk

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 94

Preliminary

PIC16F785

REGISTER 13-3: PWMPH1 – PWM PHASE 1 CONTROL REGISTER (ADDRESS: 113h)

R/W-0

POL

R/W-0

C2EN

R/W-0

C1EN

R/W-0

PH4

R/W-0

PH3

R/W-0

PH2

R/W-0

PH1

R/W-0

PH0

bit 7

bit 0

bit 7

bit 6

POL: PH1 Output Polarity bit

1= PH1 Pin is active low

0= PH1 Pin is active high

C2EN: Comparator 2 Enable bit

When COMOD<1:0> = 00⁽¹⁾

1= PH1 is reset when C2OUT goes high

0= PH1 ignores Comparator 2

When COMOD<1:0> = X1⁽¹⁾

1= Complementary drive terminates when C2OUT goes high

0= Comparator 2 is ignored

When COMOD<1:0> = 10⁽¹⁾

C2EN has no effect

bit 5

C1EN: Comparator 1 Enable bit

When COMOD<1:0> = 00⁽¹⁾

1= PH1 is reset when C1OUT goes high

0= PH1 ignores Comparator 1

When COMOD<1:0> = X1⁽¹⁾

1= Complementary drive terminates when C1OUT goes high

0= Comparator 1 is ignored

When COMOD<1:0> = 10⁽¹⁾

C1EN has no effect

bit 4-0

PH<4:0>: PWM Phase bits

When COMOD<1:0> = 00⁽¹⁾

00000= PH1 starts 1 pwm_clk period after falling edge of SYNC pulse. All other PH1

delays are expressed relative to this time.

00001= PH1 is delayed by 1 pwm_clk pulse

.....= . . .

11111= PH1 is delayed by 31 pwm_clk pulses

When COMOD<1:0> = X1or 1X⁽¹⁾

00000= Complementary drive starts 1 pwm_clk period after falling edge of SYNC pulse.

All other delays are expressed relative to this time.

00001= Complementary drive start is delayed by 1 pwm_clk pulse

.....= . . .

11111= Complementary drive start is delayed by 31 pwm_clk pulses

Note 1: See PWMCON1 register (Register 13-5).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 95

PIC16F785

REGISTER 13-4: PWMPH2 – PWM PHASE 2 CONTROL REGISTER (ADDRESS: 114h)

R/W-0

POL

R/W-0

C2EN

R/W-0

C1EN

R/W-0

PH4

R/W-0

PH3

R/W-0

PH2

R/W-0

PH1

R/W-0

PH0

bit 7

bit 0

bit 7

bit 6

POL: PH2 Output Polarity bit

1= PH2 Pin is active low

0= PH2 Pin is active high

C2EN: Comparator 2 Enable bit

When COMOD<1:0> = 00⁽¹⁾

1= PH2 is reset when C2OUT goes high

0= PH2 ignores Comparator 2

When COMOD<1:0> = 1Xor X1⁽¹⁾

C2EN has no effect

bit 5

C1EN: Comparator 1 Enable bit

When COMOD<1:0> = 00⁽¹⁾

1= PH2 is reset when C1OUT goes high

0= PH2 ignores Comparator 1

When COMOD<1:0> = 1Xor X1⁽¹⁾

C1EN has no effect

bit 4-0

PH<4:0>: PWM Phase bits

When COMOD<1:0> = 00⁽¹⁾

00000= PH2 starts 1 pwm_clk period after falling edge of SYNC pulse. All other PH2

delays are expressed relative to this time.

00001= PH2 is delayed by 1 pwm_clk pulse

.....= . . .

11111= PH2 is delayed by 31 pwm_clk pulses

When COMOD<1:0> = 1X⁽¹⁾

00000= Complementary drive terminates 1 pwm_clk period after falling edge of SYNC

pulse. All other PH2 delays are expressed relative to this time.

00001= Complementary drive termination is delayed by 1 pwm_clk pulse

.....= . . .

11111= Complementary drive termination is delayed by 31 pwm_clk pulses

When COMOD<1:0> = 01⁽¹⁾

PH<4:0> has no effect.

Note 1: See PWMCON1 register (Register 13-5).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 96

Preliminary

PIC16F785

FIGURE 13-2:

TWO-PHASE PWM AUTO-SHUTDOWN AND SYNC TIMING

FOSC

PWMP<1:0> = 0X01, PER<4:0> = 0X03

pwm_clk

2

pwm_count

0

1

0

1

2

3

0

1

2

3

0

SYNC

Phase1 setup: PH<4:0> = 0x00, C1EN = 1, BLANK1 = 0

pha1

SHUTDOWN

pwm_clk

0

1

2

0

1

2

3

0

1

2

3

0

pwm_count

Phase2 setup: PH<4:0> = 0x02, C2EN = 1, BLANK2 = 1

pha2

FIGURE 13-3:

TWO-PHASE PWM START-UP TIMING

FOSC

PWMP<1:0> = 0X01, PER<4:0> = 0X03

pwm_clk

pwm_count

1

2

3

0

1

2

0

SYNC

PHnEN

pwm_clk

0

1

2

3

0

1

2

3

pwm_count

PHnEN

Preliminary

DS41249B-page 97

PIC16F785

Resistor divider R5 and R6 scale the output voltage,

which is inverted and amplified by Op Amp 1, relative

to the reference voltage present at the non-inverting pin

of the op amp. R3, C5 and C2 form the inverting

stabilization gain feedback of the amplifier. The VR

reference supplies a stable reference to the non-

inverting input of the op amp, which is tweaked by the

voltage source created by a secondary time based

PWM output of the CCP and R1 and C1.

13.7 Example Single Phase Application

Figure 13-4 shows an example of a single phase buck

voltage regulator application. The PWM output drives

Q1 with pulses to alternately charge and discharge L1.

C4 holds the charge from L1 during the inactive cycle

of the drive period. R4 and C3 form a ramp generator.

At the beginning of the PWM period, the PWM output

goes high causing the voltage on C3 to rise concurrently

with the current in L1. When the voltage across C3

reaches the threshold level present at the positive input

of Comparator 1, the comparator output changes and

terminates the drive output from the PWM to Q1. When

Q1 is not driven, the current path to L1 through Q1 is

interrupted, but since the current in L1 cannot stop

instantly, the current continues to flow through D2 as L1

discharges into C4. D1 quickly discharges C3 in

preparation of the next ramp cycle.

Output regulation occurs by the following principle: If the

regulator output voltage is too low, then the voltage to the

non-inverting input of Comparator 1 will rise, resulting in

a higher threshold voltage and, consequently, longer

PWM drive pulses into Q1. If the output voltage is too

high, then the voltage to the non-inverting input of

Comparator 1 will fall, resulting in shorter PWM drive

pulses into Q1.

FIGURE 13-4:

EXAMPLE SINGLE PHASE APPLICATION

CCP

VR

PIC16F785

R1

R2

C1

OPA1

VUNREG

FOSC

FET

Driver

R3

Q1

PH1

TWO- Phase

PWM

C2

C5

L1

C4

C1

D2

R4

D1

R5

R6

C3

DS41249B-page 98

Preliminary

PIC16F785

When COMOD<1:0> = 11, the duty cycle is controlled

by the phase counter or feedback through comparator

C1 or C2. For example, in this mode, the maximum

duty cycle is determined by the values of

PWMPH1<4:0> (duty cycle start) and PWMPH2<4:0>

(duty cycle end). The duty cycle can be terminated ear-

lier than the maximum by feedback through comparator

C1 or C2.

13.8 PWM Configuration

When configuring the Two-Phase PWM, care must be

taken to avoid active output levels from the PH1 and

PH2 pins before the PWM is fully configured. The

following sequence is suggested before the TRISC

register or any of the Two-Phase PWM control registers

are first configured:

• Output inactive (OFF) levels to the PORTC RC1/

AN5/C12IN1-/PH1 and RC4/C2OUT/PH2 pins.

13.9.1

DEAD BAND CONTROL

• Clear TRISC bits 1 and 4 to configure the PH1

and PH2 pins as outputs.

The Complementary Output mode facilitates driving

series connected MOSFET drivers by providing dead

band drive timing between each phase output (see

Figure 13-6). Dead band times are selectable by the

CMDLY<4:0> bits of the PWMCON1 register. Delays

from 0 to 155 nanoseconds (typical) with a resolution of

5 nanoseconds (typical) are available.

• Configure the PWMCLK, PWMPH1, PWMPH2,

and PWMCON1 registers.

• Configure the PWMCON0 register.

13.9 Complementary Output Mode

13.9.2

OVERLAP CONTROL

The Two-Phase PWM module may be configured to

operate in a Complementary Output mode where PH1

and PH2 are always 180 degrees out-of-phase (see

Figure 13-5). Three complementary modes are

available and are selected by the COMOD<1:0> bits in

the PWMCON1 register (see Register 13-5). The differ-

ence between the modes is the method by which the

PH1 and PH2 outputs switch from the active to the

inactive state during the PWM period.

Overlap timing can be accomplished by configuring the

Complementary mode for the desired output polarity

and overlap time (as dead time) then swapping the

output connections and inverting the outputs. For

example, to configure a complementary drive for 55 ns

of overlap and an active high drive output on PH1 and

an active low drive output on PH2, set the PWM control

registers as follows:

In Complementary mode, there are three methods by

which the duty cycle can be controlled. These modes

are selected with the COMOD<1:0> bits (see

Register 13-5). In each of these modes, the duty cycle

is started when the pwm_count = PWMPH1<4:0> and

terminates on one of the following:

• Connect PH1 driver to PH2 output

• Connect PH2 driver to PH1 output

• Initialize PORTC<1> to 1(PH2 driver off)

• Initialize PORTC<4> to 0(PH1 driver off)

• Set TRISC<1,4> to 0for output

• Set PWMPH1<POL> to 1(Inverted PH1)

• Set PWMPH2<POL> to 1(Non-Inverted PH2)

• Feedback through C1 or C2.

• When the pwm_count equals PWMPH1<4:0>.

• Combined feedback and pwm_count match.

• Set PWMCON1 for 55 ns delay and desired termi-

nation (comparator, count, or both)

When COMOD<1:0> = 01, the duty cycle is controlled

only by feedback through comparator C1 or C2. In this

mode, the active drive cycle starts when pwm_count

equals PWMPH1<4:0> and terminates when compara-

tor C1’s output goes high (if enabled by

PWMPH1<5> = 1) or when comparator C2 output goes

high (if enabled by PWMPH1<6> = 1).

• Set PWMCON0 desired SYNC and auto-shutdown

configuration and to enable PH1 and PH2

13.9.3

SHUTDOWN IN COMPLEMENTARY

MODE

During shutdown the PH1 and PH2 complementary

outputs are forced to their inactive states (see

Figure 13-5). When shutdown ceases the PWM

outputs revert to their start-up states for the first cycle

which is PH1 inactive (output undriven) and PH2 active

(output driven).

When COMOD<1:0> = 10, the duty cycle is controlled

only by the PWM Phase counter. In this mode, the

active drive cycle starts when the pwm_count equals

PWMPH1<4:0> and terminates when the pwm_count

equals PWMPH2<4:0>. For example, free running

50% duty cycle can be accomplished by setting

COMOD<1:0> = 10 and choosing appropriate values

for PWMPH1<4:0> and PWMPH2<4:0>.

Preliminary

DS41249B-page 99

PIC16F785

REGISTER 13-5: PWMCON1 – PWM CONTROL REGISTER 1 (ADDRESS: 110h)

U-0

—

R/W-0

CMDLY0

bit 0

COMOD1

COMOD0

CMDLY4

CMDLY3

CMDLY2

CMDLY1

bit 7

Unimplemented: Read as ‘0’

COMOD<1:0>: Complementary Mode Select bits

(1)

bit 6-5

00= Normal two-phase operation. Complementary mode is disabled.

01= Complementary operation. Duty cycle is terminated by C1OUT or C2OUT.

10= Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count.

11= Complementary operation. Duty cycle is terminated by PWMPH2<4:0> = pwm_count or C1OUT or

C2OUT.

bit 4-0

CMDLY<4:0>: Complementary Drive Dead Time bits (typical)

00000= Delay = 0

00001= Delay = 5 ns

00010= Delay = 10 ns

.....= . . .

11111= Delay = 155 ns

Note 1: PWMCON0<1:0> must be set to ‘11’ for Complementary mode operation.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

FIGURE 13-5:

COMPLEMENTARY OUTPUT PWM BLOCK DIAGRAM

PH1EN

pwm_reset

PH2EN

PS<1:0>

PWMASE

Shutdown

MASTER

S

PASEN

FOSC

pwm_clk

0

Phase Res

Prescale

Counter

1

RB7/SYNC

M

5

PER<4:0>

5

pwm_count

PWMPH1<POL>

pha1

5

Delay

5

S

PWMPH1<4:0>

Q

RC1/AN5/C12IN1-/PH1

R⁽¹⁾

CMDLY<4:0>

5

PWMPH2<POL>

pha2

11

10

01

PWMPH2<4:0>

delay

S

PWMPH1<C1EN>

C1OUT

Q

pwm_reset

PWMPH1<C2EN>

C2OUT

RC4/C2OUT/PH2

R⁽¹⁾

Shutdown

COMOD<1:0>

Note 1:

Reset dominant.

DS41249B-page 100

Preliminary

PIC16F785

FIGURE 13-6:

COMPLEMENTARY OUTPUT PWM TIMING

FOSC

PWMP<1:0> = 0X01, PER<4:0> = 0X03

pwm_clk

3

1

0

1

2

3

0

1

2

3

0

1

pwm_count

SYNC

C1OUT

Phase 1 setup: PH<4:0> = 0x00, C1EN = 1, BLANKx = X, COMOD<1:0> = 0x01

pha1

pha2

Delay

Shutdown

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH PWM

Value on:

POR, BOR other Resets

Value on all

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

98h

REFCON

VRCON

—

BGST

VRR

VRBB

—

VREN

VR3

VROE

VR2

CVROE

VR1

—

--00 000- --00 000-

000- 0000 000- 0000

0000 0000 0000 0000

99h

C1VREN C2VREN

VR0

119h

11Ah

110h

111h

112h

113h

114h

CM1CON0

CM2CON0

PWMCON1

PWMCON0

PWMCLK

PWMPH1

PWMPH2

C1ON

C2ON

—

C1OUT

C2OUT

C1OE

C2OE

C1POL

C2POL

C1SP

C2SP

C1R

C2R

C1CH1

C2CH1

C1CH0

C2CH0

COMOD1 COMOD0 CMDLY4 CMDLY3 CMDLY2 CMDLY1 CMDLY0 -000 0000 -000 0000

PRSEN

PASEN

BLANK2 BLANK1

SYNC1

PER3

PH3

SYNC0

PER2

PH2

PH2EN

PER1

PH1

PH1EN

PER0

PH0

0000 0000 0000 0000

PWMASE PWMP1 PWMP0

PER4

PH4

POL

C2EN

C1EN

PH4

PH3

PH2

PH1

PH0

Legend: x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition. Shaded cells are not used by data PWM

module.

Preliminary

DS41249B-page 101

PIC16F785

NOTES:

DS41249B-page 102

Preliminary

PIC16F785

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write). The EEPROM

data memory is rated for high erase/write cycles. The

write time is controlled by an on-chip timer. The write

time will vary with voltage and temperature, as well as

from chip-to-chip. Please refer to AC Specifications in

Section 18.0 “Electrical Specifications” for exact

limits.

14.0 DATA EEPROM MEMORY

The EEPROM data memory is readable and writable

during normal operation (full VDD range). This memory

is not directly mapped in the register file space.

Instead, it is indirectly addressed through the Special

Function Registers. There are four SFRs used to read

and write this memory:

• EECON1

• EECON2 (not a physically implemented register)

When the data memory is code-protected, the CPU

may continue to read and write the data EEPROM

memory. The device programmer can no longer access

the data EEPROM data and will read zeroes.

• EEDAT

• EEADR

EEDAT holds the 8-bit data for read/write, and EEADR

holds the address of the EEPROM location being

accessed. The PIC16F785 has 256 bytes of data

EEPROM with an address range from 0h to FFh.

Additional information on the data EEPROM is

available in the “PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023).

REGISTER 14-1: EEDAT – EEPROM DATA REGISTER (ADDRESS: 9Ah)

R/W-0

EEDAT7 EEDAT6 EEDAT5 EEDAT4

bit 7

EEDAT3

EEDAT2 EEDAT1 EEDAT0

bit 0

bit 7-0

EEDATn: Byte Value to Write to or Read From Data EEPROM bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 14-2:

EEADR – EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)

R/W-0

EEADR7 EEADR6 EEADR5 EEADR4

bit 7

EEADR3

EEADR2 EEADR1 EEADR0

bit 0

bit 7-0

EEADR: Specifies one of 256 locations for EEPROM Read/Write Operation bits

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41249B-page 103

PIC16F785

The WREN bit, when set, will allow a write operation. On

power-up, the WREN bit is clear. The WRERR bit is set

when a write operation is interrupted by a MCLR Reset,

or a WDT Time-out Reset during normal operation. In

these situations, following Reset, the user can check the

WRERR bit, clear it and rewrite the location. The EEDAT

14.1 EECON1 and EECON2 Registers

EECON1 is the control register with four low-order bits

physically implemented. The upper four bits are non-

implemented and read as ‘0’s.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

and EEADR registers are cleared by

a Reset.

Therefore, the EEDAT and EEADR registers will need to

be re-initialized.

Interrupt flag EEIF bit (PIR1<7>) is set when write is

complete. This bit must be cleared in software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

Note:

The EECON1, EEDAT and EEADR

registers should not be modified during a

data EEPROM write (WR bit = 1).

REGISTER 14-3: EECON1 – EEPROM CONTROL REGISTER (ADDRESS: 9Ch)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

WRERR

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

WRERR: EEPROM Error Flag bit

1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR reset)

0= The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the data EEPROM

WR: Write Control bit

1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit

can only be set, not cleared, in software.)

0= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit

can only be set, not cleared, in software.)

0= Does not initiate an EEPROM read

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41249B-page 104

Preliminary

PIC16F785

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

14.2 Reading the EEPROM Data

Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>), as shown in Example 14-1. The

data is available, in the very next cycle, in the EEDAT

register. Therefore, it can be read in the next

instruction. EEDAT holds this value until another read,

or until it is written to by the user (during a write

operation).

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR1<7>) register must be cleared by software.

14.4 Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 14-3) to the

desired value to be written.

EXAMPLE 14-1:

DATA EEPROM READ

STATUS,RP0 ;Bank 1

STATUS,RP1

BSF

BCF

MOVLW

MOVWF

BSF

CONFIG_ADDR;

EEADR

EECON1,RD ;EE Read

EEDAT,W ;Move data to W

;Address to read

EXAMPLE 14-3:

WRITE VERIFY

BSF

BCF

MOVF

STATUS,RP0 ;Bank 1

STATUS,RP1

EEDAT,W

MOVF

;EEDAT not changed

; from previous write

14.3 Writing to the EEPROM Data

Memory

BSF

EECON1,RD ;YES, Read the

; value written

EEDAT,W

;Is data the same

WRITE_ERR ;No, handle error

;Yes, continue

XORWF

BTFSS

GOTO

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 14-2.

STATUS,Z

14.4.1

USING THE DATA EEPROM

EXAMPLE 14-2:

DATA EEPROM WRITE

The data EEPROM is

a high-endurance, byte

BSF

BCF

BSF

STATUS,RP0

STATUS,RP1

EECON1,WREN ;Enable write

;Bank 1

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). When variables in one section change

frequently, while variables in another section do not

change, it is possible to exceed the total number of

write cycles to the EEPROM (specification D124)

without exceeding the total number of write cycles to a

single byte (specifications D120 and D120A). If this is

the case, then an array refresh must be performed. For

this reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

BCF

INTCON,GIE

$-2

55h

EECON2

AAh

EECON2

EECON1,WR

INTCON,GIE

;Disable INTs

;See AN-576

;

;Unlock write

;

BTFSC

GOTO

MOVLW

MOVWF

MOVLW

MOVWF

BSF

;Start the write

;Enable INTs

BSF

The write will not initiate if the above sequence is not

followed exactly (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

14.5 Protect Against Spurious Write

There are conditions when the user may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been built in. On power-up, WREN is cleared. Also, the

Power-up

EEPROM write.

Timer

(64 ms

duration)

prevents

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating the EEPROM. The WREN bit is not cleared

by hardware.

The write initiate sequence and the WREN bit together

help prevent an accidental write during:

• brown-out

• power glitch

• software malfunction

Preliminary

DS41249B-page 105

PIC16F785

14.6 Data EEPROM Operation During

Code-Protect

Data memory can be code-protected by programming

the CPD bit in the Configuration Word (Register 15-1)

to ‘0’.

When the data memory is code-protected, the CPU is

able to read and write data to the data EEPROM. It is

recommended to code-protect the program memory

when code-protecting data memory. This prevents

anyone from programming zeroes over the existing

code (which will execute as NOPs) to reach an added

routine, programmed in unused program memory,

which outputs the contents of data memory.

Programming unused locations in program memory to

‘0’ will also help prevent data memory code protection

from becoming breached.

TABLE 14-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh,

INTCON

GIE

PEIE

T0IE

INTE

RAIE

T0IF

INTF

RAIF

0000 0000 0000 0000

10Bh,18Bh

0Ch

8Ch

9Ah

9Bh

9Ch

9Dh

PIR1

EEIF

EEIE

ADIF

ADIE

CCP1IF

CCP1IE

C2IF

C2IE

C1IF

C1IE

OSFIF

TMR2IF TMR1IF 0000 0000 0000 0000

PIE1

OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

EEDAT

EEADR

EECON1

EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000

EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000

—

WRERR WREN

WR

RD

---- x000 ---- q000

---- ---- ---- ----

EECON2 EEPROM Control register 2 (not a physical register)

Legend: x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition. Shaded cells are not used by

data EEPROM module.

DS41249B-page 106

Preliminary

PIC16F785

15.1 Configuration Bits

15.0 SPECIAL FEATURES OF THE

CPU

The configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 15-1.

These bits are mapped in program memory location

2007h.

The PIC16F785 has a host of features intended to

maximize system reliability, minimize cost through

elimination of external components, provide power

saving features and offer code protection.

These features are:

Note:

Address 2007h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/PS200

Memory Programming Specification”

(DS41237) for more information.

• Reset:

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• Oscillator selection

• Sleep

• Code protection

• ID Locations

• In-Circuit Serial Programming™ (ICSP™)

The PIC16F785 has two timers that offer necessary

delays on power-up. One is the Oscillator Start-up

Timer (OST), intended to keep the chip in Reset until

the crystal oscillator is stable. The other is the Power-

up Timer (PWRT), which provides a fixed delay of

64 ms (nominal) on power-up only, designed to keep

the part in Reset while the power supply stabilizes.

There is also circuitry to reset the device if a brown-out

occurs, which can use the Power-up Timer to provide

at least a 64 ms Reset. With these three functions on-

chip, most applications need no external Reset

circuitry.

The Sleep mode is designed to offer a very low-current

Power-down mode. The user can wake-up from Sleep

through:

• External Reset

• Watchdog Timer Wake-up

• An interrupt

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost, while the LP crystal option saves

power. A set of configuration bits are used to select

various options (see Register 15-1).

Preliminary

DS41249B-page 107

PIC16F785

REGISTER 15-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)

(5)

(1)

(2,3)

(2)

(4)

(5)

—

FCMEN

IESO BOREN1

BOREN0

CPD

CP

MCLRE

PWRTE WDTE

FOSC2 FOSC1 FOSC0

bit 0

bit 13

bit 13-12

bit 11

Unimplemented: Read as ‘1’

(5)

FCMEN: Fail-Safe Clock Monitor Enabled bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

bit 10

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled

0= Internal External Switchover mode is disabled

(1)

bit 9-8

BOREN<1:0>: Brown-out Reset Selection bits

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit (PCON<4>)

00= BOR disabled

(2,3)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

CPD: Data Code Protection bit

1= Data memory code protection is disabled

0= Data memory code protection is enabled

(2)

CP: Code Protection bit

1= Program memory code protection is disabled

0= Program memory code protection is enabled

(4)

MCLRE: RA3/MCLR pin function select bit

1= RA3/MCLR pin function is MCLR

0= RA3/MCLR pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

(5)

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)

FOSC<2:0>: Oscillator Selection bits

111= RC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN

110= RCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN

101= INTOSC oscillator: CLKOUT function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on

RA5/T1CKI/OSC1/CLKIN

100= INTOSCIO oscillator: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, I/O function on

RA5/T1CKI/OSC1/CLKIN

011= EC: I/O function on RA4/AN3/T1G/OSC2/CLKOUT pin, CLKIN on RA5/T1CKI/OSC1/CLKIN

010= HS oscillator: High-speed crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN

(5)

001= XT oscillator: Crystal/resonator on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN

(5)

000= LP oscillator: Low-power crystal on RA4/AN3/T1G/OSC2/CLKOUT and RA5/T1CKI/OSC1/CLKIN

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: Program memory bulk erase must be performed to turn off code protection.

3: The entire data EEPROM will be erased when the code protection is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

5: If the HS, XT, or LP oscillator fails In Fail-safe mode the Watchdog time-out can occur only once after

which it will be disabled until the oscillator is restored.

Legend:

R = Readable

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS41249B-page 108

Preliminary

PIC16F785

They are not affected by a WDT wake-up since this is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 15-2. These bits are

used in software to determine the nature of the Reset.

See Table 15-4 for a full description of Reset states of

all registers.

15.2 Reset

The PIC16F785 differentiates between various kinds of

Reset:

• Power-on Reset (POR)

• WDT Reset during normal operation

• WDT Reset during Sleep

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 15-1.

• MCLR Reset during normal operation

• MCLR Reset during Sleep

• Brown-out Reset (BOR)

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 18.0 “Electrical

Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

FIGURE 15-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

Sleep

WDT

Module

Time-out

Reset

Power-on Reset

VDD Rise

Detect

VDD

Brown-out⁽¹⁾

Reset

BOREN

SBOREN

S

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

R

Q

OSC1/

CLKI pin

PWRT

11-bit Ripple Counter

LFINTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word register (Register 15-1).

Preliminary

DS41249B-page 109

PIC16F785

15.2.1

POWER-ON RESET

15.2.3

POWER-UP TIMER (PWRT)

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. A minimum rise time for VDD is required. See

Section 18.0 “Electrical Specifications” for details. If

the BOR is enabled, the minimum rise time

specification does not apply. The BOR circuitry will

keep the device in Reset until VDD reaches VBOR (see

Section 15.2.4 “Brown-Out Reset (BOR)”)

The Power-up Timer provides a fixed 64 ms (nominal)

time out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 3.4 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A

configuration bit, PWRTE can disable (if ‘1’) or enable

(if ‘0’) the Power-up Timer. The Power-up Timer should

be enabled when Brown-out Reset is enabled,

although it is not required.

The POR circuit on this device has a POR re-arm

circuit. This circuit is designed to ensure a re-arm of the

POR circuit if VDD drops below a preset re-arming

voltage (V^PARM) for at least the minimum required time.

Once VDD has been below the re-arming point for the

minimum required time, the POR Reset will reactivate

and remain in Reset until VDD returns to a value greater

than VPOR. At this point, a 1μs (typical) delay will be

initiated to allow VDD to continue to ramp to a voltage

safely above VPOR.

The Power-up Time Delay will vary from chip-to-chip

and vary due to:

• VDD variation

• Temperature variation

• Process variation

See DC parameters for details (Section 18.0

“Electrical Specifications”).

When the device starts normal operation (exits the

Reset condition), device operating parameters

(i.e., voltage, frequency, temperature, etc.) must be

met to ensure operation. If these conditions are not

met, the device must be held in Reset until the

operating conditions are met.

15.2.4

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word select one of four BOR modes. Two modes have

been added to allow software or hardware control of

the BOR enable. When BOREN<1:0> = 01, the

SBOREN bit (PCON<4>) enables/disables the BOR

allowing it to be controlled in software. By selecting

BOREN<1:0>, the BOR is automatically disabled in

Sleep to conserve power and enabled on wake-up. In

this mode, the SBOREN bit is disabled. See

Register 15-1 for the Configuration Word definition.

For additional information, refer to the Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

15.2.2

MASTER CLEAR (MCLR)

PIC16F785 has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

If VDD falls below VBOR for greater than parameter

(TBOR), see Section 18.0 “Electrical Specifica-

tions”, the Brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not assured if VDD falls below VBOR for less than

parameter (TBOR).

The behavior of the ESD protection on the MCLR pin

has been altered from early devices of this family.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 15-1, is suggested.

On any Reset (Power-on, Brown-out Reset, Watchdog,

etc.), the chip will remain in Reset until VDD rises above

VBOR (see Figure 15-2). The Power-up Timer will now

be invoked, if enabled, and will keep the chip in Reset

an additional 64 ms.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word. When cleared,

MCLR is internally tied to VDD and an internal Weak

Pull-up is enabled for the MCLR pin. In-Circuit Serial

Programming is not affected by selecting the internal

MCLR option.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

DS41249B-page 110

Preliminary

PIC16F785

15.2.5

BOR CALIBRATION

The PIC16F785 stores the BOR calibration values in

fuses located in the Calibration Word (2008h). The

Calibration Word is not erased when using the specified

bulk erase sequence in the “PIC16F785/PS200 Memory

Programming Specification” (DS41237) and thus, does

not require reprogramming.

Note:

Address 2008h is beyond the user program

memory space. It belongs to the special

configuration memory space (2000h-

3FFFh), which can be accessed only during

programming. See “PIC16F785/PS200

Memory Programming Specification”

(DS41237) for more information.

FIGURE 15-2:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

<64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

Preliminary

DS41249B-page 111

PIC16F785

15.2.6

TIME-OUT SEQUENCE

15.2.7

POWER CONTROL (PCON)

REGISTER

On power-up, the time-out sequence is as follows: first,

PWRT time out is invoked after POR has expired, then

OST is activated after the PWRT time out has expired.

The total time out will vary based on oscillator configu-

ration and PWRTE bit status. For example, in EC mode

with PWRTE bit equal to ‘1’ (PWRT disabled), there will

be no time out at all. Figure 15-3, Figure 15-4 and

Figure 15-5 depict time-out sequences. The device can

execute code from the INTOSC, while OST is active by

enabling Two-Speed Start-up or Fail-Safe Monitor (see

Section 3.6.2 “Two-Speed Start-up Sequence” and

Section 3.7 “Fail-Safe Clock Monitor”).

The Power Control register PCON (address 8Eh) has

two Status bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00in the Configuration Word).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Since the time outs occur from the POR pulse, if MCLR

is kept low long enough, the time outs will expire. Then

bringing MCLR high will begin execution immediately

(see Figure 15-4). This is useful for testing purposes or

to synchronize more than one PIC16F785 device

operating in parallel.

For more information, see Section 15.2.4 “Brown-Out

Reset (BOR)”.

Table 15-5 shows the Reset conditions for some

special registers, while Table 15-4 shows the Reset

conditions for all the registers.

TABLE 15-1: TIME OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Oscillator Configuration

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

XT, HS, LP

TPWRT +

1024•TOSC

TPWRT +

1024•TOSC

—

RC, EC, INTOSC

TPWRT

—

TPWRT

—

TABLE 15-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

1

u

x

0

u

1

0

1

u

0

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

TABLE 15-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

03h, 103h STATUS

83h, 183h

IRP

—

RP1

—

RP0

—

TO

PD

—

Z

DC

C

0001 1xxx 000q quuu

8Eh

PCON

SBOREN

—

POR

BOR

---1 --qq ---u --uu

Legend:

u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are not

used by BOR.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41249B-page 112

Preliminary

PIC16F785

FIGURE 15-3:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 15-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 15-5:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD)

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

Preliminary

DS41249B-page 113

PIC16F785

TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS

• MCLR Reset

• Wake-up from Sleep

through interrupt

Power-on

Reset

• WDT Reset

• Brown-out Reset⁽¹⁾

Register

Address

• Wake-up from Sleep

through WDT time out

W

—

00h/80h

01h

xxxx xxxx

0000 0000

0001 1xxx

xxxx xxxx

--x0 x000⁽⁶⁾

xx00 ----⁽⁶⁾

00xx 0000⁽⁶⁾

---0 0000

0000 0000

xxxx xxxx

0000 0000

-000 0000

xxxx xxxx

--00 0000

---0 1000

xxxx xxxx

0000 0000

1111 1111

--11 1111

1111 ----

1111 1111

0000 0000

---1 --0x

-110 x000

---0 0000

1111 1111

uuuu uuuu

xxxx xxxx

uuuu uuuu

0000 0000

000q quuu⁽⁴⁾

uuuu uuuu

--u0 u000⁽⁷⁾

uu00 ----⁽⁷⁾

00uu uuuu⁽⁷⁾

---0 0000

0000 0000

uuuu uuuu

0000 0000

-000 0000

uuuu uuuu

--00 0000

---0 1000

uuuu uuuu

0000 0000

1111 1111

--11 1111

1111 ----

1111 1111

0000 0000

---u --uq^(1,5)

-110 x000

---u uuuu

1111 1111

uuuu uuuu

PC + 1⁽³⁾

INDF

TMR0

PCL

02h/82h

03h/83h

04h/84h

05h

STATUS

FSR

uuuq quuu⁽⁴⁾

uuuu uuuu

--uu uuuu

uuuu ----

uuuu uuuu

---u uuuu

uuuu uuuu⁽²⁾

uuuu uuuu

-uuu uuuu

uuuu uuuu

--uu uuuu

---u uuuu

uuuu uuuu

--uu uuuu

uuuu ----

uuuu uuuu

---u --uu

-uuu uuuu

---u uuuu

uuuu uuuu

1111 1111

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

06h

07h

0Ah/8Ah

0Bh/8Bh

0Ch

TMR1L

TMR1H

T1CON

TMR2

0Eh

0Fh

10h

11h

T2CON

CCPR1L

CCPR1H

CCP1CON

WDTCON

ADRESH

ADCON0

OPTION_REG

TRISA

12h

13h

14h

15h

18h

1Eh

1Fh

81h

85h

TRISB

86h

TRISC

87h

PIE1

8Ch

PCON

8Eh

OSCCON

OSCTUNE

ANSEL0

PR2

8Fh

90h

91h

92h

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 15-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Analog channels read 0but data latches are unknown.

7: Analog channels read 0but data latches are unchanged.

DS41249B-page 114

Preliminary

PIC16F785

TABLE 15-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

• MCLR Reset

• Wake-up from Sleep

through interrupt

Power-on

Reset

• WDT Reset (Continued)

• Brown-out Reset⁽¹⁾

Register

Address

• Wake-up from Sleep

through WDT time out

ANSEL1

93h

95h

---- 1111

--11 1111

--00 0000

--00 000-

000- 0000

0000 0000

---- x000

---- ----

xxxx xxxx

-000 ----

-000 0000

0000 0000

00-- --10

0--- ----

---- 1111

--11 1111

--00 0000

--00 000-

000- 0000

0000 0000

---- q000

---- ----

uuuu uuuu

-000 ----

-000 0000

0000 0000

00-- --10

0--- ----

---- uuuu

--uu uuuu

--uu uuu-

uuu- uuuu

uuuu uuuu

---- uuuu

---- ----

uuuu uuuu

-uuu ----

-uuu uuuu

uuuu uuuu

uu-- --uu

u--- ----

WPUA

IOCA

96h

REFCON

VRCON

98h

99h

EEDAT

9Ah

EEADR

9Bh

EECON1

EECON2

ADRESL

ADCON1

PWMCON1

PWMCON0

PWMCLK

PWMPH1

PWMPH2

CM1CON0

CM2CON0

CM2CON1

OPA1CON

OPA2CON

9Ch

9Dh

9Eh

9Fh

110h

111h

112h

113h

114h

119h

11Ah

11Bh

11Ch

11Dh

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 15-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

6: Analog channels read 0but data latches are unknown.

7: Analog channels read 0but data latches are unchanged.

Preliminary

DS41249B-page 115

PIC16F785

TABLE 15-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

STATUS

Register

PCON

Register

Condition

Power-on Reset

000h

0001 1xxx

000u uuuu

---1 --0x

---u --uu

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

000h

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

---u --uu

---1 --10

---u --uu

WDT Wake-up

PC + 1

000h

PC + 1⁽¹⁾

Brown-out Reset

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, – = unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the

interrupt vector (0004h) after execution of PC+1.

DS41249B-page 116

Preliminary

PIC16F785

For external interrupt events, such as the INT pin or

PORTA change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 15-7). The latency is the same for one or two-

cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

15.3 Interrupts

The PIC16F785 has 11 sources of interrupt:

• External Interrupt RA2/INT

• TMR0 Overflow Interrupt

• PORTA Change Interrupt

• 2 Comparator Interrupts

• A/D Interrupt

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

The Interrupt Control register (INTCON) and Peripheral

Interrupt register (PIR1) record individual interrupt

requests in flag bits. The INTCON register also has

individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>)

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in

INTCON register and PIE1 register. GIE is cleared on

Reset.

For additional information on Timer1, Timer2,

comparators, A/D, Data EEPROM or CCP modules,

refer to the respective peripheral section.

The Return from Interrupt instruction, RETFIE, exits

interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

The following interrupt flags are contained in the

INTCON register:

• INT Pin Interrupt

• PORTA Change Interrupt

• TMR0 Overflow Interrupt

The peripheral interrupt flags are contained in the

special register PIR1. The corresponding interrupt

enable bit is contained in special register PIE1.

The following interrupt flags are contained in the PIR1

register:

• EEPROM Data Write Interrupt

• A/D Interrupt

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• Timer2 Match Interrupt

• Fail-Safe Clock Monitor Interrupt

• CCP Interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt

• The return address is PUSHed onto the stack

• The PC is loaded with 0004h

Preliminary

DS41249B-page 117

PIC16F785

15.3.1

RA2/AN2/T0CKI/INT/C1OUT

INTERRUPT

15.3.2

TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF (INTCON<2>) bit. The interrupt can be

enabled/disabled by setting/clearing T0IE (INTCON<5>)

bit. See Section 5.0 “Timer0 Module” for operation of

the Timer0 module.

External interrupt on RA2/AN2/T0CKI/INT/C1OUT pin

is edge-triggered; either rising, if INTEDG bit

(OPTION_REG<6>) is set, or falling, if INTEDG bit is

clear. When a valid edge appears on the RA2/AN2/

T0CKI/INT/C1OUT pin, the INTF bit (INTCON<1>) is

set. This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>). The INTF bit must be cleared

in software in the Interrupt Service Routine before re-

enabling this interrupt. The RA2/AN2/T0CKI/INT/

C1OUT interrupt can wake-up the processor from

Sleep if the INTE bit was set prior to going into Sleep.

The status of the GIE bit decides whether or not the

processor branches to the interrupt vector following

wake-up (0004h). See Section 15.6 “Power-Down

Mode (Sleep)” for details on Sleep and Figure 15-9 for

timing of wake-up from Sleep through RA2/AN2/

T0CKI/INT/C1OUT interrupt.

15.3.3

PORTA INTERRUPT

An input change on PORTA change sets the RAIF

(INTCON<0>) bit. The interrupt can be enabled/

disabled by setting/clearing the RAIE (INTCON<3>)

bit. Plus, individual pins can be configured through the

IOCA register.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RAIF

interrupt flag may not get set.

Note:

The ANSEL0 (91h), and ANSEL1 (93h)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

FIGURE 15-6:

INTERRUPT LOGIC

IOC-RA0

IOCA0

IOC-RA1

IOCA1

IOC-RA2

IOCA2

IOC-RA3

IOCA3

IOC-RA4

IOCA4

IOC-RA5

IOCA5

(1)

Wake-up (If in Sleep mode)

T0IF

T0IE

TMR2IF

TMR2IE

INTF

INTE

RAIF

Interrupt to CPU

TMR1IF

TMR1IE

RAIE

C1IF

C1IE

PEIE

GIE

C2IF

C2IE

ADIF

ADIE

EEIF

EEIE

Note 1: Some peripherals depend upon the system clock for

operation. Since the system clock is suspended during

Sleep, only those peripherals which do not depend upon

the system clock will wake the part from Sleep. See

Section 15.6.1 “Wake-up from Sleep”.

OSFIF

OSFIE

CCP1IF

CCP1IE

DS41249B-page 118

Preliminary

PIC16F785

FIGURE 15-7:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKOUT

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

0004h

PC + 1

—

0005h

PC

Instruction

Fetched

Inst (PC)

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC - 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 18.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

TABLE 15-6: SUMMARY OF INTERRUPT REGISTERS

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh INTCON

GIE

EEIF

EEIE

PEIE

ADIF

ADIE

T0IE

INTE

C2IF

C2IE

RAIE

C1IF

C1IE

T0IF

INTF

RAIF

0000 0000 0000 0000

0Ch

PIR1

PIE1

CCP1IF

CCP1IE

OSFIF TMR2IF TMR1IF 0000 0000 0000 0000

OSFIE TMR2IE TMR1IE 0000 0000 0000 0000

8Ch

Legend:

x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition. Shaded cells are not

used by the Interrupt module.

Preliminary

DS41249B-page 119

PIC16F785

15.4 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and STATUS

registers). This must be implemented in software.

Since the last 16 bytes of all banks are common in the

PIC16F785 (see Figure 2-2), temporary holding

registers W_TEMP and STATUS_TEMP should be

placed in here. These 16 locations do not require

banking, therefore, making it easier to save and restore

context. The same code shown in Example 15-1 can

be used to:

• Store the W register

• Store the STATUS register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

Note:

The PIC16F785 normally does not require

saving the PCLATH. However, if computed

GOTO’s are used in the ISR and the main

code, the PCLATH must be saved and

restored in the ISR.

EXAMPLE 15-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

CLRF

MOVWF

:

W_TEMP

STATUS,W

STATUS

;Copy W to TEMP register

;Swap status to be saved into W (swap does not affect status)

;bank 0, regardless of current bank, Clears IRP,RP1,RP0

;Save status to bank zero STATUS_TEMP register

STATUS_TEMP

:(ISR)

:

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into Status register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS41249B-page 120

Preliminary

PIC16F785

A new prescaler has been added to the path between

the INTRC and the multiplexers used to select the path

for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTRC by 128 to 65536,

giving the time base used for the WDT a nominal range

of 1 ms to 268s.

15.5 Watchdog Timer (WDT)

For PIC16F785, the WDT has been modified from

previous PIC16F785 devices. The new WDT is code

and functionally compatible with previous PIC16F785

WDT modules and adds a 16-bit prescaler to the WDT.

This allows the user to scale the value for the WDT and

TMR0 at the same time. In addition, the WDT time out

value can be extended to 268 seconds. WDT is cleared

under certain conditions described in Table 15-7.

15.5.2

WDT CONTROL

The WDTE bit is located in the Configuration Word.

When set, the WDT runs continuously.

15.5.1

WDT OSCILLATOR

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit (WDTCON<0>) has no effect.

If WDTE is clear, then the SWDTEN bit can be used to

enable and disable the WDT. Setting the bit will enable

it and clearing the bit will disable it.

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled (OSCON<1>).

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 16 ms, which is com-

patible with the time base generated with previous

PIC16F785 microcontroller versions.

The PSA and PS<2:0> bits (OPTION_REG) have the

same function as in previous versions of the

PIC16F785 family of microcontrollers. See Section 5.0

“Timer0 Module” for more information.

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

FIGURE 15-8:

WATCHDOG TIMER BLOCK DIAGRAM

0

From TMR0 Clock Source

Prescaler⁽¹⁾

1

16-bit WDT Prescaler

8

PSA

PS<2:0>

31 kHz

LFINTOSC Clock

WDTPS<3:0>

TO TMR0

1

0

PSA

WDTE from Configuration Word

SWDTEN from WDTCON

WDT time-out

Note 1:

This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

TABLE 15-7: WDT STATUS

Conditions

WDT

WDTE = 0

CLRWDTcommand

OSC FAIL detected

Cleared

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Preliminary

DS41249B-page 121

PIC16F785

REGISTER 15-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 18h)

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN⁽¹⁾

bit 7

bit 0

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = reserved

1101 = reserved

1110 = reserved

1111 = reserved

bit 0

SWDTEN: Software Enable or Disable the Watchdog Timer bit⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this

control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with

this control bit.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 15-8: SUMMARY OF WATCHDOG TIMER REGISTERS

Value on all

other

resets

Value on:

POR,BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

03h, 103h

83h, 183h

STATUS

IRP

—

RP1

—

RPO

—

TO

PD

Z

DC

C

0001 1xxx 000q quuu

18h

WDTCON

WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

81h/

181h

OPTION_REG

RAPU INTEDG T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

2007h⁽¹⁾

CONFIG

CPD CP MCLRE

PWRTE

WDTE

FOSC2

FOSC1

FOSC0 uuuu uuuu uuuu uuuu

Legend:

Note 1:

Shaded cells are not used by the Watchdog Timer.

See Register 15-1 for operation of all Configuration Word bits.

DS41249B-page 122

Preliminary

PIC16F785

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit (and PEIE bit where applicable)

must be set (enabled). Wake-up is regardless of the

state of the GIE bit. If the GIE bit is clear (disabled), the

device continues execution at the instruction after the

SLEEP instruction. If the GIE bit is set (enabled), the

device executes the instruction after the SLEEPinstruc-

tion, then branches to the interrupt address (0004h). In

cases where the execution of the instruction following

SLEEP is not desirable, the user should have a NOP

after the SLEEPinstruction.

15.6 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEPinstruction.

If the Watchdog Timer is enabled:

• WDT will be cleared but keeps running.

• PD bit in the STATUS register is cleared.

• TO bit is set.

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or high-

impedance).

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the corresponding

interrupt flag bits set (including PEIE, where

applicable), the device will immediately

wake-up from Sleep. The SLEEPinstruction

is completely executed.

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin, and all

unused peripheral modules should be disabled. Digital

I/O pins that are high-impedance inputs should be

pulled high or low externally to avoid switching currents

caused by floating inputs. The T0CKI input should also

be at VDD or VSS for lowest current consumption. The

contribution from on-chip pull-ups on PORTA should be

considered.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

15.6.2

WAKE-UP USING INTERRUPTS

The MCLR pin must be at a logic high level.

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

Note:

It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

15.6.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin

2. Watchdog Timer Wake-up (if WDT was enabled)

• If the interrupt occurs during or after the

execution of a SLEEPinstruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set, and the PD bit will be cleared.

3. Interrupt from RA2/AN2/T0CKI/INT/C1OUT pin,

PORTA change or a peripheral interrupt.

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the STATUS register

can be used to determine the cause of device Reset.

The PD bit, which is set on power-up, is cleared when

Sleep is invoked. TO bit is cleared if WDT Wake-up

occurred.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

The following peripheral interrupts can wake the device

from Sleep:

1. TMR1 interrupt. Timer1 must be operating as an

asynchronous counter.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

2. CCP Capture mode interrupt

3. A/D conversion (when A/D clock source is RC)

4. EEPROM write operation completion

5. Comparator output changes state

6. Interrupt-on-change

7. External Interrupt from INT pin

Other peripherals cannot generate interrupts since,

during Sleep, no on-chip clocks are present.

Preliminary

DS41249B-page 123

PIC16F785

FIGURE 15-9:

WAKE-UP FROM SLEEP THROUGH INTERRUPT⁽¹⁾

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIE bit

(INTCON<7>)

Processor

in Sleep

INSTRUCTION FLOW

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Inst(PC - 1)

Fetched

Instruction

Executed

Dummy cycle

Sleep

Inst(PC + 1)

Inst(0004h)

Note 1:

2:

XT, HS or LP Oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale). This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up

(see Section 3.6 “Two-Speed Clock Start-up Mode”).

3:

4:

GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h.

If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

DS41249B-page 124

Preliminary

PIC16F785

FIGURE 15-10:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

15.7 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP^™for verification purposes.

To Normal

Connections

Note:

The entire data EEPROM and Flash

program memory will be erased when the

code protection is turned off by performing

a bulk erase. See the “PIC16F785/PS200

Memory Programming Specification”

(DS41237) for more information.

External

Connector

Signals

*

PIC16F785

+5.0V

0V

VDD

VSS

VPP

MCLR/VPP/RA3

15.8 ID Locations

RA1

RA0

CLK

Data I/O

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are

readable and writable during Program/Verify. Only the

Least Significant 7 bits of the ID locations are used.

*

15.9 In-Circuit Serial Programming™

To Normal

Connections

The PIC16F785 microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with five lines:

*

Isolation devices (as required)

• clock

• data

• power

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware or a custom

firmware to be programmed.

The device is placed into a Program/Verify mode by

holding the RA0 and RA1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH. See the “PIC16F785/

PS200

Memory

Programming

Specification”

(DS41237) for more information. RA0 becomes the

programming data and RA1 becomes the programming

clock. Both RA0 and RA1 are Schmitt Trigger inputs in

this mode.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the “PIC16F785/PS200 Memory Programming

Specification” (DS41237).

A typical In-Circuit Serial Programming connection is

shown in Figure 15-10.

Preliminary

DS41249B-page 125

PIC16F785

15.10 In-Circuit Debugger

In-circuit debugging requires clock, data and MCLR

pins. A special 28-pin PIC16F785 ICD device is used

with MPLAB^®ICD 2 to provide separate clock, data

and MCLR pins so that no pins are lost for these

functions leaving all 18 of the PIC16F785 I/O pins

available to the user during debug operation.

This special ICD device is mounted on the top of a

header and its signals are routed to the MPLAB ICD 2

connector. On the bottom of the header is a 20-pin

socket that plugs into the user’s target via the 20-pin

stand-off connector.

When the ICD pin on the PIC16F785 ICD device is held

low, the In-Circuit Debugger functionality is enabled.

This function allows simple debugging functions when

used with MPLAB ICD 2. When the microcontroller has

this feature enabled, some of the resources are not

available for general use. Table 15-9 shows which

features are consumed by the background debugger:

TABLE 15-9: DEBUGGER RESOURCES

Resource

Description

I/O pins

Stack

ICDCLK, ICDDATA

1 level

Data RAM

65h-70h, F0h

Program Memory Address 0h must be NOP

700h-7FFh

For more information, see “MPLAB^®ICD 2 In-Circuit

Debugger User’s Guide” (DS51331), available on

Microchip’s web site (www.microchip.com).

FIGURE 15-11:

28-Pin PDIP

28-PIN ICD PINOUT

In-Circuit Debug Device

1

28

SHNTREG

ICDCLK

2

3

27

26

ICDMCLR/VPP

VDD

ICDDATA

Vss

4

5

25

24

RA5

RA4

RA3

RC5

RC4

RA0

RA1

RA2

RC0

RC1

6

7

8

23

22

21

9

20

19

18

17

RC3

RC6

RC7

RB7

RC2

RB4

RB5

RB6

10

11

12

13

14

16

15

ICD

NC

DS41249B-page 126

Preliminary

PIC16F785

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back

to PORTA. This example would have the unintended

result of clearing the condition that set the RAIF flag.

16.0 INSTRUCTION SET SUMMARY

The PIC16F785 instruction set is highly orthogonal and

is comprised of three basic categories:

• Byte-oriented operations

• Bit-oriented operations

TABLE 16-1: OPCODE FIELD

DESCRIPTIONS

• Literal and control operations

Field

Description

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The format for each of the categories is

presented in Figure 16-1, while the various opcode

fields are summarized in Table 16-1.

f

W

b

k

x

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Table 16-2 lists the instructions recognized by the

MPASM^TMassembler. A complete description of

each instruction is also available in the “PICmicro^®

Mid-Range MCU Family Reference Manual”

(DS33023).

Don't care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

PC

TO

PD

Program Counter

Time-out bit

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

Power-down bit

FIGURE 16-1:

GENERAL FORMAT FOR

INSTRUCTIONS

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

changed as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

Note:

To maintain upward compatibility with

future products, do not use the OPTION

and TRISinstructions.

General

13

8

7

0

OPCODE

k (literal)

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’signifies

a hexadecimal digit.

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

16.1 Read-Modify-Write Operations

0

Any instruction that specifies a file register as part of

the instruction performs a read-modify-write (RMW)

operation. The register is read, the data is modified,

and the result is stored according to either the

instruction, or the destination designator ‘d’. A read

operation is always performed, even if the instruction is

a write command.

k (literal)

Preliminary

DS41249B-page 127

PIC16F785

TABLE 16-2: PIC16F785 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Description

Operands

Status

Affected

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C,DC,Z

1,2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

-

f, d

f

1,2

1,2,3

1,2

1,2,3

1,2

Z

Move W to f

No Operation

-

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1,2

00 0010 dfff ffff C,DC,Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1,2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C,DC,Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

00 0000 0110 0100

10 1kkk kkkk kkkk

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

00 0000 0110 0011

Z

TO,PD

Z

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

TO,PD

11 110x kkkk kkkk C,DC,Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note:

Additional information on the mid-range

instruction set is available in the “PICmicro^®

Mid-Range MCU Family Reference

Manual” (DS33023).

DS41249B-page 128

Preliminary

PIC16F785

16.2 Instruction Descriptions

ADDLW

Add Literal and W

BCF

Bit Clear f

Syntax:

[label] ADDLW

0 ≤ k ≤ 255

k

Syntax:

[label] BCF f,b

Operands:

Operation:

Status Affected:

Description:

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

(W) + k → (W)

C, DC, Z

Operation:

0 → (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the W

register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[label] BSF f,b

Syntax:

[label] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1 → (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

BTFSC

Bit Test f, Skip if Clear

ANDLW

AND Literal with W

Syntax:

[label] BTFSC f,b

Syntax:

[label] ANDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description:

If bit ‘b’ in register ‘f'’ is ‘1’, the next

instruction is executed.

If bit ‘b’, in register ‘f’, is ‘0’, the

next instruction is discarded, and

a NOPis executed instead, making

this a two-cycle instruction.

ANDWF

AND W with f

BTFSS

Bit Test f, Skip if Set

Syntax:

[label] ANDWF f,d

Syntax:

[label] BTFSS f,b

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operation:

(W) .AND. (f) → (destination)

Operation:

skip if (f<b>) = 1

Status Affected:

Description:

Z

Status Affected: None

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

Description: If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

If bit ‘b’ is ‘1’, then the next instruc-

tion is discarded and a NOPis

executed instead, making this a

two-cycle instruction.

result is stored back in register ‘f’.

Preliminary

DS41249B-page 129

PIC16F785

COMF

Complement f

CALL

Call Subroutine

Syntax:

[ label ] COMF f,d

Syntax:

[ label ] CALL

0 ≤ k ≤ 2047

k

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in regis-

ter ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit immedi-

ate address is loaded into PC bits

<10:0>. The upper bits of the PC

are loaded from PCLATH. CALLis

a two-cycle instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[label] DECF f,d

Syntax:

[label] CLRF

0 ≤ f ≤ 127

f

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → (f)

1 → Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW

Clear W

DECFSZ

Decrement f, Skip if 0

Syntax:

[ label ] CLRW

Syntax:

[ label ] DECFSZ f,d

Operands:

Operation:

None

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

00h → (W)

1 → Z

Operation:

(f) - 1 → (destination);

skip if result = 0

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

Status Affected: None

Description: The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] CLRWDT

Operands:

Operation:

None

If the result is ‘1’, the next instruc-

tion is executed. If the result is ‘0’,

then a NOPis executed instead,

making it a two-cycle instruction.

00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

DS41249B-page 130

Preliminary

PIC16F785

GOTO

Unconditional Branch

IORLW

Inclusive OR Literal with W

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a two-

cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

INCFSZ

Increment f, Skip if 0

MOVF

Move f

Syntax:

[ label ] INCFSZ f,d

Syntax:

Operands:

[ label ] MOVF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) + 1 → (destination),

skip if result = 0

Operation:

(f) → (dest)

Status Affected:

Encoding:

Z

Status Affected: None

00

1000

dfff

ffff

Description: The contents of register ‘f’ are

Description:

The contents of register ‘f’ is

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next instruc-

tion is executed. If the result is ‘0’,

a NOPis executed instead, making

it a two-cycle instruction.

moved to a destination dependent

upon the status of ‘d’. If ‘d’ = 0,

destination is W register. If ‘d’ = 1,

the destination is file register ‘f’

itself. ‘d’ = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVF

FSR,

0

After Instruction

W

=

value in FSR

register

Z

=

1

Preliminary

DS41249B-page 131

PIC16F785

NOP

No Operation

[ label ] NOP

None

MOVLW

Move Literal to W

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → (W)

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

Status Affected:

Encoding:

Description:

No operation

None

00

0000

0xx0

0000

11

00xx

kkkk

No operation.

The eight-bit literal ‘k’ is loaded

into W register. The “don’t cares”

will assemble as 0’s.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

RETFIE

Return from Interrupt

[ label ] RETFIE

None

MOVWF

Move W to f

Syntax:

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

f

Operands:

Operation:

Operands:

Operation:

Status Affected:

Encoding:

Description:

TOS → PC,

1 → GIE

None

Status Affected:

Encoding:

None

00

0000

1fff

ffff

00

0000

1001

Move data from W register to

register ‘f’.

Description:

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global

Interrupt Enable bit, GIE

Words:

1

Cycles:

Example:

MOVWF

OPTION

(INTCON<7>). This is a two-cycle

instruction.

Before Instruction

OPTION =

0xFF

0x4F

Words:

1

W

=

After Instruction

Cycles:

Example:

2

OPTION =

W

0x4F

RETFIE

=

After Interrupt

PC

GIE =

=

TOS

1

DS41249B-page 132

Preliminary

PIC16F785

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

RLF

Rotate Left f through Carry

Syntax:

Operands:

[ label ]

RLF f,d

Operands:

Operation:

0 ≤ f ≤ 127

d ∈ [0,1]

k → (W);

TOS → PC

Operation:

See description below

C

Status Affected:

Encoding:

None

Status Affected:

Encoding:

11

01xx

kkkk

00

1101

dfff

ffff

Description:

The W register is loaded with the

eight-bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

Description:

The contents of register ‘f’ are

rotated one bit to the left through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Words:

1

2

C

Register f

Cycles:

Example:

CALL TABLE;W contains

table

Words:

1

Cycles:

Example:

;offset value

TABLE

•

;W now has table value

RLF

REG1,0

Before Instruction

REG1

C

=

1110 0110

0

ADDWF PC ;W = offset

RETLW k1 ;Begin table

After Instruction

RETLW k2

;

REG1

W

C

=

1110 0110

1100 1100

1

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

Preliminary

DS41249B-page 133

PIC16F785

RRF

Rotate Right f through Carry

SUBLW

Subtract W from Literal

Syntax:

[ label ] RRF f,d

Syntax:

[label]

SUBLW k

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

0 ≤ k ≤ 255

k - (W) → (W)

Operation:

See description below

C

Status

Affected:

C, DC, Z

Status Affected:

Encoding:

00

1100

dfff

ffff

11

110x

kkkk

Encoding:

Description:

The contents of register ‘f’ are

rotated one bit to the right

through the Carry Flag. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’ the result is

placed back in register ‘f’.

Description:

The W register is subtracted (2’s

complement method) from the eight-

bit literal ‘k’. The result is placed in

the W register.

Words:

1

Cycles:

C

REGISTER F

SUBLW

0x02

Example 1:

Before Instruction

W = 1

Words:

1

Cycles:

Example:

1

C

= ?

RRF

REG1, 0

After Instruction

Before Instruction

REG1 = 1110 0110

= 0

After Instruction

REG1 = 1110 0110

W = 1

C

= 1; result is positive

C

Example 2:

Example 3:

Before Instruction

W =

C =

2

?

W

C

= 0111 0011

= 0

After Instruction

W =

C = 1; result is zero

Before Instruction

W =

C =

0

SLEEP

Go into Standby mode

Syntax:

[label]

SLEEP

3

?

Operands:

Operation:

None

00h → WDT,

0 → WDT prescaler,

1 → TO,

After Instruction

W = 0xFF

0 → PD

C = 0; result is negative

Status Affected:

Encoding:

TO, PD

00

0000

0110

0011

Description:

The power-down Status bit, PD

is cleared. Time out Status bit,

TO is set. Watchdog Timer and

its prescaler are cleared.

The processor is put into Sleep

mode with the oscillator

stopped.

Words:

1

Cycles:

Example:

1

SLEEP

DS41249B-page 134

Preliminary

PIC16F785

SUBWF

Subtract W from f

SWAPF

Swap Nibbles in f

Syntax:

[label]

SUBWF f,d

Syntax:

[ label ]

SWAPF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - (W) → (dest)

Operation:

(f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>)

Status

C, DC, Z

Affected:

Status Affected:

Encoding:

None

00

0010

dfff

ffff

00

1110

dfff

ffff

Encoding:

Description:

Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W reg-

ister. If ‘d’ is ‘1’, the result is stored

back in register ‘f’.

Description:

The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in W regis-

ter. If ‘d’ is ‘1’, the result is placed

in register ‘f’.

Words:

1

Words:

1

Cycles:

Example:

SUBWF

REG1, 1

SWAPF

REG1, 0

Example 1:

Before Instruction

REG1 = 3

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

0x5A

W

C

= 2

= ?

After Instruction

W

=

REG1 = 1

W

C

= 2

= 1; result is positive

TRIS

Load TRIS Register

Z

DC

= 0

= 1

Syntax:

[ label ] TRIS

5 ≤ f ≤ 6

f

Operands:

Operation:

Status Affected:

Encoding:

Description:

Example 2:

Before Instruction

(W) → TRIS register f;

REG1 = 2

W

C

None

= 2

= ?

00

0000

0110

0fff

The instruction is supported for

code compatibility with the

PIC16C5X products. Since TRIS

registers are readable and writ-

able, the user can directly

address them.

After Instruction

REG1 = 0

W

C

Z

= 2

= 1; result is zero

= DC = 1

Example 3:

Before Instruction

Words:

Cycles:

Example

1

REG1 = 1

W

C

= 2

= ?

To maintain upward compatibil-

ity with future PICmicro^®

products, do not use this

instruction.

After Instruction

REG1 = 0xFF

W

C

Z

= 2

= 0; result is negative

= DC = 0

Preliminary

DS41249B-page 135

PIC16F785

XORLW

Exclusive OR Literal with W

[label] XORLW k

XORWF

Exclusive OR W with f

Syntax:

[ label ]

XORWF f,d

Operands:

Operation:

Status Affected:

Encoding:

0 ≤ k ≤ 255

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(W) .XOR. k → (W)

Operation:

(W) .XOR. (f) → (dest)

Z

Status Affected:

Encoding:

Z

11

1010

kkkk

00

0110

dfff

ffff

Description:

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

Description:

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’ the result is

stored back in register ‘f’.

Words:

1

Cycles:

Example:

Words:

1

XORLW

0xAF

Cycles:

Example:

Before Instruction

W = 0xB5

XORWF

REG1, 1

Before Instruction

REG1 = 0xAF

0xB5

After Instruction

W = 0x1A

W

=

After Instruction

REG1 = 0x1A

0xB5

W

=

DS41249B-page 136

Preliminary

PIC16F785

17.1 MPLAB Integrated Development

Environment Software

17.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• An interface to debugging tools

- simulator

- MPLAB C17 and MPLAB C18 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

• Customizable data windows with direct edit of

contents

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

• Emulators

• High-level source code debugging

• Mouse over variable inspection

• Extensive on-line help

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

- MPLAB ICD 2

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

(automatically updates all project information)

• Device Programmers

- PRO MATE^®II Universal Device Programmer

- PICSTART^®Plus Development Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration Boards

- PICDEM^TM1 Demonstration Board

- PICDEM.net^TMDemonstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM LIN Demonstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

• Debug using:

- source files (assembly or C)

- mixed assembly and C

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increasing flexibility

and power.

17.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

®

- KEELOQ Evaluation and Programming Tools

- PICDEM MSC

- microID^®Developer Kits

- CAN

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol ref-

erence, absolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

- PowerSmart^®Developer Kits

- Analog

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User defined macros to streamline assembly code

• Conditional assembly for multi-purpose source

files

• Directives that allow complete control over the

assembly process

Preliminary

DS41249B-page 137

PIC16F785

17.3 MPLAB C17 and MPLAB C18

C Compilers

17.6 MPLAB ASM30 Assembler, Linker

and Librarian

The MPLAB C17 and MPLAB C18 Code Development

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

Systems are complete ANSI

C

compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

17.4 MPLINK Object Linker/

MPLIB Object Librarian

• Rich directive set

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

• Flexible macro language

• MPLAB IDE compatibility

17.7 MPLAB SIM Software Simulator

The MPLAB SIM software simulator allows code devel-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any pin. The execu-

tion can be performed in Single-Step, Execute Until

Break or Trace mode.

The MPLIB object librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool.

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

17.5 MPLAB C30 C Compiler

17.8 MPLAB SIM30 Software Simulator

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command

line options and language extensions to take full

advantage of the dsPIC30F device hardware capabili-

ties and afford fine control of the compiler code

generator.

The MPLAB SIM30 software simulator allows code

development in a PC hosted environment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler. The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high-speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been vali-

dated and conform to the ANSI C library standard. The

library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keeping and math functions (trigonometric, exponential

and hyperbolic). The compiler provides symbolic

information for high-level source debugging with the

MPLAB IDE.

DS41249B-page 138

Preliminary

PIC16F785

17.9 MPLAB ICE 2000

High-Performance Universal

17.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the Flash devices. This feature, along with

In-Circuit Emulator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

Microchip’s In-Circuit Serial Programming^TM(ICSP^TM

)

protocol, offers cost effective in-circuit Flash debugging

from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro devices.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

features. Interchangeable processor modules allow the

system to be easily reconfigured for emulation of differ-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

17.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maximum reliability. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II device programmer can read, verify and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

17.10 MPLAB ICE 4000

High-Performance Universal

In-Circuit Emulator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for high-

end PICmicro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debugging from a single environment.

17.13 MPLAB PM3 Device Programmer

The MPLAB PM3 is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maximum reliability. It features

a large LCD display (128 x 64) for menus and error

messages and a modular detachable socket assembly

to support various package types. The ICSP™ cable

assembly is included as a standard item. In Stand-

Alone mode, the MPLAB PM3 device programmer can

read, verify and program PICmicro devices without a

PC connection. It can also set code protection in this

mode. MPLAB PM3 connects to the host PC via an RS-

232 or USB cable. MPLAB PM3 has high-speed com-

munications and optimized algorithms for quick pro-

gramming of large memory devices and incorporates

an SD/MMC card for file storage and secure data appli-

cations.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, up to 2 Mb of emulation memory and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

Preliminary

DS41249B-page 139

PIC16F785

17.14 PICSTART Plus Development

Programmer

17.17 PICDEM 2 Plus

Demonstration Board

The PICSTART Plus development programmer is an

easy-to-use, low-cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

The PICDEM 2 Plus demonstration board supports

many 18, 28 and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary hardware and software is included to run the dem-

onstration programs. The sample microcontrollers

provided with the PICDEM 2 demonstration board can

be programmed with a PRO MATE II device program-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB ICD 2 and MPLAB ICE in-circuit emulators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display, a piezo speaker, an on-board temperature

sensor, four LEDs and sample PIC18F452 and

PIC16F877 Flash microcontrollers.

17.15 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demonstration board demonstrates the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provided with the PICDEM 1 demonstration board can

be programmed with a PRO MATE II device program-

mer or a PICSTART Plus development programmer.

The PICDEM 1 demonstration board can be connected

to the MPLAB ICE in-circuit emulator for testing. A

prototype area extends the circuitry for additional appli-

cation components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

17.18 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and software is included to run

the demonstration programs.

17.19 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8, 14 and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F87/88, PIC16F62XA and the PIC18F1320

family of microcontrollers. PICDEM 4 is intended to

showcase the many features of these low pin count

parts, including LIN and Motor Control using ECCP.

Special provisions are made for low-power operation

with the supercapacitor circuit and jumpers allow on-

board hardware to be disabled to eliminate current

draw in this mode. Included on the demo board are pro-

visions for Crystal, RC or Canned Oscillator modes, a

five volt regulator for use with a nine volt wall adapter

or battery, DB-9 RS-232 interface, ICD connector for

programming via ICSP and development with MPLAB

ICD 2, 2 x 16 liquid crystal display, PCB footprints for

H-Bridge motor driver, LIN transceiver and EEPROM.

Also included are: header for expansion, eight LEDs,

four potentiometers, three push buttons and a proto-

typing area. Included with the kit is a PIC16F627A and

a PIC18F1320. Tutorial firmware is included along

with the User’s Guide.

17.16 PICDEM.net Internet/Ethernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

DS41249B-page 140

Preliminary

PIC16F785

17.20 PICDEM 17 Demonstration Board

17.24 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM 17 demonstration board is an evaluation

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A pro-

grammed sample is included. The PRO MATE II device

programmer, or the PICSTART Plus development pro-

grammer, can be used to reprogram the device for user

tailored application development. The PICDEM 17

demonstration board supports program download and

execution from external on-board Flash memory. A

generous prototype area is available for user hardware

expansion.

The PICDEM USB Demonstration Board shows off the

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

17.25 Evaluation and

Programming Tools

In addition to the PICDEM series of circuits, Microchip

has a line of evaluation kits and demonstration software

for these products.

• KEELOQ evaluation and programming tools for

Microchip’s HCS Secure Data Products

17.21 PICDEM 18R PIC18C601/801

Demonstration Board

• CAN developers kit for automotive network

applications

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/Demultiplexed and 16-bit

Memory modes. The board includes 2 Mb external

Flash memory and 128 Kb SRAM memory, as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

• Analog design boards and filter design software

• PowerSmart battery charging evaluation/

calibration kits

• IrDA^®development kit

• microID development and rfLab^TMdevelopment

software

• SEEVAL^®designer kit for memory evaluation and

endurance calculations

17.22 PICDEM LIN PIC16C43X

Demonstration Board

• PICDEM MSC demo boards for Switching mode

power supply, high-power IR driver, delta sigma

ADC and flow rate sensor

The powerful LIN hardware and software kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

Check the Microchip web page and the latest Product

Selector Guide for the complete list of demonstration

and evaluation kits.

on-board LIN transceivers.

A PIC16F874 Flash

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN bus communication.

17.23 PICkit^TM1 Flash Starter Kit

A complete “development system in a box”, the PICkit™

Flash Starter Kit includes a convenient multi-section

board for programming, evaluation and development of

8/14-pin Flash PIC^®microcontrollers. Powered via USB,

the board operates under a simple Windows GUI. The

PICkit 1 Starter Kit includes the User’s Guide (on CD

ROM), PICkit 1 tutorial software and code for various

applications. Also included are MPLAB^®IDE (Integrated

Development Environment) software, software and

hardware “Tips 'n Tricks for 8-pin Flash PIC^®

Microcontrollers” Handbook and a USB interface cable.

Supports all current 8/14-pin Flash PIC microcontrollers,

as well as many future planned devices.

Preliminary

DS41249B-page 141

PIC16F785

NOTES:

DS41249B-page 142

Preliminary

PIC16F785

18.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings^(†)

Ambient temperature under bias........................................................................................................... -40 to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ...................................................................................................... -0.3 to +6.5V

Voltage on MCLR with respect to Vss ..................................................................................................-0.3 to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾(PDIP and SOIC)................................................................................................... 800 mW

Total power dissipation⁽¹⁾(SSOP)..................................................................................................................600 mW

Maximum current out of VSS pin ..................................................................................................................... 300 mA

Maximum current into VDD pin ........................................................................................................................ 250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................ 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD).......................................................................................................... 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sunk by PORTA, PORTB, and PORTC (combined)...........................................................200 mA

Maximum current sourced PORTA, PORTB, and PORTC (combined)...........................................................200 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note:

Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin, rather than

pulling this pin directly to VSS.

Preliminary

DS41249B-page 143

PIC16F785

FIGURE 18-1:

PIC16F785 WITH ANALOG DISABLED VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VDD

(Volts)

0

4

8

10

12

16

20

Frequency (MHz)

Note:

The shaded region indicates the permissible combinations of voltage and frequency.

DS41249B-page 144

Preliminary

PIC16F785

18.1 DC Characteristics: PIC16F785-I (Industrial), PIC16F785-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

No.

Sym

Characteristic

Min Typ† Max Units

Conditions

VDD

Supply Voltage

FOSC ≤ 4 MHz:

D001

2.0

2.2

2.5

3.0

4.5

—

5.5

V

PIC16F785with A/D off

D001A

D001B

D001C

D001D

PIC16F785 with A/D on, 0°C to +125°C

PIC16F785 with A/D on, -40°C to +125°C

4 MHz ≤ FOSC ≤ 10 MHz

10 MHz ≤ FOSC ≤ 20 MHz

D002

VDR

RAM Data Retention

Voltage⁽¹⁾

1.5*

—

1.8

1.0

—

V

Device in Sleep mode

D003

VPOR

VDD voltage above which

the internal POR releases

—

See Section 15.2.1 “Power-On Reset” for

details.

D003A VPARM VDD voltage below which

—

See Section 15.2.1 “Power-On Reset” for

details.

the internal POR rearms

D004

D005

SVDD

VDD Rise Rate to ensure 0.05*

internal Power-on Reset

signal

V/ms See Section 15.2.1 “Power-On Reset” for

details.

VBOR

Brown-out Reset

—

2.1

—

V

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

Preliminary

DS41249B-page 145

PIC16F785

(1,2)

18.2 DC Characteristics: PIC16F785-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Device Characteristics

Min Typ† Max Units

VDD

Note

D010

Supply Current (IDD)

—

9

TBD

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

17

33

D011

D012

D013

D014

D015

D016

D017

110

190

330

220

300

540

70

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

FOSC = 1 MHz

EC Oscillator mode

140

260

180

320

580

9

FOSC = 4 MHz

EC Oscillator mode

FOSC = 31 kHz

INTRC mode

18

35

340

500

0.8

180

320

580

2.8

3.3

FOSC = 4 MHz

INTOSC mode

FOSC = 4 MHz

EXTRC mode

D018

FOSC = 20 MHz

HS Oscillator mode

Legend:

TBD = To Be Determined.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.

DS41249B-page 146

Preliminary

PIC16F785

(1,2)

18.2 DC Characteristics: PIC16F785-I (Industrial)

(Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Device Characteristics

Min Typ† Max Units

VDD

Note

D020

Power-down Base Current

(IPD)

—

25

45

TBD

nA

μA

nA

μA

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF, T1OSC,

Op Amps and VR disabled

(4)

85

(3)

D021

0.3

1.2

2.2

50

WDT Current

(3)

D022

D023

BOR Current

100

150

170

200

3.3

6.1

35

(3)

Comparator Current

CxSP = 1

(3)

D023A

D024

Comparator Current

CxSP = 0

(3)

58

CVREF Current

Low Range

85

104

35

(3)

D024A

D025

CVREF Current

High Range (VRR = 0)

45

80

(3)

1.8

2.0

3.2

1.2

2.2

10

T1 OSC Current

(3)

D026

D027

A/D Current

(not converting)

(3)

VR Current

11

12

(3)

D028

150

250

Op Amp Current

Legend:

TBD = To Be Determined.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail-to-

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. the power-down current spec includes any such leakage from the A/D module.

Preliminary

DS41249B-page 147

PIC16F785

(1,2)

18.3 DC Characteristics: PIC16F785-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Param

No.

Device Characteristics

Min Typ† Max Units

VDD

Note

D010E Supply Current (IDD)

—

9

TBD

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

17

33

D011E

D012E

D013E

D014E

D015E

D016E

D017E

D018E

110

190

330

220

300

540

70

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

FOSC = 1 MHz

EC Oscillator mode

140

260

180

320

580

9

FOSC = 4 MHz

EC Oscillator mode

FOSC = 31 kHz

INTRC mode

18

35

340

500

0.8

180

320

580

2.8

3.3

FOSC = 4 MHz

INTOSC mode

FOSC = 4 MHz

EXTRC mode

FOSC = 20 MHz

HS Oscillator mode

Legend:

TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. The power-down current spec includes any such leakage from the A/D

module.

DS41249B-page 148

Preliminary

PIC16F785

(1,2)

18.3 DC Characteristics: PIC16F785-E (Extended)

(Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Param

No.

Device Characteristics

Min Typ† Max Units

VDD

Note

D020E Power-down Base Current

—

25

45

TBD

nA

μA

nA

μA

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF, T1OSC,

Op Amps and VR disabled

(4)

(IPD)

85

(3)

D021E

0.3

1.2

2.2

50

WDT Current

(3)

D022E

D023E

BOR Current

100

50

(3)

Comparator Current

CxSP = 1

170

200

3.3

6.1

35

(3)

D023E

D024E

D025E

Comparator Current

CxSP = 0

(3)

58

CVREF Current

Low Range

85

104

35

(3)

CVREF Current

High Range

45

80

(3)

1.8

2.0

3.2

1.2

2.2

10

T1 OSC Current

(3)

D026E

D027E

A/D Current

(not converting)

(3)

VR Current

11

12

(3)

D028E

150

250

Op Amp Current

Legend:

TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave, from rail to

rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current

consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is

enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD current from this limit. Max

values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with

the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD. When A/D is off, it will not consume

any current other than leakage current. The power-down current spec includes any such leakage from the A/D

module.

Preliminary

DS41249B-page 149

PIC16F785

18.4 DC Characteristics: PIC16F785-I (Industrial), PIC16F785-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

Input Low Voltage

I/O ports

VIL

D030

D030A

D031

D032

D033

D033A

with TTL buffer

VSS

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

0.15 VDD

0.2 VDD

0.3

Otherwise

with Schmitt Trigger buffer

MCLR, OSC1 (RC mode)

Entire range

(1)

OSC1 (XT and LP modes)

(1)

OSC1 (HS mode)

0.3 VDD

Input High Voltage

I/O ports

VIH

—

D040

D040A

with TTL buffer

2.0

—

VDD

V

4.5V ≤ VDD ≤ 5.5V

Otherwise

(0.25 VDD + 0.8)

D041

D042

D043

D043A

D043B

D070

with Schmitt Trigger buffer

MCLR

0.8 VDD

1.6

—

VDD

400*

V

Entire range

OSC1 (XT and LP modes)

OSC1 (HS mode)

—

(Note 1)

0.7 VDD

0.9 VDD

50*

—

OSC1 (RC mode)

—

IPUR

IIL

PORTA Weak Pull-up Current

250

μA VDD = 5.0V, VPIN = VSS

(2)

Input Leakage Current

D060

I/O ports

—

0.1

1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

D060A

D060B

D061

Analog inputs

VREF

—

0.1

1

5

μA VSS ≤ VPIN ≤ VDD

(3)

MCLR

D063

OSC1

μA VSS ≤ VPIN ≤ VDD, XT, HS and

LP osc configuration

Output Low Voltage

I/O ports

D080

D083

VOL

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V

OSC2/CLKOUT (RC mode)

IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

Output High Voltage

I/O ports

D090

D092

VOH

VOD

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V

OSC2/CLKOUT (RC mode)

IOH = -1.3 mA, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

D193*

Open-Drain High Voltage

—

TBD

V

RB6 pin

Legend:

TBD = To Be Determined

These parameters are characterized but not tested.

*

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

DS41249B-page 150

Preliminary

PIC16F785

18.4 DC Characteristics: PIC16F785-I (Industrial), PIC16F785-E (Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

Sym

No.

Characteristic

Min

Typ†

Max

Units

Conditions

Capacitive Loading Specs on

Output Pins

D100

COSC2 OSC2 pin

—

15*

50*

pF In XT, HS and LP modes when

external clock is used to drive

OSC1

D101

D120

CIO

ED

All I/O pins

pF

Data EEPROM Memory

Byte Endurance

VDD for Read/Write

100K

10K

1M

100K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D120A ED

D121

VDRW

VMIN

5.5

V

Using EECON1 to read/write

VMIN = Minimum operating

voltage

D122

D123

TDEW

Erase/Write cycle time

—

5

6

ms

TRETD Characteristic Retention

40

—

Year Provided no other specifications

are violated

D124

TREF

Number of Total Erase/Write

Cycles before Refresh

1M

10M

—

E/W -40°C ≤ TA ≤ +85°C

(1)

Program Flash Memory

Cell Endurance

D130

EP

10K

1K

100K

10K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D130A EP

Cell Endurance

D131

VPR

VDD for Read

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132

D133

D134

VPEW

TPEW

VDD for Erase/Write

4.5

—

2

5.5

2.5

—

V

Erase/Write cycle time

ms

TRETD Characteristic Retention

40

—

Year Provided no other specifications

are violated

Legend:

TBD = To Be Determined

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external

clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

normal operating conditions. Higher leakage current may be measured at different input voltages.

Preliminary

DS41249B-page 151

PIC16F785

18.5 Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKOUT

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 18-2:

LOAD CONDITIONS

Load Condition 1

Load Condition 2

VDD/2

RL

CL

VSS

Legend:

RL = 464Ω

CL = 50 pF for all pins

15 pF for OSC2 output

FIGURE 18-3:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

Q1

OSC1

1

3

4

3

2

CLKOUT

DS41249B-page 152

Preliminary

PIC16F785

TABLE 18-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

Sym

Characteristic

Min Typ†

Max

Units

Conditions

No.

FOSC External CLKIN Frequency⁽¹⁾

—

32.768

—

kHz LP mode (complementary input

only)

DC

—

4

MHz XT mode

20

—

4

MHz HS mode

—

MHz EC mode

Oscillator Frequency⁽¹⁾

32.768

4

kHz LP Osc mode

MHz INTOSC mode

MHz RC Osc mode

MHz XT Osc mode

MHz HS Osc mode

—

DC

0.1

1

—

4

—

20

—

1

—

0.3052

μs LP mode (complementary input

TOSC

External CLKIN Period⁽¹⁾

only)

50

—

∞

ns HS Osc mode

ns EC Osc mode

ns XT Osc mode

250

Oscillator Period⁽¹⁾

—

0.3052

250

—

μs LP Osc mode

ns INTOSC mode

ns RC Osc mode

ns XT Osc mode

ns HS Osc mode

250

50

—

10,000

1,000

—

2

3

TCY

Instruction Cycle Time⁽¹⁾

200

TCY

—

DC

—

ns TCY = 4/FOSC

TosL, External CLKIN (OSC1) High 2*

TosH External CLKIN Low

μs LP oscillator, TOSC L/H duty cycle

ns HS oscillator, TOSC L/H duty cycle

ns XT oscillator, TOSC L/H duty cycle

ns LP oscillator

20*

100 *

—

4

TosR, External CLKIN Rise

TosF External CLKIN Fall

50*

25*

15*

—

ns XT oscillator

—

ns HS oscillator

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’

values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle

time limit is ‘DC’ (no clock) for all devices.

Preliminary

DS41249B-page 153

PIC16F785

TABLE 18-2:

Param

PRECISION INTERNAL OSCILLATOR PARAMETERS

Freq

Sym

Characteristic

Min

Typ†

Max Units

Conditions

No.

Tolerance

F10

FOSC

Internal Calibrated

1%

2%

7.92

7.84

8.00

8.08

8.16

MHz VDD = 3.5V, 25°C

MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

INTOSC Frequency⁽¹⁾

5%

7.60

8.00

8.40

MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

μs VDD = 2.0V, -40°C to +85°C

μs VDD = 3.0V, -40°C to +85°C

μs VDD = 5.0V, -40°C to +85°C

F14

TIOSCST Oscillator wake-up from

Sleep start-up time*

—

10.3

9.0

TBD

6.5

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1uF and 0.01uF values in parallel are recommended.

FIGURE 18-4:

CLKOUT AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

11

10

22

23

CLKOUT

13

12

19

18

14

16

I/O pin

(Input)

15

17

I/O pin

(Output)

New Value

Old Value

20, 21

TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

10

11

12

13

14

15

16

TOSH2CKL OSC1↑ to CLOUT↓

TOSH2CKH OSC1↑ to CLOUT↑

—

75

35

—

200

100

20

ns (Note 1)

TCKR

TCKF

CLKOUT rise time

CLKOUT fall time

TCKL2IOV CLKOUT↓ to Port out valid

TIOV2CKH Port in valid before CLKOUT↑

TCKH2IOI Port in hold after CLKOUT↑

These parameters are characterized but not tested.

TOSC + 200 ns

0

—

*

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

DS41249B-page 154

Preliminary

PIC16F785

TABLE 18-3: CLKOUT AND I/O TIMING REQUIREMENTS (CONTINUED)

Param

Sym

Characteristic

Min

Typ†

Max

Units Conditions

No.

17

TOSH2IOV OSC1↑ (Q1 cycle) to Port out valid

—

50

—

150 *

300

—

ns

18

19

TOSH2IOI OSC1↑ (Q2 cycle) to Port input

100

invalid (I/O in hold time)

TIOV2OSH Port input valid to OSC1↑

0

—

ns

(I/O in setup time)

20

21

22

23

TIOR

TIOF

TINP

TRBP

Port output rise time

Port output fall time

INT pin high or low time

—

10

—

40

—

ns

25

PORTA change INT high or low

time

TCY

*

These parameters are characterized but not tested.

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

†

FIGURE 18-5:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O Pins

Preliminary

DS41249B-page 155

PIC16F785

FIGURE 18-6:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

VBOR

(Device not in Brown-out Reset)

(Device in Brown-out Reset)

36

Reset (due to BOR)

(1)

64 ms time-out

Note 1: 64 ms delay only if PWRTE bit in Configuration Word is programmed to ‘0’.

TABLE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Param

No.

Sym

TMCL

Characteristic

Min

Typ†

Max Units

Conditions

30

MCLR Pulse Width (low)

2

11

—

18

—

μs VDD = 5.0V, -40°C to +85°C

24

ms Extended temperature

31

TWDT

TOST

Watchdog Timer Time-out

Period

(No Prescaler)

10

17

25

30

ms VDD = 5.0V, -40°C to +85°C

ms Extended temperature

32

33*

34

Oscillation Start-up Timer

Period

—

1024 TOSC

—

TOSC = OSC1 period

TPWRT Power-up Timer Period

28*

TBD

64

TBD

132*

TBD

ms VDD = 5.0V, -40°C to +85°C

ms Extended Temperature

TIOZ

I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

—

2.0

μs

35

36

VBOR

TBOR

Brown-out Reset Voltage

2.025

100*

—

2.175

—

V

Brown-out Reset Pulse Width

μs VDD ≤ VBOR (D005)

Legend: TBD = To Be Determined.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41249B-page 156

Preliminary

PIC16F785

FIGURE 18-7:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

49

47

TMR0 or

TMR1

TABLE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym

TT0H

Characteristic

T0CKI High Pulse Width

Min

Typ† Max Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale

value (2, 4, ...,

256)

45*

46*

47*

TT1H

TT1L

T1CKI High

Time

Synchronous, No Prescaler

0.5 TCY + 20

15

—

ns

Synchronous,

with Prescaler

Asynchronous

30

0.5 TCY + 20

15

—

ns

T1CKI Low Time Synchronous, No Prescaler

Synchronous,

with Prescaler

Asynchronous

30

—

ns

TT1P

FT1

T1CKI Input

Period

Synchronous

Greater of:

30 or TCY + 40

N

ns N = prescale

value (1, 2, 4,

8)

Asynchronous

60

—

ns

48

49

Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN)

DC

200*

kHz

TCKEZTMR1 Delay from external clock edge to timer increment

These parameters are characterized but not tested.

2 TOSC*

—

7 TOSC*

—

*

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Preliminary

DS41249B-page 157

PIC16F785

FIGURE 18-8:

CAPTURE/COMPARE/PWM TIMINGS (CCP)

CCP1

(Capture mode)

50

51

52

CCP1

(Compare or PWM mode)

53

Note: Refer to Figure 18-2 for load conditions.

54

TABLE 18-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP)

Param

Symbol

Characteristic

Min

Typ† Max Units Conditions

No.

50* TCCL

51* TCCH

52* TCCP

CCP1 input low time

No Prescaler

0.5TCY +

20

—

ns

With Prescaler

No Prescaler

20

—

ns

CCP1 input high time

CCP1 input period

0.5TCY +

20

With Prescaler

20

—

ns

3TCY + 40

N

ns N = prescale

value (1,4 or

16)

53* TCCR

54* TCCF

CCP1 output rise time

CCP1 output fall time

—

25

50

45

ns

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS41249B-page 158

Preliminary

PIC16F785

TABLE 18-7: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Comparator Specifications

Param

Symbol

No.

Characteristics

Min

Typ

Max

Units

Comments

C01

C02

C03

C04

VOS

VCM

ILC

Input Offset Voltage

—

0

5

—

TBD

VDD – 1.5

200*

mV

V

Input Common Mode Voltage

Input Leakage Current

—

nA

dB

CMRR

Common Mode Rejection

Ratio

+70*

—

C05

TRT

Response Time⁽¹⁾

—

20*

40*

ns

Internal

Output to pin

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from

VSS to VDD – 1.5V.

TABLE 18-8: COMPARATOR VOLTAGE REFERENCE (CVREF) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Comparator Voltage Reference Specifications

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Symbol

CVRES Resolution

Absolute Accuracy

Characteristics

Min

Typ

Max

Units

Comments

CV01

—

VDD/24*

VDD/32

—

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

CV02

—

1/4*

1/2*

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

CV03

CV04

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

2K*

—

Ω

10*

μs

*

These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from 0000to 1111.

TABLE 18-9: VOLTAGE REFERENCE (VR) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

VR Voltage Reference Specifications

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

3.0V ≤ VDD ≤ 5.5V

VR01

VR02

VROUT

VR voltage output

TBD

—

1.200

150

TBD

V

TCVOUT Voltage drift temperature

coefficient

ppm/°C

VR03

VR04

ΔVROUT/ Voltage drift with respect to

—

200

10

—

μV/V

μs

ΔVDD

VDD regulation

TSTABLE Settling Time

100*

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

Preliminary

DS41249B-page 159

PIC16F785

TABLE 18-10: VOLTAGE REFERENCE OUTPUT (VREF) BUFFER SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Voltage Reference Output Buffer Specifications Operating temperature -40°C ≤ TA ≤ +125°C

Operating voltage 3.0V ≤ VDD ≤ 5.5V

Param

No.

Symbol

Characteristics

Min

Typ

Max

Units

Comments

VB01*

VB02*

CL

External capacitor load

—

1

200

TBD

pF

ΔVOUT/ Load regulation

ΔIOUT

mV/mA VREF=1.2V, IREF= 1ma

VREF=0.5V, IREF= 1ma

1

VREF=3.6V, IREF= 1ma

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

TABLE 18-11: OPERATIONAL AMPLIFIER (OPA) MODULE DC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50pF,

RL = 100k

OPA DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym

Characteristics

Min

Typ

Max

Units

Comments

OPA01*

VOS

Input Offset Voltage

—

5

—

mV

Input current and impedance

Input bias current

Input offset bias current

OPA02*

OPA03*

IB

IOS

—

2*

1*

—

nA

pA

Common Mode

OPA04*

OPA05*

VCM

CMR

Common mode input range

Common mode rejection

VSS

TBD

—

70

VDD – 1.4

—

V

dB

VDD = 5.0V

VCM = VDD/2, Freq = DC

Open Loop Gain

DC Open loop gain

OPA06A* AOL

OPA06B* AOL

—

90

60

—

dB

No load

Standard load

Output

OPA07*

Vout

Output voltage swing

VSS+100

—

VDD – 100

mV To VDD/2 (20 kΩ

connected to VDD,

20 kΩ + 20 pF to Vss)

mA

OPA08*

OPA10

Isc

Output short circuit current

—

25

—

TBD

—

Power Supply

Power supply rejection

PSR

80

dB

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

DS41249B-page 160

Preliminary

PIC16F785

TABLE 18-12: OPERATIONAL AMPLIFIER (OPA) MODULE AC SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

VCM = 0V, VOUT = VDD/2, VDD = 5.0V, VSS = 0V, CL = 50 pF,

RL = 100k

OPA AC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C

Param

Symbol

Characteristics

Min

Typ

Max

Units

Comments

No.

OPA11* GBWP Gain bandwidth product

—

2

3

—

TBD

—

MHz

μs

OPA12* TON

OPA13* ΘM

OPA14* SR

Turn on time

Phase margin

Slew rate

10

60

—

deg

V/μs

—

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

TABLE 18-13: TWO-PHASE PWM DEAD TIME DELAY SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Dead Time Delay Characteristics

Param

Symbol

Characteristics

Min

Typ

Max

Units

Comments

No.

PW01* TDLY

Dead Time Delay

TBD

150

TBD

ns

Fosc = 4 MHz,

maximum delay,

Complementary mode

Legend: TBD = To Be Determined

These parameters are characterized but not tested.

*

Preliminary

DS41249B-page 161

PIC16F785

TABLE 18-14: PIC16F785 A/D CONVERTER CHARACTERISTICS:

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

A01

NR

Resolution

—

10 bits

bit

A03

A04

EIL

EDL

Integral Error

Differential Error

1

LSb VREF = 5.0V (external)

LSb No missing codes to 10 bits

VREF = 5.0V (external)

A05

A06

A07

A10

EFS

Full Scale Range

2.2*

—

5.5*

1

V

EOFF Offset Error

EGN Gain Error

—

LSb VREF = 5.0V (external)

—

guaranteed⁽²⁾

—

1

—

Monotonicity

—

V

VSS ≤ VAIN ≤ VREF

A20

VREF Reference Voltage 2.2⁽⁴⁾

—

A20A

1.0

VDD + 0.3

Absolute minimum to ensure 10-bit

accuracy

(5)

A25

A30

VAIN Analog Input

Voltage

VSS

—

VREF

V

ZAIN Recommended

Impedance of

Analog Voltage

Source

10

kΩ

A50

IREF VREF Input

Current*⁽³⁾

—

150

1

μA During VAIN acquisition.

Based on differential of VHOLD to

mA VAIN.

Transient during A/D conversion

cycle.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Total Absolute Error includes Integral, Differential, Offset and Gain Errors.

2: The A/D conversion result never decreases with an increase in the input voltage and has no missing

codes.

3: VREF current is from external VREF or VDD pin, whichever is selected as reference input.

4: Only limited when VDD is at or below 2.5V. If VDD is above 2.5V, VREF is allowed to go as low as 1.0V.

5: Analog input voltages are allowed up to VDD, however the conversion accuracy is limited to VSS to VREF.

DS41249B-page 162

Preliminary

PIC16F785

FIGURE 18-9:

PIC16F785 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

134

Q4

1 TCY

(1)

(TOSC/2)

131

130

A/D CLK

9

8

7

6

3

2

1

0

A/D DATA

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

TABLE 18-15: PIC16F785 A/D CONVERSION REQUIREMENTS

Param

No.

Sym

Characteristic

Min

Typ†

Max

Units

Conditions

130

TAD

A/D Clock Period

1.6

—

μs

TOSC-based, VREF ≥ 3.0V

3.0*

TOSC-based, VREF full range

130

TAD

A/D Internal RC

Oscillator Period

ADCS<1:0> = 11(RC mode)

At VDD = 2.5V

3.0*

2.0*

—

6.0

4.0

11

9.0*

6.0*

—

μs

At VDD = 5.0V

131

132

TCNV

TACQ

Conversion Time (not

including

Acquisition Time)

TAD Set GO bit to new data in A/D result

register

(1)

Acquisition Time

(Note 2)

11.5

—

μs

5*

μs

The minimum time is the amplifier settling

time. This may be used if the “new” input

voltage has not changed by more than 1

LSb (i.e., 4.1 mV @ 4.096V) from the last

sampled voltage (as stored on CHOLD).

134

TGO

Q4 to A/D Clock Start

—

TOSC/2

—

If the A/D clock source is selected as

RC, a time of TCY is added before the

A/D clock starts. This allows the SLEEP

instruction to be executed.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are

not tested.

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Table 12-2 for minimum conditions.

Preliminary

DS41249B-page 163

PIC16F785

FIGURE 18-10:

PIC16F785 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

134

(1)

(TOSC/2 + TCY)

1 TCY

131

Q4

130

A/D CLK

9

8

7

3

2

1

0

6

A/D DATA

NEW_DATA

1 TCY

OLD_DATA

ADRES

ADIF

GO

DONE

SAMPLING STOPPED

132

SAMPLE

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This

allows the SLEEPinstruction to be executed.

TABLE 18-16: PIC16F785 A/D CONVERSION REQUIREMENTS (SLEEP MODE)

Param

Sym

Characteristic

Min

Typ†

Max Units

Conditions

No.

130

TAD

A/D Internal RC

Oscillator Period

ADCS<1:0> = 11(RC mode)

μs At VDD = 2.5V

3.0*

2.0*

—

6.0

4.0

11

9.0*

6.0*

—

μs At VDD = 5.0V

131

132

TCNV

TACQ

Conversion Time

(not including

TAD

Acquisition Time)⁽¹⁾

Acquisition Time

(Note 2)

11.5

—

μs

5*

μs The minimum time is the amplifier

settling time. This may be used if

the “new” input voltage has not

changed by more than 1 LSb (i.e.,

4.1 mV @ 4.096V) from the last

sampled voltage (as stored on

CHOLD).

134

TGO

Q4 to A/D Clock

Start

—

TOSC/2 + TCY

—

If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEPinstruction to be

executed.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Table 12-1 for minimum conditions.

DS41249B-page 164

Preliminary

PIC16F785

19.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs are not available at this time.

Preliminary

DS41249B-page 165

PIC16F785

NOTES:

DS41249B-page 166

Preliminary

PIC16F785

20.0 PACKAGING INFORMATION

20.1 Package Marking Information

20-Lead PDIP

Example

XXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F785-I/P

0410017

20-Lead SOIC (.300”)

XXXXXXXXXXXXXX

PIC16F785

-E/SO

0410017

YYWWNNN

20-Lead SSOP

Example

XXXXXXXXXXX

PIC16F785

-I/SS

0410017

YYWWNNN

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Preliminary

DS41249B-page 167

PIC16F785

20.2 Package Details

The following sections give the technical details of the

packages.

20-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)

E1

D

2

α

n

1

E

A2

A

L

c

A1

β

B1

eB

p

B

Units

INCHES*

NOM

20

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

20

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.140

.155

.130

.170

3.56

2.92

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.295

.240

1.025

.120

.008

.055

.014

.310

5

.145

3.68

0.38

7.49

6.10

26.04

3.05

0.20

1.40

0.36

7.87

5

.310

.250

1.033

.130

.012

.060

.018

.370

10

.325

.260

1.040

.140

.015

.065

.022

.430

15

7.87

6.35

26.24

3.30

0.29

1.52

0.46

9.40

10

8.26

6.60

26.42

3.56

0.38

1.65

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-019

DS41249B-page 168

Preliminary

PIC16F785

20-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

A1

L

Units

INCHES*

NOM

20

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

20

MAX

n

p

Number of Pins

Pitch

.050

.099

.091

.008

.407

.295

.504

.020

.033

4

1.27

Overall Height

A

.093

.088

.004

.394

.291

.496

.010

.016

0

.104

2.36

2.50

2.31

0.20

10.34

7.49

12.80

0.50

0.84

4

2.64

Molded Package Thickness

Standoff

A2

A1

E

.094

.012

.420

.299

.512

.029

.050

8

2.24

0.10

10.01

7.39

12.60

0.25

0.41

0

2.39

0.30

10.67

7.59

13.00

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-094

Preliminary

DS41249B-page 169

PIC16F785

20-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)

DS41249B-page 170

Preliminary

PIC16F785

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PICmicro^®

DEVICES

Revision A

This discusses some of the issues in migrating from the

PIC16F684 PICmicro device to the PIC16F785.

This is a new data sheet.

Revision B

B.1

TABLE B-1:

Feature

PIC16F684 to PIC16F785

FEATURE COMPARISON

Updates throughout document.

PIC16F684

PIC16F785

Max Operating Speed

20 MHz

2048

20 MHz

2048

Max Program

Memory (Words)

SRAM (bytes)

A/D Resolution

128

10-bit

256

128

10-bit

256

Data EEPROM

(bytes)

Timers (8/16-bit)

Oscillator modes

Brown-out Reset

Internal Pull-ups

2/1

8

2/1

8

Y

RA0/1/2/4/5 RA0/1/2/3/4/5

MCLR MCLR

Interrupt-on-change RA0/1/2/3/4/5 RA0/1/2/3/4/5

Comparator

CCP

2

ECCP

Y

Op Amps

PWM

N

Y

2

Two-Phase

N

Ultra Low-Power

Wake-up

Extended WDT

Y

Software Control

Option of WDT/BOR

INTOSC Frequencies

Clock Switching

32 kHz -

8 MHz

32 kHz -

8 MHz

Y

Preliminary

DS41249B-page 171

PIC16F785

NOTES:

DS41249B-page 172

Preliminary

PIC16F785

INDEX

RC2 and RC3 Pins ..................................................... 47

RC4 Pin ...................................................................... 47

RC5 Pin ...................................................................... 48

Resonator Operation .................................................. 25

Timer1 ........................................................................ 51

Timer2 ........................................................................ 56

TMR0/WDT Prescaler ................................................ 49

Two-Phase PWM

A

A/D...................................................................................... 79

Acquisition Requirements ........................................... 86

Analog Port Pins ......................................................... 80

Associated Registers .................................................. 89

Block Diagram............................................................. 79

Calculating Acquisition Time....................................... 86

Channel Selection....................................................... 80

Configuration and Operation....................................... 80

Configuring.................................................................. 85

Configuring Interrupt ................................................... 85

Conversion Clock........................................................ 80

Effects of Reset........................................................... 89

Internal Sampling Switch (RSS) Impedance................ 86

Operation During Sleep .............................................. 88

Output Format............................................................. 81

Reference Voltage (VREF)........................................... 80

Source Impedance...................................................... 86

Special Event Trigger.................................................. 89

Specifications............................................ 162, 163, 164

Starting a Conversion ................................................. 81

Using the ECCP Trigger ............................................. 89

Absolute Maximum Ratings .............................................. 143

AC Characteristics

Complementary Output Mode .......................... 100

Simplified Diagram ............................................. 92

Single Phase Example ....................................... 98

VR Reference............................................................. 74

Watchdog Timer (WDT)............................................ 121

Brown-out Reset (BOR).................................................... 110

Associated registers ................................................. 112

Calibration ................................................................ 111

Specifications ........................................................... 156

Timing and Characteristics....................................... 156

C

C Compilers

MPLAB C17.............................................................. 138

MPLAB C18.............................................................. 138

MPLAB C30.............................................................. 138

Capture Module. See Capture/Compare/PWM (CCP)

Capture/Compare/PWM (CCP) .......................................... 57

Associated Registers.................................................. 62

Associated registers w/ Capture/Compare/Timer1..... 59

Capture Mode............................................................. 58

CCP1 Pin Configuration ............................................. 58

Compare Mode........................................................... 58

CCP1 Pin Configuration ..................................... 59

Software Interrupt Mode..................................... 59

Special Event Trigger and A/D Conversions ...... 59

Timer1 Mode Selection....................................... 59

Prescaler .................................................................... 58

PWM Mode................................................................. 60

Duty Cycle .......................................................... 61

Effects of Reset.................................................. 62

Example PWM Frequencies and Resolutions .... 61

Operation in Power Managed Modes................. 62

Operation with Fail-Safe Clock Monitor.............. 62

Setup for Operation ............................................ 62

Setup for PWM Operation .................................. 62

Specifications ........................................................... 158

Timer Resources ........................................................ 57

CCP. See Capture/Compare/PWM (CCP)

Load Conditions........................................................ 152

ADCON0 Register............................................................... 83

ADCON1 Register............................................................... 84

Analog-to-Digital Converter. See A/D

ANSEL Register.............................................. 93, 94, 96, 100

ANSEL0 Register................................................................ 82

ANSEL1 Register................................................................ 82

Assembler

MPASM Assembler................................................... 137

B

Block Diagrams

(CCP) Capture Mode Operation ................................. 58

A/D.............................................................................. 79

Analog Input Model..................................................... 87

CCP PWM................................................................... 60

Clock Source............................................................... 23

Comparator 1.............................................................. 64

Comparator 2.............................................................. 66

Compare ..................................................................... 58

CVref........................................................................... 71

Fail-Safe Clock Monitor (FSCM)................................. 31

In-Circuit Serial Programming Connections.............. 125

Interrupt Logic........................................................... 118

On-Chip Reset Circuit............................................... 109

OPA Module................................................................ 75

PIC16F684.................................................................... 5

RA0 Pin....................................................................... 38

RA1 Pin....................................................................... 38

RA2 Pin....................................................................... 39

RA3 Pin....................................................................... 39

RA4 Pin....................................................................... 40

RA5 Pin....................................................................... 40

RB4 and RB5 Pins...................................................... 43

RB6 Pin....................................................................... 43

RB7 Pin....................................................................... 43

RC0 and RC1 Pins...................................................... 43

RC0, RC6 and RC7 Pins ............................................ 46

RC1 Pin....................................................................... 46

CCP1CON Register............................................................ 57

CCPR1H Register............................................................... 57

CCPR1L Register ............................................................... 57

Clock Sources..................................................................... 23

CM1CON0 .......................................................................... 65

CM2CON1 .......................................................................... 68

Code Examples

Assigning Prescaler to Timer0.................................... 50

Assigning Prescaler to WDT....................................... 50

Changing Between Capture Prescalers ..................... 58

Data EEPROM Read................................................ 105

Data EEPROM Write................................................ 105

EEPROM Write Verify .............................................. 105

Indirect Addressing..................................................... 22

Initializing A/D............................................................. 85

Initializing PORTA ...................................................... 35

Initializing PORTB ...................................................... 42

Preliminary

DS41249B-page 173

PIC16F785

Initializing PORTC.......................................................45

Interrupt Context Saving ...........................................120

Code Protection ................................................................125

Comparator Module ............................................................63

Associated registers....................................................74

C1 Output State Versus Input Conditions...................63

C2 Output State Versus Input Conditions...................66

Comparator Interrupts.................................................69

Effects of Reset...........................................................69

Comparator Voltage Reference (CVREF)

F

Fail-Safe Clock Monitor ...................................................... 31

Fail-Safe Condition Clearing....................................... 32

Reset and Wake-up from Sleep.................................. 32

Firmware Instructions ....................................................... 127

Fuses. See Configuration Bits

G

General Purpose Register File ............................................. 9

I

Specifications............................................................159

Comparators

ID Locations...................................................................... 125

In-Circuit Debugger........................................................... 126

In-Circuit Serial Programming (ICSP)............................... 125

Indirect Addressing, INDF and FSR registers..................... 22

Instruction Format............................................................. 127

Instruction Set................................................................... 127

ADDLW..................................................................... 129

ADDWF..................................................................... 129

ANDLW..................................................................... 129

ANDWF..................................................................... 129

BCF .......................................................................... 129

BSF........................................................................... 129

BTFSC...................................................................... 129

BTFSS ...................................................................... 129

CALL......................................................................... 130

CLRF ........................................................................ 130

CLRW ....................................................................... 130

CLRWDT .................................................................. 130

COMF ....................................................................... 130

DECF........................................................................ 130

DECFSZ ................................................................... 130

GOTO ....................................................................... 131

INCF ......................................................................... 131

INCFSZ..................................................................... 131

IORLW...................................................................... 131

IORWF...................................................................... 131

MOVF ....................................................................... 131

MOVLW .................................................................... 132

MOVWF.................................................................... 132

NOP.......................................................................... 132

RETFIE..................................................................... 132

RETLW ..................................................................... 133

RETURN................................................................... 133

RLF........................................................................... 133

RRF .......................................................................... 134

SLEEP ...................................................................... 134

SUBLW..................................................................... 134

SUBWF..................................................................... 135

SWAPF..................................................................... 135

TRIS ......................................................................... 135

XORLW .................................................................... 136

XORWF .................................................................... 136

Summary Table ........................................................ 128

INTCON Register................................................................ 17

Internal Oscillator Block

C2OUT as T1 Gate .....................................................52

Specifications............................................................159

Compare Module. See Capture/Compare/PWM (CCP)

CONFIG Register..............................................................108

Configuration Bits..............................................................107

CPU Features ...................................................................107

Customer Change Notification Service .................................1

Customer Support.................................................................1

D

Data EEPROM Memory

Associated registers..................................................106

Code Protection ................................................ 103, 106

Data Memory.........................................................................9

DC Characteristics

Extended and Industrial ............................................150

Industrial and Extended ............................................145

Demonstration Boards

PICDEM 1 .................................................................140

PICDEM 17 ...............................................................141

PICDEM 18R ............................................................141

PICDEM 2 Plus.........................................................140

PICDEM 3 .................................................................140

PICDEM 4 .................................................................140

PICDEM LIN .............................................................141

PICDEM USB............................................................141

PICDEM.net Internet/Ethernet ..................................140

Development Support .......................................................137

Device Overview ...................................................................5

E

EEADR Register ...............................................................103

EECON1 Register.............................................................104

EECON2 Register.............................................................104

EEDAT Register................................................................103

EEPROM Data Memory

Avoiding Spurious Write............................................105

Reading.....................................................................105

Write Verify ...............................................................105

Writing.......................................................................105

Effects of Reset

A/D module .................................................................89

Comparator module ....................................................69

OPA module................................................................77

PWM mode .................................................................62

Electrical Specifications ....................................................143

Errata ....................................................................................3

Evaluation and Programming Tools..................................141

INTOSC

Specifications ................................................... 154

Internal Sampling Switch (RSS) Impedance........................ 86

Internet Address ................................................................... 1

Interrupts........................................................................... 117

(CCP) Compare.......................................................... 58

A/D.............................................................................. 85

Associated registers ................................................. 119

Comparator................................................................. 69

DS41249B-page 174

Preliminary

PIC16F785

Context Saving.......................................................... 120

Data EEPROM Memory Write .................................. 104

Interrupt-on-change .................................................... 37

Oscillator Fail (OSF) ................................................... 31

PORTA Interrupt-on-change..................................... 118

RA2/INT .................................................................... 118

TMR0 ........................................................................ 118

TMR1 .......................................................................... 52

TMR2 to PR2 Match ............................................. 55, 56

INTOSC Specifications ..................................................... 154

IOCA (Interrupt-on-Change) ............................................... 37

IOCA Register..................................................................... 37

PIR1 Register ..................................................................... 19

PORTA ............................................................................... 35

Additional Pin Functions............................................. 36

Interrupt-on-change............................................ 37

Weak Pull-up ...................................................... 36

Associated registers ................................................... 41

Pin Descriptions and Diagrams .................................. 38

RA0............................................................................. 38

RA1............................................................................. 38

RA2............................................................................. 39

RA3............................................................................. 39

RA4............................................................................. 40

RA5............................................................................. 40

Specifications ........................................................... 154

PORTB ............................................................................... 42

Associated registers ................................................... 44

Pin Descriptions and Diagrams .................................. 43

RB4............................................................................. 43

RB5............................................................................. 43

RB6............................................................................. 43

RB7............................................................................. 43

PORTC ............................................................................... 45

Associated registers ............................................. 33, 48

Pin Descriptions and Diagrams .................................. 46

RC0 ............................................................................ 46

RC1 ............................................................................ 46

RC2 ............................................................................ 47

RC3 ............................................................................ 47

RC4 ............................................................................ 47

RC5 ............................................................................ 48

RC6 ............................................................................ 46

RC7 ............................................................................ 46

Specifications ........................................................... 154

Power-Down Mode (Sleep)............................................... 123

Power-up Timer (PWRT).................................................. 110

Specifications ........................................................... 156

Power-up Timing Delays................................................... 112

Precision Internal Oscillator Parameters .......................... 154

Prescaler

L

Load Conditions................................................................ 152

M

MCLR................................................................................ 110

Internal...................................................................... 110

Memory Organization............................................................ 9

Data .............................................................................. 9

Data EEPROM Memory............................................ 103

Program ........................................................................ 9

Microchip Internet Web Site.................................................. 1

Migrating from other PICmicro Devices ............................ 171

MPLAB ASM30 Assembler, Linker, Librarian ................... 138

MPLAB ICD 2 In-Circuit Debugger ................................... 139

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator .................................................... 139

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator .................................................... 139

MPLAB Integrated Development Environment Software .. 137

MPLAB PM3 Device Programmer .................................... 139

MPLINK Object Linker/MPLIB Object Librarian ................ 138

O

OPA2CON Register ............................................................ 76

OPCODE Field Descriptions............................................. 127

Operational Amplifier (OPA) Module................................... 75

AC Specifications...................................................... 161

Associated Registers .................................................. 77

DC Specifications...................................................... 161

OPTION_REG Register ...................................................... 16

OSCCON Register.............................................................. 33

Oscillator

Associated registers.................................................... 33

Oscillator Specifications.................................................... 153

Oscillator Start-up Timer (OST)

Specifications............................................................ 156

Oscillator Switching

Shared WDT/Timer0................................................... 50

Switching Prescaler Assignment ................................ 50

PRO MATE II Universal Device Programmer................... 139

Product Identification ........................................................ 175

Program Memory.................................................................. 9

Map and Stack.............................................................. 9

Programming, Device Instructions.................................... 127

PWM. See Two-Phase PWM

PWMCLK Register.............................................................. 94

PWMCON0 Register........................................................... 93

PWMCON1 Register......................................................... 100

PWMPH1 Register.............................................................. 95

PWMPH2 Register.............................................................. 96

Fail-Safe Clock Monitor............................................... 31

Two-Speed Clock Start-up.......................................... 30

P

R

Packaging ......................................................................... 167

Marking ..................................................................... 167

PDIP Details.............................................................. 168

PCL and PCLATH............................................................... 21

Stack........................................................................... 21

PCON Register ................................................................. 112

PICkit 1 Flash Starter Kit................................................... 141

PICSTART Plus Development Programmer ..................... 140

PIE1 Register...................................................................... 18

Pin Diagram .......................................................................... 2

Pinout Descriptions

Reader Response................................................................. 2

Read-Modify-Write Operations ......................................... 127

REFCON (VR control) ........................................................ 73

Register

IOCA (Interrupt-on-Change)....................................... 37

WPUA (Weak Pull-up PORTA)................................... 36

Registers

ADCON0 (A/D Control 0)............................................ 83

ADCON1 (A/D Control 1)............................................ 84

ANSEL (Analog Select) .......................... 93, 94, 96, 100

ANSEL0 (Analog Select 0) ......................................... 82

ANSEL1 (Analog Select 1) ......................................... 82

PIC16F684.................................................................... 6

Preliminary

DS41249B-page 175

PIC16F785

CCP1CON (CCP Operation).......................................57

CCPR1H .....................................................................57

CCPR1L......................................................................57

CM1CON0 (C1 Control)..............................................65

CM1CON0 (C2 Control)

Prescaler .................................................................... 50

Specifications ........................................................... 157

Timer1................................................................................. 51

Associated registers ................................................... 54

Asynchronous Counter Mode ..................................... 54

Reading and Writing........................................... 54

Interrupt ...................................................................... 52

Modes of Operations .................................................. 52

Operation During Sleep .............................................. 54

Oscillator..................................................................... 54

Prescaler .................................................................... 52

Specifications ........................................................... 157

Timer1 Gate

Inverting Gate..................................................... 52

Selecting Source ................................................ 52

TMR1H Register......................................................... 51

TMR1L Register.......................................................... 51

Timer2................................................................................. 55

Associated registers ................................................... 56

Operation.................................................................... 55

Postscaler................................................................... 55

PR2 Register .............................................................. 55

Prescaler .................................................................... 55

TMR2 Register............................................................ 55

TMR2 to PR2 Match Interrupt............................... 55, 56

Timing Diagrams

CM2CON0 ..........................................................67

CM2CON1 (C2 control)...............................................68

CONFIG (Configuration Word)..................................108

Data Memory Map ......................................................10

EEADR (EEPROM Address) ....................................103

EECON1 (EEPROM Control 1).................................104

EECON2 (EEPROM Control 2).................................104

EEDAT (EEPROM Data) ..........................................103

INTCON (Interrupt Control).........................................17

IOCA (Interrupt-on-change PORTA)...........................37

Op Amp 2 Control Register (OPA2CON)....................76

OPTION_REG (Option) ..............................................16

OSCCON (Oscillator Control) .....................................33

PCON (Power Control) .............................................112

PIE1 (Peripheral Interrupt Enable 1)...........................18

PIR1 (Peripheral Interrupt Register 1) ........................19

PORTA........................................................................35

PORTB........................................................................42

PORTC .......................................................................45

PWMCLK (PWM clock control) ...................................94

PWMCON0 (PWM control 0) ......................................93

PWMCON1 (PWM control 1) ....................................100

PWMPH1 (PWM Phase 1 control) ..............................95

PWMPH2 (PWM Phase 2 control) ..............................96

REFCON (VR control).................................................73

Reset Values.............................................................114

Reset Values (special registers) ...............................116

Special Function registers.............................................9

Special Register Summary ............................. 12, 13, 14

Status..........................................................................15

T1CON (Timer1 Control).............................................53

T2CON (Timer2 Control).............................................55

TRISA (Tri-state PORTA) ...........................................36

TRISB (Tri-state PORTB) ...........................................42

TRISC (Tri-state PORTC) ...........................................45

WDTCON (Watchdog Timer Control)........................122

WPUA (Weak Pull-up PORTA)...................................36

Resets...............................................................................109

Power-On Reset .......................................................110

Revision History ................................................................171

RRF Instruction .................................................................134

A/D Conversion......................................................... 163

A/D Conversion (Sleep Mode).................................. 164

Brown-out Reset (BOR)............................................ 156

Brown-out Reset Situations ...................................... 111

Capture/Compare/PWM (CCP) ................................ 158

CLKOUT and I/O ...................................................... 154

External Clock........................................................... 152

Fail-Safe Clock Monitor (FSCM)................................. 32

INT Pin Interrupt ....................................................... 119

Reset, WDT, OST and Power-up Timer................... 155

Time-out Sequence

Case 1 .............................................................. 113

Case 2 .............................................................. 113

Case 3 .............................................................. 113

Timer0 and Timer1 External Clock ........................... 157

Timer1 Incrementing Edge ......................................... 52

Two-Phase PWM

Complementary Output .................................... 101

Start-up............................................................... 97

Two-Speed Start-up.................................................... 31

Two-Phase PWM

S

Auto-Shutdown................................................... 97

Wake-up from Interrupt............................................. 124

Timing Parameter Symbology .......................................... 152

TRIS Instruction................................................................ 135

TRISA Register................................................................... 36

TRISB Register................................................................... 42

TRISC Register................................................................... 45

Two-Phase PWM................................................................ 91

Activating .................................................................... 91

Active Output Level .................................................... 92

Associated registers ................................................. 101

Auto-shutdown............................................................ 92

Clock control (PWMCLK)............................................ 94

Control Register 0 (PWMCON0)................................. 93

Control Register 1 (PWMCON1)............................... 100

Master/Slave Operation.............................................. 91

Output Blanking .......................................................... 91

Phase 1 control (PWMPH1)........................................ 95

SLEEP Instruction.............................................................134

Software Simulator (MPLAB SIM).....................................138

Software Simulator (MPLAB SIM30).................................138

Special Event Trigger..........................................................89

Special Function registers.....................................................9

Specifications....................................................................162

STATUS Register................................................................15

SUBLW Instruction............................................................134

SUBWF Instruction............................................................135

SWAPF Instruction............................................................135

T

Time-out Sequence...........................................................112

Timer0.................................................................................49

Associated registers....................................................50

External Clock.............................................................50

Interrupt.......................................................................49

Operation ....................................................................49

DS41249B-page 176

Preliminary

PIC16F785

Phase 2 control (PWMPH1)........................................ 96

PWM Duty Cycle......................................................... 91

PWM Frequency ......................................................... 91

PWM Period................................................................ 91

PWM Phase................................................................ 91

PWM Phase resolution ............................................... 91

Shutdown.................................................................... 92

Two-Phase PWM

Dead Time Delay ...................................................... 162

Two-Speed Clock Start-up Mode........................................ 30

V

Voltage Reference (VR)

Specifications............................................................ 160

Voltage Reference Output (VREF) BUFFER

Specifications............................................................ 160

Voltage References ............................................................ 71

Associated registers.................................................... 74

Configuring CVref ....................................................... 71

CVref (Comparator Reference)................................... 71

CVref Accuracy........................................................... 71

Fixed VR reference..................................................... 73

VR Stabilization........................................................... 74

VREF. SEE A/D Reference Voltage

W

Wake-up Using Interrupts ................................................. 123

Watchdog Timer (WDT) .................................................... 121

Associated registers.................................................. 122

Clock Source............................................................. 121

Modes ....................................................................... 121

Period........................................................................ 121

Specifications............................................................ 156

WDTCON Register ........................................................... 122

WPUA (Weak Pull-up PORTA)........................................... 36

WPUA Register................................................................... 36

WWW Address...................................................................... 1

WWW, On-Line Support ....................................................... 3

X

XORLW Instruction ........................................................... 136

XORWF Instruction ........................................................... 136

Preliminary

DS41249B-page 177

PIC16F785

NOTES:

DS41249B-page 178

Preliminary

PIC16F785

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

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software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

In addition, there is

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Development Systems

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Microchip’s development systems software products.

This line also provides information on how customers

can receive currently available upgrade kits.

The Development Systems Information Line

numbers are:

CUSTOMER CHANGE NOTIFICATION

SERVICE

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Microchip’s customer notification service helps keep

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will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS41249B-page 179

PIC16F785

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Application (optional):

Would you like a reply?

Y

N

PIC16F785

DS41249B

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41249B-page 180

Preliminary

PIC16F785

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature Package

Range

Pattern

a)

PIC16F785 – E/P 301 = Extended Temp., PDIP

package, 20 MHz, QTP pattern #301

PIC16F785 – I/SO = Industrial Temp., SOIC

package, 20 MHz

b)

Device:

PIC16F785, PIC16F785T⁽¹⁾

:

Temperature Range:

Package:

I

E

=

-40°C to +85°C

-40°C to +125°C

P

SO

SS

=

PDIP

SOIC (Gull wing, 300 mil body)

SSOP(5.3 mm)

Pattern:

3-Digit Pattern Code for QTP (blank otherwise)

Note 1: T = in tape and reel SOIC, and SSOP

packages only.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Preliminary

DS41249B-page 181

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

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Tel: 61-2-9868-6733

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Technical Support:

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Web Address:

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Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

04/20/05

DS41249B-page 182

Preliminary


型号：	PIC16F785-I/P
厂家：	MICROCHIP
描述：	20-Pin Flash-Based, 8-Bit CMOS Microcontroller with Two-Phase Asynchronous Feedback PWM Dual High-Speed Comparators and Dual Operational Amplifiers 20引脚基于闪存的8位CMOS微控制器，带有两相异步反馈PWM双高速比较器和双通道运算放大器闪存比较器微控制器和处理器外围集成电路运算放大器光电二极管 PC 时钟
文件：	总184页 (文件大小：3445K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F785-I/P [MICROCHIP]

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