PIC16F88_技术文档

PIC16F87/88

M

This document includes programming specifications

for the following devices:

• PIC16F87

• PIC16F88

Flash Memory Programming Specification

Both algorithms can be used with the two available

programming entry methods. The first method, called

Low-Voltage ICSP^TM(LVP for short), applies VDD to

MCLR and uses the I/O pin RB3 to enter Programming

mode. When RB3 is driven to VDD from ground, the

PIC16F87/88 device enters Programming mode. The

second method follows the normal Microchip

Programming mode entry of holding pins RB6 and RB7

low, while raising the MCLR pin from VIL to VIHH

(13V ± 0.5V).

1.0

DEVICE OVERVIEW

2.0

PROGRAMMING THE

PIC16F87/88

The PIC16F87/88 is programmed using a serial

method. The Serial mode will allow the PIC16F87/88 to

be programmed while in the user’s system, which

allows for increased design flexibility. This

programming specification applies to PIC16F87/88

devices in all packages.

2.2

Programming Mode

The Programming mode for the PIC16F87/88 allows

programming of user program memory, data memory,

special locations used for ID, and the configuration

words.

2.1

Programming Algorithm

Requirements

The programming algorithm used depends on the

operating voltage (VDD) of the PIC16F87/88 device.

Algorithm #

VDD Range

1

2

2.0V ≤ VDD < 5.5V

4.5V ≤ VDD ≤ 5.5V

FIGURE 2-1:

PIC16F87 18-PIN DIP, SOIC

RA2/AN2/CVREF

RA3/AN3/C1OUT

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

RA1/AN1

RA0/AN0

RA4/T0CKI/C2OUT

RA5/MCLR/VPP

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

VSS

(1)

RB0/INT/CCP1

RB7/PGD/T1OSI

RB1/SDI/SDA

RB6/PGC/T1OSO/T1CKI

RB5/SS/TX/CK

RB2/SDO/RX/DT

(1)

RB3/PGM/CCP1

RB4/SCK/SCL

Note 1: Location of CCP1 function is determined by CCPMX.

2002 Microchip Technology Inc.

DS39607B-page 1

PIC16F87/88

FIGURE 2-2:

PIC16F87 20-PIN SSOP

RA2/AN2/CVREF

RA3/AN3/C1OUT

RA1/AN1

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

RA0/AN0

RA4/T0CKI/C2OUT

RA5/MCLR/VPP

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

VSS

AVSS

AVDD

(1)

RB7/PGD/T1OSI

RB0/INT/CCP1

RB6/PGC/T1OSO/T1CKI

RB5/SS/TX/CK

RB1/SDI/SDA

RB2/SDO/RX/DT

9

12

11

(1)

RB4/SCK/SCL

RB3/PGM/CCP1

10

Note 1: Location of CCP1 function is determined by CCPMX.

FIGURE 2-3:

PIC16F87 28-PIN QFN

RA5/MCLR/VPP

1

21

20

19

18

17

16

15

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

NC

VSS

NC

2

3

4

5

6

7

PIC16F87

AVSS

NC

AVDD

RB7/PGD/T1OSI

RB6/PGC/T1OSO/T1CKI

RB0/INT/CCP1⁽¹⁾

Note 1: Location of CCP1 function is determined by CCPMX.

DS39607B-page 2

2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 2-4:

PIC16F88 18-PIN DIP, SOIC

RA2/AN2/CVREF/VREF-

RA3/AN3/VREF+/C1OUT

1

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

11

10

RA1/AN1

RA0/AN0

RA4/AN4/T0CKI/C2OUT

RA5/MCLR/VPP

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

VSS

(1)

RB0/INT/CCP1

RB7/AN6/PGD/T1OSI

RB1/SDI/SDA

RB6/AN5/PGC/T1OSO/T1CKI

RB5/SS/TX/CK

RB2/SDO/RX/DT

(1)

RB3/PGM/CCP1

RB4/SCK/SCL

Note 1: Location of CCP1 function is determined by CCPMX.

FIGURE 2-5:

PIC16F88 20-PIN SSOP

RA2/AN2/CVREF/VREF-

RA1/AN1

1

2

3

4

5

6

7

8

20

19

18

17

16

15

14

13

RA3/AN3/VREF+/C1OUT

RA0/AN0

RA4/AN4/T0CKI/C2OUT

RA5/MCLR/VPP

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

VSS

AVSS

AVDD

(1)

RB7/AN6/PGD/T1OSI

RB0/INT/CCP1

RB6/AN5/PGC/T1OSO/T1CKI

RB5/SS/TX/CK

RB1/SDI/SDA

RB2/SDO/RX/DT

9

12

11

(1)

RB3/PGM/CCP1

RB4/SCK/SCL

10

Note 1: Location of CCP1 function is determined by CCPMX.

2002 Microchip Technology Inc.

DS39607B-page 3

PIC16F87/88

FIGURE 2-6:

PIC16F88 28-PIN QFN

RA5/MCLR/VPP

21

20

19

18

17

16

15

1

2

3

4

5

6

7

RA7/OSC1/CLKI

RA6/OSC2/CLKO

VDD

NC

VSS

NC

PIC16F88

AVSS

NC

AVDD

RB7/AN6/PGD/T1OSI

RB6/AN5/PGC/T1OSO/T1CKI

(1)

RB0/INT/CCP1

Note 1: Location of CCP1 function is determined by CCPMX.

TABLE 2-1:

Pin Name

RB3

PIN DESCRIPTIONS (DURING PROGRAMMING): PIC16F87/88

During Programming

Function

Pin Type

Pin Description

PGM

I

Low-Voltage ICSP Programming Input if LVP

Configuration bit equals ‘1’

RB6

RB7

MCLR

VDD

CLOCK

DATA

VPP

VDD

VSS

I

Clock Input

I/O

P*

P

Data Input/Output

Program Mode Select

Power Supply

Ground

VSS

P

Legend: I = Input, O = Output, P = Power

*

To activate the Programming mode, high voltage needs to be applied to the MCLR input. Since MCLR is

used for a level source, this means that MCLR does not draw any significant current.

DS39607B-page 4

2002 Microchip Technology Inc.

PIC16F87/88

3.2

Data EEPROM Memory

3.0

3.1

PROGRAM MODE ENTRY

User Program Memory Map

The EEPROM data memory space is a separate block

of high-endurance memory that the user accesses

using a special sequence of instructions. The amount

of data EEPROM memory depends on the device and

is shown below in number-of-bytes.

The user memory space extends from 0x0000 to

0x1FFF (8K), of which 4K (0000h-0FFFh) is physically

implemented. In Programming mode, the program

memory space extends from 0x0000 to 0x3FFF, with

the first half (0x0000-0x1FFF) being user program

memory and the second half (0x2000-0x3FFF) being

configuration memory. The PC will increment from

0x0000 to 0x0FFF, then increment to 0x1000 and

access 0x0000. Once the PC reaches 0x1FFF, it will

increment to 0x2000. From 0x2000, the PC will

increment up to 0x3FFF and wrap around to 0x2000

(not to 0x0000). Once in configuration memory, the

highest bit of the PC stays a ‘1’, always pointing to the

configuration memory. The only way to point to user

program memory is to reset the part and re-enter

Program mode, as described in Section 3.4 “Program

Mode”.

Device

# of Bytes

PIC16F87

PIC16F88

256

The contents of data EEPROM memory have the

capability to be embedded into the HEX file.

The programmer should be able to read data EEPROM

information from a HEX file and conversely (as an

option) write data EEPROM contents to a HEX file,

along with program memory information and

configuration bit information.

The 256 data memory locations are logically mapped

and use PC<7:0>. The format for data memory storage

is one data byte per address location, LSb aligned.

Device

Program Flash

PIC16F87

PIC16F88

4K

In the configuration memory space, 0x2000-0x201F

are physically implemented. However, only locations

0x2000 through 0x2008 are available. Other locations

are reserved. Locations beyond 0x201F will physically

access user memory (see Figure 3-1).

2002 Microchip Technology Inc.

DS39607B-page 5

PIC16F87/88

For these devices, it is recommended that ID location

be written as “11 1111 1000 bbbb”, where ‘bbbb’ is

ID information.

In other devices, the ID locations read out normally,

even after code protection. To understand how the

devices behave, refer to Table 6-1.

3.3

ID Locations

A user may store identification information (ID) in four

ID locations. The ID locations are mapped in

[0x2000:0x2003]. It is recommended that the user use

only the four Least Significant bits of each ID location.

In some devices, the ID locations read out in an

unscrambled fashion once code-protection is enabled.

FIGURE 3-1:

PROGRAM MEMORY MAPPING

4K words

0h

ID Location

2000h

2001h

2002h

2003h

2004h

2005h

2006h

2007h

Implemented

ID Location

FFFh

Reserved

Accesses

0x0000 to

0x0FFF

Device ID

Configuration Word 1

Configuration Word 2

1FFFh

2009h

2008h

Reserved

3FFFh

DS39607B-page 6

2002 Microchip Technology Inc.

PIC16F87/88

program one row.

3.4

Program Mode

The address and program counter are reset to 0x0000

by resetting the device (taking MCLR below VIL) and

re-entering Programming mode. Program and

configuration memory may then be read or verified

using the ‘Read Data’ and ‘Increment Address’

commands.

Program mode is entered by holding pins RB6 and RB7

low, while raising MCLR pin from VIL to VIHH (high

voltage). In this mode, the state of the RB3 pin does not

effect programming. Low-Voltage ICSP Programming

mode is entered by raising RB3 from VIL to VDD, and

then applying VDD to MCLR. Once in this mode, the

user program memory, as well as the configuration

memory, can be accessed and programmed in serial

fashion. The mode of operation is serial, and the

memory accessed is the user program memory. RB6

and RB7 are Schmitt Trigger inputs in this mode.

3.4.1

LOW-VOLTAGE ICSP

PROGRAMMING MODE

Low-voltage ICSP Programming mode allows

a

PIC16F87/88 device to be programmed using VDD

only. However, when this mode is enabled by a

configuration bit (LVP), the PIC16F87/88 device

dedicates RB3 to control entry/exit into Programming

mode.

Note:

The Osc must not have 72 osc clocks

while the device MCLR is between VIL and

VIHH.

The sequence that enters the device into the

Programming mode places all other logic into the

RESET state (the MCLR pin was initially at VIL). This

means all I/O are in the RESET state (high-impedance

inputs).

When the LVP bit is set to ‘1’, the Low-voltage ICSP

Programming entry is enabled. Since the LVP

configuration

bit

allows

Low-voltage

ICSP

Programming entry in its erased state, an erased

device will have the LVP bit enabled at the factory.

While LVP is ‘1’, RB3 is dedicated to Low-voltage ICSP

Programming. The following LVP steps assume the

LVP bit is set in the Configuration register.

Note:

The MCLR pin should be raised from

below VIL to above the minimum VIHH

(VPP), within 250 µs of VDD rise. This

ensures that the device always enters

1. Apply VDD to the VDD pin.

2. Drive MCLR low.

3. Apply VDD to the RB3/PGM pin.

4. Apply VDD to the MCLR pin.

Programming

mode

before

any

instructions that may be in program

memory can be executed. Otherwise,

unintended instruction execution could

occur when the INTRC clock source is

configured as the primary clock. Refer to

Figure 7-1.

All other specifications for High-voltage ICSP apply.

To disable Low-voltage ICSP mode, the LVP bit must

be programmed to ‘0’. This must be done while entered

with the High-voltage Entry mode (LVP bit = 1). RB3 is

now a general purpose I/O pin.

A device RESET will clear the PC and set the address

to ‘0’. The ‘Increment Address’ command will

increment the PC. The ‘Load Configuration’ command

will set the PC to 0x2000. The available commands are

shown in Table 3-1.

The normal sequence for programming four program

memory words at a time is as follows:

1. Set pointer to row location.

2. Issue a ‘Begin Erase’ command.

3. Wait tprog2.

4. Issue an ‘End Programming’ command.

5. Load a word at the current program memory

address using the ‘Load Data’ command.

6. Issue an ‘Increment Address’ command.

7. Load a word at the current program memory

address using the ‘Load Data’ command.

8. Repeat Step 6 and Step 7 two times.

9. Issue a ‘Begin Programming’ command to begin

programming.

10. Wait tprog1.

11. Issue an ‘End Programming’ command.

12. Increment to the next address.

13. Repeat steps 5 through 12 seven times to

2002 Microchip Technology Inc.

DS39607B-page 7

PIC16F87/88

3.4.2

SERIAL PROGRAM OPERATION

3.4.2.3

Load Data for Data Memory

The RB6 pin is used as a clock input pin, while the RB7

pin is used to enter command bits, and input or output

data during serial operation. To input a command, the

clock pin (RB6) is cycled six times. Each command bit

is latched on the falling edge of the clock, with the Least

Significant bit (LSb) of the command being input first.

The data on RB7 is required to have a minimum setup

(tset1) and hold (thold1) time (see AC/DC

specifications), with respect to the falling edge of the

clock. Commands with associated data (read and load)

are specified to have a minimum delay (tdly1) of 1 µs

between the command and the data. After this delay,

the clock pin is cycled 16 times, with the first cycle

being a Start bit (0) and the last cycle being a Stop bit

(0). Data is transferred LSb first.

After receiving this command, the chip will load a 14-bit

“data word” when 16 cycles are applied. However, the

data memory is only 8 bits wide and, thus, only the first

8 bits of data after the Start bit will be programmed into

the data memory (8 data bits and 6 zeros). It is still

necessary to cycle the clock the full 16 cycles in order

to allow the internal circuitry to reset properly. The data

memory contains up to 256 bytes. If the device is code

protected, the data is read as all zeros. A timing

diagram for this command is shown in Figure 7-2.

3.4.2.4

Read Data from Program Memory

After receiving this command, the chip will transmit

data bits out of the program memory (user or

configuration) currently accessed, starting with the

second rising edge of the clock input. The RB7 pin will

go into Output mode on the second rising clock edge,

reverting to Input mode (high-impedance) after the 16th

rising edge. A timing diagram of this command is

shown in Figure 7-3.

During a read operation, the LSb will be transmitted

onto RB7 on the rising edge of the second cycle, while,

during a load operation, the LSb will be latched on the

falling edge of the second cycle. A minimum 1 µs delay

(tdly2) is specified between consecutive commands.

All commands and data words are transmitted LSb first.

The data is transmitted on the rising edge and latched

on the falling edge of the clock. To allow decoding of

commands and reversal of data pin configuration, a

time separation of at least 1 µs (tdly1) is required

between a command and a data word, or another

command.

3.4.2.5

Read Data from Data Memory

After receiving this command, the chip will transmit

data bits out of the data memory, starting with the

second rising edge of the clock input. The RB7 pin will

go into Output mode on the second rising edge,

reverting to Input mode (high-impedance) after the 16th

rising edge. As previously stated, the data memory is

8-bits wide and, therefore, only the first 8 bits that are

output are actual data. A timing diagram for this

command is shown in Figure 7-4.

The available commands are described in the following

paragraphs and listed in Table 3-1.

3.4.2.1

Load Configuration

Upon receipt of the Load Configuration command, the

PC will be set to 0x2000 and the data sent with the

command is discarded. The four ID locations and the

configuration words can then be programmed using the

normal programming sequence, as described in

Section 3.4 “Program Mode”. A description of the

memory mapping schemes of the program memory for

normal operation and Configuration mode operation is

shown in Figure 3-1. Once the configuration memory is

entered, the only way to get back to the user program

memory is to exit the Program/Verify Test mode by

taking MCLR low (VIL).

3.4.2.6

Increment Address

The PC is incremented when this command is

received. A timing diagram of this command is shown

in Figure 7-5.

Note:

Upon entering Programming mode, a

“Load Data for Program Memory” or “Load

Data for Data Memory” command of 0x01

must be given before a Begin Erase or

Begin Programming command is initiated.

This will ensure that the programming

pointer is pointing to the correct location in

data or program memory.

3.4.2.2

Load Data for Program Memory

After receiving this command, the chip will load one

word (with 14 bits as a “data word”) to be programmed

into user program memory when 16 cycles are applied.

A timing diagram for this command is shown in

Figure 7-1.

DS39607B-page 8

2002 Microchip Technology Inc.

PIC16F87/88

The internal timer is not used for this command, so the

‘End Programming’ command must be used to stop

programming.

3.4.2.7

Begin Erase (Program and Data

Memory)

The erase block size for program memory is 32 words

(row) and 1 word for data memory. The row or word to

be programmed must first be erased. This is done by

setting the pointer to a location in the row or word and

then performing a ‘Begin Erase’ command. The row or

word is then erased. The user must allow the combined

time for row erase and programming, as specified in

the electrical specifications, for programming to

complete. This is an externally timed event.

1. If the address is pointing to user memory, the

user memory alone will be affected.

2. If the address is pointing to the physically

implemented configuration memory (2000h-

2008h), the configuration memory will be

written. The configuration words will not be

written unless the address is specifically

pointing to the corresponding address.

The internal timer is not used for this command, so the

‘End Programming’ command must be used to stop

erase.

A timing diagram for this command is shown in

Figure 7-7.

3.4.2.9

End Programming

Note 1: The code-protect bits cannot be erased

After receiving this command, the chip stops

programming the memory (configuration memory or

user program memory) that it was programming at the

time.

with this command.

2: All ‘Begin Erase’ operations can take

place over the entire VDD range.

A timing diagram for this command is shown in

Figure 7-6.

Note:

This command will also set the write data

shift latches to all ‘1’s to avoid issues with

downloading only one word before the

write.

3.4.2.8

Begin Programming Only

Programming of program and data memory will begin

once this command is received and decoded. The

user must allow the time for programming, as specified

in the electrical specifications, for programming to

complete. An ‘End Programming’ command is

required.

TABLE 3-1:

COMMAND MAPPING FOR PIC16F87/88

Mapping (MSB … LSB)

Command

Data

Voltage Range

Load Configuration

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0, data (14), 0

2.0V-5.5V

4.5V-5.5V

2.0V-5.5V

Load Data for Program Memory

Read Data from Program Memory

Increment Address

Begin Erase

externally timed

internally timed

Begin Programming Only Cycle

Bulk Erase Program Memory

Bulk Erase Data Memory

Chip Erase

Load Data for Data Memory

0, zeroes (6),

data (8), 0

Read Data from Data Memory

End Programming

0

1

0

1

0

1

0, zeroes (6),

data (8), 0

2.0V-5.5V

2002 Microchip Technology Inc.

DS39607B-page 9

PIC16F87/88

3.5.1.3

Chip Erase

3.5

Erasing Program and Data

Memory

This command, when performed, will erase the

program memory, EE data memory, and all of the code

protection bits. All on-chip Flash and EEPROM

memory is erased, regardless of the address contained

in the PC.

When a Chip Erase command is issued and the PC

points to (0000h-1FFFh), the configuration words

(2007h and 2008h) and the user program memory will

be erased. When a Chip Erase command is issued and

the PC points to (2000h-2008h), all of the configuration

memory, program memory, and data memory will be

erased.

Depending on the state of the code protection bits,

program and data memory will be erased using

different methods. The first two commands are used

when both program and data memories are not code

protected. The third command is used when either

memory is code protected, or if you want to also erase

the code protect bits. A device programmer should

determine the state of the code protection bits and then

apply the proper command to erase the desired

memory.

3.5.1

ERASING PROGRAM AND

DATA MEMORY

The Chip Erase is internally self-timed to ensure that all

program and data memory are erased before the code

protect bits are erased. A timing diagram for this

command is shown in Figure 7-10.

When both program and data memories are not code-

protected, they can be individually erased by the

following ‘Bulk Erase’ commands. If it is desired to

erase both program and data memory with a single

command, the ‘Chip Erase’ command must be used

whether code protection is disabled or enabled

(detailed in Section 3.5.1.3 “Chip Erase”).

Note:

The Chip Erase operation must take place

at the 4.5V to 5.5V VDD range.

3.5.2

ERASING CODE-PROTECTED

MEMORY

For the PIC16F87/88 devices, once code protection is

enabled, all protected program and data memory

locations read all '0's and further programming is

disabled. The ID locations and configuration words

read out unscrambled and can be reprogrammed

normally. The only command to erase a code-protected

PIC16F87/88 device is the ‘Chip Erase’. This erases

program memory, data memory, configuration bits and

ID locations, as described in Section 3.5.1.3 “Chip

Erase”. Since all data within the program and data

memory will be erased when this command is

executed, the security of the data or code is not

compromised.

3.5.1.1

Bulk Erase Program Memory

When this command is performed, and is followed by

a ‘Begin Erase’ command, the entire program memory

will be erased.

If the address is pointing to user memory, only the user

memory will be erased.

If the address is pointing to the configuration memory

(2000h-2008h), then both the user memory and the

configuration memory will be erased. The configuration

words will not be erased, even if the address is pointing

to location 2007h.

Previously, a load data with 0FFh command was

recommended before any ‘Bulk Erase’. On these

devices, this will not be required.

The ‘Bulk Erase’ command is disabled when the CP

bit is programmed to ‘0’, enabling code-protect.

A timing diagram for this command is shown in

Figure 7-8.

3.5.1.2

Bulk Erase Data Memory

When this command is performed, and is followed by

a ‘Begin Erase’ command, the entire data memory will

be erased.

The ‘Bulk Erase Data’ command is disabled when the

CPD bit is programmed to ‘0’, enabling protected data

memory. A timing diagram for this command is shown

in Figure 7-9.

Note:

All ‘Bulk Erase’ operations must take place

at the 4.5V to 5.5V VDD range.

DS39607B-page 10

2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 3-2:

ALGORITHM 1 FLOW CHART – PROGRAM MEMORY (2.0V ≤ VDD < 5.5V)

Start

Set VDD = VDDP

Begin

Erase

Command

Wait tprog2

End

Programming

Command

Load Data

Command

Increment

Address

No

Four Loads

Done?

Command

Yes

Begin

Programming Only

Command

Wait tprog1

End

Programming

Command

Verify all

Locations

All

Increment

Address

No

Row Locations

Done?

Command

Yes

No

Report Verify

Error

Data Correct?

Increment

Address

All Locations

Done?

Yes

End

Command

Yes

2002 Microchip Technology Inc.

DS39607B-page 11

PIC16F87/88

FIGURE 3-3:

ALGORITHM 2 FLOW CHART – PROGRAM MEMORY (4.5V ≤ VDD ≤ 5.5V)

Start

Chip Erase

Sequence

Set VDD = VDDP

Load Data

Command

Increment

Address

No

Four Loads

Done?

Command

Yes

Begin

Programming Only

Command

Wait tprog1

End

Programming

Command

Increment

Address

Yes

No

All Locations

Done?

Command

Verify all

Locations

No

Report Verify

Error

Data Correct?

Yes

End

DS39607B-page 12

2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 3-4:

FLOW CHART – PIC16F87/88 CONFIGURATION MEMORY

(2.0V ≤ VDD < 5.5V) AND (4.5V ≤ VDD < 5.5V)

PROGRAM

FOUR LOCATIONS

Start

Begin

Erase

Load

Configuration

Data

Command

Load

Configuration

Data

(Set PC = 2000h)

Wait tprog2

Yes

End

Programming

Command

Program ID

Location?

Program Four

Locations

Read Data

Command

No

Load Data

Command

Report

Programming

Failure

No

Data Correct?

Yes

Increment

No

Four Loads

Done?

Address

Command

Address =

0x2003?

Yes

Increment

Address

Begin

No

Program Only

Command

Increment

Address

Address =

0x2004?

Command

No

Wait tprog1

Yes

End

Programming

Command

Increment

Address

Command

End

Increment

Address

PROGRAM

CONFIG1

and

Start

Command

CONFIG2

Load Data

Command

Increment

Address

Increment

Address

Program

Config1

Command

Begin

Program Only

Command

Report Program

No

Read Data

Command

Program

Config2

Wait tprog1

Configuration

Word Error

Data Correct?

Yes

End

Programming

Command

End

2002 Microchip Technology Inc.

DS39607B-page 13

PIC16F87/88

4.0

CONFIGURATION WORD

The PIC16F87/88 has several configuration bits.

These bits can be written to ‘0’ or ‘1’ with the ‘Begin

Program Only’ command. A ‘Begin Erase’ command is

not required when programming configuration memory.

4.1

Device ID Word

The device ID word for the PIC16F87/88 is located at

2006h.

TABLE 4-1:

Device

DEVICE ID VALUE

Device ID Value

Dev

Rev

PIC16F87

PIC16F88

00 0111 0010

00 0111 0110

XXXX

DS39607B-page 14

2002 Microchip Technology Inc.

PIC16F87/88

REGISTER 4-1:

CONFIGURATION WORD 1 (2007h) REGISTER

CP

bit 13

CCPMX DEBUG WRT1 WRT0

CPD

LVP

BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0

bit 0

bit 13

bit 12

bit 11

CP: Flash Program Memory Code Protection bits

1= Code protection off

0= 0000h to 0FFFh code protected (all protected)

CCPMX: CCP Mux bit

1= CCP1 function on RB0

0= CCP1 function on RB3

DEBUG: In-Circuit Debugger Mode bit

1= In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins

0= In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger

bit 10-9

WRT1:WRT0: Flash Program Memory Write Enable bits

11= Write protection off

10= 0000h to 00FFh write-protected, 0100h to 0FFFh may be modified by EECON control

01= 0000h to 07FFh write-protected, 0800h to 0FFFh may be modified by EECON control

00= 0000h to 0FFFh write-protected

bit 8

CPD: Data EE Memory Code Protection bit

1= Code protection off

0= Data EE memory code-protected

bit 7

LVP: Low-voltage Programming Enable bit

1= RB3/PGM pin has PGM function, Low-voltage Programming enabled

0= RB3 is digital I/O, HV on MCLR must be used for programming

bit 6

BOREN: Brown-out Reset Enable bit

1= BOR enabled

0= BOR disabled

bit 5

MCLRE: RA5/MCLR Pin Function Select bit

1= RA5/MCLR pin function is MCLR

0= RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD

bit 3

PWRTEN: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

bit 2

WDTEN: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled

bit 4, 1-0

FOSC2:FOSC0: Oscillator Selection bits

111= EXTRC oscillator; CLKO function on RA6/OSC2/CLKO

110= EXTRC oscillator; port I/O function on RA6/OSC2/CLKO

101= INTRC oscillator; CLKO function on RA6/OSC2/CLKO

100= INTRC oscillator; port I/O function on RA6/OSC2/CLKO

011= EXTCLK; port I/O function on RA6/OSC2/CLKO

010= HS oscillator

001= XT oscillator

000= LP oscillator

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

1 = bit is set

U = Unimplemented bit, read as ‘0’

0 = bit is cleared x = bit is unknown

2002 Microchip Technology Inc.

DS39607B-page 15

PIC16F87/88

REGISTER 4-2:

CONFIGURATION WORD 2 (2008h) REGISTER

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

U-1

—

IESO FCMEN

bit 0

bit 13

bit 13-2

bit 1

Unimplemented: Read as ‘1’

IESO: Internal External Switch Over bit

1= Internal External Switch Over mode enabled

0= Internal External Switch Over mode disabled

bit 0

FCMEN: Fail-Safe Clock Monitor Enable bit

1= Fail-Safe Clock Monitor enabled

0= Fail-Safe Clock Monitor disabled

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

1 = bit is set

U = Unimplemented bit, read as ‘0’

0 = bit is cleared

x = bit is unknown

DS39607B-page 16

2002 Microchip Technology Inc.

PIC16F87/88

5.0

EMBEDDING CONFIGURATION WORD AND ID INFORMATION IN HEX FILE

To allow portability of code, the programmer is required to read the configuration word and ID locations from the HEX

file when loading the HEX file. If configuration word information was not present in the HEX file, a simple warning

message may be issued. Similarly, while saving a HEX file, configuration word and ID information must be included.

An option to not include this information may be provided.

Specifically for the PIC16F87/88, the EEPROM data memory should also be embedded in the HEX file (see

Section 3.2 “Data EEPROM Memory”).

Microchip Technology Inc. feels strongly that this feature is important for the benefit of the end customer.

The Least Significant 16 bits of this sum are the

checksum.

6.0

CHECKSUM COMPUTATION

Checksum is calculated by reading the contents of the

PIC16F87/88 memory locations and totaling the

opcodes, up to the maximum user-addressable

location (e.g., 0xFFF for the PIC16F87/88). Any carry

bits exceeding 16 bits are neglected. Finally, the

configuration word (appropriately masked) is added to

the checksum. Checksum computation for each

member of the PIC16F87/88 devices is shown in

Table 6-1.

The following table describes how to calculate the

checksum for each device. Note that the checksum

calculation differs depending on the code protect

setting. Since the program memory locations read out

differently depending on the code protect setting, the

table describes how to manipulate the actual program

memory values to simulate the values that would be

read from a protected device. When calculating a

checksum by reading a device, the entire program

memory can simply be read and summed. The

configuration words and ID locations can always be

read.

The checksum is calculated by summing the following:

• The contents of all program memory locations

• The configuration words, appropriately masked

• Masked ID locations (when applicable)

Note that some older devices have an additional value

added in the checksum. This is to maintain compatibility

with older device programmer checksums.

TABLE 6-1:

CHECKSUM COMPUTATION

0x25E6 at 0

Blank

Code-

Device

Checksum*

and Max

Address

Protect

Value

PIC16F87

OFF

ON

OFF

ON

SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003)

3002

5004

3002

5004

FBD0

IBD2

FBD0

IBD2

(CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID

SUM(0000:0FFF) + (CONFIG0 & 3FFF) + (CONFIG1 & 0003)

(CONFIG0 & 3FFF) + (CONFIG1 & 0003) + SUM_ID

PIC16F88

Legend: CFGW

=

Configuration Word

SUM[a:b]

=

[Sum of locations a to b inclusive]

SUM_ID

ID locations masked by 0xF, then made into a 16-bit value with ID0 as the Most Significant

nibble.

For example, ID0 = 0x1, ID1 = 0x2, ID3 = 0x3, ID4 = 0x4, then SUM_ID = 0x1234.

*Checksum = [Sum of all the individual expressions] MODULO [0xFFFF]

+

&

= Addition

= Bitwise AND

2002 Microchip Technology Inc.

DS39607B-page 17

PIC16F87/88

7.0

PROGRAM MODE ELECTRICAL CHARACTERISTICS

TABLE 7-1:

TIMING REQUIREMENTS FOR PROGRAM MODE

Standard Operating Procedure (unless otherwise stated)

AC/DC CHARACTERISTICS

POWER SUPPLY PINS

Operating Temperature

Operating Voltage

0 ≤ TA ≤ +70°C

2.0V ≤ VDD ≤ 5.5V

Characteristics

General

Sym

Min

Typ

Max

Units Conditions/Comments

VDD level for Begin Erase, Begin

Program operations and EECON1

writes of program memory

VDD

2.0

—

5.5

V

VDD level for Begin Erase, Begin

Program operations and EECON1

writes of data memory

VDD level for Bulk Erase, Chip Erase,

and Begin Program operations of

program and data memory

VDD

2.0

4.5

—

5.5

V

Begin Programming Only cycle time

tprog1

tprog2

1

2

1

2

8

—

ms

V

Externally Timed, > 4.5V

Externally Timed, < 4.5V

Externally Timed, > 4.5V

Externally Timed, < 4.5V

Externally Timed

Begin Erase

Bulk Erase cycle time

Chip Erase cycle time

High voltage on MCLR and

RA4/T0CKI for Program mode entry

tprog3

tprog4

VIHH

—

13.5

Internally Timed

VDD + 3.5

MCLR rise time (VSS to VHH) for

Program mode entry

tVHHR

—

1.0

µs

(RB6, RB7) input high level

(RB6, RB7) input low level

RB<7:4> setup time before MCLR↑

(Program mode selection pattern

setup time)

VIH1

VIL1

tset0

0.8 VDD

0.2 VDD

100

—

V

ns

Schmitt Trigger input

RB<7:4> hold time after MCLR↑

(Program mode selection pattern

setup time)

thld0

5

—

µs

Serial Program

Data in setup time before clock↓

Data in hold time after clock↓

Data input not driven to next clock

input (delay required between

command/data or command/

command)

tset1

thld1

tdly1

100

1.0

—

ns

µs

ns

2.0V ≤ VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

100

Delay between clock↓ to clock↑

tdly2

1.0

100

80

—

µs

ns

2.0V ≤ VDD < 4.5V

4.5V ≤ VDD ≤ 5.5V

of next command or data

Clock↑ to data out valid

tdly3

tpu

(during read data)

Setup time between VDD rise and

MCLR rise

tset0

—

250

µs

DS39607B-page 18

2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 7-1:

LOAD DATA FOR USER PROGRAM MEMORY COMMAND (PROGRAM)

VIHH

MCLR

1 µs min

tset0

1

2

3

4

5

15

1

2

3

4

5

0

6

16

tdly2

RB6

(Clock)

thld0

0

1

0

strt_bit

RB7

(Data)

stp_bit

X

tset1

thld1

tset1

tdly1

1 µs min

thld1

100 ns min

Program Mode

Reset

FIGURE 7-2:

LOAD DATA FOR USER DATA MEMORY COMMAND (PROGRAM)

VIHH

MCLR

1 µs min

tset0

1

2

3

4

5

15

1

2

3

4

5

0

6

16

tdly2

RB6

(Clock)

thld0

1

strt_bit

RB7

(Data)

0

stp_bit

X

tset1

thld1

tset1

tdly1

1 µs min

thld1

100 ns min

Program Mode

Reset

FIGURE 7-3:

READ DATA FROM PROGRAM MEMORY COMMAND (PROGRAM)

VIHH

MCLR

tdly2

tset0

thld0

1 µs min

1

2

3

4

5

15

1

2

3

4

5

6

16

RB6

(Clock)

tdly3

RB7

bit 13

0

1

0

bit 0

X

(Data)

tdly1

tset1

thld1

1 µs min

RB7

Input

100 ns min

RB7 = Input

RB7 = Output

Program Mode

Reset

2002 Microchip Technology Inc.

DS39607B-page 19

PIC16F87/88

FIGURE 7-4:

READ DATA FROM DATA MEMORY COMMAND (PROGRAM)

VIHH

MCLR

tset0

tdly2

thld0

1

1 µs min

1

2

3

4

5

15

2

3

4

5

6

16

RB6

(Clock)

tdly3

RB7

(Data)

bit 13

1

bit 0

0

1

0

X

tdly1

tset1

thld1

1 µs min

RB7

Input

100 ns min

RB7 = Input

RB7 = Output

Program Mode

Reset

FIGURE 7-5:

INCREMENT ADDRESS COMMAND (SERIAL PROGRAM)

VIHH

MCLR

tdly2

Next Command

2

1 µs min.

1

0

2

3

4

5

6

RB6

(Clock)

RB7

(Data)

1

0

X

0

tset1

tdly1

thld1

100 ns min.

Program Mode

1 µs min.

Reset

FIGURE 7-6:

BEGIN ERASE (SERIAL PROGRAM)

VIHH

MCLR

tprog2

End Programming Command

2

1

2

3

4

5

6

RB6

(Clock)

RB7

0

1

0

X

0

(Data)

tset1

?

thld1

100 ns min.

Program Mode

Reset

DS39607B-page 20

2002 Microchip Technology Inc.

PIC16F87/88

FIGURE 7-7:

BEGIN PROGRAMING ONLY COMMAND (SERIAL PROGRAM)

VIHH

MCLR

tprog1

End Programming Command

2

1

2

3

4

5

6

RB6

(Clock)

RB7

0

1

X

0

(Data)

tset1

?

thld1

100 ns min.

Program Mode

Reset

FIGURE 7-8:

BULK ERASE PROGRAM MEMORY COMMAND (SERIAL PROGRAM/VERIFY)

VIHH

End

MCLR

tprog3

Programming

Begin Erase

1

2

1

2

3

4

5

6

1

2

RB6

(Clock)

RB7

1

0

X

0

X

0

(Data)

tset1

?

thld1

100 ns min.

Program/Verify Test Mode

Reset

FIGURE 7-9:

BULK ERASE DATA MEMORY COMMAND (SERIAL PROGRAM/VERIFY)

VIHH

MCLR

tprog3

Begin Erase

2

End Programming

2

1

2

3

4

5

6

RB6

(Clock)

RB7

X

0

1

X

0

(Data)

tset1

?

thld1

100 ns min.

Program/Verify Test Mode

Reset

2002 Microchip Technology Inc.

DS39607B-page 21

PIC16F87/88

FIGURE 7-10:

CHIP ERASE COMMAND (SERIAL PROGRAM)

VIHH

MCLR

tprog4

Next Command

1

2

1

2

1

3

4

5

6

RB6

(Clock)

RB7

1

X

0

X

(Data)

tdly1

tset1

1 µs min.

thld1

100 ns min.

Program Mode

Reset

FIGURE 7-11:

PROGRAM MODE ENTRY

VIHH

MCLR

VDD

tpu

1

2

3

4

5

RB6

(CLOCK)

RB7

(DATA)

Program Mode

Reset

DS39607B-page 22

2002 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is intended through suggestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microchip Technology Incorporated with respect

to the accuracy or use of such information, or infringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE and PowerSmart are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER,

SEEVAL, SmartShunt and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Application Maestro, dsPICDEM, dsPICDEM.net,

dsPICworks, ECAN, ECONOMONITOR, FanSense,

FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,

ICEPIC, microPort, Migratable Memory, MPASM, MPLIB,

MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail,

PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC,

Select Mode, SmartSensor, SmartTel and Total Endurance

are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in October

2003 . The Company’s quality system processes and procedures are

®

for its PICmicro 8-bit MCUs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, non-volatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS39607B-page 23

2003 Microchip Technology Inc.

M

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11/24/03

DS39607B-page 24

2002 Microchip Technology Inc.


型号：	PIC16F88
厂家：	MICROCHIP
描述：	Flash Memory Programming Specification 闪存编程规范闪存
文件：	总24页 (文件大小：404K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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