PIC16F913E/SS301_技术文档

PIC16F917/916/914/913

Data Sheet

28/40/44-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

Preliminary

DS41250E

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

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Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM,

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PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS41250E-page ii

Preliminary

PIC16F917/916/914/913

28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with

LCD Driver and nanoWatt Technology

High-Performance RISC CPU:

Low-Power Features:

• Only 35 instructions to learn:

- All single-cycle instructions except branches

• Operating speed:

• Standby Current:

- <100 nA @ 2.0V, typical

• Operating Current:

- 8.5 μA @ 32 kHz, 2.0V, typical

- 100 μA @ 1 MHz, 2.0V, typical

• Watchdog Timer Current:

- 1 μA @ 2.0V, typical

- DC – 20 MHz oscillator/clock input

- DC – 200 ns instruction cycle

• Program Memory Read (PMR) capability

• Interrupt capability

• 8-level deep hardware stack

Peripheral Features:

• Direct, Indirect and Relative Addressing modes

• Liquid Crystal Display module:

Special Microcontroller Features:

- Up to 60 pixel drive capability on 28-pin

devices

• Precision Internal Oscillator:

-

Up to 96 pixel drive capability on 40-pin

devices

- Factory calibrated to ±1%

- Software selectable frequency range of

8 MHz to 32 kHz

- Four commons

- Software tunable

• Up to 35 I/O pins and 1 input-only pin:

- High-current source/sink for direct LED drive

- Interrupt-on-pin change

- Individually programmable weak pull-ups

• In-Circuit Serial Programming™ (ICSP™) via two

pins

- Two-Speed Start-up mode

- Crystal fail detect for critical applications

- Clock mode switching during operation for

power savings

• Power-saving Sleep mode

• Wide operating voltage range (2.0V-5.5V)

• Industrial and Extended temperature range

• Power-on Reset (POR)

• Analog comparator module with:

- Two analog comparators

- Programmable on-chip voltage reference

(CVREF) module (% of VDD)

- Comparator inputs and outputs externally

accessible

• A/D Converter:

- 10-bit resolution and up to 8 channels

• Timer0: 8-bit timer/counter with 8-bit

programmable prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR) with software control

option

• Enhanced Low-Current Watchdog Timer (WDT)

with on-chip oscillator (software selectable

nominal 268 seconds with full prescaler) with

software enable

• Multiplexed Master Clear with pull-up/input pin

• Programmable code protection

- Option to use OSC1 and OSC2 as Timer1

oscillator if INTOSCIO or LP mode is

selected

• High-Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

• Timer2: 8-bit timer/counter with 8-bit period

register, prescaler and postscaler

• Addressable Universal Synchronous

Asynchronous Receiver Transmitter (AUSART)

• Up to 2 Capture, Compare, PWM modules:

- 16-bit Capture, max. resolution 12.5 ns

- 16-bit Compare, max. resolution 200 ns

- 10-bit PWM, max. frequency 20 kHz

• Synchronous Serial Port (SSP) with I²C™

Preliminary

DS41250E-page 1

PIC16F917/916/914/913

Program

Data Memory

Memory

LCD

(segment

drivers)

Timers

8/16-

bit

10-bit A/D

(ch)

Device

I/O

CCP

Flash

(words/bytes)

SRAM

EEPROM

(bytes)

PIC16F913

PIC16F914

PIC16F916

PIC16F917

4K/7K

256

352

256

24

35

24

35

5

8

5

8

16

24

16

24

1

2

1

2

2/1

8K/14K

Pin Diagrams – PIC16F914/917, 40-Pin

40-pin PDIP

RE3/MCLR/VPP

1

RA0/AN0/C1-/SEG12

2

40

RB7/ICSPDAT/ICDDAT/SEG13

RB6/ICSPCLK/ICDCK/SEG14

RB5/COM1

39

38

37

36

35

34

33

32

31

30

29

28

RA1/AN1/C2-/SEG7

3

RA2/AN2/C2+/VREF-/COM2

4

RA3/AN3/C1+/VREF+/SEG15

5

RA4/C1OUT/T0CKI/SEG4

6

RB4/COM0

RB3/SEG3

RB2/SEG2

RA5/AN4/C2OUT/SS/SEG5

7

RB1/SEG1

RE0/AN5/SEG21

8

RE1/AN6/SEG22

9

RE2/AN7/SEG23

10

RB0/INT/SEG0

VDD

VSS

VDD

11

VSS

12

RD7/SEG20

RD6/SEG19

RA7/OSC1/CLKI/T1OSI

13

RD5/SEG18

RA6/OSC2/CLKO/T1OSO

14

27

26

25

24

23

22

21

RD4/SEG17

RC0/VLCD1

15

RC1/VLCD2

16

RC2/VLCD3

17

RC3/SEG6

18

RC7/RX/DT/SDI/SDA/SEG8

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G/SDO/SEG11

RD3/SEG16

RD0/COM3

19

RD1

20

RD2/CCP2

DS41250E-page 2

Preliminary

PIC16F917/916/914/913

Pin Diagrams – PIC16F913/916, 28-Pin

28-pin PDIP, SOIC, SSOP

28

27

1

2

3

4

5

6

7

8

9

RE3/MCLR/VPP

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/VREF+/COM3/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS/SEG5

VSS

RB7/ICSPDAT/ICDDAT/SEG13

RB6/ICSPCLK/ICDCK/SEG14

RB5/COM1

RB4/COM0

RB3/SEG3

RB2/SEG2

RB1/SEG1

26

25

24

23

22

21

20

19

18

17

16

15

RB0/INT/SEG0

VDD

RA7/OSC1/CLKI/T1OSI

RA6/OSC2/CLKO/T1OSO

RC0/VLCD1

VSS

10

11

RC7/RX/DT/SDI/SDA/SEG8

RC6/TX/CK/SCK/SCL/SEG9

RC5/T1CKI/CCP1/SEG10

RC4/T1G/SDO/SEG11

RC1/VLCD2

12

13

14

RC2/VLCD3

RC3/SEG6

28-pin QFN

RB3/SEG3

RB2/SEG2

RB1/SEG1

RB0/INT/SEG0

VDD

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/VREF+/COM3/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS/SEG5

VSS

1

2

3

4

5

6

7

21

20

19

18

17

16

15

PIC16F913/916

VSS

RA7/OSC1/CLKI/T1OSI

RA6/OSC2/CLKO/T1OSO

RC7/RX/DT/SDI/SDA/SEG8

Preliminary

DS41250E-page 3

PIC16F917/916/914/913

Pin Diagrams – PIC16F914/917, 44-Pin

44-pin TQFP

NC

RC0/VLCD1

RA6/OSC2/CLKO/T1OSO

RA7/OSC1/CLKI/T1OSI

VSS

RC7/RX/DT/SDI/SDA/SEG8

RD4/SEG17

RD5/SEG18

RD6/SEG19

RD7/SEG20

VSS

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

PIC16F914/917

VDD

RE2/AN7/SEG23

RE1/AN6/SEG22

RE0/AN5/SEG21

RA5/AN4/C2OUT/SS/SEG5

RA4/C1OUT/T0CKI/SEG4

VDD

RB0/SEG0/INT

RB1/SEG1

25

24

23

RB2/SEG2

RB3/SEG3

44-pin QFN

RA6/OSC2/CLK0/T1OSO

RA7/OSC1/CLKI/T1OSI

VSS

NC

RC7/RX/DT/SDI/SDA/SEG8

RD4/SEG17

RD5/SEG18

RD6/SEG19

RD7/SEG20

VSS

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

PIC16F914/917

VDD

RE2/AN7/SEG23

RE1/AN6/SEG22

RE0/AN5/SEG21

RA5/AN4/C2OUT/SS/SEG5

RA4/C1OUT/T0CKI/SEG4

VDD

RB0/INT/SEG0

RB1/SEG1

RB2/SEG2

25

24

23

DS41250E-page 4

Preliminary

PIC16F917/916/914/913

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Memory Organization................................................................................................................................................................. 13

3.0 I/O Ports ..................................................................................................................................................................................... 31

4.0 Clock Sources ............................................................................................................................................................................ 69

5.0 Timer0 Module ........................................................................................................................................................................... 81

6.0 Timer1 Module With Gate Control.............................................................................................................................................. 85

7.0 Timer2 Module ........................................................................................................................................................................... 90

8.0 Comparator Module.................................................................................................................................................................... 93

9.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 101

10.0 Programmable Low-Voltage Detect (PLVD) Module................................................................................................................ 125

11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 127

12.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................ 143

13.0 Data EEPROM and Flash Program Memory Control............................................................................................................... 153

14.0 SSP Module Overview ............................................................................................................................................................. 159

15.0 Capture/Compare/PWM Modules ............................................................................................................................................ 177

16.0 Special Features of the CPU.................................................................................................................................................... 185

17.0 Instruction Set Summary.......................................................................................................................................................... 205

18.0 Development Support............................................................................................................................................................... 215

19.0 Electrical Specifications............................................................................................................................................................ 219

20.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 245

21.0 Packaging Information.............................................................................................................................................................. 247

Appendix A: Data Sheet Revision History.......................................................................................................................................... 257

®

Appendix B: Migrating From Other PICmicro Devices..................................................................................................................... 257

Appendix C: Conversion Considerations ........................................................................................................................................... 258

Index .................................................................................................................................................................................................. 259

On-line Support.................................................................................................................................................................................. 267

Systems Information and Upgrade Hot Line ...................................................................................................................................... 267

Reader Response.............................................................................................................................................................................. 268

Product Identification System ............................................................................................................................................................ 269

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•

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Preliminary

DS41250E-page 5

PIC16F917/916/914/913

NOTES:

DS41250E-page 6

Preliminary

PIC16F917/916/914/913

1.0

DEVICE OVERVIEW

This document contains device specific information for

the PIC16F91X. Additional information may be found in

the “PICmicro^®Mid-Range MCU Family Reference

Manual” (DS33023), downloaded from the Microchip

web site. The Reference Manual should be considered

a complementary document to this data sheet and is

highly recommended reading for

a

better

understanding of the device architecture and operation

of the peripheral modules.

The PIC16F91X devices are covered by this data

sheet. It is available in 28/40/44-pin packages.

Figure 1-1 shows a block diagram of the PIC16F913/

916 device and Table 1-1 shows the pinout description.

Figure 1-2 shows a block diagram of the PIC16F914/

917 device and Table 1-1 shows the pinout description.

Preliminary

DS41250E-page 7

PIC16F917/916/914/913

FIGURE 1-1:

PIC16F913/916 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

Flash

4k/8k x 14

Program

Memory

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/VREF+/COM3/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS/SEG5

RA6/OSC2/CLKO/T1OSO

RA7/OSC1/CLKI/T1OSI

RAM

256/352 bytes

File

8-Level Stack (13-bit)

Registers

Program

Bus

14

Program Memory Read

(PRM)

RAM Addr

9

PORTB

RB0/INT/SEG0

RB1/SEG1

RB2/SEG2

Addr MUX

Instruction Reg

Indirect

Addr

7

Direct Addr

8

RB3/SEG3

RB4/COM0

RB5/COM1

FSR Reg

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

Status Reg

8

PORTC

RC0/VLCD1

RC1/VLCD2

3

MUX

Power-up

Timer

RC2/VLCD3

RC3/SEG6

RC4/T1G/SDO/SEG11

RC5/T1CKI/CCP1/SEG10

RC6/TX/CK/SCK/SCL/SEG9

RC7/RX/DT/SDI/SDA/SEG8

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

Watchdog

Timer

W Reg

PORTE

Brown-out

Reset

Internal

RE3/MCLR/VPP

Oscillator

Block

VDD

VSS

Data EEPROM

256 bytes

Timer0

Timer1

Timer2

10-bit A/D

Addressable

USART

Comparators

CCP1

SSP

BOR

PLVD

LCD

DS41250E-page 8

Preliminary

PIC16F917/916/914/913

FIGURE 1-2:

PIC16F914/917 BLOCK DIAGRAM

INT

Configuration

13

8

PORTA

Data Bus

Program Counter

RA0/AN0/C1-/SEG12

Flash

4k/8k x 14

Program

Memory

RA1/AN1/C2-/SEG7

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/VREF+/SEG15

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS/SEG5

RA6/OSC2/CLKO/T1OSO

RA7/OSC1/CLKI/T1OSI

RAM

256/352 bytes

File

8-Level Stack (13-bit)

Registers

Program

Bus

14

Program Memory Read

(PRM)

RAM Addr

9

PORTB

RB0/INT/SEG0

RB1/SEG1

RB2/SEG2

Addr MUX

Instruction Reg

Indirect

Addr

7

Direct Addr

8

RB3/SEG3

RB4/COM0

RB5/COM1

FSR Reg

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

Status Reg

8

PORTC

RC0/VLCD1

RC1/VLCD2

3

MUX

Power-up

Timer

RC2/VLCD3

RC3/SEG6

RC4/T1G/SDO/SEG11

RC5/T1CKI/CCP1/SEG10

RC6/TX/CK/SCK/SCL/SEG9

RC7/RX/DT/SDI/SDA/SEG8

Instruction

Decode and

Control

Oscillator

Start-up Timer

ALU

OSC1/CLKI

OSC2/CLKO

Power-on

Reset

8

Timing

Generation

PORTD

Watchdog

Timer

W Reg

RD0/COM3

RD1

Brown-out

Reset

RD2/CCP2

RD3/SEG16

RD4/SEG17

RD5/SEG18

RD6/SEG19

RD7/SEG20

Internal

Oscillator

Block

VDD

VSS

PORTE

RE0/AN5/SEG21

RE1/AN6/SEG22

RE2/AN7/SEG23

RE3/MCLR/VPP

Timer0

Timer1

Timer2

10-bit A/D

Data EEPROM

256 bytes

Addressable

USART

Comparators

CCP1

CCP2

SSP

BOR

PLVD

LCD

Preliminary

DS41250E-page 9

PIC16F917/916/914/913

TABLE 1-1:

PIC16F91X PINOUT DESCRIPTIONS

Input Output

Name

Function

Description

Type Type

RA0/AN0/C1-/SEG12

RA0

AN0

TTL

AN

—

CMOS General purpose I/O.

—

Analog input Channel 0/Comparator 1 input – negative.

Comparator 1 negative input.

C1-

AN

SEG12

RA1

—

LCD analog output.

RA1/AN1/C2-/SEG7

TTL

AN

—

CMOS General purpose I/O.

AN1

—

Analog input Channel 1/Comparator 2 input – negative.

C2-

AN

Comparator 2 negative input.

LCD analog output.

SEG7

RA2

—

RA2/AN2/C2+/VREF-/COM2

TTL

AN

—

CMOS General purpose I/O.

AN2

—

AN

—

Analog input Channel 2/Comparator 2 input – positive.

C2+

Comparator 2 positive input.

External Voltage Reference – negative.

LCD analog output.

VREF-

COM2

RA3

AN

—

AN

(1)

RA3/AN3/C1+/VREF+/COM3

SEG15

/

TTL

AN

—

CMOS General purpose I/O.

AN3

—

AN

—

Analog input Channel 3/Comparator 1 input – positive.

C1+

Comparator 1 positive input.

External Voltage Reference – positive.

LCD analog output.

VREF+

AN

—

(1)

COM3

AN

SEG15

RA4

—

LCD analog output.

RA4/C1OUT/T0CKI/SEG4

RA5/AN4/C2OUT/SS/SEG5

TTL

—

CMOS General purpose I/O.

CMOS Comparator 1 output.

C1OUT

T0CKI

SEG4

RA5

ST

—

Timer0 clock input.

LCD analog output.

AN

TTL

AN

—

CMOS General purpose I/O.

Analog input Channel 4.

CMOS Comparator 2 output.

AN4

—

C2OUT

SS

TTL

—

Slave select input.

LCD analog output.

SEG5

RA6

AN

RA6/OSC2/CLKO/T1OSO

RA7/OSC1/CLKI/T1OSI

TTL

—

CMOS General purpose I/O.

XTAL Crystal/Resonator.

OSC2

CLKO

T1OSO

RA7

—

CMOS TOSC/4 reference clock.

XTAL Timer1 oscillator output.

CMOS General purpose I/O.

—

TTL

XTAL

ST

XTAL

TTL

ST

—

OSC1

CLKI

—

Crystal/Resonator.

Clock input.

T1OSI

RB0

Timer1 oscillator input.

RB0/INT/SEG0

RB1/SEG1

CMOS General purpose I/O. Individually enabled pull-up.

INT

—

External interrupt pin.

LCD analog output.

SEG0

RB1

AN

TTL

—

CMOS General purpose I/O. Individually enabled pull-up.

AN LCD analog output.

SEG1

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D = Direct

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917.

2: Pins available on PIC16F914/917 only.

DS41250E-page 10

Preliminary

PIC16F917/916/914/913

TABLE 1-1:

PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)

Input Output

Type Type

Name

Function

Description

RB2/SEG2

RB3/SEG3

RB4/COM0

RB2

SEG2

RB3

TTL

—

CMOS General purpose I/O. Individually enabled pull-up.

AN LCD analog output.

CMOS General purpose I/O. Individually enabled pull-up.

AN LCD analog output.

TTL

—

SEG3

RB4

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

COM0

RB5

—

AN

LCD analog output.

RB5/COM1

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

COM1

RB6

—

AN

LCD analog output.

RB6/ICSPCLK/ICDCK/SEG14

RB7/ICSPDAT/ICDDAT/SEG13

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

ICSPCLK

ICDCK

SEG14

RB7

ST

—

ICSP™ clock.

ICD clock I/O.

AN

LCD analog output.

TTL

CMOS General purpose I/O. Individually controlled interrupt-on-

change. Individually enabled pull-up.

ICSPDAT

ICDDAT

SEG13

RC0

ST

—

CMOS ICSP Data I/O.

CMOS ICD Data I/O.

AN

CMOS General purpose I/O.

LCD analog input.

CMOS General purpose I/O.

LCD analog input.

CMOS General purpose I/O.

LCD analog input.

CMOS General purpose I/O.

AN LCD analog output.

CMOS General purpose I/O.

Timer1 gate input.

CMOS Serial data output.

AN LCD analog output.

CMOS General purpose I/O.

Timer1 clock input.

CMOS Capture 1 input/Compare 1 output/PWM 1 output.

AN LCD analog output.

LCD analog output.

RC0/VLCD1

ST

AN

ST

AN

ST

AN

ST

—

VLCD1

RC1

—

RC1/VLCD2

VLCD2

RC2

—

RC2/VLCD3

VLCD3

RC3

—

RC3/SEG6

SEG6

RC4

RC4/T1G/SDO/SEG11

ST

—

T1G

—

SDO

SEG11

RC5

—

RC5/T1CKI/CCP1/SEG10

ST

—

T1CKI

CCP1

SEG10

RC6

—

RC6/TX/CK/SCK/SCL/SEG9

ST

—

CMOS General purpose I/O.

TX

CMOS USART asynchronous serial transmit.

CMOS USART synchronous serial clock.

CMOS SPI™ clock.

CK

ST

—

SCK

2

SCL

CMOS I C™ clock.

SEG9

AN

LCD analog output.

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D = Direct

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917.

2: Pins available on PIC16F914/917 only.

Preliminary

DS41250E-page 11

PIC16F917/916/914/913

TABLE 1-1:

PIC16F91X PINOUT DESCRIPTIONS (CONTINUED)

Input Output

Type Type

Name

Function

Description

RC7/RX/DT/SDI/SDA/SEG8

RC7

RX

ST

—

CMOS General purpose I/O.

—

USART asynchronous serial receive.

DT

CMOS USART synchronous serial data.

CMOS SPI™ data input.

SDI

2

SDA

CMOS I C™ data.

SEG8

RD0

AN

CMOS General purpose I/O.

AN LCD analog output.

LCD analog output.

(1, 2)

RD0/COM3

ST

—

COM3

RD1

(2)

RD1

ST

—

CMOS General purpose I/O.

(2)

RD2/CCP2

RD2

CMOS General purpose I/O.

CCP2

RD3

CMOS Capture 2 input/Compare 2 output/PWM 2 output.

CMOS General purpose I/O.

(2)

RD3/SEG16

SEG16

RD4

AN

CMOS General purpose I/O.

AN LCD analog output.

CMOS General purpose I/O.

AN LCD analog output.

CMOS General purpose I/O.

AN LCD analog output.

CMOS General purpose I/O.

AN LCD analog output.

CMOS General purpose I/O.

LCD analog output.

(2)

RD4/SEG17

ST

—

SEG17

RD5

(2)

RD5/SEG18

ST

—

SEG18

RD6

(2)

RD6/SEG19

ST

—

SEG19

RD7

(2)

RD7/SEG20

ST

—

SEG20

RE0

(2)

RE0/AN5/SEG21

ST

AN

—

AN5

—

Analog input Channel 5.

LCD analog output.

SEG21

RE1

AN

(2)

RE1/AN6/SEG22

ST

AN

—

CMOS General purpose I/O.

AN6

—

Analog input Channel 6.

LCD analog output.

SEG22

RE2

AN

(2)

RE2/AN7/SEG23

ST

AN

—

CMOS General purpose I/O.

AN7

—

AN

—

Analog input Channel 7.

SEG23

RE3

LCD analog output.

RE3/MCLR/VPP

ST

HV

D

Digital input only.

MCLR

VPP

Master Clear with internal pull-up.

Programming voltage.

VDD

VSS

VDD

Power supply for microcontroller.

Ground reference for microcontroller.

VSS

D

Legend: AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

XTAL = Crystal

D = Direct

Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917.

2: Pins available on PIC16F914/917 only.

DS41250E-page 12

Preliminary

PIC16F917/916/914/913

FIGURE 2-2:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F916/917

2.0

2.1

MEMORY ORGANIZATION

Program Memory Organization

The PIC16F917/916/914/913 has a 13-bit program

counter capable of addressing a 4k x 14 program

memory space for the PIC16F913/914 (0000h-0FFFh)

and an 8k x 14 program memory space for the

PIC16F916/917 (0000h-1FFFh). Accessing a location

above the memory boundaries for the PIC16F913 and

PIC16F914 will cause a wrap around within the first 4k x

14 space. The Reset vector is at 0000h and the interrupt

vector is at 0004h.

pc<12:0>

CALL, RETURN

RETFIE, RETLW

13

Stack Level 1

Stack Level 2

Stack Level 8

Reset Vector

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK FOR THE

PIC16F913/914

0000h

Interrupt Vector

Page 0

0004h

0005h

pc<12:0>

CALL, RETURN

RETFIE, RETLW

07FFh

0800h

13

Page 1

On-chip

Program

Memory

Stack Level 1

Stack Level 2

0FFFh

1000h

Page 2

Page 3

17FFh

1800h

Stack Level 8

Reset Vector

0000h

1FFFh

Interrupt Vector

Page 0

0004h

0005h

On-chip

Program

Memory

07FFh

0800h

Page 1

0FFFh

1000h

1FFFh

Preliminary

DS41250E-page 13

PIC16F917/916/914/913

2.2

Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers (GPRs)

and the Special Function Registers (SFRs). Bits RP0

and RP1 are bank select bits.

RP0

RP1

(STATUS<6:5>)

=

00: → Bank 0

01: → Bank 1

10: → Bank 2

11: → Bank 3

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Function Registers. Above the Special Function

Registers are the General Purpose Registers,

implemented as static RAM. All implemented banks

contain Special Function Registers. Some frequently

used Special Function Registers from one bank are

mirrored in another bank for code reduction and

quicker access.

2.2.1

GENERAL PURPOSE REGISTER

FILE

The register file is organized as 256 x 8 in the

PIC16F913/914 and 352 x 8 in the PIC16F916/917.

Each register is accessed either directly or indirectly

through the File Select Register (FSR) (see Section 2.5

“Indirect Addressing, INDF and FSR Registers”).

2.2.2

SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral functions for controlling the

desired operation of the device (see Tables 2-1,

2-2, 2-3 and 2-4). These registers are static RAM.

The special registers can be classified into two sets:

core and peripheral. The Special Function Registers

associated with the “core” are described in this section.

Those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

DS41250E-page 14

Preliminary

PIC16F917/916/914/913

FIGURE 2-3:

PIC16F913/916 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Address

Indirect addr. ⁽¹⁾80h

Address

Indirect addr. ⁽¹⁾100h

Address

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

TRISA

TRISB

TRISC

WDTCON

PORTB

TRISB

LCDCON

LCDPS

PORTE

PCLATH

INTCON

PIR1

TRISE

PCLATH

INTCON

PIE1

LVDCON

PCLATH

INTCON

EEDATL

EEADRL

EEDATH

EEADRH

LCDDATA0

LCDDATA1

PCLATH

INTCON

EECON1

EECON2⁽¹⁾

PIR2

PIE2

TMR1L

TMR1H

T1CON

TMR2

PCON

OSCCON

OSCTUNE

ANSEL

PR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

SSPADD

SSPSTAT

WPUB

LCDDATA3

LCDDATA4

IOCB

LCDDATA6

LCDDATA7

CMCON1

TXSTA

SPBRG

LCDDATA9

General

Purpose

LCDDATA10 11Ah

11Bh

Register⁽²⁾

CMCON0

VRCON

LCDSE0

LCDSE1

11Ch

11Dh

11Eh

11Fh

120h

96 Bytes

ADRESH

ADCON0

ADRESL

ADCON1

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

80 Bytes

96 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F913, unimplemented data memory locations, read as ‘0’.

Preliminary

DS41250E-page 15

PIC16F917/916/914/913

FIGURE 2-4:

PIC16F914/917 SPECIAL FUNCTION REGISTERS

File

Address

Indirect addr. ⁽¹⁾00h

Address

Indirect addr. ⁽¹⁾80h

Address

Indirect addr. ⁽¹⁾100h

Address

Indirect addr. ⁽¹⁾180h

TMR0

PCL

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

OPTION_REG 81h

TMR0

PCL

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

OPTION_REG 181h

PCL

STATUS

FSR

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

PCL

STATUS

FSR

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

STATUS

FSR

STATUS

FSR

PORTA

PORTB

PORTC

PORTD

PORTE

PCLATH

INTCON

PIR1

TRISA

WDTCON

PORTB

TRISB

TRISC

TRISD

TRISE

LCDCON

LCDPS

LVDCON

PCLATH

INTCON

PCLATH

INTCON

PIE1

PCLATH

INTCON

EEDATL

EECON1

EECON2⁽¹⁾

PIR2

PIE2

EEADRL

EEDATH

EEADRH

LCDDATA0

LCDDATA1

LCDDATA2

LCDDATA3

LCDDATA4

LCDDATA5

LCDDATA6

LCDDATA7

LCDDATA8

LCDDATA9

TMR1L

TMR1H

T1CON

TMR2

PCON

OSCCON

OSCTUNE

ANSEL

PR2

T2CON

SSPBUF

SSPCON

CCPR2L

CCPR2H

CCP2CON

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

SSPADD

SSPSTAT

WPUB

IOCB

CMCON1

TXSTA

SPBRG

General

Purpose

LCDDATA10 11Ah

LCDDATA11 11Bh

Register⁽²⁾

CMCON0

VRCON

LCDSE0

LCDSE1

LCDSE2

11Ch

11Dh

11Eh

11Fh

120h

96 Bytes

CCPR2CON 1Dh

ADRESH

ADCON0

1Eh

1Fh

20h

ADRESL

ADCON1

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

80 Bytes

96 Bytes

EFh

F0h

FFh

16Fh

170h

17Fh

1EFh

1F0h

1FFh

accesses

70h-7Fh

accesses

70h-7Fh

accesses

70h-7Fh

7Fh

Bank 0

Bank 1

Bank 2

Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

2: On the PIC16F914, unimplemented data memory locations, read as ‘0’.

DS41250E-page 16

Preliminary

PIC16F917/916/914/913

TABLE 2-1:

PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 0

Value on

POR/BOR

Reset

Value on

all other

Resets⁽¹⁾

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 0

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

---- xxxx ---- uuuu

---0 0000 ---0 0000

0000 000x 0000 000x

0000 0000 0000 0000

0000 -0-0 0000 -0-0

xxxx xxxx uuuu uuuu

TMR0

PCL

Program Counter’s (PC) Least Significant Byte

STATUS

FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

PORTA

PORTB

PORTC

PORTD⁽²⁾

PORTE

PCLATH

INTCON

PIR1

RA7

RB7

RC7

RD7

—

RA6

RB6

RC6

RD6

—

RA5

RB5

RC5

RD5

—

RA4

RB4

RC4

RD4

—

RA3

RB3

RC3

RD3

RE3

RA2

RB2

RA1

RB1

RA0

RB0

RC2

RC1

RC0

RD2

RE2⁽²⁾

RD1

RE1⁽²⁾

RD0

RE0⁽²⁾

—

Write Buffer for upper 5 bits of Program Counter

GIE

PEIE

ADIF

C2IF

T0IE

RCIF

C1IF

INTE

TXIF

RBIE

SSPIF

—

T0IF

CCP1IF

LVDIF

INTF

TMR2IF

—

RBIF

EEIF

OSFIF

TMR1IF

CCP2IF

PIR2

LCDIF

TMR1L

TMR1H

T1CON

TMR2

Holding Register for the Least Significant Byte of the 16-bit TMR1

Holding Register for the Most Significant Byte of the 16-bit TMR1

T1GINV

T1GE

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

Timer2 Module Register

0000 0000 0000 0000

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

Synchronous Serial Port Receive Buffer/Transmit Register

WCOL SSPOV SSPEN CKP SSPM3

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

SSPM2

SSPM1

SSPM0

Capture/Compare/PWM Register 1 (LSB)

Capture/Compare/PWM Register 1 (MSB)

—

CCP1X

SREN

CCP1Y

CREN

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

SPEN

RX9

ADDEN

FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

USART Transmit Data Register

USART Receive Data Register

1Bh⁽²⁾CCPR2L

1Ch⁽²⁾CCPR2H

1Dh⁽²⁾CCP2CON

Capture/Compare/PWM Register 2 (LSB)

Capture/Compare/PWM Register 2 (MSB)

—

CCP2X

A/D Result Register High Byte

ADFM VCFG1 VCFG0

CCP2Y

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

1Eh

1Fh

ADRESH

ADCON0

xxxx xxxx uuuu uuuu

CHS2

CHS1

CHS0

GO/DONE

ADON

0000 0000 0000 0000

Legend:

Note 1:

2:

-= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

PIC16F914/917 only.

Preliminary

DS41250E-page 17

PIC16F917/916/914/913

TABLE 2-2:

PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1

Value on

POR/BOR

Reset

Value on

all other

Resets⁽¹⁾

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 1

80h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

register)

xxxx xxxx

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

OPTION_REG

PCL

RBPU

Program Counter’s (PC) Least Significant Byte

IRP RP1 RP0 TO

Indirect Data Memory Address Pointer

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

C

1111 1111

0000 0000

0001 1xxx

xxxx xxxx

1111 1111

0000 0000

000q quuu

uuuu uuuu

1111 1111

---- 1111

---0 0000

0000 000x

0000 0000

0000 -0-0

---u --uu

-110 x000

---u uuuu

1111 1111

0000 0000

1111 1111

0000 ----

---- --10

0000 -010

0000 0000

—

STATUS

FSR

PD

Z

DC

TRISA

TRISA7

TRISB7

TRISC7

TRISD7

—

TRISA6

TRISB6

TRISC6

TRISD6

—

TRISA5

TRISB5

TRISC5

TRISD5

—

TRISA4

TRISB4

TRISC4

TRISD4

—

TRISA3

TRISB3

TRISC3

TRISD3

TRISA2

TRISB2

TRISC2

TRISD2

TRISA1

TRISB1

TRISC1

TRISD1

TRISA0

TRISB0

TRISC0

TRISD0

TRISB

TRISC

TRISD⁽²⁾

TRISE

TRISE3⁽⁵⁾TRISE2⁽²⁾TRISE1⁽²⁾TRISE0⁽²⁾---- 1111

PCLATH

INTCON

PIE1

—

Write Buffer for the upper 5 bits of the Program Counter

---0 0000

0000 000x

0000 0000

0000 -0-0

---1 --qq

-110 q000

---0 0000

1111 1111

0000 0000

1111 1111

0000 ----

GIE

PEIE

ADIE

C2IE

—

T0IE

INTE

TXIE

RBIE

SSPIE

—

T0IF

CCP1IE

LVDIE

—

INTF

TMR2IE

—

RBIF

TMR1IE

CCP2IE

BOR

EEIE

OSFIE

—

RCIE

C1IE

—

PIE2

LCDIE

SBOREN

IRCF0

TUN4

PCON

—

POR

LTS

OSCCON

OSCTUNE

ANSEL

PR2

—

IRCF2

IRCF1

OSTS⁽⁴⁾

TUN3

ANS3

HTS

SCS

—

TUN2

ANS2

TUN1

ANS1

TUN0

ANS0

ANS7⁽³⁾

ANS6⁽³⁾

ANS5⁽³⁾

ANS4

Timer2 Period Register

Synchronous Serial Port (I²C mode) Address Register

SSPADD

SSPSTAT

WPUB

SMP

WPUB7

IOCB7

—

CKE

WPUB6

IOCB6

—

D/A

WPUB5

IOCB5

—

P

S

WPUB3

—

R/W

WPUB2

—

UA

WPUB1

—

BF

WPUB0

—

WPUB4

IOCB4

—

IOCB

CMCON1

TXSTA

SPBRG

—

T1GSS

TRMT

C2SYNC ---- --10

TX9D 0000 -010

CSRC

TX9

TXEN

SYNC

—

BRGH

SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000

Unimplemented

—

CMCON0

VRCON

ADRESL

ADCON1

C2OUT

VREN

C1OUT

C2INV

VRR

C1INV

—

CIS

CM2

VR2

CM1

VR1

CM0

VR0

0000 0000

0-0- 0000

xxxx xxxx

-000 ----

0000 0000

0-0- 0000

uuuu uuuu

-000 ---

—

VR3

A/D Result Register Low Byte

ADCS2 ADCS1

—

ADCS0

—

Legend:

-= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Note 1:

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

2:

3:

4:

PIC16F914/917 only.

PIC16F914/917 only, forced ‘0’ on PIC16F913/916.

The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.0 “Clock

Sources”.

5:

Bit is read-only; TRISE = 1always.

DS41250E-page 18

Preliminary

PIC16F917/916/914/913

TABLE 2-3:

PIC16F917/916/914/913 SPECIAL REGISTERS SUMMARY BANK 2

Value on

POR/BOR

Reset

Value on

all other

Resets⁽¹⁾

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 2

100h INDF

Addressing this location uses contents of FSR to address data memory (not a physical register)

Timer0 Module Register

xxxx xxxx xxxx xxxx

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

101h TMR0

102h PCL

Program Counter’s (PC) Least Significant Byte

103h STATUS

104h FSR

IRP

RP1

RP0

TO

PD

Z

DC

C

Indirect Data Memory Address Pointer

105h WDTCON

106h PORTB

107h LCDCON

108h LCDPS

109h LVDCON

10Ah PCLATH

10Bh INTCON

—

RB7

LCDEN

WFT

—

RB6

—

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 ---0 1000

RB5

RB4

VLCDEN

WA

RB3

CS1

LP3

—

RB2

CS0

RB1

LMUX1

LP1

RB0

LMUX0

LP0

xxxx xxxx uuuu uuuu

0001 0011 0001 0011

0000 0000 0000 0000

--00 -100 --00 -100

---0 0000 ---0 0000

0000 000x 0000 000x

SLPEN

BIASMD

—

WERR

LCDA

IRVST

—

LP2

LVDEN

LVDL2

LVDL1

LVDL0

—

Write Buffer for the upper 5 bits of the Program Counter

INTE RBIE T0IF INTF RBIF

GIE

PEIE

T0IE

EEDATL

EEADRL

EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000

EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000

10Ch

10Dh

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

10Eh EEDATH

10Fh EEADRH

110h LCDDATA0

—

--00 0000 --00 0000

---0 0000 ---0 0000

xxxx xxxx uuuu uuuu

EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

—

SEG7

COM0

SEG6

COM0

SEG5

COM0

SEG4

COM0

SEG3

COM0

SEG2

COM0

SEG1

COM0

SEG0

COM0

111h LCDDATA1

112h LCDDATA2⁽²⁾

113h LCDDATA3

114h LCDDATA4

115h LCDDATA5⁽²⁾

116h LCDDATA6

117h LCDDATA7

118h LCDDATA8⁽²⁾

119h LCDDATA9

11Ah LCDDATA10

SEG15

COM0

SEG14

COM0

SEG13

COM0

SEG12

COM0

SEG11

COM0

SEG10

COM0

SEG9

COM0

SEG8

COM0

xxxx xxxx uuuu uuuu

SEG23

COM0

SEG22

COM0

SEG21

COM0

SEG20

COM0

SEG19

COM0

SEG18

COM0

SEG17

COM0

SEG16

COM0

SEG7

COM1

SEG6

COM1

SEG5

COM1

SEG4

COM1

SEG3

COM1

SEG2

COM1

SEG1

COM1

SEG0

COM1

SEG15

COM1

SEG14

COM1

SEG13

COM1

SEG12

COM1

SEG11

COM1

SEG10

COM1

SEG9

COM1

SEG8

COM1

SEG23

COM1

SEG22

COM1

SEG21

COM1

SEG20

COM1

SEG19

COM1

SEG18

COM1

SEG17

COM1

SEG16

COM1

SEG7

COM2

SEG6

COM2

SEG5

COM2

SEG4

COM2

SEG3

COM2

SEG2

COM2

SEG1

COM2

SEG0

COM2

SEG15

COM2

SEG14

COM2

SEG13

COM2

SEG12

COM2

SEG11

COM2

SEG10

COM2

SEG9

COM2

SEG8

COM2

SEG23

COM2

SEG22

COM2

SEG21

COM2

SEG20

COM2

SEG19

COM2

SEG18

COM2

SEG17

COM2

SEG16

COM2

SEG7

COM3

SEG6

COM3

SEG5

COM3

SEG4

COM3

SEG3

COM3

SEG2

COM3

SEG1

COM3

SEG0

COM3

SEG15

COM3

SEG14

COM3

SEG13

COM3

SEG12

COM3

SEG11

COM3

SEG10

COM3

SEG9

COM3

SEG8

COM3

LCDDATA11⁽²⁾

11Bh

SEG23

COM3

SEG22

COM3

SEG21

COM3

SEG20

COM3

SEG19

COM3

SEG18

COM3

SEG17

COM3

SEG16

COM3

11Ch LCDSE0⁽³⁾

11Dh LCDSE1⁽³⁾

11Eh LCDSE2^(2,3)

SE7

SE15

SE23

SE6

SE14

SE22

SE5

SE13

SE21

SE4

SE12

SE20

SE3

SE11

SE19

SE2

SE10

SE18

SE1

SE9

SE0

SE8

0000 0000 uuuu uuuu

SE17

SE16

11Fh

—

Unimplemented

—

Legend:

Note 1:

-= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

PIC16F914/917 only.

2:

3:

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

Preliminary

DS41250E-page 19

PIC16F917/916/914/913

TABLE 2-4:

PIC16F917/916/914/913 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3

Value on

POR/BOR

Reset

Value on

all other

Resets⁽¹⁾

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bank 3

180h

INDF

Addressing this location uses contents of FSR to address data memory (not a physical

register)

xxxx xxxx xxxx xxxx

181h

182h

183h

184h

185h

OPTION_REG

PCL

RBPU

Program Counter (PC) Least Significant Byte

IRP RP1 RP0 TO

INTEDG

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111 1111 1111

0000 0000 0000 0000

0001 1xxx 000q quuu

xxxx xxxx uuuu uuuu

STATUS

FSR

PD

Z

DC

C

Indirect Data Memory Address Pointer

Unimplemented

—

186h

187h

188h

189h

18Ah

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0 1111 1111 1111 1111

—

Unimplemented

—

PCLATH

Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

—

T0IE

—

18Bh

18Ch

INTCON

EECON1

GIE

PEIE

—

INTE

—

RBIE

T0IF

INTF

WR

RBIF

RD

0000 000x 0000 000x

0--- x000 0--- q000

EEPGD

WRERR

WREN

18Dh

EECON2

EEPROM Control Register 2 (not a physical register)

---- ---- ---- ----

Legend:

-= Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition, shaded = unimplemented

Note 1:

Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41250E-page 20

Preliminary

PIC16F917/916/914/913

For example, CLRF STATUSwill clear the upper three

bits and set the Z bit. This leaves the Status register as

‘000u u1uu’ (where u= unchanged).

2.2.2.1

Status Register

The Status register, shown in Register 2-1, contains:

• the arithmetic status of the ALU

• the Reset status

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

Status register, because these instructions do not affect

any Status bits. For other instructions not affecting any

Status bits (see Section 17.0 “Instruction Set

Summary”).

• the bank select bits for data memory (SRAM)

The Status register can be the destination for any

instruction, like any other register. If the Status register

is the destination for an instruction that affects the Z,

DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

Status register as destination may be different than

intended.

Note 1: The C and DC bits operate as a Borrow

and Digit Borrow out bit, respectively, in

subtraction. See the SUBLW and SUBWF

instructions for examples.

REGISTER 2-1:

STATUS – STATUS REGISTER (ADDRESS: 03h, 83h, 103h OR 183h)

R/W-0

IRP

R/W-0

RP1

R/W-0

RP0

R-1

TO

R-1

PD

R/W-x

Z

R/W-x

DC

R/W-x

C

bit 7

bit 0

bit 7

IRP: Register Bank Select bit (used for indirect addressing)

1= Bank 2, 3 (100h-1FFh)

0= Bank 0, 1 (00h-FFh)

bit 6-5

RP<1:0>: Register Bank Select bits (used for direct addressing)

00= Bank 0 (00h-7Fh)

01= Bank 1 (80h-FFh)

10= Bank 2 (100h-17Fh)

11= Bank 3 (180h-1FFh)

bit 4

bit 3

bit 2

bit 1

bit 0

TO: Time-out bit

1= After power-up, CLRWDTinstruction or SLEEPinstruction

0= A WDT time-out occurred

PD: Power-down bit

1= After power-up or by the CLRWDTinstruction

0= By execution of the SLEEPinstruction

Z: Zero bit

1= The result of an arithmetic or logic operation is zero

0= The result of an arithmetic or logic operation is not zero

DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWFinstructions)⁽¹⁾

1= A carry-out from the 4th low-order bit of the result occurred

0= No carry-out from the 4th low-order bit of the result

C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)⁽¹⁾

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low-order bit of the source register.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 21

PIC16F917/916/914/913

2.2.2.2

Option Register

Note:

To achieve a 1:1 prescaler assignment for

TMR0, assign the prescaler to the WDT by

setting PSA bit to ‘1’ (OPTION_REG<3>).

See Section 5.4 “Prescaler”.

The Option register is a readable and writable register,

which contains various control bits to configure:

• TMR0/WDT prescaler

• External RB0/INT interrupt

• TMR0

• Weak pull-ups on PORTB

REGISTER 2-2:

OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBPU: PORTB Pull-up Enable bit

1= PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RB0/INT/SEG0 pin

0= Interrupt on falling edge of RB0/INT/SEG0 pin

T0CS: TMR0 Clock Source Select bit

1= Transition on RA4/C1OUT/T0CKI/SEG4 pin

0= Internal instruction cycle clock (CLKO)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin

0= Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value

TMR0 Rate WDT Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

DS41250E-page 22

Preliminary

PIC16F917/916/914/913

2.2.2.3

INTCON Register

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to

enabling an interrupt.

The INTCON register is a readable and writable

register, which contains the various enable and flag bits

for TMR0 register overflow, PORTB change and

external RB0/INT/SEG0 pin interrupts.

REGISTER 2-3:

INTCON – INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh OR

18Bh)

R/W-0

GIE

R/W-0

PEIE

R/W-0

T0IE

R/W-0

INTE

R/W-0

RBIE

R/W-0

T0IF

R/W-0

INTF

R/W-x

RBIF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

GIE: Global Interrupt Enable bit

1= Enables all unmasked interrupts

0= Disables all interrupts

PEIE: Peripheral Interrupt Enable bit

1= Enables all unmasked peripheral interrupts

0= Disables all peripheral interrupts

T0IE: TMR0 Overflow Interrupt Enable bit

1= Enables the TMR0 interrupt

0= Disables the TMR0 interrupt

INTE: RB0/INT/SEG0 External Interrupt Enable bit

1= Enables the RB0/INT/SEG0 external interrupt

0= Disables the RB0/INT/SEF0 external interrupt

RBIE: PORTB Change Interrupt Enable bit⁽¹⁾

1= Enables the PORTB change interrupt

0= Disables the PORTB change interrupt

T0IF: TMR0 Overflow Interrupt Flag bit⁽²⁾

1= TMR0 register has overflowed (must be cleared in software)

0= TMR0 register did not overflow

INTF: RB0/INT/SEG0 External Interrupt Flag bit

1= The RB0/INT/SEG0 external interrupt occurred (must be cleared in software)

0= The RB0/INT/SEG0 external interrupt did not occur

RBIF: PORTB Change Interrupt Flag bit

1= When at least one of the PORTB <5:0> pins changed state (must be cleared in software)

0= None of the PORTB <7:4> pins have changed state

Note 1: IOCB register must also be enabled.

2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should

be initialized before clearing T0IF bit.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 23

PIC16F917/916/914/913

2.2.2.4

PIE1 Register

The PIE1 register contains the interrupt enable bits, as

shown in Register 2-1.

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-4:

PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)

R/W-0

EEIE

R/W-0

ADIE

R/W-0

RCIE

R/W-0

TXIE

R/W-0

SSPIE

R/W-0

TMR1IE

bit 0

CCP1IE TMR2IE

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

EEIE: EE Write Complete Interrupt Enable bit

1= Enabled

0= Disabled

ADIE: A/D Converter Interrupt Enable bit

1= Enabled

0= Disabled

RCIE: USART Receive Interrupt Enable bit

1= Enabled

0= Disabled

TXIE: USART Transmit Interrupt Enable bit

1= Enabled

0= Disabled

SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit

1= Enabled

0= Disabled

CCP1IE: CCP1 Interrupt Enable bit

1= Enabled

0= Disabled

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1= Enabled

0= Disabled

TMR1IE: TMR1 Overflow Interrupt Enable bit

1= Enabled

0= Disabled

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 24

Preliminary

PIC16F917/916/914/913

2.2.2.5

PIE2 Register

The PIE2 register contains the interrupt enable bits, as

shown in Register 2-5.

Note:

Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

REGISTER 2-5:

PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS: 8Dh)

R/W-0

OSFIE

R/W-0

C2IE

R/W-0

C1IE

R/W-0

LCDIE

U-0

—

R/W-0

LVDIE

U-0

—

R/W-0

CCP2IE

bit 0

bit 7

bit 6

bit 5

bit 4

OSFIE: Oscillator Fail Interrupt Enable bit

1= Enabled

0= Disabled

C2IE: Comparator 2 Interrupt Enable bit

1= Enables Comparator 2 interrupt

0= Disables Comparator 2 interrupt

C1IE: Comparator 1 Interrupt Enable bit

1= Enables Comparator 1 interrupt

0= Disables Comparator 1 interrupt

LCDIE: LCD Module Interrupt Enable bit

1= LCD interrupt is enabled

0= LCD interrupt is disabled

bit 3

bit 2

Unimplemented: Read as ‘0’

LVDIE: Low Voltage Detect Interrupt Enable bit

1= Enables LVD Interrupt

0= Disables LVD Interrupt

bit 1

bit 0

Unimplemented: Read as ‘0’

CCP2IE: CCP2 Interrupt Enable bit (only available in 16F914/917)

1= Enables the CCP2 interrupt

0= Disables the CCP2 interrupt

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 25

PIC16F917/916/914/913

2.2.2.6

PIR1 Register

The PIR1 register contains the interrupt flag bits, as

shown in Register 2-6.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

REGISTER 2-6:

PIR1 – PERIPHERAL INTERRUPT REQUEST REGISTER 1 (ADDRESS: 0Ch)

R/W-0

EEIF

R/W-0

ADIF

R-0

R/W-0

SSPIF

R/W-0

TMR1IF

bit 0

RCIF

TXIF

CCP1IF TMR2IF

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

EEIF: EE Write Operation Interrupt Flag bit

1= The write operation completed (must be cleared in software)

0= The write operation has not completed or has not started

ADIF: A/D Converter Interrupt Flag bit

1= The A/D conversion completed (must be cleared in software)

0= The A/D conversion is not complete

RCIF: USART Receive Interrupt Flag bit

1= The USART receive buffer is full (cleared by reading RCREG)

0= The USART receive buffer is not full

TXIF: USART Transmit Interrupt Flag bit

1= The USART transmit buffer is empty (cleared by writing to TXREG)

0= The USART transmit buffer is full

SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit

1= The Transmission/Reception is complete (must be cleared in software)

0= Waiting to Transmit/Receive

CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare Mode

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode

Unused in this mode

bit 1

bit 0

TMR2IF: TMR2 to PR2 Interrupt Flag bit

1= A TMR2 to PR2 match occurred (must be cleared in software)

0= No TMR2 to PR2 match occurred

TMR1IF: TMR1 Overflow Interrupt Flag bit

1= The TMR1 register overflowed (must be cleared in software)

0= The TMR1 register did not overflow

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 26

Preliminary

PIC16F917/916/914/913

2.2.2.7

PIR2 Register

The PIR2 register contains the interrupt flag bits, as

shown in Register 2-7.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

REGISTER 2-7:

PIR2 – PERIPHERAL INTERRUPT REQUEST REGISTER 2 (ADDRESS: 0Dh)

R/W-0

OSFIF

R/W-0

C2IF

R-0

U-0

—

R/W-0

LVDIF

U-0

—

R/W-0

CCP2IF

bit 0

C1IF

LCDIF

bit 7

bit 6

bit 5

bit 4

OSFIF: Oscillator Fail Interrupt Flag bit

1= System oscillator failed, clock input has changed to INTOSC (must be cleared in software)

0= System clock operating

C2IF: Comparator 2 Interrupt Flag bit

1= Comparator output (C2OUT bit) has changed (must be cleared in software)

0= Comparator output (C2OUT bit) has not changed

C1IF: Comparator 1 Interrupt Flag bit

1= Comparator output (C1OUT bit) has changed (must be cleared in software)

0= Comparator output (C1OUT bit) has not changed

LCDIF: LCD Module Interrupt bit

1= LCD has generated an interrupt

0= LCD has not generated an interrupt

bit 3

bit 2

Unimplemented: Read as ‘0’

LVDIF: Low Voltage Detect Interrupt Flag bit

1= LVD has generated an interrupt

0= LVD has not generated an interrupt

bit 1

bit 0

Unimplemented: Read as ‘0’

CCP2IF: CCP2 Interrupt Flag bit (only available in 16F914/917)

Capture Mode

1= A TMR1 register capture occurred (must be cleared in software)

0= No TMR1 register capture occurred

Compare Mode

1= A TMR1 register compare match occurred (must be cleared in software)

0= No TMR1 register compare match occurred

PWM mode

Unused in this mode

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 27

PIC16F917/916/914/913

2.2.2.8

PCON Register

The Power Control (PCON) register (See Table 17-2)

contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Watchdog Timer Reset (WDT)

• External MCLR Reset

The PCON register also controls the software enable of

the BOR.

The PCON register bits are shown in Register 2-8.

REGISTER 2-8:

PCON – POWER CONTROL REGISTER (ADDRESS: 8Eh)

U-0

R/W-1

U-0

R/W-0

POR

R/W-x

BOR

—

SBOREN

—

bit 7

bit 0

bit 7-5

bit 4

Unimplemented: Read as ‘0’

SBOREN: Software BOR Enable bit⁽¹⁾

1= BOR enabled

0= BOR disabled

bit 3-2

bit 1

Unimplemented: Read as ‘0’

POR: Power-on Reset Status bit

1= No Power-on Reset occurred

0= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0

BOR: Brown-out Reset Status bit

1= No Brown-out Reset occurred

0= A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: BOREN<1:0> = 01in the Configuration Word register for this bit to control the BOR.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 28

Preliminary

PIC16F917/916/914/913

2.3

PCL and PCLATH

Note 1: There are no Status bits to indicate stack

The Program Counter (PC) is 13 bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The high byte (PC<12:8>) is not

directly readable or writable and comes from

PCLATH. On any Reset, the PC is cleared. Figure 2-5

shows the two situations for the loading of the PC. The

upper example in Figure 2-5 shows how the PC is

loaded on a write to PCL (PCLATH<4:0> → PCH).

The lower example in Figure 2-5 shows how the PC is

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW and RETFIE instruc-

tions or the vectoring to an interrupt

address.

loaded during

(PCLATH<4:3> → PCH).

a

CALL or GOTO instruction

2.4

Program Memory Paging

All PIC16F917/916/914/913 devices are capable of

addressing a continuous 8K word block of program

memory. The CALLand GOTOinstructions provide only

11 bits of address to allow branching within any 2K pro-

gram memory page. When doing a CALL or GOTO

instruction, the upper 2 bits of the address are provided

by PCLATH<4:3>. When doing a CALLor GOTOinstruc-

tion, the user must ensure that the page select bits are

programmed so that the desired program memory

page is addressed. If a return from a CALLinstruction

(or interrupt) is executed, the entire 13-bit PC is POPed

off the stack. Therefore, manipulation of the

PCLATH<4:3> bits is not required for the RETURN

instructions (which POPs the address from the stack).

FIGURE 2-5:

LOADING OF PC IN

DIFFERENT SITUATIONS

PCH

PCL

Instruction with

12

8

7

0

PCL as

Destination

PC

8

PCLATH<4:0>

PCLATH

5

ALU Result

PCH

12 11 10

PC

PCL

8

7

0

GOTO, CALL

Note:

The contents of the PCLATH register are

unchanged after a RETURN or RETFIE

instruction is executed. The user must

rewrite the contents of the PCLATH regis-

ter for any subsequent subroutine calls or

GOTOinstructions.

PCLATH<4:3>

PCLATH

11

2

OPCODE<10:0>

2.3.1

COMPUTED GOTO

Example 2-1 shows the calling of a subroutine in

page 1 of the program memory. This example assumes

that PCLATH is saved and restored by the Interrupt

Service Routine (if interrupts are used).

A computed GOTOis accomplished by adding an offset

to the program counter (ADDWF PCL). When perform-

ing a table read using a computed GOTOmethod, care

should be exercised if the table location crosses a PCL

memory boundary (each 256-byte block). Refer to the

Application Note AN556, “Implementing a Table Read”

(DS00556).

EXAMPLE 2-1:

CALL OF A SUBROUTINE

IN PAGE 1 FROM PAGE 0

ORG 0x500

BCF PCLATH,4

BSF PCLATH,3 ;Select page 1

;(800h-FFFh)

CALL SUB1_P1 ;Call subroutine in

:

2.3.2

The

STACK

PIC16F917/916/914/913

family

has

an

8-level x 13-bit wide hardware stack (see Figures 2-1

and 2-2). The stack space is not part of either program

or data space and the Stack Pointer is not readable or

writable. The PC is PUSHed onto the stack when a

CALLinstruction is executed or an interrupt causes a

branch. The stack is POPed in the event of a RETURN,

RETLWor a RETFIEinstruction execution. PCLATH is

not affected by a PUSH or POP operation.

;page 1 (800h-FFFh)

:

ORG 0x900

;page 1 (800h-FFFh)

SUB1_P1

:

;called subroutine

;page 1 (800h-FFFh)

:

RETURN

;return to

;Call subroutine

;in page 0

;(000h-7FFh)

The stack operates as a circular buffer. This means that

after the stack has been PUSHed eight times, the ninth

PUSH overwrites the value that was stored from the

first PUSH. The tenth PUSH overwrites the second

PUSH (and so on).

Preliminary

DS41250E-page 29

PIC16F917/916/914/913

EXAMPLE 2-2:

INDIRECT ADDRESSING

2.5

Indirect Addressing, INDF and

FSR Registers

MOVLW

MOVWF

0x20

FSR

;initialize pointer

;to RAM

The INDF register is not a physical register. Addressing

the INDF register will cause indirect addressing.

NEXTCLRF

INCF

INDF

FSR

;clear INDF register

;inc pointer

BTFSS

GOTO

CONTINUE

FSR,4

;no clear next

;yes continue

Indirect addressing is possible by using the INDF

register. Any instruction using the INDF register

actually accesses data pointed to by the File Select

Register (FSR). Reading INDF itself indirectly will

produce 00h. Writing to the INDF register indirectly

results in a no operation (although Status bits may be

affected). An effective 9-bit address is obtained by

concatenating the 8-bit FSR register and the IRP bit

(STATUS<7>), as shown in Figure 2-6.

A simple program to clear RAM location 20h-2Fh using

indirect addressing is shown in Example 2-2.

FIGURE 2-6:

DIRECT/INDIRECT ADDRESSING PIC16F917/916/914/913

Direct Addressing

From Opcode

Indirect Addressing

7

RP1

RP0

6

0

IRP

File Select Register

Bank Select

180h

Location Select

Bank Select

Location Select

00h

00

01

10

11

Data

Memory

7Fh

1FFh

Bank 0

Bank 1

Bank 2

Bank 3

Note:

For memory map detail, see Figures 2-3 and 2-4.

DS41250E-page 30

Preliminary

PIC16F917/916/914/913

EXAMPLE 3-1:

INITIALIZING PORTA

3.0

I/O PORTS

BCF

CLRF

BSF

BCF

MOVLW

MOVWF

CLF

MOVLW

MOVWF

STATUS,RP0

STATUS,RP1

PORTA

STATUS,RP0

STATUS,RP1

07h

CMCON0

ANSEL

;Bank 0

;

;Init PORTA

;Bank 1

;

;Set RA<2:0> to

;digital I/O

;Make all PORTA I/O

;Set RA<7:4> as inputs

;and set RA<3:0>

; as outputs

;Bank 0

This device includes four 8-bit port registers along with

their corresponding TRIS registers and one four bit

port:

• PORTA and TRISA

• PORTB and TRISB

• PORTC and TRISC

• PORTD and TRISD

• PORTE and TRISE

F0h

TRISA

PORTA, PORTB, PORTC and RE3/MCLR/VPP are

implemented on all devices. PORTD and RE<2:0> are

implemented only on the PIC16F914 and PIC16F917.

BCF

STATUS,RP0

STATUS,RP1

;

3.1

PORTA and TRISA Registers

PORTA is

a 8-bit wide, bidirectional port. The

corresponding data direction register is TRISA

(Register 3-2). Setting a TRISA bit (= 1) will make the

corresponding PORTA pin an input (i.e., put the

corresponding output driver in a High-impedance mode).

Clearing a TRISA bit (= 0) will make the corresponding

PORTA pin an output (i.e., put the contents of the output

latch on the selected pin). Example 3-1 shows how to

initialize PORTA.

Five of the pins of PORTA can be configured as analog

inputs. These pins, RA5 and RA<3:0>, are configured

as analog inputs on device power-up and must be

reconfigured by the user to be used as I/O’s. This is

done by writing the appropriate values to the CMCON0

and ANSEL registers (see Example 3-1).

Reading the PORTA register (Register 3-1) reads the

status of the pins, whereas writing to it will write to the

port latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then written

to the port data latch.

The TRISA register controls the direction of the

PORTA pins, even when they are being used as analog

inputs. The user must ensure the bits in the TRISA

register are maintained set when using them as analog

inputs. I/O pins configured as analog input always read

‘0’.

Note 1: The CMCON0 (9Ch) register must be

initialized to configure an analog channel

as a digital input. Pins configured as

analog inputs will read ‘0’.

2: Analog lines that carry LCD signals

(i.e., SEGx, COMy, where x and y are

segment and common identifiers) are

shown as direct connections to the device

pins. The signals are outputs from the

LCD module and may be tri-stated,

depending on the configuration of the

LCD module.

Preliminary

DS41250E-page 31

PIC16F917/916/914/913

REGISTER 3-1:

PORTA – PORTA REGISTER (ADDRESS: 05h)

R/W-x

RA7

R/W-x

RA6

R/W-x

RA5

R/W-x

RA4

R/W-x

RA3

R/W-x

RA2

R/W-x

RA1

R/W-x

RA0

bit 7

bit 0

bit 7-0

RA<7:0>: PORTA I/O Pin bits

1= Port pin is >VIH

0= Port pin is <VIL

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 3-2:

TRISA – PORTA TRI-STATE REGISTER (ADDRESS: 85h)

R/W-1

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

bit 7

bit 0

bit 7-0

TRISA<7:0>: PORTA Tri-State Control bits

1= PORTA pin configured as an input (tri-stated)

0= PORTA pin configured as an output

Note:

TRISA<7:6> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS41250E-page 32

Preliminary

PIC16F917/916/914/913

3.1.1

PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTA pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions,

refer to the appropriate section in this data sheet.

3.1.1.1

RA0/AN0/C1-/SEG12

Figure 3-1 shows the diagram for this pin. The

RA0/AN0/C1-/SEG12 pin is configurable to function as

one of the following:

• a general purpose I/O

• an analog input for the A/D

• an analog input for Comparator 1

• an analog output for the LCD

FIGURE 3-1:

BLOCK DIAGRAM OF RA0/AN0/C1-/SEG12

Data Bus

D

Q

WR PORTA

WR TRISA

VDD

CK

Q

Data Latch

D

Q

I/O Pin

CK

Q

TRIS Latch

Analog Input or

SE12 and LCDEN

TTL

Input Buffer

RD TRISA

SE12 and LCDEN

RD PORTA

SEG12

SE12 and LCDEN

To A/D Converter or Comparator

Preliminary

DS41250E-page 33

PIC16F917/916/914/913

3.1.1.2

RA1/AN1/C2-/SEG7

Figure 3-2 shows the diagram for this pin. The

RA1/AN1/C2-/SEG7 pin is configurable to function as

one of the following:

• a general purpose I/O

• an analog input for the A/D

• an analog input for Comparator 2

• an analog output for the LCD

FIGURE 3-2:

BLOCK DIAGRAM OF RA1/AN1/C2-/SEG7

Data Bus

D

Q

WR PORTA

VDD

CK

Q

Data Latch

D

Q

I/O Pin

WR TRISA

CK

Q

TRIS Latch

Analog Input or

SE7 and LCDEN

TTL

Input Buffer

RD TRISA

SE7 and LCDEN

RD PORTA

SEG7

SE7 and LCDEN

To A/D Converter or Comparator

DS41250E-page 34

Preliminary

PIC16F917/916/914/913

3.1.1.3

RA2/AN2/C2+/VREF-/COM2

Figure 3-3 shows the diagram for this pin. The

RA2/AN2/C2+/VREF-/COM2 pin is configurable to

function as one of the following:

• a general purpose I/O

• an analog input for the A/D

• an analog input for Comparator 2

• a voltage reference input for the A/D

• an analog output for the LCD

FIGURE 3-3:

BLOCK DIAGRAM OF RA2/AN2/C2+/VREF-/COM2

Data Bus

D

Q

WR PORTA

WR TRISA

VDD

CK

Data Latch

D

Q

I/O Pin

CK

Q

TRIS Latch

Analog Input or

LCDEN and

LMUX<1:0> = 1X

RD TRISA

LCDEN and

TTL

Input Buffer

LMUX<1:0> = 1X

RD PORTA

COM2

LCDEN and

LMUX<1:0> = 1X

To A/D Converter or Comparator

To A/D Module VREF- Input

Preliminary

DS41250E-page 35

PIC16F917/916/914/913

3.1.1.4

Figure 3-4 shows the diagram for this pin. The

RA3/AN3/C1+/VREF+/COM3/SEG15 pin is

RA3/AN3/C1+/VREF+/COM3/SEG15

configurable to function as one of the following:

• a general purpose input

• an analog input for the A/D

• an analog input from Comparator 1

• a voltage reference input for the A/D

• analog outputs for the LCD

FIGURE 3-4:

BLOCK DIAGRAM OF RA3/AN3/C1+/VREF+/COM3/SEG15

Data Bus

D

Q

VDD

VSS

WR PORTA

CK

Data Latch

Q

D

I/O Pin

WR TRISA

CK

Q

TRIS Latch

Analog Input or

LCDMODE_EN⁽²⁾

TTL

Input Buffer

LCDMODE_EN⁽²⁾

RD TRISA

RD PORTA

LCDMODE_EN⁽²⁾

COM3⁽¹⁾or SEG15

To A/D Converter or Comparator

To A/D Module VREF+ Input

Note 1: PIC16F913/916 only.

2: For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11).

For the PIC16F914/917, the LCDMODE_EN = LCDEN and SE15.

DS41250E-page 36

Preliminary

PIC16F917/916/914/913

3.1.1.5

RA4/C1OUT/T0CKI/SEG4

Figure 3-5 shows the diagram for this pin. The

RA4/C1OUT/T0CKI/SEG4 pin is configurable to

function as one of the following:

• a general purpose I/O

• a digital output from Comparator 1

• a clock input for TMR0

• an analog output for the LCD

FIGURE 3-5:

BLOCK DIAGRAM OF RA4/C1OUT/T0CKI/SEG4

CM<2:0> = 110or 101

C1OUT

1

Data Bus

0

D

Q

VDD

WR PORTA

CK

Data Latch

Q

I/O Pin

D

Q

WR TRISA

VSS

CK

Q

TRIS Latch

Analog Input or

SE4 and LCDEN

TTL

Input Buffer

RD TRISA

SE4 and LCDEN

RD PORTA

T0CKI

SE4 and LCDEN

Schmitt

Trigger

SE4 and LCDEN

SEG4

Preliminary

DS41250E-page 37

PIC16F917/916/914/913

3.1.1.6

RA5/AN4/C2OUT/SS/SEG5

Figure 3-6 shows the diagram for this pin. The

RA5/AN4/C2OUT/SS/SEG5 pin is configurable to

function as one of the following:

• a general purpose I/O

• a digital output from Comparator 2

• a slave select input

• an analog output for the LCD

• an analog input for the A/D

FIGURE 3-6:

BLOCK DIAGRAM OF RA5/AN4/C2OUT/SS/SEG5

CM<2:0> = 110or 101

C2OUT

1

Data Bus

0

D

Q

VDD

WR PORTA

CK

Data Latch

I/O Pin

D

Q

WR TRISA

VSS

CK

Q

TRIS Latch

RD TRISA

Analog Input or

SE5 and LCDEN

TTL

Input Buffer

SE5 and LCDEN

RD PORTA

To SS Input

SE5 and LCDEN

SEG5

AN4

DS41250E-page 38

Preliminary

PIC16F917/916/914/913

3.1.1.7

RA6/OSC2/CLKO/T1OSO

Figure 3-7 shows the diagram for this pin. The

RA6/OSC2/CLKO/T1OSO pin is configurable to

function as one of the following:

• a general purpose I/O

• a crystal/resonator connection

• a clock output

• a TMR1 oscillator connection

FIGURE 3-7:

BLOCK DIAGRAM OF RA6/OSC2/CLKO/T1OSO

From OSC1

Oscillator

Circuit

FOSC = 1x1

CLKO (FOSC/4)

1

0

Data Bus

D

Q

VDD

WR PORTA

CK

Q

Data Latch

RA6/OSC2/

CLKO/T1OSO

D

Q

WR TRISA

VSS

CK

Q

FOSC = 00x, 010

TRIS Latch

FOSC = 00x, 010

or T1OSCEN

TTL

Input Buffer

RD TRISA

RD PORTA

Preliminary

DS41250E-page 39

PIC16F917/916/914/913

3.1.1.8

RA7/OSC1/CLKI/T1OSI

Figure 3-8 shows the diagram for this pin. The

RA7/OSC1/CLKI/T1OSI pin is configurable to function

as one of the following:

• a general purpose I/O

• a crystal/resonator connection

• a clock input

• a TMR1 oscillator connection

FIGURE 3-8:

BLOCK DIAGRAM OF RA7/OSC1/CLKI/T1OSI

From OSC1

Oscillator

Circuit

FOSC = 011

Data Bus

D

Q

WR PORTA

CK

VDD

Data Latch

D

Q

RA7/OSC1/

CLKI/T1OSI

WR TRISA

CK

FOSC = 10x

TRIS Latch

FOSC = 10x

TTL

Input Buffer

RD TRISA

RD PORTA

TABLE 3-1:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

10h

14h

1Fh

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xxxx xxxx uuuu uuuu

T1CON

T1GINV

WCOL

ADFM

T1GE

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

SSPCON

ADCON0

SSPOV

VCFG1

SSPEN

VCFG0

CKP

SSPM3

CHS1

SSPM2

CHS0

SSPM1

SSPM0 0000 0000 0000 0000

CHS2

GO/DONE

ADON

PS0

0000 0000 0000 0000

1111 1111 1111 1111

81h/181h OPTION_REG RBPU

INTEDG

T0CS

TRISA5

ANS5

C2INV

WERR

SE5

T0SE

TRISA4

ANS4

PSA

TRISA3

ANS3

CIS

PS2

TRISA2

ANS2

CM2

PS1

TRISA1

ANS1

CM1

85h

TRISA

TRISA7 TRISA6

ANS7 ANS6

C2OUT C1OUT

TRISA0 1111 1111 1111 1111

91h

ANSEL

ANS0

CM0

1111 1111 1111 1111

0000 0000 0000 0000

9Ch

107h

11Ch

11Dh

CMCON0

LCDCON

LCDSE0⁽¹⁾

LCDSE1⁽¹⁾

C1INV

VLCDEN

SE4

LCDEN

SE7

SLPEN

SE6

CS1

CS0

LMUX1

SE1

LMUX0 0001 0011 0001 0011

SE3

SE2

SE0

SE8

0000 0000 uuuu uuuu

SE15

SE14

SE13

SE12

SE11

SE10

SE9

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1:

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

DS41250E-page 40

Preliminary

PIC16F917/916/914/913

3.2

PORTB and TRISB Registers

3.3

Additional PORTB Pin Functions

PORTB is a general purpose I/O port with similar

functionality as the PIC16F77. All PORTB pins can have

a weak pull-up feature, and PORTB<7:4> implements an

interrupt-on-input change function.

RB<7:6> are used as data and clock signals, respectively,

for both serial programming and the in-circuit debugger

features on the device. Also, RB0 can be configured as an

external interrupt input.

PORTB is also used for the Serial Flash programming

interface.

3.3.1

WEAK PULL-UPS

Each of the PORTB pins has an individually configurable

internal weak pull-up. Control bits WPUB<7:0> enable or

disable each pull-up. Refer to Register 3-6. Each weak

pull-up is automatically turned off when the port pin is

configured as an output. The pull-ups are disabled on a

Power-on Reset by the RBPU bit (OPTION_REG<7>).

Note:

Analog lines that carry LCD signals

(i.e., SEGx, COMy, where x and y are seg-

ment and common identifiers) are shown

as direct connections to the device pins.

The signals are outputs from the LCD

module and may be tri-stated, depending

on the configuration of the LCD module.

3.3.2

INTERRUPT-ON-CHANGE

Four of the PORTB pins are individually configurable

as an interrupt-on-change pin. Control bits IOCB<7:4>

enable or disable the interrupt function for each pin.

Refer to Register 3-5. The interrupt-on-change feature

is disabled on a Power-on Reset.

EXAMPLE 3-2:

INITIALIZING PORTB

BCF

STATUS,RP0 ;Bank 0

BCF

CLRF

BSF

STATUS,RP1

PORTB

STATUS,RP0 ;Bank 1

;

;Init PORTB

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

PORTB. The ‘mismatch’ outputs of the last read are

OR’d together to set the PORTB Change Interrupt flag

bit (RBIF) in the INTCON register (Register 2-3).

BCF

STATUS,RP1

FFh

TRISB

STATUS,RP0 ;Bank 0

STATUS,RP1

;

MOVLW

MOVWF

BCF

;Set RB<7:0> as inputs

;

BCF

;

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear the flag bit RBIF.

A mismatch condition will continue to set flag bit RBIF.

Reading or writing PORTB will end the mismatch con-

dition and allow flag bit RBIF to be cleared. The latch

holding the last read value is not affected by a MCLR

nor Brown-out Reset. After these Resets, the RBIF flag

will continue to be set if a mismatch is present.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set. Furthermore,

since a read or write on a port affects all bits

of that port, care must be taken when using

multiple pins in Interrupt-on-change mode.

Changes on one pin may not be seen while

servicing changes on another pin.

Preliminary

DS41250E-page 41

PIC16F917/916/914/913

REGISTER 3-3:

PORTB – PORTB REGISTER (ADDRESS: 06h OR 106h)

R/W-x

RB7

R/W-x

RB6

R/W-x

RB5

R/W-x

RB4

R/W-x

RB3

R/W-x

RB2

R/W-x

RB1

R/W-x

RB0

bit 7

bit 0

bit 7-0

RB<7:0>: PORTB I/O Pin bits

1= Port pin is >VIH

0= Port pin is <VIL

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 3-4:

TRISB – PORTB TRI-STATE REGISTER (ADDRESS: 86h, 186h)

R/W-1

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1

TRISB0

bit 7

bit 0

bit 7-0

TRISB<7:0>: PORTB Tri-State Control bits

1= PORTB pin configured as an input (tri-stated)

0= PORTB pin configured as an output

Note:

TRISB<7:6> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

REGISTER 3-5:

IOCB – PORTB INTERRUPT-ON-CHANGE REGISTER (ADDRESS: 96h)

R/W-0

IOCB7

R/W-0

IOCB6

R/W-0

IOCB5

R/W-0

IOCB4

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

bit 7-4

bit 3-0

IOCB<7:4>: Interrupt-on-Change bits

1= Interrupt-on-change enabled

0= Interrupt-on-change disabled

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 42

Preliminary

PIC16F917/916/914/913

REGISTER 3-6:

WPUB – WEAK PULL-UP REGISTER (ADDRESS: 95h)

R/W-1

WPUB7

WPUB6

WPUB5

WPUB4

WPUB3

WPUB2

WPUB1

WPUB0

bit 7

bit 0

bit 7-0

WPUB<7:0>: Weak Pull-up Register bits

1= Pull-up enabled

0= Pull-up disabled

Note 1: Global RBPU must be enabled for individual pull-ups to be enabled.

2: The weak pull-up device is automatically disabled if the pin is in Output mode

(TRISB<7:0> = 0).

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 43

PIC16F917/916/914/913

3.3.3

PIN DESCRIPTIONS AND

DIAGRAMS

Each PORTB pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the LCD or interrupts, refer to the appropriate

section in this data sheet.

3.3.3.1

RB0/INT/SEG0

Figure 3-9 shows the diagram for this pin. The

RB0/INT/SEG0 pin is configurable to function as one of

the following:

• a general purpose I/O

• an external edge triggered interrupt

• an analog output for the LCD

3.3.3.2

RB1/SEG1

Figure 3-9 shows the diagram for this pin. The

RB1/SEG1 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

3.3.3.3

RB2/SEG2

Figure 3-9 shows the diagram for this pin. The

RB2/SEG2 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

3.3.3.4

RB3/SEG3

Figure 3-9 shows the diagram for this pin. The

RB3/SEG3 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

DS41250E-page 44

Preliminary

PIC16F917/916/914/913

FIGURE 3-9:

BLOCK DIAGRAM OF RB<3:0>

SE<3:0>

VDD

RBPU⁽¹⁾

VDD

Weak

Pull-up

P

Data Bus

D

Q

I/O Pin

WR PORTB

CK

Data Latch

D

Q

WR TRISB

CK

TRIS Latch

SE<3:0> and LCDEN

TTL

Input Buffer

RD TRISB

RD PORTB

SEG<3:0>

SE<3:0> and LCDEN

SE0 and LCDEN

INT⁽²⁾

Schmitt

Trigger

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.

2: RB0 only.

Preliminary

DS41250E-page 45

PIC16F917/916/914/913

3.3.3.5

RB4/COM0

Figure 3-10 shows the diagram for this pin. The

RB4/COM0 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

FIGURE 3-10:

BLOCK DIAGRAM OF RB4/COM0

LCDEN

VDD

RBPU⁽¹⁾

VDD

Weak

Pull-up

P

Data Bus

D

Q

I/O Pin

WR PORTB

CK

Data Latch

D

Q

WR TRISB

CK

TRIS Latch

RD TRISB

LCDEN

TTL

Input Buffer

Q

D

RD PORTB

FOSC/4

EN

Set RBIF

LCDEN

D

Q

From other

RB<7:4> pins

EN

LCDEN

COM0

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.

DS41250E-page 46

Preliminary

PIC16F917/916/914/913

3.3.3.6

RB5/COM1

Figure 3-11 shows the diagram for this pin. The

RB5/COM1 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

FIGURE 3-11:

BLOCK DIAGRAM OF RB5/COM1

LCDEN and LMUX<1:0> ≠ 00

VDD

RBPU⁽¹⁾

VDD

Weak

P

Pull-up

Data Bus

D

Q

I/O Pin

WR PORTB

CK

Data Latch

D

Q

WR TRISB

CK

TRIS Latch

RD TRISB

LCDEN and LMUX<1:0> ≠ 00

TTL

Input Buffer

D

Q

FOSC/4

EN

RD PORTB

Set RBIF

LCDEN and

LMUX<1:0> ≠ 00

D

Q

From other

RD PORTB

RB<7:4> pins

EN

LCDEN and LMUX<1:0> ≠ 00

COM1

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.

Preliminary

DS41250E-page 47

PIC16F917/916/914/913

3.3.3.7

RB6/ICSPCLK/ICDCK/SEG14

Figure 3-12 shows the diagram for this pin. The

RB6/ICSPCLK/ICDCK/SEG14 pin is configurable to

function as one of the following:

• a general purpose I/O

• an In-Circuit Serial Programming™ clock

• an ICD clock I/O

• an analog output for the LCD

FIGURE 3-12:

BLOCK DIAGRAM OF RB6/ICSPCLK/ICDCK/SEG14

Program Mode/ICD

RBPU⁽¹⁾

VDD

Weak

P

SE14 and LCDEN

Pull-up

VDD

Data Bus

D

Q

I/O Pin

WR PORTB

WR TRISB

CK

Data Latch

D

Q

CK

TRIS Latch

RD TRISB

TTL

Input Buffer

SE14 and LCDEN

D

Q

RD PORTB

EN

RD PORTB

Set RBIF

Program Mode/ICD

D

Q

From other

RB<7:4> pins

EN

FOSC/4

SE14 and LCDEN

PGC

Schmitt

Trigger Buffer

SE14 and LCDEN

SEG14

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.

DS41250E-page 48

Preliminary

PIC16F917/916/914/913

3.3.3.8

RB7/ICSPDAT/ICDDAT/SEG13

Figure 3-13 shows the diagram for this pin. The

RB7/ICSPDAT/ICDDAT/SEG13 pin is configurable to

function as one of the following:

• a general purpose I/O

• an In-Circuit Serial Programming™ I/O

• an ICD data I/O

• an analog output for the LCD

FIGURE 3-13:

BLOCK DIAGRAM OF RB7/ICSPDAT/ICDDAT/SEG13

PORT/Program Mode/ICD

PGD

VDD

RBPU⁽¹⁾

SE13 and LCDEN

Weak

P

Pull-up

VDD

1

Data Bus

D

Q

0

I/O Pin

WR PORTB

CK

Data Latch

D

Q

WR TRISB

CK

TRIS Latch

0

1

PGD DRVEN

TTL

Input Buffer

SE13 and LCDEN

RD TRISB

D

Q

RD PORTB

EN

RD PORTB

Program

Mode/ICD

Set RBIF

D

Q

From other

RB<7:4> pins

EN

FOSC/4

SE13 and LCDEN

PGD

Schmitt

Trigger Buffer

SE13 and LCDEN

SEG13

Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.

Preliminary

DS41250E-page 49

PIC16F917/916/914/913

TABLE 3-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Value on all

other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h/106h

86h/186h

PORTB

TRISB

RB7

RB6

RB5

TRISB5

T0IE

RB4

TRISB4

INTE

RB3

TRISB3

RBIE

RB2

TRISB2

T0IF

RB1

TRISB1

INTF

RB0

xxxx xxxx uuuu uuuu

TRISB7 TRISB6

GIE PEIE

TRISB0 1111 1111 1111 1111

RBIF 0000 000x 0000 000x

0Bh/8Bh/

INTCON

10Bh/18Bh

95h

WPUB

WPUB7 WPUB6

WPUB5

IOCB5

WERR

SE5

WPUB4

IOCB4

VLCDEN

SE4

WPUB3

—

WPUB2

—

WPUB1

—

WPUB0 1111 1111 1111 1111

0000 ---- 0000 ----

LMUX0 0001 0011 0001 0011

96h

IOCB

IOCB7

LCDEN

SE7

IOCB6

SLPEN

SE6

—

107h

11Ch

11Dh

LCDCON

LCDSE0⁽¹⁾

LCDSE1⁽¹⁾

CS1

CS0

LMUX1

SE1

SE3

SE2

SE0

SE8

0000 0000 uuuu uuuu

SE15

SE14

SE13

SE12

SE11

SE10

SE9

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.

Note 1:

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

DS41250E-page 50

Preliminary

PIC16F917/916/914/913

EXAMPLE 3-3:

INITIALIZING PORTC

3.4

PORTC and TRISC Registers

BCF

CLRF

BSF

STATUS,RP0 ;Bank 0

PORTC is an 8-bit bidirectional port. PORTC is

multiplexed with several peripheral functions. PORTC

pins have Schmitt Trigger input buffers.

STATUS,RP1

PORTC

;

;Init PORTC

STATUS,RP0 ;Bank 1

BCF

STATUS,RP1

FFh

TRISC

STATUS,RP0 ;Bank 2

STATUS,RP1

LCDCON

;

All PORTC pins have latch bits (PORTC register).

They, when written, will modify the contents of the

PORTC latch; thus, modifying the value driven out on

a pin if the corresponding TRISC bit is configured for

output.

MOVLW

MOVWF

BCF

BSF

CLRF

;Set RC<7:0> as inputs

;

;Disable VLCD<3:1>

;inputs on RC<2:0>

Note:

Analog lines that carry LCD signals

(i.e., SEGx, VLCDy, where x and y are

segment and LCD bias voltage identifiers)

are shown as direct connections to the

device pins. The signals are outputs from

the LCD module and may be tri-stated,

depending on the configuration of the LCD

module.

BCF

STATUS,RP0 ;Bank 0

STATUS,RP1

;

REGISTER 3-7:

PORTC – PORTC REGISTER (ADDRESS: 07h)

R/W-x

RC7

R/W-x

RC6

R/W-x

RC5

R/W-x

RC4

R/W-x

RC3

R/W-x

RC2

R/W-x

RC1

R/W-x

RC0

bit 7

bit 0

bit 7-0

RC<7:0>: PORTC I/O Pin bits

1= Port pin is >VIH

0= Port pin is <VIL

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 3-8:

TRISC – PORTC TRI-STATE REGISTER (ADDRESS: 87h)

R/W-1

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3

TRISC2

TRISC1

TRISC0

bit 7

bit 0

bit 7-0

TRISC<7:0>: PORTC Tri-State Control bits

1= PORTC pin configured as an input (tri-stated)

0= PORTC pin configured as an output

Note:

TRISC<7:6> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS41250E-page 51

PIC16F917/916/914/913

3.4.1

PIN DESCRIPTIONS AND

DIAGRAMS

3.4.1.3

RC2/VLCD3

Figure 3-16 shows the diagram for this pin. The

RC2/VLCD3 pin is configurable to function as one of

the following:

Each PORTC pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the LCD or SSP, refer to the appropriate section

in this data sheet.

• a general purpose I/O

• an analog input for the LCD bias voltage

3.4.1.1

RC0/VLCD1

Figure 3-14 shows the diagram for this pin. The

RC0/VLCD1 pin is configurable to function as one of

the following:

• a general purpose I/O

• an analog input for the LCD bias voltage

3.4.1.2

RC1/VLCD2

Figure 3-15 shows the diagram for this pin. The

RC1/VLCD2 pin is configurable to function as one of

the following:

• a general purpose I/O

• an analog input for the LCD bias voltage

FIGURE 3-14:

BLOCK DIAGRAM OF RC0/VLCD1

VDD

Data Bus

D

Q

WR PORTC

WR TRISC

CK

RC0/VLCD1

Data Latch

D

Q

CK

TRIS Latch

(VLCDEN and LMUX<1:0> ≠ 00)

RD TRISC

Schmitt

Trigger

RD PORTC

VLCD1

(VLCDEN and LMUX<1:0> ≠ 00)

DS41250E-page 52

Preliminary

PIC16F917/916/914/913

FIGURE 3-15:

BLOCK DIAGRAM OF RC1/VLCD2

VDD

Data Bus

D

Q

WR PORTC

CK

RC1/VLCD2

Data Latch

D

Q

WR TRISC

Q

CK

TRIS Latch

(VLCDEN and LMUX<1:0> ≠ 00)

RD TRISC

Schmitt

Trigger

RD PORTC

VLCD2

(VLCDEN and LMUX<1:0> ≠ 00)

FIGURE 3-16:

BLOCK DIAGRAM OF RC2/VLCD3

VDD

Data Bus

D

Q

WR PORTC

CK

RC2/VLCD3

Data Latch

D

Q

WR TRISC

Q

CK

TRIS Latch

VLCDEN

RD TRISC

Schmitt

Trigger

RD PORTC

VLCD3

VLCDEN

Preliminary

DS41250E-page 53

PIC16F917/916/914/913

3.4.1.4

RC3/SEG6

Figure 3-17 shows the diagram for this pin. The

RC3/SEG6 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

FIGURE 3-17:

BLOCK DIAGRAM OF RC3/SEG6

VDD

Data Bus

D

Q

WR PORTC

CK

RC3/SEG6

Data Latch

D

Q

WR TRISC

Q

CK

TRIS Latch

SE6 and LCDEN

RD TRISC

Schmitt

Trigger

RD PORTC

SE6 and LCDEN

SEG6 and LCDEN

DS41250E-page 54

Preliminary

PIC16F917/916/914/913

3.4.1.5

RC4/T1G/SDO/SEG11

Figure 3-18 shows the diagram for this pin. The

RC4//T1G/SDO/SEG11pin is configurable to function

as one of the following:

• a general purpose I/O

• a TMR1 gate input

• a serial data output

• an analog output for the LCD

FIGURE 3-18:

BLOCK DIAGRAM OF RC4/T1G/SDO/SEG11

PORT/SDO Select

SDO

0

1

Data Bus

D

Q

VDD

WR PORTC

CK

Q

Data Latch

RC4/T1G/

SDO/SEG11

D

Q

WR TRISC

VSS

CK

Q

TRIS Latch

RD TRISC

SE11 and LCDEN

Schmitt

Trigger

RD PORTC

Timer1 Gate

SE11 and LCDEN

SEG11

Preliminary

DS41250E-page 55

PIC16F917/916/914/913

3.4.1.6

RC5/T1CKI/CCP1/SEG10

Figure 3-19 shows the diagram for this pin. The

RC5/T1CKI/CCP1/SEG10 pin is configurable to

function as one of the following:

• a general purpose I/O

• a TMR1 clock input

• a Capture input, Compare output or PWM output

• an analog output for the LCD

FIGURE 3-19:

BLOCK DIAGRAM OF RC5/T1CKI/CCP1/SEG10

(PORT/CCP1 Select) and CCPMX

CCP1 Data Out

Q

0

1

Data Bus

D

VDD

WR PORTC

CK

Data Latch

Q

RC5/T1CKI/

CCP1/SEG10

D

Q

WR TRISC

VSS

CK

Q

TRIS Latch

RD TRISC

SE10 and LCDEN

Schmitt

Trigger

RD PORTC

Timer1 Gate

SE10 and LCDEN

SEG10

DS41250E-page 56

Preliminary

PIC16F917/916/914/913

3.4.1.7

RC6/TX/CK/SCK/SCL/SEG9

Figure 3-20 shows the diagram for this pin. The

RC6/TX/CK/SCK/SCL/SEG9 pin is configurable to

function as one of the following:

• a general purpose I/O

• an asynchronous serial output

• a synchronous clock I/O

• a SPI clock I/O

• an I²C data I/O

• an analog output for the LCD

FIGURE 3-20:

BLOCK DIAGRAM OF RC6/TX/CK/SCK/SCL/SEG9

PORT/SCEN/SSP Mode Select⁽¹⁾

I²C^™Data Out

TX/CK Data Out

SCK Data Out

0

1

2

3

Data Bus

D

Q

VDD

WR PORTC

CK

Data Latch

Q

RC6/TX/

CK/SCK/

D

Q

SCL/SEG9

WR TRISC

VSS

CK

Q

TRIS Latch

RD TRISC

SCEN or I²C^™Drive

SE9 and LCDEN

Schmitt

Trigger

RD PORTC

CK/SCL/SCK Input

SE9 and LCDEN

SEG9

Note 1: If all three data output sources are enabled, the following priority order will be used:

•

USART data

SSP data

PORT data

Preliminary

DS41250E-page 57

PIC16F917/916/914/913

3.4.1.8

RC7/RX/DT/SDI/SDA/SEG8

Figure 3-21 shows the diagram for this pin. The

RC7/RX/DT/SDI/SDA/SEG8 pin is configurable to

function as one of the following:

• a general purpose I/O

• an asynchronous serial input

• a synchronous serial data I/O

• a SPI data I/O

• an I²C data I/O

• an analog output for the LCD

FIGURE 3-21:

BLOCK DIAGRAM OF RC7/RX/DT/SDI/SDA/SEG8

SCEN/I²C^™Mode Select⁽¹⁾

DT Data Out

0

1

I²C^™Data Out

PORT/(SCEN or I²C^™) Select

VDD

0

1

RC7/RX/DT/

SDI/SDA/

SEG8

Data Bus

D

Q

WR PORTC

CK

Data Latch

D

Q

WR TRISC

CK

Q

TRIS Latch

SE8 and LCDEN

Schmitt

Trigger

RD TRISC

I²C^™Drive

or SCEN Drive

RD PORTC

RX/SDI Input

SE8 and LCDEN

SEG8

Note 1: If SSP and USART outputs are both enabled, the USART data output will have priority over the

SSP data output. Both SSP and USART data outputs will have priority over the PORT data

output.

DS41250E-page 58

Preliminary

PIC16F917/916/914/913

TABLE 3-3:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

07h

PORTC

RC7

RC6

RC5

RC4

RC3

RC2

RC1

RC0

xxxx xxxx uuuu uuuu

10h

T1CON

T1GINV

WCOL

—

T1GE

SSPOV

—

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

14h

SSPCON

CCP1CON

RCSTA

SSPEN

CCP1X

SREN

TRISC5

WERR

SE5

CKP

CCP1Y

CREN

TRISC4

VLCDEN

SE4

SSPM3

SSPM2

SSPM1

SSPM0 0000 0000 0000 0000

17h

CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h

SPEN

RX9

ADDEN

TRISC3

CS1

FERR

TRISC2

CS0

OERR

TRISC1

LMUX1

SE1

RX9D

0000 000x 0000 000x

87h

TRISC

TRISC7 TRISC6

TRISC0 1111 1111 1111 1111

LMUX0 0001 0011 0001 0011

107h

11Ch

11Dh

LCDCON

LCDSE0⁽¹⁾

LCDSE1⁽¹⁾

LCDEN

SE7

SLPEN

SE6

SE3

SE2

SE0

SE8

0000 0000 uuuu uuuu

SE15

SE14

SE13

SE12

SE11

SE10

SE9

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

Note 1:

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

Preliminary

DS41250E-page 59

PIC16F917/916/914/913

EXAMPLE 3-4:

INITIALIZING PORTD

3.5

PORTD and TRISD Registers

BCF

CLRF

BSF

BCF

MOVLW

MOVWF

BCF

STATUS,RP0 ;Bank 0

PORTD is an 8-bit port with Schmitt Trigger input buffers.

Each pin is individually configured as an input or output.

STATUS,RP1

PORTD

;

;Init PORTD

PORTD is only available on the PIC16F914 and

PIC16F917.

STATUS,RP0 ;Bank 1

STATUS,RP1

FFh

TRISD

;

;Set RD<7:0> as inputs

;

Note:

Analog lines that carry LCD signals

(i.e., SEGx, COMy, where x and y are seg-

ment and common identifiers) are shown

as direct connections to the device pins.

The signals are outputs from the LCD

module and may be tri-stated, depending

on the configuration of the LCD module.

STATUS,RP0 ;Bank 0

BCF

STATUS,RP1

;

REGISTER 3-9:

PORTD – PORTD REGISTER (ADDRESS: 08h)

R/W-x

RD7

R/W-x

RD6

R/W-x

RD5

R/W-x

RD4

R/W-x

RD3

R/W-x

RD2

R/W-x

RD1

R/W-x

RD0

bit 7

bit 0

bit 7-0

RD<7:0>: PORTD I/O Pin bits

1= Port pin is >VIH

0= Port pin is <VIL

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 3-10: TRISD – PORTD TRI-STATE REGISTER (ADDRESS: 88h)

R/W-1

TRISD7

TRISD6

TRISD5

TRISD4

TRISD3

TRISD2

TRISD1

TRISD0

bit 7

bit 0

bit 7-0

TRISD<7:0>: PORTD Tri-State Control bits

1= PORTD pin configured as an input (tri-stated)

0= PORTD pin configured as an output

Note:

TRISD<7:6> always reads ‘1’ in XT, HS and LP OSC modes.

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

DS41250E-page 60

Preliminary

PIC16F917/916/914/913

3.5.1

PIN DESCRIPTIONS AND

DIAGRAMS

3.5.1.7

RD6/SEG19

Figure 3-25 shows the diagram for this pin. The

RD6/SEG19 pin is configurable to function as one of

the following:

Each PORTD pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the comparator or the A/D, refer to the

appropriate section in this data sheet.

• a general purpose I/O

• an analog output for the LCD

3.5.1.8

RD7/SEG20

3.5.1.1

RD0/COM3

Figure 3-25 shows the diagram for this pin. The

RD7/SEG20 pin is configurable to function as one of

the following:

Figure 3-22 shows the diagram for this pin. The

RD0/COM3 pin is configurable to function as one of the

following:

• a general purpose I/O

• an analog output for the LCD

• an analog input for the A/D

3.5.1.2

RD1

Figure 3-23 shows the diagram for this pin. The RD1

pin is configurable to function as one of the following:

• a general purpose I/O

3.5.1.3

RD2/CCP2

Figure 3-24 shows the diagram for this pin. The

RD2/CCP2 pin is configurable to function as one of the

following:

• a general purpose I/O

• a Capture input, Compare output or PWM output

3.5.1.4

RD3/SEG16

Figure 3-25 shows the diagram for this pin. The

RD3/SEG16 pin is configurable to function as one of

the following:

• a general purpose I/O

• an analog output for the LCD

3.5.1.5

RD4/SEG17

Figure 3-25 shows the diagram for this pin. The

RD4/SEG17 pin is configurable to function as one of

the following:

• a general purpose I/O

• an analog output for the LCD

3.5.1.6

RD5/SEG18

Figure 3-25 shows the diagram for this pin. The

RD5/SEG18 pin is configurable to function as one of

the following:

• a general purpose I/O

• an analog output for the LCD

Preliminary

DS41250E-page 61

PIC16F917/916/914/913

FIGURE 3-22:

BLOCK DIAGRAM OF RD0/COM3

VDD

Data Bus

D

Q

WR PORTD

RD0/COM3

CK

Data Latch

D

Q

WR TRISD

CK

TRIS Latch

Schmitt

Trigger

RD TRISD

LCDEN and LMUX<1:0> = 11

RD PORTD

LCDEN and

LMUX<1:0> = 11

COM3

FIGURE 3-23:

BLOCK DIAGRAM OF RD1

VDD

Data Bus

D

Q

WR PORTD

CK

RD1 Pin

Data Latch

D

Q

WR TRISD

CK

TRIS Latch

Schmitt

Trigger

RD TRISD

RD PORTD

DS41250E-page 62

Preliminary

PIC16F917/916/914/913

FIGURE 3-24:

BLOCK DIAGRAM OF RD2/CCP2

(PORT/CCP2 Select) and CCPMX

VDD

CCP2 Data Out

0

1

Data Bus

D

Q

RD2/CCP2

WR PORTD

CK

Data Latch

D

Q

WR TRISD

CK

TRIS Latch

Schmitt

Trigger

RD TRISD

RD PORTD

CCP2 Input

FIGURE 3-25:

BLOCK DIAGRAM OF RD<7:3>

VDD

Data Bus

D

Q

WR PORTD

CK

RD<7:3> Pin

Data Latch

D

Q

WR TRISD

CK

TRIS Latch

SE<20:16> and LCDEN

Schmitt

Trigger

RD TRISD

RD PORTD

SE<20:16> and LCDEN

SEG<20:16>

Preliminary

DS41250E-page 63

PIC16F917/916/914/913

TABLE 3-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

PORTD

RD7

—

RD6

—

RD5

CCP2X

TRISD5

WERR

SE21

RD4

CCP2Y

TRISD4

VLCDEN

SE20

RD3

RD2

RD1

RD0

xxxx xxxx uuuu uuuu

1Dh⁽²⁾

CCP2CON

TRISD⁽²⁾

CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

88h

TRISD7 TRISD6

TRISD3

CS1

TRISD2

CS0

TRISD1

LMUX1

SE17

TRISD0 1111 1111 1111 1111

LMUX0 0001 0011 0001 0011

107h

11Eh

LCDCON

LCDSE2^(1,2)

LCDEN

SE23

SLPEN

SE22

SE19

SE18

SE16

0000 0000 uuuu uuuu

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

Note 1:

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

2:

PIC16F914/917 only.

DS41250E-page 64

Preliminary

PIC16F917/916/914/913

EXAMPLE 3-5:

INITIALIZING PORTE

3.6

PORTE and TRISE Registers

BCF

CLRF

BSF

BCF

MOVLW

MOVWF

CLRF

BCF

STATUS,RP0

STATUS,RP1

PORTE

STATUS,RP0

STATUS,RP1

0Fh

TRISE

ANSEL

STATUS,RP0

STATUS,RP1

;Bank 0

;

;Init PORTE

;Bank 1

PORTE is a 4-bit port with Schmitt Trigger input buffers.

RE<2:0> are individually configured as inputs or out-

puts. RE3 is only available as an input if MCLRE is ‘0’

in Configuration Word (Register 16-1).

;

;Set RE<3:0> as inputs

;

;Make RE<2:0> as I/O’s

;Bank 0

;

RE<2:0> are only available on the PIC16F914 and

PIC16F917.

Note:

Analog lines that carry LCD signals

(i.e., SEGx, where x are segment identifi-

ers) are shown as direct connections to

the device pins. The signals are outputs

from the LCD module and may be

tri-stated, depending on the configuration

of the LCD module.

BCF

REGISTER 3-11: PORTE – PORTE REGISTER (ADDRESS: 09h)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-x

RE3

R/W-x

RE2

R/W-x

RE1

R/W-x

RE0

bit 7

bit 0

bit 7-4

bit 3-0

Unimplemented: Read as ‘0’

RE<3:0>: PORTE I/O Pin bits

1= Port pin is >VIH

0= Port pin is <VIL

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 3-12: TRISE – PORTE TRI-STATE REGISTER (ADDRESS: 89h)

U-0

—

U-0

—

U-0

—

U-0

—

R-1

R/W-1

TRISE3

TRISE2

TRISE1

TRISE0

bit 7

bit 0

bit 7-4

bit 3

Unimplemented: Read as ‘0’

TRISE3: Data Direction bit. RE3 is always an input, so this bit always reads as a ‘1’

TRISE<2:0>: Data Direction bits

bit 2-0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 65

PIC16F917/916/914/913

3.6.1

PIN DESCRIPTIONS AND

DIAGRAMS

3.6.1.3

RE2/AN7/SEG23

Figure 3-26 shows the diagram for this pin. The

RE2/AN7/SEG23 pin is configurable to function as one

of the following:

Each PORTE pin is multiplexed with other functions. The

pins and their combined functions are briefly described

here. For specific information about individual functions

such as the comparator or the A/D, refer to the

appropriate section in this data sheet.

• a general purpose I/O

• an analog input for the A/D

• an analog output for the LCD

3.6.1.1

RE0/AN5/SEG21

3.6.1.4

RE3/MCLR/VPP

Figure 3-26 shows the diagram for this pin. The

RE0/AN5/SEG21pin is configurable to function as one

of the following:

Figure 3-27 shows the diagram for this pin. The

RE3/MCLR/VPP pin is configurable to function as one

of the following:

• a general purpose I/O

• a digital input only

• an analog input for the A/D

• an analog output for the LCD

• as Master Clear Reset with weak pull-up

• a programming voltage reference input

3.6.1.2

RE1/AN6/SEG22

Figure 3-26 shows the diagram for this pin. The

RE1/AN6/SEG22 pin is configurable to function as one

of the following:

• a general purpose I/O

• an analog input for the A/D

• an analog output for the LCD

FIGURE 3-26:

BLOCK DIAGRAM OF RE<2:0>

VDD

Data Bus

D

Q

WR PORTE

CK

RE<2:0> Pin

Data Latch

D

Q

WR TRISE

CK

TRIS Latch

Analog Mode or

SE<23:21> and LCDEN

Schmitt

Trigger

RD TRISE

RD PORTE

SE<23:21> and LCDEN

SEG<23:21>

AN<7:5>

DS41250E-page 66

Preliminary

PIC16F917/916/914/913

FIGURE 3-27:

BLOCK DIAGRAM OF RE3/MCLR/VPP

HV

Schmitt Trigger

Buffer

MCLR circuit

MCLR Filter⁽¹⁾

HV Detect

Programming mode

RE3/MCLR/VPP

MCLRE

Data Bus

HV

Schmitt Trigger

Buffer

RE TRIS

RE Port

Note 1: The MCLR filter is bypassed in Emulation mode.

TABLE 3-5:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Value on all

other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

09h

PORTE

—

ADFM

—

CHS2

—

RE3

RE2

RE1

RE0

---- xxxx ---- uuuu

0000 0000 0000 0000

1Fh

89h

ADCON0

TRISE

VCFG1

—

VCFG0

—

CHS1

CHS0

ADON

GO/DONE

TRISE3⁽³⁾TRISE2⁽²⁾TRISE1⁽²⁾TRISE0⁽²⁾---- 1111 ---- 1111

91h

ANSEL

ANS7

LCDEN

SE23

ANS6

SLPEN

SE22

ANS5

WERR

SE21

ANS4

VLCDEN

SE20

ANS3

CS1

ANS2

CS0

ANS1

LMUX1

SE17

ANS0

LMUX0

SE16

1111 1111 1111 1111

0001 0011 0001 0011

0000 0000 uuuu uuuu

107h

11Eh

LCDCON

LCDSE2^(1,2)

SE19

SE18

Legend:

Note 1:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

PIC16F914/917 only.

2:

3:

Bit is read-only; TRISE = 1always.

Preliminary

DS41250E-page 67

PIC16F917/916/914/913

NOTES:

DS41250E-page 68

Preliminary

PIC16F917/916/914/913

The PIC16F917/916/914/913 can be configured in one

of eight clock modes.

4.0

4.1

CLOCK SOURCES

Overview

1. EC – External clock with I/O on RA6.

2. LP – Low-gain Crystal or Ceramic Resonator

Oscillator mode.

The PIC16F917/916/914/913 has a wide variety of

clock sources and selection features to allow it to be

used in a wide range of applications while maximizing

performance and minimizing power consumption.

3. XT – Medium-gain Crystal or Ceramic Resonator

Oscillator mode.

4. HS – High-gain Crystal or Ceramic Resonator

mode.

Figure 4-1 illustrates

PIC16F917/916/914/913 clock sources.

a

block diagram of the

5. RC – External Resistor-Capacitor (RC) with

FOSC/4 output on RA6.

Clock sources can be configured from external oscillators,

quartz crystal resonators, ceramic resonators, and

Resistor-Capacitor (RC) circuits. In addition, the system

clock source can be configured from one of two internal

oscillators, with a choice of speeds selectable via

software. Additional clock features include:

6. RCIO – External Resistor-Capacitor with I/O on

RA6.

7. INTOSC – Internal oscillator with FOSC/4 output

on RA6 and I/O on RA7.

8. INTOSCIO – Internal oscillator with I/O on RA6

and RA7.

• Selectable system clock source between external

or internal via software.

• Two-Speed Clock Start-up mode, which

minimizes latency between external oscillator

start-up and code execution.

Clock source modes are configured by the FOSC<2:0>

bits in the Configuration Word register (see

Section 16.0 “Special Features of the CPU”). The

internal clock can be generated by two oscillators. The

HFINTOSC is a high-frequency calibrated oscillator.

• Fail-Safe Clock Monitor (FSCM) designed to

detect a failure of the external clock source (LP,

XT, HS, EC or RC modes) and switch to the

Internal Oscillator.

The LFINTOSC is

oscillator.

a low-frequency uncalibrated

FIGURE 4-1:

PIC16F917/916/914/913 SYSTEM CLOCK BLOCK DIAGRAM

FOSC<2:0>

(Configuration Word)

External Oscillator

SCS

(OSCCON<0>)

OSC2

OSC1

Sleep

LP, XT, HS, RC, RCIO, EC

IRCF<2:0>

(OSCCON<6:4>)

System Clock

(CPU and Peripherals)

8 MHz

4 MHz

111

110

Internal Oscillator

2 MHz

101

100

011

010

001

000

1 MHz

HFINTOSC

8 MHz

500 kHz

250 kHz

125 kHz

31 kHz

LFINTOSC

31 kHz

LCD Module

Power-up Timer (PWRT)

Watchdog Timer (WDT)

Fail-Safe Clock Monitor (FSCM)

Preliminary

DS41250E-page 69

PIC16F917/916/914/913

REGISTER 4-1:

OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)

U-0

—

R/W-1

IRCF2

R/W-1

IRCF1

R/W-0

IRCF0

R-q

OSTS⁽¹⁾

R-0

LTS

R/W-0

SCS

HTS

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

000= 31 kHz

001= 125 kHz

010= 250 kHz

011= 500 kHz

100= 1 MHz

101= 2 MHz

110= 4 MHz

111= 8 MHz

bit 3

bit 2

bit 1

bit 0

OSTS: Oscillator Start-up Time-out Status bit

1= Device is running from the external system clock defined by FOSC<2:0>

0= Device is running from the internal system clock (HFINTOSC or LFINTOSC)

HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit

1= HFINTOSC is stable

0= HFINTOSC is not stable

LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

1= LFINTOSC is stable

0= LFINTOSC is not stable

SCS: System Clock Select bit

1= Internal oscillator is used for system clock

0= Clock source defined by FOSC<2:0>

Note 1: The value of the OSTS bit on device power-up is dependent on the value of the

Configuration Word (CONFIG) of the device. The value of the OSTS bit will be ‘0’

on a device Power-on Reset (POR) or any automatic clock switch, which may occur

from Two-Speed Start-up or Fail-Safe Clock Monitor, if the following conditions are

true:

OSTS = 0if:

FOSC<2:0> = 000 (LP) or 001 (XT) or 010 (HS)

and

IESO = 1or FSCM = 1

(IESO will be enabled automatically if FSCM is enabled)

If any of the above conditions are not met, the value of the OSTS bit will be ‘1’ on

a device POR. See Section 4.6 “Two-Speed Clock Start-up Mode” and

Section 4.7 “Fail-Safe Clock Monitor” for more details.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

q = value depends on condition

DS41250E-page 70

Preliminary

PIC16F917/916/914/913

4.3.1.1

Special Case

4.2

Clock Source Modes

An exception to this is when the device is put to Sleep

while the following conditions are true:

Clock source modes can be classified as external or

internal.

• LP is the selected primary oscillator mode.

• External clock modes rely on external circuitry for

the clock source. Examples are oscillator modules

(EC mode), quartz crystal resonators or ceramic

resonators (LP, XT and HS modes), and

• T1OSCEN = 1(Timer1 oscillator is enabled).

• SCS = 0(oscillator mode is defined by

FOSC<2:0>).

Resistor-Capacitor (RC mode) circuits.

• OSTS = 1(device is running from primary system

• Internal clock sources are contained internally

within the PIC16F917/916/914/913. The

PIC16F917/916/914/913 has two internal oscilla-

tors: the 8 MHz High-Frequency Internal Oscilla-

tor (HFINTOSC) and 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

clock).

For this case, the OST is not necessary after a wake-up

from Sleep, since Timer1 continues to run during Sleep

and uses the same LP oscillator circuit as its clock

source. For these devices, this case is typically seen

when the LCD module is running during Sleep.

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 4.5 “Clock Switching”).

In applications where the OSCTUNE register is used to

shift the FINTOSC frequency, the application should not

expect the FINTOSC frequency to stabilize immediately.

In this case, the frequency may shift gradually toward

the new value. The time for this frequency shift is less

than eight cycles of the base frequency.

4.3

External Clock Modes

4.3.1

OSCILLATOR START-UP TIMER

(OST)

Note:

When the OST is invoked, the WDOG is

held in Reset, because the WDOG ripple

counter is used by the OST to perform the

oscillator delay count. When the OST

count has expired, the WDOG will begin

counting (if enabled).

If the PIC16F917/916/914/913 is configured for LP, XT

or HS modes, the Oscillator Start-up Timer (OST)

counts 1024 oscillations from the OSC1 pin, following a

Power-on Reset (POR), and the Power-up Timer

(PWRT) has expired (if configured), or a wake-up from

Sleep. During this time, the program counter does not

increment and program execution is suspended. The

OST ensures that the oscillator circuit, using a quartz

crystal resonator or ceramic resonator, has started and

Table 4-1 shows examples where the oscillator delay is

invoked.

In order to minimize latency between external oscillator

start-up and code execution, the Two-Speed Clock

Start-up mode can be selected (see Section 4.6

“Two-Speed Clock Start-up Mode”).

is providing

a

stable system clock to the

PIC16F917/916/914/913. When switching between

clock sources a delay is required to allow the new clock

to stabilize. These oscillator delays are shown in

Table 4-1.

Preliminary

DS41250E-page 71

PIC16F917/916/914/913

TABLE 4-1:

OSCILLATOR DELAY EXAMPLES

System Clock

Source

Oscillator Delay

(TOST)

Frequency

Switching From

Comments

LFIOSC

HFIOSC

31 kHz

Sleep

10 μs internal delay Following a wake-up from Sleep mode

or POR, an internal delay is invoked to

allow the memory bias to stabilize

before program execution can begin.

125 kHz-8 MHz

Sleep

10 μs internal delay Following a wake-up from Sleep mode

or POR, an internal delay is invoked to

allow the memory bias to stabilize

before program execution can begin.

XT or HS

LP

4-20 MHz

32 kHz

INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an

OST of 1024 cycles must occur.

INTOSC or Sleep 1024 clock cycles Following a change from INTOSC, an

OST of 1024 cycles must occur. See

Section 4.3.1.1 “Special Case” for

special case conditions.

LP with T1OSC

enabled

32 kHz

Sleep

10 μs internal delay Following a wake-up from Sleep mode,

an internal delay is invoked to allow the

memory bias to stabilize before

program execution can begin. See

Section 4.3.1.1 “Special Case” for

details about this special case.

EC, RC

0-20 MHz

Sleep

10 μs internal delay Following a wake-up from Sleep mode

or POR, an internal delay is invoked to

allow the memory bias to stabilize

before program execution can begin.

LFIOSC

10 μs internal delay Following a switch from a LFIOSC or

POR, an internal delay is invoked to

allow the memory bias to stabilize

before program execution can begin.

DS41250E-page 72

Preliminary

PIC16F917/916/914/913

4.3.2

EC MODE

4.3.3

LP, XT, HS MODES

The External Clock (EC) mode allows an externally

generated logic level as the system clock source.

When operating in this mode, an external clock source

is connected to the OSC1 pin and the RA6 pin is

available for general purpose I/O. Figure 4-2 shows the

pin connections for EC mode.

The LP, XT and HS modes support the use of quartz

crystal resonators or ceramic resonators connected to

the OSC1 and OSC2 pins (Figures 4-3 and 4-4). The

mode selects a low, medium or high gain setting of the

internal inverter-amplifier to support various resonator

types and speed.

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in

operation after a Power-on Reset (POR) or wake-up

from Sleep. Because the PIC16F917/916/914/913

design is fully static, stopping the external clock input

will have the effect of halting the device while leaving all

data intact. Upon restarting the external clock, the

device will resume operation as if no time had elapsed.

LP Oscillator mode selects the lowest gain setting of the

internal inverter-amplifier. LP mode current consumption

is the least of the three modes. This mode is best suited

to drive resonators with a low drive level specification, for

example, tuning fork type crystals.

Note:

In the past, the sources for the LP oscilla-

tor and Timer1 oscillator have been sepa-

rate circuits. In this family of devices, the

LP oscillator and Timer1 oscillator use the

same oscillator circuitry. When using a

device configured for the LP oscillator and

with T1OSCEN = 1, the source of the

clock for each function comes from the

same oscillator block.

FIGURE 4-2:

EXTERNAL CLOCK (EC)

MODE OPERATION

PIC16F917/916/914/913

Clock

XT Oscillator mode selects the intermediate gain

setting of the internal inverter-amplifier. XT mode

current consumption is the medium of the three modes.

This mode is best suited to drive resonators with a

medium drive level specification, for example,

low-frequency/AT-cut quartz crystal resonators.

OSC1/

CLKIN

FOSC

Internal

Clock

(External

System)

FOSC<2:0> = 011

RA6/OSC2/CLKO/T1OSO

RA6

HS Oscillator mode selects the highest gain setting of

the internal inverter-amplifier. HS mode current

consumption is the highest of the three modes. This

mode is best suited for resonators that require a high

drive setting, for example, high-frequency/AT-cut

quartz crystal resonators or ceramic resonators.

Figures 4-3 and 4-4 show typical circuits for quartz

crystal and ceramic resonators, respectively.

Preliminary

DS41250E-page 73

PIC16F917/916/914/913

FIGURE 4-3:

QUARTZ CRYSTAL

OPERATION (LP, XT OR

HS MODE)

FIGURE 4-4:

CERAMIC RESONATOR

OPERATION

(XT OR HS MODE)

PIC16F917/916/914/913

OSC1

To Int.

Logic

To Int.

C1

Logic

(2)

(3)

RF

Quartz

Crystal

Sleep⁽³⁾

Sleep

OSC2

(1)

RS

Ceramic

C2

Resonator

Note 1: A series resistor (RS) may be required for

quartz crystals with low drive level.

ceramic resonators with low drive level.

2: The value of RF varies with the oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

2: The value of RF varies with the oscillator

mode selected (typically between 2 MΩ to

10 MΩ).

3: If using LP mode and T1OSC in enable,

the LP oscillator will continue to run during

Sleep.

3: An additional parallel feedback resistor

(RP) may be required for proper ceramic

resonator operation (typical value 1 MΩ).

Note 1: Quartz crystal characteristics vary

according to type, package and manufac-

turer. The user should consult the

manufacturer data sheets for specifica-

tions and recommended application.

2: Always verify oscillator performance over

the VDD and temperature range that is

expected for the application.

DS41250E-page 74

Preliminary

PIC16F917/916/914/913

4.3.4

EXTERNAL RC MODES

4.4

Internal Clock Modes

The External Resistor-Capacitor (RC) modes support

the use of an external RC circuit. This allows the

designer maximum flexibility in frequency choice while

keeping costs to a minimum when clock accuracy is not

required. There are two modes, RC and RCIO.

The PIC16F917/916/914/913 has two independent,

internal oscillators that can be configured or selected

as the system clock source.

1. The HFINTOSC (High-Frequency Internal

Oscillator) is factory calibrated and operates at

8 MHz. The frequency of the HFINTOSC can be

user adjusted ±12% via software using the

OSCTUNE register (Register 4-2).

In RC mode, the RC circuit connects to the OSC1 pin.

The OSC2/CLKO pin outputs the RC oscillator

frequency divided by 4. This signal may be used to

provide a clock for external circuitry, synchronization,

calibration, test or other application requirements.

Figure 4-5 shows the RC mode connections.

2. The LFINTOSC (Low-Frequency Internal

Oscillator) is uncalibrated and operates at

approximately 31 kHz.

The system clock speed can be selected via software

using the Internal Oscillator Frequency Select (IRCF)

bits.

FIGURE 4-5:

RC MODE

VDD

PIC16F917/916/914/913

The system clock can be selected between external or

internal clock sources via the System Clock Selection

(SCS) bit (see Section 4.5 “Clock Switching”).

REXT

OSC1

Internal

Clock

4.4.1

INTOSC AND INTOSCIO MODES

CEXT

VSS

The INTOSC and INTOSCIO modes configure the

internal oscillators as the system clock source when the

device is programmed using the Oscillator Selection

(FOSC) bits in the Configuration Word register

(Register 16-1).

OSC2/CLKO

FOSC/4

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

In INTOSC mode, the OSC1 pin is available for general

purpose I/O. The OSC2/CLKO pin outputs the selected

internal oscillator frequency divided by 4. The CLKO

signal may be used to provide a clock for external

circuitry, synchronization, calibration, test or other

application requirements.

In RCIO mode, the RC circuit is connected to the OSC1

pin. The OSC2 pin becomes an additional general

purpose I/O pin. The I/O pin becomes bit 4 of PORTA

(RA4). Figure 4-6 shows the RCIO mode connections.

In INTOSCIO mode, the OSC1 and OSC2 pins are

available for general purpose I/O.

FIGURE 4-6:

RCIO MODE

VDD

4.4.2

HFINTOSC

PIC16F917/916/914/913

REXT

The High-Frequency Internal Oscillator (HFINTOSC) is

a factory calibrated 8 MHz internal clock source. The

frequency of the HFINTOSC can be altered

approximately ±12% via software using the OSCTUNE

register (Register 4-2).

OSC1

Internal

Clock

CEXT

VSS

I/O (OSC2)

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 4-1). One of seven

frequencies can be selected via software using the

IRCF bits (see Section 4.4.4 “Frequency Select Bits

(IRCF)”).

RA6

Recommended values:3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20 pF

The HFINTOSC is enabled by selecting any frequency

between 8 MHz and 125 kHz (IRCF ≠ 000) as the

System Clock Source (SCS = 1), or when Two-Speed

Start-up is enabled (IESO = 1and IRCF ≠ 000).

The RC oscillator frequency is a function of the supply

voltage, the resistor (REXT) and capacitor (CEXT)

values and the operating temperature. In addition to

this, the oscillator frequency will vary from unit to unit

due to normal threshold voltage. Furthermore, the

difference in lead frame capacitance between package

types will also affect the oscillation frequency or for low

CEXT values. The user also needs to take into account

variation due to tolerance of external RC components

used.

The HF Internal Oscillator (HTS) bit (OSCCON<2>)

indicates whether the HFINTOSC is stable or not.

Preliminary

DS41250E-page 75

PIC16F917/916/914/913

When the OSCTUNE register is modified, the HFINTOSC

frequency will begin shifting to the new frequency. The

HFINTOSC clock will stabilize within 1 ms. Code

execution continues during this shift. There is no

indication that the shift has occurred.

4.4.2.1

OSCTUNE Register

The HFINTOSC is factory calibrated but can be

adjusted in software by writing to the OSCTUNE

register (Register 4-2).

The OSCTUNE register has a tuning range of ±12%.

The default value of the OSCTUNE register is ‘0’. The

value is a 5-bit two’s complement number. Due to

process variation, the monotonicity and frequency step

cannot be specified.

OSCTUNE does not affect the LFINTOSC frequency.

Operation of features that depend on the LFINTOSC

clock source frequency, such as the Power-up Timer

(PWRT), Watchdog Timer (WDT), Fail-Safe Clock

Monitor (FSCM) and peripherals, are not affected by the

change in frequency.

REGISTER 4-2:

OSCTUNE – OSCILLATOR TUNING RESISTOR (ADDRESS: 90h)

U-0

—

U-0

—

U-0

—

R/W-0

TUN4

R/W-0

TUN3

R/W-0

TUN2

R/W-0

TUN1

R/W-0

TUN0

bit 7

bit 0

bit 7-5

bit 4-0

Unimplemented: Read as ‘0’

TUN<4:0>: Frequency Tuning bits

01111= Maximum frequency

01110=

•

00001=

00000= Center frequency. Oscillator module is running at the calibrated frequency.

11111=

•

10000= Minimum frequency

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 76

Preliminary

PIC16F917/916/914/913

4.4.3

LFINTOSC

4.4.5

HF AND LF INTOSC CLOCK

SWITCH TIMING

The Low-Frequency Internal Oscillator (LFINTOSC) is

an uncalibrated (approximate) 31 kHz internal clock

source.

When switching between the LFINTOSC and the

HFINTOSC, the new oscillator may already be shut

down to save power. If this is the case, there is a 10 μs

delay after the IRCF bits are modified before the

frequency selection takes place. The LTS/HTS bits will

reflect the current active status of the LFINTOSC and

the HFINTOSC oscillators. The timing of a frequency

selection is as follows:

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 4-1). 31 kHz can be

selected via software using the IRCF bits (see

Section 4.4.4 “Frequency Select Bits (IRCF)”). The

LFINTOSC is also the frequency for the Power-up

Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe

Clock Monitor (FSCM).

1. IRCF bits are modified.

2. If the new clock is shut down, a 10 μs clock

The LFINTOSC is enabled by selecting 31 kHz

(IRCF = 000) as the System Clock Source (SCS = 1),

or when any of the following are enabled:

start-up delay is started.

3. Clock switch circuitry waits for a falling edge of

the current clock.

• Two-Speed Start-up (IESO = 1and IRCF = 000)

• Power-up Timer (PWRT)

4. CLKO is held low and the clock switch circuitry

waits for a rising edge in the new clock.

• Watchdog Timer (WDT)

5. CLKO is now connected with the new clock.

HTS/LTS bits are updated as required.

• Fail-Safe Clock Monitor (FSCM)

• Selected as LCD module clock source

6. Clock switch is complete.

The LF Internal Oscillator (LTS) bit (OSCCON<1>)

indicates whether the LFINTOSC is stable or not.

If the internal oscillator speed selected is between

8 MHz and 125 kHz, there is no start-up delay before

the new frequency is selected. This is because the old

and the new frequencies are derived from the

HFINTOSC via the postscaler and multiplexer.

4.4.4

FREQUENCY SELECT BITS (IRCF)

The output of the 8 MHz HFINTOSC and 31 kHz

LFINTOSC connect to a postscaler and multiplexer

(see Figure 4-1). The Internal Oscillator Frequency

select bits, IRCF<2:0> (OSCCON<6:4>), select the

frequency output of the internal oscillators. One of eight

frequencies can be selected via software:

4.5

Clock Switching

The system clock source can be switched between

external and internal clock sources via software using

the System Clock Select (SCS) bit.

• 8 MHz

• 4 MHz (Default after Reset)

• 2 MHz

4.5.1

SYSTEM CLOCK SELECT (SCS) BIT

The System Clock Select (SCS) bit (OSCCON<0>)

selects the system clock source that is used for the

CPU and peripherals.

• 1 MHz

• 500 kHz

• 250 kHz

• When SCS = 0, the system clock source is

determined by configuration of the FOSC<2:0>

bits in the Configuration Word register (CONFIG).

• 125 kHz

• 31 kHz

• When SCS = 1, the system clock source is

chosen by the internal oscillator frequency

selected by the IRCF bits. After a Reset, SCS is

always cleared.

Note:

Following any Reset, the IRCF bits are set

to ‘110’ and the frequency selection is set

to 4 MHz. The user can modify the IRCF

bits to select a different frequency.

Note:

Any automatic clock switch, which may

occur from Two-Speed Start-up or

Fail-Safe Clock Monitor, does not update

the SCS bit. The user can monitor the

OSTS (OSCCON<3>) to determine the

current system clock source.

Preliminary

DS41250E-page 77

PIC16F917/916/914/913

4.5.2

OSCILLATOR START-UP TIME-OUT

STATUS BIT

4.6.2

TWO-SPEED START-UP

SEQUENCE

The Oscillator Start-up Time-out Status (OSTS) bit

(OSCCON<3>) indicates whether the system clock is

running from the external clock source, as defined by

the FOSC bits, or from the internal clock source. In

particular, OSTS indicates that the Oscillator Start-up

Timer (OST) has timed out for LP, XT or HS modes.

1. Wake-up from Power-on Reset or Sleep.

2. Instructions begin execution by the internal

oscillator at the frequency set in the IRCF bits

(OSCCON<6:4>).

3. OST enabled to count 1024 clock cycles.

4. OST timed out, wait for falling edge of the

internal oscillator.

4.6

Two-Speed Clock Start-up Mode

5. OSTS is set.

Two-Speed Start-up mode provides additional power

savings by minimizing the latency between external

oscillator start-up and code execution. In applications

that make heavy use of the Sleep mode, Two-Speed

Start-up will remove the external oscillator start-up

time from the time spent awake and can reduce the

overall power consumption of the device.

6. System clock held low until the next falling edge

of new clock (LP, XT or HS mode).

7. System clock is switched to external clock

source.

4.6.3

CHECKING EXTERNAL/INTERNAL

CLOCK STATUS

This mode allows the application to wake-up from

Sleep, perform a few instructions using the INTOSC

as the clock source and go back to Sleep without

waiting for the primary oscillator to become stable.

Checking the state of the OSTS bit (OSCCON<3>) will

confirm if the PIC16F917/916/914/913 is running from

the external clock source as defined by the FOSC bits

in the Configuration Word (CONFIG) or the internal

oscillator.

Note:

Executing a SLEEP instruction will abort

the oscillator start-up time and will cause

the OSTS bit (OSCCON<3>) to remain

clear.

When the PIC16F917/916/914/913 is configured for

LP, XT or HS modes, the Oscillator Start-up Timer

(OST) is enabled (see Section 4.3.1 “Oscillator

Start-up Timer (OST)”). The OST timer will suspend

program execution until 1024 oscillations are counted.

Two-Speed Start-up mode minimizes the delay in code

execution by operating from the internal oscillator as

the OST is counting. When the OST count reaches

1024 and the OSTS bit (OSCCON<3>) is set, program

execution switches to the external oscillator.

4.6.1

TWO-SPEED START-UP MODE

CONFIGURATION

Two-Speed Start-up mode is configured by the

following settings:

• IESO = 1(CONFIG<10>) Internal/External

Switchover bit.

• SCS = 0.

• FOSC configured for LP, XT or HS mode.

Two-Speed Start-up mode is entered after:

• Power-on Reset (POR) and, if enabled, after

PWRT has expired, or

• Wake-up from Sleep.

If the external clock oscillator is configured to be anything

other than LP, XT or HS mode, then Two-Speed Start-up

is disabled. This is because the external clock oscillator

does not require any stabilization time after POR or an

exit from Sleep.

DS41250E-page 78

Preliminary

PIC16F917/916/914/913

FIGURE 4-7:

TWO-SPEED START-UP

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

Q1

INTOSC

TOST

OSC1

0

1

1022 1023

OSC2

Program Counter

PC

PC + 1

PC + 2

System Clock

The frequency of the internal oscillator will depend upon

the value contained in the IRCF bits (OSCCON<6:4>).

Upon entering the Fail-Safe condition, the OSTS bit

(OSCCON<3>) is automatically cleared to reflect that

the internal oscillator is active and the WDT is cleared.

The SCS bit (OSCCON<0>) is not updated. Enabling

FSCM does not affect the LTS bit.

4.7

Fail-Safe Clock Monitor

The Fail-Safe Clock Monitor (FSCM) is designed to

allow the device to continue to operate in the event of

an oscillator failure. The FSCM can detect oscillator

failure at any point after the device has exited a Reset

or Sleep condition and the Oscillator Start-up Timer

(OST) has expired.

The FSCM sample clock is generated by dividing the

INTOSC clock by 64. This will allow enough time

between FSCM sample clocks for a system clock edge

to occur. Figure 4-8 shows the FSCM block diagram.

FIGURE 4-8:

FSCM BLOCK DIAGRAM

On the rising edge of the sample clock, a monitoring

latch (CM = 0) will be cleared. On a falling edge of the

primary system clock, the monitoring latch will be set

(CM = 1). In the event that a falling edge of the sample

clock occurs, and the monitoring latch is not set, a clock

failure has been detected. The assigned internal

oscillator is enabled when FSCM is enabled as

reflected by the IRCF.

Primary

Clock

Fail

Detector

Clock

Failure

Detected

LFINTOSC

Oscillator

÷ 64

Note 1: Two-Speed Start-up is automatically

enabled when the Fail-Safe Clock Monitor

mode is enabled.

The FSCM function is enabled by setting the FCMEN

bit in the Configuration Word (CONFIG). It is applicable

to all external clock options (LP, XT, HS, EC or RC

modes).

2: Primary clocks with a frequency ≤ ~488Hz

will be considered failed by the FSCM. A

slow starting oscillator can cause an

FSCM interrupt.

In the event of an external clock failure, the FSCM will

set the OSFIF bit (PIR2<7>) and generate an oscillator

fail interrupt if the OSFIE bit (PIE2<7>) is set. The

device will then switch the system clock to the internal

oscillator. The system clock will continue to come from

the internal oscillator unless the external clock recovers

and the Fail-Safe condition is exited.

Preliminary

DS41250E-page 79

PIC16F917/916/914/913

4.7.1

FAIL-SAFE CONDITION CLEARING

The Fail-Safe condition is cleared after a Reset, the

execution of a SLEEP instruction, or a modification of

the SCS bit. While in Fail-Safe condition, the

PIC16F91X uses the internal oscillator as the system

without exiting the Fail-Safe condition.

The Fail-Safe condition must be cleared before the

OSFIF flag can be cleared.

FIGURE 4-9:

FSCM TIMING DIAGRAM

Sample Clock

Oscillator

Failure

System

Clock

Output

CM Output

(Q)

Failure

Detected

OSCFIF

CM Test

Note:

The system clock is normally at a much higher frequency than the sample clock. The relative

frequencies in this example have been chosen for clarity.

4.7.2

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at

any point after the device has exited a Reset or Sleep

condition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit (OSCCON<3>) to verify the

oscillator start-up and system clock

switchover has successfully completed.

For LP, XT or HS mode the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time, a false clock failure may be

detected (see Figure 4-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable

(the OST has timed out). This is identical to

Two-Speed Start-up mode. Once the external

oscillator is stable, the LFINTOSC returns to its role as

the FSCM source.

TABLE 4-2:

SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on

all other

Resets

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(2)

8Fh

OSCCON

OSCTUNE

CONFIG

—

IRCF2 IRCF1

IRCF0 OSTS

TUN4 TUN3

HTS

LTS

SCS

-110 q000 -110 x000

90h

—

TUN2

TUN1

TUN0 ---0 0000 ---u uuuu

(1)

2007h

CPD

CP

MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0

—

Legend:

x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.

Note 1: See Register 16-1 for operation of all Configuration Word bits.

2: See Register 4-1 for details.

DS41250E-page 80

Preliminary

PIC16F917/916/914/913

Counter mode is selected by setting the T0CS bit

(OPTION_REG<5>). In this mode, the Timer0 module

will increment either on every rising or falling edge of pin

RA4/C1OUT/T0CKI/SEG4. The incrementing edge is

determined by the source edge (T0SE) control bit

(OPTION_REG<4>). Clearing the T0SE bit selects the

rising edge.

5.0

TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Note:

Counter mode has specific external clock

requirements. Additional information on

these requirements is available in the

“PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023).

Figure 5-1 is a block diagram of the Timer0 module and

the prescaler shared with the WDT.

5.2

Timer0 Interrupt

Note:

Additional information on the Timer0

module is available in the “PICmicro^®

Mid-Range MCU Family Reference

Manual” (DS33023).

A Timer0 interrupt is generated when the TMR0

register timer/counter overflows from FFh to 00h. This

overflow sets the T0IF bit (INTCON<2>). The interrupt

can be masked by clearing the T0IE bit (INTCON<5>).

The T0IF bit must be cleared in software by the Timer0

module Interrupt Service Routine before re-enabling

this interrupt. The Timer0 interrupt cannot wake the

processor from Sleep, since the timer is shut off during

Sleep.

5.1

Timer0 Operation

Timer mode is selected by clearing the T0CS bit

(OPTION_REG<5>). In Timer mode, the Timer0

module will increment every instruction cycle (without

prescaler). If TMR0 is written, the increment is inhibited

for the following two instruction cycles. The user can

work around this by writing an adjusted value to the

TMR0 register.

FIGURE 5-1:

BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKO

(= FOSC/4)

Data Bus

0

1

8

1

SYNC 2

Cycles

TMR0

T0CKI

0

1

Set Flag bit T0IF

on Overflow

T0CS

T0SE

8-bit

Prescaler

PSA

8

PSA

WDTE

SWDTEN

1

PS<2:0>

WDT

Time-out

16-bit

Prescaler

0

16

Watchdog

Timer

31 kHz

INTOSC

PSA

WDTPS<3:0>

T0SE, T0CS, PSA and PS<2:0> are bits in the Option register; WDTPS<3:0> are bits in the WDTCON register.

Note:

Preliminary

DS41250E-page 81

PIC16F917/916/914/913

5.3

Using Timer0 with an External

Clock

When no prescaler is used, the external clock input is the

same as the prescaler output. The synchronization of

T0CKI, with the internal phase clocks, is accomplished by

sampling the prescaler output on the Q2 and Q4 cycles of

the internal phase clocks. Therefore, it is necessary for

T0CKI to be high for at least 2 TOSC (and a small RC delay

of 20 ns) and low for at least 2 TOSC (and a small RC delay

of 20 ns). Refer to the electrical specification of the

desired device.

REGISTER 5-1:

OPTION_REG – OPTION REGISTER (ADDRESS: 81h OR 181h)

R/W-1

RBPU

R/W-1

T0CS

R/W-1

T0SE

R/W-1

PSA

R/W-1

PS2

R/W-1

PS1

R/W-1

PS0

INTEDG

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

RBPU: PORTB Pull-up Enable bit

1= PORTB pull-ups are disabled

0= PORTB pull-ups are enabled by individual port latch values in WPUA register

INTEDG: Interrupt Edge Select bit

1= Interrupt on rising edge of RB0/INT/SEG0 pin

0= Interrupt on falling edge of RB0/INT/SEG0 pin

T0CS: TMR0 Clock Source Select bit

1= Transition on RA4/C1OUT/T0CKI/SEG4 pin

0= Internal instruction cycle clock (CLKO)

T0SE: TMR0 Source Edge Select bit

1= Increment on high-to-low transition on RA4/C1OUT/T0CKI/SEG4 pin

0= Increment on low-to-high transition on RA4/C1OUT/T0CKI/SEG4 pin

PSA: Prescaler Assignment bit

1= Prescaler is assigned to the WDT

0= Prescaler is assigned to the Timer0 module

PS<2:0>: Prescaler Rate Select bits

Bit Value TMR0 Rate WDT Rate⁽¹⁾

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available for the PIC16F917/916/914/913.

See Section 16.6 “Watchdog Timer (WDT)” for more information.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 82

Preliminary

PIC16F917/916/914/913

EXAMPLE 5-1:

CHANGING PRESCALER

(TIMER0 → WDT)

5.4

Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. For simplicity, this counter will be referred to as

“prescaler” throughout this data sheet. The prescaler

assignment is controlled in software by the control bit

PSA (OPTION_REG<3>). Clearing the PSA bit will

assign the prescaler to Timer0. Prescale values are

selectable via the PS<2:0> bits (OPTION_REG<2:0>).

BCF

STATUS,RP0

;Bank 0

CLRWDT

CLRF

;Clear WDT

;Clear TMR0 and

; prescaler

;Bank 1

TMR0

BSF

STATUS,RP0

MOVLW

MOVWF

CLRWDT

b’00101111’

OPTION_REG

;Required if desired

; PS2:PS0 is

; 000 or 001

;

;Set postscaler to

; desired WDT rate

;Bank 0

The prescaler is not readable or writable. When

assigned to the Timer0 module, all instructions writing

to the TMR0 register (e.g., CLRF 1, MOVWF 1,

BSF 1, x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer.

MOVLW

MOVWF

BCF

b’00101xxx’

OPTION_REG

STATUS,RP0

To change prescaler from the WDT to the TMR0

module, use the sequence shown in Example 5-2. This

precaution must be taken even if the WDT is disabled.

5.4.1

SWITCHING PRESCALER

ASSIGNMENT

EXAMPLE 5-2:

CHANGING PRESCALER

(WDT → TIMER0)

The prescaler assignment is fully under software control

(i.e., it can be changed “on-the-fly” during program

execution). To avoid an unintended device Reset, the

following instruction sequence (Example 5-1 and

Example 5-2) must be executed when changing the

prescaler assignment from Timer0 to WDT.

CLRWDT

;Clear WDT and

; prescaler

;Bank 1

BSF

STATUS,RP0

b’xxxx0xxx’

MOVLW

;Select TMR0,

; prescale, and

; clock source

;

MOVWF

BCF

OPTION_REG

STATUS,RP0

;Bank 0

TABLE 5-1:

REGISTERS ASSOCIATED WITH TIMER0

Value on

all other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

TMR0

Timer0 Module Register

xxxx xxxx uuuu uuuu

0000 000x 0000 000x

1111 1111 1111 1111

0Bh/10Bh INTCON

GIE

OPTION_REG RBPU INTEDG

TRISA

PEIE

T0IE

INTE

T0SE

RBIE

PSA

T0IF

PS2

INTF

PS1

RBIF

PS0

81h

85h

T0CS

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111

Legend: -= Unimplemented locations, read as ‘0’, u= unchanged, x= unknown. Shaded cells are not used by the Timer0 module.

Preliminary

DS41250E-page 83

PIC16F917/916/914/913

NOTES:

DS41250E-page 84

Preliminary

PIC16F917/916/914/913

The Timer1 Control register (T1CON), shown in

Register 6-1, is used to enable/disable Timer1 and

select the various features of the Timer1 module.

6.0

TIMER1 MODULE WITH GATE

CONTROL

The PIC16F917/916/914/913 has a 16-bit timer.

Figure 6-1 shows the basic block diagram of the Timer1

module. Timer1 has the following features:

Note:

Additional information on timer modules is

available in the “PICmicro^®Mid-Range MCU

Family Reference Manual” (DS33023).

• 16-bit timer/counter (TMR1H:TMR1L)

• Readable and writable

• Internal or external clock selection

• Synchronous or asynchronous operation

• Interrupt-on-overflow from FFFFh to 0000h

• Wake-up upon overflow (Asynchronous mode)

• Optional external enable input:

- Selectable gate source: T1G or C2 output

(T1GSS)

- Selectable gate polarity (T1GINV)

• Optional LP oscillator

FIGURE 6-1:

TIMER1 ON THE PIC16F917/916/914/913 BLOCK DIAGRAM

TMR1ON

T1GE

T1GINV

Clear on special

TMR1ON

event trigger

T1GE

Set Flag bit

TMR1IF on

Overflow

To C2 Comparator Module

TMR1 Clock

(1)

TMR1

Synchronized

Clock Input

0

TMR1L

TMR1H

1

LP OSC

(2)

T1SYNC

1

0

OSC1/T1OSI

1

Synchronize

det

Prescaler

1, 2, 4, 8

FOSC/4

Internal

Clock

0

OSC2/T1OSO

2

Sleep Input

T1CKPS<1:0>

FOSC = 000

FOSC = x00

T1OSCEN

RC4/T1G/

SDO/SEG11

1

T1CS

0

C2OUT

RC5/T1CKI/

CCP1/SEG10

T1GSS

Note 1: Timer1 increments on the rising edge.

2: ST Buffer is low-power type when using LP oscillator or high-speed type when using T1CKI.

Preliminary

DS41250E-page 85

PIC16F917/916/914/913

6.1

Timer1 Modes of Operation

6.3

Timer1 Prescaler

Timer1 can operate in one of three modes:

Timer1 has four prescaler options allowing 1, 2, 4 or 8

divisions of the clock input. The T1CKPS bits

(T1CON<5:4>) control the prescale counter. The

prescale counter is not directly readable or writable;

however, the prescaler counter is cleared upon a write

to TMR1H or TMR1L.

• 16-bit timer with prescaler

• 16-bit synchronous counter

• 16-bit asynchronous counter

In Timer mode, Timer1 is incremented on every

instruction cycle. In Counter mode, Timer1 is incremented

on the rising edge of the external clock input T1CKI. In

addition, the Counter mode clock can be synchronized to

the microcontroller system clock or run asynchronously.

6.4

Timer1 Gate

Timer1 gate source is software configurable to be the

T1G pin or the output of Comparator 2. This allows the

device to directly time external events using T1G or

analog events using Comparator 2. See CMCON1

(Register 8-2) for selecting the Timer1 gate source.

This feature can simplify the software for a Delta-Sigma

A/D converter and many other applications. For more

information on Delta-Sigma A/D converters, see the

Microchip web site (www.microchip.com).

In the Timer1 module, the module clock can be gated

by the Timer1 gate, which can be selected as either the

T1G pin or Comparator 2 output.

If an external clock oscillator is needed (and the

microcontroller is using the INTOSC without CLKO),

Timer1 can use the LP oscillator as a clock source.

Note:

In Counter mode, a falling edge must be

registered by the counter prior to the first

incrementing rising edge.

Note:

T1GE bit (T1CON<6>) must be set to use

either T1G or C2OUT as the Timer1 gate

source. See Register 8-2 for more

information on selecting the Timer1 gate

source.

6.2

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments

to FFFFh and rolls over to 0000h. When Timer1 rolls

over, the Timer1 Interrupt Flag bit (PIR1<0>) is set. To

enable the interrupt on rollover, you must set these bits:

Timer1 gate can be inverted using the T1GINV bit

(T1CON<7>), whether it originates from the T1G pin or

Comparator 2 output. This configures Timer1 to

measure either the active-high or active-low time

between events.

• Timer1 Interrupt Enable bit (PIE1<0>)

• PEIE bit (INTCON<6>)

• GIE bit (INTCON<7>)

The interrupt is cleared by clearing the TMR1IF bit in

the Interrupt Service Routine.

Note:

The TMR1H:TTMR1L register pair and the

TMR1IF bit should be cleared before

enabling interrupts.

FIGURE 6-2:

TIMER1 INCREMENTING EDGE

T1CKI = 1

when TMR1

Enabled

T1CKI = 0

when TMR1

Enabled

Note 1: Arrows indicate counter increments.

2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing

rising edge of the clock.

DS41250E-page 86

Preliminary

PIC16F917/916/914/913

REGISTER 6-1:

T1CON – TIMER1 CONTROL REGISTER (ADDRESS: 10h)

R/W-0

T1GE

R/W-0

T1GINV

bit 7

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 0

bit 7

bit 6

T1GINV: Timer1 Gate Invert bit⁽¹⁾

1= Timer1 gate is inverted

0= Timer1 gate is not inverted

T1GE: Timer1 Gate Enable bit⁽²⁾

If TMR1ON = 0:

This bit is ignored.

If TMR1ON = 1:

1= Timer1 gate is enabled

0= Timer1 gate is disabled

bit 5-4

bit 3

T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:8 Prescale Value

10= 1:4 Prescale Value

01= 1:2 Prescale Value

00= 1:1 Prescale Value

T1OSCEN: LP Oscillator Enable Control bit

If INTOSC without CLKO oscillator is active:

1= LP oscillator is enabled for Timer1 clock

0= LP oscillator is off

Else:

This bit is ignored.

bit 2

T1SYNC: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1:

1= Do not synchronize external clock input

0= Synchronize external clock input

TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock.

bit 1

bit 0

TMR1CS: Timer1 Clock Source Select bit

1= External clock from RC5/T1CKI/CCP1/SEG10 pin or T1OSC (on the rising edge)

0= Internal clock (FOSC/4)

TMR1ON: Timer1 On bit

1= Enables Timer1

0= Stops Timer1

Note 1: T1GINV bit inverts the Timer1 gate logic, regardless of source.

2: T1GE bit must be set to use either T1G pin or C2OUT, as selected by the T1GSS

bit (CMCON1<1>), as a Timer1 gate source.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 87

PIC16F917/916/914/913

6.5

Timer1 Operation in

6.6

TIMER1 OSCILLATOR

Asynchronous Counter Mode

To minimize the multiplexing of peripherals on the I/O

ports, the dedicated TMR1 oscillator, which is normally

used for TMR1 real-time clock applications, is eliminated.

Instead, the TMR1 module can enable the LP oscillator.

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during Sleep and can

generate an interrupt-on-overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer (see

Section 6.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”).

If the microcontroller is programmed to run from

INTOSC with no CLKO or LP oscillator:

1. Setting the T1OSCEN and TMR1CS bits to ‘1’

will enable the LP oscillator to clock TMR1 while

the microcontroller is clocked from either the

INTOSC or LP oscillator. Note that the T1OSC

and LP oscillators share the same circuitry.

Therefore, when LP oscillator is selected and

T1OSC is enabled, both the microcontroller and

the Timer1 module share the same clock

source.

Note: The ANSEL (91h) and CMCON0 (9Ch)

registers must be initialized to configure an

analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

6.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

2. Sleep mode does not shut off the LP oscillator

operation (i.e., if the INTOSC oscillator runs the

microcontroller, and T1OSCEN = 1 (TMR1 is

running from the LP oscillator), then the LP

oscillator will continue to run during Sleep mode.

Reading TMR1H or TMR1L, while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user should keep in mind that reading the 16-bit timer

in two 8-bit values itself, poses certain problems, since

the timer may overflow between the reads.

In all oscillator modes except for INTOSC with no

CLKOUT and LP, the T1OSC enable option is unavail-

able and is ignored.

Note:

When INTOSC without CLKO oscillator is

selected and T1OSCEN = 1, the LP

oscillator will run continuously independent

of the TMR1ON bit.

For writes, it is recommended that the user simply stop

the timer and write the desired values. A write

contention may occur by writing to the timer registers,

while the register is incrementing. This may produce an

unpredictable value in the timer register.

6.7

Resetting Timer1 Using a CCP

Trigger Output

Reading the 16-bit value requires some care.

Examples in the “PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023) show how to read and

write Timer1 when it is running in Asynchronous mode.

If the CCP1 or CCP2 module is configured in Compare

mode to generate “special event trigger”

(CCP1M<3:0> = 1011), this signal will reset Timer1.

a

Note:

The special event triggers from the CCP1

and CCP2 modules will not set interrupt

flag bit, TMR1IF (PIR1<0>).

Timer1 must be configured for either Timer or Synchro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this Reset operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1 or CCP2, the write will

take precedence.

In this mode of operation, the CCPRxH:CCPRxL register

pair effectively becomes the period register for Timer1.

DS41250E-page 88

Preliminary

PIC16F917/916/914/913

6.8

Resetting of Timer1 Register Pair

(TMR1H, TMR1L)

TMR1H and TMR1L registers are not reset to 00h on a

POR, or any other Reset, except by the CCP1 and

CCP2 special event triggers.

T1CON register is reset to 00h on a Power-on Reset,

or a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other Resets, the register

is unaffected.

6.9

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external

crystal or clock source can be used to increment the

counter. To set up the timer to wake the device:

• Timer1 must be on (T1CON<0>)

• TMR1IE bit (PIE1<0>) must be set

• PEIE bit (INTCON<6>) must be set

The device will wake-up on an overflow. If the GIE bit

(INTCON<7>) is set, the device will wake-up and jump

to the Interrupt Service Routine (0004h) on an overflow.

If the GIE bit is clear, execution will continue with the

next instruction.

TABLE 6-1:

REGISTERS ASSOCIATED WITH TIMER1

Value on

POR, BOR

Addr

Name

Bit 7

GIE

Bit 6

PEIE

ADIF

Bit 5

T0IE

RCIF

Bit 4

INTE

TXIF

Bit 3

RBIE

Bit 2

Bit 1

Bit 0

all other

Resets

0Bh/ INTCON

8Bh

T0IF

INTF

RBIF 0000 000x 0000 000x

0Ch

0Eh

0Fh

10h

1Ah

8Ch

PIR1

EEIF

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

T1CON

CMCON1

PIE1

T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

—

T1GSS C2SYNC ---- --10 ---- --10

EEIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

Legend: x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.

Preliminary

DS41250E-page 89

PIC16F917/916/914/913

7.1

Timer2 Operation

7.0

TIMER2 MODULE

Timer2 can be used as the PWM time base for the

PWM mode of the CCP module. The TMR2 register is

readable and writable, and is cleared on any device

Reset. The input clock (FOSC/4) has a prescale option

of 1:1, 1:4 or 1:16, selected by control bits T2CKPSx

(T2CON<1:0>). The match output of TMR2 goes

through a 4-bit postscaler (which gives a 1:1 to 1:16

scaling inclusive) to generate a TMR2 interrupt (latched

in flag bit TMR2IF, (PIR1<1>)).

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match with PR2

Timer2 has a control register shown in Register 7-1.

TMR2 can be shut-off by clearing control bit TMR2ON

(T2CON<2>) to minimize power consumption.

Figure 7-1 is a simplified block diagram of the Timer2

module. The prescaler and postscaler selection of

Timer2 are controlled by this register.

The prescaler and postscaler counters are cleared

when any of the following occurs:

• A write to the TMR2 register

• A write to the T2CON register

• Any device Reset (Power-on Reset, MCLR Reset,

Watchdog Timer Reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

REGISTER 7-1:

T2CON – TIMER2 CONTROL REGISTER (ADDRESS: 12h)

U-0

—

R/W-0

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscale Select bits

0000=1:1 Postscale

0001=1:2 Postscale

•

1111=1:16 Postscale

bit 2

TMR2ON: Timer2 On bit

1= Timer2 is on

0= Timer2 is off

bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits

00=Prescaler is 1

01=Prescaler is 4

1x=Prescaler is 16

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 90

Preliminary

PIC16F917/916/914/913

7.2

Timer2 Interrupt

7.3

Timer2 Output

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon Reset.

The output of TMR2 (before the postscaler) is fed to the

SSP module, which optionally uses it to generate the

shift clock.

FIGURE 7-1:

TIMER2 BLOCK DIAGRAM

Sets Flag

bit TMR2IF

Output⁽¹⁾

TMR2

Prescaler

1:1, 1:4, 1:16

Reset

TMR2

FOSC/4

Postscaler

1:1 to 1:16

EQ

2

Comparator

PR2

T2CKPS<1:0>

4

TOUTPS<3:0>

Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.

TABLE 7-1:

REGISTERS ASSOCIATED WITH TIMER2

Value on

all other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh/

8Bh

INTCON

GIE

PEIE

ADIF

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

RCIF

SSPIF

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

11h

TMR2

T2CON

PIE1

Holding Register for the 8-bit TMR2 Register

0000 0000 0000 0000

12h

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

8Ch

EEIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

92h

PR2

Timer2 Period Register

1111 1111 1111 1111

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Preliminary

DS41250E-page 91

PIC16F917/916/914/913

NOTES:

DS41250E-page 92

Preliminary

PIC16F917/916/914/913

The CMCON0 register (Register 8-1) controls the

comparator input and output multiplexers. A block

diagram of the various comparator configurations is

shown in Figure 8-3.

8.0

COMPARATOR MODULE

The comparator module contains two analog

comparators. The inputs to the comparators are

multiplexed with I/O port pins RA<3:0>, while the outputs

are multiplexed to pins RA<5:4>. An on-chip Comparator

Voltage Reference (CVREF) can also be applied to the

inputs of the comparators.

REGISTER 8-1:

CMCON0 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 9Ch)

R-0

R/W-0

C2INV

R/W-0

C1INV

R/W-0

CIS

R/W-0

CM2

R/W-0

CM1

R/W-0

CM0

C2OUT

C1OUT

bit 7

bit 0

bit 7

C2OUT: Comparator 2 Output bit

When C2INV = 0:

1= C2 VIN+ > C2 VIN-

0= C2 VIN+ < C2 VIN-

When C2INV = 1:

0= C2 VIN+ > C2 VIN-

1= C2 VIN+ < C2 VIN-

bit 6

C1OUT: Comparator 1 Output bit

When C1INV = 0:

1= C1 VIN+ > C1 VIN-

0= C1 VIN+ < C1 VIN-

When C1INV = 1:

0= C1 VIN+ > C1 VIN-

1= C1 VIN+ < C1 VIN-

bit 5

bit 4

bit 3

C2INV: Comparator 2 Output Inversion bit

1= C2 Output inverted

0= C2 Output not inverted

C1INV: Comparator 1 Output Inversion bit

1= C1 Output inverted

0= C1 Output not inverted

CIS: Comparator Input Switch bit

When CM<2:0> = 010:

1= C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15

C2 VIN- connects to RA2/AN2/C2+/VREF-/COM2

0= C1 VIN- connects to RA0/AN0/C1-/SEG12

C2 VIN- connects to RA1/AN1/C2-/SEG7

When CM<2:0> = 001:

1= C1 VIN- connects to RA3/AN3/C1+/VREF+/SEG15

0= C1 VIN- connects to RA0/AN0/C1-/SEG12

When CM<2:0> = 101:

1= C2 VIN+ connects to internal 0.6V reference

0= C2 VIN+ connects to RA2/AN2/C2+/VREF-/COM2

bit 2-0

CM<2:0>: Comparator Mode bits⁽¹⁾

See Figure 8-3 for comparator modes and CM<2:0> bit settings.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit

must be set to Input mode in order to allow external control of the voltage on the pin.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 93

PIC16F917/916/914/913

FIGURE 8-1:

SINGLE COMPARATOR

8.1

Comparator Operation

A single comparator is shown in Figure 8-1 along with

the relationship between the analog input levels and

the digital output. When the analog input at VIN+ is less

than the analog input VIN-, the output of the comparator

is a digital low level. When the analog input at VIN+ is

greater than the analog input VIN-, the output of the

comparator is a digital high level. The shaded areas of

the output of the comparator in Figure 8-1 represent

the uncertainty due to input offsets and response time.

VIN+

VIN-

+

Output

–

VIN-

V

IN–

VIN+

V

IN+

Note: To use CIN+ and CIN- pins as analog

inputs, the appropriate bits must be

programmed in the CMCON0 (9Ch)

register.

Output

The polarity of the comparator output can be inverted

by setting the CxINV bits (CMCON0<5:4>). Clearing

CxINV results in a non-inverted output. A complete

table showing the output state versus input conditions

and the polarity bit is shown in Table 8-1.

8.2

Analog Input Connection

Considerations

A simplified circuit for an analog input is shown in

Figure 8-2. Since the analog pins are connected to a

digital output, they have reverse biased diodes to VDD

and VSS. The analog input, therefore, must be between

VSS and VDD. If the input voltage deviates from this

range by more than 0.6V in either direction, one of the

diodes is forward biased and a latch-up may occur. A

maximum source impedance of 10 kΩ is recommended

for the analog sources. Any external component

connected to an analog input pin, such as a capacitor

or a Zener diode, should have very little leakage.

TABLE 8-1:

OUTPUT STATE VS. INPUT

CONDITIONS

Input Conditions

CINV

CxOUT

VIN- > VIN+

VIN- < VIN+

VIN- > VIN+

VIN- < VIN+

0

1

0

1

0

FIGURE 8-2:

ANALOG INPUT MODEL

VDD

VT = 0.6V

RIC

Rs < 10K

AIN

Leakage

±500 nA

CPIN

5 pF

VA

VT = 0.6V

Vss

Legend: CPIN = Input Capacitance

VT = Threshold Voltage

ILEAKAGE= Leakage Current at the pin due to various junctions

RIC = Interconnect Resistance

RS = Source Impedance

VA = Analog Voltage

DS41250E-page 94

Preliminary

PIC16F917/916/914/913

If the Comparator mode is changed, the comparator

output level may not be valid for the specified mode

change delay shown in Section 19.0 “Electrical

Specifications”.

8.3

Comparator Configuration

There are eight modes of operation for the comparators.

The CMCON0 register is used to select these modes.

Figure 8-3 shows the eight possible modes.

Note:

Comparator interrupts should be disabled

during Comparator mode change.

Otherwise, a false interrupt may occur.

a

FIGURE 8-3:

COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value)

Comparators Off

CM<2:0> = 000

CM<2:0> = 111

RA0/AN0/

C1-/SEG12

A

D

VIN-

RA0/AN0/

C1-/SEG12

RA3/AN3/

C1

Off (Read as ‘0’)

C1

C2

VIN+

RA3/AN3/

C1+/VREF+/SEG15

RA1/AN1/

D

RA1/AN1/

C2-/SEG7

A

VIN-

VIN+

VIN-

C2-/SEG7

C2

VIN+

D

RA2/AN2/

C2+/VREF-/COM2

RA2/AN2/

C2+/VREF-/COM2

Four Inputs Multiplexed to Two Comparators

CM<2:0> = 010

Two Independent Comparators

CM<2:0> = 100

RA0/AN0/

C1-/SEG12

RA3/AN3/

A

RA0/AN0/

C1-/SEG12

CIS = 0

CIS = 1

VIN-

A

VIN-

A

C1OUT

C2OUT

C1

C2

C1OUT

C2OUT

C1

VIN+

C1+/VREF+/SEG15

RA3/AN3/

C1+/VREF+/SEG15

A

RA1/AN1/

C2-/SEG7

RA2/AN2/

VIN-

CIS = 0

CIS = 1

RA1/AN1/

C2-/SEG7

A

VIN-

VIN+

C2+/VREF-/COM2

C2

VIN+

A

RA2/AN2/

C2+/VREF-/COM2

From CVREF Module

Two Common Reference Comparators

Two Common Reference Comparators with Outputs

CM<2:0> = 011

CM<2:0> = 110

A

VIN-

RA0/AN0/

C1-/SEG12

A

D

RA0/AN0/

C1-/SEG12

RA3/AN3/

VIN-

C1OUT

RA4

C1

C2

VIN+

C1OUT

C2OUT

C1

C2

VIN+

C1+/VREF+/SEG15

RA1/AN1/

C2-/SEG7

A

VIN-

RA1/AN1/

C2-/SEG7

A

VIN-

C2OUT

RA5

VIN+

RA2/AN2/

VIN+

RA2/AN2/

C2+/VREF-/COM2

One Independent Comparator with Reference Option

CM<2:0> = 101

Three Inputs Multiplexed to Two Comparators

CM<2:0> = 001

RA0/AN0/

C1-/SEG12

RA0/AN0/

C1-/SEG12

A

D

VIN-

CIS = 0

CIS = 1

VIN-

Off (Read as ‘0’)

C1

VIN+

RA3/AN3/

C1+/VREF+/SEG15

RA3/AN3/

C1+/VREF+/

SEG15

C1OUT

C2OUT

C1

C2

VIN+

RA1/AN1/

A

RA1/AN1/

C2-/SEG7

VIN-

A

VIN-

C2-/SEG7

A

VIN+

A

C2OUT

RA5

C2

RA2/AN2/

C2+/VREF-/

COM2

CIS = 0 VIN+

CIS = 1

C2+/VREF-/COM2

A

Internal 0.6V reference

Legend:

A = Analog Input, port reads zeros always.

D = Digital Input.

CIS (CMCON0<3>) is the computer Input Switch.

DS41250E-page 95

Preliminary

PIC16F917/916/914/913

FIGURE 8-4:

COMPARATOR C1 OUTPUT BLOCK DIAGRAM

C1INV

To C1OUT pin

To Data Bus

Q

D

EN

Q

RD CMCON

Set C1IF bit

D

RD CMCON

EN

CL

NReset

FIGURE 8-5:

COMPARATOR C2 OUTPUT BLOCK DIAGRAM

C2INV

C2SYNC

To TMR1

To C2OUT pin

0

1

Q

D

TMR1

Clock Source

EN

(1)

To Data Bus

D

EN

Q

RD CMCON

Set C2IF bit

D

RD CMCON

EN

CL

Reset

Note 1: Comparator 2 output is latched on falling edge of T1 clock source.

DS41250E-page 96

Preliminary

PIC16F917/916/914/913

REGISTER 8-2:

CMCON1 – COMPARATOR CONFIGURATION REGISTER (ADDRESS: 97h)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-1

R/W-0

C2SYNC

bit 0

T1GSS

bit 7

bit 7-2:

bit 1

Unimplemented: Read as ‘0’

T1GSS: Timer1 Gate Source Select bit

1= Timer1 gate source is T1G pin (RC4 must be configured as digital input)

0= Timer1 gate source is Comparator 2 Output

bit 0

C2SYNC: Comparator 2 Synchronize bit

1= C2 output synchronized with falling edge of Timer1 clock

0= C2 output not synchronized with Timer1 clock

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

8.4

Comparator Outputs

8.5

Comparator Interrupts

The comparator outputs are read through the

CMCON0 register. These bits are read-only. The

comparator outputs may also be directly output to the

RA4 and RA5 I/O pins. When enabled, multiplexers in

the output path of the RA4 and RA5 pins will switch

and the output of each pin will be the unsynchronized

output of the comparator. The uncertainty of each of

the comparators is related to the input offset voltage

and the response time given in the specifications.

Figure 8-4 and Figure 8-5 show the output block

diagram for Comparator 1 and 2.

The comparator interrupt flags are set whenever there is

a change in the output value of its respective comparator.

Software will need to maintain information about the

status of the output bits, as read from CMCON0<7:6>, to

determine the actual change that has occurred. The CxIF

bits, PIR2<6:5>, are the Comparator Interrupt flags. This

bit must be reset in software by clearing it to ‘0’. Since it

is also possible to write a ‘1’ to this register, a simulated

interrupt may be initiated.

The CxIE bits (PIE2<6:5>) and the PEIE bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CxIF bits will still be set if an interrupt condition occurs.

The TRIS bits will still function as an output

enable/disable for the RA4 and RA5 pins while in this

mode.

The polarity of the comparator outputs can be changed

using the C1INV and C2INV bits (CMCON0<5:4>).

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS

bit (CMCON1<1>). This feature can be used to time

the duration or interval of analog events. The output of

Comparator 2 can also be synchronized with Timer1

by setting the C2SYNC bit (CMCON1<0>). When

enabled, the output of Comparator 2 is latched on the

falling edge of Timer1 clock source. If a prescaler is

used with Timer1, Comparator 2 is latched after the

prescaler. To prevent a race condition, the Comparator

2 output is latched on the falling edge of the Timer1

clock source and Timer1 increments on the rising edge

of its clock source. See (Figure 8-5), Comparator 2

Block Diagram and (Figure 6-1), Timer1 Block

Diagram for more information.

a) Any read or write of CMCON0. This will end the

mismatch condition.

b) Clear flag bit CxIF

A mismatch condition will continue to set flag bit CxIF.

Reading CMCON0 will end the mismatch condition and

allow flag bits CxIF to be cleared.

Note: If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the Q2

cycle), then the CxIF (PIR2<6:5>) interrupt

flag may not get set.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

Preliminary

DS41250E-page 97

PIC16F917/916/914/913

8.6.2

VOLTAGE REFERENCE

ACCURACY/ERROR

8.6

Comparator Reference

The comparator module also allows the selection of an

internally generated voltage reference for one of the

comparator inputs. The VRCON register, Register 8-3,

controls the voltage reference module shown in

Figure 8-6.

The full range of VSS to VDD cannot be realized due to

the construction of the module. The transistors on the

top and bottom of the resistor ladder network

(Figure 8-6) keep CVREF from approaching VSS or

VDD. The exception is when the module is disabled by

clearing the VREN bit (VRCON<7>). When disabled,

the reference voltage is VSS when VR<3:0> = 0000.

This allows the comparators to detect a zero-crossing

and not consume CVREF module current.

8.6.1

CONFIGURING THE VOLTAGE

REFERENCE

The voltage reference can output 32 distinct voltage

levels; 16 in a high range and 16 in a low range.

The voltage reference is VDD derived and therefore, the

CVREF output changes with fluctuations in VDD. The

tested absolute accuracy of the comparator voltage

reference can be found in Section 19.0 “Electrical

Specifications”.

The following equation determines the output voltages:

EQUATION 8-1:

VRR = 1(low range): CVREF = (VR3:VR0/24) x VDD

VRR = 0(high range):

CVREF = (VDD/4) + (VR3:VR0 x VDD/32)

FIGURE 8-6:

COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM

16 Stages

8R

R

VDD

VRR

8R

16-1 Analog

MUX

VREN

CVREF to

Comparator

Input

VR<3:0>

VREN

VR <3:0> = ‘0000’

VRR

DS41250E-page 98

Preliminary

PIC16F917/916/914/913

8.7

Comparator Response Time

8.9

Effects of a Reset

Response time is the minimum time, after selecting a

new reference voltage or input source, before the

comparator output is ensured to have a valid level. If

the internal reference is changed, the maximum delay

of the internal voltage reference must be considered

when using the comparator outputs. Otherwise, the

maximum delay of the comparators should be used

(Table 19-10).

A device Reset forces the CMCON0, CMCON1 and

VRCON registers to their Reset states. This forces the

comparator module to be in the Comparator Reset

mode, CM<2:0> = 000and the voltage reference to its

OFF state. Thus, all potential inputs are analog inputs

with the comparator and voltage reference disabled to

consume the smallest current possible.

8.8

Operation During Sleep

The comparators and voltage reference, if enabled

before entering Sleep mode, remain active during

Sleep. This results in higher Sleep currents than shown

in the power-down specifications. The additional

current consumed by the comparator and the voltage

reference is shown separately in the specifications. To

minimize power consumption while in Sleep mode, turn

off the comparator, CM<2:0> = 111, and voltage

reference, VRCON<7> = 0.

While the comparator is enabled during Sleep, an

interrupt will wake-up the device. If the GIE bit

(INTCON<7>) is set, the device will jump to the inter-

rupt vector (0004h), and if clear, continues execution

with the next instruction. If the device wakes up from

Sleep, the contents of the CMCON0, CMCON1 and

VRCON registers are not affected.

Preliminary

DS41250E-page 99

PIC16F917/916/914/913

REGISTER 8-3:

VRCON – VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 9Dh)

R/W-0

VREN

U-0

—

R/W-0

VRR

R/W-0

—

R/W-0

VR3

R/W-0

VR2

R/W-0

VR1

R/W-0

VR0

bit 7

bit 0

bit 7

VREN: CVREF Enable bit

1= CVREF circuit powered on

0= CVREF circuit powered down, no IDD drain and CVREF = VSS.

bit 6

bit 5

Unimplemented: Read as ‘0’

VRR: CVREF Range Selection bit

1= Low range

0= High range

bit 4

Unimplemented: Read as ‘0’

bit 3-0

VR<3:0>: CVREF value selection 0 ≤ VR<3:0> ≤ 15

When VRR = 1: CVREF = (VR<3:0>/24) * VDD

When VRR = 0: CVREF = VDD/4 + (VR<3:0>/32) * VDD

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

TABLE 8-2:

REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

POR, BOR

Resets

0Bh/8Bh

0Dh

INTCON

PIR2

GIE

OSFIF

C2OUT

—

PEIE

C2IF

C1OUT

—

T0IE

C1IF

INTE

LCDIF

C1INV

—

RBIE

—

T0IF

LVDIF

CM2

INTF

—

RBIF

CCP2IF

CM0

0000 000x

0000 -0-0

0000 0000

---- --10

1111 1111

0000 -0-0

0-0- 0000

0000 000x

0000 -0-0

0000 0000

---- --10

1111 1111

0000 -0-0

0-0- 0000

9Ch

CMCON0

CMCON1

TRISA

C2INV

—

CIS

CM1

97h

—

T1GSS C2SYNC

85h

TRISA7

OSFIE

VREN

TRISA6

C2IE

—

TRISA5

C1IE

VRR

TRISA4

LCDIE

—

TRISA3

—

TRISA2

LVDIE

VR2

TRISA1

—

TRISA0

CCP2IE

VR0

8Dh

PIE2

9Dh

VRCON

VR3

VR1

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the comparator or Comparator Voltage

Reference module.

DS41250E-page 100

Preliminary

PIC16F917/916/914/913

Once the module is initialized for the LCD panel, the

individual bits of the LCDDATA<11:0> registers are

9.0

LIQUID CRYSTAL DISPLAY

(LCD) DRIVER MODULE

cleared/set to represent

respectively:

a

clear/dark pixel,

The Liquid Crystal Display (LCD) driver module generates

the timing control to drive a static or multiplexed LCD

panel. In the PIC16F914/917 devices (PIC16F914/917),

the module drives the panels of up to four commons and

up to 24 segments and in the PIC16F913/916 devices

(PIC16F913/916), the module drives the panels of up to

four commons and up to 16 segments. It also provides

control of the LCD pixel data.

• LCDDATA0 SEG7COM0:SEG0COM0

• LCDDATA1 SEG15COM0:SEG8COM0

• LCDDATA2 SEG23COM0:SEG16COM0

• LCDDATA3 SEG7COM1:SEG0COM1

• LCDDATA4 SEG15COM1:SEG8COM1

• LCDDATA5 SEG23COM1:SEG16COM1

• LCDDATA6 SEG7COM2:SEG0COM2

• LCDDATA7 SEG15COM2:SEG8COM2

• LCDDATA8 SEG23COM2:SEG16COM2

• LCDDATA9 SEG7COM3:SEG0COM3

• LCDDATA10 SEG15COM3:SEG8COM3

• LCDDATA11 SEG23COM3:SEG16COM3

The LCD driver module supports:

• Direct driving of LCD panel

• Three LCD clock sources with selectable prescaler

• Up to four commons:

- Static

- 1/2 multiplex

- 1/3 multiplex

As an example, LCDDATAx is detailed in Register 9-4.

- 1/4 multiplex

Once the module is configured, the LCDEN

(LCDCON<7>) bit is used to enable or disable the LCD

module. The LCD panel can also operate during Sleep

by clearing the SLPEN (LCDCON<6>) bit.

• Up to 24 (in PIC16F914/917 devices)/16 (in

PIC16F913/916 devices) segments

• Static, 1/2 or 1/3 LCD Bias

The module has 32 registers:

Note:

Writing into the registers LCDDATA2,

LCDDATA5, LCDDATA8 and LCDDATA11

in PIC16F913/916 devices will not affect the

status of any pixel and these registers can

be used as General Purpose Registers.

• LCD Control Register (LCDCON)

• LCD Phase Register (LCDPS)

• Three LCD Segment Enable Registers

(LCDSE<2:0>)

• 24 LCD Data Registers (LCDDATA<11:0>)

The LCDCON register, shown in Register 9-1, controls

the operation of the LCD driver module. The LCDPS

register, shown in Register 9-2, configures the LCD

clock source prescaler and the type of waveform;

Type-A or Type-B. The LCDSE<2:0> registers configure

the functions of the port pins:

• LCDSE0 SE<7:0>

• LCDSE1 SE<15:8>

• LCDSE2 SE<23:16>

As an example, LCDSEn is detailed in Register 9-3.

Note:

The LCDSE2 register is not implemented

in PIC16F913/916 devices.

Preliminary

DS41250E-page 101

PIC16F917/916/914/913

FIGURE 9-1:

LCD DRIVER MODULE BLOCK DIAGRAM

96

to

24

LCDDATAx

Registers

12 x 8

(= 4 x 24)

SEG<23:0>

Data Bus

To I/O Pads⁽¹⁾

MUX

Timing Control

LCDCON

LCDPS

COM<3:0>

To I/O Pads⁽¹⁾

LCDSEn

FOSC/8192

T10SC/32

Clock Source

Select and

Prescaler

LFINTOSC/32

Note 1: These are not directly connected to the I/O pads. See Section 3.0 “I/O Ports” for more detail.

DS41250E-page 102

Preliminary

PIC16F917/916/914/913

REGISTER 9-1:

LCDCON–LIQUIDCRYSTALDISPLAYCONTROLREGISTER(ADDRESS:107h)

R/W-0

R/C-0

R/W-1

R/W-0

CS1

R/W-0

CS0

R/W-1

LCDEN

SLPEN

WERR

VLCDEN

LMUX1

LMUX0

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

LCDEN: LCD Driver Enable bit

1= LCD driver module is enabled

0= LCD driver module is disabled

SLPEN: LCD Driver Enable in Sleep mode bit

1= LCD driver module is disabled in Sleep mode

0= LCD driver module is enabled in Sleep mode

WERR: LCD Write Failed Error bit

1= LCDDATAx register written while LCDPS<WA> = 0(must be cleared in software)

0= No LCD write error

VLCDEN: LCD Bias Voltage Pins Enable bit

1= VLCD pins are enabled

0= VLCD pins are disabled

bit 3-2 CS<1:0>: Clock Source Select bits

00= FOSC/8192

01= T1OSC (Timer1)/32

1x= LFINTOSC (31 kHz)/32

bit 1-0 LMUX<1:0>: Commons Select bits

Maximum

LMUX<1:0>

Multiplex

Number of Pixels Number of Pixels

(PIC16F913/916) (PIC16F914/917)

Bias

Static

00

01

10

11

Static (COM0)

1/2 (COM<1:0>)

1/3 (COM<2:0>)

1/4 (COM<3:0>)

16

32

24

48

72

96

1/2 or 1/3

1/3

48

60⁽¹⁾

Note 1: On PIC16F913/916 devices, COM3 and SEG15 are shared on one pin, limiting the

device from driving 64 pixels.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

C = Only clearable bit

- n = Value at POR

Preliminary

DS41250E-page 103

PIC16F917/916/914/913

REGISTER 9-2:

LCDPS – LCD PRESCALER SELECT REGISTER (ADDRESS: 108h)

R/W-0

WFT

R/W-0

R-0

WA

R/W-0

LP3

R/W-0

LP2

R/W-0

LP1

R/W-0

LP0

BIASMD

LCDA

bit 7

bit 0

bit 7

bit 6

WFT: Waveform Type Select bit

1= Type-B waveform (phase changes on each frame boundary)

0= Type-A waveform (phase changes within each common type)

BIASMD: Bias Mode Select bit

When LMUX<1:0> = 00:

0= Static Bias mode (do not set this bit to ‘1’)

When LMUX<1:0> = 01:

1= 1/2 Bias mode

0= 1/3 Bias mode

When LMUX<1:0> = 10:

1= 1/2 Bias mode

0= 1/3 Bias mode

When LMUX<1:0> = 11:

0= 1/3 Bias mode (do not set this bit to ‘1’)

LCDA: LCD Active Status bit

bit 5

1= LCD driver module is active

0= LCD driver module is inactive

bit 4

WA: LCD Write Allow Status bit

1= Write into the LCDDATAx registers is allowed

0= Write into the LCDDATAx registers is not allowed

bit 3-0

LP<3:0>: LCD Prescaler Select bits

1111= 1:16

1110= 1:15

1101= 1:14

1100= 1:13

1011= 1:12

1010= 1:11

1001= 1:10

1000= 1:9

0111= 1:8

0110= 1:7

0101= 1:6

0100= 1:5

0011= 1:4

0010= 1:3

0001= 1:2

0000= 1:1

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 104

Preliminary

PIC16F917/916/914/913

REGISTER 9-3:

LCDSEn – LCD SEGMENT REGISTERS (ADDRESS: 11Ch, 11Dh OR 11Eh)

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

R/W-0

SEn

bit 7

bit 0

bit 7-0

SEn: Segment Enable bits

1= Segment function of the pin is enabled

0= I/O function of the pin is enabled

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 9-4:

LCDDATAx – LCD DATA REGISTERS (ADDRESS: 110h-119h, 11Ah, 11Bh)

R/W-0

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

SEGx-

COMy

bit 7

bit 0

bit 7-0

SEGx-COMy: Pixel On bits

1= Pixel on (dark)

0= Pixel off (clear)

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

Preliminary

DS41250E-page 105

PIC16F917/916/914/913

9.1.1

LCD PRESCALER

9.1

LCD Clock Source Selection

A 16-bit counter is available as a prescaler for the LCD

clock. The prescaler is not directly readable or writable;

its value is set by the LP<3:0> bits (LCDPS<3:0>), which

determine the prescaler assignment and prescale ratio.

The LCD driver module has 3 possible clock sources:

• FOSC/8192

• T1OSC/32

• LFINTOSC/32

The prescale values from 1:1 through 1:16.

The first clock source is the system clock divided by

8192 (FOSC/8192). This divider ratio is chosen to

provide about 1 kHz output when the system clock is

8 MHz. The divider is not programmable. Instead, the

LCD prescaler bits, LCDPS<3:0>, are used to set the

LCD frame clock rate.

9.2

LCD Bias Types

The LCD driver module can be configured into three

bias types:

• Static Bias (2 voltage levels: VSS and VDD)

The second clock source is the T1OSC/32. This also

gives about 1 kHz when a 32.768 kHz crystal is used

with the Timer1 oscillator. To use the Timer1 oscillator

as a clock source, the T1OSCEN (T1CON<3>) bit

should be set.

• 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD)

• 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD

and VDD)

This module uses an external resistor ladder to

generate the LCD bias voltages.

The third clock source is the 31 kHz LFINTOSC/32,

which provides approximately 1 kHz output.

The external resistor ladder should be connected to the

Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3

pin should also be connected to VDD.

The second and third clock sources may be used to

continue running the LCD while the processor is in

Sleep.

Figure 9-2 shows the proper way to connect the

resistor ladder to the Bias pins.

Using the bits, CS<1:0> (LCDCON<3:2>), any of these

clock sources can be selected.

Note:

VLCD pins used to supply LCD bias

voltage are enabled on power-up (POR)

and must be disabled by the user by

clearing LCDCON<4>, the VLCDEN bit,

(see Register 9-1).

FIGURE 9-2:

LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM

Static

1/2 Bias 1/3 Bias

Bias

VLCD 0

VLCD 1

VLCD 2

VLCD 3

VSS

—

VSS

VLCD 3

VLCD 2

VLCD 1

VLCD 0⁽¹⁾

1/2 VDD 1/3 VDD

1/2 VDD 2/3 VDD

To

LCD

Driver

—

VDD

LCD Bias 3

LCD Bias 2 LCD Bias 1

Connections for External R-ladder

Static Bias

VDD*

1/2 Bias

10 kΩ*

VSS

1/3 Bias

10 kΩ*

VDD*

VSS

*

These values are provided for design guidance only and should be optimized for the application by the

designer.

Note 1: Internal connection.

DS41250E-page 106

Preliminary

PIC16F917/916/914/913

9.3

LCD Multiplex Types

9.6

LCD Frame Frequency

The LCD driver module can be configured into four

multiplex types:

The rate at which the COM and SEG outputs change is

called the LCD frame frequency.

• Static (only COM0 used)

TABLE 9-2:

FRAME FREQUENCY

FORMULAS

• 1/2 multiplex (COM0 and COM1 are used)

• 1/3 multiplex (COM0, COM1 and COM2 are used)

Multiplex

Frame Frequency =

• 1/4 multiplex (all COM0, COM1, COM2 and COM3

are used)

Static

1/2

Clock source/(4 x 1 x (LP<3:0> + 1))

Clock source/(2 x 2 x (LP<3:0> + 1))

Clock source/(1 x 3 x (LP<3:0> + 1))

Clock source/(1 x 4 x (LP<3:0> + 1))

The LMUX<1:0> setting decides the function of RB5,

RA2 or either RA3 or RD0 pins (see Table 9-1 for

details).

1/3

1/4

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. If the pin is a COM drive,

then the TRIS setting of that pin is overridden.

Note:

Clock source is FOSC/8192, T1OSC/32 or

LFINTOSC/32.

Note:

On a Power-on Reset, the LMUX<1:0>

bits are ‘11’.

TABLE 9-3:

APPROXIMATE FRAME

FREQUENCY (IN Hz) USING

FOSC @ 8 MHz, TIMER1 @

32.768 kHz OR INTOSC

TABLE 9-1:

LMUX

RA3, RA2, RB5 FUNCTION

RA3/RD0⁽¹⁾

RA2

RB5

LP<3:0>

Static

1/2

1/3

1/4

<1:0>

2

3

4

5

6

7

85

64

51

43

37

32

85

64

51

43

37

32

114

85

68

57

49

43

85

64

51

43

37

32

00

01

10

11

Digital I/O

Digital I/O COM1 Driver

Digital I/O COM2 Driver COM1 Driver

COM3 Driver COM2 Driver COM1 Driver

Note 1: RA3 for PIC16F913/916, RD0 for

PIC16F914/917

9.4

Segment Enables

The LCDSEn registers are used to select the pin

function for each segment pin. The selection allows

each pin to operate as either an LCD segment driver or

as one of the pin’s alternate functions. To configure the

pin as a segment pin, the corresponding bits in the

LCDSEn registers must be set to ‘1’.

If the pin is a digital I/O, the corresponding TRIS bit

controls the data direction. Any bit set in the LCDSEn

registers overrides any bit settings in the corresponding

TRIS register.

Note:

On a Power-on Reset, these pins are

configured as digital I/O.

9.5

Pixel Control

The LCDDATAx registers contain bits which define the

state of each pixel. Each bit defines one unique pixel.

Register 9-4 shows the correlation of each bit in the

LCDDATAx registers to the respective common and

segment signals.

Any LCD pixel location not being used for display can

be used as general purpose RAM.

Preliminary

DS41250E-page 107

PIC16F917/916/914/913

FIGURE 9-3:

LCD CLOCK GENERATION

FOSC

÷8192

STAT

DUP

÷4

T1OSC 32 kHz

Crystal Osc.

÷32

÷1, 2, 3, 4

Ring Counter

4-bit Prog Presc

÷2

TRIP

QUAD

LFINTOSC

Nom FRC = 31 kHz

÷32

LP<3:0>

(LCDPS<3:0>)

LMUX<1:0>

(LCDCON<1:0>)

CS<1:0>

(LCDCON<3:2>)

LMUX<1:0>

(LCDCON<1:0>)

DS41250E-page 108

Preliminary

PIC16F917/916/914/913

FIGURE 9-4:

LCD SEGMENT MAPPING WORKSHEET

Preliminary

DS41250E-page 109

PIC16F917/916/914/913

The LCDs can be driven by two types of waveform:

Type-A and Type-B. In Type-A waveform, the phase

changes within each common type, whereas in Type-B

waveform, the phase changes on each frame

boundary. Thus, Type-A waveform maintains 0 VDC

over a single frame, whereas Type-B waveform takes

two frames.

9.7

LCD Waveform Generation

LCD waveforms are generated so that the net AC

voltage across the dark pixel should be maximized and

the net AC voltage across the clear pixel should be

minimized. The net DC voltage across any pixel should

be zero.

The COM signal represents the time slice for each

common, while the SEG contains the pixel data.

Note 1: If Sleep has to be executed with LCD

Sleep enabled (LCDCON<SLPEN> is

‘1’), then care must be taken to execute

Sleep only when VDC on all the pixels is

‘0’.

The pixel signal (COM-SEG) will have no DC compo-

nent and it can take only one of the two rms values. The

higher rms value will create a dark pixel and a lower

rms value will create a clear pixel.

2: When the LCD clock source is FOSC/8192,

if Sleep is executed, irrespective of the

LCDCON<SLPEN> setting, the LCD goes

into Sleep. Thus, take care to see that VDC

on all pixels is ‘0’ when Sleep is executed.

As the number of commons increases, the delta

between the two rms values decreases. The delta

represents the maximum contrast that the display can

have.

Figure 9-5 through Figure 9-15 provide waveforms for

static,

half-multiplex,

one-third-multiplex

and

quarter-multiplex drives for Type-A and Type-B

waveforms.

FIGURE 9-5:

TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE

V₁

COM0

SEG0

SEG1

V₀

V₁

COM0

V₀

V₁

V₀

V₁

V₀

COM0-SEG0

COM0-SEG1

-V₁

V₀

1 Frame

DS41250E-page 110

Preliminary

PIC16F917/916/914/913

FIGURE 9-6:

TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0

COM1

COM0

V₂

V₁

V₀

V₂

V₁

V₀

SEG0

SEG1

V₂

V₁

V₀

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

1 Frame

Preliminary

DS41250E-page 111

PIC16F917/916/914/913

FIGURE 9-7:

TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0

COM1

COM0

V₂

V₁

V₀

COM1

SEG0

V₂

V₁

V₀

V₂

V₁

V₀

SEG1

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

2 Frames

DS41250E-page 112

Preliminary

PIC16F917/916/914/913

FIGURE 9-8:

TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM0

COM1

COM0

COM1

SEG0

SEG1

V₃

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

-V₃

1 Frame

Preliminary

DS41250E-page 113

PIC16F917/916/914/913

FIGURE 9-9:

TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM0

COM1

COM0

COM1

SEG0

SEG1

V₃

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

-V₃

2 Frames

DS41250E-page 114

Preliminary

PIC16F917/916/914/913

FIGURE 9-10:

TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0

V₂

V₁

V₀

COM2

COM1

COM2

COM1

COM0

V₂

V₁

V₀

V₂

V₁

V₀

SEG0

SEG2

V₂

V₁

V₀

SEG1

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

1 Frame

Preliminary

DS41250E-page 115

PIC16F917/916/914/913

FIGURE 9-11:

TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

V₂

V₁

V₀

COM0

COM1

COM2

SEG0

SEG1

COM2

V₂

V₁

V₀

COM1

COM0

V₂

V₁

V₀

V₂

V₁

V₀

V₂

V₁

V₀

V₂

V₁

V₀

COM0-SEG0

-V₁

-V₂

V₂

V₁

V₀

COM0-SEG1

-V₁

-V₂

2 Frames

DS41250E-page 116

Preliminary

PIC16F917/916/914/913

FIGURE 9-12:

TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

COM0

COM1

COM2

COM1

COM0

SEG0

SEG2

SEG1

COM0-SEG0

COM0-SEG1

1 Frame

Preliminary

DS41250E-page 117

PIC16F917/916/914/913

FIGURE 9-13:

TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

V₃

V₂

V₁

V₀

-V₁

-V₂

-V₃

COM0

COM1

COM2

SEG0

SEG1

COM2

COM1

COM0

COM0-SEG0

COM0-SEG1

2 Frames

DS41250E-page 118

Preliminary

PIC16F917/916/914/913

FIGURE 9-14:

COM3

TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

V

3

2

1

0

COM2

COM0

COM1

V

3

2

1

0

COM1

COM0

V

3

2

1

0

COM2

COM3

SEG0

SEG1

V

3

2

1

0

V

3

2

1

0

V

3

2

1

0

V

-V

3

2

1

0

COM0-SEG0

COM0-SEG1

1

2

3

V

3

2

1

0

-V

1

2

3

1 Frame

Preliminary

DS41250E-page 119

PIC16F917/916/914/913

FIGURE 9-15:

COM3

TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

V

3

2

1

0

COM2

COM0

COM1

V

3

2

1

0

COM1

COM0

V

3

2

1

0

COM2

COM3

SEG0

SEG1

V

3

2

1

0

V

3

2

1

0

V

3

2

1

0

V

-V

3

2

1

0

COM0-SEG0

COM0-SEG1

1

2

3

V

3

2

1

0

-V

1

2

3

2 Frames

DS41250E-page 120

Preliminary

PIC16F917/916/914/913

When the LCD driver is running with Type-B waveforms

and the LMUX<1:0> bits are not equal to ‘00’, there are

some additional issues that must be addressed. Since

the DC voltage on the pixel takes two frames to maintain

zero volts, the pixel data must not change between

subsequent frames. If the pixel data were allowed to

change, the waveform for the odd frames would not

necessarily be the complement of the waveform

generated in the even frames and a DC component

would be introduced into the panel. Therefore, when

using Type-B waveforms, the user must synchronize the

LCD pixel updates to occur within a subframe after the

frame interrupt.

9.8

LCD Interrupts

The LCD timing generation provides an interrupt that

defines the LCD frame timing. This interrupt can be

used to coordinate the writing of the pixel data with the

start of a new frame. Writing pixel data at the frame

boundary allows a visually crisp transition of the image.

This interrupt can also be used to synchronize external

events to the LCD.

A new frame is defined to begin at the leading edge of

the COM0 common signal. The interrupt will be set

immediately after the LCD controller completes

accessing all pixel data required for a frame. This will

occur at a fixed interval before the frame boundary

(TFINT), as shown in Figure 9-16. The LCD controller

will begin to access data for the next frame within the

interval from the interrupt to when the controller begins

to access data after the interrupt (TFWR). New data

must be written within TFWR, as this is when the LCD

controller will begin to access the data for the next

frame.

To correctly sequence writing while in Type-B, the

interrupt will only occur on complete phase intervals. If the

user attempts to write when the write is disabled, the

WERR (LCDCON<5>) bit is set.

Note: The interrupt is not generated when the

Type-A waveform is selected and when the

Type-B with no multiplex (static) is

selected.

FIGURE 9-16:

WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE

(EXAMPLE – TYPE-B, NON-STATIC)

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

V

3

2

1

0

COM0

COM1

V

3

2

1

0

V

3

2

1

0

COM2

COM3

V

3

2

1

0

2 Frames

Frame

TFINT

TFWR

Frame

Boundary

Frame

Boundary

TFWR = TFRAME/2*(LMUX<1:0> + 1) + TCY/2

TFINT = (TFWR/2 – (2 TCY + 40 ns)) → minimum = 1.5(TFRAME/4) – (2 TCY + 40 ns)

(TFWR/2 – (1 TCY + 40 ns)) → maximum = 1.5(TFRAME/4) – (1 TCY + 40 ns)

Preliminary

DS41250E-page 121

PIC16F917/916/914/913

9.9

Operation During Sleep

The LCD module can operate during Sleep. The selec-

tion is controlled by bit SLPEN (LCDCON<6>). Setting

the SLPEN bit allows the LCD module to go to Sleep.

Clearing the SLPEN bit allows the module to continue

to operate during Sleep.

If a SLEEPinstruction is executed and SLPEN = 1, the

LCD module will cease all functions and go into a very

low-current Consumption mode. The module will stop

operation immediately and drive the minimum LCD

voltage on both segment and common lines.

Figure 9-17 shows this operation.

To ensure that no DC component is introduced on the

panel, the SLEEPinstruction should be executed imme-

diately after a LCD frame boundary. The LCD interrupt

can be used to determine the frame boundary. See

Section 9.8 “LCD Interrupts” for the formulas to

calculate the delay.

If a SLEEPinstruction is executed and SLPEN = 0, the

module will continue to display the current contents of

the LCDDATA registers. To allow the module to

continue operation while in Sleep, the clock source

must be either the LFINTOSC or T1OSC external

oscillator. While in Sleep, the LCD data cannot be

changed. The LCD module current consumption will

not decrease in this mode; however, the overall

consumption of the device will be lower due to shut

down of the core and other peripheral functions.

Table 9-4 shows the status of the LCD module during

a Sleep while using each of the three available clock

sources:

TABLE 9-4:

LCD MODULE STATUS

DURING SLEEP

Operation

During Sleep?

Clock Source

T1OSC

SLPEN

0

1

0

1

0

1

Yes

No

Yes

No

LFINTOSC

FOSC/4

Note:

The LFINTOSC or external T1OSC

oscillator must be used to operate the LCD

module during Sleep.

DS41250E-page 122

Preliminary

PIC16F917/916/914/913

FIGURE 9-17:

SLEEP ENTRY/EXIT WHEN SLPEN = 1 OR CS<1:0> = 00

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

V₃

V₂

V₁

V₀

COM0

COM1

COM2

SEG0

2 Frames

Wake-up

SLEEPInstruction Execution

Preliminary

DS41250E-page 123

PIC16F917/916/914/913

4. Write initial values to pixel data registers,

LCDDATA0 through LCDDATA11.

9.10 Configuring the LCD Module

The following is the sequence of steps to configure the

LCD module.

5. Clear LCD Interrupt Flag, LCDIF (PIR2<4>) and

if desired, enable the interrupt by setting bit

LCDIE (PIE2<4>).

1. Select the frame clock prescale using bits

LP<3:0> (LCDPS<3:0>).

6. Enable bias voltage pins (VLCD<3:1>) by

setting VLCDEN (LCDCON<4>).

2. Configure the appropriate pins to function as

segment drivers using the LCDSEn registers.

7. Enable the LCD module by setting bit LCDEN

(LCDCON<7>).

3. Configure the LCD module for the following

using the LCDCON register:

-Multiplex and Bias mode, bits LMUX<1:0>

-Timing source, bits CS<1:0>

-Sleep mode, bit SLPEN

TABLE 9-5:

REGISTERS ASSOCIATED WITH LCD OPERATION

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

10h

T1CON

INTCON

T1GINV

GIE

T1GE

PEIE

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

0Bh/8Bh/

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

10Bh/18Bh

0Dh

PIR2

0000 -0-0 0000 -0-0

OSFIF

OSFIE

LCDEN

WFT

C2IF

C2IE

C1IF

C1IE

LCDIF

LCDIE

VLCDEN

WA

—

LVDIF

LVDIE

CS0

—

CCP2IF

CCP2IE

8Dh

PIE2

107h

108h

110h

LCDCON

LCDPS

LCDDATA0

SLPEN

BIASMD

WERR

LCDA

CS1

LP3

LMUX1

LP1

LMUX0 0001 0011 0001 0011

LP2

LP0

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

SEG7

COM0

SEG6

COM0

SEG5

COM0

SEG4

COM0

SEG3

COM0

SEG2

COM0

SEG1

COM0

SEG0

COM0

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

LCDDATA1

LCDDATA2⁽²⁾

LCDDATA3

LCDDATA4

LCDDATA5⁽²⁾

LCDDATA6

LCDDATA7

LCDDATA8⁽²⁾

LCDDATA9

LCDDATA10

LCDDATA11⁽²⁾

SEG15

COM0

SEG14

COM0

SEG13

COM0

SEG12

COM0

SEG11

COM0

SEG10

COM0

SEG9

COM0

SEG8

COM0

xxxx xxxx uuuu uuuu

SEG23

COM0

SEG22

COM0

SEG21

COM0

SEG20

COM0

SEG19

COM0

SEG18

COM0

SEG17

COM0

SEG16 xxxx xxxx uuuu uuuu

COM0

SEG7

COM1

SEG6

COM1

SEG5

COM1

SEG4

COM1

SEG3

COM1

SEG2

COM1

SEG1

COM1

SEG0

COM1

xxxx xxxx uuuu uuuu

SEG15

COM1

SEG14

COM1

SEG13

COM1

SEG12

COM1

SEG11

COM1

SEG10

COM1

SEG9

COM1

SEG8

COM1

SEG23

COM1

SEG22

COM1

SEG21

COM1

SEG20

COM1

SEG19

COM1

SEG18

COM1

SEG17

COM1

SEG16 xxxx xxxx uuuu uuuu

COM1

SEG7

COM2

SEG6

COM2

SEG5

COM2

SEG4

COM2

SEG3

COM2

SEG2

COM2

SEG1

COM2

SEG0

COM2

xxxx xxxx uuuu uuuu

SEG15

COM2

SEG14

COM2

SEG13

COM2

SEG12

COM2

SEG11

COM2

SEG10

COM2

SEG9

COM2

SEG8

COM2

SEG23

COM2

SEG22

COM2

SEG21

COM2

SEG20

COM2

SEG19

COM2

SEG18

COM2

SEG17

COM2

SEG16 xxxx xxxx uuuu uuuu

COM2

SEG7

COM3

SEG6

COM3

SEG5

COM3

SEG4

COM3

SEG3

COM3

SEG2

COM3

SEG1

COM3

SEG0

COM3

xxxx xxxx uuuu uuuu

SEG15

COM3

SEG14

COM3

SEG13

COM3

SEG12

COM3

SEG11

COM3

SEG10

COM3

SEG9

COM3

SEG8

COM3

SEG23

COM3

SEG22

COM3

SEG21

COM3

SEG20

COM3

SEG19

COM3

SEG18

COM3

SEG17

COM3

SEG16 xxxx xxxx uuuu uuuu

COM3

11Ch

11Dh

11Eh

LCDSE0⁽³⁾

LCDSE1⁽³⁾

LCDSE2^(2,3)

SE7

SE15

SE23

SE6

SE14

SE22

SE5

SE13

SE21

SE4

SE12

SE20

SE3

SE11

SE19

SE2

SE10

SE18

SE1

SE9

SE0

SE8

0000 0000 uuuu uuuu

SE17

SE16

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the LCD module.

Note 1:

These pins may be configured as port pins, depending on the oscillator mode selected.

2:

3:

PIC16F914/917 only.

This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

DS41250E-page 124

Preliminary

PIC16F917/916/914/913

10.1.1

PLVD CALIBRATION

10.0 PROGRAMMABLE

LOW-VOLTAGE DETECT

(PLVD) MODULE

The PIC16F91X stores the PLVD calibration values in

fuses located in the Calibration Word 2 (2009h). The

Calibration Word 2 is not erased when using the spec-

ified bulk erase sequence in the “PIC16F91X Memory

Programming Specification” (DS41244) and thus, does

not require reprogramming.

The Programmable Low-Voltage Detect module is an

interrupt driven supply level detection. The voltage

detection monitors the internal power supply.

10.1 Voltage Trip Points

The PIC16F917/916/914/913 device supports eight

internal PLVD trip points. See Register 10-1 for avail-

able PLVD trip point voltages.

REGISTER 10-1: LVDCON – LOW-VOLTAGE DETECT CONTROL REGISTER (ADDRESS: 109h)

U-0

—

U-0

—

R-0

R/W-0

U-0

—

R/W-1

LVDL2

R/W-0

LVDL1

R/W-0

LVDL0

IRVST

LVDEN

bit 7

bit 0

bit 7-6

bit 5

Unimplemented: Read as ‘0’

IRVST: Internal Reference Voltage Stable Status Flag bit⁽¹⁾

1= Indicates that the PLVD is stable and PLVD interrupt is reliable

0= Indicates that the PLVD is not stable and PLVD interrupt should not be enabled

bit 4

LVDEN: Low-Voltage Detect Power Enable bit

1= Enables PLVD, powers up PLVD circuit and supporting reference circuitry

0= Disables PLVD, powers down PLVD and supporting circuitry

bit 3

Unimplemented: Read as ‘0’

bit 2-0

LVDL<2:0>: Low-Voltage Detection Limit bits (nominal values)

111= 4.5V

110= 4.2V

101= 4.0V

100= 2.3V (default)

011= 2.2V

010= 2.1V

001= 2.0V

000= 1.9V⁽²⁾

Note 1: The IRVST bit is usable only when the HFINTOSC is running. When using an

external crystal to run the microcontroller, the PLVD settling time is expected to be

<50 μs when VDD = 5V and <25 μs when VDD = 3V. Appropriate software delays

should be used after enabling the PLVD module to ensure proper status readings

of the module.

2: Not tested and below minimum VDD.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 125

PIC16F917/916/914/913

TABLE 10-1: REGISTERS ASSOCIATED WITH PROGRAMMABLE LOW-VOLTAGE DETECT

Value on

all other

Resets

Value on

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh/8Bh/ INTCON

10Bh/18Bh

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Dh

PIR2

0000 -0-0 0000 -0-0

OSFIF

OSFIE

—

C2IF

C2IE

—

C1IF

C1IE

LCDIF

LCDIE

—

LVDIF

LVDIE

—

CCP2IF

CCP2IE

8Dh

PIE2

109h

Legend:

LVDCON

IRVST LVDEN

LVDL2 LVDL1 LVDL0 --00 -100 --00 -100

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the PLVD module.

DS41250E-page 126

Preliminary

PIC16F917/916/914/913

The USART can be configured in the following modes:

11.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

• Asynchronous (full-duplex)

• Synchronous – Master (half-duplex)

• Synchronous – Slave (half-duplex)

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be

set in order to configure pins RC6/TX/CK/SCK/SCL/SEG9

and RC7/RX/DT/SDI/SDA/SEG8 as the Universal

Synchronous Asynchronous Receiver Transmitter.

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O modules. (USART is also known as a Serial

Communications Interface or SCI.) The USART can be

configured as a full-duplex asynchronous system that

can communicate with peripheral devices, such as

CRT terminals and personal computers, or it can be

configured as a half-duplex synchronous system that

can communicate with peripheral devices, such as A/D

or D/A integrated circuits, serial EEPROMs, etc.

The USART module also has a multi-processor

communication capability using 9-bit address detection.

REGISTER 11-1: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)

R/W-0

CSRC

R/W-0

TX9

R/W-0

TXEN

R/W-0

SYNC

U-0

—

R/W-0

BRGH

R-1

R/W-0

TX9D

TRMT

bit 7

bit 0

bit 7

CSRC: Clock Source Select bit

Asynchronous mode:

Don’t care

Synchronous mode:

1= Master mode (clock generated internally from BRG)

0= Slave mode (clock from external source)

bit 6

bit 5

TX9: 9-bit Transmit Enable bit

1= Selects 9-bit transmission

0= Selects 8-bit transmission

TXEN: Transmit Enable bit

1= Transmit enabled

0= Transmit disabled

Note:

SREN/CREN overrides TXEN in Sync mode.

bit 4

SYNC: USART Mode Select bit

1= Synchronous mode

0= Asynchronous mode

bit 3

bit 2

Unimplemented: Read as ‘0’

BRGH: High Baud Rate Select bit

Asynchronous mode:

1= High speed

0= Low speed

Synchronous mode:

Unused in this mode

bit 1

bit 0

TRMT: Transmit Shift Register Status bit

1= TSR empty

0= TSR full

TX9D: 9th bit of Transmit Data, can be Parity bit

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 127

PIC16F917/916/914/913

REGISTER 11-2: RCSTA – RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)

R/W-0

SPEN

R/W-0

RX9

R/W-0

SREN

R/W-0

CREN

R/W-0

R-0

R-x

ADDEN

FERR

OERR

RX9D

bit 7

bit 0

bit 7

SPEN⁽¹⁾: Serial Port Enable bit

1= Serial port enabled (configures RC7/RX/DT/SDI/SDA/SEG8 and

RC6/TX/CK/SCK/SCL/SEG9 pins as serial port pins)

0= Serial port disabled

bit 6

bit 5

RX9: 9-bit Receive Enable bit

1= Selects 9-bit reception

0= Selects 8-bit reception

SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode – Master:

1= Enables single receive

0= Disables single receive

This bit is cleared after reception is complete

Synchronous mode – Slave:

Don’t care.

bit 4

CREN: Continuous Receive Enable bit

Asynchronous mode:

1= Enables continuous receive

0= Disables continuous receive

Synchronous mode:

1= Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0= Disables continuous receive

bit 3

ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1= Enables address detection, enables interrupt and load of the receive buffer when RSR<8>

is set

0= Disables address detection, all bytes are received and ninth bit can be used as parity bit

bit 2

bit 1

bit 0

FERR: Framing Error bit

1= Framing error (can be updated by reading RCREG register and receive next valid byte)

0= No framing error

OERR: Overrun Error bit

1= Overrun error (can be cleared by clearing bit CREN)

0= No overrun error

RX9D: 9th bit of Received Data (can be parity bit but must be calculated by user firmware)

Note 1: CCP2CON used for PIC16F914/917 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 128

Preliminary

PIC16F917/916/914/913

It may be advantageous to use the high baud rate

(BRGH = 1) even for slower baud clocks. This is

because the FOSC/(16 (X + 1)) equation can reduce the

baud rate error in some cases.

11.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and

Synchronous modes of the USART. It is a dedicated

8-bit baud rate generator. The SPBRG register controls

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

the period of

a

free running 8-bit timer. In

Asynchronous mode, bit BRGH (TXSTA<2>) also

controls the baud rate. In Synchronous mode, bit

BRGH is ignored. Table 11-1 shows the formula for

computation of the baud rate for different USART

modes which only apply in Master mode (internal

clock).

11.1.1

SAMPLING

The data on the RC7/RX/DT/SDI/SDA/SEG8 pin is

sampled three times by a majority detect circuit to

determine if a high or a low level is present at the RX

pin.

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculated

using the formula in Table 11-1. From this, the error in

baud rate can be determined.

TABLE 11-1: BAUD RATE FORMULA

SYNC

BRGH = 0 (Low Speed)

BRGH = 1 (High Speed)

0

1

(Asynchronous) Baud Rate = FOSC/(64 (X + 1))

(Synchronous) Baud Rate = FOSC/(4 (X + 1))

Baud Rate = FOSC/(16 (X + 1))

N/A

Legend: X = value in SPBRG (0 to 255)

TABLE 11-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on

all other

Resets

Value on:

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

98h

18h

99h

TXSTA CSRC TX9 TXEN SYNC

—

BRGH TRMT TX9D 0000 -010 0000 -010

RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, ^-= unimplemented, read as ‘0’. Shaded cells are not used by the BRG.

Preliminary

DS41250E-page 129

PIC16F917/916/914/913

TABLE 11-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

FOSC = 20 MHz

FOSC = 16 MHz

FOSC = 10 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

%

value

KBAUD

ERROR

KBAUD

ERROR

KBAUD ERROR

(decimal)

0.3

1.2

—

255

129

31

15

9

—

207

103

25

12

8

—

129

64

15

7

1.221

1.75

0.17

1.73

1.72

8.51

3.34

8.51

—

1.202

0.17

0.16

3.55

6.29

8.51

—

1.202

0.17

1.73

1.72

8.51

6.99

9.58

—

2.4

2.404

9.6

9.766

9.615

9.766

19.2

28.8

33.6

57.6

HIGH

LOW

19.531

31.250

34.722

62.500

1.221

19.231

27.778

35.714

62.500

0.977

19.531

31.250

52.083

0.610

4

8

6

4

3

2

255

0

255

0

255

0

312.500

—

250.000

—

156.250

—

FOSC = 4 MHz

FOSC = 3.6864 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

(decimal)

%

ERROR

KBAUD

(decimal)

KBAUD

0.3

1.2

0.300

1.202

2.404

8.929

20.833

31.250

—

0

207

51

25

6

0.3

1.2

0

191

47

23

5

0.17

6.99

8.51

—

2.4

0

9.6

0

19.2

28.8

33.6

57.6

HIGH

LOW

2

19.2

28.8

—

0

2

1

0

1

—

0

—

0

—

0

62.500

0.244

62.500

8.51

—

57.6

0.225

57.6

255

0

—

255

0

—

TABLE 11-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

FOSC = 20 MHz

FOSC = 16 MHz

FOSC = 10 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

SPBRG

value

%

KBAUD

ERROR

KBAUD

ERROR

KBAUD

ERROR

(decimal)

0.3

1.2

—

2.4

—

2.441

9.615

19.531

28.409

32.895

56.818

2.441

625.000

1.71

0.16

1.72

1.36

2.10

1.36

-

255

64

31

21

18

10

255

0

9.6

9.615

19.231

29.070

33.784

59.524

4.883

1250.000

0.16

0.94

0.55

3.34

—

129

64

42

36

20

255

0

9.615

19.231

29.412

33.333

58.824

3.906

1000.000

0.16

2.13

0.79

2.13

—

103

51

33

29

16

255

0

19.2

28.8

33.6

57.6

HIGH

LOW

—

-

FOSC = 4 MHz

FOSC = 3.6864 MHz

BAUD

RATE

(K)

SPBRG

value

SPBRG

value

%

ERROR

KBAUD

(decimal) KBAUD

(decimal)

0.3

1.2

—

207

103

25

12

8

—

1.2

—

0

—

191

95

23

11

7

1.202

0.17

0.16

3.55

6.29

8.51

—

2.4

2.404

2.4

0

9.6

9.615

9.6

0

19.2

28.8

33.6

57.6

HIGH

LOW

19.231

27.798

35.714

62.500

0.977

19.2

28.8

32.9

57.6

0.9

0

6

2.04

0

6

3

255

0

—

255

0

250.000

—

230.4

DS41250E-page 130

Preliminary

PIC16F917/916/914/913

Transmission is enabled by setting enable bit, TXEN

(TXSTA<5>). The actual transmission will not occur until

the TXREG register has been loaded with data and the

Baud Rate Generator (BRG) has produced a shift clock

(Figure 11-2). The transmission can also be started by

first loading the TXREG register and then setting enable

bit TXEN. Normally, when transmission is first started, the

TSR register is empty. At that point, transfer to the

TXREG register will result in an immediate transfer to

TSR, resulting in an empty TXREG. A back-to-back

transfer is thus possible (Figure 11-3). Clearing enable bit

TXEN during a transmission will cause the transmission

to be aborted and will reset the transmitter. As a result, the

RC6/TX/CK/SCK/SCL/SEG9 pin will revert to

high-impedance.

11.2 USART Asynchronous Mode

In this mode, the USART uses standard

Non-Return-to-Zero (NRZ) format (one Start bit, eight

or nine data bits and one Stop bit). The most common

data format is 8 bits. An on-chip, dedicated, 8-bit Baud

Rate Generator can be used to derive standard baud

rate frequencies from the oscillator. The USART

transmits and receives the LSb first. The transmitter

and receiver are functionally independent but use the

same data format and baud rate. The baud rate

generator produces a clock, either x16 or x64 of the bit

shift rate, depending on bit BRGH (TXSTA<2>). Parity

is not supported by the hardware, but can be

implemented in software (and stored as the ninth data

bit). Asynchronous mode is stopped during Sleep.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG reg-

ister. This is because a data write to the TXREG regis-

ter can result in an immediate transfer of the data to the

TSR register (if the TSR is empty). In such a case, an

incorrect ninth data bit may be loaded in the TSR

register.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

When setting up an Asynchronous Transmission,

follow these steps:

11.2.1

USART ASYNCHRONOUS

TRANSMITTER

1. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH (Section 11.1 “USART Baud

Rate Generator (BRG)”).

The USART transmitter block diagram is shown in

Figure 11-1. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The shift register obtains

its data from the Read/Write Transmit Buffer, TXREG.

The TXREG register is loaded with data in software.

The TSR register is not loaded until the Stop bit has

been transmitted from the previous load. As soon as

the Stop bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG register is empty and

flag bit, TXIF (PIR1<4>), is set. This interrupt can be

enabled/disabled by setting/clearing enable bit, TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit, TRMT (TXSTA<1>),

shows the status of the TSR register. Status bit TRMT

is a read-only bit which is set when the TSR register is

empty. No interrupt logic is tied to this bit so the user

has to poll this bit in order to determine if the TSR

register is empty.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit TXIE.

4. If 9-bit transmission is desired, then set transmit

bit TX9.

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set. TXIF is cleared by loading TXREG.

Preliminary

DS41250E-page 131

PIC16F917/916/914/913

FIGURE 11-1:

USART TRANSMIT BLOCK DIAGRAM

Data Bus

TXIF

TXREG Register

8

TXIE

MSb

(8)

LSb

Pin Buffer

and Control

0

•

• •

TSR Register

RC6/TX/CK/SCK/

SCL/SEG9 pin

Interrupt

TXEN

Baud Rate CLK

SPBRG

TRMT

SPEN

TX9

TX9D

Baud Rate Generator

FIGURE 11-2:

ASYNCHRONOUS MASTER TRANSMISSION

Write to TXREG

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK/

SCK/SCL/SEG9

Start bit

bit 0

bit 1

Word 1

bit 7/8

Stop bit

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

Word 1

Transmit Shift Reg

TRMT bit

(Transmit Shift

Reg. Empty Flag)

FIGURE 11-3:

ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK)

Write to TXREG

Word 2

Start bit

Word 1

BRG Output

(Shift Clock)

RC6/TX/CK/

SCK/SCL/SEG9

Start bit

Word 2

bit 0

bit 1

Word 1

bit 7/8

bit 0

Stop bit

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1

Transmit Shift Reg.

Word 2

Transmit Shift Reg.

Note:

This timing diagram shows two consecutive transmissions.

DS41250E-page 132

Preliminary

PIC16F917/916/914/913

TABLE 11-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

19h

TXREG USART Transmit Data Register

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

0000 0000 0000 0000

99h

SPBRG Baud Rate Generator Register

Legend:

x= unknown, -= unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.

Preliminary

DS41250E-page 133

PIC16F917/916/914/913

When setting up an Asynchronous Reception, follow

these steps:

11.2.2

USART ASYNCHRONOUS

RECEIVER

1. Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH (Section 11.1 “USART Baud

Rate Generator (BRG)”).

The receiver block diagram is shown in Figure 11-4.

The data is received on the

RC7/RX/DT/SDI/SDA/SEG8 pin and drives the data

recovery block. The data recovery block is actually a

high-speed shifter, operating at x16 times the baud

rate; whereas the main receive serial shifter operates

at the bit rate or at FOSC.

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit

RCIE.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

The heart of the receiver is the Receive (Serial) Shift

Register (RSR). After sampling the Stop bit, the

received data in the RSR is transferred to the RCREG

register (if it is empty). If the transfer is complete, flag

bit, RCIF (PIR1<5>), is set. The actual interrupt can be

enabled/disabled by setting/clearing enable bit, RCIE

(PIE1<5>). Flag bit RCIF is a read-only bit which is

cleared by the hardware. It is cleared when the RCREG

register has been read and is empty. The RCREG is a

double-buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte to

begin shifting to the RSR register. On the detection of

the Stop bit of the third byte, if the RCREG register is

still full, the Overrun Error bit, OERR (RCSTA<1>), will

be set. The word in the RSR will be lost. The RCREG

register can be read twice to retrieve the two bytes in

the FIFO. Overrun bit OERR has to be cleared in soft-

ware. This is done by resetting the receive logic (CREN

is cleared and then set). If bit OERR is set, transfers

from the RSR register to the RCREG register are inhib-

ited and no further data will be received. It is, therefore,

essential to clear error bit OERR if it is set. Framing

error bit, FERR (RCSTA<2>), is set if a Stop bit is

detected as clear. Bit FERR and the 9th receive bit are

buffered the same way as the receive data. Reading

the RCREG will load bits RX9D and FERR with new

values, therefore, it is essential for the user to read the

RCSTA register before reading the RCREG register in

order not to lose the old FERR and RX9D information.

6. Flag bit RCIF will be set when reception is com-

plete and an interrupt will be generated if enable

bit RCIE is set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

DS41250E-page 134

Preliminary

PIC16F917/916/914/913

FIGURE 11-4:

USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

FERR

OERR

CREN

FOSC

SPBRG

÷64

RSR Register

MSb

Stop

LSb

Start

or

÷16

Baud Rate Generator

7

1

0

(8)

• • •

RC7/RX/DT/

SDI/SDA/SEG8

Pin Buffer

and Control

Data

Recovery

RX9

RX9D RCREG Register

SPEN

FIFO

8

RCIF

RCIE

Interrupt

Data Bus

FIGURE 11-5:

ASYNCHRONOUS RECEPTION

Start

bit

Start

bit

Start

bit

RX (pin)

bit 0 bit 1

Stop

bit

Stop

bit

bit 7/8 Stop

bit

bit 0

bit 7/8

Rcv Shift

Reg

Rcv Buffer Reg

Word 2

RCREG

Word 1

RCREG

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Note:

This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,

causing the OERR (Overrun Error) bit to be set.

TABLE 11-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

1Ah

RCREG USART Receive Data Register

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN

SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

0000 0000 0000 0000

99h

SPBRG Baud Rate Generator Register

Legend:

x= unknown, -= unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Preliminary

DS41250E-page 135

PIC16F917/916/914/913

• Flag bit RCIF will be set when reception is

complete, and an interrupt will be generated if

enable bit RCIE was set.

11.2.3

SETTING UP 9-BIT MODE WITH

ADDRESS DETECT

When setting up an Asynchronous Reception with

address detect enabled:

• Read the RCSTA register to get the ninth bit and

determine if any error occurred during reception.

• Initialize the SPBRG register for the appropriate

baud rate. If a high-speed baud rate is desired,

set bit BRGH.

• Read the 8-bit received data by reading the

RCREG register to determine if the device is

being addressed.

• Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• If any error occurred, clear the error by clearing

enable bit CREN.

• If interrupts are desired, then set enable bit RCIE.

• Set bit RX9 to enable 9-bit reception.

• If the device has been addressed, clear the

ADDEN bit to allow data bytes and address bytes

to be read into the receive buffer and interrupt the

CPU.

• Set ADDEN to enable address detect.

• Enable the reception by setting enable bit CREN.

FIGURE 11-6:

USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

FERR

OERR

CREN

FOSC

SPBRG

÷ 64

or

÷ 16

RSR Register

• • •

LSb

MSb

Stop (8)

7

1

0

Start

Baud Rate Generator

RC7/RX/DT

SDI/SDA/SEG8

Pin Buffer

and Control

Data

Recovery

RX9

8

SPEN

RX9

Enable

Load of

ADDEN

Receive

Buffer

RX9

ADDEN

RSR<8>

8

RX9D

RCREG Register

FIFO

8

RCIF

RCIE

Interrupt

Data Bus

DS41250E-page 136

Preliminary

PIC16F917/916/914/913

FIGURE 11-7:

ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT

Start

bit

Start

bit

RC7/RX/DT/

SDI/SDA/SEG8

bit 0 bit 1

Stop

bit

bit 8 Stop

bit

bit 0

bit 8

Load RSR

Read

Word 1

RCREG

bit 8 = 0, Data Byte

bit 8 = 1, Address Byte

RCIF

Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)

because ADDEN = 1.

FIGURE 11-8:

ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST

Start

bit

RC7/RX/DT/

SDI/SDA/SEG8

Start

bit

bit 0 bit 1

Stop

bit

bit 8 Stop

bit

bit 0

bit 8

Load RSR

Read

Word 1

RCREG

bit 8 = 1, Address Byte

bit 8 = 0, Data Byte

RCIF

Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer)

because ADDEN was not updated and still = 0.

TABLE 11-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 000x 0000 000x

1Ah

RCREG USART Receive Data Register

0000 0000 0000 0000

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN SYNC

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend:

x= unknown, -= unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Preliminary

DS41250E-page 137

PIC16F917/916/914/913

Clearing enable bit TXEN during a transmission will

cause the transmission to be aborted and will reset the

transmitter. The DT and CK pins will revert to

high-impedance. If either bit CREN or bit SREN is set

during a transmission, the transmission is aborted and

the DT pin reverts to a high-impedance state (for a

reception). The CK pin will remain an output if bit CSRC

is set (internal clock). The transmitter logic, however, is

not reset, although it is disconnected from the pins. In

order to reset the transmitter, the user has to clear bit

TXEN. If bit SREN is set (to interrupt an on-going trans-

mission and receive a single word), then after the sin-

gle word is received, bit SREN will be cleared and the

serial port will revert back to transmitting, since bit

TXEN is still set. The DT line will immediately switch

from High-Impedance Receive mode to transmit and

start driving. To avoid this, bit TXEN should be cleared.

11.3 USART Synchronous

Master Mode

In Synchronous Master mode, the data is transmitted in

a half-duplex manner (i.e., transmission and reception

do not occur at the same time). When transmitting data,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit, SYNC (TXSTA<4>). In

addition, enable bit, SPEN (RCSTA<7>), is set in order

to configure the RC6/TX/CK/SCK/SCL/SEG9 and

RC7/RX/DT/SDI/SDA/SEG8 I/O pins to CK (clock) and

DT (data) lines, respectively. The Master mode indi-

cates that the processor transmits the master clock on

the CK line. The Master mode is entered by setting bit,

CSRC (TXSTA<7>).

11.3.1

USART SYNCHRONOUS MASTER

TRANSMISSION

In order to select 9-bit transmission, the TX9

(TXSTA<6>) bit should be set and the ninth bit should

be written to bit TX9D (TXSTA<0>). The ninth bit must

be written before writing the 8-bit data to the TXREG

register. This is because a data write to the TXREG can

result in an immediate transfer of the data to the TSR

register (if the TSR is empty). If the TSR was empty and

the TXREG was written before writing the “new” TX9D,

the “present” value of bit TX9D is loaded.

The USART transmitter block diagram is shown in

Figure 11-6. The heart of the transmitter is the Transmit

(Serial) Shift Register (TSR). The shift register obtains

its data from the Read/Write Transmit Buffer register,

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXREG is empty and inter-

rupt bit, TXIF (PIR1<4>), is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicates the status

of the TXREG register, another bit, TRMT (TXSTA<1>),

shows the status of the TSR register. TRMT is a

read-only bit which is set when the TSR is empty. No

interrupt logic is tied to this bit so the user has to poll

this bit in order to determine if the TSR register is

empty. The TSR is not mapped in data memory so it is

not available to the user.

Steps to follow when setting up a Synchronous Master

Transmission:

1. Initialize the SPBRG register for the appropriate

baud rate (Section 11.1 “USART Baud Rate

Generator (BRG)”).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmission by loading data to the TXREG

register.

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

Transmission is enabled by setting enable bit, TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data.

The first data bit will be shifted out on the next available

rising edge of the clock on the CK line. Data out is

stable around the falling edge of the synchronous clock

(Figure 11-9). The transmission can also be started by

first loading the TXREG register and then setting bit

TXEN (Figure 11-10). This is advantageous when slow

baud rates are selected, since the BRG is kept in Reset

when bits TXEN, CREN and SREN are clear. Setting

enable bit TXEN will start the BRG, creating a shift

clock immediately. Normally, when transmission is first

started, the TSR register is empty, so a transfer to the

TXREG register will result in an immediate transfer to

TSR, resulting in an empty TXREG. Back-to-back

transfers are possible.

DS41250E-page 138

Preliminary

PIC16F917/916/914/913

TABLE 11-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 000x 0000 000x

19h

TXREG USART Transmit Data Register

0000 0000 0000 0000

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

0000 0000 0000 0000

99h

SPBRG Baud Rate Generator Register

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.

FIGURE 11-9:

SYNCHRONOUS TRANSMISSION

Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

RC7/RX/DT/

SDI/SDA/SEG8

bit 0

bit 1

Word 1

bit 2

bit 7

bit 0

bit 1

Word 2

bit 7

RC6/TX/CK/

SCK/SCL/SEG9

Write to

TXREG reg

Write Word 1

Write Word 2

TXIF bit

(Interrupt Flag)

TRMT bit

TXEN bit

‘1

’

‘1’

Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.

FIGURE 11-10:

SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT/SDI/SDA/SEG8

RC6/TX/CK/SCK/SCL/SEG9

bit 0

bit 2

bit 1

bit 6

bit 7

Write to

TXREG Reg

TXIF bit

TRMT bit

TXEN bit

Preliminary

DS41250E-page 139

PIC16F917/916/914/913

When setting up a Synchronous Master Reception:

11.3.2

USART SYNCHRONOUS MASTER

RECEPTION

1. Initialize the SPBRG register for the appropriate

baud rate (Section 11.1 “USART Baud Rate

Generator (BRG)”).

Once Synchronous mode is selected, reception is

enabled by setting either enable bit, SREN

(RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data

is sampled on the RC7/RX/DT/SDI/SDA/SEG8 pin on

the falling edge of the clock. If enable bit SREN is set,

then only a single word is received. If enable bit CREN

is set, the reception is continuous until CREN is

cleared. If both bits are set, CREN takes precedence.

After clocking the last bit, the received data in the

Receive Shift Register (RSR) is transferred to the

RCREG register (if it is empty). When the transfer is

complete, interrupt flag bit, RCIF (PIR1<5>), is set. The

actual interrupt can be enabled/disabled by set-

ting/clearing enable bit, RCIE (PIE1<5>). Flag bit RCIF

is a read-only bit which is reset by the hardware. In this

case, it is reset when the RCREG register has been

read and is empty. The RCREG is a double-buffered

register (i.e., it is a two-deep FIFO). It is possible for two

bytes of data to be received and transferred to the

RCREG FIFO and a third byte to begin shifting into the

RSR register. On the clocking of the last bit of the third

byte, if the RCREG register is still full, then Overrun

Error bit, OERR (RCSTA<1>), is set. The word in the

RSR will be lost. The RCREG register can be read

twice to retrieve the two bytes in the FIFO. Bit OERR

has to be cleared in software (by clearing bit CREN). If

bit OERR is set, transfers from the RSR to the RCREG

are inhibited so it is essential to clear bit OERR if it is

set. The ninth receive bit is buffered the same way as

the receive data. Reading the RCREG register will load

bit RX9D with a new value, therefore, it is essential for

the user to read the RCSTA register before reading

RCREG in order not to lose the old RX9D information.

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, then set enable bit

RCIE.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

7. Interrupt flag bit RCIF will be set when reception

is complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 11-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D

0000 000x 0000 000x

0000 0000 0000 0000

1Ah

RCREG USART Receive Data Register

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN SYNC

—

BRGH

TRMT

TX9D

0000 -010 0000 -010

0000 0000 0000 0000

99h

SPBRG Baud Rate Generator Register

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.

DS41250E-page 140

Preliminary

PIC16F917/916/914/913

FIGURE 11-11:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4

RC7/RX/DT/

SDI/SDA/SEG8

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

RC6/TX/CK/

SCK/SCL/SEG9

Write to

bit SREN

SREN bit

‘0’

CREN bit

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1and bit BRG = 0.

When setting up a Synchronous Slave Transmission,

follow these steps:

11.4 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/CK/SCK/SCL/SEG9 pin (instead of being

supplied internally in Master mode). This allows the

device to transfer or receive data while in Sleep mode.

Slave mode is entered by clearing bit, CSRC

(TXSTA<7>).

1. Enable the synchronous slave serial port by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmission is desired, then set bit TX9.

11.4.1

USART SYNCHRONOUS SLAVE

TRANSMIT

5. Enable the transmission by setting enable bit

TXEN.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep mode.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

If two words are written to the TXREG and then the

SLEEPinstruction is executed, the following will occur:

7. Start transmission by loading data to the TXREG

register.

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register.

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit TXIF will now be set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from Sleep and if the global interrupt is

enabled, the program will branch to the interrupt

vector (0004h).

Preliminary

DS41250E-page 141

PIC16F917/916/914/913

TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 000x 0000 000x

19h

TXREG USART Transmit Data Register

0000 0000 0000 0000

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN SYNC

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.

When setting up a Synchronous Slave Reception,

follow these steps:

11.4.2

USART SYNCHRONOUS SLAVE

RECEPTION

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the Sleep

mode. Bit SREN is a “don't care” in Slave mode.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

If receive is enabled by setting bit CREN prior to the

SLEEPinstruction, then a word may be received during

Sleep. On completely receiving the word, the RSR

register will transfer the data to the RCREG register

and if enable bit RCIE bit is set, the interrupt generated

will wake the chip from Sleep. If the global interrupt is

enabled, the program will branch to the interrupt vector

(0004h).

5. Flag bit RCIF will be set when reception is

complete and an interrupt will be generated if

enable bit RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on

all other

Resets

Value on:

POR, BOR

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

ADIF

RX9

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

18h

RCSTA

SPEN

SREN CREN ADDEN FERR

OERR

RX9D 0000 000x 0000 000x

1Ah

RCREG USART Receive Data Register

0000 0000 0000 0000

8Ch

PIE1

EEIE

ADIE

TX9

RCIE

TXIE

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

98h

TXSTA

CSRC

TXEN SYNC

—

BRGH

TRMT

TX9D 0000 -010 0000 -010

99h

SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend:

x= unknown, -= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

DS41250E-page 142

Preliminary

PIC16F917/916/914/913

12.0 ANALOG-TO-DIGITAL

CONVERTER (A/D) MODULE

The Analog-to-Digital converter (A/D) allows conversion

of an analog input signal to a 10-bit binary representation

of that signal. The PIC16F917/916/914/913 has up to

eight analog inputs, multiplexed into one sample and hold

circuit. The output of the sample and hold is connected to

the input of the converter. The converter generates a

binary result via successive approximation and stores the

result in a 10-bit register. The voltage reference used in

the conversion is software selectable to either VDD or a

voltage applied by the VREF pin. Figure 12-1 shows the

block diagram of the A/D on the PIC16F917/916/914/913.

FIGURE 12-1:

A/D BLOCK DIAGRAM

VDD

VCFG0 = 0

VREF+

VCFG0 = 1

RA0/AN0/C1-/SEG12

RA1/AN1/C2-/SEG7

A/D

RA2/AN2/C2+/VREF-/COM2

RA3/AN3/C1+/VREF+/COM3⁽²⁾/SEG15

RA5/AN4/C2OUT/SS/SEG5

10

GO/DONE

ADFM

RE0/AN5/SEG21⁽¹⁾

RE1/AN6/SEG22⁽¹⁾

RE2/AN7/SEG23⁽¹⁾

ADON

VSS

ADRESH ADRESL

VCFG1 = 0

VCFG1 = 1

CHS<2:0>

VREF-

Note 1: These channels are only available on PIC16F914/917 devices.

2: COM3 available on RA3 only on PIC16F913/916 devices.

Preliminary

DS41250E-page 143

PIC16F917/916/914/913

12.1.4

CONVERSION CLOCK

12.1 A/D Configuration and Operation

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the

ADCS bits (ADCON1<6:4>). There are seven possible

clock options:

There are three registers available to control the

functionality of the A/D module:

1. ANSEL (Register 12-1)

2. ADCON0 (Register 12-2)

3. ADCON1 (Register 12-3)

• FOSC/2

• FOSC/4

• FOSC/8

12.1.1

ANALOG PORT PINS

• FOSC/16

The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits

control the operation of the A/D port pins. Set the

corresponding TRIS bits to set the pin output driver to

its high-impedance state. Likewise, set the correspond-

ing ANSEL bit to disable the digital input buffer.

• FOSC/32

• FOSC/64

• FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of

1.6 μs. Table 12-1 shows a few TAD calculations for

selected frequencies.

Note:

Analog voltages on any pin that is defined

as a digital input may cause the input

buffer to conduct excess current.

12.1.2

CHANNEL SELECTION

There are up to eight analog channels on the

PIC16F917/916/914/913, AN<7:0>. The CHS<2:0> bits

(ADCON0<4:2>) control which channel is connected to

the sample and hold circuit.

12.1.3

VOLTAGE REFERENCE

There are two options for each reference to the A/D

converter, VREF+ and VREF-. VREF+ can be connected to

either VDD or an externally applied voltage. Alternatively,

VREF- can be connected to either VSS or an externally

applied voltage. VCFG<1:0> bits are used to select the

reference source.

TABLE 12-1: TAD vs. DEVICE OPERATING FREQUENCIES

Device Frequency

A/D Clock Source (TAD)

Operation

ADCS<2:0>

000

20 MHz

100 ns⁽²⁾

200 ns⁽²⁾

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

5 MHz

400 ns⁽²⁾

800 ns⁽²⁾

1.6 μs

4 MHz

500 ns⁽²⁾

1.0 μs⁽²⁾

2.0 μs

1.25 MHz

1.6 μs

2 TOSC

4 TOSC

100

3.2 μs

6.4 μs

12.8 μs⁽³⁾

25.6 μs⁽³⁾

51.2 μs⁽³⁾

2-6 μs^(1,4)

8 TOSC

001

16 TOSC

32 TOSC

64 TOSC

A/D RC

101

3.2 μs

4.0 μs

010

6.4 μs

8.0 μs⁽³⁾

16.0 μs⁽³⁾

2-6 μs^(1,4)

110

3.2 μs

2-6 μs^(1,4)

12.8 μs⁽³⁾

2-6 μs^(1,4)

x11

Legend: Shaded cells are outside of recommended range.

Note 1: The A/D RC source has a typical TAD time of 4 μs for VDD > 3.0V.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the

conversion will be performed during Sleep.

DS41250E-page 144

Preliminary

PIC16F917/916/914/913

12.1.5

STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bit (ADCON0<1>). When the conversion is

complete, the A/D module:

• Clears the GO/DONE bit

• Sets the ADIF flag (PIR1<6>)

• Generates an interrupt (if enabled)

If the conversion must be aborted, the GO/DONE bit

can be cleared in software. The ADRESH:ADRESL

registers will not be updated with the partially complete

A/D

conversion

sample.

Instead,

the

ADRESH:ADRESL registers will retain the value of the

previous conversion. After an aborted conversion, a

2 TAD delay is required before another acquisition can

be initiated. Following the delay, an input acquisition is

automatically started on the selected channel.

Note:

The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

FIGURE 12-2:

A/D CONVERSION TAD CYCLES

TCY TO TAD

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11

b9

Conversion Starts

Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

b8

b7

b6

b5

b4

b3

b2

b1

b0

Set GO/DONE bit

ADRESH and ADRESL registers are loaded,

GO/DONE bit is cleared,

ADIF bit is set,

Holding Capacitor is Connected to Analog Input

12.1.6

CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right shifted. The ADFM bit (ADCON0<7>) controls

the output format. Figure 12-3 shows the output

formats.

FIGURE 12-3:

10-BIT A/D RESULT FORMAT

ADRESH

ADRESL

LSB

(ADFM = 0) MSB

bit 7

bit 0

bit 7

bit 0

10-bit A/D Result

MSB

Unimplemented: Read as ‘0’

(ADFM = 1)

LSB

bit 7

bit 0

Unimplemented: Read as ‘0’

10-bit A/D Result

Preliminary

DS41250E-page 145

PIC16F917/916/914/913

REGISTER 12-1: ANSEL – ANALOG SELECT REGISTER (ADDRESS: 91h)

R/W-1

ANS7⁽²⁾

bit 7

R/W-1

ANS6⁽²⁾

R/W-1

ANS5⁽²⁾

R/W-1

ANS4

R/W-1

ANS3

R/W-1

ANS2

R/W-1

ANS1

R/W-1

ANS0

bit 0

bit 7-0:

ANS<7:0>: Analog Select bits⁽²⁾

Select between analog or digital function on pins AN<7:0>, respectively.

1= Analog input. Pin is assigned as analog input.⁽¹⁾

0= Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,

weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit

must be set to Input mode in order to allow external control of the voltage on the pin.

2: ANS<7:5> on PIC16F914/917 only; forced ‘0’ on PIC16F913/916.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 12-2: ADCON0 – A/D CONTROL REGISTER (ADDRESS: 1Fh)

R/W-0

ADFM

R/W-0

CHS2

R/W-0

CHS1

R/W-0

CHS0

R/W-0

ADON

VCFG1

VCFG0

GO/DONE

bit 7

bit 0

bit 7

ADFM: A/D Result Formed Select bit

1= Right justified

0= Left justified

bit 6

VCFG1: Voltage Reference bit

1= VREF- pin

0= VSS

bit 5

VCFG0: Voltage Reference bit

1= VREF+ pin

0= VDD

bit 4-2

CHS<2:0>: Analog Channel Select bits

000= Channel 00 (AN0)

001= Channel 01 (AN1)

010= Channel 02 (AN2)

011= Channel 03 (AN3)

100= Channel 04 (AN4)

101= Channel 05 (AN5)

110= Channel 06 (AN6)

111= Channel 07 (AN7)

bit 1

bit 0

GO/DONE: A/D Conversion Status bit

1= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0= A/D conversion completed/not in progress

ADON: A/D Conversion Status bit

1= A/D converter module is operating

0= A/D converter is shut off and consumes no operating current

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 146

Preliminary

PIC16F917/916/914/913

REGISTER 12-3: ADCON1 – A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

ADCS2

ADCS1

ADCS0

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000= FOSC/2

001= FOSC/8

010= FOSC/32

x11= FRC (clock derived from a dedicated internal oscillator = 500 kHz max)

100= FOSC/4

101= FOSC/16

110= FOSC/64

bit 3-0

Unimplemented: Read as ‘0’

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 147

PIC16F917/916/914/913

12.1.7

CONFIGURING THE A/D

EXAMPLE 12-1:

A/D CONVERSION

;This code block configures the A/D

;for polling, Vdd reference, R/C clock

;and RA0 input.

;

After the A/D module has been configured as desired,

the selected channel must be acquired before the

conversion is started. The analog input channels must

have their corresponding TRIS bits selected as inputs.

;Conversion start and wait for complete

;polling code included.

;

To determine sample time, see Section 19.0 “Electrical

Specifications”. After this sample time has elapsed, the

A/D conversion can be started.

BSF

STATUS,RP0

;Bank 1

MOVLW B’01110000’

MOVWF ADCON1

;A/D RC clock

These steps should be followed for an A/D conversion:

BSF

BCF

TRISA,0

ANSEL,0

STATUS,RP0

;Set RA0 to input

;Set RA0 to analog

;Bank 0

1. Configure the A/D module:

• Configure analog/digital I/O (ANSEL)

• Configure voltage reference (ADCON0)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON1)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit (PIR1<6>)

MOVLW B’10000001’

MOVWF ADCON0

CALL

BSF

BTFSC ADCON0,GO

GOTO

MOVF

MOVWF RESULTHI

BSF

MOVF

MOVWF RESULTLO

;Right, Vdd Vref, AN0

SampleTime

ADCON0,GO

;Wait min sample time

;Start conversion

;Is conversion done?

;No, test again

$-1

ADRESH,W

;Read upper 2 bits

• Set ADIE bit (PIE1<6>)

STATUS,RP0

ADRESL,W

;Bank 1

;Read lower 8 bits

• Set PEIE and GIE bits (INTCON<7:6>)

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0<1>)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(with interrupts disabled); OR

• Waiting for the A/D interrupt

6. Read A/D Result register pair

(ADRESH:ADRESL); clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as

required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

DS41250E-page 148

Preliminary

PIC16F917/916/914/913

As the impedance is decreased, the acquisition time

may be decreased. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

12.2 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 12-4. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance varies over the device voltage

(VDD), see Figure 12-4. The maximum recom-

mended impedance for analog sources is 10 kΩ.

To calculate the minimum acquisition time,

Equation 12-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 steps for the A/D). The

1/2 LSb error is the maximum error allowed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the “PICmicro^®Mid-Range MCU Family Reference

Manual” (DS33023).

EQUATION 12-1: ACQUISITION TIME

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

= TAMP + TC + TCOFF

= 2µs + TC + [(Temperature - 25°C)(0.05µs/°C)]

Where CHOLD is charged to within 1/2 lsb:

1

⎛

⎞

⎠

-----------

2047

;[1] VCHOLD charged to within 1/2 lsb

VAPPLIED 1 –

= VCHOLD

⎝

–TC

---------

⎛

⎞

VAPPLIED 1 – e ^RC= VCHOLD

;[2] VCHOLD charge response to VAPPLIED

⎜

⎝

⎟

⎠

–Tc

--------

⎛

⎞

1

2047

VAPPLIED 1 – e^RC= V^APPLIED1 –

⎛

⎞

⎠

;combining [1] and [2]

-----------

⎜

⎝

⎟

⎠

⎝

Solving for TC:

TC = –CHOLD(RIC + RSS + RS) ln(1/2047)

= –10pF(1kΩ + 7kΩ + 10kΩ) ln(0.0004885)

= 1.37µs

Therefore:

TACQ = 2µS + 1.37µS + [(50°C- 25°C)(0.05µS/°C)]

= 4.67µS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

Preliminary

DS41250E-page 149

PIC16F917/916/914/913

FIGURE 12-4:

ANALOG INPUT MODEL

VDD

Sampling

Switch

VT = 0.6V

ANx

SS

RIC ≤ 1k

RSS

RS

CHOLD

= DAC capacitance

= 10 pF

CPIN

5 pF

VA

I LEAKAGE

± 500 nA

VT = 0.6V

VSS

6V

5V

RSS

VDD 4V

3V

Legend: CPIN

= Input Capacitance

= Threshold Voltage

VT

2V

I LEAKAGE = Leakage current at the pin due to

various junctions

RIC

SS

CHOLD

= Interconnect Resistance

= Sampling Switch

= Sample/Hold Capacitance (from DAC)

5 6 7 8 9 1011

Sampling Switch

(kΩ)

interrupt is enabled, the device awakens from Sleep. If

the GIE bit (INTCON<7>) is set, the program counter is

set to the interrupt vector (0004h). If GIE is clear, the

next instruction is executed. If the A/D interrupt is not

enabled, the A/D module is turned off, although the

ADON bit remains set.

12.3 A/D Operation During Sleep

The A/D converter module can operate during Sleep.

This requires the A/D clock source to be set to the

internal oscillator. When the RC clock source is

selected, the A/D waits one instruction before starting

the conversion. This allows the SLEEPinstruction to be

executed, thus eliminating much of the switching noise

from the conversion. When the conversion is complete,

the GO/DONE bit is cleared and the result is loaded

into the ADRESH:ADRESL registers. If the A/D

When the A/D clock source is something other than

RC, a SLEEPinstruction causes the present conversion

to be aborted, and the A/D module is turned off. The

ADON bit remains set.

FIGURE 12-5:

A/D TRANSFER FUNCTION

Full-Scale Range

1 LSB Ideal

3FFh

3FEh

3FDh

3FCh

3FBh

1/2 LSB Ideal

004h

003h

002h

001h

000h

Full-Scale

Transition

Center of

Full-Scale Code

Analog Input

1/2 LSB Ideal

Zero-Scale

Transition

Zero-Scale

DS41250E-page 150

Preliminary

PIC16F917/916/914/913

12.4 Effects of Reset

A device Reset forces all registers to their Reset state.

Thus, the A/D module is turned off and any pending

conversion is aborted. The ADRESH:ADRESL

registers are unchanged.

TABLE 12-2: SUMMARY OF A/D REGISTERS

Value on

Value on:

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

all other

Resets

05h

PORTA

PORTE

RA7

—

RA6

—

RA5

—

RA4

—

RA3

RE3

RA2

RE2

RA1

RE1

RA0

RE0

xxxx xxxx uuuu uuuu

---- xxxx ---- uuuu

09h

0Bh/

8Bh

INTCON

GIE

PEIE

ADIF

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

1Eh

1Fh

85h

89h

8Ch

91h

9Eh

9Fh

PIR1

EEIF

RCIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0000 0000 0000 0000

xxxx xxxx uuuu uuuu

0000 0000 0000 0000

1111 1111 1111 1111

---- 1111 ---- 1111

0000 0000 0000 0000

1111 1111 1111 1111

xxxx xxxx uuuu uuuu

-000 ---- -000 ----

ADRESH

ADCON0

TRISA

Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result

ADFM

TRISA7

—

VCFG1

TRISA6

—

VCFG0

TRISA5

—

CHS2

TRISA4

—

CHS1

TRISA3

TRISE3

SSPIE

ANS3

CHS0

TRISA2

TRISE2

CCP1IE

ANS2

GO/DONE

TRISA1

TRISE1

TMR2IE

ANS1

ADON

TRISA0

TRISE0

TMR1IE

ANS0

TRISE

PIE1

EEIE

ADIE

RCIE

ANS5

TXIE

ANSEL

ADRESL

ADCON1

ANS7

ANS6

ANS4

Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result

ADCS2 ADCS1 ADCS0

—

Legend: x= unknown, u= unchanged, -= unimplemented read as ‘0’. Shaded cells are not used for A/D module.

Preliminary

DS41250E-page 151

PIC16F917/916/914/913

NOTES:

DS41250E-page 152

Preliminary

PIC16F917/916/914/913

13.1 EEADRL and EEADRH Registers

13.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The EEADRL and EEADRH registers can address up

to a maximum of 256 bytes of data EEPROM or up to a

maximum of 8k words of program EEPROM.

Data EEPROM memory is readable and writable and

the Flash program memory is readable during normal

operation (full VDD range). These memories are not

directly mapped in the register file space. Instead, they

are indirectly addressed through the Special Function

Registers. There are six SFRs used to access these

memories:

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is written to the EEADRL register. When selecting

a data address value, only the LSB of the address is

written to the EEADRL register.

13.1.1

EECON1 AND EECON2 REGISTERS

• EECON1

• EECON2

• EEDATL

• EEDATH

• EEADRL

• EEADRH

EECON1 is the control register for EE memory

accesses.

Control bit EEPGD determines if the access will be a

program or data memory access. When clear, as it is

when reset, any subsequent operations will operate on

the data memory. When set, any subsequent operations

will operate on the program memory. Program memory

can only be read.

When interfacing the data memory block, EEDATL

holds the 8-bit data for read/write, and EEADRL holds

the address of the EE data location being accessed.

This device has 256 bytes of data EEPROM with an

address range from 0h to 0FFh.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

When interfacing the program memory block, the

EEDATL and EEDATH registers form a 2-byte word

that holds the 14-bit data for read, and the EEADRL

and EEADRH registers form a 2-byte word that holds

the 13-bit address of the EEPROM location being

accessed. This device has 4k and 8k words of program

EEPROM with an address range from 0h-0FFFh and

0h-1FFFh. The program memory allows one word

reads.

The WREN bit, when set, will allow a write operation to

data EEPROM. On power-up, the WREN bit is clear.

The WRERR bit is set when a write operation is

interrupted by a MCLR or a WDT Time-out Reset

during normal operation. In these situations, following

Reset, the user can check the WRERR bit and rewrite

the location. The data and address will be unchanged

in the EEDATL and EEADRL registers.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).

Interrupt flag bit EEIF (PIR1<7>), is set when write is

complete. It must be cleared in the software.

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

When the device is code-protected, the CPU may

continue to read and write the data EEPROM memory

and read the program memory. When code-protected,

the device programmer can no longer access data or

program memory.

Additional information on the data EEPROM is

available in the “PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023).

Preliminary

DS41250E-page 153

PIC16F917/916/914/913

REGISTER 13-1: EEDATL – EEPROM DATA LOW BYTE REGISTER (ADDRESS: 10Ch)

R/W-0

EEDATL7

bit 7

R/W-0

EEDATL6 EEDATL5 EEDATL4

EEDATL3

EEDATL2 EEDATL1 EEDATL0

bit 0

bit 7-0

EEDATL<7:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 13-2:

EEADRL – EEPROM ADDRESS LOW BYTE REGISTER (ADDRESS: 10Dh)

R/W-0

EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0

bit 7 bit 0

R/W-0

bit 7-0

EEADRL<7:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or low byte for

program memory reads

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 13-3: EEDATH – EEPROM DATA HIGH BYTE REGISTER (ADDRESS: 10Eh)

U-0

R/W-0

—

EEDATH5 EEDATH4

EEDATH3

EEDATH2 EEDATH1 EEDATH0

bit 0

bit 7

bit 5-0

EEDATH<5:0>: Byte value to Write to or Read from data EEPROM bits or to Read from program memory

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

REGISTER 13-4:

EEADRH– EEPROMADDRESSHIGH BYTEREGISTER(ADDRESS:10Fh)

U-0

—

U-0

—

U-0

—

R/W-0

EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

bit 0

bit 7

bit 4-0

EEADRH<4:0>: Specifies one of 256 locations for EEPROM Read/Write operation bits or high bits for

program memory reads

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 154

Preliminary

PIC16F917/916/914/913

REGISTER 13-5: EECON1 – EEPROM CONTROL REGISTER 1 (ADDRESS: 18Ch)

R/W-0

U-0

—

U-0

—

U-0

—

R/W-x

R/W-0

WREN

R/S-0

WR

R/S-0

RD

EEPGD

WRERR

bit 7

bit 0

bit 7

EEPGD: Program/Data EEPROM Select bit

1= Accesses program memory

0= Accesses data memory

bit 6-4

bit 3

Unimplemented: Read as ‘0’

WRERR: EEPROM Error Flag bit

1= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during

normal operation or BOR Reset)

0= The write operation completed

bit 2

bit 1

WREN: EEPROM Write Enable bit

1= Allows write cycles

0= Inhibits write to the data EEPROM

WR: Write Control bit

EEPGD = 1:

This bit is ignored

EEPGD = 0:

1= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only be

set, not cleared, in software.)

0= Write cycle to the data EEPROM is complete

bit 0

RD: Read Control bit

1= Initiates a memory read (RD is cleared in hardware. The RD bit can only be set, not cleared, in

software.)

0= Does not initiate an memory read

Legend:

S = Bit can only be set

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 155

PIC16F917/916/914/913

The steps to write to EEPROM data memory are:

13.1.2

READING THE DATA EEPROM

MEMORY

1. If step 10 is not implemented, check the WR bit

to see if a write is in progress.

To read a data memory location, the user must write the

address to the EEADRL register, clear the EEPGD

control bit (EECON1<7>), and then set control bit RD

(EECON1<0>). The data is available in the very next

cycle, in the EEDATL register; therefore, it can be read

in the next instruction. EEDATL will hold this value until

another read or until it is written to by the user (during

a write operation).

2. Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the device.

3. Write the 8-bit data value to be programmed in

the EEDATA register.

4. Clear the EEPGD bit to point to EEPROM data

memory.

5. Set the WREN bit to enable program operations.

6. Disable interrupts (if enabled).

EXAMPLE 13-1:

DATA EEPROM READ

BSF

STATUS,RP1

STATUS,RP0

;

7. Execute the special five instruction sequence:

BCF

; Bank 2

• Write 55h to EECON2 in two steps (first to W,

then to EECON2)

MOVF

MOVWF

BSF

DATA_EE_ADDR,W ; Data Memory

EEADR

STATUS,RP0

EECON1,EEPGD

; Address to read

; Bank 3

; Point to Data

; memory

• Write AAh to EECON2 in two steps (first to

W, then to EECON2)

BCF

• Set the WR bit

BSF

BCF

MOVF

EECON1,RD

STATUS,RP0

EEDATA,W

; EE Read

; Bank 2

; W = EEDATA

8. Enable interrupts (if using interrupts).

9. Clear the WREN bit to disable program

operations.

13.1.3

WRITING TO THE DATA EEPROM

MEMORY

10. At the completion of the write cycle, the WR bit

is cleared and the EEIF interrupt flag bit is set.

(EEIF must be cleared by firmware.) If step 1 is

not implemented, then firmware should check

for EEIF to be set, or WR to clear, to indicate the

end of the program cycle.

To write an EEPROM data location, the user must first

write the address to the EEADRL register and the data

to the EEDATL register. Then the user must follow a

specific sequence to initiate the write for each byte.

The write will not initiate if the sequence described below

is not followed exactly (write 55h to EECON2, write AAh

to EECON2, then set WR bit) for each byte. Interrupts

should be disabled during this code segment.

EXAMPLE 13-2:

DATA EEPROM WRITE

BSF

STATUS,RP1

STATUS,RP0

;

BTFSC EECON1,WR

;Wait for write

;to complete

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

GOTO

BCF

$-1

STATUS,RP0 ;Bank 2

MOVF

DATA_EE_ADDR,W;Data Memory

MOVWF EEADR

MOVF DATA_EE_DATA,W;Data Memory Value

MOVWF EEDATA ;to write

;Address to write

BSF

BCF

STATUS,RP0 ;Bank 3

EECON1,EEPGD;Point to DATA

;memory

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

BSF

EECON1,WREN ;Enable writes

BCF

MOVLW 55h

MOVWF EECON2

MOVLW AAh

MOVWF EECON2

INTCON,GIE ;Disable INTs.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

;

;Write 55h

;

;Write AAh

BSF

EECON1,WR

;Set WR bit to

;begin write

BSF

BCF

INTCON,GIE ;Enable INTs.

EECON1,WREN ;Disable writes

DS41250E-page 156

Preliminary

PIC16F917/916/914/913

13.1.4

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must

write two bytes of the address to the EEADRL and

EEADRH registers, set the EEPGD control bit

(EECON1<7>), and then set control bit RD

(EECON1<0>). Once the read control bit is set, the

program memory Flash controller will use the second

instruction cycle to read the data. This causes the

second instruction immediately following the

“BSF EECON1,RD” instruction to be ignored. The data

is available in the very next cycle, in the EEDATL and

EEDATH registers; therefore, it can be read as two

bytes in the following instructions. EEDATL and

EEDATH registers will hold this value until another read

or until it is written to by the user (during a write

operation).

Note 1: The two instructions following a program

memory read are required to be NOP’s.

This prevents the user from executing a

two-cycle instruction on the next

instruction after the RD bit is set.

2: If the WR bit is set when EEPGD = 1, it

will be immediately reset to ‘0’ and no

operation will take place.

EXAMPLE 13-3:

FLASH PROGRAM READ

BSF

BCF

STATUS, RP1

STATUS, RP0

;

; Bank 2

MOVLW

MOVWF

MOVLW

MOVWF

BSF

MS_PROG_EE_ADDR;

EEADRH

; MS Byte of Program Address to read

LS_PROG_EE_ADDR;

EEADR

STATUS, RP0

; LS Byte of Program Address to read

; Bank 3

BSF

EECON1, EEPGD ; Point to PROGRAM memory

BSF

EECON1, RD

; EE Read

;

NOP

; Any instructions here are ignored as program

; memory is read in second cycle after BSF EECON1,RD

;

BCF

STATUS, RP0

EEDATA, W

DATAL

EEDATH, W

DATAH

; Bank 2

; W = LS Byte of Program EEDATA

;

; W = MS Byte of Program EEDATA

;

MOVF

MOVWF

MOVF

MOVWF

Preliminary

DS41250E-page 157

PIC16F917/916/914/913

FIGURE 13-1:

FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC

PC + 1

EEADRH,EEADRL

P C + 3

PC+3

PC + 4

PC + 5

Flash ADDR

Flash Data

INSTR (PC)

INSTR (PC + 1)

EEDATH,EEDATL

INSTR (PC + 3)

INSTR (PC + 4)

BSF EECON1,RD

executed here

INSTR(PC - 1)

executed here

INSTR(PC + 1)

executed here

Forced NOP

executed here

INSTR(PC + 3)

executed here

INSTR(PC + 4)

executed here

RD bit

EEDATH

EEDATL

register

EERHLT

TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

Value on

all other

Resets

Value on

POR, BOR

Addr

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh/8Bh/ INTCON

10Bh

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

PIR1

EEIF

EEIE

ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

0000 0000 0000 0000

8Ch

PIE1

TMR1IE 0000 0000 0000 0000

10Ch

10Dh

EEDATL

EEADRL

EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 0000 0000

EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 0000 0000

EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0

10Eh

EEDATH

EEADRH

EECON1

EECON2

—

--00 0000 --00 0000

---0 0000 ---0 0000

0--- x000 ---- q000

---- ---- --------

EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0

WRERR WREN WR RD

10Fh

—

18Ch

EEPGD

—

18Dh

EEPROM Control Register 2 (not a physical register)

Legend:

x= unknown, u= unchanged, -= unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by data EEPROM module.

DS41250E-page 158

Preliminary

PIC16F917/916/914/913

14.0 SSP MODULE OVERVIEW

The Synchronous Serial Port (SSP) module is a serial

interface used to communicate with other peripheral or

microcontroller devices. These peripheral devices may

be serial EEPROMs, shift registers, display drivers,

A/D converters, etc. The SSP module can operate in

one of two modes:

• Serial Peripheral Interface (SPI™)

• Inter-Integrated Circuit (I²C™)

An overview of I²C operations and additional information

on the SSP module can be found in the “PICmicro^®

Mid-Range MCU Family Reference Manual” (DS33023).

Refer to Application Note AN578, “Use of the SSP

Module in the Multi-Master Environment” (DS00578).

14.1 SPI Mode

This section contains register definitions and operational

characteristics of the SPI module. Additional information

on the SPI module can be found in the “PICmicro^®

Mid-Range MCU Family Reference Manual” (DS33023).

The SPI mode allows 8 bits of data to be synchronously

transmitted and received simultaneously. To accomplish

communication, typically three pins are used:

• Serial Data Out (SDO) – RC4/T1G/SDO/SEG11

• Serial Data In (SDI) – RC7/RX/DT/SDI/SDA/SEG8

• Serial Clock (SCK) – RC6/TX/CK/SCK/SCL/SEG9

Additionally, a fourth pin may be used when in a Slave

mode of operation:

• Slave Select (SS) – RA5/AN4/C2OUT/SS/SEG5

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>)

and SSPSTAT<7:6>. These control bits allow the

following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

Preliminary

DS41250E-page 159

PIC16F917/916/914/913

REGISTER 14-1: SSPSTAT – SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)

R/W-0

SMP

R/W-0

CKE

R-0

D/A

R-0

P

R-0

S

R-0

UA

R-0

BF

R/W

bit 7

bit 0

bit 7

SMP: SPI™ Data Input Sample Phase bit

SPI Master mode:

1= Input data sampled at end of data output time

0= Input data sampled at middle of data output time (Microwire)

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

I²C™ mode:

This bit must be maintained clear

bit 6

CKE: SPI Clock Edge Select bit

SPI mode, CKP = 0:

1= Data transmitted on falling edge of SCK

0= Data transmitted on rising edge of SCK (Microwire alternate)

SPI mode, CKP = 1:

1= Data transmitted on rising edge of SCK

0= Data transmitted on falling edge of SCK (Microwire default)

I²C mode:

This bit must be maintained clear

bit 5

bit 4

D/A: Data/Address bit (I²C mode only)

1= Indicates that the last byte received or transmitted was data

0= Indicates that the last byte received or transmitted was address

P: Stop bit (I²C mode only)

This bit is cleared when the SSP module is disabled, or when the Start bit is detected last.

SSPEN is cleared.

1= Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset)

0= Stop bit was not detected last

bit 3

bit 2

S: Start bit (I²C mode only)

This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last.

SSPEN is cleared.

1= Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset)

0= Start bit was not detected last

R/W: Read/Write bit Information (I²C mode only)

This bit holds the R/W bit information following the last address match. This bit is only valid from

the address match to the next Start bit, Stop bit or ACK bit.

1= Read

0= Write

bit 1

bit 0

UA: Update Address bit (10-bit I²C mode only)

1= Indicates that the user needs to update the address in the SSPADD register

0= Address does not need to be updated

BF: Buffer Full Status bit

Receive (SPI and I²C modes):

1= Receive complete, SSPBUF is full

0= Receive not complete, SSPBUF is empty

Transmit (I²C mode only):

1= Transmit in progress, SSPBUF is full

0= Transmit complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 160

Preliminary

PIC16F917/916/914/913

REGISTER 14-2: SSPCON – SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0

WCOL

R/W-0

CKP

R/W-0

SSPOV

SSPEN

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

bit 6

WCOL: Write Collision Detect bit

1= The SSPBUF register is written while it is still transmitting the previous word (must be cleared

in software)

0= No collision

SSPOV: Receive Overflow Indicator bit

In SPI™ mode:

1= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read

the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over-

flow bit is not set since each new reception (and transmission) is initiated by writing to the SSP-

BUF register.

0= No overflow

2

In I C™ mode:

1= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t

care” in Transmit mode. SSPOV must be cleared in software in either mode.

0= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In SPI mode:

1= Enables serial port and configures SCK, SDO, and SDI as serial port pins

0= Disables serial port and configures these pins as I/O port pins

2

In I C mode:

1= Enables the serial port and configures the SDA and SCL pins as serial port pins

0= Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

1= Idle state for clock is a high level (Microwire default)

0= Idle state for clock is a low level (Microwire alternate)

2

In I C mode:

SCK release control

1= Enable clock

0= Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0

SSPM<3:0>: Synchronous Serial Port Mode Select bits

0000= SPI Master mode, clock = FOSC/4

0001= SPI Master mode, clock = FOSC/16

0010= SPI Master mode, clock = FOSC/64

0011= SPI Master mode, clock = TMR2 output/2

0100= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

0110= I²C Slave mode, 7-bit address

0111= I²C Slave mode, 10-bit address

1011= I²C Firmware Controlled Master mode (slave idle)

1110= I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled

1111= I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

Preliminary

DS41250E-page 161

PIC16F917/916/914/913

FIGURE 14-1:

SSP BLOCK DIAGRAM

(SPI MODE)

Note 1: When the SPI is in Slave mode with SS

pin control enabled (SSPCON<3:0> =

0100), the SPI module will reset if the SS

pin is set to VDD.

Internal

Data Bus

Read

Write

2: If the SPI is used in Slave mode with

CKE = 1, then the SS pin control must be

enabled.

SSPBUF Reg

RC7/RX/

DT/SDI/

SDA/SEG8

3: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),

the state of the SS pin can affect the state

read back from the TRISC<4> bit. The

peripheral OE signal from the SSP module

into PORTC controls the state that is read

back from the TRISC<4> bit (see

SSPSR Reg

Shift

bit 0

Clock

RC4/T1G/

SDO/SEG11

Peripheral OE

Section 19.4

PIC16F917/916/914/913-I

PIC16F917/916/914/913-E (Extended)”

for information on PORTC). If

“DC

Characteristics:

(Industrial)

Control

Enable

SS

RA5/AN2/

C2OUT/SS/

SEG5

Edge

Select

read-modify-write instructions, such as

BSF,are performed on the TRISC register

while the SS pin is high, this will cause the

TRISC<4> bit to be set, thus disabling the

SDO output.

2

Clock Select

SSPM<3:0>

4

TMR2 Output

2

Edge

Select

TCY

Prescaler

4, 16, 64

RC6/TX/CK/

SCK/SCL/

SEG9

TRISC<6>

To enable the serial port, SSPEN bit (SSPCON<5>)

must be set. To reset or reconfigure SPI mode:

• Clear bit SSPEN

• Re-initialize the SSPCON register

• Set SSPEN bit

This configures the SDI, SDO, SCK and SS pins as

serial port pins. For the pins to behave in a serial port

function, they must have their data direction bits (in the

TRISC register) appropriately programmed. This is:

• SDI must have TRISC<7> set

• SDO must have TRISC<4> cleared

• SCK (Master mode) must have TRISC<6>

cleared

• SCK (Slave mode) must have TRISC<6> set

• SS must have TRISA<5> set.

DS41250E-page 162

Preliminary

PIC16F917/916/914/913

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. Buffer

Full bit, BF (SSPSTAT<0>), indicates when SSPBUF

has been loaded with the received data (transmission

is complete). When the SSPBUF is read, the BF bit is

cleared. This data may be irrelevant if the SPI is only a

transmitter. Generally, the SSP interrupt is used to

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 14-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

14.2 Operation

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits (SSPCON<5:0> and SSPSTAT<7:6>).

These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Data Input Sample Phase (middle or end of data

output time)

• Clock Edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

The SSPSR is not directly readable or writable and can

only be accessed by addressing the SSPBUF register.

Additionally, the SSP Status register (SSPSTAT)

indicates the various status conditions.

• Slave Select mode (Slave mode only)

The SSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR

until the received data is ready. Once the eight bits of

data have been received, that byte is moved to the

SSPBUF register. Then, the Buffer Full detect bit, BF

(SSPSTAT<0>), and the interrupt flag bit, SSPIF, are

set. This double-buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored and the write collision detect bit, WCOL

(SSPCON<7>), will be set. User software must clear the

WCOL bit so that it can be determined if the following

write(s) to the SSPBUF register completed successfully.

EXAMPLE 14-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF

;Has data been received(transmit complete)?

BRA

LOOP

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF RXDATA

;Save in user RAM, if data is meaningful

MOVF

MOVWF SSPBUF

TXDATA, W

;W reg = contents of TXDATA

;New data to xmit

Preliminary

DS41250E-page 163

PIC16F917/916/914/913

14.3 Enabling SPI I/O

14.4 Typical Connection

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON<5>), must be set. To reset or reconfigure

SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers and then set the SSPEN bit. This

configures the SDI, SDO, SCK and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, some must have their data direction bits (in the

TRIS register) appropriately programmed. That is:

Figure 14-2 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their

programmed clock edge and latched on the opposite

edge of the clock. Both processors should be

programmed to the same Clock Polarity (CKP), then

both controllers would send and receive data at the

same time. Whether the data is meaningful (or dummy

data) depends on the application software. This leads

to three scenarios for data transmission:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<4> bit cleared

• SCK (Master mode) must have TRISC<6> bit

cleared

• Master sends data – Slave sends dummy data

• Master sends data – Slave sends data

• SCK (Slave mode) must have TRISC<6> bit set

• SS must have TRISA<5> bit set

• Master sends dummy data – Slave sends data

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

FIGURE 14-2:

SPI™ MASTER/SLAVE CONNECTION

SPI™ Master SSPM<3:0> = 00xxb

SDO

SPI™ Slave SSPM<3:0> = 010xb

SDI

Serial Input Buffer

(SSPBUF)

Serial Input Buffer

(SSPBUF)

SDI

SDO

SCK

Shift Register

(SSPSR)

Shift Register

(SSPSR)

LSb

MSb

LSb

Serial Clock

SCK

Processor 1

Processor 2

DS41250E-page 164

Preliminary

PIC16F917/916/914/913

Figure 14-3, Figure 14-5 and Figure 14-6, where the

MSB is transmitted first. In Master mode, the SPI clock

rate (bit rate) is user programmable to be one of the

following:

14.5 Master Mode

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 14-2) is to

broadcast data by the software protocol.

• FOSC/4 (or TCY)

• FOSC/16 (or 4 • TCY)

• FOSC/64 (or 16 • TCY)

• Timer2 output/2

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI is

only going to receive, the SDO output could be

disabled (programmed as an input). The SSPSR

register will continue to shift in the signal present on the

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and Status bits

appropriately set). This could be useful in receiver

applications as a “Line Activity Monitor” mode.

This allows a maximum data rate (at 40 MHz) of

10 Mbps.

Figure 14-3 shows the waveforms for Master mode.

When the CKE bit is set, the SDO data is valid before

there is a clock edge on SCK. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPBUF is loaded with the received

data is shown.

The clock polarity is selected by appropriately program-

ming the CKP bit (SSPCON<4>). This then, would give

waveforms for SPI communication as shown in

FIGURE 14-3:

SPI™ MODE WAVEFORM (MASTER MODE)

Write to

SSPBUF

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

4 Clock

Modes

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

SDO

(CKE = 0)

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

bit 7

bit 3

SDO

(CKE = 1)

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SDI

(SMP = 1)

bit 0

bit 7

Input

Sample

(SMP = 1)

SSPIF

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

Preliminary

DS41250E-page 165

PIC16F917/916/914/913

becomes a floating output. External pull-up/pull-down

resistors may be desirable, depending on the applica-

tion.

14.6 Slave Mode

In Slave mode, the data is transmitted and received as

the external clock pulses appear on SCK. When the

last bit is latched, the SSPIF interrupt flag bit is set.

Note 1: When the SPI is in Slave mode with SS pin

control enabled (SSPCON<3:0> = 0100),

the SPI module will reset if the SS pin is set

to VDD.

While in Slave mode, the external clock is supplied by

the external clock source on the SCK pin. This external

clock must meet the minimum high and low times as

specified in the electrical specifications.

2: If the SPI is used in Slave Mode with CKE

set, then the SS pin control must be

enabled.

While in Sleep mode, the slave can transmit/receive

data. When a byte is received, the device will wake-up

from Sleep.

When the SPI module resets, the bit counter is forced

to ‘0’. This can be done by either forcing the SS pin to

a high level or clearing the SSPEN bit.

14.7 Slave Select Synchronization

To emulate two-wire communication, the SDO pin can

be connected to the SDI pin. When the SPI needs to

operate as a receiver, the SDO pin can be configured

as an input. This disables transmissions from the SDO.

The SDI can always be left as an input (SDI function)

since it cannot create a bus conflict.

The SS pin allows a Synchronous Slave mode. The

SPI must be in Slave mode with SS pin control enabled

(SSPCON<3:0> = 04h). The pin must not be driven low

for the SS pin to function as an input. The data latch

must be high. When the SS pin is low, transmission and

reception are enabled and the SDO pin is driven. When

the SS pin goes high, the SDO pin is no longer driven,

even if in the middle of a transmitted byte, and

FIGURE 14-4:

SLAVE SYNCHRONIZATION WAVEFORM

SS

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 7

bit 0

SDO

bit 7

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

DS41250E-page 166

Preliminary

PIC16F917/916/914/913

FIGURE 14-5:

SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 0)

SS

Optional

SCK

(CKP = 0

CKE = 0)

SCK

(CKP = 1

CKE = 0)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

FIGURE 14-6:

SPI™ MODE WAVEFORM (SLAVE MODE WITH CKE = 1)

SS

Not Optional

SCK

(CKP = 0

CKE = 1)

SCK

(CKP = 1

CKE = 1)

Write to

SSPBUF

bit 6

bit 2

bit 5

bit 4

bit 1

bit 0

SDO

bit 7

bit 3

SDI

(SMP = 0)

bit 0

bit 7

Input

Sample

(SMP = 0)

SSPIF

Interrupt

Flag

Next Q4 Cycle

after Q2↓

SSPSR to

SSPBUF

Preliminary

DS41250E-page 167

PIC16F917/916/914/913

14.8 Sleep Operation

14.10 Bus Mode Compatibility

In Master mode, all module clocks are halted and the

transmission/reception will remain in that state until the

device wakes from Sleep. After the device returns to

normal mode, the module will continue to trans-

mit/receive data.

Table 14-1 shows the compatibility between the

standard SPI modes and the states of the CKP and

CKE control bits.

TABLE 14-1: SPI™ BUS MODES

In Slave mode, the SPI Transmit/Receive Shift register

operates asynchronously to the device. This allows the

device to be placed in Sleep mode and data to be

shifted into the SPI Transmit/Receive Shift register.

When all 8 bits have been received, the SSP interrupt

flag bit will be set and if enabled, will wake the device

from Sleep.

Control Bits State

Standard SPI™

Mode Terminology

CKP

CKE

0, 0

0, 1

1, 0

1, 1

0

1

0

1

0

14.9 Effects of a Reset

There is also a SMP bit which controls when the data is

sampled.

A Reset disables the SSP module and terminates the

current transfer.

TABLE 14-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION

Value on:

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh.

10Bh,18Bh

INTCON

PIR1

GIE

PEIE

ADIF

T0IE

INTE

TXIF

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

13h

EEIF

RCIF

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

1111 1111 1111 1111

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

14h

SSPCON

TRISC

WCOL

SSPOV SSPEN

CKP

87h

TRISC7

EEIE

TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0

8Ch

85h

PIE1

ADIE

TRISA6 TRISA5

CKE D/A

RCIE

TXIE

TRISA4

P

TRISA

1111 1111 1111 1111

0000 0000 0000 0000

TRISA7

SMP

TRISA3 TRISA2

R/W

TRISA1

UA

TRISA0

BF

94h

SSPSTAT

S

Legend:

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.

DS41250E-page 168

Preliminary

PIC16F917/916/914/913

The SSPCON register allows control of the I²C

operation. Four mode selection bits (SSPCON<3:0>)

allow one of the following I²C modes to be selected:

• I²C Slave mode (7-bit address)

• I²C Slave mode (10-bit address)

• I²C Slave mode (7-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

• I²C Slave mode (10-bit address), with Start and

Stop bit interrupts enabled to support Firmware

Master mode

2

14.11 SSP I C Operation

The SSP module in I²C mode, fully implements all

slave functions, except general call support, and pro-

vides interrupts on Start and Stop bits in hardware to

facilitate firmware implementations of the master func-

tions. The SSP module implements the Standard mode

specifications, as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the

RC6/TX/CK/SCK/SCL/SEG9 pin, which is the clock

(SCL), and the RC7/RX/DT/SDI/SDA/SEG8 pin, which

is the data (SDA).

• I²C Start and Stop bit interrupts enabled to

support Firmware Master mode; Slave is idle

The SSP module functions are enabled by setting SSP

enable bit SSPEN (SSPCON<5>).

Selection of any I²C mode with the SSPEN bit set

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits. Pull-up resistors must be

provided externally to the SCL and SDA pins for proper

operation of the I²C module.

FIGURE 14-7:

SSP BLOCK DIAGRAM

(I²C™ MODE)

Internal

Data Bus

Additional information on SSP I²C operation can be

found in the “PICmicro^®Mid-Range MCU Family

Reference Manual” (DS33023).

Read

Write

RC6/TX/

CK/SCK/

SCL/SEG9

SSPBUF Reg

Shift

Clock

14.12 Slave Mode

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<7:6> set). The SSP module will

override the input state with the output data when

required (slave-transmitter).

SSPSR Reg

RC7/

MSb

LSb

RX/DT/

SDI/

SDA/

SEG8

Addr Match

Match Detect

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the Acknowledge (ACK) pulse, and

then load the SSPBUF register with the received value

currently in the SSPSR register.

SSPADD Reg

Set, Reset

S, P bits

(SSPSTAT reg)

Start and

Stop bit Detect

There are certain conditions that will cause the SSP

module not to give this ACK pulse. They include (either

or both):

The SSP module has five registers for the I²C operation,

which are listed below.

a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

In this case, the SSPSR register value is not loaded into

the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 14-3

shows the results of when a data transfer byte is received,

given the status of bits BF and SSPOV. The shaded cells

show the condition where user software did not properly

clear the overflow condition. Flag bit BF is cleared by

reading the SSPBUF register, while bit SSPOV is cleared

through software.

• SSP Shift Register (SSPSR) – Not directly

accessible

• SSP Address Register (SSPADD)

The SCL clock input must have a minimum high and

low for proper operation. For high and low times of the

I²C specification, as well as the requirements of the

SSP module, see Section 19.0 “Electrical Specifica-

tions”.

Preliminary

DS41250E-page 169

PIC16F917/916/914/913

The sequence of events for 10-bit address is as follows,

with steps 7-9 for slave-transmitter:

14.12.1 ADDRESSING

Once the SSP module has been enabled, it waits for a

Start condition to occur. Following the Start condition,

the 8-bits are shifted into the SSPSR register. All

incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

1. Receive first (high) byte of address (bits SSPIF,

BF and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

4. Receive second (low) byte of address (bits

SSPIF, BF and UA are set).

a) The SSPSR register value is loaded into the

SSPBUF register.

5. Update the SSPADD register with the first (high)

byte of address; if match releases SCL line, this

will clear bit UA.

b) The buffer full bit, BF is set.

c) An ACK pulse is generated.

6. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) on the falling

edge of the ninth SCL pulse.

7. Receive repeated Start condition.

8. Receive first (high) byte of address (bits SSPIF

and BF are set).

In 10-bit Address mode, two address bytes need to be

received by the slave (Figure 14-8). The five Most

Significant bits (MSbs) of the first address byte specify

if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must

specify a write so the slave device will receive the

second address byte. For a 10-bit address, the first

byte would equal ‘1111 0 A9 A8 0’, where A9and

A8are the two MSbs of the address.

9. Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

TABLE 14-3: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

Generate ACK

Transfer is Received

SSPSR → SSPBUF

Pulse

BF

SSPOV

0

1

Yes

No

Yes

No

Yes

1

0

Note:

Shaded cells show the conditions where the user software did not properly clear the overflow condition.

DS41250E-page 170

Preliminary

PIC16F917/916/914/913

14.12.2 RECEPTION

When the R/W bit of the address byte is clear and an

address match occurs, the R/W bit of the SSPSTAT

register is cleared. The received address is loaded into

the SSPBUF register.

When the address byte overflow condition exists, then

no Acknowledge (ACK) pulse is given. An overflow

condition is defined as either bit BF (SSPSTAT<0>) is

set, or bit SSPOV (SSPCON<6>) is set. This is an error

condition due to the user’s firmware.

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF (PIR1<3>) must be cleared in

software. The SSPSTAT register is used to determine

the status of the byte.

FIGURE 14-8:

I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

R/W = 0

Receiving Address

A7 A6 A5 A4

Receiving Data

ACK

9

ACK

9

ACK

9

SDA

SCL

A3 A2 A1

D5

D2

D0

8

D5

D2

D0

8

D7 D6

D4 D3

D7 D6

D4 D3

D1

7

D1

7

3

7

1

2

4

5

4

3

6

5

6

1

2

3

6

1

2

4

8

5

P

S

SSPIF (PIR1<3>)

Cleared in software

Bus Master

terminates

transfer

BF (SSPSTAT<0>)

SSPBUF register is read

SSPOV (SSPCON<6>)

Bit SSPOV is set because the SSPBUF register is still full.

ACK is not sent.

Preliminary

DS41250E-page 171

PIC16F917/916/914/913

FIGURE 14-9:

I²C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS)

DS41250E-page 172

Preliminary

PIC16F917/916/914/913

An SSP interrupt is generated for each data transfer

byte. Flag bit SSPIF must be cleared in software, and

the SSPSTAT register is used to determine the status

of the byte. Flag bit SSPIF is set on the falling edge of

the ninth clock pulse.

14.12.3 TRANSMISSION

When the R/W bit of the incoming address byte is set

and an address match occurs, the R/W bit of the

SSPSTAT register is set. The received address is

loaded into the SSPBUF register. The ACK pulse will

As a slave-transmitter, the ACK pulse from the master

receiver is latched on the rising edge of the ninth SCL

input pulse. If the SDA line was high (not ACK), then

the data transfer is complete. When the ACK is latched

by the slave, the slave logic is reset (resets SSPSTAT

register) and the slave then monitors for another occur-

rence of the Start bit. If the SDA line was low (ACK), the

transmit data must be loaded into the SSPBUF register,

which also loads the SSPSR register. Then pin

RC6/TX/CK/SCK/SCL/SEG9 should be enabled by

setting bit CKP.

be

sent

on

the

ninth

bit,

and

RC6/TX/CK/SCK/SCL/SEG9 is held low. The transmit

data must be loaded into the SSPBUF register, which

also loads the SSPSR register. Then, pin

RC6/TX/CK/SCK/SCL/SEG9 should be enabled by

setting bit CKP (SSPCON<4>). The master must mon-

itor the SCL pin prior to asserting another clock pulse.

The slave devices may be holding off the master by

stretching the clock. The eight data bits are shifted out

on the falling edge of the SCL input. This ensures that

the SDA signal is valid during the SCL high time

(Figure 14-10).

FIGURE 14-10:

I²C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address

R/W = 1

ACK

Transmitting Data

ACK

9

SDA

A7 A6 A5 A4 A3 A2 A1

D7 D6 D5 D4 D3 D2 D1 D0

SCL

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

S

P

SCL held low

while CPU

responds to SSPIF

Data in

sampled

Cleared in software

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

From SSP Interrupt

Service Routine

SSPBUF is written in software

CKP (SSPCON<4>)

Set bit after writing to SSPBUF

(the SSPBUF must be written to

before the CKP bit can be set)

Preliminary

DS41250E-page 173

PIC16F917/916/914/913

2

FIGURE 14-11:

I C™ SLAVE MODE TIMING (TRANSMISSION, 10-BIT ADDRESS)

DS41250E-page 174

Preliminary

PIC16F917/916/914/913

14.13 Master Mode

14.14 Multi-Master Mode

Master mode of operation is supported in firmware

using interrupt generation on the detection of the Start

and Stop conditions. The Stop (P) and Start (S) bits are

cleared from a Reset or when the SSP module is dis-

abled. The Stop (P) and Start (S) bits will toggle based

on the Start and Stop conditions. Control of the I²C bus

may be taken when the P bit is set or the bus is idle and

both the S and P bits are clear.

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions, allows the

determination of when the bus is free. The Stop (P)

and Start (S) bits are cleared from a Reset or when the

SSP module is disabled. The Stop (P) and Start (S)

bits will toggle based on the Start and Stop conditions.

Control of the I²C bus may be taken when bit P

(SSPSTAT<4>) is set, or the bus is idle and both the S

and P bits clear. When the bus is busy, enabling the

SSP Interrupt will generate the interrupt when the Stop

condition occurs.

In Master mode, the SCL and SDA lines are manipu-

lated by clearing the corresponding TRISC<6:7> bit(s).

The output level is always low, irrespective of the

value(s) in PORTC<6:7>. So when transmitting data, a

‘1’ data bit must have the TRISC<7> bit set (input) and

a ‘0’ data bit must have the TRISC<7> bit cleared (out-

put). The same scenario is true for the SCL line with the

TRISC<6> bit. Pull-up resistors must be provided

externally to the SCL and SDA pins for proper opera-

tion of the I²C module.

In Multi-Master operation, the SDA line must be moni-

tored to see if the signal level is the expected output

level. This check only needs to be done when a high

level is output. If a high level is expected and a low

level is present, the device needs to release the SDA

and SCL lines (set TRISC<6:7>). There are two

stages where this arbitration can be lost, these are:

The following events will cause the SSP Interrupt Flag

bit, SSPIF, to be set (SSP Interrupt will occur if

enabled):

• Address Transfer

• Data Transfer

When the slave logic is enabled, the slave continues

to receive. If arbitration was lost during the address

transfer stage, communication to the device may be in

progress. If addressed, an ACK pulse will be gener-

ated. If arbitration was lost during the data transfer

stage, the device will need to re-transfer the data at a

later time.

• Start condition

• Stop condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the

Slave mode idle (SSPM<3:0> = 1011), or with the

Slave active. When both Master and Slave modes are

enabled, the software needs to differentiate the

source(s) of the interrupt.

14.14.1 CLOCK SYNCHRONIZATION AND

THE CKP BIT

When the CKP bit is cleared, the SCL output is forced

to ‘0’; however, setting the CKP bit will not assert the

SCL output low until the SCL output is already sampled

low. Therefore, the CKP bit will not assert the SCL line

until an external I²C master device has already

asserted the SCL line. The SCL output will remain low

until the CKP bit is set and all other devices on the I²C

bus have deasserted SCL. This ensures that a write to

the CKP bit will not violate the minimum high time

requirement for SCL (see Figure 14-12).

Preliminary

DS41250E-page 175

PIC16F917/916/914/913

FIGURE 14-12:

CLOCK SYNCHRONIZATION TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

SDA

SCL

DX

DX-1

Master device

asserts clock

CKP

Master device

deasserts clock

WR

SSPCON

TABLE 14-4: REGISTERS ASSOCIATED WITH I²C™ OPERATION

Value on:

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, 8Bh, INTCON

10Bh,18Bh

GIE

PEIE

T0IE

INTE RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

8Ch

13h

14h

87h

93h

94h

PIR1

PIE1

EEIF

EEIE

ADIF

ADIE

RCIF

RCIE

TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

xxxx xxxx uuuu uuuu

TRISC

PORTC Data Direction Register

1111 1111 1111 1111

0000 0000 0000 0000

2

SSPADD Synchronous Serial Port (I C™ mode) Address Register

(1)

SSPSTAT SMP

CKE

D/A

P

S

R/W

UA

BF

Legend: x= unknown, u= unchanged, -= unimplemented locations read as ‘0’. Shaded cells are not used by SSP

2

module in I C mode.

Note 1: Maintain these bits clear in I C mode.

2

DS41250E-page 176

Preliminary

PIC16F917/916/914/913

CCP2 Module:

15.0 CAPTURE/COMPARE/PWM

MODULES

Capture/Compare/PWM Register2 (CCPR2) is com-

prised of two 8-bit registers: CCPR2L (low byte) and

CCPR2H (high byte). The CCP2CON register controls

the operation of CCP2. The special event trigger is

generated by a compare match and will reset Timer1

and start an A/D conversion (if the A/D module is

enabled).

Each Capture/Compare/PWM (CCP) module contains

a 16-bit register which can operate as a:

• 16-bit Capture register

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Additional information on CCP modules is available in

the “PICmicro^®Mid-Range MCU Family Reference

Manual” (DS33023) and in Application Note AN594,

“Using the CCP Modules” (DS00594).

Both the CCP1 and CCP2 modules are identical in

operation, with the exception being the operation of the

special event trigger. Table 15-1 and Table 15-2 show

the resources and interactions of the CCP module(s).

In the following sections, the operation of a CCP

module is described with respect to CCP1. CCP2

operates the same as CCP1, except where noted.

TABLE 15-1: CCP MODE – TIMER

RESOURCES REQUIRED

CCP1 Module:

CCP Mode

Timer Resource

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. The special event trigger is

generated by a compare match and will reset Timer1.

Capture

Compare

PWM

Timer1

Timer2

TABLE 15-2: INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode

Interaction

Capture

Same TMR1 time base

Capture

Compare

PWM

Compare

PWM

The compare should be configured for the special event trigger, which clears TMR1

The compare(s) should be configured for the special event trigger, which clears TMR1

The PWMs will have the same frequency and update rate (TMR2 interrupt)

PWM

Capture

Compare

None

PWM

Preliminary

DS41250E-page 177

PIC16F917/916/914/913

REGISTER 15-1: CCP1CON – CCP2CON⁽¹⁾REGISTER (ADDRESS: 17h/1Dh)

U-0

—

U-0

—

R/W-0

CCPxX

CCPxY

CCPxM3

CCPxM2 CCPxM1 CCPxM0

bit 0

bit 7

bit 7-6

bit 5-4

Unimplemented: Read as ‘0’

CCPxX:CCPxY: PWM Least Significant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0

CCPxM<3:0>: CCPx Mode Select bits

0000= Capture/Compare/PWM disabled (resets CCPx module)

0100= Capture mode, every falling edge

0101= Capture mode, every rising edge

0110= Capture mode, every 4th rising edge

0111= Capture mode, every 16th rising edge

1000= Compare mode, set output on match (CCPxIF bit is set)

1001= Compare mode, clear output on match (CCPxIF bit is set)

1010= Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is

unaffected)

1011= Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected);

CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module

is enabled)

11xx= PWM mode

Note 1: CCP2CON used for PIC16F914/917 only.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

DS41250E-page 178

Preliminary

PIC16F917/916/914/913

15.1.4

CCP PRESCALER

15.1 Capture Mode

There are four prescaler settings, specified by bits

CCP1M<3:0>. Whenever the CCP module is turned

off, or the CCP module is not in Capture mode, the

prescaler counter is cleared. Any Reset will clear the

prescaler counter.

In Capture mode, CCPR1H:CCPR1L captures the

16-bit value of the TMR1 register when an event occurs

on pin RC5/T1CKI/CCP1/SEG10. An event is defined

as one of the following:

• Every falling edge

• Every rising edge

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleared, therefore, the first capture may be from

a non-zero prescaler. Example 15-1 shows the recom-

mended method for switching between capture pre-

scalers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

• Every 4th rising edge

• Every 16th rising edge

The type of event is configured by control bits

CCP1M<3:0> (CCPxCON<3:0>). When a capture is

made, the interrupt request flag bit CCP1IF (PIR1<2>)

is set. The interrupt flag must be cleared in software. If

another capture occurs before the value in register

CCPR1 is read, the old captured value is overwritten by

the new value.

EXAMPLE 15-1:

CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF

CCP1CON

; Turn CCP module off

MOVLW

NEW_CAPT_PS ; Load the W reg with

; the new prescaler

15.1.1

CCP PIN CONFIGURATION

; move value and CCP ON

; Load CCP1CON with this

; value

In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin

should be configured as an input by setting the

TRISC<5> bit.

MOVWF

CCP1CON

Note:

If the RC5/T1CKI/CCP1/SEG10 pin is

configured as an output, a write to the port

can cause a capture condition.

FIGURE 15-3:

CAPTURE MODE

OPERATION BLOCK

DIAGRAM

RC5/T1CKI/

Set Flag bit CCP1IF

(PIR1<2>)

CCP1/SEG10

Prescaler

÷ 1, 4, 16

CCPR1H

CCPR1L

Capture

Enable

and

edge detect

TMR1H

TMR1L

CCP1CON<3:0>

Qs

15.1.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

15.1.3

SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit CCP1IF, following any such

change in Operating mode.

Preliminary

DS41250E-page 179

PIC16F917/916/914/913

15.2.3

SOFTWARE INTERRUPT MODE

15.2 Compare Mode

When Generate Software Interrupt mode is chosen, the

RC5/T1CKI/CCP1/SEG10 pin is not affected. The

CCPIF bit is set, causing a CCP interrupt (if enabled).

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against the TMR1 register pair

value.

When

a

match

occurs,

the

RC5/T1CKI/CCP1/SEG10 pin is:

15.2.4

SPECIAL EVENT TRIGGER

• Driven high

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

• Driven low

• Remains unchanged

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The action on the pin is based on the value of control

bits CCP1M<3:0> (CCP1CON<3:0>). At the same

time, interrupt flag bit CCP1IF is set.

The special event trigger output of CCP2 resets the

TMR1 register pair and starts an A/D conversion (if the

A/D module is enabled).

FIGURE 15-4:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

Note:

The special event trigger from the CCP1

and CCP2 modules will not set interrupt

flag bit TMR1IF (PIR1<0>).

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Special Event Trigger

Set Flag bit CCP1IF

15.3 PWM Mode (PWM)

In Pulse Width Modulation mode, the CCPx pin pro-

duces up to a 10-bit resolution PWM output. Since the

RC5/T1CKI/CCP1/SEG10 pin is multiplexed with the

PORTC data latch, the TRISC<5> bit must be cleared

to make the RC5/T1CKI/CCP1/SEG10 pin an output.

RC5/T1CKI/

(PIR1<2>)

CCP1/SEG10

CCPR1H CCPR1L

Comparator

Q

S

R

Output

Logic

Match

TRISC<5>

Output Enable

TMR1H TMR1L

Note:

Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default

low level. This is not the PORTC I/O data

latch.

CCP1CON<3:0>

Mode Select

15.2.1

CCP PIN CONFIGURATION

Figure 15-5 shows a simplified block diagram of the

CCP module in PWM mode.

The user must configure the RC5/T1CKI/CCP1/SEG10

pin as an output by clearing the TRISC<5> bit.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 15.3.3

“Setup for PWM Operation”.

Note:

Clearing the CCP1CON register will force

the RC5/T1CKI/CCP1/SEG10 compare

output latch to the default low level. This is

not the PORTC I/O data latch.

15.2.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

DS41250E-page 180

Preliminary

PIC16F917/916/914/913

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

FIGURE 15-5:

SIMPLIFIED PWM BLOCK

DIAGRAM

• TMR2 is cleared

CCP1CON<5:4>

Duty Cycle Registers

• The RC5/T1CKI/CCP1/SEG10 pin is set

(exception: if PWM duty cycle = 0%, the

RC5/T1CKI/CCP1/SEG10 pin will not be set)

CCPR1L

• The PWM duty cycle is latched from CCPR1L into

CCPR1H

CCPR1H (Slave)

Comparator

TMR2

RC5/T1CKI/

CCP1/SEG10

Note:

The Timer2 postscaler (see Section 7.0

“Timer2 Module”) is not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

Q

R

S

(1)

TRISC<5>

Comparator

PR2

15.3.2

PWM DUTY CYCLE

Clear Timer,

CCP1 pin and

latch D.C.

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

Note 1: The 8-bit timer is concatenated with 2-bit internal Q

clock, or 2 bits of the prescaler, to create 10-bit time

base.

A PWM output (Figure 15-6) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

PWM duty cycle =(CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

FIGURE 15-6:

PWM OUTPUT

Period

The CCPR1H register and a 2-bit internal latch are

used to double buffer the PWM duty cycle. This double

buffering is essential for glitch-free PWM operation.

Duty Cycle

TMR2 = PR2

When the CCPR1H and 2-bit latch match TMR2, con-

catenated with an internal 2-bit Q clock, or 2 bits of the

TMR2 prescaler, the CCP1 pin is cleared.

TMR2 = Duty Cycle

TMR2 = PR2

The maximum PWM resolution (bits) for a given PWM

frequency is given by the formula:

15.3.1

PWM PERIOD

FOSC

⎛

⎝

⎞

⎠

-------------------------------------------------------------

log

FPWM × TMR2 Prescaler

The PWM period is specified by writing to the PR2

register. The PWM period can be calculated using the

following formula:

PWM Resolution = --------------------------------------------------------------------------- bits

log(2)

Note:

If the PWM duty cycle value is longer than

the PWM period, the

RC5/T1CKI/CCP1/SEG10 pin will not be

cleared.

PWM period = (PR2) + 1] • 4 • TOSC •

(TMR2 prescale value)

PWM frequency is defined as 1/[PWM period].

Preliminary

DS41250E-page 181

PIC16F917/916/914/913

15.3.3

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

register.

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the RC5/T1CKI/CCP1/SEG10 pin an

output by clearing the TRISC<5> bit.

4. Set the TMR2 prescale value and enable Timer2

by writing to T2CON.

5. Configure the CCP1 module for PWM operation.

TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency

1.22 kHz 4.88 kHz 19.53 kHz

78.12kHz

156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16)

PR2 Value

16

0xFFh

10

4

1

0x3Fh

8

1

0x1Fh

7

1

0xFFh

10

0xFFh

10

0x17h

5.5

Maximum Resolution (bits)

TABLE 15-2: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1

Value on:

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh,

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

10Bh, 18Bh

0Ch

0Dh

8Ch

8Dh

87h

PIR1

EEIF

OSFIF

EEIE

ADIF

C2IF

ADIE

C2IE

RCIF

C1IF

RCIE

C1IE

TXIF

LCDIF

TXIE

SSPIF

—

CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

LVDIF CCP2IF 0000 -0-0 0000 -0-0

CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

LVDIE CCP2IE 0000 -0-0 0000 -0-0

TRISC2 TRISC1 TRISC0 1111 1111 1111 1111

PIR2

—

PIE1

SSPIE

—

PIE2

OSFIE

LCDIE

—

TRISC

TRISC7 TRISC6 TRISC5 TRISC4

TRISC3

0Eh

0Fh

TMR1L

TMR1H

T1CON

CCPR1L

CCPR1H

CCP1CON

CCPR2L

CCPR2H

CCP2CON

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx uuuu uuuu

10h

T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu

15h

Capture/Compare/PWM Register1 (LSB)

Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

16h

17h

—

CCP1X

CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh

1Ch

1Dh

Legend:

Capture/Compare/PWM Register 2 (LSB)

Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

—

CCP2X

CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.

DS41250E-page 182

Preliminary

PIC16F917/916/914/913

TABLE 15-3: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on:

POR,

BOR

Value on

all other

Resets

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh,8Bh,

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

10Bh, 18Bh

0Ch

0Dh

8Ch

8Dh

87h

PIR1

EEIF

OSFIF

EEIE

ADIF

C2IF

ADIE

C2IE

RCIF

C1IF

RCIE

C1IE

TXIF

LCDIF

TXIE

SSPIF

—

CCP1IF TMR2IF

LVDIF

CCP1IE TMR2IE

LVDIE

TMR1IF 0000 0000 0000 0000

CCP2IF 0000 -0-0 0000 -0-0

TMR1IE 0000 0000 0000 0000

CCP2IE 0000 -0-0 0000 -0-0

1111 1111 1111 1111

PIR2

—

PIE1

SSPIE

—

PIE2

OSFIE

LCDIE

—

TRISC

TMR2

PR2

PORTC Data Direction Register

Timer2 Module Register

11h

0000 0000 0000 0000

92h

Timer2 Module Period Register

1111 1111 1111 1111

12h

T2CON

—

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h

CCPR1L Capture/Compare/PWM Register 1 (LSB)

CCPR1H Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx uuuu uuuu

16h

17h

CCP1CON

—

CCP1X

CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

1Bh

1Ch

1Dh

Legend:

CCPR2L Capture/Compare/PWM Register 2 (LSB)

CCPR2H Capture/Compare/PWM Register 2 (MSB)

xxxx xxxx uuuu uuuu

CCP2CON

—

CCP2X

CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

x= unknown, u= unchanged, -= unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.

Preliminary

DS41250E-page 183

PIC16F917/916/914/913

NOTES:

DS41250E-page 184

Preliminary

PIC16F917/916/914/913

The PIC16F917/916/914/913 has two timers that offer

necessary delays on power-up. One is the Oscillator

Start-up Timer (OST), intended to keep the chip in

Reset until the crystal oscillator is stable. The other is

the Power-up Timer (PWRT), which provides a fixed

delay of 64 ms (nominal) on power-up only, designed

to keep the part in Reset while the power supply

stabilizes. There is also circuitry to reset the device if

a brown-out occurs, which can use the Power-up

Timer to provide at least a 64 ms Reset. With these

three functions-on-chip, most applications need no

external Reset circuitry.

16.0 SPECIAL FEATURES OF THE

CPU

The PIC16F917/916/914/913 has a host of features

intended to maximize system reliability, minimize cost

through elimination of external components, provide

power saving features and offer code protection.

These features are:

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

The Sleep mode is designed to offer a very low-current

Power-down mode. The user can wake-up from Sleep

through:

• External Reset

• Watchdog Timer (WDT)

• Oscillator Selection

• Sleep

• Watchdog Timer Wake-up

• An interrupt

• Code Protection

Several oscillator options are also made available to

allow the part to fit the application. The INTOSC option

saves system cost, while the LP crystal option saves

power. A set of configuration bits are used to select

various options (see Register 16-1).

• ID Locations

• In-Circuit Serial Programming™

Preliminary

DS41250E-page 185

PIC16F917/916/914/913

16.1 Configuration Bits

Note:

Address 2007h is beyond the user

program memory space. It belongs to the

special configuration memory space

(2000h-3FFFh), which can be accessed

The configuration bits can be programmed (read as

‘0’), or left unprogrammed (read as ‘1’) to select various

device configurations as shown in Register 16-1.

These bits are mapped in program memory location

2007h.

only

during

programming.

See

“PIC16F917/916/914/913

Memory

Programming Specification” (DS41244)

for more information.

REGISTER 16-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)

—

DEBUG

FCMEN

IESO

BOREN1 BOREN0

CPD

CP

MCLRE PWRTE

WDTE

FOSC2

FOSC1

FOSC0

bit 0

bit 13

bit 12

Unimplemented: Read as ‘1’

DEBUG: In-Circuit Debugger Mode bit

1= In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins

0= In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger

bit 11

bit 10

bit 9-8

FCMEN: Fail-Safe Clock Monitor Enabled bit

1= Fail-Safe Clock Monitor is enabled

0= Fail-Safe Clock Monitor is disabled

IESO: Internal External Switchover bit

1= Internal External Switchover mode is enabled

0= Internal External Switchover mode is disabled

BOREN<1:0>: Brown-out Reset Selection bits⁽¹⁾

11= BOR enabled

10= BOR enabled during operation and disabled in Sleep

01= BOR controlled by SBOREN bit (PCON<4>)

00= BOR disabled

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-0

CPD: Data Code Protection bit⁽²⁾

1= Data memory code protection is disabled

0= Data memory code protection is enabled

CP: Code Protection bit⁽³⁾

1= Program memory code protection is disabled

0= Program memory code protection is enabled

MCLRE: RB3/MCLR/VPP pin function select bit⁽⁴⁾

1= RB3/MCLR/VPP pin function is MCLR

0= RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD

PWRTE: Power-up Timer Enable bit

1= PWRT disabled

0= PWRT enabled

WDTE: Watchdog Timer Enable bit

1= WDT enabled

0= WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)

FOSC<2:0>: Oscillator Selection bits

111= RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI

110= RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI

101= INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI

100= INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI

011= EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI

010= HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

001= XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

000= LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI

Note 1: Enabling Brown-out Reset does not automatically enable Power-up Timer.

2: The entire data EEPROM will be erased when the code protection is turned off.

3: The entire program memory will be erased when the code protection is turned off.

4: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

- n = Value at POR

x = Bit is unknown

DS41250E-page 186

Preliminary

PIC16F917/916/914/913

They are not affected by a WDT wake-up since this is

viewed as the resumption of normal operation. TO and

PD bits are set or cleared differently in different Reset

situations, as indicated in Table 16-2. These bits are

used in software to determine the nature of the Reset.

See Table 16-5 for a full description of Reset states of

all registers.

16.2 Reset

The PIC16F917/916/914/913 differentiates between

various kinds of Reset:

a) Power-on Reset (POR)

b) WDT Reset during normal operation

c) WDT Reset during Sleep

A simplified block diagram of the On-Chip Reset Circuit

is shown in Figure 16-1.

d) MCLR Reset during normal operation

e) MCLR Reset during Sleep

f) Brown-out Reset (BOR)

The MCLR Reset path has a noise filter to detect and

ignore small pulses. See Section 19.0 “Electrical

Specifications” for pulse width specifications.

Some registers are not affected in any Reset condition;

their status is unknown on POR and unchanged in any

other Reset. Most other registers are reset to a “Reset

state” on:

• Power-on Reset

• MCLR Reset

• MCLR Reset during Sleep

• WDT Reset

• Brown-out Reset (BOR)

FIGURE 16-1:

SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP pin

SLEEP

WDT

Module

Time-out

Reset

VDD Rise

Detect

Power-on Reset

VDD

Brown-out⁽¹⁾

Reset

BOREN

SBOREN

S

OST/PWRT

OST

10-bit Ripple Counter

Chip_Reset

R

Q

OSC1/

CLKI pin

PWRT

11-bit Ripple Counter

LFINTOSC

Enable PWRT

Enable OST

Note 1: Refer to the Configuration Word register (Register 16-1).

Preliminary

DS41250E-page 187

PIC16F917/916/914/913

FIGURE 16-2:

RECOMMENDED MCLR

CIRCUIT

16.3 Power-on Reset

The on-chip POR circuit holds the chip in Reset until

VDD has reached a high enough level for proper

operation. To take advantage of the POR, simply

connect the MCLR pin through a resistor to VDD. This

will eliminate external RC components usually needed

to create Power-on Reset. A maximum rise time for

VDD is required. See Section 19.0 “Electrical Specifi-

cations” for details. If the BOR is enabled, the maxi-

mum rise time specification does not apply. The BOR

circuitry will keep the device in Reset until VDD reaches

VBOR (see Section 16.3.3 “Brown-Out Reset

(BOR)”).

VDD

R1

PIC16F917/916/

914/913

1 kΩ (or greater)

MCLR

C1

0.1 μF

(optional, not critical)

Note:

The POR circuit does not produce an

internal Reset when VDD declines. To

re-enable the POR, VDD must reach Vss

for a minimum of 100 μs.

16.3.2

POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 64 ms (nominal)

time-out on power-up only, from POR or Brown-out

Reset. The Power-up Timer operates from the 31 kHz

LFINTOSC oscillator. For more information, see

Section 4.4 “Internal Clock Modes”. The chip is kept

in Reset as long as PWRT is active. The PWRT delay

allows the VDD to rise to an acceptable level. A config-

uration bit, PWRTE, can disable (if set) or enable (if

cleared or programmed) the Power-up Timer. The

Power-up Timer should be enabled when Brown-out

Reset is enabled, although it is not required.

When the device starts normal operation (exits the

Reset condition), device operating parameters (i.e.,

voltage, frequency, temperature, etc.) must be met to

ensure operation. If these conditions are not met, the

device must be held in Reset until the operating

conditions are met.

For additional information, refer to Application Note

AN607, “Power-up Trouble Shooting” (DS00607).

16.3.1

MCLR

The Power-up Timer delay will vary from chip-to-chip

and vary due to:

PIC16F917/916/914/913 has a noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

• VDD variation

• Temperature variation

• Process variation

It should be noted that a WDT Reset does not drive

MCLR pin low.

See DC parameters for details (Section 19.0

“Electrical Specifications”).

The behavior of the ESD protection on the MCLR pin

has been altered from early devices of this family.

Voltages applied to the pin that exceed its specification

can result in both MCLR Resets and excessive current

beyond the device specification during the ESD event.

For this reason, Microchip recommends that the MCLR

pin no longer be tied directly to VDD. The use of an RC

network, as shown in Figure 16-2, is suggested.

An internal MCLR option is enabled by clearing the

MCLRE bit in the Configuration Word register. When

cleared, MCLR is internally tied to VDD and an internal

weak pull-up is enabled for the MCLR pin. In-Circuit

Serial Programming is not affected by selecting the

internal MCLR option.

DS41250E-page 188

Preliminary

PIC16F917/916/914/913

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-up Timer will execute a

64 ms Reset.

16.3.3

BROWN-OUT RESET (BOR)

The BOREN0 and BOREN1 bits in the Configuration

Word register selects one of four BOR modes. Two

modes have been added to allow software or hardware

control of the BOR enable. When BOREN<1:0> = 01,

the SBOREN bit (PCON<4>) enables/disables the

BOR allowing it to be controlled in software. By select-

ing BOREN<1:0>, the BOR is automatically disabled in

Sleep to conserve power and enabled on wake-up. In

this mode, the SBOREN bit is disabled. See

Register 16-1 for the configuration word definition.

16.3.4

BOR CALIBRATION

The PIC16F917/916/914/913 stores the BOR calibra-

tion values in fuses located in the Calibration Word

(2008h). The Calibration Word is not erased when

using the specified bulk erase sequence in the

“PIC16F917/916/914/913

Memory

Programming

If VDD falls below VBOR for greater than parameter

(TBOR) (see Section 19.0 “Electrical Specifica-

tions”), the Brown-out situation will reset the device.

This will occur regardless of VDD slew rate. A Reset is

not insured to occur if VDD falls below VBOR for less

than parameter (TBOR).

Specification” (DS41244) and thus, does not require

reprogramming.

Address 2008h is beyond the user program memory

space. It belongs to the special configuration memory

space (2000h-3FFFh), which can be accessed only

during programming. See “PIC16F917/916/914/913

Memory

On any Reset (Power-on, Brown-out Reset, Watchdog

Timer, etc.), the chip will remain in Reset until VDD rises

above VBOR (see Figure 16-3). The Power-up Timer

will now be invoked, if enabled and will keep the chip in

Reset an additional 64 ms.

Programming Specification” (DS41244) for more

information.

Note:

The Power-up Timer is enabled by the

PWRTE bit in the Configuration Word.

FIGURE 16-3:

BROWN-OUT SITUATIONS

VDD

VBOR

Internal

Reset

(1)

64 ms

VDD

VBOR

Internal

Reset

< 64 ms

(1)

64 ms

VDD

VBOR

Internal

Reset

(1)

64 ms

Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.

Preliminary

DS41250E-page 189

PIC16F917/916/914/913

16.3.5

TIME-OUT SEQUENCE

16.3.6

POWER CONTROL (PCON)

REGISTER

On power-up, the time-out sequence is as follows: first,

PWRT time-out is invoked after POR has expired, then

OST is activated after the PWRT time-out has expired.

The total time-out will vary based on oscillator configu-

ration and PWRTE bit status. For example, in EC mode

with PWRTE bit erased (PWRT disabled), there will be

no time-out at all. Figure 16-4, Figure 16-5 and Figure

16-6 depict time-out sequences. The device can exe-

cute code from the INTOSC while OST is active, by

enabling Two-Speed Start-up or Fail-Safe Monitor (see

Section 4.6.2 “Two-Speed Start-up Sequence” and

Section 4.7 “Fail-Safe Clock Monitor”).

The Power Control (PCON) register (address 8Eh) has

two Status bits to indicate what type of Reset that last

occurred.

Bit 0 is BOR (Brown-out Reset). BOR is unknown on

Power-on Reset. It must then be set by the user and

checked on subsequent Resets to see if BOR = 0,

indicating that a Brown-out has occurred. The BOR

Status bit is a “don’t care” and is not necessarily

predictable if the brown-out circuit is disabled

(BOREN<1:0> = 00in the Configuration Word register).

Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on

Reset and unaffected otherwise. The user must write a

‘1’ to this bit following a Power-on Reset. On a

subsequent Reset, if POR is ‘0’, it will indicate that a

Power-on Reset has occurred (i.e., VDD may have

gone too low).

Since the time-outs occur from the POR pulse, if MCLR

is kept low long enough, the time-outs will expire. Then,

bringing MCLR high will begin execution immediately

(see Figure 16-5). This is useful for testing purposes or

to synchronize more than one PIC16F917/916/914/913

device operating in parallel.

For more information, see Section 16.3.3 “Brown-Out

Reset (BOR)”.

Table 16-5 shows the Reset conditions for some

special registers, while Table 16-5 shows the Reset

conditions for all the registers.

TABLE 16-1: TIME-OUT IN VARIOUS SITUATIONS

Power-up

Brown-out Reset

Wake-up from

Oscillator Configuration

Sleep

PWRTE = 0

PWRTE = 1

PWRTE = 0

PWRTE = 1

XT, HS, LP⁽¹⁾

TPWRT + 1024 •

TOSC

1024 • TOSC

TPWRT + 1024 •

TOSC

1024 • TOSC

—

RC, EC, INTOSC

TPWRT

—

TPWRT

—

Note 1: LP mode with T1OSC disabled.

TABLE 16-2: PCON BITS AND THEIR SIGNIFICANCE

POR

BOR

TO

PD

Condition

0

1

u

0

u

1

0

1

u

0

Power-on Reset

Brown-out Reset

WDT Reset

WDT Wake-up

u

1

u

0

MCLR Reset during normal operation

MCLR Reset during Sleep

Legend: u= unchanged, x= unknown

TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Value on

all other

Resets

Value on

POR, BOR

Address Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(1)

03h

STATUS

PCON

IRP

—

RP1

—

RPO

—

TO

PD

—

Z

DC

C

0001 1xxx 000q quuu

--01 --qq --0u --uu

8Eh

SBOREN

—

POR

BOR

Legend:

u= unchanged, x= unknown, -= unimplemented bit, reads as ‘0’, q= value depends on condition. Shaded cells are

not used by BOR.

Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.

DS41250E-page 190

Preliminary

PIC16F917/916/914/913

FIGURE 16-4:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 16-5:

TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

FIGURE 16-6:

TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD): CASE 3

VDD

MCLR

Internal POR

TPWRT

PWRT Time-out

OST Time-out

Internal Reset

TOST

Preliminary

DS41250E-page 191

PIC16F917/916/914/913

TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS

• Wake-up from Sleep

through interrupt

• MCLR Reset

Power-on

Reset

• WDT Reset

• Brown-out Reset⁽¹⁾

Register

Address

• Wake-up from Sleep

through WDT time-out

W

—

xxxx xxxx

uuuu uuuu

xxxx xxxx

uuuu uuuu

INDF

00h/80h/

100h/180h

TMR0

PCL

01h/101h

xxxx xxxx

0000 0000

uuuu uuuu

0000 0000

uuuu uuuu

PC + 1⁽³⁾

02h/82h/

102h/182h

STATUS

FSR

03h/83h/

103h/183h

0001 1xxx

xxxx xxxx

000q quuu⁽⁴⁾

uuuu uuuu

uuuq quuu⁽⁴⁾

uuuu uuuu

04h/84h/

104h/184h

PORTA

PORTB

PORTC

PORTD

PORTE

PCLATH

05h

06h/106h

07h

xxxx xxxx

---- xxxx

---0 0000

0000 0000

---- 0000

---0 0000

uuuu uuuu

---- uuuu

---u uuuu

08h

09h

0Ah/8Ah/

10Ah/18Ah

INTCON

0Bh/8Bh/

0000 000x

uuuu uuuu⁽²⁾

10Bh/18Bh

PIR1

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Dh

1Eh

0000 0000

0000 -0-0

xxxx xxxx

0000 0000

01-0 0-00

-000 0000

xxxx xxxx

0000 0000

0000 0010

000x 000x

---0 1000

0000 0000

--00 0000

xxxx xxxx

0000 0000

0000 -0-0

uuuu uuuu

01-0 0-00

-000 0000

xxxx xxxx

0000 0000

0000 0010

000x 000x

---0 1000

0000 0000

--00 0000

uuuu uuuu

uuuu uuuu⁽²⁾

uuuu -u-u

uuuu uuuu

uu-u u-uu

-uuu uuuu

uuuu uuuu

---u uuuu

uuuu uuuu

--uu uuuu

uuuu uuuu

PIR2

TMR1L

TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA

TXREG

RCREG

CCP2CON

ADRESH

Legend: u= unchanged, x= unknown, ^-= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 16-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

DS41250E-page 192

Preliminary

PIC16F917/916/914/913

TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

• Wake-up from Sleep

through interrupt

• MCLR Reset

Power-on

Reset

• WDT Reset

• Brown-out Reset⁽¹⁾

Register

Address

• Wake-up from Sleep

through WDT time-out

ADCON0

1Fh

0000 0000

1111 1111

0000 0000

--01 --0x

-110 q000

---0 0000

1111 1111

0000 0000

1111 1111

0000 ----

---- --10

0000 -010

0000 0000

0-0- 0000

xxxx xxxx

-000 ----

---0 1000

0001 0011

0000 0000

--00 -100

0000 0000

--00 0000

---0 0000

xxxx xxxx

0000 0000

1111 1111

0000 0000

uuuu uuuu

--uu --uu

-uuu uuuu

---u uuuu

uuuu uuuu

1111 1111

uuuu uuuu

uuuu ----

---- --uu

uuuu -uuu

uuuu uuuu

u-u- uuuu

uuuu uuuu

-uuu ----

---u uuuu

uuuu uuuu

--uu -uuu

uuuu uuuu

OPTION_REG 81h/181h

TRISA

85h

86h/186h

87h

TRISB

TRISC

TRISD

88h

TRISE

89h

PIE1

8Ch

8Dh

8Eh

PIE2

PCON

--0u --uu^(1,5)

OSCCON

OSCTUNE

ANSEL

8Fh

-110 x000

---u uuuu

1111 1111

0000 0000

1111 1111

0000 ----

---- --10

0000 -010

0000 0000

0-0- 0000

uuuu uuuu

-000 ----

---0 1000

0001 0011

0000 0000

--00 -100

0000 0000

uuuu uuuu

90h

91h

PR2

92h

SSPADD

SSPSTAT

WPUB

93h

94h

95h

IOCB

96h

CMCON1

TXSTA

97h

98h

SPBRG

CMCON0

VRCON

ADRESL

ADCON1

WDTCON

LCDCON

LCDPS

99h

9Ch

9Dh

9Eh

9Fh

105h

107h

108h

109h

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

LVDCON

EEDATL

EEADRL

EEDATH

EEADRH

LCDDATA0

LCDDATA1

LCDDATA2

Legend: u= unchanged, x= unknown, ^-= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 16-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

Preliminary

DS41250E-page 193

PIC16F917/916/914/913

TABLE 16-4: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED)

• Wake-up from Sleep

through interrupt

• MCLR Reset

Power-on

Reset

• WDT Reset

• Brown-out Reset⁽¹⁾

Register

Address

• Wake-up from Sleep

through WDT time-out

LCDDATA3

LCDDATA4

LCDDATA5

LCDDATA6

LCDDATA7

LCDDATA8

LCDDATA9

LCDDATA10

LCDDATA11

LCDSE0

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

18Ch

xxxx xxxx

0000 0000

x--- x000

uuuu uuuu

u--- q000

uuuu uuuu

u--- uuuu

LCDSE1

LCDSE2

EECON1

Legend: u= unchanged, x= unknown, ^-= unimplemented bit, reads as ‘0’, q= value depends on condition.

Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.

2: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt

vector (0004h).

4: See Table 16-5 for Reset value for specific condition.

5: If Reset was due to brown-out, then bit 0 = 0. All other Resets will cause bit 0 = u.

TABLE 16-5: INITIALIZATION CONDITION FOR SPECIAL REGISTERS

Program

Counter

Status

Register

PCON

Register

Condition

Power-on Reset

000h

0001 1xxx

000u uuuu

--01 --0x

--0u --uu

MCLR Reset during normal operation

MCLR Reset during Sleep

WDT Reset

000h

0001 0uuu

0000 uuuu

uuu0 0uuu

0001 1uuu

uuu1 0uuu

--0u --uu

--uu --uu

--01 --10

--uu --uu

WDT Wake-up

PC + 1

Brown-out Reset

000h

PC + 1⁽¹⁾

Interrupt Wake-up from Sleep

Legend: u= unchanged, x= unknown, ^-= unimplemented bit, reads as ‘0’.

Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit, GIE, is set, the PC is loaded with

the interrupt vector (0004h) after execution of PC + 1.

DS41250E-page 194

Preliminary

PIC16F917/916/914/913

The following interrupt flags are contained in the PIR2

register:

16.4 Interrupts

The PIC16F917/916/914/913 has multiple sources of

interrupt:

• Fail-Safe Clock Monitor Interrupt

• Comparator 1 and 2 Interrupts

• LCD Interrupt

• External Interrupt RB0/INT/SEG0

• TMR0 Overflow Interrupt

• PORTB Change Interrupts

• 2 Comparator Interrupts

• A/D Interrupt

• PLVD Interrupt

• CCP2 Interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

• Timer1 Overflow Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• LCD Interrupt

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 16-8). The latency is the same for one or

two-cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

• PLVD Interrupt

• USART Receive and Transmit interrupts

• CCP1 and CCP2 Interrupts

• TMR2 Interrupt

The Interrupt Control (INTCON) register and Peripheral

Interrupt Request 1 (PIR1) register record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared) all interrupts. Individual interrupts can be

disabled through their corresponding enable bits in the

INTCON register and PIE1 register. GIE is cleared on

Reset.

Note 1: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

The following interrupt flags are contained in the

INTCON register:

For additional information on Timer1, A/D or data

EEPROM modules, refer to the respective peripheral

section.

• INT Pin Interrupt

• PORTB Change Interrupt

• TMR0 Overflow Interrupt

Note:

The ANSEL (91h) and CMCON0 (9Ch)

registers must be initialized to configure

an analog channel as a digital input. Pins

configured as analog inputs will read ‘0’.

Also, if a LCD output function is active on

an external interrupt pin, that interrupt

function will be disabled.

The peripheral interrupt flags are contained in the special

registers, PIR1 and PIR2. The corresponding interrupt

enable bit are contained in the special registers, PIE1

and PIE2.

The following interrupt flags are contained in the PIR1

register:

• EEPROM Data Write Interrupt

• A/D Interrupt

• USART Receive and Transmit Interrupts

• Timer1 Overflow Interrupt

• CCP1 Interrupt

• SSP Interrupt

Preliminary

DS41250E-page 195

PIC16F917/916/914/913

16.4.1

RB0/INT/SEG0 INTERRUPT

16.4.2

TMR0 INTERRUPT

External interrupt on RB0/INT/SEG0 pin is edge-trig-

gered; either rising if the INTEDG bit (OPTION<6>) is

set, or falling, if the INTEDG bit is clear. When a valid

edge appears on the RB0/INT/SEG0 pin, the INTF bit

(INTCON<1>) is set. This interrupt can be disabled by

clearing the INTE control bit (INTCON<4>). The INTF

bit must be cleared in software in the Interrupt Service

Routine before re-enabling this interrupt. The

RB0/INT/SEG0 interrupt can wake-up the processor

from Sleep if the INTE bit was set prior to going into

Sleep. The status of the GIE bit decides whether or not

the processor branches to the interrupt vector following

wake-up (0004h). See Section 16.7 “Power-Down

Mode (Sleep)” for details on Sleep and Figure 16-10

for timing of wake-up from Sleep through

RB0/INT/SEG0 interrupt.

An overflow (FFh → 00h) in the TMR0 register will set

the T0IF (INTCON<2>) bit. The interrupt can be

enabled/disabled

by

setting/clearing

T0IE

(INTCON<5>) bit. See Section 5.0 “Timer0 Module”

for operation of the Timer0 module.

16.4.3

An input change on PORTB change sets the RBIF

(INTCON<0>) bit. The interrupt can be

PORTB INTERRUPT

enabled/disabled by setting/clearing the RBIE

(INTCON<3>) bit. Plus, individual pins can be config-

ured through the IOCB register.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set.

FIGURE 16-7:

INTERRUPT LOGIC

IOC-RB4

IOCB4

IOC-RB5

IOCB5

IOC-RB6

IOCB6

IOC-RB7

IOCB7

TMR0IF

TMR0IE

Wake-up (If in Sleep mode)

Interrupt to CPU

TMR2IF

TMR2IE

INTF

INTE

RBIF

RBIE

TMR1IF

TMR1IE

C1IF

C1IE

PEIF

PEIE

C2IF

C2IE

ADIF

ADIE

GIE

OSFIF

OSFIE

EEIF

EEIE

CCP1IF

CCP1IE

CCP2IF

CCP2IE

*

RCIF

RCIE

TXIF

TXIE

SSPIF

SSPIE

LCDIF

LCDIE

LVDIF

LVDIE

* Only available on the PIC16F914/917.

DS41250E-page 196

Preliminary

PIC16F917/916/914/913

FIGURE 16-8:

INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

(3)

CLKO

(4)

INT pin

(1)

(2)

(5)

Interrupt Latency

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

PC

0004h

PC + 1

—

0005h

PC

Instruction

Fetched

Inst (PC)

Inst (PC + 1)

Inst (0004h)

Inst (0005h)

Inst (0004h)

Instruction

Executed

Dummy Cycle

Inst (PC)

Inst (PC - 1)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKO is available only in INTOSC and RC Oscillator modes.

4: For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.

5: INTF is enabled to be set any time during the Q4-Q1 cycles.

TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS

Value on

all other

Resets

Value on

POR, BOR

Addr Name

Bit 7 Bit 6 Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh, INTCON GIE

8Bh

PEIE T0IE INTE RBIE

T0IF

INTF

RBIF

0000 000x 0000 000x

0Ch

0Dh

8Ch

8Dh

PIR1

PIR2

PIE1

PIE2

EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

OSFIF C2IF C1IF LCDIF LVDIF CCP2IF 0000 -0-0 0000 -0-0

EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

OSFIE C2IE C1IE LCDIE LVDIE CCP2IE 0000 -0-0 0000 -0-0

—

Legend: x= unknown, u= unchanged, ^-= unimplemented read as ‘0’, q= value depends upon condition.

Shaded cells are not used by the interrupt module.

Preliminary

DS41250E-page 197

PIC16F917/916/914/913

16.5 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key

registers during an interrupt (e.g., W and Status

registers). This must be implemented in software.

Since the lower 16 bytes of all banks are common in the

PIC16F917/916/914/913 (see Figure 2-3), temporary

holding registers, W_TEMP and STATUS_TEMP,

should be placed in here. These 16 locations do not

require banking and therefore, make it easier to context

save and restore. The same code shown in

Example 16-1 can be used to:

• Store the W register

• Store the Status register

• Execute the ISR code

• Restore the Status (and Bank Select Bit register)

• Restore the W register

Note:

The PIC16F917/916/914/913 normally

does not require saving the PCLATH.

However, if computed GOTO’s are used in

the ISR and the main code, the PCLATH

must be saved and restored in the ISR.

EXAMPLE 16-1:

SAVING STATUS AND W REGISTERS IN RAM

MOVWF

SWAPF

CLRF

MOVWF

:

W_TEMP

STATUS,W

STATUS

;Copy W to TEMP register

;Swap status to be saved into W

;bank 0, regardless of current bank, Clears IRP,RP1,RP0

;Save status to bank zero STATUS_TEMP register

STATUS_TEMP

:(ISR)

:

;Insert user code here

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

;Move W into Status register

;Swap W_TEMP

MOVWF

SWAPF

STATUS

W_TEMP,F

W_TEMP,W

;Swap W_TEMP into W

DS41250E-page 198

Preliminary

PIC16F917/916/914/913

A new prescaler has been added to the path between

the INTOSC and the multiplexers used to select the

path for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTOSC by 32 to 65536,

giving the WDT a nominal range of 1 ms to 268s.

16.6 Watchdog Timer (WDT)

For PIC16F917/916/914/913, the WDT has been mod-

ified from previous PIC16F devices. The new WDT is

code and functionally compatible with previous PIC16F

WDT modules and adds a 16-bit prescaler to the WDT.

This allows the user to have a scaled value for the WDT

and TMR0 at the same time. In addition, the WDT

time-out value can be extended to 268 seconds. WDT

is cleared under certain conditions described in

Table 16-7.

16.6.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

register. When set, the WDT runs continuously.

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit (WDTCON<0>) has no effect.

If WDTE is clear, then the SWDTEN bit can be used to

enable and disable the WDT. Setting the bit will enable

it and clearing the bit will disable it.

16.6.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled.

The PSA and PS<2:0> bits (OPTION_REG) have the

same function as in previous versions of the PIC16F

family of microcontrollers. See Section 5.0 “Timer0

Module” for more information.

The value of WDTCON is ‘---0 1000’on all Resets.

This gives a nominal time base of 16 ms, which is

compatible with the time base generated with previous

PIC16F microcontroller versions.

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

FIGURE 16-9:

WATCHDOG TIMER BLOCK DIAGRAM

0

1

From TMR0 Clock Source

Prescaler⁽¹⁾

16-bit WDT Prescaler

8

PSA

PS<2:0>

To TMR0

31 kHz

LFINTOSC Clock

WDTPS<3:0>

1

0

PSA

WDTE from Configuration Word register

SWDTEN from WDTCON

WDT Time-out

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.4 “Prescaler” for more information.

TABLE 16-7: WDT STATUS

Conditions

WDT

WDTE = 0

CLRWDTCommand

Oscillator Fail Detected

Cleared

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

Preliminary

DS41250E-page 199

PIC16F917/916/914/913

REGISTER 16-2: WDTCON – WATCHDOG TIMER CONTROL REGISTER (ADDRESS: 105h)

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

R/W-0

WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN

bit 0

bit 7

bit 7-5

bit 4-1

Unimplemented: Read as ‘0’

WDTPS<3:0>: Watchdog Timer Period Select bits

Bit Value = Prescale Rate

0000 = 1:32

0001 = 1:64

0010 = 1:128

0011 = 1:256

0100 = 1:512 (Reset value)

0101 = 1:1024

0110 = 1:2048

0111 = 1:4096

1000 = 1:8192

1001 = 1:16384

1010 = 1:32768

1011 = 1:65536

1100 = reserved

1101 = reserved

1110 = reserved

1111 = reserved

bit 0

SWDTEN: Software Enable or Disable the Watchdog Timer bit⁽¹⁾

1= WDT is turned on

0= WDT is turned off (Reset value)

Note 1: If WDTE configuration bit = 1, then WDT is always enabled, irrespective of this

control bit. If WDTE configuration bit = 0, then it is possible to turn WDT on/off with

this control bit.

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

TABLE 16-8: SUMMARY OF WATCHDOG TIMER REGISTERS

Address

105h

Name

WDTCON

OPTION_REG

Bit 7

Bit 6

Bit 5

—

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

—

WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN

81h

RBPU INTEDG

CPD CP

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 16-1 for operation of all Configuration Word register bits.

T0CS

T0SE

PSA

PS2

PS1

PS0

2007h⁽¹⁾CONFIG

MCLRE PWRTE

WDTE

FOSC2 FOSC1 FOSC0

DS41250E-page 200

Preliminary

PIC16F917/916/914/913

The following peripheral interrupts can wake the device

from Sleep:

16.7 Power-Down Mode (Sleep)

The Power-down mode is entered by executing a

SLEEPinstruction.

1. TMR1 Interrupt. Timer1 must be operating as an

asynchronous counter.

If the Watchdog Timer is enabled:

2. EUSART Receive Interrupt

• WDT will be cleared but keeps running.

• PD bit in the Status register is cleared.

• TO bit is set.

3. A/D conversion (when A/D clock source is RC)

4. EEPROM write operation completion

5. Comparator output changes state

6. Interrupt-on-change

• Oscillator driver is turned off.

• I/O ports maintain the status they had before

SLEEPwas executed (driving high, low or

high-impedance).

7. External Interrupt from INT pin

8. PLVD Interrupt

9. LCD Interrupt (if running during Sleep)

For lowest current consumption in this mode, all I/O

pins should be either at VDD or VSS, with no external

circuitry drawing current from the I/O pin, and the

comparators and CVREF should be disabled. I/O pins

that are high-impedance inputs should be pulled high

or low externally to avoid switching currents caused by

floating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The

contribution from on-chip pull-ups on PORTB should be

considered.

Other peripherals cannot generate interrupts since

during Sleep, no on-chip clocks are present.

When the SLEEPinstruction is being executed, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEPinstruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction, then branches to the interrupt

address (0004h). In cases where the execution of the

instruction following SLEEP is not desirable, the user

should have a NOPafter the SLEEPinstruction.

The MCLR pin must be at a logic high level.

Note:

It should be noted that a Reset generated

by a WDT time-out does not drive MCLR

pin low.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt flag bits set, the device will

immediately wake-up from Sleep. The

SLEEPinstruction is completely executed.

16.7.1

WAKE-UP FROM SLEEP

The device can wake-up from Sleep through one of the

following events:

1. External Reset input on MCLR pin.

2. Watchdog Timer wake-up (if WDT was

enabled).

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

3. Interrupt from RB0/INT/SEG0 pin, PORTB

change or a peripheral interrupt.

16.7.2

WAKE-UP USING INTERRUPTS

The first event will cause a device Reset. The two latter

events are considered a continuation of program

execution. The TO and PD bits in the Status register

can be used to determine the cause of device Reset.

The PD bit, which is set on power-up, is cleared when

Sleep is invoked. TO bit is cleared if WDT wake-up

occurred.

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a

SLEEPinstruction, the SLEEPinstruction will

complete as a NOP. Therefore, the WDT and WDT

prescaler and postscaler (if enabled) will not be

cleared, the TO bit will not be set and the PD bit

will not be cleared.

• If the interrupt occurs during or after the

execution of a SLEEPinstruction, the device will

immediately wake-up from Sleep. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT prescaler

and postscaler (if enabled) will be cleared, the TO

bit will be set and the PD bit will be cleared.

Preliminary

DS41250E-page 201

PIC16F917/916/914/913

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEPinstruction completes. To

determine whether a SLEEPinstruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDTinstruction

should be executed before a SLEEPinstruction.

FIGURE 16-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1⁽¹⁾

CLKO⁽⁴⁾

INT pin

(2)

TOST

INTF flag

(INTCON<1>)

Interrupt Latency⁽³⁾

GIE bit

(INTCON<7>)

Processor in

Sleep

Instruction Flow

PC

PC + 1

PC + 2

0004h

0005h

Instruction

Fetched

Inst(0004h)

Inst(PC + 1)

Inst(PC + 2)

Inst(0005h)

Inst(PC) = Sleep

Instruction

Executed

Dummy Cycle

Sleep

Inst(PC + 1)

Inst(PC - 1)

Inst(0004h)

Note 1:

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RC Oscillator modes.

GIE = 1assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

2:

3:

4:

CLKO is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

DS41250E-page 202

Preliminary

PIC16F917/916/914/913

A typical In-Circuit Serial Programming connection is

shown in Figure 16-11.

16.8 Code Protection

If the code protection bit(s) have not been

programmed, the on-chip program memory can be

read out using ICSP for verification purposes.

FIGURE 16-11:

TYPICAL IN-CIRCUIT

SERIAL PROGRAMMING

CONNECTION

Note:

The entire data EEPROM and Flash

program memory will be erased when the

code protection is turned off. See the

“PIC16F917/916/914/913 Memory Pro-

gramming Specification” (DS41244) for

more information.

To Normal

Connections

External

Connector

Signals

*

PIC16F917/916/

914/913

VDD

VSS

+5V

0V

16.9 ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are

readable and writable during Program/Verify mode.

Only the Least Significant 7 bits of the ID locations are

used.

RE3/MCLR/VPP

VPP

RB6/ICSPCLK/

ICDCK/SEG14

RB7/ICSPDATA/

ICDDAT/SEG13

CLK

Data I/O

16.10 In-Circuit Serial Programming

*

The PIC16F917/916/914/913 microcontrollers can be

serially programmed while in the end application circuit.

This is simply done with two lines for clock and data

and three other lines for:

To Normal

Connections

* Isolation devices (as required)

• power

• ground

• programming voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The device is placed into a Program/Verify mode by

holding

the

RB7/ICSPDAT/ICDDAT/SEG13

and

RB6/ICSPCLK/ICDCK/SEG14 pins low, while raising the

MCLR (VPP) pin from

“PIC16F917/916/914/913

VIL

Memory

to VIHH. See

Programming

Specification” (DS41244) for more information.

RB7/ICSPDAT/ICDDAT/SEG13 becomes the

programming data and RB6/ICSPCLK/ICDCK/SEG14

becomes

RB7/ICSPDAT/ICDDAT/SEG13

the

programming

clock.

Both

and

RB6/ICSPCLK/ICDCK/SEG14 are Schmitt Trigger inputs

in this mode.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the “PIC16F917/916/914/913 Memory Programming

Specification” (DS41244).

Preliminary

DS41250E-page 203

PIC16F917/916/914/913

For more information, see “Using MPLAB^®ICD 2”

(DS51265), available on Microchip’s web site

(www.microchip.com).

16.11 In-Circuit Debugger

The PIC16F917/916/914/913-ICD can be used in any

of the package types. The device will be mounted on

the target application board, which in turn has a 3 or 4

wire connection to the ICD tool.

16.11.1 ICD PINOUT

The devices in the PIC16F91X family carry the

circuitry for the In-Circuit Debugger on-chip and on

existing device pins. This eliminates the need for a

separate die or package for the ICD device. The pinout

for the ICD device is the same as the devices (see

Section 1.0 “Device Overview” for complete pinout

and pin descriptions). Table 16-9 shows the location

and function of the ICD related pins on the 28 and 40

pin devices.

When the debug bit in the Configuration Word

(CONFIG<12>) is programmed to a ‘0’, the In-Circuit

Debugger functionality is enabled. This function allows

simple debugging functions when used with MPLAB^®

ICD 2. When the microcontroller has this feature

enabled, some of the resources are not available for

general use. See Table 16-9 for more detail.

Note: The user’s application must have the

circuitry

required

to

support

ICD

functionality. Once the ICD circuitry is

enabled, normal device pin functions on

RB6/ICSPCLK/ICDCK/SEG14

and

RB7/ICSPDAT/ICDDAT/SEG13 will not be

usable. The ICD circuitry uses these pins for

communication with the ICD2 external

debugger.

TABLE 16-9: PIC16F917/916/914/913-ICD PIN DESCRIPTIONS

Pin (PDIP)

Name

Type Pull-up

Description

PIC16F914/917 PIC16F913/916

40

39

28

27

ICDDATA

ICDCLK

MCLR/VPP

VDD

TTL

ST

HV

P

—

In Circuit Debugger Bidirectional data

In Circuit Debugger Bidirectional clock

Programming voltage

1

11,32

12,31

20

8,19

VSS

P

Legend: TTL = TTL input buffer, ST = Schmitt Trigger input buffer, P = Power, HV = High Voltage

DS41250E-page 204

Preliminary

PIC16F917/916/914/913

17.1 READ-MODIFY-WRITE

OPERATIONS

17.0 INSTRUCTION SET SUMMARY

The PIC16F917/916/914/913 instruction set is highly

orthogonal and is comprised of three basic categories:

Any instruction that specifies a file register as part of

the instruction performs a Read-Modify-Write (R-M-W)

operation. The register is read, the data is modified,

and the result is stored according to either the instruc-

tion, or the destination designator ‘d’. A read operation

is performed on a register even if the instruction writes

to that register.

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations

Each PIC16 instruction is a 14-bit word divided into an

opcode, which specifies the instruction type and one or

more operands, which further specify the operation of

the instruction. The formats for each of the categories

is presented in Figure 17-1, while the various opcode

fields are summarized in Table 17-1.

For example, a CLRF GPIOinstruction will read GPIO,

clear all the data bits, then write the result back to

GPIO. This example would have the unintended result

of clearing the condition that set the GPIF flag.

Table 17-2 lists the instructions recognized by the

MPASM^TMassembler. A complete description of each

instruction is also available in the “PICmicro^®

Mid-Range MCU Family Reference Manual”

(DS33023).

TABLE 17-1: OPCODE FIELD

DESCRIPTIONS

Field

Description

f

W

b

k

x

Register file address (0x00 to 0x7F)

Working register (accumulator)

For byte-oriented instructions, ‘f’ represents a file

register designator and ‘d’ represents a destination

designator. The file register designator specifies which

file register is to be used by the instruction.

Bit address within an 8-bit file register

Literal field, constant data or label

The destination designator specifies where the result of

the operation is to be placed. If ‘d’ is zero, the result is

placed in the W register. If ‘d’ is one, the result is placed

in the file register specified in the instruction.

Don’t care location (= 0or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip software tools.

For bit-oriented instructions, ‘b’ represents a bit field

designator, which selects the bit affected by the

operation, while ‘f’ represents the address of the file in

which the bit is located.

d

Destination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1.

PC

TO

PD

Program Counter

Time-out bit

For literal and control operations, ‘k’ represents an

8-bit or 11-bit constant, or literal value.

Power-down bit

One instruction cycle consists of four oscillator periods;

for an oscillator frequency of 4 MHz, this gives a normal

instruction execution time of 1 μs. All instructions are

executed within a single instruction cycle, unless a

conditional test is true, or the program counter is

changed as a result of an instruction. When this occurs,

the execution takes two instruction cycles, with the

second cycle executed as a NOP.

Note: To maintain upward compatibility with

future products, do not use the OPTION

and TRISinstructions.

All instruction examples use the format ‘0xhh’ to

represent a hexadecimal number, where ‘h’ signifies a

hexadecimal digit.

Preliminary

DS41250E-page 205

PIC16F917/916/914/913

FIGURE 17-1:

GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13

8

7

6

0

OPCODE

d

f (FILE #)

d = 0for destination W

d = 1for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9

b (BIT #)

7

6

0

OPCODE

f (FILE #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

General

13

8

7

0

OPCODE

k (literal)

k = 8-bit immediate value

CALLand GOTOinstructions only

13 11 10

OPCODE

k = 11-bit immediate value

k (literal)

DS41250E-page 206

Preliminary

PIC16F917/916/914/913

TABLE 17-2: PIC16F917/916/914/913 INSTRUCTION SET

14-Bit Opcode

Mnemonic,

Operands

Status

Affected

Description

Cycles

Notes

MSb

LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

f, d

f

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

1

1(2)

1

1(2)

1

00 0111 dfff ffff C,DC,Z

1, 2

2

00 0101 dfff ffff

00 0001 lfff ffff

00 0001 0xxx xxxx

00 1001 dfff ffff

00 0011 dfff ffff

00 1011 dfff ffff

00 1010 dfff ffff

00 1111 dfff ffff

00 0100 dfff ffff

00 1000 dfff ffff

00 0000 lfff ffff

00 0000 0xx0 0000

00 1101 dfff ffff

00 1100 dfff ffff

Z

-

f, d

f

1, 2

1, 2, 3

1, 2

1, 2, 3

1, 2

Z

Move W to f

No Operation

-

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

C

1, 2

00 0010 dfff ffff C,DC,Z

00 1110 dfff ffff

00 0110 dfff ffff

Z

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1

1 (2)

01 00bb bfff ffff

1, 2

3

01 01bb bfff ffff

01 10bb bfff ffff

01 11bb bfff ffff

3

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

k

-

k

-

k

-

k

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

1

2

1

2

1

2

1

11 111x kkkk kkkk C,DC,Z

11 1001 kkkk kkkk

10 0kkk kkkk kkkk

00 0000 0110 0100

10 1kkk kkkk kkkk

11 1000 kkkk kkkk

11 00xx kkkk kkkk

00 0000 0000 1001

11 01xx kkkk kkkk

00 0000 0000 1000

00 0000 0110 0011

Z

TO,PD

Z

Inclusive OR literal with W

Move literal to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

TO,PD

11 110x kkkk kkkk C,DC,Z

11 1010 kkkk kkkk

Z

Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external

device, the data will be written back with a ‘0’.

2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle

is executed as a NOP.

Note:

Additional information on the mid-range instruction set is available in the PICmicro^®Mid-Range MCU

Family Reference Manual” (DS33023).

Preliminary

DS41250E-page 207

PIC16F917/916/914/913

17.2 Instruction Descriptions

BCF

Bit Clear f

ADDLW

Add Literal and W

Syntax:

[ label ] BCF f,b

Syntax:

[ label ] ADDLW

0 ≤ k ≤ 255

k

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

Operation:

Status Affected:

Description:

(W) + k → (W)

C, DC, Z

Operation:

0 → (f<b>)

Status Affected:

Description:

None

The contents of the W register

are added to the eight-bit literal ‘k’

and the result is placed in the W

register.

Bit ‘b’ in register ‘f’ is cleared.

BSF

Bit Set f

ADDWF

Add W and f

Syntax:

[ label ] BSF f,b

Syntax:

[ label ] ADDWF f,d

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

1 → (f<b>)

Operation:

(W) + (f) → (destination)

Status Affected:

Description:

None

Status Affected: C, DC, Z

Bit ‘b’ in register ‘f’ is set.

Description:

Add the contents of the W register

with register ‘f’. If ‘d’ is ‘0’, the

result is stored in the W register. If

‘d’ is ‘1’, the result is stored back

in register ‘f’.

ANDLW

AND Literal with W

BTFSC

Bit Test, Skip if Clear

Syntax:

[ label ] ANDLW

0 ≤ k ≤ 255

k

Syntax:

[ label ] BTFSC f,b

Operands:

Operation:

Status Affected:

Description:

Operands:

0 ≤ f ≤ 127

0 ≤ b ≤ 7

(W) .AND. (k) → (W)

Operation:

skip if (f<b>) = 0

Z

Status Affected: None

The contents of W register are

AND’ed with the eight-bit literal

‘k’. The result is placed in the W

register.

Description: If bit ‘b’ in register ‘f’ is ‘1’, the next

instruction is executed.

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is discarded, and a NOP

is executed instead, making this a

two-cycle instruction.

ANDWF

AND W with f

Syntax:

[ label ] ANDWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .AND. (f) → (destination)

Status Affected:

Description:

Z

AND the W register with register

‘f’. If ‘d’ is ‘0’, the result is stored in

the W register. If ‘d’ is ‘1’, the

result is stored back in register ‘f’.

DS41250E-page 208

Preliminary

PIC16F917/916/914/913

BTFSS

Bit Test f, Skip if Set

CLRWDT

Clear Watchdog Timer

Syntax:

[ label ] BTFSS f,b

Syntax:

[ label ] CLRWDT

Operands:

0 ≤ f ≤ 127

0 ≤ b < 7

Operands:

Operation:

None

00h → WDT

0 → WDT prescaler,

1 → TO

Operation:

skip if (f<b>) = 1

Status Affected: None

1 → PD

Description:

If bit ‘b’ in register ‘f’ is ‘0’, the next

instruction is executed.

Status Affected: TO, PD

If bit ‘b’ is ‘1’, then the next

instruction is discarded and a NOP

is executed instead, making this a

two-cycle instruction.

Description:

CLRWDTinstruction resets the

Watchdog Timer. It also resets the

prescaler of the WDT.

Status bits TO and PD are set.

CALL

Call Subroutine

COMF

Complement f

Syntax:

[ label ] CALL k

0 ≤ k ≤ 2047

Syntax:

[ label ] COMF f,d

Operands:

Operation:

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

(PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Operation:

(f) → (destination)

Status Affected:

Description:

Z

Status Affected: None

The contents of register ‘f’ are

complemented. If ‘d’ is ‘0’, the

result is stored in W. If ‘d’ is ‘1’,

the result is stored back in

register ‘f’.

Description:

Call Subroutine. First, return

address (PC + 1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALLis a two-cycle instruction.

DECF

Decrement f

CLRF

Clear f

Syntax:

[ label ] DECF f,d

Syntax:

[ label ] CLRF

0 ≤ f ≤ 127

f

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

00h → (f)

1 → Z

Operation:

(f) - 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Decrement register ‘f’. If ‘d’ is ‘0’,

the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

The contents of register ‘f’ are

cleared and the Z bit is set.

CLRW

Clear W

Syntax:

[ label ] CLRW

Operands:

Operation:

None

00h → (W)

1 → Z

Status Affected:

Description:

Z

W register is cleared. Zero bit (Z)

is set.

Preliminary

DS41250E-page 209

PIC16F917/916/914/913

DECFSZ

Decrement f, Skip if 0

INCFSZ

Increment f, Skip if 0

Syntax:

[ label ] DECFSZ f,d

Syntax:

[ label ] INCFSZ f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f) - 1 → (destination);

skip if result = 0

Operation:

(f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description:

The contents of register ‘f’ are

Description:

The contents of register ‘f’ are

decremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, then a NOPis

executed instead, making it a

two-cycle instruction.

If the result is ‘1’, the next

instruction is executed. If the

result is ‘0’, a NOPis executed

instead, making it a two-cycle

instruction.

GOTO

Go to Address

IORLW

Inclusive OR Literal with W

Syntax:

[ label ] GOTO k

0 ≤ k ≤ 2047

Syntax:

[ label ] IORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Operands:

Operation:

Status Affected:

Description:

k → PC<10:0>

PCLATH<4:3> → PC<12:11>

(W) .OR. k → (W)

Z

Status Affected: None

The contents of the W register are

OR’ed with the eight-bit literal ‘k’.

The result is placed in the W

register.

Description:

GOTOis an unconditional branch.

The eleven-bit immediate value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTOis a

two-cycle instruction.

IORWF

Inclusive OR W with f

INCF

Increment f

Syntax:

[ label ] IORWF f,d

Syntax:

[ label ] INCF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .OR. (f) → (destination)

Operation:

(f) + 1 → (destination)

Status Affected:

Description:

Z

Status Affected:

Description:

Z

Inclusive OR the W register with

register ‘f’. If ‘d’ is ‘0’, the result is

placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

The contents of register ‘f’ are

incremented. If ‘d’ is ‘0’, the result

is placed in the W register. If ‘d’ is

‘1’, the result is placed back in

register ‘f’.

DS41250E-page 210

Preliminary

PIC16F917/916/914/913

MOVF

Move f

MOVWF

Move W to f

[ label ] MOVWF

0 ≤ f ≤ 127

(W) → (f)

Syntax:

Operands:

[ label ] MOVF f,d

Syntax:

f

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

Operation:

Status Affected:

Encoding:

Description:

Operation:

(f) → (dest)

None

Status Affected:

Encoding:

Z

00

0000

1fff

ffff

00

1000

dfff

ffff

Move data from W register to

register ‘f’.

Description:

The contents of register ‘f’ is

moved to a destination dependent

upon the status of ‘d’. If ‘d’ = 0,

destination is W register. If ‘d’ = 1,

the destination is file register ‘f’

itself. ‘d’ = 1is useful to test a file

register since status flag Z is

affected.

Words:

1

Cycles:

Example:

MOVWF

OPTION

Before Instruction

OPTION = 0xFF

W

=

0x4F

Words:

1

After Instruction

OPTION = 0x4F

W

Cycles:

Example:

=

0x4F

MOVF

FSR,

0

After Instruction

W

=

value in FSR

register

Z

=

1

NOP

No Operation

[ label ] NOP

None

MOVLW

Move Literal to W

Syntax:

[ label ] MOVLW k

0 ≤ k ≤ 255

k → (W)

Operands:

Operation:

Status Affected:

Encoding:

Description:

Words:

Operands:

Operation:

Status Affected:

Encoding:

Description:

No operation

None

00

0000

0xx0

0000

11

00xx

kkkk

No operation.

The eight bit literal ‘k’ is loaded

into W register. The “don’t cares”

will assemble as ‘0’s.

1

Cycles:

1

Words:

1

NOP

Example:

Cycles:

Example:

MOVLW

0x5A

After Instruction

W

=

0x5A

Preliminary

DS41250E-page 211

PIC16F917/916/914/913

RETFIE

Return from Interrupt

[ label ] RETFIE

None

RETLW

Return with Literal in W

[ label ] RETLW k

0 ≤ k ≤ 255

Syntax:

Operands:

Operation:

Operands:

Operation:

TOS → PC,

1 → GIE

k → (W);

TOS → PC

Status Affected:

Encoding:

None

Status Affected:

Encoding:

None

00

0000

1001

11

01xx

kkkk

Description:

Return from Interrupt. Stack is

POPed and Top-of-Stack (TOS) is

loaded in the PC. Interrupts are

enabled by setting Global Interrupt

Enable bit, GIE (INTCON<7>).

This is a two-cycle instruction.

Description:

The W register is loaded with the

eight bit literal ‘k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

Words:

1

2

Words:

1

Cycles:

Example:

Cycles:

Example:

2

CALL TABLE ;W contains table

RETFIE

;offset value

•

;W now has table

After Interrupt

PC = TOS

TABLE

value

•

GIE =

1

ADDWF PC ;W = offset

RETLW k1

RETLW k2

;Begin table

;

•

RETLW kn ; End of table

Before Instruction

W

=

0x07

After Instruction

W

=

value of k8

RETURN

Return from Subroutine

Syntax:

[ label ] RETURN

None

Operands:

Operation:

TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed and the top of the stack

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

DS41250E-page 212

Preliminary

PIC16F917/916/914/913

SLEEP

RLF

Rotate Left f through Carry

Syntax:

[ label ] SLEEP

Syntax:

Operands:

[ label ] RLF f,d

Operands:

Operation:

None

0 ≤ f ≤ 127

d ∈ [0,1]

00h → WDT,

0 → WDT prescaler,

1 → TO,

Operation:

See description below

C

Status Affected:

Encoding:

0 → PD

00

1101

dfff

ffff

Status Affected:

Description:

TO, PD

Description:

The contents of register ‘f’ are

rotated one bit to the left through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register. If

‘d’ is ‘1’, the result is stored back in

register ‘f’.

The power-down Status bit, PD is

cleared. Time-out Status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The processor is put into Sleep

mode with the oscillator stopped.

C

Register f

Words:

1

SUBLW

Subtract W from Literal

Cycles:

Example:

Syntax:

[ label ] SUBLW k

0 ≤ k ≤ 255

RLF

REG1,0

Operands:

Operation:

Before Instruction

k - (W) → (W)

REG1

C

=

1110 0110

0

Status Affected: C, DC, Z

After Instruction

Description:

The W register is subtracted (2’s

REG1

W

C

=

1110 0110

1100 1100

1

complement method) from the

eight-bit literal ‘k’. The result is

placed in the W register.

RRF

Rotate Right f through Carry

SUBWF

Subtract W from f

Syntax:

[ label ] RRF f,d

Syntax:

[ label ] SUBWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

See description below

C

Operation:

(f) - (W) → (destination)

Status Affected:

Description:

Status Affected: C, DC, Z

The contents of register ‘f’ are

rotated one bit to the right through

the Carry Flag. If ‘d’ is ‘0’, the

result is placed in the W register.

If ‘d’ is ‘1’, the result is placed

back in register ‘f’.

Description: Subtract (2’s complement method)

W register from register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

C

Register f

Preliminary

DS41250E-page 213

PIC16F917/916/914/913

SWAPF

Swap Nibbles in f

Syntax:

[ label ] SWAPF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected: None

Description:

The upper and lower nibbles of

register ‘f’ are exchanged. If ‘d’ is

‘0’, the result is placed in the W

register. If ‘d’ is ‘1’, the result is

placed in register ‘f’.

XORLW

Exclusive OR Literal with W

Syntax:

[ label ] XORLW k

0 ≤ k ≤ 255

Operands:

Operation:

Status Affected:

Description:

(W) .XOR. k → (W)

Z

The contents of the W register

are XOR’ed with the eight-bit

literal ‘k’. The result is placed in

the W register.

XORWF

Exclusive OR W with f

Syntax:

[ label ] XORWF f,d

Operands:

0 ≤ f ≤ 127

d ∈ [0,1]

Operation:

(W) .XOR. (f) → (destination)

Status Affected:

Description:

Z

Exclusive OR the contents of the

W register with register ‘f’. If ‘d’ is

‘0’, the result is stored in the W

register. If ‘d’ is ‘1’, the result is

stored back in register ‘f’.

DS41250E-page 214

Preliminary

PIC16F917/916/914/913

18.1 MPLAB Integrated Development

Environment Software

18.0 DEVELOPMENT SUPPORT

The PICmicro^®microcontrollers are supported with a

full range of hardware and software development tools:

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows^®

operating system-based application that contains:

• Integrated Development Environment

- MPLAB^®IDE Software

• Assemblers/Compilers/Linkers

- MPASM^TMAssembler

• A single graphical interface to all debugging tools

- Simulator

- MPLAB C18 and MPLAB C30 C Compilers

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

- Programmer (sold separately)

- Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

• Emulators

• Customizable data windows with direct edit of

contents

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

• High-level source code debugging

• Visual device initializer for easy register

initialization

- MPLAB ICD 2

• Mouse over variable inspection

• Device Programmers

- PICSTART^®Plus Development Programmer

• Drag and drop variables from source to watch

windows

- MPLAB PM3 Device Programmer

• Extensive on-line help

• Low-Cost Demonstration and Development

Boards and Evaluation Kits

• Integration of select third party tools, such as

HI-TECH Software C Compilers and IAR

C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either assembly or C)

• One touch assemble (or compile) and download

to PICmicro MCU emulator and simulator tools

(automatically updates all project information)

• Debug using:

- Source files (assembly or C)

- Mixed assembly and C

- Machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost-effective

simulators, through low-cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve when upgrading to tools with increased flexibility

and power.

Preliminary

DS41250E-page 215

PIC16F917/916/914/913

18.2 MPASM Assembler

18.5 MPLAB ASM30 Assembler, Linker

and Librarian

The MPASM Assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

MPLAB ASM30 Assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 C Compiler uses the

assembler to produce its object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatable object files and

archives to create an executable file. Notable features

of the assembler include:

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code and COFF files for

debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• User-defined macros to streamline

assembly code

• Rich directive set

• Conditional assembly for multi-purpose

source files

• Flexible macro language

• MPLAB IDE compatibility

• Directives that allow complete control over the

assembly process

18.6 MPLAB SIM Software Simulator

18.3 MPLAB C18 and MPLAB C30

C Compilers

The MPLAB SIM Software Simulator allows code

development in a PC-hosted environment by simulat-

ing the PICmicro MCUs and dsPIC^®DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, as well as internal

registers.

The MPLAB C18 and MPLAB C30 Code Development

Systems are complete ANSI

C

compilers for

Microchip’s PIC18 family of microcontrollers and

dsPIC30F family of digital signal controllers. These

compilers provide powerful integration capabilities,

superior code optimization and ease of use not found

with other compilers.

For easy source level debugging, the compilers provide

symbol information that is optimized to the MPLAB IDE

debugger.

The MPLAB SIM Software Simulator fully supports

symbolic debugging using the MPLAB C18 and

MPLAB C30 C Compilers, and the MPASM and

MPLAB ASM30 Assemblers. The software simulator

offers the flexibility to develop and debug code outside

of the laboratory environment, making it an excellent,

economical software development tool.

18.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects

from precompiled libraries, using directives from a

linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

DS41250E-page 216

Preliminary

PIC16F917/916/914/913

18.7 MPLAB ICE 2000

High-Performance

18.9 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low-cost, run-time development tool,

connecting to the host PC via an RS-232 or high-speed

USB interface. This tool is based on the Flash PICmicro

MCUs and can be used to develop for these and other

PICmicro MCUs and dsPIC DSCs. The MPLAB ICD 2

utilizes the in-circuit debugging capability built into

the Flash devices. This feature, along with Microchip’s

In-Circuit Serial Programming^TM(ICSP^TM) protocol,

offers cost-effective, in-circuit Flash debugging from the

graphical user interface of the MPLAB Integrated

Development Environment. This enables a designer to

develop and debug source code by setting breakpoints,

single stepping and watching variables, and CPU

status and peripheral registers. Running at full speed

enables testing hardware and applications in real

time. MPLAB ICD 2 also serves as a development

programmer for selected PICmicro devices.

In-Circuit Emulator

The MPLAB ICE 2000 In-Circuit Emulator is intended

to provide the product development engineer with a

complete microcontroller design tool set for PICmicro

microcontrollers. Software control of the MPLAB ICE

2000 In-Circuit Emulator is advanced by the MPLAB

Integrated Development Environment, which allows

editing, building, downloading and source debugging

from a single environment.

The MPLAB ICE 2000 is a full-featured emulator

system with enhanced trace, trigger and data monitor-

ing features. Interchangeable processor modules allow

the system to be easily reconfigured for emulation of

different processors. The architecture of the MPLAB

ICE 2000 In-Circuit Emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft^®Windows^®32-bit operating system were

chosen to best make these features available in a

simple, unified application.

18.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modu-

lar, detachable socket assembly to support various

package types. The ICSP™ cable assembly is included

as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PICmicro devices without a PC connection. It can also

set code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices and incorporates an SD/MMC card for

file storage and secure data applications.

18.8 MPLAB ICE 4000

High-Performance

In-Circuit Emulator

The MPLAB ICE 4000 In-Circuit Emulator is intended to

provide the product development engineer with a

complete microcontroller design tool set for high-end

PICmicro MCUs and dsPIC DSCs. Software control of

the MPLAB ICE 4000 In-Circuit Emulator is provided by

the MPLAB Integrated Development Environment,

which allows editing, building, downloading and source

debugging from a single environment.

The MPLAB ICE 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high-speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanced emulator features include complex triggering

and timing, and up to 2 Mb of emulation memory.

The MPLAB ICE 4000 In-Circuit Emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

Preliminary

DS41250E-page 217

PIC16F917/916/914/913

18.11 PICSTART Plus Development

Programmer

18.12 Demonstration, Development and

Evaluation Boards

The PICSTART Plus Development Programmer is an

easy-to-use, low-cost, prototype programmer. It

connects to the PC via a COM (RS-232) port. MPLAB

Integrated Development Environment software makes

using the programmer simple and efficient. The

PICSTART Plus Development Programmer supports

most PICmicro devices in DIP packages up to 40 pins.

Larger pin count devices, such as the PIC16C92X and

PIC17C76X, may be supported with an adapter socket.

The PICSTART Plus Development Programmer is CE

compliant.

A wide variety of demonstration, development and

evaluation boards for various PICmicro MCUs and dsPIC

DSCs allows quick application development on fully func-

tional systems. Most boards include prototyping areas for

adding custom circuitry and provide application firmware

and source code for examination and modification.

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™ demon-

stration/development board series of circuits, Microchip

has a line of evaluation kits and demonstration software

®

for analog filter design, KEELOQ security ICs, CAN,

IrDA^®, PowerSmart^®battery management, SEEVAL^®

evaluation system, Sigma-Delta ADC, flow rate

sensing, plus many more.

Check the Microchip web page (www.microchip.com)

and the latest “Product Selector Guide” (DS00148) for

the complete list of demonstration, development and

evaluation kits.

DS41250E-page 218

Preliminary

PIC16F917/916/914/913

19.0 ELECTRICAL SPECIFICATIONS

(†)

Absolute Maximum Ratings

Ambient temperature under bias..........................................................................................................-40° to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +6.5V

Voltage on MCLR with respect to Vss ............................................................................................... -0.3V to +13.5V

Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)

Total power dissipation⁽¹⁾............................................................................................................................... 800 mW

Maximum current out of VSS pin ..................................................................................................................... 300 mA

Maximum current into VDD pin ........................................................................................................................ 250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)................................................................................................................ 20 mA

Output clamp current, IOK (Vo < 0 or Vo >VDD).......................................................................................................... 20 mA

Maximum output current sunk by any I/O pin....................................................................................................25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Maximum current sourced by all ports (combined) ......................................................................................... 200 mA

Maximum current sunk by by all ports (combined).......................................................................................... 200 mA

Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL).

2: PORTD and PORTE are not implemented in PIC16F913/916 devices.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

Note:

Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin, rather than

pulling this pin directly to VSS.

Preliminary

DS41250E-page 219

PIC16F917/916/914/913

FIGURE 19-1:

PIC16F917/916/914/913 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +125°C

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

VDD

(Volts)

0

4

8

10

12

16

20

Frequency (MHz)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

DS41250E-page 220

Preliminary

PIC16F917/916/914/913

19.1 DC Characteristics: PIC16F917/916/914/913-I (Industrial)

PIC16F917/916/914/913-E (Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

DC CHARACTERISTICS

Param

Sym.

Characteristic

Min. Typ† Max. Units

Conditions

FOSC < = 4 MHz:

No.

VDD

Supply Voltage

D001

D001C

D001D

2.0

3.0

4.5

—

5.5

V

FOSC < = 10 MHz

FOSC < = 20 MHz

D002

VDR

RAM Data Retention

Voltage⁽¹⁾

1.5*

—

V

Device in Sleep mode

D003

VPOR

VDD Start Voltage to

ensure internal Power-on

Reset signal

—

VSS

—

V

See Section 16.3 “Power-on Reset” for

details.

D004

D005

SVDD

VBOR

VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05

*

—

V/ms See Section 16.3 “Power-on Reset” for

details.

Brown-out Reset

—

2.1

V

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.

Preliminary

DS41250E-page 221

PIC16F917/916/914/913

19.2 DC Characteristics: PIC16F917/916/914/913-I (Industrial)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Device Characteristics

Min. Typ† Max. Units

VDD

Note

D010

Supply Current (IDD)^{(1, 2)}

—

8

TBD

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

FOSC = 32 kHz

LP Oscillator mode

11

33

D011

D012

D013

D014

D015

D016

D017

D018

110

190

330

220

370

0.6

70

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

FOSC = 1 MHz

EC Oscillator mode

140

260

180

320

500

5

FOSC = 4 MHz

EC Oscillator mode

FOSC = 31 kHz

INTOSC mode

14

30

340

500

0.8

180

320

580

2.1

3.0

FOSC = 4 MHz

INTOSC mode

FOSC = 4 MHz

EXTRC mode

FOSC = 20 MHz

HS Oscillator mode

Legend: TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41250E-page 222

Preliminary

PIC16F917/916/914/913

19.2 DC Characteristics: PIC16F917/916/914/913-I (Industrial) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

Conditions

Param

No.

Device Characteristics

Min. Typ† Max. Units

VDD

Note

D020

Power-down Base

Current (IPD)⁽⁴⁾

—

0.1

0.5

0.75

0.6

1.8

8.4

58

TBD

μA

nA

μA

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF and

T1OSC disabled

D021

WDT Current

D022

D023

BOR Current

75

35

Comparator Current⁽³⁾

65

130

40

D024

D025

D026

CVREF Current

T1OSC Current

A/D Current

50.5

80

2.1

2.5

3.4

1.2

0.0022 TBD

Legend: TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square wave,

from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

Preliminary

DS41250E-page 223

PIC16F917/916/914/913

19.3 DC Characteristics: PIC16F917/916/914/913-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Param

No.

Device Characteristics

Min.

Typ†

Max. Units

VDD

Note

FOSC = 32 kHz

D010E Supply Current (IDD)^{(1, 2)}

—

8

TBD

μA

mA

μA

mA

μA

mA

μA

mA

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

4.5

5.0

LP Oscillator mode

11

33

D011E

D012E

D013E

D014E

D015E

D016E

D017E

110

190

330

220

370

0.6

70

FOSC = 1 MHz

XT Oscillator mode

FOSC = 4 MHz

XT Oscillator mode

FOSC = 1 MHz

EC Oscillator mode

140

260

180

320

500

5

FOSC = 4 MHz

EC Oscillator mode

FOSC = 31 kHz

INTOSC mode

14

30

340

500

0.8

180

320

580

2.1

3.0

FOSC = 4 MHz

INTOSC mode

FOSC = 4 MHz

EXTRC mode

D018E

FOSC = 20 MHz

HS Oscillator mode

Legend: TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

DS41250E-page 224

Preliminary

PIC16F917/916/914/913

19.3 DC Characteristics: PIC16F917/916/914/913-E (Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +125°C for extended

Conditions

Param

No.

Device Characteristics

Min.

Typ†

Max. Units

VDD

Note

D020E Power-down Base

—

0.1

0.5

0.75

0.6

1.8

8.4

58

TBD

μA

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

2.0

3.0

5.0

3.0

5.0

WDT, BOR, Comparators, VREF

and T1OSC disabled

Current (IPD)⁽⁴⁾

D021E

WDT Current

D022E

D023E

BOR Current

75

35

Comparator Current⁽³⁾

65

130

40

D024E

D025E

CVREF Current

T1OSC Current

A/D Current⁽³⁾

50.5

80

2.1

2.5

3.4

1.2

D026E

0.0022 TBD

Legend: TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: The test conditions for all IDD measurements in active Operation mode are: OSC1 = external square

wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have

an impact on the current consumption.

3: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this

peripheral is enabled. The peripheral Δ current can be determined by subtracting the base IDD or IPD

current from this limit. Max values should be used when calculating total current consumption.

4: The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is

measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD.

Preliminary

DS41250E-page 225

PIC16F917/916/914/913

19.4 DC Characteristics: PIC16F917/916/914/913-I (Industrial)

PIC16F917/916/914/913-E (Extended)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

VIL

Input Low Voltage

I/O port:

D030

D030A

D031

D032

D033

D033A

D034

with TTL buffer

Vss

VSS

—

0.8

V

4.5V ≤ VDD ≤ 5.5V

0.15 VDD

0.2 VDD

0.3

Otherwise

with Schmitt Trigger buffer

MCLR, OSC1 (RC mode)

Entire range

(1)

OSC1 (XT and LP modes)

(1)

OSC1 (HS mode)

0.3 VDD

0.3VDD

2

I C™ mode

Entire VDD Range

VIH

Input High Voltage

I/O port:

—

D040

D040A

with TTL buffer

2.0

(0.25 VDD +

0.8)

—

VDD

V

4.5V ≤ VDD ≤ 5.5V

Otherwise

D041

D042

D043

D043A

D043B

D044

D070

with Schmitt Trigger buffer

MCLR

0.8 VDD

1.6

—

VDD

400*

V

Entire range

OSC1 (XT and LP modes)

OSC1 (HS mode)

—

(Note 1)

0.7 VDD

0.9 VDD

0.7VDD

50*

—

OSC1 (RC mode)

—

2

I C mode

—

Entire VDD Range

IPUR

IIL

PORTB Weak Pull-up Current

250

μA VDD = 5.0V, VPIN = VSS

(2)

Input Leakage Current

D060

I/O port

—

0.1

1

μA VSS ≤ VPIN ≤ VDD,

Pin at high-impedance

(3)

D061

D063

MCLR

—

0.1

5

μA VSS ≤ VPIN ≤ VDD

OSC1

μA VSS ≤ VPIN ≤ VDD, XT, HS and

LP OSC configuration

VOL

VOH

Output Low Voltage

I/O port

D080

D083

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V (Ind.)

OSC2/CLKO (RC mode)

IOL = 1.6 mA, VDD = 4.5V (Ind.)

IOL = 1.2 mA, VDD = 4.5V (Ext.)

Output High Voltage

I/O port

D090

D092

VDD – 0.7

—

V

IOH = -3.0 mA, VDD = 4.5V (Ind.)

OSC2/CLKO (RC mode)

IOH = -1.3 mA, VDD = 4.5V (Ind.)

IOH = -1.0 mA, VDD = 4.5V (Ext.)

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an

external clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

DS41250E-page 226

Preliminary

PIC16F917/916/914/913

19.4 DC Characteristics: PIC16F917/916/914/913-I (Industrial)

PIC16F917/916/914/913-E (Extended) (Continued)

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating temperature

-40°C ≤ TA ≤ +85°C for industrial

-40°C ≤ TA ≤ +125°C for extended

Param

No.

Sym.

Characteristic

Min.

Typ†

Max. Units

Conditions

Capacitive Loading Specs

on Output Pins

D100 COS OSC2 pin

C2

—

15*

50*

pF In XT, HS and LP modes

when external clock is used to

drive OSC1

D101

CIO

All I/O pins

pF

Data EEPROM Memory

Byte Endurance

D120 ED

D120A ED

100K

10K

1M

100K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D121 VDRW VDD for Read/Write

VMIN

5.5

V

Using EECON1 to read/write

VMIN = Minimum operating

voltage

D122 TDEW Erase/Write Cycle Time

D123 TRETD Characteristic Retention

—

5

6

ms

40

—

Year Provided no other specifica-

tions are violated

D124 TREF Number of Total Erase/Write

Cycles before Refresh⁽²⁾

1M

10M

—

E/W -40°C ≤ TA ≤ +85°C

Program Flash Memory

D130 EP

D130A ED

Cell Endurance

VDD for Read

10K

1K

100K

10K

—

E/W -40°C ≤ TA ≤ +85°C

E/W +85°C ≤ TA ≤ +125°C

D131

VPR

VMIN

5.5

V

VMIN = Minimum operating

voltage

D132 VPEW VDD for Erase/Write

D133 TPEW Erase/Write cycle time

D134 TRETD Characteristic Retention

4.5

—

2

5.5

2.5

—

V

ms

40

—

Year Provided no other specifica-

tions are violated

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended to use an

external clock in RC mode.

2: Negative current is defined as current sourced by the pin.

3: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

Preliminary

DS41250E-page 227

PIC16F917/916/914/913

19.5 Timing Parameter Symbology

The timing parameter symbols have been created with

one of the following formats:

1. TppS2ppS

2. TppS

T

F

Frequency

Lowercase letters (pp) and their meanings:

pp

cc

T

Time

CCP1

CLKO

CS

osc

rd

OSC1

RD

ck

cs

di

rw

sc

ss

t0

RD or WR

SCK

SDI

do

dt

SDO

SS

Data in

I/O port

MCLR

T0CKI

T1CKI

WR

io

t1

mc

wr

Uppercase letters and their meanings:

S

F

H

I

Fall

P

R

V

Z

Period

High

Rise

Invalid (High-impedance)

Low

Valid

L

High-impedance

FIGURE 19-2:

LOAD CONDITIONS

Load Condition 1

Load Condition 2

VDD/2

RL

CL

VSS

Legend:

RL = 464Ω

CL = 50 pF for all pins

15 pF for OSC2 output

DS41250E-page 228

Preliminary

PIC16F917/916/914/913

19.6 AC Characteristics: PIC16F917/916/914/913 (Industrial, Extended)

FIGURE 19-3:

EXTERNAL CLOCK TIMING

Q4

Q1

Q2

Q3

Q4

4

Q1

OSC1

CLKO

1

3

4

2

TABLE 19-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym.

No.

Characteristic

Min. Typ†

Max. Units

Conditions

FOSC External CLKI Frequency⁽¹⁾

DC

5

—

4

37

4

kHz LP Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

MHz EC Oscillator mode

kHz LP Oscillator mode

MHz INTOSC mode

20

37

—

Oscillator Frequency⁽¹⁾

—

DC

0.1

1

—

4

MHz RC Oscillator mode

MHz XT Oscillator mode

MHz HS Oscillator mode

μs LP Oscillator mode

ns HS Oscillator mode

ns EC Oscillator mode

ns XT Oscillator mode

μs LP Oscillator mode

ns INTOSC mode

4

20

1

TOSC

External CLKI Period⁽¹⁾

Oscillator Period⁽¹⁾

27

∞

50

250

27

200

—

250

—

250

50

—

ns RC Oscillator mode

ns XT Oscillator mode

ns HS Oscillator mode

ns TCY = 4/FOSC

—

10,000

1,000

DC

—

2

3

TCY

Instruction Cycle Time⁽¹⁾

200

2*

TCY

—

TosL, External CLKI (OSC1) High

TosH External CLKI Low

μs LP oscillator, TOSC L/H duty cycle

ns HS oscillator, TOSC L/H duty cycle

ns XT oscillator, TOSC L/H duty cycle

ns LP oscillator

20*

100 *

—

4

TosR, External CLKI Rise

TosF External CLKI Fall

—

50*

25*

15*

—

ns XT oscillator

—

ns HS oscillator

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at ‘min’

values with an external clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle

time limit is ‘DC’ (no clock) for all devices.

Preliminary

DS41250E-page 229

PIC16F917/916/914/913

TABLE 19-2:

PRECISION INTERNAL OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym.

No.

Freq.

Tolerance

Characteristic

Min. Typ†

Max. Units

Conditions

F10

FOSC Internal Calibrated

INTOSC Frequency⁽¹⁾

1%

2%

—

8.00

TBD

MHz VDD and Temperature TBD

MHz 2.5V ≤ VDD ≤ 5.5V

0°C ≤ TA ≤ +85°C

5%

—

8.00

TBD

MHz 2.0V ≤ VDD ≤ 5.5V

-40°C ≤ TA ≤ +85°C (Ind.)

-40°C ≤ TA ≤ +125°C (Ext.)

F14

TIOSC Oscillator Wake-up from

—

TBD

μs VDD = 2.0V, -40°C to +85°C

μs VDD = 3.0V, -40°C to +85°C

μs VDD = 5.0V, -40°C to +85°C

ST

Sleep Start-up Time*

Legend: TBD = To Be Determined

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to

the device as possible. 0.1 uF and 0.01 uF values in parallel are recommended.

DS41250E-page 230

Preliminary

PIC16F917/916/914/913

FIGURE 19-4:

CLKO AND I/O TIMING

Q1

Q2

Q3

Q4

OSC1

CLKO

11

10

22

23

13

12

19

18

14

16

I/O pin

(Input)

15

17

I/O pin

(Output)

New Value

Old Value

20, 21

TABLE 19-3: CLKO AND I/O TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max.

Units Conditions

10* TOSH2CKL OSC1↑ to CLOUT↓

11* TOSH2CKH OSC1↑ to CLOUT↑

—

75

35

—

50

—

200

100

ns (Note 1)

12* TCKR

13* TCKF

CLKO Rise Time

CLKO Fall Time

14* TCKL2IOV CLKO↓ to Port Out Valid

15* TIOV2CKH Port In Valid before CLKO↑

16* TCKH2IOI Port In Hold after CLKO↑

17* TOSH2IOV OSC1↑ (Q1 cycle) to Port Out Valid

0.5 TCY + 20 ns (Note 1)

TOSC + 200 ns

—

ns (Note 1)

0

—

ns (Note 1)

150*

300

—

ns

—

18* TOSH2IOI OSC1↑ (Q2 cycle) to Port

3.0-5.5V

100

200

0

Input Invalid (I/O in hold time)

2.0-5.5V

—

19* TIOV2OSH Port Input Valid to OSC1↑

—

(I/O in setup time)

20* TIOR

21* TIOF

Port Output Rise Time

Port Output Fall Time

INT Pin High or Low Time

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

—

10

—

10

—

40

145

40

ns

—

145

—

22* TINP

23* TRBP

25

TCY

ns

PORTA change INT High or Low Time

—

*

These parameters are characterized but not tested.

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.

†

Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.

Preliminary

DS41250E-page 231

PIC16F917/916/914/913

FIGURE 19-5:

RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND

POWER-UP TIMER TIMING

VDD

MCLR

30

Internal

POR

33

PWRT

Time-out

32

OSC

Time-out

Internal

Reset

Watchdog

Timer

Reset

31

34

I/O pins

FIGURE 19-6:

BROWN-OUT RESET TIMING AND CHARACTERISTICS

VDD

BVDD

(Device not in Brown-out Reset)

(Device in Brown-out Reset)

35

Reset (due to BOR)

(1)

64 ms Time-out

Note 1: 64 ms delay only if PWRTE bit in the Configuration Word is programmed to ‘0’.

DS41250E-page 232

Preliminary

PIC16F917/916/914/913

TABLE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

Sym.

No.

Characteristic

Min.

Typ†

Max. Units

Conditions

30

TMCL

TWDT

TOST

MCLR Pulse Width (low)

2

11

—

18

—

24

μs VDD = 5V, -40°C to +85°C

ms Extended temperature

31

Watchdog Timer Time-out

Period (No Prescaler)

10

17

25

30

ms VDD = 5V, -40°C to +85°C

ms Extended temperature

32

Oscillation Start-up Timer

Period

—

1024 TOSC

—

TOSC = OSC1 period

33*

34

TPWRT Power-up Timer Period

28*

TBD

64

TBD

132*

TBD

ms VDD = 5V, -40°C to +85°C

ms Extended Temperature

TIOZ

I/O High-impedance from

MCLR Low or Watchdog Timer

Reset

—

2.0

μs

BVDD

TBOR

Brown-out Reset Voltage

2.025

100*

—

2.175

—

V

35

Brown-out Reset Pulse Width

μs VDD ≤ BVDD (D005)

Legend: TBD = To Be Determined

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 19-7:

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45

46

48

47

TMR0 or

TMR1

Preliminary

DS41250E-page 233

PIC16F917/916/914/913

TABLE 19-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym.

TT0H

Characteristic

T0CKI High Pulse Width

Min.

Typ†

Max.

Units

Conditions

40*

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 TCY + 20

—

ns

10

0.5 TCY + 20

10

41*

42*

TT0L

TT0P

T0CKI Low Pulse Width

T0CKI Period

Greater of:

20 or TCY + 40

N

ns N = prescale

value (2, 4, ...,

256)

45*

46*

47*

TT1H

TT1L

TT1P

T1CKI High

Time

Synchronous, No Prescaler

0.5 TCY + 20

—

ns

Synchronous,

with Prescaler

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

15

25

Asynchronous

30

50

T1CKI Low

Time

Synchronous, No Prescaler

0.5 TCY + 20

Synchronous,

with Prescaler

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

3.0-5.5V

15

25

30

50

Asynchronous

T1CKI Input Synchronous

Period

Greater of:

30 or TCY + 40

N

ns N = prescale

value (1, 2, 4, 8)

2.0-5.5V

50 or TCY + 40

N

—

ns

Asynchronous

3.0-5.5V

2.0-5.5V

60

100

DC

—

ns

FT1

Timer1 oscillator input frequency range

37*

kHz

(oscillator enabled by setting bit T1OSCEN)

48

TCKEZTMR1 Delay from external clock edge to timer

increment

2 TOSC*

—

7 TOSC*

—

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

FIGURE 19-8:

USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK

SCK/SCL/SEG9

121

RC7/RX/DT/

SDI/SDA/SEG8

120

Refer to Figure 19-2 for load conditions.

122

Note:

DS41250E-page 234

Preliminary

PIC16F917/916/914/913

TABLE 19-6: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param.

Symbol

No.

Characteristic

Min.

Max.

Units Conditions

120

121

122

TCKH2DT SYNC XMIT (Master and Slave)

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

—

80

100

45

ns

V

Clock high to data-out valid

TCKRF

Clock out rise time and fall time

(Master mode)

50

TDTRF

Data-out rise time and fall time

45

50

FIGURE 19-9:

RC6/TX/CK

USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

SCK/SCL/SEG9

125

RC7/RX/DT/

SDI/SDA/SEG8

126

Note: Refer to Figure 19-2 for load conditions.

TABLE 19-7: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param.

Symbol

No.

Characteristic

Min.

Max. Units

Conditions

125

TDTV2CKL SYNC RCV (Master and Slave)

Data-hold before CK ↓ (DT hold time)

TCKL2DTL Data-hold after CK ↓ (DT hold time)

10

15

—

ns

126

FIGURE 19-10:

CAPTURE/COMPARE/PWM TIMINGS

CCP1/CCP2

(Capture mode)

50

51

52

CCP1/CCP2

(Compare mode)

53

Note: Refer to Figure 19-2 for load conditions.

54

Preliminary

DS41250E-page 235

PIC16F917/916/914/913

TABLE 19-8: CAPTURE/COMPARE/PWM REQUIREMENTS

Param. Sym. Characteristic

No.

Min.

Typ† Max. Units Conditions

50*

51*

TCCL CCP1

input low time

No Prescaler

0.5TCY + 5

10

—

ns

With Prescaler

3.0-5.5V

2.0-5.5V

20

0.5TCY + 5

10

—

ns

TCCH

No Prescaler

CCP1

input high time

With Prescaler

3.0-5.5V

2.0-5.5V

20

52*

53*

TCCP

3TCY + 40

N

ns N = prescale

value (1,4 or 16)

CCP1 input period

TCCR CCP1 output fall time

TCCF CCP1 output fall time

3.0-5.5V

2.0-5.5V

3.0-5.5V

2.0-5.5V

—

10

25

10

25

50

25

45

ns

54*

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 19-9: COMPARATOR SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Comparator Specifications

Sym.

Characteristics

Min.

Typ.

Max.

Units

Comments

VOS

Input Offset Voltage

—

0

5.0

—

10

VDD – 1.5

—

mV

V

VCM

CMRR

TRT

Input Common Mode Voltage

Common Mode Rejection Ratio

Response Time⁽¹⁾

+55*

—

db

ns

μs

150

—

400*

TMC2COV Comparator Mode Change to

Output Valid

—

10*

*

These parameters are characterized but not tested.

Note 1: Response time measured with one comparator input at (VDD – 1.5)/2 while the other input transitions from

VSS to VDD – 1.5V.

TABLE 19-10: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated)

Voltage Reference Specifications

Operating temperature

-40°C ≤ TA ≤ +125°C

Sym.

Characteristics

Resolution

Min.

Typ.

Max.

Units

Comments

—

VDD/24*

VDD/32

—

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

Absolute Accuracy

—

1/4*

1/2*

LSb Low Range (VRR = 1)

LSb High Range (VRR = 0)

Unit Resistor Value (R)

Settling Time⁽¹⁾

—

2K*

—

Ω

μs

10*

*

These parameters are characterized but not tested.

Note 1: Settling time measured while VRR = 1and VR<3:0> transitions from ‘0000’ to ‘1111’.

DS41250E-page 236

Preliminary

PIC16F917/916/914/913

TABLE 19-11: PIC16F917/916/914/913 PLVD CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

DC CHARACTERISTICS

Operating Temperature

Operating Voltage

-40°C ≤ TA ≤ +125°C

VDD Range 2.0V-5.5V

Sym.

Characteristic

Min.

Typ†

Max.

Units

Conditions

VPLVD

PLVD

Voltage

LVDL<2:0> = 000

TBD

1.9

2.0

2.1

2.2

2.3

4.0

4.2

4.5

TBD

V

TBD

Legend: TBD = To Be Determined

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Preliminary

DS41250E-page 237

PIC16F917/916/914/913

FIGURE 19-11:

SPI™ MASTER MODE TIMING (CKE = 0, SMP = 0)

SS

70

SCK

(CKP = 0)

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note: Refer to Figure 19-2 for load conditions.

FIGURE 19-12:

SPI™ MASTER MODE TIMING (CKE = 1, SMP = 1)

SS

81

SCK

(CKP = 0)

71

72

79

73

SCK

(CKP = 1)

80

78

LSb

MSb

bit 6 - - - - - -1

SDO

SDI

75, 76

MSb In

74

bit 6 - - - -1

LSb In

Note: Refer to Figure 19-2 for load conditions.

DS41250E-page 238

Preliminary

PIC16F917/916/914/913

FIGURE 19-13:

SPI™ SLAVE MODE TIMING (CKE = 0)

SS

70

SCK

(CKP = 0)

83

71

72

78

79

SCK

(CKP = 1)

78

80

MSb

LSb

SDO

SDI

bit 6 - - - - - -1

77

75, 76

MSb In

74

bit 6 - - - -1

LSb In

73

Note: Refer to Figure 19-2 for load conditions.

FIGURE 19-14:

SPI™ SLAVE MODE TIMING (CKE = 1)

82

SS

70

SCK

83

(CKP = 0)

71

72

SCK

(CKP = 1)

80

MSb

bit 6 - - - - - -1

LSb

SDO

SDI

75, 76

77

MSb In

74

bit 6 - - - -1

LSb In

Note: Refer to Figure 19-2 for load conditions.

Preliminary

DS41250E-page 239

PIC16F917/916/914/913

TABLE 19-12: SPI™ MODE REQUIREMENTS

Param

No.

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input

TCY

—

ns

TSSL2SCL

71* TSCH

72* TSCL

SCK input high time (Slave mode)

SCK input low time (Slave mode)

TCY + 20

100

—

ns

73* TDIV2SCH, Setup time of SDI data input to SCK edge

TDIV2SCL

74* TSCH2DIL, Hold time of SDI data input to SCK edge

TSCL2DIL

100

—

ns

75* TDOR

SDO data output rise time

3.0-5.5V

2.0-5.5V

—

10

—

Tcy

10

25

10

—

10

25

10

—

25

50

25

50

25

50

25

50

145

—

ns

76* TDOF

SDO data output fall time

77* TSSH2DOZ SS↑ to SDO output high-impedance

78* TSCR

SCK output rise time

(Master mode)

3.0-5.5V

2.0-5.5V

79* TSCF

SCK output fall time (Master mode)

80* TSCH2DOV, SDO data output valid after

TSCL2DOV SCK edge

3.0-5.5V

2.0-5.5V

81* TDOV2SCH, SDO data output setup to SCK edge

TDOV2SCL

82* TSSL2DOV SDO data output valid after SS↓ edge

—

50

—

ns

83* TSCH2SSH, SS ↑ after SCK edge

1.5TCY + 40

TSCL2SSH

*

These parameters are characterized but not tested.

†

Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

FIGURE 19-15:

I²C™ BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

Stop

Condition

Start

Condition

Note: Refer to Figure 19-2 for load conditions.

DS41250E-page 240

Preliminary

PIC16F917/916/914/913

TABLE 19-13: I²C™ BUS START/STOP BITS REQUIREMENTS

Param

No.

Symbol

Characteristic

Min. Typ. Max. Units

Conditions

90*

91*

92*

93

TSU:STA Start condition

Setup time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4700

600

—

ns Only relevant for Repeated

Start condition

THD:STA Start condition

Hold time

4000

600

ns After this period, the first

clock pulse is generated

TSU:STO Stop condition

Setup time

4700

600

ns

THD:STO Stop condition

Hold time

4000

600

ns

*

These parameters are characterized but not tested.

FIGURE 19-16:

I²C™ BUS DATA TIMING

103

102

100

101

SCL

90

106

107

91

92

SDA

In

110

109

SDA

Out

Note: Refer to Figure 19-2 for load conditions.

Preliminary

DS41250E-page 241

PIC16F917/916/914/913

TABLE 19-14: I²C™ BUS DATA REQUIREMENTS

Param.

No.

Symbol

Characteristic

Min.

Max. Units

Conditions

100*

THIGH

Clock high time

100 kHz mode

4.0

—

μs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

Device must operate at a

minimum of 10 MHz

SSP Module

1.5TCY

4.7

—

101*

TLOW

Clock low time

100 kHz mode

μs

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

SSP Module

1.3

—

Device must operate at a

minimum of 10 MHz

1.5TCY

—

102*

103*

TR

TF

SDA and SCL rise 100 kHz mode

time

1000

ns

400 kHz mode

20 + 0.1CB 300

CB is specified to be from

10-400 pF

SDA and SCL fall

time

100 kHz mode

400 kHz mode

—

300

ns

20 + 0.1CB 300

CB is specified to be from

10-400 pF

90*

91*

TSU:STA Start condition

setup time

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

0

—

μs

ns

μs

ns

μs

ns

μs

Only relevant for

Repeated Start condition

THD:STA Start condition hold 100 kHz mode

—

After this period the first

clock pulse is generated

time

400 kHz mode

—

106*

107*

92*

THD:DAT Data input hold time 100 kHz mode

400 kHz mode

—

0

0.9

—

TSU:DAT Data input setup

time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

250

100

4.7

0.6

—

(Note 2)

—

TSU:STO Stop condition

setup time

—

109*

110*

TAA

Output valid from

clock

3500

—

(Note 1)

—

TBUF

Bus free time

4.7

1.3

—

Time the bus must be free

before a new transmission

can start

—

CB

Bus capacitive loading

—

400

pF

*

These parameters are characterized but not tested.

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

2: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it

must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS41250E-page 242

Preliminary

PIC16F917/916/914/913

TABLE 19-15: PIC16F917/916/914/913 A/D CONVERTER CHARACTERISTICS:

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C ≤ TA ≤ +125°C

Param

No.

Sym.

Characteristic

Resolution

Min.

Typ†

Max.

Units

Conditions

A01

NR

—

10 bits

< 1

bits

A03

A04

EIL

EDL

Integral Error

LSb VREF = 5.0V

Differential Error

< 1

LSb No missing codes to 10 bits

VREF = 5.0V

A06

A07

A10

A20

EOFF Offset Error

—

< 1

—

LSb VREF = 5.0V

EGN

—

Gain Error

(1)

Monotonicity

—

assured

—

V

VSS ≤ VAIN ≤ VREF+

VREF Reference Voltage

(VREF+ – VREF-)

2.5

VDD

Full 10-bit accuracy

A21

A22

A25

A30

VREF+ Reference Voltage High VDD – 2.5V

—

VDD + 0.3V

VREF+ -2V

VREF+ +0.3V

10

V

VREF- Reference Voltage Low

VSS – 0.3V

—

VAIN

ZAIN

Analog Input Voltage

V

Recommended Imped-

ance of Analog Voltage

Source

kΩ

A50

IREF

VREF Input Current (2)

—

±5

μA During VAIN acquisition.

±150

μA During A/D conversion cycle.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

2: VREF+ current is from RA3/AN3/C1+/VREF+/SEG15 pin or VDD, whichever is selected as the VREF+ source.

VREF- current is from RA2/AN2/C2+/VREF-/COM2 pin or VSS, whichever is selected as the VREF- source.

FIGURE 19-17:

PIC16F917/916/914/913 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

134

Q4

1 TCY

(1)

(TOSC/2)

131

130

A/D CLK

9

8

7

6

3

2

1

0

A/D Data

ADRES

NEW_DATA

1 TCY

OLD_DATA

ADIF

GO

DONE

Sampling Stopped

132

Sample

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEPinstruction to be executed.

Preliminary

DS41250E-page 243

PIC16F917/916/914/913

TABLE 19-16: PIC16F917/916/914/913 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature

-40°C ≤ TA ≤ +125°C

Param

No.

Sym.

Characteristic

A/D Clock Period⁽²⁾

Min.

Typ†

Max.

Units

Conditions

130

TAD

1.6

—

μs TOSC-based, VREF ≥ 3.0V

μs TOSC-based, VREF full range

3.0*

130

TAD

A/D Internal RC

Oscillator Period

ADCS<1:0> = 11(RC mode)

μs At VDD = 2.5V

3.0*

2.0*

—

6.0

4.0

11

9.0*

6.0*

—

μs At VDD = 5.0V

131

132

TCNV Conversion Time

(not including

TAD Set GO/DONE bit to new data in A/D

Result register

Acquisition Time)⁽¹⁾

TACQ Acquisition Time

11.5

—

μs

5*

—

μs The minimum time is the amplifier

settling time. This may be used if the

“new” input voltage has not changed

by more than 1 LSb (i.e., 4.1 mV @

4.096V) from the last sampled

voltage (as stored on CHOLD).

134

TGO

Q4 to A/D Clock

Start

TOSC/2

—

If the A/D clock source is selected as

RC, a time of TCY is added before

the A/D clock starts. This allows the

SLEEPinstruction to be executed.

*

These parameters are characterized but not tested.

†

Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.

2: See Table 12-1 for minimum conditions.

DS41250E-page 244

Preliminary

PIC16F917/916/914/913

20.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs are not available at this time.

Preliminary

DS41250E-page 245

PIC16F917/916/914/913

NOTES:

DS41250E-page 246

Preliminary

PIC16F917/916/914/913

21.0 PACKAGING INFORMATION

21.1 Package Marking Information

28-Lead SPDIP

Example

PIC16F913-I/SP

0410017

XXXXXXXXXXXXXXXXX

YYWWNNN

40-Lead PDIP

Example

XXXXXXXXXXXXXXXXXX

YYWWNNN

PIC16F914-I/P

0410017

Example

28-Lead QFN

16F916

-I/ML

0410017

XXXXXXXX

YYWWNNN

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

*

Standard PICmicro^®device marking consists of Microchip part number, year code, week code and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

Preliminary

DS41250E-page 247

PIC16F917/916/914/913

Package Marking Information (Continued)

44-Lead QFN

Example

XXXXXXXXXX

YYWWNNN

PIC16F914

-I/ML

0410017

28-Lead SOIC

Example

XXXXXXXXXXXXXXXXXXXX

PIC16F913-I/SO

0410017

YYWWNNN

28-Lead SSOP

Example

XXXXXXXXXXXX

PIC16F916-I/SS

0410017

YYWWNNN

44-Lead TQFP

Example

XXXXXXXXXX

YYWWNNN

PIC16F917-I/PT

0310017

DS41250E-page 248

Preliminary

PIC16F917/916/914/913

21.2 Package Details

The following sections give the technical details of the

packages.

28-Lead Skinny Plastic Dual In-line (SP) – 300 mil Body (PDIP)

E1

D

2

n

1

α

E

A2

L

A

c

B1

β

A1

eB

B

p

Units

INCHES*

NOM

28

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.100

2.54

3.81

3.30

Top to Seating Plane

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A

A2

A1

E

.140

.150

.130

.160

3.56

4.06

.125

.015

.300

.275

1.345

.125

.008

.040

.016

.320

.135

3.18

0.38

7.62

6.99

34.16

3.18

0.20

1.02

3.43

.310

.285

1.365

.130

.012

.053

.019

.350

10

.325

.295

1.385

.135

.015

.065

.022

.430

15

7.87

7.24

8.26

7.49

35.18

3.43

0.38

1.65

0.56

10.92

15

E1

D

34.67

3.30

Tip to Seating Plane

Lead Thickness

L

c

0.29

Upper Lead Width

B1

B

1.33

Lower Lead Width

0.41

8.13

5

0.48

8.89

10

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

5

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-095

Drawing No. C04-070

Preliminary

DS41250E-page 249

PIC16F917/916/914/913

40-Lead Plastic Dual In-line (P) – 600 mil Body (PDIP)

E1

D

2

α

n

1

E

A2

A

L

c

B1

B

β

A1

p

eB

Units

INCHES*

NOM

40

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

40

MAX

n

p

Number of Pins

Pitch

.100

2.54

Top to Seating Plane

A

.160

.175

.190

.160

4.06

3.56

4.45

3.81

4.83

4.06

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.140

.015

.595

.530

2.045

.120

.008

.030

.014

.620

5

.150

0.38

15.11

13.46

51.94

3.05

0.20

0.76

0.36

15.75

5

.600

.545

2.058

.130

.012

.050

.018

.650

10

.625

.560

2.065

.135

.015

.070

.022

.680

15

15.24

13.84

52.26

3.30

0.29

1.27

0.46

16.51

10

15.88

14.22

52.45

3.43

0.38

1.78

0.56

17.27

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

§

eB

α

β

Mold Draft Angle Bottom

* Controlling Parameter

§ Significant Characteristic

5

10

15

5

10

15

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

DS41250E-page 250

Preliminary

PIC16F917/916/914/913

28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) –

With 0.55 mm Contact Length (Saw Singulated)

E

E2

EXPOSED

METAL

PAD

e

D

D2

2

1

b

n

OPTIONAL

INDEX

AREA

SEE DETAIL

ALTERNATE

INDEX

INDICATORS

L

TOP VIEW

BOTTOM VIEW

A1

A

DETAIL

ALTERNATE

PAD OUTLINE

Units

Dimension Limits

INCHES

NOM

28

MILLIMETERS*

NOM

28

MIN

MAX

MIN

MAX

n

e

Number of Pins

Pitch

.026 BSC

.035

0.65 BSC

0.90

Overall Height

Standoff

A

.031

.039

0.80

1.00

A1

A3

E

.000

.001

.002

0.00

0.02

0.05

Contact Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

.008 REF

.236

0.20 REF

6.00

.232

.140

.232

.140

.009

.020

.240

.152

.240

.152

.013

.028

5.90

3.55

5.90

3.55

0.23

0.50

6.10

3.85

6.10

3.85

0.33

0.70

E2

D

.146

3.70

.236

6.00

D2

b

.146

3.70

.011

0.28

L

.024

0.60

*Controlling Parameter

Notes:

JEDEC equivalent: MO-220

Drawing No. C04-105

Revised 05-24-04

Preliminary

DS41250E-page 251

PIC16F917/916/914/913

44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN)

DS41250E-page 252

Preliminary

PIC16F917/916/914/913

28-Lead Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC)

E

E1

p

D

B

2

1

n

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

28

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.050

1.27

Overall Height

A

.093

.099

.091

.008

.407

.295

.704

.020

.033

4

.104

2.36

2.50

2.31

0.20

10.34

7.49

17.87

0.50

0.84

4

2.64

Molded Package Thickness

Standoff

A2

A1

E

.088

.004

.394

.288

.695

.010

.016

0

.094

.012

.420

.299

.712

.029

.050

8

2.24

0.10

10.01

7.32

17.65

0.25

0.41

0

2.39

0.30

10.67

7.59

18.08

0.74

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle Top

c

Lead Thickness

Lead Width

.009

.014

0

.011

.017

12

.013

.020

15

0.23

0.36

0

0.28

0.42

12

0.33

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

Preliminary

DS41250E-page 253

PIC16F917/916/914/913

28-Lead Plastic Shrink Small Outline (SS) – 209 mil Body, 5.30 mm (SSOP)

E

E1

p

D

B

2

1

n

A

c

A2

f

A1

L

Units

Dimension Limits

INCHES

NOM

28

MILLIMETERS*

MIN

MAX

MIN

NOM

28

MAX

n

p

Number of Pins

Pitch

.026

-

0.65

-

Overall Height

Molded Package Thickness

Standoff

A

A2

A1

E

-

.079

-

2.0

.065

.002

.295

.009

.390

.022

.004

0°

.069

-

.073

-

1.65

0.05

7.49

5.00

9.90

0.55

0.09

0°

1.75

-

1.85

-

Overall Width

Molded Package Width

Overall Length

Foot Length

.307

.209

.402

.030

-

.323

.220

.413

.037

.010

8°

7.80

5.30

10.20

0.75

-

8.20

5.60

10.50

0.95

0.25

8°

E1

D

L

c

Lead Thickness

Foot Angle

f

4°

Lead Width

B

.009

-

.015

0.22

-

0.38

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions

shall not exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-150

Drawing No. C04-073

DS41250E-page 254

Preliminary

PIC16F917/916/914/913

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

E

E1

#leads=n1

p

D1

D

2

1

B

n

°

CH x 45

α

A

c

φ

β

A1

A2

L

(F)

Units

INCHES

NOM

44

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

44

MAX

n

p

Number of Pins

Pitch

.031

0.80

11

Pins per Side

Overall Height

n1

A

11

.043

.039

.004

.024

.039

3.5

.039

.037

.002

.018

.047

1.00

0.95

1.10

1.00

0.10

0.60

1.20

Molded Package Thickness

Standoff

A2

A1

L

(F)

φ

.041

.006

.030

1.05

0.15

0.75

§

0.05

0.45

1.00

0

Foot Length

Footprint (Reference)

Foot Angle

0

.463

.390

.004

.012

.025

5

7

.482

.398

.008

.017

.045

15

3.5

12.00

10.00

0.15

0.38

0.89

10

7

12.25

10.10

0.20

0.44

1.14

15

Overall Width

E

D

.472

.394

.006

.015

.035

10

11.75

9.90

0.09

0.30

0.64

5

Overall Length

Molded Package Width

Molded Package Length

Lead Thickness

E1

D1

c

Lead Width

B

CH

α

Pin 1 Corner Chamfer

Mold Draft Angle Top

Mold Draft Angle Bottom

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

Preliminary

DS41250E-page 255

PIC16F917/916/914/913

NOTES:

DS41250E-page 256

Preliminary

PIC16F917/916/914/913

APPENDIX A: DATA SHEET

REVISION HISTORY

APPENDIX B: MIGRATING FROM

OTHER PICmicro^®

DEVICES

Revision A

This discusses some of the issues in migrating from

other PICmicro devices to the PIC16F917/916/914/913

family of devices.

This is a new data sheet.

Revision B

B.1

PIC16F676 to PIC16F917/916/914/

913

Updated Peripheral Features.

Page 2, Table: Corrected I/O numbers.

Figure 8-3: Revised Comparator I/O operating modes.

Register 9-1, Table: Corrected max. number of pixels.

TABLE B-1:

FEATURE COMPARISON

PIC16F917/

916/914/913

Feature

PIC16F676

Revision C

Max Operating Speed

20 MHz

1K

20 MHz

8K

Correction to Pin Description Table.

Correction to IPD base and T1OSC.

Max Program Memory

(Words)

Max SRAM (Bytes)

A/D Resolution

64

352

10-bit

256

Revision D

10-bit

Revised references 31.25 kHz to 31 kHz.

Revised Standby Current to 100 nA.

Revised 9.1: internal RC oscillator to internal LF

oscillator.

Data EEPROM (bytes)

Timers (8/16-bit)

Oscillator Modes

Brown-out Reset

Internal Pull-ups

Interrupt-on-change

128

1/1

2/1

8

Y

8

Y

Revision E

RB0/1/2/4/5

RB<7:0>

RB<7:4>

Removed “Advance Information” from Section 19.0

Electrical Specifications. Removed 28-Lead Plastic

Quad Flat No Lead Package (ML) (QFN-S) package.

RB0/1/2/3

/4/5

Comparator

USART

1

2

Y

N

Extended WDT

Software Control

Option of WDT/BOR

INTOSC Frequencies

Clock Switching

4 MHz

N

32 kHz -

8 MHz

Y

Preliminary

DS41250E-page 257

PIC16F917/916/914/913

APPENDIX C: CONVERSION

CONSIDERATIONS

Considerations for converting from previous versions

of devices to the ones listed in this data sheet are listed

in Table C-1.

TABLE C-1:

CONVERSION CONSIDERATIONS

Characteristic

PIC16F917/916/914/913

PIC16F87X

PIC16F87XA

Pins

28/40

3

28/40

3

28/40

3

Timers

Interrupts

Communication

11 or 12

13 or 14

14 or 15

USART, SSP

PSP, USART, SSP

(SPI™, I²C™ Slave)

(SPI, I²C Master/Slave)

Frequency

Voltage

A/D

20 MHz

2.0V-5.5V

2.2V-5.5V

2.0V-5.5V

10-bit,

7 conversion clock selects

4 conversion clock selects

7 conversion clock selects

CCP

2

Comparator

—

Comparator Voltage

Reference

Yes

Program Memory

4K, 8K EPROM

4K, 8K Flash

(Erase/Write on

single-word)

4K, 8K Flash

(Erase/Write on

four-word blocks)

RAM

256, 352 bytes

256 bytes

On/Off

192, 368 bytes

128, 256 bytes

192, 368 bytes

128, 256 bytes

On/Off

EEPROM Data

Code Protection

Segmented, starting at end

of program memory

Program Memory

Write Protection

—

On/Off

Segmented, starting at

beginning of

program memory

LCD Module

Other

16, 24 segment drivers,

4 commons

—

In-Circuit Debugger,

Low-Voltage Programming Low-Voltage Programming

Low-Voltage Programming

DS41250E-page 258

Preliminary

PIC16F917/916/914/913

INDEX

PWM Mode............................................................... 181

RA0 Pin ...................................................................... 33

RA1 Pin ...................................................................... 34

RA2 Pin ...................................................................... 35

RA3 Pin ...................................................................... 36

RA4 Pin ...................................................................... 37

RA5 Pin ...................................................................... 38

RA6 Pin ...................................................................... 39

RA7 Pin ...................................................................... 40

RB Pins....................................................................... 45

RB4 Pin ...................................................................... 46

RB5 Pin ...................................................................... 47

RB6 Pin ...................................................................... 48

RB7 Pin ...................................................................... 49

RC0 Pin ...................................................................... 52

RC1 Pin ...................................................................... 53

RC2 Pin ...................................................................... 53

RC3 Pin ...................................................................... 54

RC4 Pin ...................................................................... 55

RC5 Pin ...................................................................... 56

RC6 Pin ...................................................................... 57

RC7 Pin ...................................................................... 58

RD Pins ...................................................................... 63

RD0 Pin ...................................................................... 62

RD1 Pin ...................................................................... 62

RD2 Pin ...................................................................... 63

RE Pins....................................................................... 66

Resonator Operation .................................................. 74

A

A/D

Acquisition Requirements ......................................... 149

Analog Port Pins ....................................................... 144

Associated Registers ................................................ 151

Block Diagram........................................................... 143

Calculating Acquisition Time..................................... 149

Channel Selection..................................................... 144

Configuration and Operation..................................... 144

Configuring................................................................ 148

Configuring Interrupt ................................................. 148

Conversion (TAD) Cycles .......................................... 145

Conversion Clock...................................................... 144

Effects of Reset......................................................... 151

Internal Sampling Switch (RSS) Impedance.............. 149

Operation During Sleep ............................................ 150

Output Format........................................................... 145

Reference Voltage (VREF)......................................... 144

Source Impedance.................................................... 149

Specifications............................................................ 244

Starting a Conversion ............................................... 145

TAD vs. Operating Frequencies................................. 144

Absolute Maximum Ratings .............................................. 219

AC Characteristics

Industrial and Extended ............................................ 229

Load Conditions........................................................ 228

ACK pulse......................................................................... 169

ADCON0 Register............................................................. 146

ADCON1 Register............................................................. 147

Addressable Universal Synchronous Asynchronous

Receiver Transmitter. See USART

Analog Input Connections................................................... 94

Analog-to-Digital Converter Module. See A/D

ANSEL Register................................................................ 146

Assembler

2

SSP (I C Mode)........................................................ 169

SSP (SPI Mode) ....................................................... 162

System Clock.............................................................. 69

Timer1 ........................................................................ 85

Timer2 ........................................................................ 91

TMR0/WDT Prescaler ................................................ 81

USART Receive ............................................... 135, 136

USART Transmit ...................................................... 132

Watchdog Timer (WDT)............................................ 199

BRGH bit .......................................................................... 129

Brown-out Reset (BOR).................................................... 189

Associated Registers................................................ 190

Calibration ................................................................ 189

Specifications ........................................................... 233

Timing and Characteristics....................................... 232

MPASM Assembler................................................... 216

Asynchronous Reception

Associated Registers ........................................ 135, 137

Asynchronous Transmission

Associated Registers ................................................ 133

B

Baud Rate Generator

Associated Registers ................................................ 129

BF bit................................................................................. 160

Block Diagrams

C

C Compilers

MPLAB C18.............................................................. 216

MPLAB C30.............................................................. 216

Capture/Compare/PWM (CCP) ........................................ 177

Associated Registers

A/D............................................................................ 143

Analog Input Model............................................. 94, 150

Capture Mode ........................................................... 179

Comparator 1.............................................................. 96

Comparator 2.............................................................. 96

Comparator Modes ..................................................... 95

Comparator Voltage Reference (CVREF).................... 98

Compare Mode ......................................................... 180

Fail-Safe Clock Monitor (FSCM)................................. 79

In-Circuit Serial Programming Connections.............. 203

Interrupt Logic........................................................... 196

LCD Clock Generation.............................................. 108

LCD Driver Module ................................................... 102

LCD Resistor Ladder Connection ............................. 106

MCLR Circuit............................................................. 188

On-Chip Reset Circuit............................................... 187

PIC16F913/916............................................................. 8

PIC16F914/917............................................................. 9

Capture, Compare and Timer1......................... 182

PWM and Timer2.............................................. 183

Capture Mode........................................................... 179

Block Diagram .................................................. 179

CCP1CON Register.......................................... 178

CCP1IF............................................................. 179

Prescaler .......................................................... 179

CCP Timer Resources.............................................. 177

Compare

Special Trigger Output of CCP1....................... 180

Special Trigger Output of CCP2....................... 180

Compare Mode......................................................... 180

Block Diagram.................................................. 180

Software Interrupt Mode................................... 180

Preliminary

DS41250E-page 259

PIC16F917/916/914/913

Special Event Trigger........................................180

Interaction of Two CCP Modules (table)...................177

PWM Mode ...............................................................180

Block Diagram...................................................181

Duty Cycle.........................................................181

Example Frequencies/Resolutions (table) ........182

PWM Period......................................................181

Special Event Trigger and A/D Conversions.............180

CCP. See Capture/Compare/PWM

D

D/A bit............................................................................... 160

Data EEPROM Memory.................................................... 153

Associated Registers................................................ 158

Reading .................................................................... 156

Writing ...................................................................... 156

Data Memory ...................................................................... 14

Data/Address bit (D/A)...................................................... 160

DC Characteristics

CCP1CON Register .................................................... 64, 178

CCPR1H Register.............................................................177

CCPR1L Register..............................................................177

CCPxM0 bit.......................................................................178

CCPxM1 bit.......................................................................178

CCPxM2 bit.......................................................................178

CCPxM3 bit.......................................................................178

CCPxX bit..........................................................................178

CCPxY bit..........................................................................178

CKE bit..............................................................................160

CKP bit..............................................................................161

CMCON0 Register ..............................................................93

CMCON1 Register ..............................................................97

Code Examples

Extended and Industrial............................................ 226

Industrial and Extended............................................ 221

Development Support....................................................... 215

Device Overview................................................................... 7

E

EEADRH Registers................................................... 153, 154

EEADRL Registers ................................................... 153, 154

EECON1 Register..................................................... 153, 155

EECON2 Register............................................................. 153

EEDATH Register............................................................. 154

EEDATL Register ............................................................. 154

Electrical Specifications.................................................... 219

Enhanced Capture/Compare/PWM (ECCP)

A/D Conversion.........................................................148

Assigning Prescaler to Timer0 ....................................83

Assigning Prescaler to WDT .......................................83

Call of a Subroutine in Page 1 from Page 0................29

Indirect Addressing .....................................................30

Initializing PORTA.......................................................31

Initializing PORTB.......................................................41

Initializing PORTC.......................................................51

Initializing PORTD.......................................................60

Initializing PORTE.......................................................65

Loading the SSPBUF (SSPSR) Register..................163

Saving Status and W Registers in RAM ...................198

Code Protection ................................................................203

Comparator Module ............................................................93

Comparator Voltage Reference (CVREF)

Associated Registers ................................................100

Effects of a Reset........................................................99

Response Time...........................................................99

Comparator Voltage Reference (CVREF) ............................98

Accuracy/Error ............................................................98

Configuring..................................................................98

Specifications............................................................236

Comparators

Associated Registers ................................................100

C2OUT as T1 Gate ...............................................86, 97

Configurations.............................................................95

Effects of a Reset........................................................99

Interrupts.....................................................................97

Operation ....................................................................94

Operation During Sleep ..............................................99

Outputs .......................................................................97

Response Time...........................................................99

Specifications............................................................236

Synchronizing C2OUT w/ Timer1 ...............................97

CONFIG Register..............................................................186

Configuration Bits..............................................................186

Conversion Considerations...............................................258

CPU Features ...................................................................185

Customer Change Notification Service .............................267

Customer Notification Service...........................................267

Customer Support.............................................................267

Enhanced PWM Mode

TMR2 to PR2 Match........................................... 90

Errata.................................................................................... 5

F

Fail-Safe Clock Monitor ...................................................... 79

Fail-Safe Condition Clearing....................................... 80

Reset and Wake-up from Sleep.................................. 80

Firmware Instructions ....................................................... 205

Flash Program Memory .................................................... 153

Fuses. See Configuration Bits

G

General Purpose Register File ........................................... 14

I

I/O Ports.............................................................................. 31

I C Mode

2

Addressing................................................................ 170

Associated Registers................................................ 176

Master Mode............................................................. 175

Mode Selection......................................................... 169

Multi-Master Mode.................................................... 175

Operation.................................................................. 169

Reception ................................................................. 171

Slave Mode

SCL and SDA pins............................................ 169

Transmission ............................................................ 173

ID Locations...................................................................... 203

In-Circuit Debugger........................................................... 204

In-Circuit Serial Programming (ICSP)............................... 203

Indirect Addressing, INDF and FSR Registers ................... 30

Instruction Format............................................................. 206

Instruction Set................................................................... 205

ADDLW..................................................................... 208

ADDWF..................................................................... 208

ANDLW..................................................................... 208

ANDWF..................................................................... 208

BCF .......................................................................... 208

BSF........................................................................... 208

BTFSC...................................................................... 209

BTFSS ...................................................................... 208

DS41250E-page 260

Preliminary

PIC16F917/916/914/913

CALL......................................................................... 209

CLRF......................................................................... 209

CLRW ....................................................................... 209

CLRWDT................................................................... 209

COMF ....................................................................... 209

DECF ........................................................................ 209

DECFSZ.................................................................... 210

GOTO ....................................................................... 210

INCF.......................................................................... 210

INCFSZ..................................................................... 210

IORLW ...................................................................... 210

IORWF...................................................................... 210

MOVF........................................................................ 211

MOVLW .................................................................... 211

MOVWF .................................................................... 211

NOP .......................................................................... 211

RETFIE ..................................................................... 212

RETLW ..................................................................... 212

RETURN................................................................... 212

RLF ........................................................................... 213

RRF........................................................................... 213

SLEEP ...................................................................... 213

SUBLW ..................................................................... 213

SUBWF..................................................................... 213

SWAPF ..................................................................... 214

XORLW..................................................................... 214

XORWF..................................................................... 214

Summary Table......................................................... 207

INTCON Register................................................................ 23

Pixel Control ............................................................. 107

Prescaler .................................................................. 106

Segment Enables ..................................................... 107

Waveform Generation .............................................. 110

LCDCON Register ............................................................ 101

LCDDATA Register........................................................... 101

LCDPS Register ............................................................... 101

LP Bits ...................................................................... 106

LCDSE Register ............................................................... 101

Liquid Crystal Display (LCD) Driver.................................. 101

Load Conditions................................................................ 228

M

MCLR ............................................................................... 188

Internal...................................................................... 188

Memory Organization ......................................................... 13

Data............................................................................ 14

Program...................................................................... 13

Microchip Internet Web Site.............................................. 267

Migrating from other PICmicro Devices............................ 257

MPLAB ASM30 Assembler, Linker, Librarian................... 216

MPLAB ICD 2 In-Circuit Debugger ................................... 217

MPLAB ICE 2000 High-Performance Universal

In-Circuit Emulator.................................................... 217

MPLAB ICE 4000 High-Performance Universal

In-Circuit Emulator.................................................... 217

MPLAB Integrated Development Environment Software.. 215

MPLAB PM3 Device Programmer .................................... 217

MPLINK Object Linker/MPLIB Object Librarian................ 216

2

Inter-Integrated Circuit (I C). See I C Mode

Internal Oscillator Block

O

OPCODE Field Descriptions............................................. 205

OPTION_REG Register................................................ 22, 82

OSCCON Register.............................................................. 70

Oscillator

Associated Registers.................................................. 80

Oscillator Configurations..................................................... 69

Oscillator Delay Examples.......................................... 72

Special Cases............................................................. 71

Oscillator Specifications.................................................... 229

Oscillator Start-up Timer (OST)

Specifications ........................................................... 233

Oscillator Switching

Fail-Safe Clock Monitor .............................................. 79

Two-Speed Clock Start-up ......................................... 78

OSCTUNE Register............................................................ 76

INTOSC

Specifications.................................................... 230

Internal Sampling Switch (Rss) Impedance...................... 149

Internet Address................................................................ 267

Interrupt Sources

USART Receive/Transmit Complete ........................ 127

Interrupts........................................................................... 195

A/D............................................................................ 148

Associated Registers ................................................ 197

Comparators ............................................................... 97

Context Saving.......................................................... 198

Interrupt-on-change .................................................... 41

PORTB Interrupt-on-Change .................................... 196

RB0/INT/SEG0.......................................................... 196

TMR0 ........................................................................ 196

TMR1 .......................................................................... 86

TMR2 to PR2 Match ................................................... 91

TMR2 to PR2 Match (PWM) ....................................... 90

INTOSC Specifications ..................................................... 230

IOCB Register..................................................................... 42

P

P (Stop) bit........................................................................ 160

Packaging......................................................................... 247

Marking............................................................. 247, 248

PDIP Details ............................................................. 249

SOIC Details............................................................. 253

TSSOP Details ......................................................... 253

Paging, Program Memory................................................... 29

PCL and PCLATH............................................................... 29

Computed GOTO ....................................................... 29

Stack........................................................................... 29

PCON Register................................................................. 190

PICSTART Plus Development Programmer..................... 218

PIE1 Register ..................................................................... 24

PIE2 Register ..................................................................... 25

Pin Diagram

L

LCD

Associated Registers ................................................ 124

Bias Types ................................................................ 106

Clock Source Selection............................................. 106

Configuring the Module............................................. 124

Frame Frequency...................................................... 107

Interrupts................................................................... 121

LCDCON Register .................................................... 101

LCDDATA Register................................................... 101

LCDPS Register........................................................ 101

LCDSE Register........................................................ 101

Multiplex Types......................................................... 107

Operation During Sleep ............................................ 122

PIC16F913/916, 28-pin ................................................ 3

PIC16F914/917, 40-pin ................................................ 2

PIC16F914/917, 44-pin ................................................ 4

Preliminary

DS41250E-page 261

PIC16F917/916/914/913

Pinout Description...............................................................10

PIR1 Register......................................................................26

PIR2 Register......................................................................27

PORTA

Associated Registers.................................................. 67

Pin Descriptions and Diagrams .................................. 66

RE0............................................................................. 66

RE1............................................................................. 66

RE2............................................................................. 66

RE3............................................................................. 66

Registers .................................................................... 65

PORTE Register................................................................. 65

Power-Down Mode (Sleep)............................................... 201

Power-on Reset................................................................ 188

Power-up Timer (PWRT) .................................................. 188

Specifications ........................................................... 233

Precision Internal Oscillator Parameters .......................... 230

Prescaler

Shared WDT/Timer0................................................... 83

Switching Prescaler Assignment ................................ 83

Product Identification System ........................................... 269

Program Memory................................................................ 13

Map and Stack (PIC16F913/914)............................... 13

Map and Stack (PIC16F916/917)............................... 13

Paging ........................................................................ 29

Programmable Low-Voltage Detect (PLVD) Module ........ 125

Programming, Device Instructions.................................... 205

Pulse Width Modulation.SeeCapture/Compare/PWM, PWM

Mode.

Associated Registers ..................................................40

Pin Descriptions and Diagrams...................................33

RA0 .............................................................................33

RA1 .............................................................................34

RA2 .............................................................................35

RA3 .............................................................................36

RA4 .............................................................................37

RA5 .............................................................................38

RA6 .............................................................................39

RA7 .............................................................................40

Registers.....................................................................31

Specifications............................................................231

PORTA Register .................................................................32

PORTB

Additional Pin Functions .............................................41

Weak Pull-up.......................................................41

Associated Registers ..................................................50

Interrupt-on-change ....................................................41

Pin Descriptions and Diagrams...................................44

RB0 .............................................................................44

RB1 .............................................................................44

RB2 .............................................................................44

RB3 .............................................................................44

RB4 .............................................................................46

RB5 .............................................................................47

RB6 .............................................................................48

RB7 .............................................................................49

Registers.....................................................................41

PORTB Register .................................................................42

PORTC

Associated Registers ..................................................59

Pin Descriptions and Diagrams...................................52

RC0.............................................................................52

RC1.............................................................................52

RC2.............................................................................52

RC3.............................................................................54

RC4.............................................................................55

RC5.............................................................................56

RC6.............................................................................57

RC6/TX/CK/SCK/SCL/SEG9 Pin ..............................128

RC7.............................................................................58

RC7/RX/DT Pin.........................................................129

RC7/RX/DT/SDI/SDA/SEG8 Pin...............................128

Registers.....................................................................51

Specifications............................................................231

TRISC Register.........................................................127

PORTC Register .................................................................51

PORTD

Associated Registers ..................................................64

Pin Descriptions and Diagrams...................................61

RD0.............................................................................61

RD1.............................................................................61

RD2.............................................................................61

RD3.............................................................................61

RD4.............................................................................61

RD5.............................................................................61

RD6.............................................................................61

RD7.............................................................................61

Registers.....................................................................60

PORTD Register .................................................................60

PORTE

R

R/W bit.............................................................................. 160

RCSTA Register

ADDEN Bit................................................................ 128

CREN Bit .................................................................. 128

FERR Bit................................................................... 128

OERR Bit .................................................................. 128

RX9 Bit ..................................................................... 128

RX9D Bit................................................................... 128

SPEN Bit........................................................... 127, 128

SREN Bit .................................................................. 128

Reader Response............................................................. 268

Read-Modify-Write Operations ......................................... 205

Receive Overflow Indicator bit (SSPOV) .......................... 161

Registers

ADCON0 (A/D Control 0).......................................... 146

ADCON1 (A/D Control 1).......................................... 147

ANSEL (Analog Select) ............................................ 146

CCP1CON (CCP Control 2)...................................... 178

CCP2CON (CCP Control 1)...................................... 178

CMCON0 (Comparator Control 0) .............................. 93

CMCON1 (Comparator Control 1) .............................. 97

CONFIG (Configuration Word) ................................. 186

EEADRH (EEPROM Address).................................. 154

EEADRL (EEPROM Address) .................................. 154

EECON1 (EEPROM Control 1) ................................ 155

EEDATH (EEPROM Data)........................................ 154

EEDATL (EEPROM Data)........................................ 154

INTCON (Interrupt Control)......................................... 23

IOCB (PORTB Interrupt-on-change)........................... 42

LCDCON (LCD Control) ........................................... 103

LCDDATAx (LCD Datax).......................................... 105

LCDPS (LCD Prescaler Select)................................ 104

LCDSEn (LCD Segment).......................................... 105

LVDCON (Low-Voltage Detect Control) ................... 125

OPTION_REG ...................................................... 22, 82

OSCCON (Oscillator Control)..................................... 70

OSCTUNE .................................................................. 76

PCON (Power Control) ............................................. 190

PIE1 (Peripheral Interrupt Enable 1)........................... 24

DS41250E-page 262

Preliminary

PIC16F917/916/914/913

PIE2 (Peripheral Interrupt Enable 2)........................... 25

PIR1 (Peripheral Interrupt Register 1) ........................ 26

PIR2 (Peripheral Interrupt Register 2) ........................ 27

PORTA........................................................................ 32

PORTB........................................................................ 42

PORTC ....................................................................... 51

PORTD ....................................................................... 60

PORTE........................................................................ 65

RCSTA (Receive Status and Control)....................... 128

Reset Values............................................................. 192

Reset Values (Special Registers) ............................. 194

Special Function Register Map

SPI Master Mode...................................................... 165

SPI Slave Mode........................................................ 166

SSPBUF ................................................................... 165

SSPSR ..................................................................... 165

SSPEN bit......................................................................... 161

SSPM bits......................................................................... 161

SSPOV bit ........................................................................ 161

Status Register ................................................................... 21

Synchronous Master Reception

Associated Registers................................................ 140

Synchronous Master Transmission

Associated Registers................................................ 139

Synchronous Serial Port Enable bit (SSPEN) .................. 161

Synchronous Serial Port Mode Select bits (SSPM).......... 161

Synchronous Serial Port. See SSP

PIC16F913/916................................................... 15

PIC16F914/917................................................... 16

Special Register Summary

Bank 0................................................................. 17

Bank 1................................................................. 18

Bank 2................................................................. 19

Bank 3................................................................. 20

SSPCON (Sync Serial Port Control) Register........... 161

SSPSTAT (Sync Serial Port Status) Register........... 160

Status.......................................................................... 21

T1CON (Timer1 Control)............................................. 87

T2CON (Timer2 Control)............................................. 90

TRISA (PORTA Tri-state) ........................................... 32

TRISB (PORTB Tri-state) ........................................... 42

TRISC (PORTC Tri-state)........................................... 51

TRISD (PORTD Tri-state)........................................... 60

TRISE (PORTE Tri-state) ........................................... 65

TXSTA (Transmit Status and Control) ...................... 127

VRCON (Voltage Reference Control) ....................... 100

WDTCON (Watchdog Timer Control) ....................... 200

WPUB (Weak Pull-up PORTB)................................... 43

Reset................................................................................. 187

Revision History................................................................ 257

Synchronous Slave Reception

Associated Registers................................................ 142

Synchronous Slave Transmission

Associated Registers................................................ 142

T

T1CON Register ................................................................. 87

Time-out Sequence .......................................................... 190

Timer0

Associated Registers.................................................. 83

External Clock ............................................................ 82

External Clock Requirements................................... 234

Interrupt ...................................................................... 81

Operation.................................................................... 81

T0CKI ......................................................................... 82

Timer0 Module.................................................................... 81

Timer1

Associated Registers.................................................. 89

Asynchronous Counter Mode..................................... 88

Reading and Writing........................................... 88

External Clock Requirements................................... 234

Interrupt ...................................................................... 86

Modes of Operations .................................................. 86

Operation During Sleep.............................................. 89

Prescaler .................................................................... 86

Resetting of Timer1 Registers.................................... 89

Resetting Timer1 Using a CCP Trigger Output .......... 88

Timer1 Gate

S

S (Start) bit........................................................................ 160

SCI. See USART

Serial Communication Interface. See USART.

Slave Select Synchronization ........................................... 166

SMP bit ............................................................................. 160

Software Simulator (MPLAB SIM)..................................... 216

Special Function Registers ................................................. 14

SPI Mode .................................................................. 159, 166

Associated Registers ................................................ 168

Bus Mode Compatibility ............................................ 168

Effects of a Reset...................................................... 168

Enabling SPI I/O ....................................................... 164

Master Mode............................................................. 165

Master/Slave Connection.......................................... 164

Serial Clock (SCK pin) .............................................. 159

Serial Data In (SDI pin)............................................. 159

Serial Data Out (SDO pin) ........................................ 159

Slave Select.............................................................. 159

Slave Select Synchronization ................................... 166

Sleep Operation........................................................ 168

SPI Clock .................................................................. 165

Typical Connection ................................................... 164

SSP

Inverting Gate..................................................... 86

Selecting Source .......................................... 86, 97

Synchronizing C2OUT w/ Timer1....................... 97

TMR1H Register......................................................... 85

TMR1L Register ......................................................... 85

Timer1 Module with Gate Control....................................... 85

Timer2 ................................................................................ 90

Associated registers ................................................... 91

Operation.................................................................... 90

Postscaler................................................................... 90

PR2 Register .............................................................. 90

Prescaler .................................................................... 90

TMR2 Output.............................................................. 91

TMR2 Register ........................................................... 90

TMR2 to PR2 Match Interrupt............................... 90, 91

Timing Diagrams

A/D Conversion ........................................................ 243

Asynchronous Master Transmission ........................ 132

Asynchronous Master Transmission (Back to Back) 132

Asynchronous Reception.......................................... 135

Asynchronous Reception with Address Byte First.... 137

Asynchronous Reception with Address Detect......... 137

Brown-out Reset (BOR)............................................ 232

Overview

SPI Master/Slave Connection................................... 164

2

SSP I C Operation............................................................ 169

Slave Mode............................................................... 169

SSP Module

Clock Synchronization and the CKP Bit.................... 175

Preliminary

DS41250E-page 263

PIC16F917/916/914/913

Brown-out Reset Situations ......................................189

Capture/Compare/PWM............................................235

CLKO and I/O ...........................................................231

Clock Synchronization ..............................................176

Comparator Output .....................................................94

External Clock...........................................................229

Fail-Safe Clock Monitor (FSCM).................................80

TRISD

Registers .................................................................... 60

TRISD Register................................................................... 60

TRISE

Registers .................................................................... 65

TRISE Register................................................................... 65

Two-Speed Clock Start-up Mode........................................ 78

TXSTA Register

2

I C Bus Data.............................................................241

2

I C Bus Start/Stop Bits..............................................240

BRGH Bit .................................................................. 127

CSRC Bit .................................................................. 127

SYNC Bit .................................................................. 127

TRMT Bit................................................................... 127

TX9 Bit...................................................................... 127

TX9D Bit ................................................................... 127

TXEN Bit................................................................... 127

2

I C Reception (7-bit Address)...................................171

2

I C Slave Mode (Transmission, 10-bit Address).......174

2

I C Slave Mode with SEN = 0 (Reception,

10-bit Address)..................................................172

I C Transmission (7-bit Address)..............................173

2

INT Pin Interrupt........................................................197

LCD Interrupt Timing in Quarter-Duty Cycle Drive....121

LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 .123

Reset, WDT, OST and Power-up Timer ...................232

Slave Synchronization ..............................................166

SPI Master Mode (CKE = 1, SMP = 1) .....................238

SPI Mode (Master Mode)..........................................165

SPI Mode (Slave Mode with CKE = 0)......................167

SPI Mode (Slave Mode with CKE = 1)......................167

SPI Slave Mode (CKE = 0) .......................................239

SPI Slave Mode (CKE = 1) .......................................239

Synchronous Reception (Master Mode, SREN) .......141

Synchronous Transmission.......................................139

Synchronous Transmission (Through TXEN) ...........139

Time-out Sequence

U

UA..................................................................................... 160

Update Address bit, UA .................................................... 160

USART.............................................................................. 127

Address Detect Enable (ADDEN Bit)........................ 128

Asynchronous Mode................................................. 131

Asynchronous Receive (9-bit Mode)......................... 136

Asynchronous Receive with Address Detect.

See Asynchronous Receive (9-bit Mode).

Asynchronous Receiver............................................ 134

Asynchronous Reception.......................................... 134

Asynchronous Transmitter........................................ 131

Baud Rate Generator (BRG) .................................... 129

Baud Rate Formula .......................................... 129

Baud Rates, Asynchronous Mode (BRGH = 0) 130

Baud Rates, Asynchronous Mode (BRGH = 1) 130

High Baud Rate Select (BRGH Bit) .................. 127

Sampling........................................................... 129

Clock Source Select (CSRC Bit)............................... 127

Continuous Receive Enable (CREN Bit)................... 128

Framing Error (FERR Bit) ......................................... 128

Mode Select (SYNC Bit) ........................................... 127

Overrun Error (OERR Bit)......................................... 128

Receive Data, 9th Bit (RX9D Bit).............................. 128

Receive Enable, 9-bit (RX9 Bit)................................ 128

Serial Port Enable (SPEN Bit) .......................... 127, 128

Single Receive Enable (SREN Bit)........................... 128

Synchronous Master Mode....................................... 138

Requirements, Synchronous Receive .............. 235

Requirements, Synchronous Transmission...... 235

Timing Diagram, Synchronous Receive ........... 235

Timing Diagram, Synchronous Transmission... 234

Synchronous Master Reception................................ 140

Synchronous Master Transmission .......................... 138

Synchronous Slave Mode......................................... 141

Synchronous Slave Reception.................................. 142

Synchronous Slave Transmit.................................... 141

Transmit Data, 9th Bit (TX9D) .................................. 127

Transmit Enable (TXEN Bit) ..................................... 127

Transmit Enable, Nine-bit (TX9 Bit).......................... 127

Transmit Shift Register Status (TRMT Bit) ............... 127

Case 1...............................................................191

Case 2...............................................................191

Case 3...............................................................191

Timer0 and Timer1 External Clock ...........................233

Timer1 Incrementing Edge..........................................86

Two Speed Start-up ....................................................79

Type-A in 1/2 Mux, 1/2 Bias Drive ............................111

Type-A in 1/2 Mux, 1/3 Bias Drive ............................113

Type-A in 1/3 Mux, 1/2 Bias Drive ............................115

Type-A in 1/3 Mux, 1/3 Bias Drive ............................117

Type-A in 1/4 Mux, 1/3 Bias Drive ............................119

Type-A/Type-B in Static Drive...................................110

Type-B in 1/2 Mux, 1/2 Bias Drive ............................112

Type-B in 1/2 Mux, 1/3 Bias Drive ............................114

Type-B in 1/3 Mux, 1/2 Bias Drive ............................116

Type-B in 1/3 Mux, 1/3 Bias Drive ............................118

Type-B in 1/4 Mux, 1/3 Bias Drive ............................120

USART Synchronous Receive (Master/Slave) .........235

USART Synchronous Transmission (Master/Slave) .234

Wake-up from Interrupt .............................................202

Timing Parameter Symbology...........................................228

Timing Requirements

2

I C Bus Data.............................................................242

I2C Bus Start/Stop Bits .............................................241

SPI Mode ..................................................................240

TMR1H Register .................................................................85

TMR1L Register..................................................................85

TRISA

Registers.....................................................................31

TRISA Register ...................................................................32

TRISB

Registers.....................................................................41

TRISB Register ...................................................................42

TRISC

V

Voltage Reference. See Comparator Voltage Reference

(CVREF)

VRCON Register .............................................................. 100

Registers.....................................................................51

TRISC Register...................................................................51

DS41250E-page 264

Preliminary

PIC16F917/916/914/913

W

Wake-up Using Interrupts ................................................. 201

Watchdog Timer (WDT) .................................................... 199

Associated Registers ................................................ 200

Clock Source............................................................. 199

Modes ....................................................................... 199

Period........................................................................ 199

Specifications............................................................ 233

WCOL bit .......................................................................... 161

WDTCON Register ........................................................... 200

WPUB Register................................................................... 43

Write Collision Detect bit (WCOL)..................................... 161

WWW Address.................................................................. 267

WWW, On-Line Support ....................................................... 5

Preliminary

DS41250E-page 265

PIC16F917/916/914/913

NOTES:

DS41250E-page 266

Preliminary

PIC16F917/916/914/913

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Preliminary

DS41250E-page 267

PIC16F917/916/914/913

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

PIC16F917/916/914/913

DS41250E

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS41250E-page 268

Preliminary

PIC16F917/916/914/913

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

XXX

Examples:

Temperature

Range

Package

Pattern

a)

PIC16F913-E/SP 301 = Extended Temp.,

skinny PDIP package, 20 MHz, QTP pattern

#301

b)

PIC16F913-I/SO

package, 20 MHz

= Industrial Temp., SOIC

Device

PIC16F917/916/914/913⁽¹⁾, PIC16F917/916/914/913T⁽²⁾

Temperature Range

Package

I

E

=

-40°C to +85°C

-40°C to +125°C

ML

P

PT

SO

SP

SS

=

Micro Lead Frame (QFN)

Plastic DIP

TQFP (Thin Quad Flatpack)

SOIC

Skinny Plastic DIP

SSOP

Note 1:

2:

F

LF

T

=

Standard Voltage Range

Wide Voltage Range

In tape and reel.

Pattern

3-Digit Pattern Code for QTP (blank otherwise)

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of

each oscillator type.

Preliminary

DS41250E-page 269

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-2229-0061

Fax: 91-80-2229-0062

Austria - Weis

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Atlanta

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

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Tel: 31-416-690399

Fax: 31-416-690340

China - Qingdao

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Fax: 86-532-8502-7205

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-352-30-52

Fax: 34-91-352-11-47

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Malaysia - Penang

Tel: 604-646-8870

Fax: 604-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Philippines - Manila

Tel: 632-634-9065

Fax: 632-634-9069

Detroit

China - Shenzhen

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

08/24/05

DS41250E-page 270

Preliminary


型号：	PIC16F913E/SS301
厂家：	MICROCHIP
描述：	28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology 28 /40/ 44引脚基于闪存的8位CMOS微控制器与LCD驱动器和纳瓦技术驱动器闪存微控制器 CD
文件：	总272页 (文件大小：4705K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PIC16F913E/SS301 [MICROCHIP]

相关型号：

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PIC16F913T-E/ML

PIC16F913T-E/MLQTP

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PIC16F913T-E/PQTP

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