PIC16LC58B-04I/JW [MICROCHIP]
8-BIT, UVPROM, 4 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, CERDIP-18;
| 型号： | PIC16LC58B-04I/JW |
| 厂家： | 
MICROCHIP |
| 描述： | 8-BIT, UVPROM, 4 MHz, RISC MICROCONTROLLER, CDIP18, 0.300 INCH, WINDOWED, CERDIP-18 可编程只读存储器 CD |
| 文件： | 总158页 (文件大小：1194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PIC16C5X
EPROM/ROM-Based 8-Bit CMOS Microcontroller Series
Peripheral Features:
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
Devices Included in this Data Sheet:
• PIC16C54
• PIC16CR54
• Power-on Reset (POR)
• PIC16C55
• Device Reset Timer (DRT)
• PIC16C56
• Watchdog Timer (WDT) with its own on-chip
RC oscillator for reliable operation
• PIC16CR56
• PIC16C57
• Programmable Code Protection
• Power saving SLEEP mode
• Selectable oscillator options:
• PIC16CR57
• PIC16C58
• PIC16CR58
- RC:
- XT:
- HS:
- LP:
Low-cost RC oscillator
Note: 16C5X refers to all revisions of the part
(i.e., 16C54 refers to 16C54, 16C54A, and
16C54C), unless specifically called out
otherwise.
Standard crystal/resonator
High-speed crystal/resonator
Power saving, low-frequency crystal
CMOS Technology:
High-Performance RISC CPU:
• Low-power, high-speed CMOS EPROM/ROM
technology
• Only 33 single word instructions to learn
• All instructions are single cycle (200 ns) except for
program branches which are two-cycle
• Fully static design
• Wide-operating voltage and temperature range:
- EPROM Commercial/Industrial 2.0V to 6.25V
- ROM Commercial/Industrial 2.0V to 6.25V
- EPROM Extended 2.5V to 6.0V
- ROM Extended 2.5V to 6.0V
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
EPROM/
ROM
Device
Pins I/O
RAM
PIC16C54
18
18
18
18
18
28
28
18
18
18
28
28
28
18
18
12
12
12
12
12
20
20
12
12
12
20
20
20
12
12
512
512
512
512
512
512
512
1K
25
25
25
25
25
24
24
25
25
25
72
72
72
73
73
• Low-power consumption
PIC16C54A
PIC16C54C
PIC16CR54A
PIC16CR54C
PIC16C55
- < 2 mA typical @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 0.6 µA typical standby current
(with WDT disabled) @ 3V, 0°C to 70°C
PIC16C55A
PIC16C56
Note: In this document, figure and table titles
refer to all varieties of the part number indi-
cated, (i.e., The title "Figure 14-1: Load
Conditions - PIC16C54A", also refers to
PIC16LC54A and PIC16LV54A parts)
unless specifically called out otherwise.
PIC16C56A
PIC16CR56A
PIC16C57
1K
1K
2K
PIC16C57C
PIC16CR57C
PIC16C58B
PIC16CR58B
2K
2K
2K
2K
• 12-bit wide instructions
• 8-bit wide data path
• Seven or eight special function hardware registers
• Two-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 1
PIC16C5X
Pin Diagrams
PDIP, SOIC, Windowed CERDIP
PDIP, SOIC, Windowed CERDIP
18
17
16
15
14
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
T0CKI
•1
2
3
4
5
6
7
8
9
RA2
RA3
T0CKI
•1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
VDD
N/C
VSS
N/C
RA0
RA1
RA2
RA3
OSC1/CLKIN
3
OSC2/CLKOUT
RC7
MCLR/VPP
VSS
4
5
RC6
RB7
RB6
RB5
RB4
13
12
RB0
RB1
RB2
RB3
6
RC5
RC4
RC3
11
10
7
8
RC2
9
RC1
RC0
RB0
RB1
RB2
RB3
RB4
10
11
12
13
14
RB7
RB6
RB5
SSOP
SSOP
VSS
•1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RA2
RA3
T0CKI
MCLR/VPP
VSS
•1
2
3
4
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
T0CKI
VDD
VDD
RA0
RA1
RA2
RA3
RB0
RB1
RB2
RB3
RB4
VSS
5
6
7
8
VDD
VDD
RB7
RB6
RB5
RB4
VSS
RB0
RB1
9
10
11
12
13
14
RB2
RB3
9
10
RC0
RB7
RB6
RB5
DS30453C-page 2
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
Device Differences
Device
Oscillator
Selection
(Program)
Process
Technology
(Microns)
Voltage
Range
ROM
Equivalent
MCLR
Filter
Oscillator
PIC16C54
2.5-6.25
2.0-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-6.25
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
Factory
User
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
See Note 1
1.2
0.9
0.7
1.7
0.7
1.7
0.7
1.2
0.7
0.7
1.2
0.7
0.7
0.7
0.7
PIC16CR54A
No
No
PIC16C54A
PIC16C54C
PIC16C55
—
User
PIC16CR54C
Yes
No
Factory
User
—
PIC16C55A
PIC16C56
—
Yes
No
Factory
User
—
PIC16CR56A
—
PIC16C56A
PIC16C57
Yes
No
Factory
User
PIC16C57C
PIC16C58B
PIC16CR54A
PIC16CR54C
PIC16CR56A
PIC16CR57C
PIC16CR58B
PIC16CR57C
PIC16CR58B
N/A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
User
Factory
Factory
Factory
Factory
Factory
N/A
N/A
N/A
N/A
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
Note: The table shown above shows the generic names of the PIC16C5X devices. For device varieties,
please refer to Section 2.0.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 3
PIC16C5X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C5X Device Varieties ......................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 25
6.0 Timer0 Module and TMR0 Register ........................................................................................................................................... 27
7.0 Special Features of the CPU...................................................................................................................................................... 31
8.0 Instruction Set Summary............................................................................................................................................................ 43
9.0 Development Support................................................................................................................................................................. 55
10.0 Electrical Characteristics - PIC16C54/55/56/57 ......................................................................................................................... 61
11.0 DC and AC Characteristics - PIC16C54/55/56/57...................................................................................................................... 73
12.0 Electrical Characteristics - PIC16CR54A ................................................................................................................................... 81
13.0 Electrical Characteristics - PIC16C54A...................................................................................................................................... 93
14.0 DC and AC Characteristics - PIC16C54A ................................................................................................................................ 105
15.0 Electrical Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B......................................... 115
16.0 DC and AC Characteristics - PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ..................................... 127
17.0 Packaging Information.............................................................................................................................................................. 137
Appendix A: Compatibility .................................................................................................................................................................. 149
Index .................................................................................................................................................................................................. 151
On-Line Support................................................................................................................................................................................. 153
Reader Response .............................................................................................................................................................................. 154
PIC16C5X Product Identification System .......................................................................................................................................... 155
PIC16C54/55/56/57 Product Identification System ........................................................................................................................... 156
To Our Valued Customers
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revi-
sion of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
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DS30453C-page 4
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
1.1
Applications
1.0
GENERAL DESCRIPTION
The PIC16C5X from Microchip Technology is a family
of low-cost, high performance, 8-bit, fully static,
EPROM/ROM-based CMOS microcontrollers. It
employs a RISC architecture with only 33 single
word/single cycle instructions. All instructions are sin-
gle cycle (200 ns) except for program branches which
take two cycles. The PIC16C5X delivers performance
an order of magnitude higher than its competitors in the
same price category. The 12-bit wide instructions are
highly symmetrical resulting in 2:1 code compression
over other 8-bit microcontrollers in its class. The easy
to use and easy to remember instruction set reduces
development time significantly.
The PIC16C5X series fits perfectly in applications rang-
ing from high-speed automotive and appliance motor
control to low-power remote transmitters/receivers,
pointing devices and telecom processors. The EPROM
technology makes customizing application programs
(transmitter codes, motor speeds, receiver frequen-
cies, etc.) extremely fast and convenient. The small
footprint packages, for through hole or surface mount-
ing, make this microcontroller series perfect for applica-
tions with space limitations. Low-cost, low-power, high
performance, ease of use and I/O flexibility make the
PIC16C5X series very versatile even in areas where no
microcontroller use has been considered before (e.g.,
timer functions, replacement of “glue” logic in larger
systems, co-processor applications).
The PIC16C5X products are equipped with special fea-
tures that reduce system cost and power requirements.
The Power-on Reset (POR) and Device Reset Timer
(DRT) eliminate the need for external reset circuitry.
There are four oscillator configurations to choose from,
including the power-saving LP (Low Power) oscillator
and cost saving RC oscillator. Power saving SLEEP
mode, Watchdog Timer and Code Protection features
improve system cost, power and reliability.
The UV erasable CERDIP packaged versions are ideal
for code development, while the cost-effective One
Time Programmable (OTP) versions are suitable for
production in any volume. The customer can take full
advantage of Microchip’s price leadership in OTP
microcontrollers, while benefiting from the OTP’s
flexibility.
The PIC16C5X products are supported by
a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a low-cost development program-
mer and a full featured programmer. All the tools are
supported on IBM PC and compatible machines.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 5
PIC16C5X
TABLE 1-1:
PIC16C5X FAMILY OF DEVICES
PIC16C54
PIC16CR54
20
PIC16C55
PIC16C56
PIC16CR56
20
Maximum Frequency
of Operation (MHz)
20
20
20
1K
—
Clock
EPROM Program Memory
(x12 words)
512
—
512
—
Memory
ROM Program Memory
(x12 words)
—
512
—
1K
RAM Data Memory (bytes)
Timer Module(s)
I/O Pins
25
25
24
25
25
Peripherals
Features
TMR0
12
TMR0
12
TMR0
20
TMR0
12
TMR0
12
Number of Instructions
Packages
33
33
33
33
33
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
28-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
20-pin SSOP
20-pin SSOP
28-pin SSOP
20-pin SSOP
20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O
current capability.
PIC16C57
20
PIC16CR57
20
PIC16C58
20
PIC16CR58
20
Maximum Frequency
of Operation (MHz)
Clock
EPROM Program Memory
(x12 words)
2K
—
2K
—
Memory
ROM Program Memory
(x12 words)
—
2K
—
2K
RAM Data Memory (bytes)
72
72
73
73
Peripherals Timer Module(s)
TMR0
20
TMR0
20
TMR0
12
TMR0
12
I/O Pins
Number of Instructions
Packages
33
33
33
33
Features
28-pin DIP,
SOIC;
28-pin DIP,
SOIC;
18-pin DIP,
SOIC;
18-pin DIP,
SOIC;
28-pin SSOP 28-pin SSOP
20-pin SSOP 20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code
Protect and high I/O current capability.
DS30453C-page 6
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
2.3
Quick-Turnaround-Production (QTP)
Devices
2.0
PIC16C5X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in this section. When placing
orders, please use the PIC16C5X Product Identifica-
tion System at the back of this data sheet to specify the
correct part number.
Microchip offers a QTP Programming Service for fac-
tory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi-
lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your
Microchip Technology sales office for more details.
For the PIC16C5X family of devices, there are four
device types, as indicated in the device number:
1. C, as in PIC16C54C. These devices have
EPROM program memory and operate over the
standard voltage range.
2.4
Serialized
Quick-Turnaround-Production
(SQTPSM) Devices
2. LC, as in PIC16LC54A. These devices have
EPROM program memory and operate over an
extended voltage range.
Microchip offers the unique programming service
where a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or sequen-
tial. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory.
3. CR, as in PIC16CR54A. These devices have
ROM program memory and operate over the
standard voltage range.
4. LCR, as in PIC16LCR54A. These devices have
ROM program memory and operate over an
extended voltage range.
2.1
UV Erasable Devices (EPROM)
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
The UV erasable versions, offered in CERDIP pack-
ages, are optimal for prototype development and pilot
programs.
2.5
Read Only Memory (ROM) Devices
UV erasable devices can be programmed for any of the
four oscillator configurations. Microchip’s PICSTART
and PRO MATE programmers both support program-
ming of the PIC16C5X. Third party programmers also
are available. Refer to the Third Party Guide for a list of
sources.
Microchip offers masked ROM versions of several of
the highest volume parts, giving the customer a low
cost option for high volume, mature products.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.
The OTP devices, packaged in plastic packages, per-
mit the user to program them once. In addition to the
program memory, the configuration bits must be pro-
grammed.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 7
PIC16C5X
NOTES:
DS30453C-page 8
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
The PIC16C5X device contains an 8-bit ALU and work-
ing register. The ALU is a general purpose arithmetic
unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C5X family can be
attributed to a number of architectural features com-
monly found in RISC microprocessors. To begin with,
the PIC16C5X uses a Harvard architecture in which
program and data are accessed on separate buses.
This improves bandwidth over traditional von Neumann
architecture where program and data are fetched on
the same bus. Separating program and data memory
further allows instructions to be sized differently than
the 8-bit wide data word. Instruction opcodes are
12-bits wide making it possible to have all single word
instructions. A 12-bit wide program memory access
bus fetches a 12-bit instruction in a single cycle. A
two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions (33) execute
in a single cycle (200ns @ 20MHz) except for program
branches.
The ALU is 8-bits wide and capable of addition, sub-
traction, shift and logical operations. Unless otherwise
mentioned, arithmetic operations are two's comple-
ment in nature. In two-operand instructions, typically
one operand is the W (working) register. The other
operand is either a file register or an immediate con-
stant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a borrow and digit borrow out bit, respec-
tively, in subtraction. See the SUBWF and ADDWF
instructions for examples.
The PIC16C54/CR54 and PIC16C55 address 512 x 12
of program memory, the PIC16C56/CR56 address
1K x 12 of program memory, and the PIC16C57/CR57
and PIC16C58/CR58 address 2K x 12 of program
memory. All program memory is internal.
A simplified block diagram is shown in Figure 3-1, with
the corresponding device pins described in Table 3-1.
The PIC16C5X can directly or indirectly address its
register files and data memory. All special function reg-
isters including the program counter are mapped in the
data memory. The PIC16C5X has a highly orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C5X simple yet efficient. In addition, the learning
curve is reduced significantly.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 9
PIC16C5X
FIGURE 3-1: PIC16C5X SERIES BLOCK DIAGRAM
9-11
T0CKI
PIN
OSC1 OSC2 MCLR
CONFIGURATION WORD
9-11
EPROM/ROM
512 X 12 TO
2048 X 12
STACK 1
STACK2
“DISABLE” “OSC
PC
SELECT”
WATCHDOG
TIMER
12
2
“CODE
OSCILLATOR/
TIMING &
CONTROL
PROTECT”
INSTRUCTION
REGISTER
WDT TIME
OUT
CLKOUT
WDT/TMR0
PRESCALER
9
12
8
“SLEEP”
INSTRUCTION
DECODER
6
“OPTION”
OPTION REG.
FROM W
DIRECT ADDRESS
DIRECT RAM
ADDRESS
GENERAL
PURPOSE
REGISTER
FILE
5
5-7
8
(SRAM)
24, 25, 72 or
73 Bytes
STATUS
TMR0
FSR
8
DATA BUS
8
W
ALU
FROM W
8
FROM W
4
FROM W
8
8
4
8
“TRIS 5”
“TRIS 6”
“TRIS 7”
TRISB PORTB
TRISA PORTA
TRISC
PORTC
8
4
8
RC<7:0>
(28-Pin
RA<3:0>
RB<7:0>
Devices Only)
DS30453C-page 10
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
TABLE 3-1:
Name
PINOUT DESCRIPTION - PIC16C54s, PIC16CR54, PIC16C56, PIC16CR56,
PIC16C58, PIC16CR58
DIP, SOIC SSOP I/O/P Input
Description
No.
No. Type Levels
RA0
RA1
RA2
RA3
17
18
1
19
20
1
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
2
2
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
6
7
8
7
8
9
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
TTL
TTL
TTL
TTL
9
10
11
12
13
T0CKI
3
3
I
ST
Clock input to Timer0. Must be tied to VSS or VDD, if not in
use, to reduce current consumption.
MCLR/VPP
4
4
I
ST
Master clear (RESET) input/programming voltage input. This
pin is an active low RESET to the device. Voltage on the
MCLR/VPP pin must not exceed VDD to avoid unintended
entering of programming mode.
OSC1/CLKIN
16
15
18
17
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT, which has 1/4 the frequency of OSC1 and denotes
the instruction cycle rate.
VDD
VSS
14
5
15,16
5,6
P
P
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 11
PIC16C5X
TABLE 3-2:
PINOUT DESCRIPTION - PIC16C55, PIC16C57, PIC16CR57
DIP, SOIC SSOP I/O/P Input
Name
Description
No.
No. Type Levels
RA0
RA1
RA2
RA3
6
7
8
9
5
6
7
8
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
10
11
12
13
14
15
16
17
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
10
11
12
13
15
16
17
TTL
TTL
TTL
TTL
TTL
TTL
TTL
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
18
19
20
21
22
23
24
25
18
19
20
21
22
23
24
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL Bi-directional I/O port
TTL
TTL
TTL
TTL
TTL
TTL
TTL
T0CKI
1
2
I
ST
Clock input to Timer0. Must be tied to VSS or VDD if not in use
to reduce current consumption.
MCLR
28
28
I
ST
Master clear (RESET) input. This pin is an active low RESET
to the device.
OSC1/CLKIN
27
26
27
26
I
ST
Oscillator crystal input/external clock source input.
OSC2/CLKOUT
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
VDD
VSS
N/C
2
4
3,4
1,14
—
P
P
—
—
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Unused, do not connect.
3,5
—
Legend: I = input, O = output, I/O = input/output, P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input
DS30453C-page 12
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
3.1
Clocking Scheme/Instruction Cycle
3.2
Instruction Flow/Pipelining
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter is incremented every Q1 and the instruc-
tion is fetched from program memory and latched into
the instruction register in Q4. It is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow are shown in Figure 3-2
and Example 3-1.
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are pipe-
lined such that fetch takes one instruction cycle, while
decode and execute takes another instruction cycle.
However, due to the pipelining, each instruction effec-
tively executes in one cycle. If an instruction causes the
program counter to change (e.g., GOTO), then two
cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q2
Q3
Q4
Q2
Q3
Q4
Q2
Q3
Q4
Q1
Q1
Q1
OSC1
Q1
Q2
Q3
Q4
PC
Internal
phase
clock
PC
PC+1
PC+2
OSC2/CLKOUT
(RC mode)
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55H
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
3. CALL SUB_1
Execute 2
Fetch 3
Execute 3
Fetch 4
4. BSF
PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 13
PIC16C5X
NOTES:
DS30453C-page 14
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
FIGURE 4-2: PIC16C56/CR56 PROGRAM
MEMORY MAP AND STACK
4.0
MEMORY ORGANIZATION
PIC16C5X memory is organized into program memory
and data memory. For devices with more than 512
bytes of program memory, a paging scheme is used.
Program memory pages are accessed using one or two
STATUS Register bits. For devices with a data memory
register file of more than 32 registers, a banking
scheme is used. Data memory banks are accessed
using the File Selection Register (FSR).
PC<9:0>
10
CALL, RETLW
Stack Level 1
Stack Level 2
000h
On-chip Program
0FFh
Memory (Page 0)
100h
4.1
Program Memory Organization
1FFh
200h
The PIC16C54, PIC16CR54 and PIC16C55 have a
9-bit Program Counter (PC) capable of addressing a
512 x 12 program memory space (Figure 4-1). The
PIC16C56 and PIC16CR56 have a 10-bit Program
Counter (PC) capable of addressing a 1K x 12 program
memory space (Figure 4-2). The PIC16CR57,
PIC16C58 and PIC16CR58 have an 11-bit Program
Counter capable of addressing a 2K x 12 program
memory space (Figure 4-3). Accessing a location
above the physically implemented address will cause a
wraparound.
On-chip Program
2FFh
Memory (Page 1)
300h
RESET Vector
3FFh
FIGURE 4-3: PIC16C57/CR57/C58/
CR58 PROGRAM MEMORY
MAP AND STACK
A NOPat the RESET vector location will cause a restart
at location 000h. The RESET vector for the PIC16C54,
PIC16CR54 and PIC16C55 is at 1FFh. The RESET
vector for the PIC16C56 and PIC16CR56 is at 3FFh.
The RESET vector for the PIC16C57, PIC16CR57,
PIC16C58, and PIC16CR58 is at 7FFh.
PC<10:0>
11
CALL, RETLW
Stack Level 1
Stack Level 2
000h
FIGURE 4-1: PIC16C54/CR54/C55
PROGRAM MEMORY MAP
AND STACK
On-chip Program
0FFh
Memory (Page 0)
100h
1FFh
200h
PC<8:0>
On-chip Program
2FFh
9
CALL, RETLW
Memory (Page 1)
300h
Stack Level 1
Stack Level 2
3FFh
400h
On-chip Program
4FFh
000h
Memory (Page 2)
500h
On-chip
Program
Memory
5FFh
600h
0FFh
100h
On-chip Program
6FFh
Memory (Page 3)
700h
RESET Vector
7FFh
RESET Vector
1FFh
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 15
PIC16C5X
4.2
Data Memory Organization
FIGURE 4-4: PIC16C54, PIC16CR54,
PIC16C55, PIC16C56,
PIC16CR56 REGISTER FILE
MAP
Data memory is composed of registers, or bytes of
RAM. Therefore, data memory for a device is specified
by its register file. The register file is divided into two
functional groups: Special Function Registers and
General Purpose Registers.
File Address
INDF(1)
00h
The Special Function Registers include the TMR0 reg-
ister, the Program Counter (PC), the Status Register,
the I/O registers (ports) and the File Select Register
(FSR). In addition, Special Purpose Registers are used
to control the I/O port configuration and prescaler
options.
01h
02h
03h
04h
05h
06h
07h
TMR0
PCL
STATUS
FSR
PORTA
PORTB
The General Purpose Registers are used for data and
control information under command of the instructions.
PORTC(2)
For the PIC16C54, PIC16CR54, PIC16C56 and
PIC16CR56, the register file is composed of 7 Special
Function Registers and 25 General Purpose Registers
(Figure 4-4).
08h
General
Purpose
Registers
0Fh
10h
For the PIC16C55, the register file is composed of 8
Special Function Registers and 24 General Purpose
Registers.
For the PIC16C57 and PIC16CR57, the register file is
composed of 8 Special Function Registers, 24 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 4-5).
1Fh
Note 1: Not a physical register. See Section 4.7.
2: PIC16C55 only, in all other devices this is
implemented as a a general purpose register.
For the PIC16C58 and PIC16CR58, the register file is
composed of 7 Special Function Registers, 25 General
Purpose Registers and up to 48 additional General
Purpose Registers that may be addressed using a
banking scheme (Figure 4-6).
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly or indirectly
through the File Select Register (FSR). The FSR Reg-
ister is described in Section 4.7.
DS30453C-page 16
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
FIGURE 4-5: PIC16C57/CR57 REGISTER FILE MAP
FSR<6:5>
File Address
00h
00
01
10
11
INDF(1)
TMR0
PCL
20h
40h
60h
01h
02h
03h
04h
05h
06h
STATUS
FSR
Addresses map back to
addresses in Bank 0.
PORTA
PORTB
07h
08h
PORTC
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
10h
1Fh
70h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: Not a physical register. See Section 4.7.
FIGURE 4-6: PIC16C58/CR58 REGISTER FILE MAP
FSR<6:5>
File Address
00h
00
01
10
11
INDF(1)
TMR0
PCL
20h
40h
60h
01h
02h
03h
04h
05h
STATUS
FSR
Addresses map back to
addresses in Bank 0.
PORTA
PORTB
06h
07h
General
Purpose
Registers
2Fh
30h
4Fh
50h
6Fh
0Fh
10h
1Fh
70h
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
General
Purpose
Registers
3Fh
5Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
Note 1: Not a physical register. See Section 4.7.
DS30453C-page 17
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions to control the opera-
tion of the device (Table 4-1).
The Special Registers can be classified into two sets.
The Special Function Registers associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section for each peripheral feature.
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on
Power-on
Reset
Value on
MCLR and
WDT Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
N/A
00h
01h
TRIS
I/O Control Registers (TRISA, TRISB, TRISC)
Contains control bits to configure Timer0 and Timer0/WDT prescaler
1111 1111
--11 1111
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
OPTION
INDF
Uses contents of FSR to address data memory (not a physical register) xxxx xxxx
TMR0
8-bit real-time clock/counter
Low order 8 bits of PC
xxxx xxxx
(1)
02h
03h
04h
05h
06h
PCL
1111 1111
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
1111 1111
000q quuu
STATUS
FSR
PA2
PA1
PA0
TO
PD
Z
DC
C
(3)
(3)
Indirect data memory address pointer
1uuu uuuu
---- uuuu
uuuu uuuu
PORTA
PORTB
—
—
—
—
RA3
RB3
RA2
RB2
RA1
RB1
RA0
RB0
RB7
RB6
RB5
RB4
(2)
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
Legend: Shaded boxes = unimplemented or unused, –= unimplemented, read as ’0’ (if applicable)
x= unknown, u= unchanged, q= see the tables in Section 7.7 for possible values.
Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5 for an explanation of how to access
these bits.
2: File address 07h is a General Purpose Register on the PIC16C54, PIC16CR54, PIC16C56, PIC16CR56, PIC16C58 and
PIC16CR58.
3: For the PIC16C54 and PIC16C55, the value on RESET is 111x xxxxand for MCLR and WDT Reset, the value is
111u uuuu.
DS30453C-page 18
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
For example, CLRF STATUSwill clear the upper three
bits and set the Z bit. This leaves the STATUS Register
as 000u u1uu(where u= unchanged).
4.3
STATUS Register
This register contains the arithmetic status of the ALU,
the RESET status, and the page preselect bits for pro-
gram memories larger than 512 words.
It is recommended, therefore, that only BCF, BSFand
MOVWFinstructions be used to alter the STATUS Regis-
ter because these instructions do not affect the Z, DC
or C bits from the STATUS Register. For other instruc-
tions which do affect STATUS Bits, see Section 8.0,
Instruction Set Summary.
The STATUS Register can be the destination for any
instruction, as with any other register. If the STATUS
Register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS Register as destination may be different than
intended.
REGISTER 4-1: STATUS REGISTER (ADDRESS:03h)
R/W-0
PA2
R/W-0
PA1
R/W-0
PA0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7
6
5
4
3
2
1
bit0
bit 7:
PA2: This bit unused at this time.
Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward
compatibility with future products.
bit 6-5: PA<1:0>: Program page preselect bits (PIC16C56/CR56)(PIC16C57/CR57)(PIC16C58/CR58)
00= Page 0 (000h - 1FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
01= Page 1 (200h - 3FFh) - PIC16C56/CR56, PIC16C57/CR57, PIC16C58/CR58
10= Page 2 (400h - 5FFh) - PIC16C57/CR57, PIC16C58/CR58
11= Page 3 (600h - 7FFh) - PIC16C57/CR57, PIC16C58/CR58
Each page is 512 words.
Using the PA<1:0> bits as general purpose read/write bits in devices which do not use them for program
page preselect is not recommended since this may affect upward compatibility with future products.
bit 4:
bit 3:
bit 2:
bit 1:
TO: Time-out bit
1= After power-up, CLRWDTinstruction, or SLEEPinstruction
0= A WDT time-out occurred
PD: Power-down bit
1= After power-up or by the CLRWDTinstruction
0= By execution of the SLEEPinstruction
Z: Zero bit
1= The result of an arithmetic or logic operation is zero
0= The result of an arithmetic or logic operation is not zero
DC: Digit carry/borrow bit (for ADDWFand SUBWFinstructions)
ADDWF
1= A carry from the 4th low order bit of the result occurred
0= A carry from the 4th low order bit of the result did not occur
SUBWF
1= A borrow from the 4th low order bit of the result did not occur
0= A borrow from the 4th low order bit of the result occurred
bit 0:
C: Carry/borrow bit (for ADDWF, SUBWFand RRF, RLFinstructions)
ADDWF
SUBWF
RRF or RLF
1= A carry occurred
0= A carry did not occur
1= A borrow did not occur
0= A borrow occurred
Loaded with LSb or MSb, respectively
DS30453C-page 19
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
4.4
OPTION Register
The OPTION Register is a 6-bit wide, write-only regis-
ter which contains various control bits to configure the
Timer0/WDT prescaler and Timer0.
By executing the OPTION instruction, the contents of
the W Register will be transferred to the OPTION Reg-
ister. A RESET sets the OPTION<5:0> bits.
REGISTER 4-2: OPTION REGISTER
U-0
U-0
—
6
W-1
T0CS
5
W-1
T0SE
4
W-1
PSA
3
W-1
PS2
2
W-1
PS1
1
W-1
PS0
—
W
U
= Writable bit
= Unimplemented bit
bit7
bit0
- n = Value at POR reset
bit 7-6: Unimplemented.
bit 5:
bit 4:
bit 3:
T0CS: Timer0 clock source select bit
1= Transition on T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: Timer0 source edge select bit
1= Increment on high-to-low transition on T0CKI pin
0= Increment on low-to-high transition on T0CKI pin
PSA: Prescaler assignment bit
1= Prescaler assigned to the WDT
0= Prescaler assigned to Timer0
bit 2-0: PS<2:0>: Prescaler rate select bits
Bit Value
Timer0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
DS30453C-page 20
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
4.5
Program Counter
FIGURE 4-7: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C54, PIC16CR54,
PIC16C55
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next pro-
gram instruction to be executed. The PC value is
increased by one, every instruction cycle, unless an
instruction changes the PC.
GOTO Instruction
8
7
0
For a GOTOinstruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0> (Figure 4-7 and Figure 4-8).
PCL
PC
Instruction Word
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page num-
ber must be supplied as well. Bit5 and bit6 of the STA-
TUS Register provide page information to bit9 and
bit10 of the PC (Figure 4-8 and Figure 4-9).
CALL or Modify PCL Instruction
8
7
0
PCL
PC
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are pro-
vided by the instruction word. However, PC<8> does
not come from the instruction word, but is always
cleared (Figure 4-7 and Figure 4-8).
Reset to ’0’
Instruction Word
FIGURE 4-8: LOADING OF PC
BRANCH INSTRUCTIONS -
PIC16C56/PIC16CR56
Instructions where the PCL is the destination, or Modify
PCL instructions, include MOVWF PC, ADDWF PC,and
BSF PC,5.
GOTO Instruction
For the PIC16C56, PIC16CR56, PIC16C57,
PIC16CR57, PIC16C58 and PIC16CR58, a page num-
ber again must be supplied. Bit5 and bit6 of the STA-
TUS Register provide page information to bit9 and
bit10 of the PC (Figure 4-8 and Figure 4-9).
10
9
8
7
0
PC
PCL
Instruction Word
Note: Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
2
PA<1:0>
7
0
STATUS
CALL or Modify PCL Instruction
10
9
8
7
0
PC
PCL
Instruction Word
Reset to ‘0’
PA<1:0>
2
7
0
STATUS
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 21
PIC16C5X
FIGURE 4-9: LOADING OF PC
4.6
Stack
BRANCH INSTRUCTIONS -
PIC16C57/PIC16CR57, AND
PIC16C58/PIC16CR58
PIC16C5X devices have a 10-bit or 11-bit wide,
two-level hardware push/pop stack.
A CALLinstruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only the
most recent two return addresses are stored.
GOTO Instruction
10
9
8
7
0
PC
PCL
A RETLWinstruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W Register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the pro-
gram memory.
Instruction Word
2
PA<1:0>
7
0
STATUS
CALL or Modify PCL Instruction
10
9
8
7
0
For the RETLW instruction, the PC is loaded with the
Top of Stack (TOS) contents. All of the devices covered
in this data sheet have a two-level stack. The stack has
the same bit width as the device PC.
PC
PCL
Instruction Word
Reset to ‘0’
PA<1:0>
4.7
Indirect Data Addressing; INDF and
FSR Registers
2
7
0
The INDF Register is not
a physical register.
STATUS
Addressing INDF actually addresses the register
whose address is contained in the FSR Register (FSR
is a pointer). This is indirect addressing.
4.5.1
PAGING CONSIDERATIONS –
PIC16C56/CR56, PIC16C57/CR57 AND
PIC16C58/CR58
EXAMPLE 4-1: INDIRECT ADDRESSING
• Register file 08 contains the value 10h
• Register file 09 contains the value 0Ah
• Load the value 08 into the FSR Register
• A read of the INDF Register will return the value
of 10h
• Increment the value of the FSR Register by one
(FSR = 09h)
• A read of the INDR register now will return the
value of 0Ah.
If the Program Counter is pointing to the last address of
a selected memory page, when it increments it will
cause the program to continue in the next higher page.
However, the page preselect bits in the STATUS Reg-
ister will not be updated. Therefore, the next GOTO,
CALLor modify PCL instruction will send the program
to the page specified by the page preselect bits (PA0 or
PA<1:0>).
For example, a NOP at location 1FFh (page 0) incre-
ments the PC to 200h (page 1). A GOTO xxxat 200h
will return the program to address 0xxh on page 0
(assuming that PA<1:0> are clear).
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF Register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 10h-1Fh
using indirect addressing is shown in Example 4-2.
To prevent this, the page preselect bits must be
updated under program control.
4.5.2
EFFECTS OF RESET
EXAMPLE 4-2: HOW TO CLEAR RAM
USING INDIRECT
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page (e.g., the RESET vector).
ADDRESSING
movlw
movwf
clrf
incf
btfsc
goto
0x10
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF Register
;inc pointer
;all done?
;NO, clear next
The STATUS Register page preselect bits are cleared
upon
pre-selected.
NEXT
a RESET, which means that page 0 is
Therefore, upon a RESET, a GOTO instruction at the
RESET vector location will automatically cause the pro-
gram to jump to page 0.
CONTINUE
:
;YES, continue
DS30453C-page 22
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
The FSR is either a 5-bit (PIC16C54, PIC16CR54,
PIC16C55), 6-bit (PIC16C56, PIC16CR56), or 7-bit
(PIC16C57s, PIC16CR57, PIC16C58, PIC16CR58)
wide register. It is used in conjunction with the INDF
Register to indirectly address the data memory area.
PIC16C54, PIC16CR54, PIC16C55: These do not use
banking. FSR<6:5> bits are unimplemented and read
as ’1’s.
PIC16C57, PIC16CR57, PIC16C58, PIC16CR58:
FSR<6:5> are the bank select bits and are used to
select the bank to be addressed (00 = bank 0,
01= bank 1, 10= bank 2, 11= bank 3).
The FSR<4:0> bits are used to select data memory
addresses 00h to 1Fh.
FIGURE 4-10: DIRECT/INDIRECT ADDRESSING
Direct Addressing
Indirect Addressing
(FSR)
4
(opcode)
0
5
(FSR)
0
6
4
5
6
location select
bank select
location select
bank
00
01
10
11
00h
Addresses map back to
addresses in Bank 0.
Data
Memory
0Fh
10h
(1)
1Fh
Bank 0
3Fh
Bank 1
5Fh
Bank 2
7Fh
Bank 3
Note 1: For register map detail see Section 4.2.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 23
PIC16C5X
NOTES:
DS30453C-page 24
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
5.5
I/O Interfacing
5.0
I/O PORTS
As with any other register, the I/O Registers can be
written and read under program control. However, read
instructions (e.g., MOVF PORTB,W) always read the I/O
pins independent of the pin’s input/output modes. On
RESET, all I/O ports are defined as input (inputs are at
hi-impedance) since the I/O control registers (TRISA,
TRISB, TRISC) are all set.
The equivalent circuit for an I/O port pin is shown in
Figure 5-1. All ports may be used for both input and
output operation. For input operations these ports are
non-latching. Any input must be present until read by
an input instruction (e.g., MOVF PORTB, W). The out-
puts are latched and remain unchanged until the output
latch is rewritten. To use a port pin as output, the corre-
sponding direction control bit (in TRISA, TRISB) must
be cleared (= 0). For use as an input, the corresponding
TRIS bit must be set. Any I/O pin can be programmed
individually as input or output.
5.1
PORTA
PORTA is a 4-bit I/O Register. Only the low order 4 bits
are used (RA<3:0>). Bits 7-4 are unimplemented and
read as '0's.
FIGURE 5-1: EQUIVALENT CIRCUIT
FOR A SINGLE I/O PIN
5.2
PORTB
Data
Bus
PORTB is an 8-bit I/O Register (PORTB<7:0>).
D
Q
Q
Data
Latch
5.3
PORTC
VDD
P
WR
Port
CK
PORTC is an 8-bit I/O Register for PIC16C55,
PIC16C57 and PIC16CR57.
PORTC is a General Purpose Register for PIC16C54,
PIC16CR54, PIC16C56, PIC16C58 and PIC16CR58.
N
I/O
pin(1)
W
Reg
D
Q
Q
5.4
TRIS Registers
TRIS
Latch
VSS
The Output Driver Control Registers are loaded with
the contents of the W Register by executing the TRIS
finstruction. A '1' from a TRIS Register bit puts the
corresponding output driver in a hi-impedance (input)
mode. A '0' puts the contents of the output data latch
on the selected pins, enabling the output buffer.
TRIS ‘f’
CK
RESET
Note:
A read of the ports reads the pins, not the
output data latches. That is, if an output
driver on a pin is enabled and driven high,
but the external system is holding it low, a
read of the port will indicate that the pin is
low.
RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
The TRIS Registers are “write-only” and are set (output
drivers disabled) upon RESET.
TABLE 5-1:
SUMMARY OF PORT REGISTERS
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
05h
06h
07h
TRIS
PORTA
I/O Control Registers (TRISA, TRISB, TRISC)
1111 1111 1111 1111
---- xxxx ---- uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
—
—
RA3
RB3
RC3
RA2
RB2
RC2
RA1
RB1
RC1
RA0
RB0
RC0
PORTB
PORTC
RB7
RC7
RB6
RC6
RB5
RC5
RB4
RC4
Legend: Shaded boxes = unimplemented, read as ‘0’, — = unimplemented, read as '0', x= unknown, u= unchanged
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 25
PIC16C5X
5.6
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-1: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.6.1
Some instructions operate internally as read followed
by write operations. The BCFand BSFinstructions, for
example, read the entire port into the CPU, execute the
bit operation and re-write the result. Caution must be
used when these instructions are applied to a port
where one or more pins are used as input/outputs. For
example, a BSFoperation on bit5 of PORTB will cause
all eight bits of PORTB to be read into the CPU, bit5 to
be set and the PORTB value to be written to the output
latches. If another bit of PORTB is used as a bi-direc-
tional I/O pin (say bit0) and it is defined as an input at
this time, the input signal present on the pin itself would
be read into the CPU and rewritten to the data latch of
this particular pin, overwriting the previous content. As
long as the pin stays in the input mode, no problem
occurs. However, if bit0 is switched into output mode
later on, the content of the data latch may now be
unknown.
;Initial PORT Settings
; PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
;
PORT latch PORT pins
---------- ----------
BCF
BCF
MOVLW 03Fh
PORTB, 7
PORTB, 6
;01pp pppp
;10pp pppp
;
11pp pppp
11pp pppp
TRIS PORTB
;10pp pppp
10pp pppp
;
;Note that the user may have expected the pin
;values to be 00pp pppp. The 2nd BCF caused
;RB7 to be latched as the pin value (High).
5.6.2
SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-2). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction, which causes that file to be
read into the CPU, is executed. Otherwise, the previous
state of that pin may be read into the CPU rather than
the new state. When in doubt, it is better to separate
these instructions with a NOPor another instruction not
accessing this I/O port.
Example 5-1 shows the effect of two sequential
read-modify-write instructions (e.g., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a high or a low should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
FIGURE 5-2: SUCCESSIVE I/O OPERATION
Q4
Q4
Q4
Q4
Q3
Q3
Q3
Q3
Q1 Q2
PC
Q1 Q2
Q1 Q2
Q1 Q2
PC + 3
NOP
PC + 1
PC + 2
NOP
Instruction
fetched
MOVWF PORTB MOVF PORTB,W
This example shows a write
to PORTB followed by a read
from PORTB.
RB<7:0>
Port pin
written here
Port pin
sampled here
Instruction
executed
MOVWF PORTB MOVF PORTB,W
NOP
(Write to
PORTB)
(Read
PORTB)
DS30453C-page 26
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode, Timer0 will increment
either on every rising or falling edge of pin T0CKI. The
incrementing edge is determined by the source edge
select bit T0SE (OPTION<4>). Clearing the T0SE bit
selects the rising edge. Restrictions on the external
clock input are discussed in detail in Section 6.1.
6.0
TIMER0 MODULE AND
TMR0 REGISTER
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Note: The prescaler may be used by either the
Timer0 module or the Watchdog Timer, but
not both.
Figure 6-1 is a simplified block diagram of the Timer0
module, while Figure 6-2 shows the electrical structure
of the Timer0 input.
The prescaler assignment is controlled in software by
the control bit PSA (OPTION<3>). Clearing the PSA bit
will assign the prescaler to Timer0. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4,...,
1:256 are selectable. Section 6.2 details the operation
of the prescaler.
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two cycles (Figure 6-3 and Figure 6-4).
The user can work around this by writing an adjusted
value to the TMR0 register.
A summary of registers associated with the Timer0
module is found in Table 6-1.
FIGURE 6-1: TIMER0 BLOCK DIAGRAM
Data Bus
FOSC/4
0
1
PSout
8
1
0
Sync with
Internal
Clocks
TMR0 reg
T0CKI
pin
Programmable
PSout
Sync
(2)
Prescaler
(1)
(2 cycle delay)
T0SE
3
(1)
(1)
PS2, PS1, PS0
PSA
(1)
T0CS
Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.
2: The prescaler is shared with the Watchdog Timer (Figure 6-6).
FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN
RIN
T0CKI
pin
(1)
Schmitt Trigger
Input Buffer
N
(1)
VSS
VSS
Note 1: ESD protection circuits.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 27
PIC16C5X
FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
Instruction
Fetch
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
T0
T0+1
T0+2
NT0
NT0
NT0
NT0+1
NT0+2
Timer0
Instruction
Executed
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 2
Write TMR0
executed
FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
PC+2
PC+3
PC+4
PC+5
PC+6
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
MOVWF TMR0
Instruction
Fetch
T0
T0+1
NT0+1
NT0
Timer0
Instruction
Execute
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Write TMR0
executed
TABLE 6-1:
Address
REGISTERS ASSOCIATED WITH TIMER0
Value on
Power-on
Reset
Value on
MCLR and
WDT Reset
Name
Bit 7
Timer0 - 8-bit real-time clock/counter
T0CS T0SE PSA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01h
N/A
TMR0
xxxx xxxx uuuu uuuu
PS0 --11 1111 --11 1111
OPTION
—
—
PS2
PS1
Legend: Shaded cells: Unimplemented bits, -= unimplemented, x = unknown, u= unchanged.
DS30453C-page 28
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type pres-
caler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple counter must be taken into account. There-
fore, it is necessary for T0CKI to have a period of at
least 4TOSC (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the mini-
mum pulse width requirement of 10 ns. Refer to param-
eters 40, 41 and 42 in the electrical specification of the
desired device.
6.1
Using Timer0 with an External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-5).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 20 ns) and low for
at least 2TOSC (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
6.1.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 mod-
ule is actually incremented. Figure 6-5 shows the delay
from the external clock edge to the timer incrementing.
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Small pulse
External Clock Input or
misses sampling
Prescaler Output (2)
(1)
External Clock/Prescaler
Output After Sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore,
the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 29
PIC16C5X
6.2
Prescaler
EXAMPLE 6-1: CHANGING PRESCALER
(TIMER0→WDT)
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 6.1.2). For simplic-
ity, this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler may
be used by either the Timer0 module or the WDT, but
not both. Thus, a prescaler assignment for the Timer0
module means that there is no prescaler for the WDT,
and vice-versa.
1.CLRWDT
2.CLRF
;Clear WDT
;Clear TMR0 & Prescaler
3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)
TMR0
4.OPTION
; are required only if
; desired
;PS<2:0> are 000 or
;001
5.CLRWDT
6.MOVLW '00xx1xxx’b ;Set Postscaler to
7.OPTION ; desired WDT rate
The PSA and PS<2:0> bits (OPTION<3:0>) determine
prescaler assignment and prescale ratio.
To change prescaler from the WDT to the Timer0 mod-
ule, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDTinstruction should be executed before switching
the prescaler.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDTinstruction will clear
the prescaler along with the WDT. The prescaler is nei-
ther readable nor writable. On a RESET, the prescaler
contains all '0's.
EXAMPLE 6-2: CHANGING PRESCALER
(WDT→TIMER0)
CLRWDT
MOVLW
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
6.2.1
SWITCHING PRESCALER ASSIGNMENT
'xxxx0xxx'
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program exe-
cution). To avoid an unintended device RESET, the fol-
lowing instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
OPTION
FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TCY ( = FOSC/4)
Data Bus
8
0
M
U
X
1
0
T0CKI
pin
M
U
X
1
Sync
2
Cycles
TMR0 reg
T0SE
T0CS
PSA
0
1
8-bit Prescaler
M
U
X
8
Watchdog
Timer
8 - to - 1MUX
PS<2:0>
PSA
1
0
WDT Enable bit
MUX
PSA
WDT
Time-Out
Note: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
DS30453C-page 30
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
The SLEEP mode is designed to offer a very low cur-
rent power-down mode. The user can wake-up from
SLEEP through external RESET or through a Watch-
dog Timer time-out. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
7.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other proces-
sors are special circuits that deal with the needs of
real-time applications. The PIC16C5X family of micro-
controllers has a host of such features intended to max-
imize system reliability, minimize cost through
elimination of external components, provide power sav-
ing operating modes and offer code protection. These
features are:
7.1
Configuration Bits
Configuration bits can be programmed to select various
device configurations. Two bits are for the selection of
the oscillator type and one bit is the Watchdog Timer
• Oscillator selection
• RESET
enable bit.
Nine bits are code protection bits
• Power-on Reset (POR)
• Device Reset Timer (DRT)
• Watchdog Timer (WDT)
• SLEEP
(Figure 7-1 and Figure 7-2) for the PIC16C54,
PIC16CR54, PIC16C56, PIC16CR56, PIC16C58, and
PIC16CR58 devices.
QTP or ROM devices have the oscillator configuration
programmed at the factory and these parts are tested
accordingly (see "Product Identification System" dia-
grams in the back of this data sheet).
• Code Protection
• ID locations
The PIC16C5X Family has a Watchdog Timer, which
can be shut off only through configuration bit WDTE. It
runs off of its own RC oscillator for added reliability.
There is an 18 ms delay provided by the Device Reset
Timer (DRT), intended to keep the chip in RESET until
the crystal oscillator is stable. With this timer on-chip,
most applications need no external RESET circuitry.
FIGURE 7-1: CONFIGURATION WORD FOR PIC16CR54A/C54C/CR54C/C55A/C56A/CR56A/C57C/
CR57C/C58B/CR58B
CP
CP
10
CP
9
CP
8
CP
7
CP
6
CP
5
CP
4
CP
3
WDTE FOSC1 FOSC0
bit0
Register: CONFIG
(1)
Address
:
FFFh
bit11
2
1
bit 11-3: CP: Code protection bits
1= Code protection off
0= Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1= WDT enabled
0= WDT disabled
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Refer to the PIC16C5X Programming Specification (Literature Number DS30190) to determine how to access the
configuration word.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 31
PIC16C5X
FIGURE 7-2: CONFIGURATION WORD FOR PIC16C54/C54A/C55/C56/C57
—
—
—
—
—
—
—
—
CP
3
WDTE FOSC1 FOSC0
bit0
Register: CONFIG
(1)
Address
:
FFFh
bit11
10
9
8
7
6
5
4
2
1
bit 11-4: Unimplemented: Read as ’0’
bit 3:
CP: Code protection bit.
1= Code protection off
0= Code protection on
bit 2:
WDTE: Watchdog timer enable bit
1= WDT enabled
0= WDT disabled
(2)
bit 1-0: FOSC1:FOSC0: Oscillator selection bits
11= RC oscillator
10= HS oscillator
01= XT oscillator
00= LP oscillator
Note 1: Refer to the PIC16C5X Programming Specifications (Literature Number DS30190) to determine how to access the
configuration word.
2: PIC16LV54A supports XT, RC and LP oscillator only.
PIC16LV58A supports XT, RC and LP oscillator only.
DS30453C-page 32
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
7.2
Oscillator Configurations
FIGURE 7-4: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
7.2.1
OSCILLATOR TYPES
OSC CONFIGURATION)
PIC16C5Xs can be operated in four different oscillator
modes. The user can program two configuration bits
(FOSC<1:0>) to select one of these four modes:
OSC1
OSC2
Clock from
ext. system
PIC16C5X
• LP:
• XT:
• HS:
• RC:
Low Power Crystal
Open
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
TABLE 7-1:
CAPACITOR SELECTION
FOR CERAMIC RESONATORS
- PIC16C5X, PIC16CR5X
Note: Not all oscillator selections available for all
parts. See Section 7.1.
Osc
Type
Resonator Cap. Range Cap. Range
7.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Freq
C1
C2
XT
455 kHz
2.0 MHz
4.0 MHz
22-100 pF
15-68 pF
15-68 pF
22-100 pF
15-68 pF
15-68 pF
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 7-3). The
PIC16C5X oscillator design requires the use of a paral-
lel cut crystal. Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers specifications.
When in XT, LP or HS modes, the device can have an
external clock source drive the OSC1/CLKIN pin
(Figure 7-4).
HS
4.0 MHz
8.0 MHz
16.0 MHz
15-68 pF
10-68 pF
10-22 pF
15-68 pF
10-68 pF
10-22 pF
Note: These values are for design guidance only.
Since each resonator has its own charac-
teristics, the user should consult the reso-
nator manufacturer for appropriate values
of external components.
FIGURE 7-3: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
TABLE 7-2:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
- PIC16C5X, PIC16CR5X
CONFIGURATION)
(1)
C1
Osc
Type
Resonator Cap.Range Cap. Range
OSC1
PIC16C5X
Freq
C1
C2
SLEEP
LP
32 kHz(1)
100 kHz
200 kHz
15 pF
15-30 pF
15-30 pF
15 pF
30-47 pF
15-82 pF
XTAL
(3)
RF
To internal
logic
OSC2
(2)
RS
XT
100 kHz
200 kHz
455 kHz
1 MHz
2 MHz
4 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-47 pF
200-300 pF
100-200 pF
15-100 pF
15-30 pF
15-30 pF
15-47 pF
(1)
C2
Note 1: See Capacitor Selection tables for
recommended values of C1 and C2.
2: A series resistor (RS) may be required for
AT strip cut crystals.
HS
4 MHz
8 MHz
20 MHz
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
15-30 pF
3: RF varies with the crystal chosen
(approx. value = 10 MΩ).
Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is
recommended.
2: These values are for design guidance only.
Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification. Since each
crystal has its own characteristics, the user
should consult the crystal manufacturer for
appropriate values of external components.
Note: If you change from one device to another
device, please verify oscillator characteris-
tics in your application.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 33
PIC16C5X
7.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
FIGURE 7-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
Either a prepackaged oscillator or a simple oscillator
circuit with TTL gates can be used as an external crys-
tal oscillator circuit. Prepackaged oscillators provide a
wide operating range and better stability.
A
To Other
Devices
well-designed crystal oscillator will provide good perfor-
mance with TTL gates. Two types of crystal oscillator
circuits can be used: one with parallel resonance or
one with series resonance.
330
330
PIC16C5X
74AS04
74AS04
74AS04
OSC1
0.1 µF
Figure 7-5 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the fun-
damental frequency of the crystal. The 74AS04 inverter
performs the 180-degree phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ potentiome-
ters bias the 74AS04 in the linear region. This circuit
could be used for external oscillator designs.
OSC2
XTAL
100k
Note: If you change from one device to another
device, please verify oscillator characteris-
tics in your application.
FIGURE 7-5: EXTERNAL PARALLEL
RESONANT CRYSTAL
7.2.4
RC OSCILLATOR
For timing insensitive applications, the RC device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the resis-
tor (REXT) and capacitor (CEXT) values, and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal pro-
cess parameter variation. Furthermore, the difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to take into account
variation due to tolerance of external R and C compo-
nents used.
OSCILLATOR CIRCUIT
(USING XT, HS OR LP
OSCILLATOR MODE)
+5V
To Other
Devices
10k
74AS04
PIC16C5X
4.7k
74AS04
OSC1
OSC2
10k
100k
XTAL
Figure 7-7 shows how the R/C combination is con-
nected to the PIC16C5X. For REXT values below
2.2 kΩ, the oscillator operation may become unstable,
or stop completely. For very high REXT values
(e.g., 1 MΩ) the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
REXT between 3 kΩ and 100 kΩ.
10k
20 pF
20 pF
Note: If you change from one device to another
device, please verify oscillator characteris-
tics in your application.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or pack-
age lead frame capacitance.
This circuit is also designed to use the fundamental fre-
quency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 Ω resistors provide the negative feed-
back to bias the inverters in their linear region.
DS30453C-page 34
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
The Electrical Specification sections show RC fre-
quency variation from part to part due to normal pro-
cess variation.
7.3
RESET
PIC16C5X devices may be RESET in one of the follow-
ing ways:
Also, see the Electrical Specification sections for varia-
tion of oscillator frequency due to VDD for given
REXT/CEXT values, as well as frequency variation due
to operating temperature for given R, C and VDD val-
ues.
• Power-on Reset (POR)
• MCLR Reset (normal operation)
• MCLR Wake-up Reset (from SLEEP)
• WDT Reset (normal operation)
• WDT Wake-up Reset (from SLEEP)
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test pur-
poses or to synchronize other logic.
Table 7-3 shows these RESET conditions for the PCL
and STATUS registers.
FIGURE 7-7: RC OSCILLATOR MODE
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), MCLR or
WDT Reset. A MCLR or WDT Wake-up from SLEEP
also results in a device RESET, and not a continuation
of operation before SLEEP.
VDD
REXT
Internal
clock
OSC1
N
CEXT
VSS
PIC16C5X
The TO and PD bits (STATUS <4:3>) are set or cleared
depending on the different RESET conditions
(Section 7.7). These bits may be used to determine the
nature of the RESET.
FOSC/4
OSC2/CLKOUT
Table 7-4 lists a full description of RESET states of all
registers. Figure 7-8 shows a simplified block diagram
of the on-chip RESET circuit.
Note: If you change from one device to another
device, please verify oscillator characteris-
tics in your application.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 35
PIC16C5X
TABLE 7-3:
RESET CONDITIONS FOR SPECIAL REGISTERS
PCL
Addr: 02h
STATUS
Addr: 03h
Condition
Power-on Reset
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0001 1xxx
000u uuuu(1)
0001 0uuu
0000 uuuu(2)
0000 0uuu
MCLR Reset (normal operation)
MCLR Wake-up (from SLEEP)
WDT Reset (normal operation)
WDT Wake-up (from SLEEP)
Legend: u= unchanged, x= unknown, -= unimplemented read as ’0’.
Note 1: TO and PD bits retain their last value until one of the other RESET conditions occur.
2: The CLRWDTinstruction will set the TO and PD bits.
TABLE 7-4:
Register
RESET CONDITIONS FOR ALL REGISTERS
Address
Power-on Reset
MCLR or WDT Reset
W
N/A
N/A
xxxx xxxx
1111 1111
--11 1111
xxxx xxxx
xxxx xxxx
1111 1111
0001 1xxx
1xxx xxxx
---- xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
1111 1111
--11 1111
uuuu uuuu
uuuu uuuu
1111 1111
000q quuu
1uuu uuuu
---- uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TRIS
OPTION
N/A
INDF
00h
TMR0
PCL(1)
STATUS(1)
01h
02h
03h
FSR
04h
PORTA
05h
PORTB
PORTC(2)
06h
07h
General Purpose Register Files
07-7Fh
Legend: u= unchanged, x= unknown, -= unimplemented, read as ’0’,
q= see tables in Section 7.7 for possible values.
Note 1: See Table 7-3 for RESET value for specific conditions.
2: General purpose register file on PIC16C54/CR54/C56/CR56/C58/CR58.
FIGURE 7-8: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Power-up
Detect
POR (Power-on Reset)
VDD
MCLR/VPP pin
WDT Time-out
RESET
8-bit Asynch
S
R
Q
WDT
On-Chip
RC OSC
Ripple Counter
Q
(Start-Up Timer)
CHIP RESET
DS30453C-page 36
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
7.4
Power-on Reset (POR)
FIGURE 7-9: EXAMPLE OF EXTERNAL
POWER-ON RESET CIRCUIT
The PIC16C5X family incorporates on-chip Power-on
Reset (POR) circuitry which provides an internal chip
RESET for most power-up situations. To use this fea-
ture, the user merely ties the MCLR/VPP pin to VDD. A
simplified block diagram of the on-chip Power-on Reset
circuit is shown in Figure 7-8.
(FOR SLOW VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
The Power-on Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the Reset Latch is set and the DRT is
RESET. The DRT timer begins counting once it detects
MCLR to be high. After the time-out period, which is
typically 18 ms, it will reset the Reset Latch and thus
end the on-chip RESET signal.
PIC16C5X
C
• External Power-on Reset circuit is required
only if VDD power-up is too slow. The diode D
helps discharge the capacitor quickly when
VDD powers down.
A power-up example where MCLR is not tied to VDD is
shown in Figure 7-10. VDD is allowed to rise and stabi-
lize before bringing MCLR high. The chip will actually
come out of RESET TDRT msec after MCLR goes high.
• R < 40 kΩ is recommended to make sure that
voltage drop across R does not violate the
device electrical specification.
In Figure 7-11, the on-chip Power-on Reset feature is
being used (MCLR and VDD are tied together). The VDD
is stable before the start-up timer times out and there is
no problem in getting a proper RESET. However,
Figure 7-12 depicts a problem situation where VDD
rises too slowly. The time between when the DRT
senses a high on the MCLR/VPP pin, and when the
MCLR/VPP pin (and VDD) actually reach their full value,
is too long. In this situation, when the start-up timer
times out, VDD has not reached the VDD (min) value and
the chip is, therefore, not guaranteed to function cor-
rectly. For such situations, we recommend that external
(RESET) BOR circuits or external RC circuits be used
to achieve longer POR delay times (Figure 7-9).
• R1 = 100Ω to 1 kΩ will limit any current flow-
ing into MCLR from external capacitor C in the
event of MCLR pin breakdown due to Electro-
static Discharge (ESD) or Electrical Over-
stress (EOS).
Note: When the device starts normal operation
(exits the RESET condition), device oper-
ating parameters (voltage, frequency, tem-
perature, etc.) must be met to ensure
operation. If these conditions are not met,
the device must be held in RESET until the
operating conditions are met.
For more information on PIC16C5X POR, see
Power-Up Considerations - AN522 in the Embedded
Control Handbook.
The POR circuit does not produce an internal RESET
when VDD declines.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 37
PIC16C5X
FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): FAST VDD RISE TIME
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
FIGURE 7-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): SLOW VDD RISE TIME
V1
VDD
MCLR
INTERNAL POR
TDRT
DRT TIME-OUT
INTERNAL RESET
When VDD rises slowly, the TDRT time-out expires long before VDD has reached its final value. In
this example, the chip will RESET properly if, and only if, V1 ≥ VDD min.
DS30453C-page 38
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
7.5
Device Reset Timer (DRT)
7.6
Watchdog Timer (WDT)
The Device Reset Timer (DRT) provides a fixed 18 ms
nominal time-out on RESET. The DRT operates on an
internal RC oscillator. The processor is kept in RESET
as long as the DRT is active. The DRT delay allows VDD
to rise above VDD min., and for the oscillator to stabi-
lize.
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKIN pin. That means that the
WDT will run even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation or SLEEP, a WDT Reset or Wake-up Reset
generates a device RESET.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the device in
a RESET condition for approximately 18 ms after the
voltage on the MCLR/VPP pin has reached a logic high
(VIH) level. Thus, external RC networks connected to
the MCLR input are not required in most cases, allow-
ing for savings in cost-sensitive and/or space restricted
applications.
The TO bit (STATUS<4>) will be cleared upon a Watch-
dog Timer Reset.
The WDT can be permanently disabled by program-
ming the configuration bit WDTE as a ’0’ (Section 7.1).
Refer to the PIC16C5X Programming Specifications
(Literature Number DS30190) to determine how to
access the configuration word.
The Device Reset time delay will vary from device to
device due to VDD, temperature, and process variation.
See AC parameters for details.
7.6.1
WDT PERIOD
The DRT will also be triggered upon a Watchdog Timer
time-out. This is particularly important for applications
using the WDT to wake the PIC16C5X from SLEEP
mode automatically.
The WDT has a nominal time-out period of 18 ms (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by writ-
ing to the OPTION register. Thus, a time-out period of
a nominal 2.3 seconds can be realized. These periods
vary with temperature, VDD and part-to-part process
variations (see DC specs).
Under worst case conditions (VDD = Min., Temperature
= Max., max. WDT prescaler), it may take several sec-
onds before a WDT time-out occurs.
7.6.2
WDT PROGRAMMING CONSIDERATIONS
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device RESET.
The SLEEP instruction resets the WDT and the
postscaler, if assigned to the WDT. This gives the max-
imum SLEEP time before a WDT Wake-up Reset.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 39
PIC16C5X
FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0
M
Postscaler
1
Watchdog
Timer
U
X
8 - to - 1 MUX
PS<2:0>
PSA
WDT Enable
EPROM Bit
To TMR0
1
0
PSA
MUX
Note: T0CS, T0SE, PSA, PS<2:0>
are bits in the OPTION register.
WDT
Time-out
TABLE 7-5:
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Value on
Power-on
Reset
Value on
MCLR and
WDT Reset
Address
Name
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N/A
—
—
T0CS
T0SE
PSA
PS2
PS1
PS0
--11 1111 --11 1111
Legend: Shaded boxes = Not used by Watchdog Timer, - = unimplemented, read as '0', u= unchanged
DS30453C-page 40
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
7.7
Time-Out Sequence and Power-down
Status Bits (TO/PD)
7.8
RESET on Brown-Out
A brown-out is a condition where device power (VDD)
dips below its minimum value, but not to zero, and then
recovers. The device should be reset in the event of a
brown-out.
The TO and PD bits in the STATUS register can be
tested to determine if a RESET condition has been
caused by a power-up condition, a MCLR or Watchdog
Timer (WDT) Reset, or a MCLR or WDT Wake-up
Reset.
To reset PIC16C5X devices when a brown-out occurs,
external brown-out protection circuits may be built, as
shown in Figure 7-14 and Figure 7-15.
TABLE 7-6:
TO/PD STATUS AFTER
RESET
FIGURE 7-14: BROWN-OUT PROTECTION
CIRCUIT 1
TO
PD
RESET was caused by
VDD
1
u
1
u
Power-up (POR)
MCLR Reset (normal operation)(1)
MCLR Wake-up Reset (from SLEEP)
WDT Reset (normal operation)
VDD
33k
1
0
0
0
1
0
Q1
10k
WDT Wake-up Reset (from SLEEP)
MCLR
Legend: u= unchanged
40k
PIC16C5X
Note 1: The TO and PD bits maintain their status
(u) until a RESET occurs. A low-pulse on
the MCLR input does not change the TO
and PD status bits.
This circuit will activate RESET when VDD goes
below Vz + 0.7V (where Vz = Zener voltage).
These STATUS bits are only affected by events listed
in Table 7-7.
FIGURE 7-15: BROWN-OUT PROTECTION
CIRCUIT 2
TABLE 7-7:
EVENTS AFFECTING TO/PD
STATUS BITS
VDD
Event
TO PD
Remarks
VDD
1
0
1
1
1
u
0
1
Power-up
R1
WDT Time-out
No effect on PD
Q1
SLEEPinstruction
CLRWDTinstruction
Legend: u= unchanged
MCLR
R2
40k
PIC16C5X
Note: A WDT time-out will occur regardless of
the status of the TO bit. A SLEEPinstruc-
tion will be executed, regardless of the sta-
tus of the PD bit.
This brown-out circuit is less expensive, although
less accurate. Transistor Q1 turns off when VDD is
below a certain level such that:
R1
Table 7-3 lists the RESET conditions for the Special
Function Registers, while Table 7-4 lists the RESET
conditions for all the registers.
= 0.7V
VDD •
R1 + R2
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 41
PIC16C5X
FIGURE 7-16: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 3
7.10
Program Verification/Code Protection
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
VDD
MCP809
VDD
bypass
capacitor
Note: Microchip does not recommend code pro-
Vss
VDD
tecting windowed devices.
RST
MCLR
7.11
ID Locations
PIC16C62X
Four memory locations are designated as ID locations,
where the user can store checksum or other
code-identification numbers. These locations are not
accessible during normal execution but are readable
and writable during program/verify.
This brown-out protection circuit employs Micro-
chip Technology’s MCP809 microcontroller super-
visor. The MCP8XX and MCP1XX families of
supervisors provide push-pull and open collector
outputs with both "active high and active low"
RESET pins. There are 7 different trip point selec-
tions to accommodate 5V and 3V systems.
Use only the lower 4 bits of the ID locations and always
program the upper 8 bits as ’1’s.
Note: Microchip will assign a unique pattern
number for QTP and SQTP requests and
for ROM devices. This pattern number will
be unique and traceable to the submitted
code.
7.9
Power-down Mode (SLEEP)
A device may be powered down (SLEEP) and later
powered up (wake-up from SLEEP).
7.9.1
SLEEP
The Power-down mode is entered by executing a
SLEEPinstruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the TO bit (STATUS<4>) is set, the PD
bit (STATUS<3>) is cleared and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, driving low, or hi-impedance).
It should be noted that a RESET generated by a WDT
time-out does not drive the MCLR/VPP pin low.
For lowest current consumption while powered down,
the T0CKI input should be at VDD or VSS and the
MCLR/VPP pin must be at a logic high level.
7.9.2
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. An external RESET input on MCLR/VPP pin.
2. A Watchdog Timer time-out RESET (if WDT was
enabled).
Both of these events cause a device RESET. The TO
and PD bits can be used to determine the cause of
device RESET. The TO bit is cleared if a WDT time-out
occurred (and caused wake-up). The PD bit, which is
set on power-up, is cleared when SLEEPis invoked.
The WDT is cleared when the device wakes from
SLEEP, regardless of the wake-up source.
DS30453C-page 42
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
All instructions are executed within one single instruc-
tion cycle, unless a conditional test is true or the pro-
gram counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time would be 1 µs. If a condi-
tional test is true or the program counter is changed as
a result of an instruction, the instruction execution time
would be 2 µs.
8.0
INSTRUCTION SET SUMMARY
Each PIC16C5X instruction is a 12-bit word divided into an
OPCODE, which specifies the instruction type, and one or
more operands which further specify the operation of the
instruction. The PIC16C5X instruction set summary in
Table 8-2 groups the instructions into byte-oriented, bit-ori-
ented, and literal and control operations. Table 8-1 shows
the opcode field descriptions.
For byte-oriented instructions, ’f’ represents a file register
designator and ’d’represents a destination designator. The
file register designator is used to specify which one of the
32 file registers in that bank is to be used by the instruction.
Figure 8-1 shows the three general formats that the
instructions can have. All examples in the figure use
the following format to represent a hexadecimal
number:
The destination designator specifies where the result of
the operation is to be placed. If ’d’ is ’0’, the result is
placed in the W register. If ’d’ is ’1’, the result is placed
in the file register specified in the instruction.
0xhhh
where ’h’ signifies a hexadecimal digit.
FIGURE 8-1: GENERAL FORMAT FOR
INSTRUCTIONS
For bit-oriented instructions, ’b’ represents a bit field
designator which selects the number of the bit affected
by the operation, while ’f’ represents the number of the
file in which the bit is located.
Byte-oriented file register operations
11
6
5
d
4
0
For literal and control operations, ’k’ represents an
8 or 9-bit constant or literal value.
OPCODE
f (FILE #)
d = 0 for destination W
d = 1 for destination f
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
f = 5-bit file register address
Bit-oriented file register operations
11 8 7
b (BIT #)
Field
Description
5
4
0
f
W
b
k
Register file address (0x00 to 0x7F)
Working register (accumulator)
OPCODE
f (FILE #)
b = 3-bit bit address
f = 5-bit file register address
Bit address within an 8-bit file register
Literal field, constant data or label
Don’t care location (= 0 or 1)
Literal and control operations (except GOTO)
11
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.
x
d
8
7
0
OPCODE
k (literal)
Destination select;
k = 8-bit immediate value
d = 0 (store result in W)
d = 1 (store result in file register ’f’)
Default is d = 1
Literal and control operations - GOTOinstruction
11 0
9
8
label Label name
OPCODE
k (literal)
TOS
PC
Top of Stack
Program Counter
Watchdog Timer Counter
Time-out bit
k = 9-bit immediate value
WDT
TO
PD
Power-down bit
Destination, either the W register or the specified
register file location
dest
[ ]
( )
→
Options
Contents
Assigned to
< >
Register bit field
In the set of
italics
User defined term (font is courier)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 43
PIC16C5X
TABLE 8-2:
INSTRUCTION SET SUMMARY
12-Bit Opcode
Mnemonic,
Operands
Status
Description
Cycles MSb
LSb Affected Notes
1
1
1
1
1
1
0001 11df ffff
C,DC,Z 1,2,4
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
f,d
f,d
f
0001 01df ffff
0000 011f ffff
0000 0100 0000
0010 01df ffff
0000 11df ffff
Z
Z
Z
2,4
4
–
Z
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
Z
None
Z
None
Z
Z
None
None
C
2,4
2,4
2,4
2,4
2,4
2,4
1,4
1(2) 0010 11df ffff
0010 10df ffff
1(2) 0011 11df ffff
1
1
1
1
1
1
1
1
1
1
0001 00df ffff
0010 00df ffff
0000 001f ffff
0000 0000 0000
0011 01df ffff
0011 00df ffff
0000 10df ffff
0011 10df ffff
0001 10df ffff
–
2,4
2,4
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
C
C,DC,Z 1,2,4
None
Z
2,4
2,4
Exclusive OR W with f
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
0100 bbbf ffff
0101 bbbf ffff
None
None
None
None
2,4
2,4
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
1 (2) 0110 bbbf ffff
1 (2) 0111 bbbf ffff
LITERAL AND CONTROL OPERATIONS
1
2
1
2
1
1
1
2
1
1
1
1110 kkkk kkkk
1001 kkkk kkkk
0000 0000 0100
101k kkkk kkkk
1101 kkkk kkkk
1100 kkkk kkkk
0000 0000 0010
1000 kkkk kkkk
0000 0000 0011
0000 0000 0fff
1111 kkkk kkkk
Z
AND literal with W
Call subroutine
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
k
k
k
k
k
k
k
k
–
f
None
TO, PD
None
Z
None
None
None
TO, PD
None
Z
1
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
3
Exclusive OR Literal to W
XORLW
k
Note 1: The 9th bit of the program counter will be forced to a ’0’ by any instruction that writes to the PC except for
GOTO. (See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Regis-
ters)
2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that
value present on the pins themselves. For example, if the data latch is ’1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ’0’.
3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate
latches of PORTA or B respectively. A ’1’ forces the pin to a hi-impedance state and disables the output buff-
ers.
4: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be
cleared (if assigned to TMR0).
DS30453C-page 44
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
ADDWF
Syntax:
Add W and f
[ label ] ADDWF f,d
0 ≤ f ≤ 31
ANDWF
Syntax:
AND W with f
[ label ] ANDWF f,d
Operands:
Operands:
0 ≤ f ≤ 31
d
[0,1]
d
[0,1]
Operation:
(W) + (f) → (dest)
Operation:
(W) .AND. (f) → (dest)
Status Affected: C, DC, Z
Status Affected:
Encoding:
Z
0001
11df
ffff
0001
01df
ffff
Encoding:
Add the contents of the W register and
register ’f’. If ’d’ is 0 the result is stored
in the W register. If ’d’ is ’1’ the result is
stored back in register ’f’.
The contents of the W register are
AND’ed with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
'1' the result is stored back in register 'f'.
Description:
Description:
Words:
1
1
Words:
1
1
Cycles:
Example:
Cycles:
Example:
ADDWF
FSR, 0
ANDWF
FSR,
1
Before Instruction
Before Instruction
W
=
0x17
W
= 0x17
FSR = 0xC2
TEMP_REG = 0xC2
After Instruction
After Instruction
W
=
0xD9
W
= 0x17
FSR = 0xC2
TEMP_REG = 0x2
ANDLW
And literal with W
[ label ] ANDLW
0 ≤ k ≤ 255
BCF
Bit Clear f
Syntax:
k
Syntax:
Operands:
[ label ] BCF f,b
Operands:
Operation:
Status Affected:
Encoding:
Description:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
(W).AND. (k) → (W)
Operation:
0 → (f<b>)
Z
Status Affected: None
1110
kkkk
kkkk
0100
bbbf
ffff
Encoding:
Description:
Words:
The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register.
Bit 'b' in register 'f' is cleared.
1
1
Words:
1
1
Cycles:
Cycles:
Example:
BCF
FLAG_REG,
7
Example:
ANDLW
0x5F
Before Instruction
Before Instruction
FLAG_REG = 0xC7
W
=
0xA3
After Instruction
After Instruction
FLAG_REG = 0x47
W
=
0x03
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 45
PIC16C5X
BSF
Bit Set f
BTFSS
Bit Test f, Skip if Set
Syntax:
Operands:
[ label ] BSF f,b
Syntax:
[ label ] BTFSS f,b
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Operands:
0 ≤ f ≤ 31
0 ≤ b < 7
Operation:
1 → (f<b>)
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected: None
0101
bbbf
ffff
0111
bbbf
ffff
Encoding:
Description:
Words:
Encoding:
Bit ’b’ in register ’f’ is set.
If bit ’b’ in register ’f’ is ’1’ then the next
instruction is skipped.
Description:
1
1
If bit ’b’ is ’1’, then the next instruction
fetched during the current instruction
execution, is discarded and a NOPis
executed instead, making this a
2-cycle instruction.
Cycles:
BSF
FLAG_REG,
7
Example:
Before Instruction
FLAG_REG = 0x0A
Words:
1
After Instruction
Cycles:
Example:
1(2)
FLAG_REG = 0x8A
HERE
FALSE GOTO
TRUE
BTFSS FLAG,1
PROCESS_CODE
•
BTFSC
Bit Test f, Skip if Clear
•
•
Syntax:
[ label ] BTFSC f,b
Operands:
0 ≤ f ≤ 31
0 ≤ b ≤ 7
Before Instruction
PC
=
address (HERE)
After Instruction
If FLAG<1>
PC
Operation:
skip if (f<b>) = 0
=
=
=
=
0,
Status Affected: None
address (FALSE);
1,
address (TRUE)
bbbf
ffff
if FLAG<1>
PC
Encoding:
0110
If bit ’b’ in register ’f’ is 0 then the next
instruction is skipped.
Description:
If bit ’b’ is 0 then the next instruction
fetched during the current instruction
execution is discarded, and a NOPis
executed instead, making this a
2-cycle instruction.
Words:
1
Cycles:
Example:
1(2)
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC
=
address (HERE)
After Instruction
if FLAG<1>
PC
=
=
=
=
0,
address (TRUE);
1,
address(FALSE)
if FLAG<1>
PC
DS30453C-page 46
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
CALL
Subroutine Call
[ label ] CALL
0 ≤ k ≤ 255
CLRW
Clear W
Syntax:
k
Syntax:
[ label ] CLRW
Operands:
Operation:
Operands:
Operation:
None
(PC) + 1→ Top of Stack;
k → PC<7:0>;
00h → (W);
1 → Z
(STATUS<6:5>) → PC<10:9>;
0 → PC<8>
Status Affected:
Encoding:
Z
0000
0100
0000
Status Affected: None
The W register is cleared. Zero bit (Z)
is set.
Description:
1001
kkkk
kkkk
Encoding:
Subroutine call. First, return address
(PC+1) is pushed onto the stack. The
eight bit immediate address is loaded
into PC bits <7:0>. The upper bits
PC<10:9> are loaded from
Description:
Words:
1
Cycles:
Example:
1
CLRW
Before Instruction
STATUS<6:5>, PC<8> is cleared.
CALLis a two-cycle instruction.
W
=
0x5A
After Instruction
Words:
1
2
W
=
0x00
Cycles:
Example:
Z
=
1
HERE
CALL
THERE
Before Instruction
CLRWDT
Clear Watchdog Timer
[ label ] CLRWDT
None
PC
=
address (HERE)
Syntax:
After Instruction
PC
=
address (THERE)
Operands:
Operation:
TOS =
address (HERE + 1)
00h → WDT;
0 → WDT prescaler (if assigned);
1 → TO;
1 → PD
CLRF
Clear f
Syntax:
[ label ] CLRF
0 ≤ f ≤ 31
f
Status Affected: TO, PD
Operands:
Operation:
0000
0000
0100
Encoding:
00h → (f);
1 → Z
The CLRWDTinstruction resets the
WDT. It also resets the prescaler, if the
prescaler is assigned to the WDT and
not Timer0. Status bits TO and PD are
set.
Description:
Status Affected:
Encoding:
Z
0000
011f
ffff
The contents of register ’f’ are cleared
and the Z bit is set.
Description:
Words:
1
Cycles:
Example:
1
Words:
1
1
CLRWDT
Cycles:
Example:
Before Instruction
CLRF
FLAG_REG
WDT counter
=
=
?
Before Instruction
FLAG_REG
After Instruction
WDT counter
=
0x5A
0x00
After Instruction
WDT prescale =
0
1
1
FLAG_REG
Z
=
=
0x00
1
TO
PD
=
=
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 47
PIC16C5X
COMF
Complement f
DECFSZ
Syntax:
Decrement f, Skip if 0
[ label ] DECFSZ f,d
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] COMF f,d
0 ≤ f ≤ 31
Operands:
d
[0,1]
d
[0,1]
Operation:
(f) → (dest)
Operation:
(f) – 1 → d; skip if result = 0
Status Affected:
Encoding:
Z
Status Affected: None
0010
01df
ffff
0010
11df
ffff
Encoding:
The contents of register ’f’ are comple-
mented. If ’d’ is 0 the result is stored in
the W register. If ’d’ is 1 the result is
stored back in register ’f’.
The contents of register ’f’ are decre-
mented. If ’d’ is 0 the result is placed in
the W register. If ’d’ is 1 the result is
placed back in register ’f’.
Description:
Description:
If the result is 0, the next instruction,
which is already fetched, is discarded
and a NOPis executed instead making
it a two-cycle instruction.
Words:
1
1
Cycles:
Example:
COMF
REG1,0
Words:
1
Before Instruction
REG1
=
0x13
0x13
Cycles:
Example:
1(2)
After Instruction
HERE
DECFSZ
GOTO
CNT, 1
LOOP
REG1
=
W
=
0xEC
CONTINUE •
•
•
DECF
Decrement f
[ label ] DECF f,d
0 ≤ f ≤ 31
Before Instruction
PC
=
address (HERE)
Syntax:
After Instruction
Operands:
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT - 1;
0,
address (CONTINUE);
0,
d
[0,1]
Operation:
(f) – 1 → (dest)
Status Affected:
Encoding:
Z
address (HERE+1)
0000
11df
ffff
Decrement register ’f’. If ’d’ is 0 the
result is stored in the W register. If ’d’ is
1 the result is stored back in register ’f’.
Description:
GOTO
Unconditional Branch
[ label ] GOTO k
0 ≤ k ≤ 511
Syntax:
Words:
1
1
Operands:
Operation:
Cycles:
Example:
k → PC<8:0>;
STATUS<6:5> → PC<10:9>
DECF
CNT,
1
Before Instruction
Status Affected: None
CNT
=
0x01
0
101k
kkkk
kkkk
Encoding:
Z
=
GOTOis an unconditional branch. The
9-bit immediate value is loaded into PC
bits <8:0>. The upper bits of PC are
loaded from STATUS<6:5>. GOTOis a
two-cycle instruction.
Description:
After Instruction
CNT
=
0x00
1
Z
=
Words:
1
Cycles:
Example:
2
GOTO THERE
After Instruction
PC
=
address (THERE)
DS30453C-page 48
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
INCF
Increment f
IORLW
Inclusive OR literal with W
Syntax:
Operands:
[ label ] INCF f,d
Syntax:
[ label ] IORLW k
0 ≤ k ≤ 255
0 ≤ f ≤ 31
Operands:
Operation:
Status Affected:
Encoding:
Description:
d
[0,1]
(W) .OR. (k) → (W)
Z
Operation:
(f) + 1 → (dest)
Status Affected:
Encoding:
Z
1101
kkkk
kkkk
0010
10df
ffff
The contents of the W register are
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
The contents of register ’f’ are incre-
mented. If ’d’ is 0 the result is placed in
the W register. If ’d’ is 1 the result is
placed back in register ’f’.
Description:
Words:
1
1
Cycles:
Example:
Words:
1
1
IORLW
0x35
Cycles:
Example:
Before Instruction
INCF
CNT,
1
W
=
0x9A
Before Instruction
After Instruction
CNT
=
0xFF
0
W
=
0xBF
Z
=
Z
=
0
After Instruction
CNT
Z
=
=
0x00
1
IORWF
Inclusive OR W with f
[ label ] IORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
INCFSZ
Increment f, Skip if 0
[ label ] INCFSZ f,d
0 ≤ f ≤ 31
d
[0,1]
Syntax:
Operation:
(W).OR. (f) → (dest)
Operands:
Status Affected:
Encoding:
Z
d
[0,1]
0001
00df
ffff
Operation:
(f) + 1 → (dest), skip if result = 0
Inclusive OR the W register with regis-
ter 'f'. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Description:
Status Affected: None
0011
11df
ffff
Encoding:
The contents of register ’f’ are incre-
mented. If ’d’ is 0 the result is placed in
the W register. If ’d’ is 1 the result is
placed back in register ’f’.
Description:
Words:
1
1
Cycles:
Example:
If the result is 0, then the next instruc-
tion, which is already fetched, is dis-
carded and a NOPis executed instead
making it a two-cycle instruction.
IORWF
RESULT, 0
Before Instruction
RESULT =
0x13
0x91
W
=
Words:
1
After Instruction
RESULT =
Cycles:
Example:
1(2)
0x13
0x93
0
W
Z
=
=
HERE
INCFSZ
GOTO
CNT,
LOOP
1
CONTINUE •
•
•
Before Instruction
PC
=
address (HERE)
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT + 1;
0,
address (CONTINUE);
0,
address (HERE +1)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 49
PIC16C5X
MOVF
Move f
MOVWF
Syntax:
Move W to f
[ label ] MOVWF
0 ≤ f ≤ 31
Syntax:
Operands:
[ label ] MOVF f,d
f
0 ≤ f ≤ 31
Operands:
Operation:
d
[0,1]
(W) → (f)
Operation:
(f) → (dest)
Status Affected: None
Status Affected:
Encoding:
Z
0000
001f
ffff
Encoding:
0010
00df
ffff
Move data from the W register to regis-
ter 'f'.
Description:
The contents of register ’f’ is moved to
destination ’d’. If ’d’ is 0, destination is
the W register. If ’d’ is 1, the destination
is file register ’f’. ’d’ is 1 is useful to test
a file register since status flag Z is
affected.
Description:
Words:
1
1
Cycles:
Example:
MOVWF
TEMP_REG
Before Instruction
Words:
1
1
TEMP_REG
W
=
=
0xFF
0x4F
Cycles:
Example:
MOVF
FSR,
0
After Instruction
TEMP_REG
W
=
=
0x4F
0x4F
After Instruction
W
=
value in FSR register
NOP
No Operation
[ label ] NOP
None
MOVLW
Move Literal to W
[ label ] MOVLW k
0 ≤ k ≤ 255
Syntax:
Syntax:
Operands:
Operation:
Operands:
Operation:
No operation
k → (W)
Status Affected: None
0000
0000
0000
Status Affected: None
Encoding:
Description:
Words:
1100
kkkk
kkkk
Encoding:
No operation.
The eight bit literal ’k’ is loaded into the
W register. The don’t cares will assem-
ble as 0s.
Description:
1
Cycles:
1
NOP
Example:
Words:
1
1
Cycles:
Example:
MOVLW
0x5A
After Instruction
W
=
0x5A
DS30453C-page 50
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
OPTION
Syntax:
Load OPTION Register
[ label ] OPTION
None
RLF
Rotate Left f through Carry
Syntax:
Operands:
[ label ] RLF f,d
Operands:
Operation:
0 ≤ f ≤ 31
d
[0,1]
(W) → OPTION
Status Affected: None
Operation:
See description below
C
0000
0000
0010
Encoding:
Status Affected:
Encoding:
The content of the W register is loaded
into the OPTION register.
Description:
0011
01df
ffff
The contents of register ’f’ are rotated
one bit to the left through the Carry
Flag. If ’d’ is 0 the result is placed in the
W register. If ’d’ is 1 the result is stored
back in register ’f’.
Description:
Words:
Cycles:
Example
1
1
OPTION
Before Instruction
register ’f’
C
W
=
0x07
0x07
After Instruction
OPTION =
Words:
1
1
Cycles:
Example:
RLF
REG1,0
RETLW
Return with Literal in W
Before Instruction
Syntax:
[ label ] RETLW
0 ≤ k ≤ 255
k
REG1
C
=
=
1110 0110
0
Operands:
Operation:
After Instruction
k → (W);
TOS → PC
REG1
W
C
=
=
=
1110 0110
1100 1100
1
Status Affected: None
1000
kkkk
kkkk
Encoding:
The W register is loaded with the eight
bit literal ’k’. The program counter is
loaded from the top of the stack (the
return address). This is a two-cycle
instruction.
Description:
RRF
Rotate Right f through Carry
[ label ] RRF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
d
[0,1]
Words:
1
2
Operation:
See description below
C
Cycles:
Example:
Status Affected:
Encoding:
CALL TABLE ;W contains
;table offset
;value.
0011
00df
ffff
The contents of register ’f’ are rotated
one bit to the right through the Carry
Flag. If ’d’ is 0 the result is placed in the
W register. If ’d’ is 1 the result is placed
back in register ’f’.
Description:
•
•
;W now has table
;value.
•
TABLE
ADDWF PC
RETLW k1
RETLW k2
;W = offset
;Begin table
;
register ’f’
C
•
•
Words:
1
•
Cycles:
Example:
1
RETLW kn
; End of table
RRF
REG1,0
Before Instruction
W
=
0x07
Before Instruction
REG1
C
=
=
1110 0110
0
After Instruction
W
=
value of k8
After Instruction
REG1
W
C
=
=
=
1110 0110
0111 0011
0
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 51
PIC16C5X
SLEEP
Enter SLEEP Mode
SUBWF
Subtract W from f
Syntax:
Syntax:
[label]
[label] SUBWF f,d
0 ≤ f ≤ 31
SLEEP
Operands:
Operands:
Operation:
None
d
[0,1]
00h → WDT;
0 → WDT prescaler;
1 → TO;
Operation:
(f) – (W) → (dest)
Status Affected: C, DC, Z
0 → PD
0000
10df
ffff
Encoding:
Status Affected: TO, PD
Subtract (2’s complement method) the
W register from register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0011
Encoding:
Time-out status bit (TO) is set. The
power-down status bit (PD) is cleared.
The WDT and its prescaler are
cleared.
Description:
Words:
1
1
Cycles:
The processor is put into SLEEP mode
with the oscillator stopped. See sec-
tion on SLEEP for more details.
SUBWF
REG1, 1
Example 1:
Before Instruction
Words:
1
REG1
W
C
=
=
=
3
2
?
Cycles:
Example:
1
SLEEP
After Instruction
REG1
W
C
=
=
=
1
2
1
; result is positive
Example 2:
Before Instruction
REG1
W
C
=
=
=
2
2
?
After Instruction
REG1
W
C
=
=
=
0
2
1
; result is zero
Example 3:
Before Instruction
REG1
W
C
=
=
=
1
2
?
After Instruction
REG1
W
C
=
=
=
FF
2
0
; result is negative
DS30453C-page 52
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
SWAPF
Syntax:
Swap Nibbles in f
[ label ] SWAPF f,d
0 ≤ f ≤ 31
XORLW
Exclusive OR literal with W
Syntax:
[label] XORLW k
0 ≤ k ≤ 255
Operands:
Operands:
d
[0,1]
Operation:
(W) .XOR. k → (W)
Z
Operation:
(f<3:0>) → (dest<7:4>);
(f<7:4>) → (dest<3:0>)
Status Affected:
Encoding:
1111
kkkk
kkkk
Status Affected: None
The contents of the W register are
XOR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Description:
0011
10df
ffff
Encoding:
The upper and lower nibbles of register
’f’ are exchanged. If ’d’ is 0 the result is
placed in W register. If ’d’ is 1 the result
is placed in register ’f’.
Description:
Words:
1
Cycles:
Example:
1
Words:
Cycles:
Example
1
1
XORLW 0xAF
Before Instruction
W
=
0xB5
SWAPF
REG1,
0
After Instruction
Before Instruction
W
=
0x1A
REG1
=
0xA5
After Instruction
REG1
W
=
=
0xA5
0X5A
XORWF
Exclusive OR W with f
[ label ] XORWF f,d
0 ≤ f ≤ 31
Syntax:
Operands:
TRIS
Load TRIS Register
d
[0,1]
Syntax:
[ label ] TRIS
f
Operation:
(W) .XOR. (f) → (dest)
Operands:
Operation:
f = 5, 6 or 7
Status Affected:
Encoding:
Z
(W) → TRIS register f
0001
10df
ffff
Status Affected: None
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Description:
0000
0000
0fff
Encoding:
TRIS register ’f’ (f = 5, 6, or 7) is loaded
with the contents of the W register.
Description:
Words:
Cycles:
Example
1
1
Words:
Cycles:
Example
1
1
TRIS
PORTA
REG,1
XORWF
Before Instruction
Before Instruction
W
=
0XA5
0XA5
REG
=
0xAF
0xB5
W
=
After Instruction
TRISA
=
After Instruction
REG
W
=
=
0x1A
0xB5
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 53
PIC16C5X
NOTES:
DS30453C-page 54
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
MPLAB allows you to:
9.0
DEVELOPMENT SUPPORT
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro tools (automatically updates all
project information)
• Integrated Development Environment
- MPLAB® IDE Software
• Debug using:
- source files
• Assemblers/Compilers/Linkers
- MPASM Assembler
- absolute listing file
- object code
- MPLAB-C17 and MPLAB-C18 C Compilers
- MPLINK/MPLIB Linker/Librarian
• Simulators
The ability to use MPLAB with Microchip’s simulator,
MPLAB-SIM, allows a consistent platform and the abil-
ity to easily switch from the cost-effective simulator to
the full featured emulator with minimal retraining.
- MPLAB-SIM Software Simulator
• Emulators
- MPLAB-ICE Real-Time In-Circuit Emulator
- ICEPIC™
9.2
MPASM Assembler
• In-Circuit Debugger
MPASM is a full featured universal macro assembler for
all PICmicro MCU’s. It can produce absolute code
directly in the form of HEX files for device program-
mers, or it can generate relocatable objects for
MPLINK.
- MPLAB-ICD for PIC16F87
• Device Programmers
- PRO MATE II Universal Programmer
- PICSTART Plus Entry-Level Prototype
Programmer
MPASM has a command line interface and a Windows
shell and can be used as a standalone application on a
Windows 3.x or greater system. MPASM generates
relocatable object files, Intel standard HEX files, MAP
files to detail memory usage and symbol reference, an
absolute LST file which contains source lines and gen-
erated machine code, and a COD file for MPLAB
debugging.
• Low-Cost Demonstration Boards
- PICDEM-1
- PICDEM-2
- PICDEM-3
- PICDEM-17
- KEELOQ
MPASM features include:
9.1
MPLAB Integrated Development
Environment Software
• MPASM and MPLINK are integrated into MPLAB
projects.
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcon-
troller market. MPLAB is a Windows -based applica-
tion which contains:
• MPASM allows user defined macros to be created
for streamlined assembly.
• MPASM allows conditional assembly for multi pur-
pose source files.
• Multiple functionality
- editor
• MPASM directives allow complete control over the
assembly process.
- simulator
9.3
MPLAB-C17 and MPLAB-C18
C Compilers
- programmer (sold separately)
- emulator (sold separately)
• A full featured editor
• A project manager
• Customizable tool bar and key mapping
• A status bar
The MPLAB-C17 and MPLAB-C18 Code Development
Systems are complete ANSI ‘C’ compilers and inte-
grated development environments for Microchip’s
PIC17CXXX and PIC18CXXX family of microcontrol-
lers, respectively. These compilers provide powerful
integration capabilities and ease of use not found with
other compilers.
• On-line help
For easier source level debugging, the compilers pro-
vide symbol information that is compatible with the
MPLAB IDE memory display.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 55
PIC16C5X
Interchangeable processor modules allow the system
to be easily reconfigured for emulation of different pro-
cessors. The universal architecture of the MPLAB-ICE
allows expansion to support new PICmicro microcon-
trollers.
9.4
MPLINK/MPLIB Linker/Librarian
MPLINK is a relocatable linker for MPASM and
MPLAB-C17 and MPLAB-C18. It can link relocatable
objects from assembly or C source files along with pre-
compiled libraries using directives from a linker script.
The MPLAB-ICE Emulator System has been designed
as a real-time emulation system with advanced fea-
tures that are generally found on more expensive devel-
opment tools. The PC platform and Microsoft® Windows
3.x/95/98 environment were chosen to best make these
features available to you, the end user.
MPLIB is a librarian for pre-compiled code to be used
with MPLINK. When a routine from a library is called
from another source file, only the modules that contains
that routine will be linked in with the application. This
allows large libraries to be used efficiently in many dif-
ferent applications. MPLIB manages the creation and
modification of library files.
MPLAB-ICE 2000 is a full-featured emulator system
with enhanced trace, trigger, and data monitoring fea-
tures. Both systems use the same processor modules
and will operate across the full operating speed range
of the PICmicro MCU.
MPLINK features include:
• MPLINK works with MPASM and MPLAB-C17
and MPLAB-C18.
• MPLINK allows all memory areas to be defined as
sections to provide link-time flexibility.
9.7
ICEPIC
ICEPIC is a low-cost in-circuit emulation solution for the
Microchip Technology PIC16C5X, PIC16C6X,
MPLIB features include:
• MPLIB makes linking easier because single librar-
ies can be included instead of many smaller files.
PIC16C7X, and PIC16CXXX families of 8-bit one-time-
programmable (OTP) microcontrollers. The modular
system can support different subsets of PIC16C5X or
PIC16CXXX products through the use of interchange-
able personality modules or daughter boards. The
emulator is capable of emulating without target applica-
tion circuitry being present.
• MPLIB helps keep code maintainable by grouping
related modules together.
• MPLIB commands allow libraries to be created
and modules to be added, listed, replaced,
deleted, or extracted.
9.5
MPLAB-SIM Software Simulator
9.8
MPLAB-ICD In-Circuit Debugger
The MPLAB-SIM Software Simulator allows code
development in a PC host environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file or user-defined key press to any of the pins. The
execution can be performed in single step, execute until
break, or trace mode.
Microchip’s In-Circuit Debugger, MPLAB-ICD, is a pow-
erful, low-cost run-time development tool. This tool is
based on the flash PIC16F877 and can be used to
develop for this and other PICmicro microcontrollers
from the PIC16CXXX family. MPLAB-ICD utilizes the
In-Circuit Debugging capability built into the
PIC16F87X. This feature, along with Microchip’s In-Cir-
cuit Serial Programming protocol, offers cost-effective
in-circuit flash programming and debugging from the
graphical user interface of the MPLAB Integrated
Development Environment. This enables a designer to
develop and debug source code by watching variables,
single-stepping and setting break points. Running at
full speed enables testing hardware in real-time. The
MPLAB-ICD is also a programmer for the flash
PIC16F87X family.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-
ware Simulator offers the flexibility to develop and
debug code outside of the laboratory environment mak-
ing it an excellent multi-project software development
tool.
9.6
MPLAB-ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
The MPLAB-ICE Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers (MCUs). Software control of
MPLAB-ICE is provided by the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
DS30453C-page 56
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
9.9
PRO MATE II Universal Programmer
9.12
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PRO MATE II Universal Programmer is a full-fea-
tured programmer capable of operating in stand-alone
mode as well as PC-hosted mode. PRO MATE II is CE
compliant.
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II pro-
grammer or PICSTART-Plus, and easily test firmware.
The MPLAB-ICE emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding addi-
tional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 inter-
face, push-button switches, a potentiometer for simu-
lated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connec-
tion to an LCD module and a keypad.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for instructions and error messages,
keys to enter commands and a modular detachable
socket assembly to support various package types. In
stand-alone mode the PRO MATE II can read, verify or
program PICmicro devices. It can also set code-protect
bits in this mode.
9.10
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, low-
cost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient.
9.13
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the neces-
sary hardware and software is included to run the
basic demonstration programs. The user can pro-
gram the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II program-
mer or PICSTART Plus with an adapter socket, and
easily test firmware. The MPLAB-ICE emulator may
also be used with the PICDEM-3 board to test firm-
ware. Additional prototype area has been provided to
the user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
an RS-232 interface, push-button switches, a potenti-
ometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 seg-
ments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an addi-
tional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A sim-
ple serial interface allows the user to construct a hard-
ware demultiplexer for the LCD signals.
PICSTART Plus supports all PICmicro devices with up
to 40 pins. Larger pin count devices such as the
PIC16C92X, and PIC17C76X may be supported with
an adapter socket. PICSTART Plus is CE compliant.
9.11
PICDEM-1 Low-Cost PICmicro
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrol-
lers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on
a PRO MATE II or
PICSTART-Plus programmer, and easily test firm-
ware. The user can also connect the PICDEM-1
board to the MPLAB-ICE emulator and download the
firmware to the emulator for testing. Additional proto-
type area is available for the user to build some addi-
tional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 57
PIC16C5X
9.14
PICDEM-17
The PICDEM-17 is an evaluation board that demon-
strates the capabilities of several Microchip microcon-
trollers,
including
PIC17C752,
PIC17C756,
PIC17C762, and PIC17C766. All necessary hardware
is included to run basic demo programs, which are sup-
plied on a 3.5-inch disk. A programmed sample is
included, and the user may erase it and program it with
the other sample programs using the PRO MATE II or
PICSTART Plus device programmers and easily debug
and test the sample code. In addition, PICDEM-17 sup-
ports down-loading of programs to and executing out of
external FLASH memory on board. The PICDEM-17 is
also usable with the MPLAB-ICE or PICMASTER emu-
lator, and all of the sample programs can be run and
modified using either emulator. Additionally, a gener-
ous prototype area is available for user hardware.
9.15
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS eval-
uation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a pro-
gramming interface to program test transmitters.
DS30453C-page 58
Preliminary
2000 Microchip Technology Inc.
®
MPLAB Integrated
Development Environment
®
MPLAB C17 Compiler
®
MPLAB C18 Compiler
MPASM/MPLINK
®
MPLAB -ICE
**
ICEPIC Low-Cost
In-Circuit Emulator
®
MPLAB -ICD In-Circuit
*
*
Debugger
PICSTART Plus
Low-Cost Universal Dev. Kit
**
**
PRO MATE II
Universal Programmer
†
†
PICDEM-1
PICDEM-2
PICDEM-3
PICDEM-14A
PICDEM-17
†
K
EE
L
OQ® Evaluation Kit
K
EE
LOQ Transponder Kit
microID™ Programmer’s Kit
125 kHz microID Developer’s Kit
125 kHz Anticollision microID
Developer’s Kit
13.56 MHz Anticollision microID
Developer’s Kit
MCP2510 CAN Developer’s Kit
®
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB -ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77
** Contact Microchip Technology Inc. for availability date.
†
Development tool is available on select devices.
PIC16C5X
NOTES:
DS30453C-page 60
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
10.0 ELECTRICAL CHARACTERISTICS - PIC16C54/55/56/57
Absolute Maximum Ratings†
Ambient Temperature under bias...........................................................................................................–55°C to +125°C
Storage Temperature .............................................................................................................................–65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................... 0V to +7.5V
Voltage on MCLR with respect to VSS(2)......................................................................................................... 0V to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total Power Dissipation(1) ....................................................................................................................................800 mW
Max. Current out of VSS pin ..................................................................................................................................150 mA
Max. Current into VDD pin .....................................................................................................................................100 mA
Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA
Input Clamp Current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ............................................................................................................ ±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................20 mA
Max. Output Current sourced by a single I/O port (PORTA, B or C).......................................................................40 mA
Max. Output Current sunk by a single I/O port (PORTA, B or C)............................................................................50 mA
Note 1: Power Dissipation is calculated as follows: Pdis = VDD x {IDD – ∑ IOH} + ∑ {(VDD – VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50 to 100 Ω should be used when applying a “low” level to the MCLR pin rather than
pulling this pin directly to VSS.
†NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 61
PIC16C5X
PIC16C54/55/56/57
10.1
DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C
Typ(1)
Characteristic
Sym Min
Max Units
Conditions
Supply Voltage
PIC16C5X-RC
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-LP
VDD
—
—
—
—
—
—
3.0
3.0
4.5
4.5
2.5
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
FOSC = DC to 4 MHz
FOSC = DC to 4 MHz
FOSC = DC to 10 MHz
FOSC = DC to 20 MHz
FOSC = DC to 40 kHz
RAM Data Retention Voltage(2)
1.5*
VSS
—
—
V
V
Device in SLEEP Mode
VDR
VDD Start Voltage to ensure
Power-on Reset
VPOR
See Section 7.4 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
IDD
—
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
32
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
PIC16C5X-RC(4)
PIC16C5X-XT
PIC16C5X-10
PIC16C5X-HS
PIC16C5X-LP
Power-down Current(5)
IPD
—
—
4.0
0.6
12
9
µA
µA
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the
current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 62
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
10.2
DC Characteristics: PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +85°C
Typ(1)
Characteristic
Sym Min
Max Units
Conditions
Supply Voltage
PIC16C5X-RCI
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-LPI
VDD
3.0
3.0
4.5
4.5
2.5
—
—
—
—
—
6.25
6.25
5.5
5.5
6.25
V
V
V
V
V
FOSC = DC to 4 MHz
FOSC = DC to 4 MHz
FOSC = DC to 10 MHz
FOSC = DC to 20 MHz
FOSC = DC to 40 kHz
RAM Data Retention Voltage(2)
VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD Start Voltage to ensure
Power-on Reset
VPOR
See Section 7.4 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
IDD
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
15
3.3
3.3
10
10
20
40
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.0V,
WDT disabled
PIC16C5X-RCI(4)
PIC16C5X-XTI
PIC16C5X-10I
PIC16C5X-HSI
PIC16C5X-LPI
Power-down Current(5)
IPD
—
4.0
0.6
14
12
µA
µA
VDD = 3.0V, WDT enabled
VDD = 3.0V, WDT disabled
—
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the
current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 63
PIC16C5X
PIC16C54/55/56/57
10.3
DC Characteristics: PIC16C54/55/56/57-RCE, XTE, 10E, HSE, LPE (Extended)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C
Typ (1)
Characteristic
Sym Min
Max Units
Conditions
Supply Voltage
PIC16C5X-RCE
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-LPE
VDD
3.25
3.25
4.5
4.5
2.5
—
—
—
—
—
6.0
6.0
5.5
5.5
6.0
V
V
V
V
V
FOSC = DC to 4 MHz
FOSC = DC to 4 MHz
FOSC = DC to 10 MHz
FOSC = DC to 16 MHz
FOSC = DC to 40 kHz
RAM Data Retention Voltage(2)
VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD Start Voltage to ensure
Power-on Reset
VPOR
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
SVDD 0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
IDD
—
—
—
—
—
—
1.8
1.8
4.8
4.8
9.0
19
3.3
3.3
10
10
20
55
mA
mA
mA
mA
mA
µA
FOSC = 4 MHz, VDD = 5.5V
FOSC = 4 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
FOSC = 32 kHz, VDD = 3.25V,
WDT disabled
PIC16C5X-RCE(4)
PIC16C5X-XTE
PIC16C5X-10E
PIC16C5X-HSE
PIC16C5X-LPE
Power-down Current(5)
IPD
—
5.0
0.8
22
18
µA
µA
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
—
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the
current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 64
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
10.4
DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Commercial)
PIC16C54/55/56/57-RCI, XTI, 10I, HSI, LPI (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
All Pins Except
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Power Supply Pins
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and
Section 10.3.
Typ(1)
Characteristic
Sym
Min
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
VIL
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
PIC16C5X-RC only(4)
PIC16C5X-XT, 10, HS, LP
Input High Voltage
I/O ports
VIH
(5)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(5)
VDD > 5.5V
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(4)
PIC16C5X-XT, 10, HS, LP
Hysteresis of Schmitt
Trigger inputs
VHYS
IIL
0.15VDD*
—
—
V
Input Leakage Current(2,3)
I/O ports
For VDD ≤ 5.5V
–1
–5
0.5
+1
µA
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
PIC16C5X-XT, 10, HS, LP
µA
µA
µA
µA
MCLR
0.5
0.5
0.5
+5
+3
+3
–3
–3
T0CKI
OSC1
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
VOH
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
Output High Voltage
I/O ports(3)
OSC2/CLKOUT
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
age.
3: Negative current is defined as coming out of the pin.
4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 65
PIC16C5X
PIC16C54/55/56/57
10.5
DC Characteristics: PIC16C54/55/56/57-RC, XT, 10, HS, LP (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and
Section 10.3.
DC Characteristics
All Pins Except
Power Supply Pins
Typ(1)
Characteristic
Sym
Min
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
VIL
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
PIC16C5X-RC only(4)
PIC16C5X-XT, 10, HS, LP
Input High Voltage
I/O ports
VIH
(5)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(5)
VDD > 5.5 V
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
PIC16C5X-RC only(4)
PIC16C5X-XT, 10, HS, LP
Hysteresis of Schmitt
Trigger inputs
VHYS
IIL
0.15VDD*
—
—
V
Input Leakage Current (2,3)
I/O ports
For VDD ≤ 5.5 V
–1
–5
0.5
+1
µA
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VPIN = VSS + 0.25V
VPIN = VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
PIC16C5X-XT, 10, HS, LP
µA
µA
µA
µA
MCLR
0.5
0.5
0.5
+5
+3
+3
–3
–3
T0CKI
OSC1
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
VOH
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
PIC16C5X-RC
Output High Voltage
I/O ports(3)
OSC2/CLKOUT
VDD – 0.7
VDD – 0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
PIC16C5X-RC
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For PIC16C5X-RC devices, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C5X be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
DS30453C-page 66
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
10.6
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 10-1: LOAD CONDITIONS - PIC16C54/55/56/57
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT, HS or LP
modes when external clock
is used to drive OSC1
VSS
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 67
PIC16C5X
PIC16C54/55/56/57
10.7
Timing Diagrams and Specifications
FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16C54/55/56/57
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3
Parameter
No.
Sym
Characteristic
Min Typ(1)
Max Units
Conditions
External CLKIN Frequency(2)
FOSC
DC
DC
DC
DC
DC
DC
0.1
4
—
—
—
—
—
—
—
—
—
—
—
4
MHz XT osc mode
MHz 10 MHz mode
10
20
16
40
4
MHz HS osc mode (Com/Indust)
MHz HS osc mode (Extended)
kHz LP osc mode
Oscillator Frequency(2)
MHz RC osc mode
4
MHz XT osc mode
10
20
16
40
MHz 10 MHz mode
4
MHz HS osc mode (Com/Indust)
MHz HS osc mode (Extended)
kHz LP osc mode
4
DC
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453C-page 68
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54/55/56/57 (CON’T)
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3
Parameter
No.
Sym
Characteristic
Min Typ(1)
Max Units
Conditions
External CLKIN Period(2)
1
TOSC
250
100
50
—
—
—
—
—
—
—
—
ns XT osc mode
ns 10 MHz mode
—
ns HS osc mode (Com/Indust)
ns HS osc mode (Extended)
µs LP osc mode
62.5
25
—
—
Oscillator Period(2)
250
250
100
50
—
ns RC osc mode
—
10,000 ns XT osc mode
—
250
250
250
—
ns 10 MHz mode
ns HS osc mode (Com/Indust)
ns HS osc mode (Extended)
µs LP osc mode
—
62.5
25
—
—
Instruction Cycle Time(3)
2
3
TCY
—
4/FOSC
—
—
TosL, TosH Clock in (OSC1) Low or High
Time
85*
20*
2*
—
—
—
—
—
—
—
—
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
25*
25*
50*
—
—
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 69
PIC16C5X
PIC16C54/55/56/57
FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16C54/55/56/57
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
16
18
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and
Section 10.3
Parameter
No.
10
11
Sym
TosH2ckL
TosH2ckH
TckR
Characteristic
OSC1↑ to CLKOUT↓(2)
Min
Typ(1)
15
15
5
Max
30**
30**
15**
15**
40**
—
Units
ns
—
OSC1↑ to CLKOUT↑(2)
—
ns
CLKOUT rise time(2)
12
13
14
15
16
17
18
—
ns
CLKOUT fall time(2)
TckF
—
5
ns
CLKOUT↓ to Port out valid(2)
Port in valid before CLKOUT↑(2)
Port in hold after CLKOUT↑(2)
OSC1↑ (Q1 cycle) to Port out valid(3)
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
—
—
ns
0.25 TCY+30*
—
ns
0*
—
—
—
ns
—
100*
—
ns
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
ns
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
Port output rise time(3)
Port output fall time(3)
20
21
TioR
TioF
—
—
10
10
25**
25**
ns
ns
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 10-1 for loading conditions.
DS30453C-page 70
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
FIGURE 10-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING -
PIC16C54/55/56/57
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54/55/56/57
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and Section 10.3
Parameter
No.
Typ(1)
Sym Characteristic
Min
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
100*
9*
—
—
ns VDD = 5.0V
Twdt Watchdog Timer Time-out Period
(No Prescaler)
18*
30*
ms VDD = 5.0V (Commercial)
32
34
TDRT Device Reset Timer Period
9*
18*
30*
ms VDD = 5.0V (Commercial)
ns
TioZ I/O Hi-impedance from MCLR Low
—
—
100*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 71
PIC16C5X
PIC16C54/55/56/57
FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16C54/55/56/57
T0CKI
40
41
42
TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54/55/56/57
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 10.1, Section 10.2 and
Section 10.3
Parameter
Typ(1)
Max Units Conditions
Sym Characteristic
Min
No.
40
Tt0H T0CKI High Pulse Width- No Prescaler 0.5 TCY + 20*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
- With Prescaler
Tt0L T0CKI Low Pulse Width- No Prescaler
- With Prescaler
10*
0.5 TCY + 20*
10*
41
42
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453C-page 72
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
11.0 DC AND AC CHARACTERISTICS - PIC16C54/55/56/57
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the
data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and
devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
REXT ≥ 10 kΩ
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
VDD = 5.5 V
VDD = 3.5 V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 11-1: RC OSCILLATOR FREQUENCIES
Average
FOSC @ 5 V, 25°C
CEXT
REXT
20 pF
3.3 k
5 k
4.973 MHz
3.82 MHz
2.22 MHz
262.15 kHz
1.63 MHz
1.19 MHz
684.64 kHz
71.56 kHz
660 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10 k
100 k
3.3 k
5 k
100 pF
300 pF
10 k
100 k
3.3 k
5.0 k
10 k
160 k
484.1 kHz
267.63 kHz
29.44 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviations from the average value for VDD = 5 V.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 73
PIC16C5X
PIC16C54/55/56/57
FIGURE 11-2: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
FIGURE 11-3: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
CEXT = 20 PF
CEXT = 100 PF
5.5
1.8
R = 3.3k
R = 3.3k
5.0
1.6
4.5
1.4
R = 5k
R = 5k
4.0
1.2
1.0
3.5
3.0
0.8
R = 10k
R = 10k
2.5
0.6
Measured on DIP Packages, T = 25°C
2.0
0.4
Measured on DIP Packages, T = 25°C
0.2
1.5
R = 100k
0.0
1.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
R = 100k
0.5
FIGURE 11-4: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD,
0.0
CEXT = 300 PF
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
800
700
R = 3.3k
600
R = 5k
500
400
300
200
100
0
R = 10k
Measured on DIP Packages, T = 25°C
R = 100k
5.5 6.0
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
DS30453C-page 74
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
FIGURE 11-5: TYPICAL IPD vs. VDD,
WATCHDOG DISABLED
FIGURE 11-7: TYPICAL IPD vs. VDD,
WATCHDOG ENABLED
2.5
20
18
16
2.0
14
12
T = 25°C
T = 25°C
1.5
10
8
1.0
0.5
6
4
2
0
0.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (Volts)
VDD (Volts)
FIGURE 11-6: MAXIMUM IPD vs. VDD,
WATCHDOG DISABLED
FIGURE 11-8: MAXIMUM IPD vs. VDD,
WATCHDOG ENABLED
60
100
50
+125°C
+85°C
10
40
–55°C
+70°C
0°C
+85°C
30
–40°C
+125°C
–40°C
+70°C
–55°C
1
20
10
0
0°C
0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDD (Volts)
VDD (Volts)
IPD, with WDT enabled, has two components:
The leakage current, which increases with higher tempera-
ture, and the operating current of the WDT logic, which
increases with lower temperature. At –40°C, the latter domi-
nates explaining the apparently anomalous behavior.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 75
PIC16C5X
PIC16C54/55/56/57
FIGURE 11-9: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.00
)
1.80
1.60
1.40
1.20
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
)
C
°
5
2
+
(
p
y
T
)
C
°
5
8
+
1.00
0.80
o
t
C
°
0
4
–
(
n
i
M
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 11-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
)
4.0
C
°
5
8
+
o
t
C
°
0
4
–
(
3.5
3.0
2.5
2.0
1.5
x
a
H m
VI
)
C
°
5
8
+
o
t
C
°
0
4
–
(
n
i
H m
VI
L
I
H
I
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note: These input pins have Schmitt Trigger input buffers.
FIGURE 11-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
)
2.8
2.6
2.4
2.2
2.0
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30453C-page 76
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (EXTERNAL CLOCK, 25°C)
10
1.0
0.1
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 11-13: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK, –40°C TO +85°C)
10
1.0
7.0
6.5
6.0
0.1
5.5
5.0
4.5
4.0
3.5
3.0
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 77
PIC16C5X
PIC16C54/55/56/57
FIGURE 11-14: MAXIMUM IDD vs. FREQUENCY (EXTERNAL CLOCK –55°C TO +125°C)
10
1.0
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.1
2.5
0.01
10k
100k
1M
10M
100M
External Clock Frequency (Hz)
FIGURE 11-15: WDT TIMER TIME-OUT
PERIOD vs. VDD
FIGURE 11-16: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR vs. VDD
50
45
40
9000
8000
Max –40°C
7000
6000
35
30
5000
Max +85°C
Typ +25°C
25
4000
3000
Max +70°C
20
Typ +25°C
Min +85°C
15
2000
MIn 0°C
10
100
0
MIn –40°C
5
2
3
4
5
6
7
2
3
4
5
6
7
VDD (Volts)
VDD (Volts)
DS30453C-page 78
Preliminary
2000 Microchip Technology Inc.
PIC16C54/55/56/57
PIC16C5X
FIGURE 11-17: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR vs. VDD
FIGURE 11-19: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR vs. VDD
45
2500
40
Max –40°C
Max –40°C
2000
35
30
1500
25
Typ +25°C
Typ +25°C
20
1000
15
Min +85°C
500
10
Min +85°C
5
0
0
2
3
4
5
6
7
2
3
4
5
6
7
VDD (Volts)
VDD (Volts)
FIGURE 11-18: IOH vs. VOH, VDD = 3 V
FIGURE 11-20: IOH vs. VOH, VDD = 5 V
0
0
Min +85°C
–5
–10
Min +85°C
–10
–20
Typ +25°C
Typ +25°C
–15
Max –40°C
–30
Max –40°C
–20
–40
–25
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
0.5 1.0 1.5 2.0
VOH (Volts)
2.5 3.0
VOH (Volts)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 79
PIC16C5X
PIC16C54/55/56/57
FIGURE 11-21: IOL vs. VOL, VDD = 3 V
FIGURE 11-22: IOL vs. VOL, VDD = 5 V
90
80
70
45
Max –40°C
Max –40°C
40
35
60
50
30
25
Typ +25°C
Typ +25°C
Min +85°C
40
20
Min +85°C
30
20
15
10
10
0
5
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0
0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
VOL (Volts)
TABLE 11-2: INPUT CAPACITANCE FOR
PIC16C54/56
TABLE 11-3: INPUT CAPACITANCE FOR
PIC16C55/57
Typical Capacitance (pF)
Pin
Typical Capacitance (pF)
Pin
18L PDIP
18L SOIC
28L PDIP
(600 mil)
28L SOIC
RA port
RB port
5.0
4.3
RA port
RB port
5.2
5.6
5.0
17.0
6.6
4.6
4.5
4.8
4.7
4.1
17.0
3.5
3.5
3.5
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
RC port
OSC1
MCLR
OSC2/CLKOUT
T0CKI
4.3
3.5
OSC1
3.2
2.8
OSC2/CLKOUT
T0CKI
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
DS30453C-page 80
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
12.0 ELECTRICAL CHARACTERISTICS - PIC16CR54A
Absolute Maximum Ratings†
Ambient Temperature under bias...........................................................................................................–55°C to +125°C
Storage Temperature .............................................................................................................................–65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS(2)............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total Power Dissipation(1) ....................................................................................................................................800 mW
Max. Current out of VSS pin ..................................................................................................................................150 mA
Max. Current into VDD pin .......................................................................................................................................50 mA
Max. Current into an input pin (T0CKI only) ....................................................................................................................±500 µA
Input Clamp Current, IIK (VI < 0 or VI > VDD) ................................................................................................................... ±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD).............................................................................................................±20 mA
Max. Output Current sunk by any I/O pin................................................................................................................25 mA
Max. Output Current sourced by any I/O pin...........................................................................................................20 mA
Max. Output Current sourced by a single I/O port (PORTA or B) ...........................................................................40 mA
Max. Output Current sunk by a single I/O port (PORTA or B).................................................................................50 mA
Note 1: Power Dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
2: Voltage spikes below Vss at the MCLR pin, inducing currents greater than 80 mA may cause latch-up. Thus,
a series resistor of 50 to 100Ω should be used when applying a low level to the MCLR pin rather than pulling
this pin directly to Vss.
†NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 81
PIC16C5X
PIC16CR54A
12.1
DC Characteristics: PIC16CR54A-04, 10, 20 (Commercial)
PIC16CR54A-04I, 10I, 20I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Typ(1)
Characteristic
Sym
Min
Max Units
Conditions
Supply Voltage
RC and XT options
HS option
VDD
2.5
4.5
6.25
5.5
V
V
RAM Data Retention Voltage(2)
VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD Start Voltage to ensure
Power-on Reset
VPOR
See Section 7.4 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
IDD
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
2.0
0.8
90
4.8
9.0
3.6
1.8
350
10
mA
mA
µA
mA
mA
FOSC = 4.0 MHz, VDD = 6.0V
FOSC = 4.0 MHz, VDD = 3.0V
FOSC = 200 kHz, VDD = 2.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 20 MHz, VDD = 5.5V
RC(4) and XT options
HS option
20
Power-down Current(5)
Commercial
IPD
IPD
1.0
2.0
3.0
5.0
6.0
8.0*
15
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
25
Power-down Current(5)
Industrial
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
µA
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
45
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on the
current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 82
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
12.2
DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C (extended)
Typ(1)
Characteristic
Sym
Min
Max Units
Conditions
Supply Voltage
RC, XT and LP options
HS options
VDD
3.25
4.5
—
—
6.0
5.5
V
V
RAM Data Retention Voltage(2)
VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD Start Voltage to ensure
Power-on Reset
VPOR
See Section 7.4 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
RC(4) and XT options
IDD
—
1.8
4.8
9.0
3.3
10
20
mA
mA
mA
FOSC = 4.0 MHz, VDD = 5.5V
FOSC = 10 MHz, VDD = 5.5V
FOSC = 16 MHz, VDD = 5.5V
—
—
HS option
Power-down Current(5)
IPD
—
5.0
0.8
22
18
µA
µA
VDD = 3.25V, WDT enabled
VDD = 3.25V, WDT disabled
—
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 83
PIC16C5X
PIC16CR54A
12.3
DC Characteristics: PIC16LCR54A-04 (Commercial)
PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
DC Characteristics
Power Supply Pins
–40°C ≤ TA ≤ +85°C (industrial)
Typ(1)
Characteristic
Sym
Min
Max Units
Conditions
Supply Voltage
VDD
VDR
2.0
—
6.25
V
V
LP Option
RAM Data Retention Voltage(2)
—
1.5*
—
Device in SLEEP mode
VDD Start Voltage to ensure
Power-on Reset
VPOR
—
VSS
—
V
See Section 7.4 for details on
Power-on Reset
VDD Rise Rate to ensure
Power-on Reset
SVDD 0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
IDD
IPD
—
10
20
70
µA
µA
FOSC = 32 kHz, VDD = 2.0V
FOSC = 32 kHz, VDD = 6.0V
Power-down Current(5)
Commercial
—
—
—
—
1.0
2.0
3.0
5.0
6.0
8.0*
15
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
25
Power-down Current(5)
IPD
Industrial
—
—
—
—
—
1.0
2.0
3.0
3.0
5.0
8.0
10*
20*
18
µA
µA
µA
µA
µA
VDD = 2.5V, WDT disabled
VDD = 4.0V, WDT disabled
VDD = 4.0V, WDT enabled
VDD = 6.0V, WDT disabled
VDD = 6.0V, WDT enabled
45
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 84
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
12.4
DC Characteristics: PIC16CR54A-04, 10, 20, PIC16LCR54A-04 (Commercial)
PIC16CR54A-04I, 10I, 20I, PIC16LCR54A-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
All Pins Except
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Operating Voltage VDD range is described in Section 12.1 and Section 12.3.
Typ(1)
Characteristic
Sym
Min
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VIL
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
V
V
V
V
V
Pin at hi-impedance
RC option only(4)
XT, HS and LP options
Input High Voltage
I/O ports
VIH
VDD = 3.0V to 5.5V(5)
Full VDD range(5)
2.0
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
0.6 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.85 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC option only(4)
XT, HS and LP options
Hysteresis of Schmitt
Trigger inputs
VHYS 0.15VDD*
—
—
V
Input Leakage Current(3)
I/O ports
IIL
For VDD ≤ 5.5V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
–1.0
+1.0
µA
–5.0
µA
µA
µA
µA
MCLR
VPIN = VSS + 0.25V(2)
0.5
0.5
0.5
+5.0
+3.0
+3.0
(2)
VPIN = VDD
–3.0
–3.0
T0CKI
OSC1
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
—
—
—
0.5
0.5
V
V
IOL = 10 mA, VDD = 6.0V
IOL = 1.9 mA, VDD = 6.0V,
RC option only
—
Output High Voltage(3)
I/O ports
VOH
VDD –0.5
VDD –0.5
—
—
—
—
V
V
IOH = –4.0 mA, VDD = 6.0V
IOH = –0.8 mA, VDD = 6.0V,
RC option only
OSC2/CLKOUT
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 85
PIC16C5X
PIC16CR54A
12.5
DC Characteristics: PIC16CR54A-04E, 10E, 20E (Extended)
DC Characteristics
All Pins Except
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C
Operating Voltage VDD range is described in Section 12.2.
Typ(1)
Characteristic
Sym
Min
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VIL
Vss
Vss
Vss
Vss
Vss
—
—
—
—
—
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
V
Pin at hi-impedance
RC option only(4)
XT, HS and LP options
Input High Voltage
I/O ports
VIH
(5)
0.45 VDD
2.0
—
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(5)
VDD > 5.5V
0.36 VDD
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC option only(4)
XT, HS and LP options
Hysteresis of Schmitt
Trigger inputs
VHYS 0.15VDD*
—
—
V
Input Leakage Current(3)
I/O ports
IIL
For VDD ≤ 5.5V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
–1.0
0.5
+1.0
µA
VPIN = VSS + 0.25V(2)
–5.0
µA
µA
µA
µA
MCLR
0.5
0.5
0.5
+5.0
+3.0
+3.0
(2)
VPIN = VDD
–3.0
–3.0
T0CKI
OSC1
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC option only
—
Output High Voltage (3)
I/O ports
VOH
VDD –0.7
VDD –0.7
—
—
—
—
V
V
IOH = –5.4 mA, VDD = 4.5V
IOH = –1.0 mA, VDD = 4.5V,
RC option only
OSC2/CLKOUT
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltage.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
DS30453C-page 86
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
12.6
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 12-1: LOAD CONDITIONS
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT, HS or LP
options when external clock
is used to drive OSC1
VSS
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 87
PIC16C5X
PIC16CR54A
12.7
Timing Diagrams and Specifications
FIGURE 12-2: EXTERNAL CLOCK TIMING - PIC16CR54A
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
External CLKIN Frequency(2)
FOSC
DC
DC
DC
DC
DC
DC
0.1
4.0
4.0
4.0
5.0
—
—
—
—
—
—
—
—
—
—
—
4.0 MHz XT osc mode
4.0 MHz HS osc mode (04)
10
20
MHz HS osc mode (10)
MHz HS osc mode (20)
200 kHz LP osc mode
4.0 MHz RC osc mode
4.0 MHz XT osc mode
4.0 MHz HS osc mode (04)
Oscillator Frequency(2)
10
20
MHz HS osc mode (10)
MHz HS osc mode (20)
200 kHz LP osc mode
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453C-page 88
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
TABLE 12-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54A (CON’T)
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
External CLKIN Period(2)
1
TOSC
250
250
100
50
—
—
—
—
—
—
—
—
—
—
—
—
—
ns XT osc mode
ns HS osc mode (04)
ns HS osc mode (10)
ns HS osc mode (20)
µs LP osc mode
5.0
Oscillator Period(2)
250
250
ns RC osc mode
10,00 ns XT osc mode
0
250
100
50
—
—
—
—
250
250
250
200
—
ns HS osc mode (04)
ns HS osc mode (10)
ns HS osc mode (20)
µs LP osc mode
—
5.0
—
Instruction Cycle Time(3)
2
3
TCY
4/FOS
C
TosL, TosH Clock in (OSC1) Low or High
Time
50*
20*
2.0*
—
—
—
—
—
—
—
—
—
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
25*
25*
50*
—
—
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 89
PIC16C5X
PIC16CR54A
FIGURE 12-3: CLKOUT AND I/O TIMING - PIC16CR54A
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
12
13
18
19
16
14
I/O Pin
(input)
15
17
I/O Pin
Old Value
(output)
New Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 12-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54A
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 12.1, Section 12.2 and
Section 12.3.
Parameter
No.
10
11
Sym
TosH2ckL
TosH2ckH
TckR
Characteristic
OSC1↑ to CLKOUT↓(2)
Min
Typ(1)
15
Max
30**
30**
15**
15**
40**
—
Units
ns
—
OSC1↑ to CLKOUT↑(2)
—
15
ns
CLKOUT rise time(2)
12
13
14
15
16
17
18
—
5.0
5.0
—
ns
CLKOUT fall time(2)
TckF
—
ns
CLKOUT↓ to Port out valid(2)
Port in valid before CLKOUT↑(2)
Port in hold after CLKOUT↑(2)
OSC1↑ (Q1 cycle) to Port out valid(3)
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
—
ns
0.25 TCY+30*
—
ns
0*
—
—
—
ns
—
100*
—
ns
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
ns
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
Port output rise time(3)
Port output fall time(3)
20
21
TioR
TioF
—
—
10
10
25**
25**
ns
ns
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 12-1 for loading conditions.
DS30453C-page 90
Preliminary
2000 Microchip Technology Inc.
PIC16CR54A
PIC16C5X
FIGURE 12-4: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER TIMING - PIC16CR54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 12-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 12.1, Section 12.2 and Section 12.3.
Parameter
No.
Typ(1)
Sym Characteristic
Min
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
1.0*
7.0*
—
—
µs VDD = 5.0V
Twdt Watchdog Timer Time-out Period
(No Prescaler)
18*
40*
ms VDD = 5.0V (Commercial)
32
34
TDRT Device Reset Timer Period
7.0*
18*
30*
ms VDD = 5.0V (Commercial)
TioZ I/O Hi-impedance from MCLR Low
—
—
1.0*
µs
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 91
PIC16C5X
PIC16CR54A
FIGURE 12-5: TIMER0 CLOCK TIMINGS - PIC16CR54A
T0CKI
40
41
42
TABLE 12-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 12.1, Section 12.2 and
Section 12.3.
Param
No.
Typ(1)
Max Units Conditions
Sym Characteristic
Min
40
41
42
Tt0H T0CKI High Pulse Width- No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5.0V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453C-page 92
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
13.0 ELECTRICAL CHARACTERISTICS - PIC16C54A
Absolute Maximum Ratings†
Ambient temperature under bias............................................................................................................–55°C to +125°C
Storage temperature............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS ...............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin............................................................................................................20 mA
Max. output current sourced by a single I/O port (PORTA or B).............................................................................50 mA
Max. output current sunk by a single I/O port (PORTA or B) ..................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 93
PIC16C5X
PIC16C54A
13.1
DC Characteristics: PIC16C54A-04, 10, 20 (Commercial)
PIC16C54A-04I, 10I, 20I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
XT, RC and LP options
HS option
VDD
3.0
4.5
—
—
6.25
5.5
V
V
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
Supply Current(3)
XT and RC(4) options
HS option
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
—
—
—
—
—
1.8
2.4
4.5
14
2.4 mA FOSC = 4.0 MHz, VDD = 5.5V
8.0 mA FOSC = 10 MHz, VDD = 5.5V
16
29
37
mA FOSC = 20 MHz, VDD = 5.5V
µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
µA FOSC = 32 kHz, VDD = 3.0V, WDT disabled
LP option, Commercial
LP option, Industrial
17
Power-down Current(5)
IPD
Commercial
—
—
—
—
4.0
0.25 4.0
5.0
0.3
12
µA VDD = 3.0V, WDT enabled
µA VDD = 3.0V, WDT disabled
µA VDD = 3.0V, WDT enabled
µA VDD = 3.0V, WDT disabled
Industrial
14
5.0
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 94
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
13.2
DC Characteristics: PIC16C54A-04E, 10E, 20E (Extended)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
XT and RC options
HS option
VDD
3.5
4.5
—
—
5.5
5.5
V
V
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
XT and RC(4) options
HS option
—
—
—
1.8
4.8
9.0
3.3 mA FOSC = 4.0 MHz, VDD = 5.5V
10
20
mA FOSC = 10 MHz, VDD = 5.5V
mA FOSC = 20 MHz, VDD = 5.5V
Power-down Current(5)
IPD
XT and RC options
—
—
—
—
5.0
0.8
4.0
22
18
22
18
µA VDD = 3.5V, WDT enabled
µA VDD = 3.5V, WDT disabled
µA VDD = 3.5V, WDT enabled
µA VDD = 3.5V, WDT disabled
HS option
0.25
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 95
PIC16C5X
PIC16C54A
13.3
DC Characteristics: PIC16LC54A-04 (Commercial)
PIC16LC54A-04I (Industrial))
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Power Supply Pins
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
XT and RC options
LP options
VDD
3.0
2.5
—
—
6.25
6.25
V
V
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
XT and RC(4) options
LP option, Commercial
LP option, Industrial
LP option, Extended
—
—
—
—
0.5
11
11
11
2.5 mA FOSC = 4.0 MHz, VDD = 5.5V
27
35
37
µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
µA FOSC = 32 kHz, VDD = 2.5V WDT disabled
Power-down Current(5)
IPD
Commercial
—
—
—
—
—
—
2.5
12
µA VDD = 2.5V, WDT enabled
µA VDD = 2.5V, WDT disabled
µA VDD = 2.5V, WDT enabled
µA VDD = 2.5V, WDT disabled
µA VDD = 2.5V, WDT enabled
µA VDD = 2.5V, WDT disabled
0.25 4.0
2.5 14
0.25 5.0
2.5 15
0.25 7.0
Industrial
Extended
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 96
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
13.4
DC Characteristics: PIC16C54A-04, 10, 20, PIC16LC54A-04, PIC16LV54A-02 (Commercial)
PIC16C54A-04I, 10I, 20I, PIC16LC54A-04I, PIC16LV54A-02I (Industrial)
PIC16C54A-04E, 10E, 20E (Extended)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
DC Characteristics
All Pins Except
Power Supply Pins
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and
Section 13.3.
Characteristic
Sym
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VIL
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.2 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
V
V
V
V
Pin at hi-impedance
RC option only(4)
XT, HS and LP options
Input High Voltage
I/O ports
VIH
(5)
0.2 VDD+1V
2.0
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
For all VDD
4.0V < VDD ≤ 5.5V(5)
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC option only(4)
XT, HS and LP options
Hysteresis of Schmitt
Trigger inputs
VHYS 0.15VDD*
—
—
V
Input Leakage Current(3)
IIL
For VDD ≤ 5.5V
I/O ports
-1.0
—
-5.0
0.5
—
—
0.5
0.5
0.5
+1.0
—
+5.0
+3.0
+3.0
—
µA VSS ≤ VPIN ≤ VDD,
—
Pin at hi-impedance
MCLR
µA VPIN = VSS +0.25V(2)
(2)
µA VPIN = VDD
T0CKI
OSC1
-3.0
-3.0
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
VOH
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC option only
Output High Voltage
I/O ports(3)
OSC2/CLKOUT
VDD-0.7
VDD-0.7
—
—
—
—
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC option only
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input volt-
age.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X
be driven with external clock in RC mode.
5: The user may use the better of the two specifications.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 97
PIC16C5X
PIC16C54A
13.5
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 13-1: LOAD CONDITIONS - PIC16C54A
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT, HS or LP
options when external clock
is used to drive OSC1
VSS
DS30453C-page 98
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
13.6
Timing Diagrams and Specifications
FIGURE 13-2: EXTERNAL CLOCK TIMING - PIC16C54A
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
FOSC
External CLKIN Frequency(2) DC
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0 MHz XT osc mode
DC
DC
DC
DC
DC
2.0 MHz XT osc mode (PIC16LV54A)
4.0 MHz HS osc mode (04)
10
20
MHz HS osc mode (10)
MHz HS osc mode (20)
200 kHz LP osc mode
Oscillator Frequency(2)
DC
DC
0.1
0.1
4
4.0 MHz RC osc mode
2.0 MHz RC osc mode (PIC16LV54A)
4.0 MHz XT osc mode
2.0 MHz XT osc mode (PIC16LV54A)
4.0 MHz HS osc mode (04)
4
10
20
MHz HS osc mode (10)
MHz HS osc mode (20)
4
5
200 kHz LP osc mode
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 99
PIC16C5X
PIC16C54A
TABLE 13-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C54A (CON’T)
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
1
TOSC
External CLKIN Period(2)
250
500
250
100
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns XT osc mode
ns XT osc mode (PIC16LV54A)
ns HS osc mode (04)
ns HS osc mode (10)
ns HS osc mode (20)
µs LP osc mode
5.0
Oscillator Period(2)
250
500
250
ns RC osc mode
ns RC osc mode (PIC16LV54A)
10,00 ns XT osc mode
0
500
250
100
50
—
—
—
—
—
—
ns XT osc mode (PIC16LV54A)
250
250
250
200
—
ns HS osc mode (04)
ns HS osc mode (10)
ns HS osc mode (20)
µs LP osc mode
—
5.0
—
2
3
TCY
Instruction Cycle Time(3)
4/FOS
C
TosL, TosH Clock in (OSC1) Low or High 85*
—
—
—
—
—
—
—
—
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
Time
20*
2.0*
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
—
—
25*
25*
50*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453C-page 100
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 13-3: CLKOUT AND I/O TIMING - PIC16C54A
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
16
18
14
19
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: All tests must be done with specified capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.
TABLE 13-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C54A
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and
Section 13.3.
Parameter
No.
Sym
Characteristic
OSC1↑ to CLKOUT↓(2)
Min
Typ(1)
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL
TosH2ckH
TckR
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
OSC1↑ to CLKOUT↑(2)
—
CLKOUT rise time(2)
—
TckF
CLKOUT fall time(2)
—
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
CLKOUT↓ to Port out valid(2)
Port in valid before CLKOUT↑(2)
Port in hold after CLKOUT↑(2)
OSC1↑ (Q1 cycle) to Port out valid(3)
—
0.25 TCY+30*
—
0*
—
—
—
—
100*
—
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
TioR
TioF
Port output rise time(3)
Port output fall time(3)
—
—
10
10
25**
25**
ns
ns
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 14-1 for loading conditions.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 101
PIC16C5X
PIC16C54A
FIGURE 13-4: RESET, WATCHDOG TIMER, AND
DEVICE RESET TIMER TIMING - PIC16C54A
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 13-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and Section 13.3.
Parameter
No.
Sym Characteristic
Min Typ(1) Max Units
Conditions
30
TmcL MCLR Pulse Width (low)
100*
1µs
—
—
—
—
ns VDD = 5.0V
VDD = 5.0V (PIC16LV54A only)
—
31
Twdt Watchdog Timer Time-out
Period (No Prescaler)
9.0*
18*
30*
ms VDD = 5.0V (Commercial)
32
34
TDRT Device Reset Timer Period
9.0*
18*
30*
ms VDD = 5.0V (Commercial)
ns
TioZ I/O Hi-impedance from MCLR
Low
—
—
—
—
100*
1µs
—
(PIC16LV54A only)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453C-page 102
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 13-5: TIMER0 CLOCK TIMINGS - PIC16C54A
T0CKI
40
41
42
TABLE 13-4: TIMER0 CLOCK REQUIREMENTS - PIC16C54A
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–20°C ≤ TA ≤ +85°C (industrial - PIC16LV54A-02I)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 13.1, Section 13.2 and
Section 13.3.
Param
No.
Sym Characteristic
Min
Typ(1) Max Units Conditions
40
41
42
Tt0H T0CKI High Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid-
ance only and are not tested.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 103
PIC16C5X
PIC16C54A
NOTES:
DS30453C-page 104
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
14.0 DC AND AC CHARACTERISTICS - PIC16C54A
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables,
the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution, while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 14-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
REXT ≥ 10 kΩ
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
VDD = 5.5 V
VDD = 3.5 V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 14-1: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5 V, 25°C
CEXT
REXT
20 pF
3.3 k
5 k
4.973 MHz
3.82 MHz
2.22 MHz
262.15 kHz
1.63 MHz
1.19 MHz
684.64 kHz
71.56 kHz
660 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10 k
100 k
3.3 k
5 k
100 pF
300 pF
10 k
100 k
3.3 k
5.0 k
10 k
160 k
484.1 kHz
267.63 kHz
29.44 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5 V.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 105
PIC16C5X
PIC16C54A
FIGURE 14-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF
6.00
R=3.3K
5.00
R=5.0K
4.00
3.00
R=10K
2.00
CEXT=20pF, T=25°C
1.00
R=100K
0.00
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volts)
FIGURE 14-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF
1.80
R=3.3K
1.60
1.40
R=5.0K
1.20
1.00
0.80
R=10K
0.60
CEXT=100pF, T=25°C
0.40
0.20
R=100K
0.00
2.5
3
3.5
4
4.5
5
5.5
6
VDD (Volts)
DS30453C-page 106
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 14-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF
700.00
R=3.3K
600.00
500.00
R=5.0K
400.00
300.00
R=10K
200.00
CEXT=300pF, T=25°C
100.00
R=100K
0.00
2.5
3
3.5
4
4.5
6
5.5
5
VDD (Volts)
FIGURE 14-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
2.50
2.00
1.50
1.00
0.50
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 107
PIC16C5X
PIC16C54A
FIGURE 14-6: VTH (INPUT THRESHOLD VOLTAGE) OF I/O PINS vs. VDD
2.00
)
1.80
1.60
1.40
1.20
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
)
C
°
5
2
+
(
p
y
T
)
C
°
5
8
+
1.00
0.80
o
t
C
°
0
4
–
(
n
i
M
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 14-7: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
)
4.0
C
°
5
8
+
o
t
C
°
0
4
–
(
3.5
3.0
2.5
2.0
1.5
x
a
H m
VI
)
C
°
5
8
+
o
t
C
°
0
4
–
(
n
i
H m
VI
L
I
H
I
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note: These input pins have Schmitt Trigger input buffers.
FIGURE 14-8: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT
(IN XT, HS, AND LP MODES) vs. VDD
3.4
3.2
3.0
)
2.8
2.6
2.4
2.2
2.0
C
°
5
8
+
o
t
C
°
0
4
–
(
x
a
M
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30453C-page 108
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 14-9: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25°C)
10000
1000
6.0V
5.5V
5.0V
100
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.1
1
10
Freq (MHz)
FIGURE 14-10: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, –40°C TO +85°C)
10000
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
100
10
0.1
1
10
Freq (MHz)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 109
PIC16C5X
PIC16C54A
FIGURE 14-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25°C)
10000
1000
6.0V
5.5V
5.0V
100
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
1
10
0.1
Freq (MHz)
FIGURE 14-12: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, –40°C TO +85°C)
10000
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
100
10
0.01
0.1
1
10
Freq (MHz)
DS30453C-page 110
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 14-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25°C)
10000
1000
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
100
10
0.01
0.1
1
Freq (MHz)
FIGURE 14-14: MAXIMUM IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, –40°C TO +85°C)
10000
1000
6.0V
5.5V
5.0V
100
4.5V
4.0V
3.5V
3.0V
2.5V
10
0.01
0.1
1
Freq (MHz)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 111
PIC16C5X
PIC16C54A
FIGURE 14-15: WDT TIMER TIME-OUT
PERIOD vs. VDD
TABLE 14-2: INPUT CAPACITANCE FOR
PIC16C54A/C58A
Typical Capacitance (pF)
Pin
50
45
40
18L PDIP
18L SOIC
RA port
RB port
5.0
4.3
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
35
OSC2/CLKOUT
T0CKI
4.3
3.5
30
3.2
2.8
Max +85°C
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
25
Max +70°C
20
Typ +25°C
15
MIn 0°C
10
MIn –40°C
5
2
3
4
5
6
7
VDD (Volts)
DS30453C-page 112
Preliminary
2000 Microchip Technology Inc.
PIC16C54A
PIC16C5X
FIGURE 14-18: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR vs. VDD
FIGURE 14-16: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR vs. VDD
2500
9000
8000
Max –40°C
Max –40°C
2000
7000
6000
1500
5000
Typ +25°C
Typ +25°C
1000
4000
3000
Min +85°C
500
Min +85°C
2000
100
0
0
2
3
4
5
6
7
VDD (Volts)
2
3
4
5
6
7
VDD (Volts)
FIGURE 14-17: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR vs. VDD
45
40
Max –40°C
35
30
25
Typ +25°C
20
15
10
Min +85°C
5
0
2
3
4
5
6
7
VDD (Volts)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 113
PIC16C5X
PIC16C54A
FIGURE 14-19: IOH vs. VOH, VDD = 3 V
FIGURE 14-21: IOL vs. VOL, VDD = 3 V
0
45
40
35
Max –40°C
–5
Min +85°C
30
25
–10
Typ +25°C
Typ +25°C
Min +85°C
–15
20
Max –40°C
15
10
–20
5
0
–25
0
0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 14-20: IOH vs. VOH, VDD = 5 V
FIGURE 14-22: IOL vs. VOL, VDD = 5 V
90
0
Max –40°C
80
Min +85°C
70
60
–10
Typ +25°C
50
–20
Typ +25°C
40
Min +85°C
30
–30
Max –40°C
20
10
–40
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
DS30453C-page 114
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
15.0 ELECTRICAL CHARACTERISTICS -
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
Absolute Maximum Ratings†
Ambient temperature under bias............................................................................................................–55°C to +125°C
Storage temperature............................................................................................................................. –65°C to +150°C
Voltage on VDD with respect to VSS ..................................................................................................................0 to +7.5V
Voltage on MCLR with respect to VSS ...............................................................................................................0 to +14V
Voltage on all other pins with respect to VSS ................................................................................. –0.6V to (VDD + 0.6V)
Total power dissipation(1) .....................................................................................................................................800 mW
Max. current out of VSS pin ...................................................................................................................................150 mA
Max. current into VDD pin......................................................................................................................................100 mA
Max. current into an input pin (T0CKI only) .....................................................................................................................±500 µA
Input clamp current, IIK (VI < 0 or VI > VDD).................................................................................................................... ±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. ±20 mA
Max. output current sunk by any I/O pin .................................................................................................................25 mA
Max. output current sourced by any I/O pin............................................................................................................20 mA
Max. output current sourced by a single I/O (Port A, B or C) .................................................................................50 mA
Max. output current sunk by a single I/O (Port A, B or C).......................................................................................50 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)
† NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indi-
cated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 115
PIC16C5X
FIGURE 15-1: PIC16C54C VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
FIGURE 15-2: PIC16C54C VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ +125°C
6.0
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS30453C-page 116
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
15.1
DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial)
PIC16C54C/C55A/C56A/C57C/C58B-04I, 20I (Industrial)
PIC16CR54B/CR/54C/CR56A/CR57C/CR58B-04I, 20I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Power Supply Pins
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
VDD
XT, RC, LP and HS options
HS option
3.0
4.5
—
—
5.5
5.5
V
V
HS Option from 0 - 10MHz
HS Option from 0 - 20MHz
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)(4)
—
—
—
—
1.8
2.6
4.5
14
2.4 mA FOSC = 4 MHz, VDD = 5.5V, XT mode
3.6 mA FOSC = 10 MHz, VDD = 3.0V, HS mode
16
32
mA FOSC = 20 MHz, VDD = 5.5V, HS mode
µA FOSC = 32 kHz, VDD = 3.0V, LP mode,
Commercial
—
17
40
µA FOSC = 32 kHz, VDD = 3.0V, LP mode,
Industrial
Power-down Current(5)
Watchdog Timer Current
IPD
—
—
—
—
0.25 4.0
0.25 5.0
µA VDD = 3.0V, WDT disabled, Commercial
µA VDD = 3.0V, WDT disabled, Industrial
µA VDD = 5.5V, WDT disabled, Commercial
µA VDD = 5.5V, WDT disabled, Industrial
1.8
2.0
7.0
8.0
∆IWDT
—
—
—
—
3.75 8.0
3.75 9.0
µA VDD = 3.0V, Commercial
µA VDD = 3.0V, Industrial
µA VDD = 5.5V*, Commercial
µA VDD = 5.5V*, Industrial
8
10
20
22
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 117
PIC16C5X
15.2
DC Characteristics: PIC16C54C/C55A/C56A/C57C/C58B-04E, 20E (Extended)
PIC16CR54C/CR56A/CR57C/CR58B-04E, 20E (Extended)
DC Characteristics
Power Supply Pins
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (extended)
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
VDD
XT, RC, LP and HS options
HS option
3.0
4.5
—
—
5.5
5.5
V
V
HS Option from 0 - 10MHz
HS Option from 0 - 20MHz
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)
XT and RC(4) options
HS option
—
—
1.8
9.0
3.3 mA FOSC = 4.0 MHz, VDD = 5.5V
20
mA FOSC = 20 MHz, VDD = 5.5V
Power-down Current(5)
IPD
—
—
—
0.3
10
12
17
50
60
µA VDD = 3.0V, WDT disabled
µA VDD = 4.5V, WDT disabled
µA VDD = 5.5V, WDT disabled
Watchdog Timer Current
∆IWDT
—
—
4.5
8
14
14
18
30
µA VDD = 3.0V
µA VDD = 4.5V*
µA VDD = 5.5V*
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
DS30453C-page 118
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
15.3
DC Characteristics: PIC16LC5X-04, PIC16LCR5X-04 (Commercial)
PIC16LC5X-04I, PIC16LCR5X-04I (Industrial)
Standard Operating Conditions (unless otherwise specified)
DC Characteristics
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
Power Supply Pins
Characteristic
Sym Min Typ(1) Max Units
Conditions
Supply Voltage
XT and RC options
LP options
VDD
3.0
2.5
—
—
5.5
5.5
V
V
RAM Data Retention Voltage(2) VDR
—
—
1.5*
VSS
—
—
V
V
Device in SLEEP mode
VDD start voltage to ensure
Power-on Reset
VPOR
SVDD
IDD
See Section 7.4 for details on
Power-on Reset
VDD rise rate to ensure
Power-on Reset
0.05*
—
—
V/ms See Section 7.4 for details on
Power-on Reset
Supply Current(3)(4)
—
—
—
0.4
0.5
11
0.6 mA FOSC = 4.0 MHz, VDD = 2.5V, XT mode
2.4 mA FOSC = 4.0 MHz, VDD = 5.5V, XT mode
27
µA FOSC = 32 kHz, VDD = 2.5V, LP mode,
Commercial
—
14
35
µA FOSC = 32 kHz, VDD = 2.5V, LP mode,
Industrial
Power-down Current(5)
Watchdog Timer Current
IPD
—
—
0.25
0.25
2
3
µA VDD = 2.5V, WDT disabled, Commercial
µA VDD = 2.5V, WDT disabled, Industrial
∆IWDT
—
—
0.8
1
3
5
µA VDD = 2.5V, Commercial
µA VDD = 2.5V, Industrial
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus
loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on
the current consumption.
a) The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to
VSS, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as specified.
b) For standby current measurements, the conditions are the same, except that
the device is in SLEEP mode.
4: Does not include current through REXT. The current through the resistor can be estimated by the
formula: IR = VDD/2REXT (mA) with REXT in kΩ.
5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 119
PIC16C5X
15.4
DC Characteristics: PIC16C54B/C54C/C55A/C56A/C57C/C58B-04, 20 (Commercial, Industrial,
Extended)
PIC16LC54B/LC54C/LC55A/LC56A/LC57C/LC58B-04 (Commercial, Industrial)
PIC16CR54C/CR56A/CR57C/CR58B-04, 20 (Commercial, Industrial, Extended)
PIC16LCR54B/LCR54C/LCR56A/LCR57C/LCR58B-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
DC Characteristics
All Pins Except
Power Supply Pins
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and
Section 15.3.
Characteristic
Sym
Min
Typ(1)
Max
Units
Conditions
Input Low Voltage
I/O Ports
I/O Ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
VIL
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
0.8 V
V
V
V
V
V
4.5V <VDD ≤ 5.5V
Otherwise
0.15 VDD
0.15 VDD
0.15 VDD
0.15 VDD
0.3 VDD
RC option only(4)
XT, HS and LP options
—
Input High Voltage
VIH
2.0
0.25 VDD+0.8V
0.85 VDD
0.85 VDD
0.85 VDD
0.7 VDD
—
—
—
—
—
—
VDD
VDD
VDD
VDD
VDD
VDD
V
V
V
V
V
V
4.5V < VDD ≤ 5.5V
Otherwise
I/O ports
MCLR (Schmitt Trigger)
T0CKI (Schmitt Trigger)
OSC1 (Schmitt Trigger)
OSC1
RC option only(4)
XT, HS and LP options
Hysteresis of Schmitt
Trigger inputs
VHYS
0.15VDD*
—
—
V
Input Leakage Current(3) IIL
For VDD ≤ 5.5V
I/O ports
-1.0
-5.0
0.5
+1.0
µA VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
MCLR
—
+5.0
+3.0
+3.0
—
µA VPIN = VSS +0.25V(2)
(2)
0.5
0.5
0.5
µA VPIN = VDD
T0CKI
OSC1
-3.0
-3.0
µA VSS ≤ VPIN ≤ VDD
µA VSS ≤ VPIN ≤ VDD,
XT, HS and LP options
Output Low Voltage
I/O ports
OSC2/CLKOUT
VOL
—
—
—
—
0.6
0.6
V
V
IOL = 8.7 mA, VDD = 4.5V
IOL = 1.6 mA, VDD = 4.5V,
RC option only
Output High Voltage
I/O ports(3)
OSC2/CLKOUT
VOH
VDD-0.7
VDD-0.7
—
—
—
—
V
V
IOH = -5.4 mA, VDD = 4.5V
IOH = -1.0 mA, VDD = 4.5V,
RC option only
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance
only and is not tested.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified lev-
els represent normal operating conditions. Higher leakage current may be measured at different input voltage.
3: Negative current is defined as coming out of the pin.
4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16C5X be
driven with external clock in RC mode.
DS30453C-page 120
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
15.5
Timing Parameter Symbology and Load Conditions
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
T
Time
2
to
mc
osc
os
MCLR
ck
cy
drt
io
CLKOUT
cycle time
device reset timer
I/O port
oscillator
OSC1
t0
T0CKI
wdt
watchdog timer
Uppercase letters and their meanings:
S
F
H
I
Fall
P
R
V
Z
Period
High
Rise
Invalid (Hi-impedance)
Low
Valid
L
Hi-impedance
FIGURE 15-3: LOAD CONDITIONS -
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B, PIC16CR5X
Pin
CL = 50 pF for all pins except OSC2
CL
15 pF for OSC2 in XT, HS or LP
options when external clock
is used to drive OSC1
VSS
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 121
PIC16C5X
15.6
Timing Diagrams and Specifications
FIGURE 15-4: EXTERNAL CLOCK TIMING - PIC16C5X, PIC16CR5X
Q4
Q3
Q4
4
Q1
Q1
Q2
OSC1
1
3
3
4
2
CLKOUT
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
FOSC
External CLKIN Frequency(2)
DC
DC
DC
DC
DC
DC
DC
DC
DC
250
250
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
4.0 MHz XT osc mode
4.0 MHz HS osc mode (04)
20 MHz HS osc mode (20)
200 kHz LP osc mode
4.0 MHz RC osc mode
4.0 MHz XT osc mode
4.0 MHz HS osc mode (04)
Oscillator Frequency(2)
20
MHz HS osc mode (20)
200 kHz LP osc mode
1
TOSC
External CLKIN Period(2)
—
—
—
—
—
ns XT osc mode
ns HS osc mode (04)
ns HS osc mode (20)
µs LP osc mode
5.0
250
250
250
50
Oscillator Period(2)
ns RC osc mode
2,200 ns XT osc mode
250
250
200
ns HS osc mode (04)
ns HS osc mode (20)
µs LP osc mode
5.0
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid-
ance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
DS30453C-page 122
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
TABLE 15-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X (CON’T)
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.
Parameter
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
2
3
TCY
Instruction Cycle Time(3)
—
50*
20*
2.0*
—
4/FOSC
—
—
—
—
TosL, TosH Clock in (OSC1) Low or High
Time
ns XT oscillator
ns HS oscillator
µs LP oscillator
ns XT oscillator
ns HS oscillator
ns LP oscillator
—
—
—
—
4
TosR, TosF Clock in (OSC1) Rise or Fall
Time
—
25*
25*
50*
—
—
—
—
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid-
ance only and are not tested.
2: All specified values are based on characterization data for that particular oscillator type under standard oper-
ating conditions with the device executing code. Exceeding these specified limits may result in an unstable
oscillator operation and/or higher than expected current consumption.
When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
3: Instruction cycle period (TCY) equals four times the input oscillator time base period.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 123
PIC16C5X
FIGURE 15-5: CLKOUT AND I/O TIMING - PIC16C5X, PIC16CR5X
Q1
Q2
Q3
Q4
OSC1
10
11
CLKOUT
13
12
18
14
19
16
I/O Pin
(input)
15
17
I/O Pin
(output)
New Value
Old Value
20, 21
Note: Refer to Figure 19-1 for load conditions.
TABLE 15-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16C5X, PIC16CR5X
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.
Parameter
No.
Sym
Characteristic
OSC1↑ to CLKOUT↓(2)
Min
Typ(1)
Max
Units
10
11
12
13
14
15
16
17
18
TosH2ckL
TosH2ckH
TckR
—
15
15
5.0
5.0
—
30**
30**
15**
15**
40**
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
OSC1↑ to CLKOUT↑(2)
—
CLKOUT rise time(2)
—
TckF
CLKOUT fall time(2)
—
TckL2ioV
TioV2ckH
TckH2ioI
TosH2ioV
TosH2ioI
CLKOUT↓ to Port out valid(2)
Port in valid before CLKOUT↑(2)
Port in hold after CLKOUT↑(2)
OSC1↑ (Q1 cycle) to Port out valid(3)
—
0.25 TCY+30*
—
0*
—
—
—
—
100*
—
OSC1↑ (Q2 cycle) to Port input invalid
TBD
—
(I/O in hold time)
19
TioV2osH
Port input valid to OSC1↑
TBD
—
—
ns
(I/O in setup time)
20
21
TioR
TioF
Port output rise time(3)
Port output fall time(3)
—
—
10
10
25**
25**
ns
ns
*
These parameters are characterized but not tested.
** These parameters are design targets and are not tested. No characterization data available at this time.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
2: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
3: See Figure 15-3 for loading conditions.
DS30453C-page 124
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
FIGURE 15-6: RESET, WATCHDOG TIMER, AND
DEVICE RESET TIMER TIMING - PIC16C5X, PIC16CR5X
VDD
MCLR
30
Internal
POR
32
32
32
DRT
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O pin
(Note 1)
Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.
TABLE 15-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16C5X, PIC16CR5X
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and Section 15.3.
Parameter
No.
Sym Characteristic
Min Typ(1) Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
1000*
9.0*
—
—
ns VDD = 5.0V
Twdt Watchdog Timer Time-out Period
(No Prescaler)
18*
30*
ms VDD = 5.0V (Commercial)
32
34
TDRT Device Reset Timer Period
9.0*
18*
30*
ms VDD = 5.0V (Commercial)
ns
TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000*
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guid-
ance only and are not tested.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 125
PIC16C5X
FIGURE 15-7: TIMER0 CLOCK TIMINGS - PIC16C5X, PIC16CR5X
T0CKI
40
41
42
TABLE 15-4: TIMER0 CLOCK REQUIREMENTS - PIC16C5X, PIC16CR5X
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature
0°C ≤ TA ≤ +70°C (commercial)
–40°C ≤ TA ≤ +85°C (industrial)
–40°C ≤ TA ≤ +125°C (extended)
Operating Voltage VDD range is described in Section 15.1, Section 15.2 and
Section 15.3.
Param
No.
Sym Characteristic
Min
Typ(1) Max Units Conditions
40
41
42
Tt0H T0CKI High Pulse Width- No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
Tt0L T0CKI Low Pulse Width - No Prescaler
- With Prescaler
0.5 TCY + 20*
10*
Tt0P T0CKI Period
20 or TCY + 40*
N
ns Whichever is greater.
N = Prescale Value
(1, 2, 4,..., 256)
*
These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
DS30453C-page 126
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
16.0 DC AND AC CHARACTERISTICS -
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables,
the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only
and devices will operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period of
time. “Typical” represents the mean of the distribution, while “max” or “min” represents (mean + 3σ) and (mean – 3σ)
respectively, where σ is standard deviation.
FIGURE 16-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
Frequency normalized to +25°C
FOSC (25°C)
1.10
REXT ≥ 10 kΩ
CEXT = 100 pF
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
VDD = 5.5 V
VDD = 3.5 V
0.92
0.90
0.88
0
10
20
25
30
40
50
60
70
T(°C)
TABLE 16-1: RC OSCILLATOR FREQUENCIES
Average
Fosc @ 5 V, 25°C
CEXT
REXT
20 pF
3.3 k
5 k
4.973 MHz
3.82 MHz
2.22 MHz
262.15 kHz
1.63 MHz
1.19 MHz
684.64 kHz
71.56 kHz
660 kHz
± 27%
± 21%
± 21%
± 31%
± 13%
± 13%
± 18%
± 25%
± 10%
± 14%
± 15%
± 19%
10 k
100 k
3.3 k
5 k
100 pF
300 pF
10 k
100 k
3.3 k
5.0 k
10 k
160 k
484.1 kHz
267.63 kHz
29.44 kHz
The frequencies are measured on DIP packages.
The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation
indicated is ±3 standard deviation from average value for VDD = 5 V.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 127
PIC16C5X
FIGURE 16-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF
6.00
R=3.3K
5.00
R=5.0K
4.00
3.00
R=10K
2.00
CEXT=20pF, T=25C
1.00
R=100K
0
2.5
3
3.5
5
5.5
6
4
4.5
VDD (Volts)
FIGURE 16-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 100 PF
1.80
R=3.3K
1.60
1.40
R=5.0K
1.00
R=10K
0.60
CEXT=20pF, T=25C
0.20
R=100K
0
2.5
3
3.5
5
5.5
4
4.5
VDD (Volts)
DS30453C-page 128
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
FIGURE 16-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF
700.0
R=3.3K
600.0
500.0
R=5.0K
400.0
300.0
R=10K
CEXT=20pF, T=25C
200.0
100.0
R=100K
0
2.5
3
3.5
5
5.5
6
4
4.5
VDD (Volts)
FIGURE 16-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)
25
20
15
10
5
0
2.5
3
3.5
5
5.5
6
4
4.5
VDD (Volts)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 129
PIC16C5X
FIGURE 16-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)
25
20
15
10
5
0
2.5
3
3.5
5
5.5
6
4
4.5
VDD (Volts)
FIGURE 16-7: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)
35
30
25
20
15
10
5
0
2.5
3
3.5
5
5.5
6
4
4.5
VDD (Volts)
DS30453C-page 130
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
FIGURE 16-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD
2.00
1.80
1.60
)
C
°
1.40
1.20
5
2
+
(
p
y
T
1.00
0.80
0.60
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 16-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD
4.5
)
4.0
C
°
5
8
+
o
t
C
°
0
4
–
(
3.5
3.0
2.5
2.0
1.5
x
a
H m
VI
)
C
°
5
8
+
o
t
C
°
0
4
–
(
n
i
H m
VI
L
I
IL
1.0
0.5
0.0
2.5
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
Note: These input pins have Schmitt Trigger input buffers.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 131
PIC16C5X
FIGURE 16-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT
(IN XT, HS AND LP MODES) vs. VDD
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
FIGURE 16-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25°C)
10000
1000
5.5V
100
4.5V
3.5V
2.5V
10
0.1
1
10
Freq(MHz)
DS30453C-page 132
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
FIGURE 16-12: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25°C)
10000
1000
5.5V
100
4.5V
3.5V
2.5V
10
0.01
0.1
1
10
Freq(MHz)
FIGURE 16-13: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25°C)
10000
1000
100
5.5V
4.5V
3.5V
2.5V
10
0.01
0.1
1
Freq(MHz)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 133
PIC16C5X
FIGURE 16-14: WDT TIMER TIME-OUT
PERIOD vs. VDD
TABLE 16-2: INPUT CAPACITANCE
Typical Capacitance (pF)
Pin
50
45
40
18L PDIP
5.0
18L SOIC
4.3
RA port
RB port
5.0
4.3
MCLR
17.0
4.0
17.0
3.5
OSC1
35
30
OSC2/CLKOUT
T0CKI
4.3
3.5
3.2
2.8
All capacitance values are typical at 25°C. A part-to-part
variation of ±25% (three standard deviations) should be
taken into account.
Typ +125°C
25
Typ +85°C
20
15
Typ +25°C
Typ –40°C
10
5
2
3
4
5
6
7
VDD (Volts)
DS30453C-page 134
Preliminary
2000 Microchip Technology Inc.
PIC16C54C/CR54C/C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B
FIGURE 16-15: IOH vs. VOH, VDD = 3 V
FIGURE 16-17: IOL vs. VOL, VDD = 3 V
0
45
Max –40°C
40
35
–5
Min +85°C
30
25
–10
Typ +25°C
Typ +25°C
Min +85°C
–15
20
Max –40°C
15
10
–20
5
0
–25
0
0.5 1.0 1.5 2.0 2.5 3.0
VOH (Volts)
0.0
0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
FIGURE 16-16: IOH vs. VOH, VDD = 5 V
FIGURE 16-18: IOL vs. VOL, VDD = 5 V
90
0
Max –40°C
80
70
–10
60
50
Typ +125°C
Typ +25°C
–20
Typ +85°C
40
Typ +25°C
Min +85°C
Typ –40°C
30
20
–30
–40
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOH (Volts)
0.0 0.5 1.0 1.5 2.0 2.5 3.0
VOL (Volts)
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 135
PIC16C5X
NOTES:
DS30453C-page 136
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
17.0 PACKAGING INFORMATION
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
α
n
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.155
.130
2.54
Top to Seating Plane
A
.140
.170
3.56
2.92
3.94
3.30
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.890
.125
.008
.045
.014
.310
5
.145
3.68
0.38
7.62
6.10
22.61
3.18
0.20
1.14
0.36
7.87
5
.313
.250
.898
.130
.012
.058
.018
.370
10
.325
.260
.905
.135
.015
.070
.022
.430
15
7.94
6.35
22.80
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 137
PIC16C5X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
L
A
c
B1
β
A1
eB
B
p
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
28
MAX
n
p
Number of Pins
Pitch
28
.100
.150
.130
2.54
3.81
3.30
Top to Seating Plane
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A
A2
A1
E
.140
.160
3.56
4.06
.125
.015
.300
.275
1.345
.125
.008
.040
.016
.320
.135
3.18
0.38
7.62
6.99
34.16
3.18
0.20
1.02
3.43
.310
.285
1.365
.130
.012
.053
.019
.350
10
.325
.295
1.385
.135
.015
.065
.022
.430
15
7.87
7.24
8.26
7.49
35.18
3.43
0.38
1.65
0.56
10.92
15
E1
D
34.67
3.30
Tip to Seating Plane
Lead Thickness
L
c
0.29
Upper Lead Width
B1
B
1.33
Lower Lead Width
0.41
8.13
5
0.48
8.89
10
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
5
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS30453C-page 138
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Dual In-line (P) – 600 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
B1
β
A1
p
B
eB
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.100
.175
.150
2.54
4.45
3.81
Top to Seating Plane
A
.160
.190
4.06
4.83
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.140
.015
.595
.505
1.395
.120
.008
.030
.014
.620
5
.160
3.56
0.38
15.11
12.83
35.43
3.05
0.20
0.76
0.36
15.75
5
4.06
.600
.545
1.430
.130
.012
.050
.018
.650
10
.625
.560
1.465
.135
.015
.070
.022
.680
15
15.24
13.84
36.32
3.30
0.29
1.27
0.46
16.51
10
15.88
14.22
37.21
3.43
0.38
1.78
0.56
17.27
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-011
Drawing No. C04-079
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 139
PIC16C5X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
1.27
Overall Height
A
.093
.104
2.36
2.24
2.50
2.31
0.20
10.34
7.49
11.53
0.50
0.84
4
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.291
.446
.010
.016
0
.094
.012
.420
.299
.462
.029
.050
8
§
0.10
10.01
7.39
11.33
0.25
0.41
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.012
.020
15
0.23
0.36
0
0.27
0.42
12
0.30
0.51
15
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
DS30453C-page 140
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
E1
p
D
B
2
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
1.27
2.50
2.31
0.20
10.34
7.49
17.87
0.50
0.84
4
Overall Height
A
.093
.104
2.36
2.64
Molded Package Thickness
Standoff
A2
A1
E
.088
.004
.394
.288
.695
.010
.016
0
.094
.012
.420
.299
.712
.029
.050
8
2.24
0.10
10.01
7.32
17.65
0.25
0.41
0
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
§
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle Top
c
Lead Thickness
Lead Width
.009
.014
0
.011
.017
12
.013
.020
15
0.23
0.36
0
0.28
0.42
12
0.33
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 141
PIC16C5X
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
20
MAX
n
p
Number of Pins
Pitch
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
0.65
Overall Height
A
.068
.078
1.73
1.63
1.85
1.73
0.15
7.85
5.25
7.20
0.75
0.18
101.60
0.32
5
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.278
.022
.004
0
.072
.010
.322
.212
.289
.037
.010
8
§
0.05
7.59
5.11
7.06
0.56
0.10
0.00
0.25
0
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS30453C-page 142
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
n
1
α
A
c
A2
A1
φ
L
β
Units
INCHES
NOM
MILLIMETERS*
NOM MAX
Dimension Limits
MIN
MAX
MIN
n
p
Number of Pins
Pitch
28
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
0.65
1.85
1.73
0.15
7.85
5.25
10.20
0.75
0.18
101.60
0.32
5
Overall Height
A
.068
.078
1.73
1.98
Molded Package Thickness
Standoff
A2
A1
E
.064
.002
.299
.201
.396
.022
.004
0
.072
.010
.319
.212
.407
.037
.010
8
1.63
0.05
7.59
5.11
10.06
0.56
0.10
0.00
0.25
0
1.83
0.25
8.10
5.38
10.34
0.94
0.25
203.20
0.38
10
§
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
c
Lead Thickness
Foot Angle
φ
Lead Width
B
α
β
.010
0
.013
5
.015
10
Mold Draft Angle Top
Mold Draft Angle Bottom
0
5
10
0
5
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 143
PIC16C5X
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
E1
D
W2
2
1
n
W1
E
A2
A
c
L
A1
B1
eB
p
B
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
18
MAX
n
p
Number of Pins
Pitch
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
2.54
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.195
4.32
3.94
4.64
4.06
0.57
7.94
7.37
22.86
3.49
0.25
1.40
0.47
9.78
3.56
5.08
4.95
A2
A1
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
0.38
7.62
7.24
22.35
3.18
0.20
1.27
0.41
8.76
3.30
4.83
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
Tip to Seating Plane
Lead Thickness
c
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Width
B1
B
§
eB
W1
W2
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-036
Drawing No. C04-010
DS30453C-page 144
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP)
E1
W
D
2
n
1
E
A2
A
L
c
B1
eB
A1
p
B
Units
INCHES*
NOM
MILLIMETERS
NOM
Dimension Limits
MIN
MAX
MIN
MAX
n
p
Number of Pins
Pitch
28
28
.100
.185
.160
.038
.600
.520
1.460
.138
.010
.058
.020
.660
.280
2.54
4.70
Top to Seating Plane
Ceramic Package Height
Standoff
A
.170
.200
.165
.060
.625
.526
1.490
.150
.012
.065
.023
.710
.290
4.32
5.08
A2
A1
.155
.015
.595
.514
1.430
.125
.008
.050
.016
.610
.270
3.94
0.38
4.06
4.19
1.52
0.95
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
E
E1
D
L
15.11
13.06
36.32
3.18
15.24
13.21
37.08
3.49
15.88
13.36
37.85
3.81
Tip to Seating Plane
Lead Thickness
c
0.20
0.25
0.30
Upper Lead Width
Lower Lead Width
Overall Row Spacing
Window Diameter
B1
B
1.27
1.46
1.65
0.41
0.51
0.58
§
eB
W
15.49
6.86
16.76
7.11
18.03
7.37
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-103
Drawing No. C04-013
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 145
PIC16C5X
17.1
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX
Example
PIC16C56A-
XXXXXXXXXXXXXXXXX
04I/P456
YYWWNNN
0023CBA
Example
Example
28-Lead Skinny PDIP (.300")
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16C55A-
04I/P456
YYWWNNN
0023CBA
28-Lead PDIP (.600")
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
XXXXXXXXXXXXXXX
YYWWNNN
PIC16C55A-
04/P126
0042CDA
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C54C-
04/S0218
YYWWNNN
0018CDK
28-Lead SOIC
Example
PIC16C57C-
04/SO
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
0015CBK
Example
20-Lead SSOP
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C54C
04/218
0020CBP
YYWWNNN
28-Lead SSOP
Example
PIC16C57C-
04/SS123
XXXXXXXXXXXX
XXXXXXXXXXXX
0025CBK
YYWWNNN
DS30453C-page 146
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
18-Lead CERDIP Windowed
Example
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
PIC16C54C
/JW
0001CBA
28-Lead CERDIP Windowed
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C57C
/JW
0038CBA
YYWWNNN
Legend: XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask
rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with
your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 147
PIC16C5X
NOTES:
DS30453C-page 148
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
APPENDIX A: COMPATIBILITY
To convert code written for PIC16CXX to PIC16C5X,
the user should take the following steps:
1. Check any CALL, GOTO or instructions that
modify the PC to determine if any program
memory page select operations (PA2, PA1, PA0
bits) need to be made.
2. Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
3. Eliminate any special function register page
switching. Redefine data variables to reallocate
them.
4. Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
5. Change Reset vector to proper value for
processor used.
6. Remove any use of the ADDLW and SUBLW
instructions.
7. Rewrite any code segments that use interrupts.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 149
PIC16C5X
NOTES:
DS30453C-page 150
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
F
INDEX
Family of Devices
A
PIC16C5X .................................................................... 6
FSR ................................................................................... 36
FSR Register ..................................................................... 22
Absolute Maximum Ratings ........................... 61, 81, 93, 115
ALU ...................................................................................... 9
Applications .......................................................................... 5
Architectural Overview ......................................................... 9
Assembler
H
High-Performance RISC CPU ............................................. 1
MPASM Assembler .................................................... 55
I
B
I/O Interfacing .................................................................... 25
I/O Ports ............................................................................ 25
I/O Programming Considerations ...................................... 26
ID Locations ................................................................. 31, 42
INDF .................................................................................. 36
INDF Register .................................................................... 22
Indirect Data Addressing ................................................... 22
Instruction Cycle ................................................................ 13
Instruction Flow/Pipelining ................................................. 13
Instruction Set Summary ................................................... 43
Block Diagram
On-Chip Reset Circuit ................................................ 36
PIC16C5X Series ....................................................... 10
Timer0 ........................................................................ 27
TMR0/WDT Prescaler ................................................ 30
Watchdog Timer ......................................................... 40
Brown-out Protection Circuit .............................................. 41
C
Carry bit ............................................................................... 9
Clocking Scheme ............................................................... 13
CMOS Technology ............................................................... 1
Code Protection ........................................................... 31, 42
Configuration Bits ............................................................... 31
Configuration Word ............................................................ 31
PIC16C54/C54A/C55/C56/C57 .................................. 32
PIC16CR54A/C54C/CR54C/C55A/C56A/
K
KeeLoq Evaluation and Programming Tools .................. 58
L
Loading of PC .............................................................. 21, 22
M
MCLR ................................................................................ 36
Memory Map ...................................................................... 15
PIC16C54/CR54/C55 ................................................ 15
PIC16C56/CR56 ........................................................ 15
PIC16C57/CR57/C58/CR58 ...................................... 15
Memory Organization ........................................................ 15
Data Memory ............................................................. 16
Program Memory ....................................................... 15
MPLAB Integrated Development Environment Software ... 55
CR56A/C57C/CR57C/C58B/CR58B .......................... 31
D
DC and AC Characteristics - PIC16C54/55/56/57 ............. 73
DC and AC Characteristics - PIC16C54A ........................ 105
DC and AC Characteristics - PIC16C54C/CR54C/
C55A/C56A/CR56A/C57C/CR57C/C58B/CR58B ............ 127
DC Characteristics ............................................... 82, 94, 117
PIC16C54/55/56/57 ........................... 62, 63, 64, 65, 66
PIC16C54A ................................................................ 94
PIC16CR54A ............................................................. 82
Development Support ........................................................ 55
Device Varieties ................................................................... 7
Digit Carry bit ....................................................................... 9
O
One-Time-Programmable (OTP) Devices ........................... 7
OPTION ............................................................................. 36
OPTION Register ............................................................... 20
OSC selection .................................................................... 31
Oscillator Configurations .................................................... 33
Oscillator Types
E
Electrical Characteristics
HS .............................................................................. 33
LP .............................................................................. 33
RC ............................................................................. 33
XT .............................................................................. 33
PIC16C54/55/56/57 ................................................... 61
PIC16C54A ................................................................ 93
PIC16C54C/CR54C/C55A/C56A/CR56A/
C57C/CR57C/C58B/CR58B .................................... 115
PIC16CR54A ............................................................. 81
Errata ................................................................................... 4
External Power-on Reset Circuit ........................................ 37
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 151
PIC16C5X
P
S
Package Marking Information ..........................................146
Packaging Information .....................................................137
PC ......................................................................................21
PCL ....................................................................................36
Peripheral Features ..............................................................1
PIC16C54/55/56/57 Product Identification System ..........156
PIC16C5X Product Identification System .........................155
PICDEM-1 Low-Cost PICmicro Demo Board .....................57
PICDEM-2 Low-Cost PIC16CXX Demo Board ..................57
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................57
PICSTART Plus Entry Level Development System ........57
Pin Configurations ................................................................2
Pinout Description - PIC16C54s,
PIC16CR54, PIC16C56, PIC16CR56,
PIC16C58, PIC16CR58 .....................................................11
Pinout Description - PIC16C55, PIC16C57,
PIC16CR57 ........................................................................12
POR
Device Reset Timer (DRT) ................................... 31, 39
PD ........................................................................ 35, 41
Power-on Reset (POR) .................................. 31, 36, 37
TO ........................................................................ 35, 41
PORTA ......................................................................... 25, 36
PORTB ......................................................................... 25, 36
PORTC ......................................................................... 25, 36
Power-down Mode (SLEEP) ..............................................42
Prescaler ............................................................................30
PRO MATE II Universal Programmer ..............................57
Program Counter ................................................................21
Serialized Quick-Turnaround-Production (SQTP)
Devices ................................................................................ 7
SLEEP ......................................................................... 31, 42
Software Simulator (MPLAB-SIM) ..................................... 56
Special Features of the CPU ............................................. 31
Special Function Registers ................................................ 18
Stack .................................................................................. 22
STATUS ............................................................................. 36
STATUS Register .......................................................... 9, 19
T
Timer0
Switching Prescaler Assignment ............................... 30
Timer0 (TMR0) Module .............................................. 27
TMR0 with External Clock ......................................... 29
Timing Diagrams and Specifications ............. 68, 88, 99, 122
Timing Parameter Symbology and
Load Conditions ............................................. 67, 87, 98, 121
TMR0 ................................................................................. 36
TRIS ................................................................................... 36
TRIS Registers .................................................................. 25
U
UV Erasable Devices ........................................................... 7
W
W Register ......................................................................... 36
Wake-up from SLEEP ........................................................ 42
Watchdog Timer (WDT) ............................................... 31, 39
Period ........................................................................ 39
Programming Considerations .................................... 39
WWW, On-Line Support ...................................................... 4
Q
Q cycles .............................................................................13
Quick-Turnaround-Production (QTP) Devices .....................7
Z
R
Zero bit ................................................................................. 9
RC Oscillator ......................................................................34
Read Only Memory (ROM) Devices .....................................7
Read-Modify-Write .............................................................26
Register File Map
PIC16C54, PIC16CR54, PIC16C55,
PIC16C56, PIC16CR56 .............................................16
PIC16C57/CR57 ........................................................17
PIC16C58/CR58 ........................................................17
Registers
Special Function ........................................................18
RESET ...............................................................................35
Reset ..................................................................................31
RESET on Brown-out .........................................................41
DS30453C-page 152
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
Systems Information and Upgrade Hot Line
ON-LINE SUPPORT
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip’s development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
Microchip provides on-line support on the Microchip
World Wide Web (WWW) site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape or Microsoft
Explorer. Files are also available for FTP download
from our FTP site.
1-800-755-2345 for U.S. and most of Canada, and
1-480-786-7302 for the rest of the world.
991103
ConnectingtotheMicrochipInternetWebSite
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User’s Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
Trademarks: The Microchip name, logo, PIC, PICmicro,
PICSTART, PICMASTER, PRO MATE and MPLAB are
registered trademarks of Microchip Technology Incorpo-
rated in the U.S.A. and other countries. FlexROM and
fuzzyLAB are trademarks and SQTP is a service mark of
Microchip in the U.S.A.
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
All other trademarks mentioned herein are the property of
their respective companies.
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Sys-
tems, technical information and more
• Listing of seminars and events
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 153
PIC16C5X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
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RE:
From:
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Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Literature Number:
DS30453C
Device:
PIC16C5X
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30453C-page 154
Preliminary
1998 Microchip Technology Inc.
PIC16C5X
PIC16C5X PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
XXX
Examples:
Temperature Package
Range
Pattern
a) PIC16C54A -04/P 301 = Commercial
temp., PDIP package, 4MHz, normal VDD
limitis, QTP pattern #301.
(2)
(2)
(3)
Device
PIC16C5X , PIC16C5XT
b) PIC16LC58A - 04I/SO = Industrial temp.,
SOIC package, 4MHz, Extended VDD
limits.
(3)
PIC16LC5X , PIC16LC5XT
(2)
(3)
PIC16CR5X , PIC16CR5XT
(2)
(3)
PIC16LCR5X , PIC16LCR5XT
(2)
(3)
c) PIC16CR54A - 10I/P355 = ROM program
memory, Industrial temp., PDIP package,
10MHz, normal VDD limits.
PIC16LV5X , PIC16LV5XT
(1)
Temperature
Range
b
I
=
0°C to +70°C (Commercial)
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Automotive)
E
Note 1: b = blank
Package
JW
P
SO
SP
SS
= Windowed CERDIP
= PDIP
= SOIC (Gull Wing, 300 mil body)
= Skinny PDIP (28-pin, 300 mil body)
= SSOP (209 mil body)
2:
C
= Standard VDD range
LC = Extended VDD range
CR = ROM Version, Standard VDD
range
LCR = ROM Version, Extended VDD
range
Pattern
3-digit Pattern Code for QTP, ROM (blank otherwise)
LV = Low Voltage VDD range
3: T = in tape and reel - SOIC, SSOP
packages only.
4: UV erasable devices are tested to all
available voltage/frequency options.
Erased devices are oscillator type 04.
The user can select 04, 10 or 20 oscil-
lators by programmng the appropriate
configuration bits.
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 155
PIC16C5X
PIC16C54/55/56/57 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.
X
/XX
XXX
PART NO.
Device
-XX
Oscillator Temperature Package
Type Range
Pattern
Examples:
a) PIC16C54 - XT/PXXX = "XT" oscillator,
commercial temp., PDIP, QTP pattern.
(2)
(2)
(2)
(2)
Device
PIC16C54, PIC16C54T
PIC16C55, PIC16C55T
PIC16C56, PIC16C56T
PIC16C57, PIC16C57T
b) PIC16C55 - XTI/SO = "XT" oscillator,
industrial temp., SOIC (OTP device)
c) PIC16C55 /JW
= Commercial temp.
CERDIP with window.
Oscillator Type
RC
LP
XT
HS
10
= Resistor Capacitor
= Low Power Crystal
= Standard Crystal/Resonator
= High Speed Crystal
= 10 MHz Crystal
d) PIC16C57 - RC/S = "RC" oscillator, com-
mercial temp., dice in waffle pack.
(1)
(3)
b
= No type for JW devices
Note 1: b = blank
(1)
Temperature
Range
b
I
=
0°C to +70°C (Commercial)
2: T = in tape and reel - SOIC, SSOP
packages only.
= -40°C to +85°C (Industrial)
= -40°C to +125°C (Automotive)
E
3: UV erasable devices are tested to all
available voltage/frequency options.
Erased devices are oscillator type RC.
The user can select RC, LP, XT or HS
oscillators by programming the appro-
priate configuration bits.
Package
JW
P
S
SO
SP
SS
= Windowed CERDIP
= PDIP
= Die in Waffle Pack
= SOIC (Gull Wing, 300 mil body)
= Skinny PDIP (28 pin, 300 mil body)
= SSOP (209 mil body)
Pattern
3-digit Pattern Code for QTP (blank otherwise)
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
DS30453C-page 156
Preliminary
2000 Microchip Technology Inc.
PIC16C5X
NOTES:
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 157
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
ASIA/PACIFIC (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Microchip Technology Inc.
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Tel: 65-334-8870 Fax: 65-334-8850
ASIA/PACIFIC
China - Beijing
Taiwan
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Atlanta
Microchip Technology, Beijing
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing, 100027, P.R.C.
Tel: 770-640-0034 Fax: 770-640-0307
Boston
EUROPE
Tel: 86-10-85282100 Fax: 86-10-85282104
Microchip Technology Inc.
2 LAN Drive, Suite 120
Westford, MA 01886
China - Shanghai
Denmark
Microchip Technology
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Unit B701, Far East International Plaza,
No. 317, Xianxia Road
Tel: 508-480-9990 Fax: 508-480-8575
Shanghai, 200051, P.R.C.
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Chicago
Microchip Technology Inc.
333 Pierce Road, Suite 180
Itasca, IL 60143
Hong Kong
Microchip Asia Pacific
Unit 2101, Tower 2
France
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Tel: 972-818-7423 Fax: 972-818-2924
India
Germany
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore, 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Italy
Japan
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Los Angeles
Korea
Microchip Technology Inc.
18201 Von Karman, Suite 1090
Irvine, CA 92612
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 949-263-1888 Fax: 949-263-1338
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
New York
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Microchip Technology Inc.
150 Motor Parkway, Suite 202
Hauppauge, NY 11788
05/16/00
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 7/00
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates.
It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights
arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property
rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.
DS30453C-page 158
Preliminary
2000 Microchip Technology Inc.
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